]> git.ipfire.org Git - thirdparty/pciutils.git/blob - ls-ecaps.c
Decoding of the Root Complex Link capability
[thirdparty/pciutils.git] / ls-ecaps.c
1 /*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11
12 #include "lspci.h"
13
14 static void
15 cap_dsn(struct device *d, int where)
16 {
17 u32 t1, t2;
18 if (!config_fetch(d, where + 4, 8))
19 return;
20 t1 = get_conf_long(d, where + 4);
21 t2 = get_conf_long(d, where + 8);
22 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
23 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
24 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
25 }
26
27 static void
28 cap_aer(struct device *d, int where)
29 {
30 u32 l;
31
32 printf("Advanced Error Reporting\n");
33 if (verbose < 2)
34 return;
35
36 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
37 return;
38
39 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
40 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
41 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
42 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
43 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
44 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
45 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
46 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
47 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
48 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
49 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
50 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
51 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
52 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
53 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
54 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
55 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
56 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
57 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
58 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
59 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
60 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
61 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
62 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
63 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
64 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
65 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
66 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
67 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
68 l = get_conf_long(d, where + PCI_ERR_CAP);
69 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
70 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
71 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
72
73 }
74
75 static void
76 cap_acs(struct device *d, int where)
77 {
78 u16 w;
79
80 printf("Access Control Services\n");
81 if (verbose < 2)
82 return;
83
84 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
85 return;
86
87 w = get_conf_word(d, where + PCI_ACS_CAP);
88 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
89 "DirectTrans%c\n",
90 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
91 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
92 FLAG(w, PCI_ACS_CAP_TRANS));
93 w = get_conf_word(d, where + PCI_ACS_CTRL);
94 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
95 "DirectTrans%c\n",
96 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
97 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
98 FLAG(w, PCI_ACS_CTRL_TRANS));
99 }
100
101 static void
102 cap_ari(struct device *d, int where)
103 {
104 u16 w;
105
106 printf("Alternative Routing-ID Interpretation (ARI)\n");
107 if (verbose < 2)
108 return;
109
110 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
111 return;
112
113 w = get_conf_word(d, where + PCI_ARI_CAP);
114 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
115 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
116 PCI_ARI_CAP_NFN(w));
117 w = get_conf_word(d, where + PCI_ARI_CTRL);
118 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
119 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
120 PCI_ARI_CTRL_FG(w));
121 }
122
123 static void
124 cap_ats(struct device *d, int where)
125 {
126 u16 w;
127
128 printf("Address Translation Service (ATS)\n");
129 if (verbose < 2)
130 return;
131
132 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
133 return;
134
135 w = get_conf_word(d, where + PCI_ATS_CAP);
136 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
137 w = get_conf_word(d, where + PCI_ATS_CTRL);
138 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
139 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
140 }
141
142 static void
143 cap_sriov(struct device *d, int where)
144 {
145 u16 b;
146 u16 w;
147 u32 l;
148 int i;
149
150 printf("Single Root I/O Virtualization (SR-IOV)\n");
151 if (verbose < 2)
152 return;
153
154 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
155 return;
156
157 l = get_conf_long(d, where + PCI_IOV_CAP);
158 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
159 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
160 w = get_conf_word(d, where + PCI_IOV_CTRL);
161 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
162 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
163 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
164 FLAG(w, PCI_IOV_CTRL_ARI));
165 w = get_conf_word(d, where + PCI_IOV_STATUS);
166 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
167 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
168 printf("\t\tInitial VFs: %d, ", w);
169 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
170 printf("Total VFs: %d, ", w);
171 w = get_conf_word(d, where + PCI_IOV_NUMVF);
172 printf("Number of VFs: %d, ", w);
173 b = get_conf_byte(d, where + PCI_IOV_FDL);
174 printf("Function Dependency Link: %02x\n", b);
175 w = get_conf_word(d, where + PCI_IOV_OFFSET);
176 printf("\t\tVF offset: %d, ", w);
177 w = get_conf_word(d, where + PCI_IOV_STRIDE);
178 printf("stride: %d, ", w);
179 w = get_conf_word(d, where + PCI_IOV_DID);
180 printf("Device ID: %04x\n", w);
181 l = get_conf_long(d, where + PCI_IOV_SUPPS);
182 printf("\t\tSupported Page Size: %08x, ", l);
183 l = get_conf_long(d, where + PCI_IOV_SYSPS);
184 printf("System Page Size: %08x\n", l);
185
186 for (i=0; i < PCI_IOV_NUM_BAR; i++)
187 {
188 u32 addr;
189 int type;
190 u32 h;
191 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
192 if (l == 0xffffffff)
193 l = 0;
194 if (!l)
195 continue;
196 printf("\t\tRegion %d: Memory at ", i);
197 addr = l & PCI_ADDR_MEM_MASK;
198 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
199 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
200 {
201 i++;
202 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
203 printf("%08x", h);
204 }
205 printf("%08x (%s-bit, %sprefetchable)\n",
206 addr,
207 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
208 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
209 }
210
211 l = get_conf_long(d, where + PCI_IOV_MSAO);
212 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
213 PCI_IOV_MSA_BIR(l));
214 }
215
216 static void
217 cap_vc(struct device *d, int where)
218 {
219 u32 cr1, cr2;
220 u16 ctrl, status;
221 int evc_cnt;
222 int arb_table_pos;
223 int i, j;
224 static const char ref_clocks[4][6] = { "100ns", "?1", "?2", "?3" };
225 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "?4", "?5", "?6", "?7" };
226 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "?6", "?7" };
227
228 printf("Virtual Channel\n");
229 if (verbose < 2)
230 return;
231
232 if (!config_fetch(d, where + 4, 0x1c - 4))
233 return;
234
235 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
236 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
237 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
238 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
239
240 evc_cnt = cr1 & 7;
241 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntrySize=%d\n",
242 (cr1 >> 4) & 7,
243 ref_clocks[(cr1 >> 8) & 3],
244 (cr1 >> 10) & 3);
245
246 printf("\t\tArb:\t");
247 for (i=0; i<8; i++)
248 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
249 printf("%s%c ", arb_selects[i], FLAG(cr2, 1 << i));
250 arb_table_pos = (cr2 >> 24) & 0xff;
251 printf("TableOffset=%x\n", arb_table_pos);
252
253 printf("\t\tCtrl:\tArbSelect=%s\n", arb_selects[(ctrl >> 1) & 7]);
254 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
255
256 if (arb_table_pos)
257 printf("\t\tPort Arbitration Table <?>\n");
258
259 for (i=0; i<=evc_cnt; i++)
260 {
261 int pos = where + PCI_VC_RES_CAP + 12*i;
262 u32 rcap, rctrl;
263 u16 rstatus;
264 int pat_pos;
265
266 printf("\t\tVC%d:\t", i);
267 if (!config_fetch(d, pos, 12))
268 {
269 printf("<unreadable>\n");
270 continue;
271 }
272 rcap = get_conf_long(d, pos);
273 rctrl = get_conf_long(d, pos+4);
274 rstatus = get_conf_word(d, pos+8);
275
276 pat_pos = (rcap >> 24) & 0xff;
277 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
278 pat_pos,
279 ((rcap >> 16) & 0x3f) + 1,
280 FLAG(rcap, 1 << 15));
281
282 printf("\t\t\tArb:");
283 for (j=0; j<8; j++)
284 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
285 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
286
287 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
288 FLAG(rctrl, 1 << 31),
289 (rctrl >> 24) & 7,
290 vc_arb_selects[(rctrl >> 17) & 7],
291 rctrl & 0xff);
292
293 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
294 FLAG(rstatus, 2),
295 FLAG(rstatus, 1));
296
297 if (pat_pos)
298 printf("\t\t\tPort Arbitration Table <?>\n");
299 }
300 }
301
302 static void
303 cap_rclink(struct device *d, int where)
304 {
305 u32 esd;
306 int num_links;
307 int i;
308 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
309 char buf[8];
310
311 printf("Root Complex Link\n");
312 if (verbose < 2)
313 return;
314
315 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
316 return;
317
318 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
319 num_links = BITS(esd, 8, 8);
320 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
321 BITS(esd, 24, 8),
322 BITS(esd, 16, 8),
323 TABLE(elt_types, BITS(esd, 0, 8), buf));
324
325 for (i=0; i<num_links; i++)
326 {
327 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
328 u32 desc;
329 u32 addr_lo, addr_hi;
330
331 printf("\t\tLink%d:\t", i);
332 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
333 {
334 printf("<unreadable>\n");
335 return;
336 }
337 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
338 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
339 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
340
341 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
342 BITS(desc, 24, 8),
343 BITS(desc, 16, 8),
344 FLAG(desc, 4),
345 ((desc & 2) ? "Config" : "MemMapped"),
346 FLAG(desc, 1));
347
348 if (desc & 2)
349 {
350 int n = addr_lo & 7;
351 if (!n)
352 n = 8;
353 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
354 BITS(addr_lo, 20, n),
355 BITS(addr_lo, 15, 5),
356 BITS(addr_lo, 12, 3),
357 addr_hi, addr_lo);
358 }
359 else
360 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
361 }
362 }
363
364 void
365 show_ext_caps(struct device *d)
366 {
367 int where = 0x100;
368 char been_there[0x1000];
369 memset(been_there, 0, 0x1000);
370 do
371 {
372 u32 header;
373 int id, version;
374
375 if (!config_fetch(d, where, 4))
376 break;
377 header = get_conf_long(d, where);
378 if (!header)
379 break;
380 id = header & 0xffff;
381 version = (header >> 16) & 0xf;
382 printf("\tCapabilities: [%03x", where);
383 if (verbose > 1)
384 printf(" v%d", version);
385 printf("] ");
386 if (been_there[where]++)
387 {
388 printf("<chain looped>\n");
389 break;
390 }
391 switch (id)
392 {
393 case PCI_EXT_CAP_ID_AER:
394 cap_aer(d, where);
395 break;
396 case PCI_EXT_CAP_ID_VC:
397 case PCI_EXT_CAP_ID_VC2:
398 cap_vc(d, where);
399 break;
400 case PCI_EXT_CAP_ID_DSN:
401 cap_dsn(d, where);
402 break;
403 case PCI_EXT_CAP_ID_PB:
404 printf("Power Budgeting <?>\n");
405 break;
406 case PCI_EXT_CAP_ID_RCLINK:
407 cap_rclink(d, where);
408 break;
409 case PCI_EXT_CAP_ID_RCILINK:
410 printf("Root Complex Internal Link <?>\n");
411 break;
412 case PCI_EXT_CAP_ID_RCECOLL:
413 printf("Root Complex Event Collector <?>\n");
414 break;
415 case PCI_EXT_CAP_ID_MFVC:
416 printf("Multi-Function Virtual Channel <?>\n");
417 break;
418 case PCI_EXT_CAP_ID_RBCB:
419 printf("Root Bridge Control Block <?>\n");
420 break;
421 case PCI_EXT_CAP_ID_VNDR:
422 printf("Vendor Specific Information <?>\n");
423 break;
424 case PCI_EXT_CAP_ID_ACS:
425 cap_acs(d, where);
426 break;
427 case PCI_EXT_CAP_ID_ARI:
428 cap_ari(d, where);
429 break;
430 case PCI_EXT_CAP_ID_ATS:
431 cap_ats(d, where);
432 break;
433 case PCI_EXT_CAP_ID_SRIOV:
434 cap_sriov(d, where);
435 break;
436 default:
437 printf("#%02x\n", id);
438 break;
439 }
440 where = (header >> 20) & ~3;
441 } while (where);
442 }