ls-ecaps.c

   1 /*
   2  *      The PCI Utilities -- Show Extended Capabilities
   3  *
   4  *      Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_tph(struct device *d, int where)
  16 {
  17   u32 tph_cap;
  18   printf("Transaction Processing Hints\n");
  19   if (verbose < 2)
  20     return;
  21
  22   if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
  23     return;
  24
  25   tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
  26
  27   if (tph_cap & PCI_TPH_INTVEC_SUP)
  28     printf("\t\tInterrupt vector mode supported\n");
  29   if (tph_cap & PCI_TPH_DEV_SUP)
  30     printf("\t\tDevice specific mode supported\n");
  31   if (tph_cap & PCI_TPH_EXT_REQ_SUP)
  32     printf("\t\tExtended requester support\n");
  33
  34   switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
  35   case PCI_TPH_ST_NONE:
  36     printf("\t\tNo steering table available\n");
  37     break;
  38   case PCI_TPH_ST_CAP:
  39     printf("\t\tSteering table in TPH capability structure\n");
  40     break;
  41   case PCI_TPH_ST_MSIX:
  42     printf("\t\tSteering table in MSI-X table\n");
  43     break;
  44   default:
  45     printf("\t\tReserved steering table location\n");
  46     break;
  47   }
  48 }
  49
  50 static u32
  51 cap_ltr_scale(u8 scale)
  52 {
  53   return 1 << (scale * 5);
  54 }
  55
  56 static void
  57 cap_ltr(struct device *d, int where)
  58 {
  59   u32 scale;
  60   u16 snoop, nosnoop;
  61   printf("Latency Tolerance Reporting\n");
  62   if (verbose < 2)
  63     return;
  64
  65   if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
  66     return;
  67
  68   snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
  69   scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  70   printf("\t\tMax snoop latency: %lldns\n",
  71          ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
  72
  73   nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
  74   scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  75   printf("\t\tMax no snoop latency: %lldns\n",
  76          ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
  77 }
  78
  79 static void
  80 cap_dsn(struct device *d, int where)
  81 {
  82   u32 t1, t2;
  83   if (!config_fetch(d, where + 4, 8))
  84     return;
  85   t1 = get_conf_long(d, where + 4);
  86   t2 = get_conf_long(d, where + 8);
  87   printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
  88         t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
  89         t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
  90 }
  91
  92 static void
  93 cap_aer(struct device *d, int where)
  94 {
  95   u32 l, l0, l1, l2, l3;
  96
  97   printf("Advanced Error Reporting\n");
  98   if (verbose < 2)
  99     return;
 100
 101   if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
 102     return;
 103
 104   l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
 105   printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 106         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 107         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 108         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 109         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 110         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 111   l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
 112   printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 113         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 114         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 115         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 116         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 117         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 118   l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
 119   printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 120         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 121         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 122         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 123         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 124         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 125   l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
 126   printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
 127         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 128         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 129   l = get_conf_long(d, where + PCI_ERR_COR_MASK);
 130   printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
 131         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 132         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 133   l = get_conf_long(d, where + PCI_ERR_CAP);
 134   printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n"
 135         "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
 136         PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
 137         FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
 138         FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
 139         FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
 140
 141   l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
 142   l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
 143   l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
 144   l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
 145   printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
 146 }
 147
 148 static void cap_dpc(struct device *d, int where)
 149 {
 150   u16 l;
 151
 152   printf("Downstream Port Containment\n");
 153   if (verbose < 2)
 154     return;
 155
 156   if (!config_fetch(d, where + PCI_DPC_CAP, 8))
 157     return;
 158
 159   l = get_conf_word(d, where + PCI_DPC_CAP);
 160   printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 161     PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
 162     FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
 163
 164   l = get_conf_word(d, where + PCI_DPC_CTL);
 165   printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
 166     PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
 167     FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
 168     FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
 169
 170   l = get_conf_word(d, where + PCI_DPC_STATUS);
 171   printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
 172     FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
 173     FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
 174
 175   l = get_conf_word(d, where + PCI_DPC_SOURCE);
 176   printf("\t\tSource:\t%04x\n", l);
 177 }
 178
 179 static void
 180 cap_acs(struct device *d, int where)
 181 {
 182   u16 w;
 183
 184   printf("Access Control Services\n");
 185   if (verbose < 2)
 186     return;
 187
 188   if (!config_fetch(d, where + PCI_ACS_CAP, 4))
 189     return;
 190
 191   w = get_conf_word(d, where + PCI_ACS_CAP);
 192   printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 193         "DirectTrans%c\n",
 194         FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
 195         FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
 196         FLAG(w, PCI_ACS_CAP_TRANS));
 197   w = get_conf_word(d, where + PCI_ACS_CTRL);
 198   printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 199         "DirectTrans%c\n",
 200         FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
 201         FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
 202         FLAG(w, PCI_ACS_CTRL_TRANS));
 203 }
 204
 205 static void
 206 cap_ari(struct device *d, int where)
 207 {
 208   u16 w;
 209
 210   printf("Alternative Routing-ID Interpretation (ARI)\n");
 211   if (verbose < 2)
 212     return;
 213
 214   if (!config_fetch(d, where + PCI_ARI_CAP, 4))
 215     return;
 216
 217   w = get_conf_word(d, where + PCI_ARI_CAP);
 218   printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
 219         FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
 220         PCI_ARI_CAP_NFN(w));
 221   w = get_conf_word(d, where + PCI_ARI_CTRL);
 222   printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
 223         FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
 224         PCI_ARI_CTRL_FG(w));
 225 }
 226
 227 static void
 228 cap_ats(struct device *d, int where)
 229 {
 230   u16 w;
 231
 232   printf("Address Translation Service (ATS)\n");
 233   if (verbose < 2)
 234     return;
 235
 236   if (!config_fetch(d, where + PCI_ATS_CAP, 4))
 237     return;
 238
 239   w = get_conf_word(d, where + PCI_ATS_CAP);
 240   printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
 241   w = get_conf_word(d, where + PCI_ATS_CTRL);
 242   printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
 243         FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
 244 }
 245
 246 static void
 247 cap_pri(struct device *d, int where)
 248 {
 249   u16 w;
 250   u32 l;
 251
 252   printf("Page Request Interface (PRI)\n");
 253   if (verbose < 2)
 254     return;
 255
 256   if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
 257     return;
 258
 259   w = get_conf_word(d, where + PCI_PRI_CTRL);
 260   printf("\t\tPRICtl: Enable%c Reset%c\n",
 261         FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
 262   w = get_conf_word(d, where + PCI_PRI_STATUS);
 263   printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
 264         FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
 265         FLAG(w, PCI_PRI_STATUS_STOPPED));
 266   l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
 267   printf("\t\tPage Request Capacity: %08x, ", l);
 268   l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
 269   printf("Page Request Allocation: %08x\n", l);
 270 }
 271
 272 static void
 273 cap_pasid(struct device *d, int where)
 274 {
 275   u16 w;
 276
 277   printf("Process Address Space ID (PASID)\n");
 278   if (verbose < 2)
 279     return;
 280
 281   if (!config_fetch(d, where + PCI_PASID_CAP, 4))
 282     return;
 283
 284   w = get_conf_word(d, where + PCI_PASID_CAP);
 285   printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
 286         FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
 287         PCI_PASID_CAP_WIDTH(w));
 288   w = get_conf_word(d, where + PCI_PASID_CTRL);
 289   printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
 290         FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
 291         FLAG(w, PCI_PASID_CTRL_PRIV));
 292 }
 293
 294 static void
 295 cap_sriov(struct device *d, int where)
 296 {
 297   u16 b;
 298   u16 w;
 299   u32 l;
 300   int i;
 301
 302   printf("Single Root I/O Virtualization (SR-IOV)\n");
 303   if (verbose < 2)
 304     return;
 305
 306   if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
 307     return;
 308
 309   l = get_conf_long(d, where + PCI_IOV_CAP);
 310   printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
 311         FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
 312   w = get_conf_word(d, where + PCI_IOV_CTRL);
 313   printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
 314         FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
 315         FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
 316         FLAG(w, PCI_IOV_CTRL_ARI));
 317   w = get_conf_word(d, where + PCI_IOV_STATUS);
 318   printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
 319   w = get_conf_word(d, where + PCI_IOV_INITIALVF);
 320   printf("\t\tInitial VFs: %d, ", w);
 321   w = get_conf_word(d, where + PCI_IOV_TOTALVF);
 322   printf("Total VFs: %d, ", w);
 323   w = get_conf_word(d, where + PCI_IOV_NUMVF);
 324   printf("Number of VFs: %d, ", w);
 325   b = get_conf_byte(d, where + PCI_IOV_FDL);
 326   printf("Function Dependency Link: %02x\n", b);
 327   w = get_conf_word(d, where + PCI_IOV_OFFSET);
 328   printf("\t\tVF offset: %d, ", w);
 329   w = get_conf_word(d, where + PCI_IOV_STRIDE);
 330   printf("stride: %d, ", w);
 331   w = get_conf_word(d, where + PCI_IOV_DID);
 332   printf("Device ID: %04x\n", w);
 333   l = get_conf_long(d, where + PCI_IOV_SUPPS);
 334   printf("\t\tSupported Page Size: %08x, ", l);
 335   l = get_conf_long(d, where + PCI_IOV_SYSPS);
 336   printf("System Page Size: %08x\n", l);
 337
 338   for (i=0; i < PCI_IOV_NUM_BAR; i++)
 339     {
 340       u32 addr;
 341       int type;
 342       u32 h;
 343       l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
 344       if (l == 0xffffffff)
 345         l = 0;
 346       if (!l)
 347         continue;
 348       printf("\t\tRegion %d: Memory at ", i);
 349       addr = l & PCI_ADDR_MEM_MASK;
 350       type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 351       if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
 352         {
 353           i++;
 354           h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
 355           printf("%08x", h);
 356         }
 357       printf("%08x (%s-bit, %sprefetchable)\n",
 358         addr,
 359         (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
 360         (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
 361     }
 362
 363   l = get_conf_long(d, where + PCI_IOV_MSAO);
 364   printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
 365         PCI_IOV_MSA_BIR(l));
 366 }
 367
 368 static void
 369 cap_vc(struct device *d, int where)
 370 {
 371   u32 cr1, cr2;
 372   u16 ctrl, status;
 373   int evc_cnt;
 374   int arb_table_pos;
 375   int i, j;
 376   static const char ref_clocks[][6] = { "100ns" };
 377   static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
 378   static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
 379   char buf[8];
 380
 381   printf("Virtual Channel\n");
 382   if (verbose < 2)
 383     return;
 384
 385   if (!config_fetch(d, where + 4, 0x1c - 4))
 386     return;
 387
 388   cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
 389   cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
 390   ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
 391   status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
 392
 393   evc_cnt = BITS(cr1, 0, 3);
 394   printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
 395     BITS(cr1, 4, 3),
 396     TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
 397     1 << BITS(cr1, 10, 2));
 398
 399   printf("\t\tArb:");
 400   for (i=0; i<8; i++)
 401     if (arb_selects[i][0] != '?' || cr2 & (1 << i))
 402       printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
 403   arb_table_pos = BITS(cr2, 24, 8);
 404
 405   printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
 406   printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
 407
 408   if (arb_table_pos)
 409     {
 410       arb_table_pos = where + 16*arb_table_pos;
 411       printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
 412     }
 413
 414   for (i=0; i<=evc_cnt; i++)
 415     {
 416       int pos = where + PCI_VC_RES_CAP + 12*i;
 417       u32 rcap, rctrl;
 418       u16 rstatus;
 419       int pat_pos;
 420
 421       printf("\t\tVC%d:\t", i);
 422       if (!config_fetch(d, pos, 12))
 423         {
 424           printf("<unreadable>\n");
 425           continue;
 426         }
 427       rcap = get_conf_long(d, pos);
 428       rctrl = get_conf_long(d, pos+4);
 429       rstatus = get_conf_word(d, pos+10);
 430
 431       pat_pos = BITS(rcap, 24, 8);
 432       printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
 433         pat_pos,
 434         BITS(rcap, 16, 6) + 1,
 435         FLAG(rcap, 1 << 15));
 436
 437       printf("\t\t\tArb:");
 438       for (j=0; j<8; j++)
 439         if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
 440           printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
 441
 442       printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
 443         FLAG(rctrl, 1 << 31),
 444         BITS(rctrl, 24, 3),
 445         TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
 446         BITS(rctrl, 0, 8));
 447
 448       printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
 449         FLAG(rstatus, 2),
 450         FLAG(rstatus, 1));
 451
 452       if (pat_pos)
 453         printf("\t\t\tPort Arbitration Table <?>\n");
 454     }
 455 }
 456
 457 static void
 458 cap_rclink(struct device *d, int where)
 459 {
 460   u32 esd;
 461   int num_links;
 462   int i;
 463   static const char elt_types[][9] = { "Config", "Egress", "Internal" };
 464   char buf[8];
 465
 466   printf("Root Complex Link\n");
 467   if (verbose < 2)
 468     return;
 469
 470   if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
 471     return;
 472
 473   esd = get_conf_long(d, where + PCI_RCLINK_ESD);
 474   num_links = BITS(esd, 8, 8);
 475   printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
 476     BITS(esd, 24, 8),
 477     BITS(esd, 16, 8),
 478     TABLE(elt_types, BITS(esd, 0, 8), buf));
 479
 480   for (i=0; i<num_links; i++)
 481     {
 482       int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
 483       u32 desc;
 484       u32 addr_lo, addr_hi;
 485
 486       printf("\t\tLink%d:\t", i);
 487       if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
 488         {
 489           printf("<unreadable>\n");
 490           return;
 491         }
 492       desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
 493       addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
 494       addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
 495
 496       printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
 497         BITS(desc, 24, 8),
 498         BITS(desc, 16, 8),
 499         FLAG(desc, 4),
 500         ((desc & 2) ? "Config" : "MemMapped"),
 501         FLAG(desc, 1));
 502
 503       if (desc & 2)
 504         {
 505           int n = addr_lo & 7;
 506           if (!n)
 507             n = 8;
 508           printf("\t\t\tAddr:\t%02x:%02x.%d  CfgSpace=%08x%08x\n",
 509             BITS(addr_lo, 20, n),
 510             BITS(addr_lo, 15, 5),
 511             BITS(addr_lo, 12, 3),
 512             addr_hi, addr_lo);
 513         }
 514       else
 515         printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
 516     }
 517 }
 518
 519 static void
 520 cap_evendor(struct device *d, int where)
 521 {
 522   u32 hdr;
 523
 524   printf("Vendor Specific Information: ");
 525   if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
 526     {
 527       printf("<unreadable>\n");
 528       return;
 529     }
 530
 531   hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
 532   printf("ID=%04x Rev=%d Len=%03x <?>\n",
 533     BITS(hdr, 0, 16),
 534     BITS(hdr, 16, 4),
 535     BITS(hdr, 20, 12));
 536 }
 537
 538 static int l1pm_calc_pwron(int scale, int value)
 539 {
 540   switch (scale)
 541     {
 542       case 0:
 543         return 2 * value;
 544       case 1:
 545         return 10 * value;
 546       case 2:
 547         return 100 * value;
 548     }
 549   return -1;
 550 }
 551
 552 static void
 553 cap_l1pm(struct device *d, int where)
 554 {
 555   u32 l1_cap, val, scale;
 556   int time;
 557
 558   printf("L1 PM Substates\n");
 559
 560   if (verbose < 2)
 561     return;
 562
 563   if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
 564     {
 565       printf("\t\t<unreadable>\n");
 566       return;
 567     }
 568
 569   l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
 570   printf("\t\tL1SubCap: ");
 571   printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
 572     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
 573     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
 574     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
 575     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
 576     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
 577
 578   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 579     {
 580       printf("\t\t\t  PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
 581       time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
 582       if (time != -1)
 583         printf("PortTPowerOnTime=%dus\n", time);
 584       else
 585         printf("PortTPowerOnTime=<error>\n");
 586     }
 587
 588   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
 589   printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
 590     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
 591     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
 592     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
 593     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
 594
 595   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 596     printf("\t\t\t   T_CommonMode=%dus", BITS(val, 8, 8));
 597
 598   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 599     {
 600       scale = BITS(val, 29, 3);
 601       if (scale > 5)
 602         printf(" LTR1.2_Threshold=<error>");
 603       else
 604         printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
 605     }
 606   printf("\n");
 607
 608   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
 609   printf("\t\tL1SubCtl2:");
 610   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 611     {
 612       time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
 613       if (time != -1)
 614         printf(" T_PwrOn=%dus", time);
 615       else
 616         printf(" T_PwrOn=<error>");
 617     }
 618   printf("\n");
 619 }
 620
 621 static void
 622 cap_ptm(struct device *d, int where)
 623 {
 624   u32 buff;
 625   u16 clock;
 626
 627   printf("Precision Time Measurement\n");
 628
 629   if (verbose < 2)
 630     return;
 631
 632   if (!config_fetch(d, where + 4, 8))
 633     {
 634       printf("\t\t<unreadable>\n");
 635       return;
 636     }
 637
 638   buff = get_conf_long(d, where + 4);
 639   printf("\t\tPTMCap: ");
 640   printf("Requester:%c Responder:%c Root:%c\n",
 641     FLAG(buff, 0x1),
 642     FLAG(buff, 0x2),
 643     FLAG(buff, 0x4));
 644
 645   clock = BITS(buff, 8, 8);
 646   printf("\t\tPTMClockGranularity: ");
 647   switch (clock)
 648     {
 649       case 0x00:
 650         printf("Unimplemented\n");
 651         break;
 652       case 0xff:
 653         printf("Greater than 254ns\n");
 654         break;
 655       default:
 656         printf("%huns\n", clock);
 657     }
 658
 659   buff = get_conf_long(d, where + 8);
 660   printf("\t\tPTMControl: ");
 661   printf("Enabled:%c RootSelected:%c\n",
 662     FLAG(buff, 0x1),
 663     FLAG(buff, 0x2));
 664
 665   clock = BITS(buff, 8, 8);
 666   printf("\t\tPTMEffectiveGranularity: ");
 667   switch (clock)
 668     {
 669       case 0x00:
 670         printf("Unknown\n");
 671         break;
 672       case 0xff:
 673         printf("Greater than 254ns\n");
 674         break;
 675       default:
 676         printf("%huns\n", clock);
 677     }
 678 }
 679
 680 void
 681 show_ext_caps(struct device *d)
 682 {
 683   int where = 0x100;
 684   char been_there[0x1000];
 685   memset(been_there, 0, 0x1000);
 686   do
 687     {
 688       u32 header;
 689       int id, version;
 690
 691       if (!config_fetch(d, where, 4))
 692         break;
 693       header = get_conf_long(d, where);
 694       if (!header)
 695         break;
 696       id = header & 0xffff;
 697       version = (header >> 16) & 0xf;
 698       printf("\tCapabilities: [%03x", where);
 699       if (verbose > 1)
 700         printf(" v%d", version);
 701       printf("] ");
 702       if (been_there[where]++)
 703         {
 704           printf("<chain looped>\n");
 705           break;
 706         }
 707       switch (id)
 708         {
 709           case PCI_EXT_CAP_ID_AER:
 710             cap_aer(d, where);
 711             break;
 712           case PCI_EXT_CAP_ID_DPC:
 713             cap_dpc(d, where);
 714             break;
 715           case PCI_EXT_CAP_ID_VC:
 716           case PCI_EXT_CAP_ID_VC2:
 717             cap_vc(d, where);
 718             break;
 719           case PCI_EXT_CAP_ID_DSN:
 720             cap_dsn(d, where);
 721             break;
 722           case PCI_EXT_CAP_ID_PB:
 723             printf("Power Budgeting <?>\n");
 724             break;
 725           case PCI_EXT_CAP_ID_RCLINK:
 726             cap_rclink(d, where);
 727             break;
 728           case PCI_EXT_CAP_ID_RCILINK:
 729             printf("Root Complex Internal Link <?>\n");
 730             break;
 731           case PCI_EXT_CAP_ID_RCECOLL:
 732             printf("Root Complex Event Collector <?>\n");
 733             break;
 734           case PCI_EXT_CAP_ID_MFVC:
 735             printf("Multi-Function Virtual Channel <?>\n");
 736             break;
 737           case PCI_EXT_CAP_ID_RBCB:
 738             printf("Root Bridge Control Block <?>\n");
 739             break;
 740           case PCI_EXT_CAP_ID_VNDR:
 741             cap_evendor(d, where);
 742             break;
 743           case PCI_EXT_CAP_ID_ACS:
 744             cap_acs(d, where);
 745             break;
 746           case PCI_EXT_CAP_ID_ARI:
 747             cap_ari(d, where);
 748             break;
 749           case PCI_EXT_CAP_ID_ATS:
 750             cap_ats(d, where);
 751             break;
 752           case PCI_EXT_CAP_ID_SRIOV:
 753             cap_sriov(d, where);
 754             break;
 755           case PCI_EXT_CAP_ID_PRI:
 756             cap_pri(d, where);
 757             break;
 758           case PCI_EXT_CAP_ID_TPH:
 759             cap_tph(d, where);
 760             break;
 761           case PCI_EXT_CAP_ID_LTR:
 762             cap_ltr(d, where);
 763             break;
 764           case PCI_EXT_CAP_ID_PASID:
 765             cap_pasid(d, where);
 766             break;
 767           case PCI_EXT_CAP_ID_L1PM:
 768             cap_l1pm(d, where);
 769             break;
 770           case PCI_EXT_CAP_ID_PTM:
 771             cap_ptm(d, where);
 772             break;
 773           default:
 774             printf("#%02x\n", id);
 775             break;
 776         }
 777       where = (header >> 20) & ~3;
 778     } while (where);
 779 }