2 * The PCI Utilities -- Show Extended Capabilities
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_tph(struct device
*d
, int where
)
18 printf("Transaction Processing Hints\n");
22 if (!config_fetch(d
, where
+ PCI_TPH_CAPABILITIES
, 4))
25 tph_cap
= get_conf_long(d
, where
+ PCI_TPH_CAPABILITIES
);
27 if (tph_cap
& PCI_TPH_INTVEC_SUP
)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap
& PCI_TPH_DEV_SUP
)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap
& PCI_TPH_EXT_REQ_SUP
)
32 printf("\t\tExtended requester support\n");
34 switch (tph_cap
& PCI_TPH_ST_LOC_MASK
) {
36 printf("\t\tNo steering table available\n");
39 printf("\t\tSteering table in TPH capability structure\n");
42 printf("\t\tSteering table in MSI-X table\n");
45 printf("\t\tReserved steering table location\n");
51 cap_ltr_scale(u8 scale
)
53 return 1 << (scale
* 5);
57 cap_ltr(struct device
*d
, int where
)
61 printf("Latency Tolerance Reporting\n");
65 if (!config_fetch(d
, where
+ PCI_LTR_MAX_SNOOP
, 4))
68 snoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_SNOOP
);
69 scale
= cap_ltr_scale((snoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
70 printf("\t\tMax snoop latency: %lldns\n",
71 ((unsigned long long)snoop
& PCI_LTR_VALUE_MASK
) * scale
);
73 nosnoop
= get_conf_word(d
, where
+ PCI_LTR_MAX_NOSNOOP
);
74 scale
= cap_ltr_scale((nosnoop
>> PCI_LTR_SCALE_SHIFT
) & PCI_LTR_SCALE_MASK
);
75 printf("\t\tMax no snoop latency: %lldns\n",
76 ((unsigned long long)nosnoop
& PCI_LTR_VALUE_MASK
) * scale
);
80 cap_dsn(struct device
*d
, int where
)
83 if (!config_fetch(d
, where
+ 4, 8))
85 t1
= get_conf_long(d
, where
+ 4);
86 t2
= get_conf_long(d
, where
+ 8);
87 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
88 t2
>> 24, (t2
>> 16) & 0xff, (t2
>> 8) & 0xff, t2
& 0xff,
89 t1
>> 24, (t1
>> 16) & 0xff, (t1
>> 8) & 0xff, t1
& 0xff);
93 cap_aer(struct device
*d
, int where
, int type
)
95 u32 l
, l0
, l1
, l2
, l3
;
98 printf("Advanced Error Reporting\n");
102 if (!config_fetch(d
, where
+ PCI_ERR_UNCOR_STATUS
, 40))
105 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_STATUS
);
106 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
107 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
108 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
109 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
110 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
111 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
112 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_MASK
);
113 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
114 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
115 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
116 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
117 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
118 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
119 l
= get_conf_long(d
, where
+ PCI_ERR_UNCOR_SEVER
);
120 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
121 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
122 FLAG(l
, PCI_ERR_UNC_DLP
), FLAG(l
, PCI_ERR_UNC_SDES
), FLAG(l
, PCI_ERR_UNC_POISON_TLP
),
123 FLAG(l
, PCI_ERR_UNC_FCP
), FLAG(l
, PCI_ERR_UNC_COMP_TIME
), FLAG(l
, PCI_ERR_UNC_COMP_ABORT
),
124 FLAG(l
, PCI_ERR_UNC_UNX_COMP
), FLAG(l
, PCI_ERR_UNC_RX_OVER
), FLAG(l
, PCI_ERR_UNC_MALF_TLP
),
125 FLAG(l
, PCI_ERR_UNC_ECRC
), FLAG(l
, PCI_ERR_UNC_UNSUP
), FLAG(l
, PCI_ERR_UNC_ACS_VIOL
));
126 l
= get_conf_long(d
, where
+ PCI_ERR_COR_STATUS
);
127 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
128 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
129 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
130 l
= get_conf_long(d
, where
+ PCI_ERR_COR_MASK
);
131 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
132 FLAG(l
, PCI_ERR_COR_RCVR
), FLAG(l
, PCI_ERR_COR_BAD_TLP
), FLAG(l
, PCI_ERR_COR_BAD_DLLP
),
133 FLAG(l
, PCI_ERR_COR_REP_ROLL
), FLAG(l
, PCI_ERR_COR_REP_TIMER
), FLAG(l
, PCI_ERR_COR_REP_ANFE
));
134 l
= get_conf_long(d
, where
+ PCI_ERR_CAP
);
135 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
136 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
137 PCI_ERR_CAP_FEP(l
), FLAG(l
, PCI_ERR_CAP_ECRC_GENC
), FLAG(l
, PCI_ERR_CAP_ECRC_GENE
),
138 FLAG(l
, PCI_ERR_CAP_ECRC_CHKC
), FLAG(l
, PCI_ERR_CAP_ECRC_CHKE
),
139 FLAG(l
, PCI_ERR_CAP_MULT_HDRC
), FLAG(l
, PCI_ERR_CAP_MULT_HDRE
),
140 FLAG(l
, PCI_ERR_CAP_TLP_PFX
), FLAG(l
, PCI_ERR_CAP_HDR_LOG
));
142 l0
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
);
143 l1
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 4);
144 l2
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 8);
145 l3
= get_conf_long(d
, where
+ PCI_ERR_HEADER_LOG
+ 12);
146 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0
, l1
, l2
, l3
);
148 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ROOT_EC
)
150 if (!config_fetch(d
, where
+ PCI_ERR_ROOT_COMMAND
, 12))
153 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_COMMAND
);
154 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
155 FLAG(l
, PCI_ERR_ROOT_CMD_COR_EN
),
156 FLAG(l
, PCI_ERR_ROOT_CMD_NONFATAL_EN
),
157 FLAG(l
, PCI_ERR_ROOT_CMD_FATAL_EN
));
159 l
= get_conf_long(d
, where
+ PCI_ERR_ROOT_STATUS
);
160 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
161 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
162 FLAG(l
, PCI_ERR_ROOT_COR_RCV
),
163 FLAG(l
, PCI_ERR_ROOT_MULTI_COR_RCV
),
164 FLAG(l
, PCI_ERR_ROOT_UNCOR_RCV
),
165 FLAG(l
, PCI_ERR_ROOT_MULTI_UNCOR_RCV
),
166 FLAG(l
, PCI_ERR_ROOT_FIRST_FATAL
),
167 FLAG(l
, PCI_ERR_ROOT_NONFATAL_RCV
),
168 FLAG(l
, PCI_ERR_ROOT_FATAL_RCV
),
171 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_COR_SRC
);
172 printf("\t\tErrorSrc: ERR_COR: %04x ", w
);
174 w
= get_conf_word(d
, where
+ PCI_ERR_ROOT_SRC
);
175 printf("ERR_FATAL/NONFATAL: %04x\n", w
);
179 static void cap_dpc(struct device
*d
, int where
)
183 printf("Downstream Port Containment\n");
187 if (!config_fetch(d
, where
+ PCI_DPC_CAP
, 8))
190 l
= get_conf_word(d
, where
+ PCI_DPC_CAP
);
191 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
192 PCI_DPC_CAP_INT_MSG(l
), FLAG(l
, PCI_DPC_CAP_RP_EXT
), FLAG(l
, PCI_DPC_CAP_TLP_BLOCK
),
193 FLAG(l
, PCI_DPC_CAP_SW_TRIGGER
), PCI_DPC_CAP_RP_LOG(l
), FLAG(l
, PCI_DPC_CAP_DL_ACT_ERR
));
195 l
= get_conf_word(d
, where
+ PCI_DPC_CTL
);
196 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
197 PCI_DPC_CTL_TRIGGER(l
), FLAG(l
, PCI_DPC_CTL_CMPL
), FLAG(l
, PCI_DPC_CTL_INT
),
198 FLAG(l
, PCI_DPC_CTL_ERR_COR
), FLAG(l
, PCI_DPC_CTL_TLP
), FLAG(l
, PCI_DPC_CTL_SW_TRIGGER
),
199 FLAG(l
, PCI_DPC_CTL_DL_ACTIVE
));
201 l
= get_conf_word(d
, where
+ PCI_DPC_STATUS
);
202 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
203 FLAG(l
, PCI_DPC_STS_TRIGGER
), PCI_DPC_STS_REASON(l
), FLAG(l
, PCI_DPC_STS_INT
),
204 FLAG(l
, PCI_DPC_STS_RP_BUSY
), PCI_DPC_STS_TRIGGER_EXT(l
), PCI_DPC_STS_PIO_FEP(l
));
206 l
= get_conf_word(d
, where
+ PCI_DPC_SOURCE
);
207 printf("\t\tSource:\t%04x\n", l
);
211 cap_acs(struct device
*d
, int where
)
215 printf("Access Control Services\n");
219 if (!config_fetch(d
, where
+ PCI_ACS_CAP
, 4))
222 w
= get_conf_word(d
, where
+ PCI_ACS_CAP
);
223 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
225 FLAG(w
, PCI_ACS_CAP_VALID
), FLAG(w
, PCI_ACS_CAP_BLOCK
), FLAG(w
, PCI_ACS_CAP_REQ_RED
),
226 FLAG(w
, PCI_ACS_CAP_CMPLT_RED
), FLAG(w
, PCI_ACS_CAP_FORWARD
), FLAG(w
, PCI_ACS_CAP_EGRESS
),
227 FLAG(w
, PCI_ACS_CAP_TRANS
));
228 w
= get_conf_word(d
, where
+ PCI_ACS_CTRL
);
229 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
231 FLAG(w
, PCI_ACS_CTRL_VALID
), FLAG(w
, PCI_ACS_CTRL_BLOCK
), FLAG(w
, PCI_ACS_CTRL_REQ_RED
),
232 FLAG(w
, PCI_ACS_CTRL_CMPLT_RED
), FLAG(w
, PCI_ACS_CTRL_FORWARD
), FLAG(w
, PCI_ACS_CTRL_EGRESS
),
233 FLAG(w
, PCI_ACS_CTRL_TRANS
));
237 cap_ari(struct device
*d
, int where
)
241 printf("Alternative Routing-ID Interpretation (ARI)\n");
245 if (!config_fetch(d
, where
+ PCI_ARI_CAP
, 4))
248 w
= get_conf_word(d
, where
+ PCI_ARI_CAP
);
249 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
250 FLAG(w
, PCI_ARI_CAP_MFVC
), FLAG(w
, PCI_ARI_CAP_ACS
),
252 w
= get_conf_word(d
, where
+ PCI_ARI_CTRL
);
253 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
254 FLAG(w
, PCI_ARI_CTRL_MFVC
), FLAG(w
, PCI_ARI_CTRL_ACS
),
259 cap_ats(struct device
*d
, int where
)
263 printf("Address Translation Service (ATS)\n");
267 if (!config_fetch(d
, where
+ PCI_ATS_CAP
, 4))
270 w
= get_conf_word(d
, where
+ PCI_ATS_CAP
);
271 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w
));
272 w
= get_conf_word(d
, where
+ PCI_ATS_CTRL
);
273 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
274 FLAG(w
, PCI_ATS_CTRL_ENABLE
), PCI_ATS_CTRL_STU(w
));
278 cap_pri(struct device
*d
, int where
)
283 printf("Page Request Interface (PRI)\n");
287 if (!config_fetch(d
, where
+ PCI_PRI_CTRL
, 0xc))
290 w
= get_conf_word(d
, where
+ PCI_PRI_CTRL
);
291 printf("\t\tPRICtl: Enable%c Reset%c\n",
292 FLAG(w
, PCI_PRI_CTRL_ENABLE
), FLAG(w
, PCI_PRI_CTRL_RESET
));
293 w
= get_conf_word(d
, where
+ PCI_PRI_STATUS
);
294 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
295 FLAG(w
, PCI_PRI_STATUS_RF
), FLAG(w
, PCI_PRI_STATUS_UPRGI
),
296 FLAG(w
, PCI_PRI_STATUS_STOPPED
));
297 l
= get_conf_long(d
, where
+ PCI_PRI_MAX_REQ
);
298 printf("\t\tPage Request Capacity: %08x, ", l
);
299 l
= get_conf_long(d
, where
+ PCI_PRI_ALLOC_REQ
);
300 printf("Page Request Allocation: %08x\n", l
);
304 cap_pasid(struct device
*d
, int where
)
308 printf("Process Address Space ID (PASID)\n");
312 if (!config_fetch(d
, where
+ PCI_PASID_CAP
, 4))
315 w
= get_conf_word(d
, where
+ PCI_PASID_CAP
);
316 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
317 FLAG(w
, PCI_PASID_CAP_EXEC
), FLAG(w
, PCI_PASID_CAP_PRIV
),
318 PCI_PASID_CAP_WIDTH(w
));
319 w
= get_conf_word(d
, where
+ PCI_PASID_CTRL
);
320 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
321 FLAG(w
, PCI_PASID_CTRL_ENABLE
), FLAG(w
, PCI_PASID_CTRL_EXEC
),
322 FLAG(w
, PCI_PASID_CTRL_PRIV
));
326 cap_sriov(struct device
*d
, int where
)
333 printf("Single Root I/O Virtualization (SR-IOV)\n");
337 if (!config_fetch(d
, where
+ PCI_IOV_CAP
, 0x3c))
340 l
= get_conf_long(d
, where
+ PCI_IOV_CAP
);
341 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
342 FLAG(l
, PCI_IOV_CAP_VFM
), PCI_IOV_CAP_IMN(l
));
343 w
= get_conf_word(d
, where
+ PCI_IOV_CTRL
);
344 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
345 FLAG(w
, PCI_IOV_CTRL_VFE
), FLAG(w
, PCI_IOV_CTRL_VFME
),
346 FLAG(w
, PCI_IOV_CTRL_VFMIE
), FLAG(w
, PCI_IOV_CTRL_MSE
),
347 FLAG(w
, PCI_IOV_CTRL_ARI
));
348 w
= get_conf_word(d
, where
+ PCI_IOV_STATUS
);
349 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w
, PCI_IOV_STATUS_MS
));
350 w
= get_conf_word(d
, where
+ PCI_IOV_INITIALVF
);
351 printf("\t\tInitial VFs: %d, ", w
);
352 w
= get_conf_word(d
, where
+ PCI_IOV_TOTALVF
);
353 printf("Total VFs: %d, ", w
);
354 w
= get_conf_word(d
, where
+ PCI_IOV_NUMVF
);
355 printf("Number of VFs: %d, ", w
);
356 b
= get_conf_byte(d
, where
+ PCI_IOV_FDL
);
357 printf("Function Dependency Link: %02x\n", b
);
358 w
= get_conf_word(d
, where
+ PCI_IOV_OFFSET
);
359 printf("\t\tVF offset: %d, ", w
);
360 w
= get_conf_word(d
, where
+ PCI_IOV_STRIDE
);
361 printf("stride: %d, ", w
);
362 w
= get_conf_word(d
, where
+ PCI_IOV_DID
);
363 printf("Device ID: %04x\n", w
);
364 l
= get_conf_long(d
, where
+ PCI_IOV_SUPPS
);
365 printf("\t\tSupported Page Size: %08x, ", l
);
366 l
= get_conf_long(d
, where
+ PCI_IOV_SYSPS
);
367 printf("System Page Size: %08x\n", l
);
369 for (i
=0; i
< PCI_IOV_NUM_BAR
; i
++)
374 l
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ 4*i
);
379 printf("\t\tRegion %d: Memory at ", i
);
380 addr
= l
& PCI_ADDR_MEM_MASK
;
381 type
= l
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
382 if (type
== PCI_BASE_ADDRESS_MEM_TYPE_64
)
385 h
= get_conf_long(d
, where
+ PCI_IOV_BAR_BASE
+ (i
*4));
388 printf("%08x (%s-bit, %sprefetchable)\n",
390 (type
== PCI_BASE_ADDRESS_MEM_TYPE_32
) ? "32" : "64",
391 (l
& PCI_BASE_ADDRESS_MEM_PREFETCH
) ? "" : "non-");
394 l
= get_conf_long(d
, where
+ PCI_IOV_MSAO
);
395 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l
),
400 cap_vc(struct device
*d
, int where
)
407 static const char ref_clocks
[][6] = { "100ns" };
408 static const char arb_selects
[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
409 static const char vc_arb_selects
[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
412 printf("Virtual Channel\n");
416 if (!config_fetch(d
, where
+ 4, 0x1c - 4))
419 cr1
= get_conf_long(d
, where
+ PCI_VC_PORT_REG1
);
420 cr2
= get_conf_long(d
, where
+ PCI_VC_PORT_REG2
);
421 ctrl
= get_conf_word(d
, where
+ PCI_VC_PORT_CTRL
);
422 status
= get_conf_word(d
, where
+ PCI_VC_PORT_STATUS
);
424 evc_cnt
= BITS(cr1
, 0, 3);
425 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
427 TABLE(ref_clocks
, BITS(cr1
, 8, 2), buf
),
428 1 << BITS(cr1
, 10, 2));
432 if (arb_selects
[i
][0] != '?' || cr2
& (1 << i
))
433 printf("%c%s%c", (i
? ' ' : '\t'), arb_selects
[i
], FLAG(cr2
, 1 << i
));
434 arb_table_pos
= BITS(cr2
, 24, 8);
436 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects
, BITS(ctrl
, 1, 3), buf
));
437 printf("\t\tStatus:\tInProgress%c\n", FLAG(status
, 1));
441 arb_table_pos
= where
+ 16*arb_table_pos
;
442 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos
);
445 for (i
=0; i
<=evc_cnt
; i
++)
447 int pos
= where
+ PCI_VC_RES_CAP
+ 12*i
;
452 printf("\t\tVC%d:\t", i
);
453 if (!config_fetch(d
, pos
, 12))
455 printf("<unreadable>\n");
458 rcap
= get_conf_long(d
, pos
);
459 rctrl
= get_conf_long(d
, pos
+4);
460 rstatus
= get_conf_word(d
, pos
+10);
462 pat_pos
= BITS(rcap
, 24, 8);
463 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
465 BITS(rcap
, 16, 6) + 1,
466 FLAG(rcap
, 1 << 15));
468 printf("\t\t\tArb:");
470 if (vc_arb_selects
[j
][0] != '?' || rcap
& (1 << j
))
471 printf("%c%s%c", (j
? ' ' : '\t'), vc_arb_selects
[j
], FLAG(rcap
, 1 << j
));
473 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
474 FLAG(rctrl
, 1 << 31),
476 TABLE(vc_arb_selects
, BITS(rctrl
, 17, 3), buf
),
479 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
484 printf("\t\t\tPort Arbitration Table <?>\n");
489 cap_rclink(struct device
*d
, int where
)
494 static const char elt_types
[][9] = { "Config", "Egress", "Internal" };
497 printf("Root Complex Link\n");
501 if (!config_fetch(d
, where
+ 4, PCI_RCLINK_LINK1
- 4))
504 esd
= get_conf_long(d
, where
+ PCI_RCLINK_ESD
);
505 num_links
= BITS(esd
, 8, 8);
506 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
509 TABLE(elt_types
, BITS(esd
, 0, 8), buf
));
511 for (i
=0; i
<num_links
; i
++)
513 int pos
= where
+ PCI_RCLINK_LINK1
+ i
*PCI_RCLINK_LINK_SIZE
;
515 u32 addr_lo
, addr_hi
;
517 printf("\t\tLink%d:\t", i
);
518 if (!config_fetch(d
, pos
, PCI_RCLINK_LINK_SIZE
))
520 printf("<unreadable>\n");
523 desc
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_DESC
);
524 addr_lo
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
);
525 addr_hi
= get_conf_long(d
, pos
+ PCI_RCLINK_LINK_ADDR
+ 4);
527 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
531 ((desc
& 2) ? "Config" : "MemMapped"),
539 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
540 BITS(addr_lo
, 20, n
),
541 BITS(addr_lo
, 15, 5),
542 BITS(addr_lo
, 12, 3),
546 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi
, addr_lo
);
551 cap_evendor(struct device
*d
, int where
)
555 printf("Vendor Specific Information: ");
556 if (!config_fetch(d
, where
+ PCI_EVNDR_HEADER
, 4))
558 printf("<unreadable>\n");
562 hdr
= get_conf_long(d
, where
+ PCI_EVNDR_HEADER
);
563 printf("ID=%04x Rev=%d Len=%03x <?>\n",
569 static int l1pm_calc_pwron(int scale
, int value
)
584 cap_l1pm(struct device
*d
, int where
)
586 u32 l1_cap
, val
, scale
;
589 printf("L1 PM Substates\n");
594 if (!config_fetch(d
, where
+ PCI_L1PM_SUBSTAT_CAP
, 12))
596 printf("\t\t<unreadable>\n");
600 l1_cap
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CAP
);
601 printf("\t\tL1SubCap: ");
602 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
603 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L12
),
604 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_PM_L11
),
605 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L12
),
606 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_ASPM_L11
),
607 FLAG(l1_cap
, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP
));
609 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
611 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap
, 8, 8));
612 time
= l1pm_calc_pwron(BITS(l1_cap
, 16, 2), BITS(l1_cap
, 19, 5));
614 printf("PortTPowerOnTime=%dus\n", time
);
616 printf("PortTPowerOnTime=<error>\n");
619 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL1
);
620 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
621 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L12
),
622 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_PM_L11
),
623 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12
),
624 FLAG(val
, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11
));
626 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
627 printf("\t\t\t T_CommonMode=%dus", BITS(val
, 8, 8));
629 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
631 scale
= BITS(val
, 29, 3);
633 printf(" LTR1.2_Threshold=<error>");
635 printf(" LTR1.2_Threshold=%lldns", BITS(val
, 16, 10) * (unsigned long long) cap_ltr_scale(scale
));
639 val
= get_conf_long(d
, where
+ PCI_L1PM_SUBSTAT_CTL2
);
640 printf("\t\tL1SubCtl2:");
641 if (l1_cap
& PCI_L1PM_SUBSTAT_CAP_PM_L12
|| l1_cap
& PCI_L1PM_SUBSTAT_CAP_ASPM_L12
)
643 time
= l1pm_calc_pwron(BITS(val
, 0, 2), BITS(val
, 3, 5));
645 printf(" T_PwrOn=%dus", time
);
647 printf(" T_PwrOn=<error>");
653 cap_ptm(struct device
*d
, int where
)
658 printf("Precision Time Measurement\n");
663 if (!config_fetch(d
, where
+ 4, 8))
665 printf("\t\t<unreadable>\n");
669 buff
= get_conf_long(d
, where
+ 4);
670 printf("\t\tPTMCap: ");
671 printf("Requester:%c Responder:%c Root:%c\n",
676 clock
= BITS(buff
, 8, 8);
677 printf("\t\tPTMClockGranularity: ");
681 printf("Unimplemented\n");
684 printf("Greater than 254ns\n");
687 printf("%huns\n", clock
);
690 buff
= get_conf_long(d
, where
+ 8);
691 printf("\t\tPTMControl: ");
692 printf("Enabled:%c RootSelected:%c\n",
696 clock
= BITS(buff
, 8, 8);
697 printf("\t\tPTMEffectiveGranularity: ");
704 printf("Greater than 254ns\n");
707 printf("%huns\n", clock
);
712 show_ext_caps(struct device
*d
, int type
)
715 char been_there
[0x1000];
716 memset(been_there
, 0, 0x1000);
722 if (!config_fetch(d
, where
, 4))
724 header
= get_conf_long(d
, where
);
727 id
= header
& 0xffff;
728 version
= (header
>> 16) & 0xf;
729 printf("\tCapabilities: [%03x", where
);
731 printf(" v%d", version
);
733 if (been_there
[where
]++)
735 printf("<chain looped>\n");
740 case PCI_EXT_CAP_ID_NULL
:
743 case PCI_EXT_CAP_ID_AER
:
744 cap_aer(d
, where
, type
);
746 case PCI_EXT_CAP_ID_DPC
:
749 case PCI_EXT_CAP_ID_VC
:
750 case PCI_EXT_CAP_ID_VC2
:
753 case PCI_EXT_CAP_ID_DSN
:
756 case PCI_EXT_CAP_ID_PB
:
757 printf("Power Budgeting <?>\n");
759 case PCI_EXT_CAP_ID_RCLINK
:
760 cap_rclink(d
, where
);
762 case PCI_EXT_CAP_ID_RCILINK
:
763 printf("Root Complex Internal Link <?>\n");
765 case PCI_EXT_CAP_ID_RCECOLL
:
766 printf("Root Complex Event Collector <?>\n");
768 case PCI_EXT_CAP_ID_MFVC
:
769 printf("Multi-Function Virtual Channel <?>\n");
771 case PCI_EXT_CAP_ID_RBCB
:
772 printf("Root Bridge Control Block <?>\n");
774 case PCI_EXT_CAP_ID_VNDR
:
775 cap_evendor(d
, where
);
777 case PCI_EXT_CAP_ID_ACS
:
780 case PCI_EXT_CAP_ID_ARI
:
783 case PCI_EXT_CAP_ID_ATS
:
786 case PCI_EXT_CAP_ID_SRIOV
:
789 case PCI_EXT_CAP_ID_MRIOV
:
790 printf("Multi-Root I/O Virtualization <?>\n");
792 case PCI_EXT_CAP_ID_PRI
:
795 case PCI_EXT_CAP_ID_REBAR
:
796 printf("Resizable BAR <?>\n");
798 case PCI_EXT_CAP_ID_DPA
:
799 printf("Dynamic Power Allocation <?>\n");
801 case PCI_EXT_CAP_ID_TPH
:
804 case PCI_EXT_CAP_ID_LTR
:
807 case PCI_EXT_CAP_ID_SECPCI
:
808 printf("Secondary PCI Express <?>\n");
810 case PCI_EXT_CAP_ID_PMUX
:
811 printf("Protocol Multiplexing <?>\n");
813 case PCI_EXT_CAP_ID_PASID
:
816 case PCI_EXT_CAP_ID_LNR
:
817 printf("LN Requester <?>\n");
819 case PCI_EXT_CAP_ID_L1PM
:
822 case PCI_EXT_CAP_ID_PTM
:
825 case PCI_EXT_CAP_ID_M_PCIE
:
826 printf("PCI Express over M_PHY <?>\n");
828 case PCI_EXT_CAP_ID_FRS
:
829 printf("FRS Queueing <?>\n");
831 case PCI_EXT_CAP_ID_RTR
:
832 printf("Readiness Time Reporting <?>\n");
834 case PCI_EXT_CAP_ID_DVSEC
:
835 printf("Designated Vendor-Specific <?>\n");
837 case PCI_EXT_CAP_ID_VF_REBAR
:
838 printf("VF Resizable BAR <?>\n");
840 case PCI_EXT_CAP_ID_DLNK
:
841 printf("Data Link Feature <?>\n");
843 case PCI_EXT_CAP_ID_16GT
:
844 printf("Physical Layer 16.0 GT/s <?>\n");
846 case PCI_EXT_CAP_ID_LMR
:
847 printf("Lane Margining at the Receiver <?>\n");
849 case PCI_EXT_CAP_ID_HIER_ID
:
850 printf("Hierarchy ID <?>\n");
852 case PCI_EXT_CAP_ID_NPEM
:
853 printf("Native PCIe Enclosure Management <?>\n");
856 printf("Extended Capability ID %#02x\n", id
);
859 where
= (header
>> 20) & ~3;