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CXL3.0: Add DVSEC CXLCtrl3 and missing CXLCtl2
[thirdparty/pciutils.git] / ls-ecaps.c
1 /*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
4 * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11
12 #include "lspci.h"
13
14 static void
15 cap_tph(struct device *d, int where)
16 {
17 u32 tph_cap;
18 printf("Transaction Processing Hints\n");
19 if (verbose < 2)
20 return;
21
22 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
23 return;
24
25 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
26
27 if (tph_cap & PCI_TPH_INTVEC_SUP)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap & PCI_TPH_DEV_SUP)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
32 printf("\t\tExtended requester support\n");
33
34 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
35 case PCI_TPH_ST_NONE:
36 printf("\t\tNo steering table available\n");
37 break;
38 case PCI_TPH_ST_CAP:
39 printf("\t\tSteering table in TPH capability structure\n");
40 break;
41 case PCI_TPH_ST_MSIX:
42 printf("\t\tSteering table in MSI-X table\n");
43 break;
44 default:
45 printf("\t\tReserved steering table location\n");
46 break;
47 }
48 }
49
50 static u32
51 cap_ltr_scale(u8 scale)
52 {
53 return 1 << (scale * 5);
54 }
55
56 static void
57 cap_ltr(struct device *d, int where)
58 {
59 u32 scale;
60 u16 snoop, nosnoop;
61 printf("Latency Tolerance Reporting\n");
62 if (verbose < 2)
63 return;
64
65 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
66 return;
67
68 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
69 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
70 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
71 ((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
72
73 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
74 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
75 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
76 ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
77 }
78
79 static void
80 cap_sec(struct device *d, int where)
81 {
82 u32 ctrl3, lane_err_stat;
83 u8 lane;
84 printf("Secondary PCI Express\n");
85 if (verbose < 2)
86 return;
87
88 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
89 return;
90
91 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
92 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
93 FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
94 FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
95
96 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
97 printf("\t\tLaneErrStat: ");
98 if (lane_err_stat)
99 {
100 printf("LaneErr at lane:");
101 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
102 if (BITS(lane_err_stat, 0, 1))
103 printf(" %u", lane);
104 }
105 else
106 printf("0");
107 printf("\n");
108 }
109
110 static void
111 cap_dsn(struct device *d, int where)
112 {
113 u32 t1, t2;
114 if (!config_fetch(d, where + 4, 8))
115 return;
116 t1 = get_conf_long(d, where + 4);
117 t2 = get_conf_long(d, where + 8);
118 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
119 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
120 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
121 }
122
123 static void
124 cap_aer(struct device *d, int where, int type)
125 {
126 u32 l, l0, l1, l2, l3;
127 u16 w;
128
129 printf("Advanced Error Reporting\n");
130 if (verbose < 2)
131 return;
132
133 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
134 return;
135
136 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
137 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
138 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
139 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
140 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
141 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
142 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
143 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
144 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
145 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
146 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
147 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
148 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
149 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
150 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
151 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
152 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
153 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
154 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
155 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
156 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
157 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
158 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
159 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
160 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
161 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
162 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
163 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
164 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
165 l = get_conf_long(d, where + PCI_ERR_CAP);
166 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
167 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
168 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
169 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
170 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
171 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
172
173 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
174 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
175 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
176 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
177 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
178
179 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
180 {
181 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
182 return;
183
184 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
185 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
186 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
187 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
188 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
189
190 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
191 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
192 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
193 FLAG(l, PCI_ERR_ROOT_COR_RCV),
194 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
195 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
196 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
197 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
198 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
199 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
200 PCI_ERR_MSG_NUM(l));
201
202 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
203 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
204
205 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
206 printf("ERR_FATAL/NONFATAL: %04x\n", w);
207 }
208 }
209
210 static void cap_dpc(struct device *d, int where)
211 {
212 u16 l;
213
214 printf("Downstream Port Containment\n");
215 if (verbose < 2)
216 return;
217
218 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
219 return;
220
221 l = get_conf_word(d, where + PCI_DPC_CAP);
222 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
223 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
224 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
225
226 l = get_conf_word(d, where + PCI_DPC_CTL);
227 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
228 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
229 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
230 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
231
232 l = get_conf_word(d, where + PCI_DPC_STATUS);
233 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
234 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
235 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
236
237 l = get_conf_word(d, where + PCI_DPC_SOURCE);
238 printf("\t\tSource:\t%04x\n", l);
239 }
240
241 static void
242 cap_acs(struct device *d, int where)
243 {
244 u16 w;
245
246 printf("Access Control Services\n");
247 if (verbose < 2)
248 return;
249
250 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
251 return;
252
253 w = get_conf_word(d, where + PCI_ACS_CAP);
254 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
255 "DirectTrans%c\n",
256 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
257 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
258 FLAG(w, PCI_ACS_CAP_TRANS));
259 w = get_conf_word(d, where + PCI_ACS_CTRL);
260 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
261 "DirectTrans%c\n",
262 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
263 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
264 FLAG(w, PCI_ACS_CTRL_TRANS));
265 }
266
267 static void
268 cap_ari(struct device *d, int where)
269 {
270 u16 w;
271
272 printf("Alternative Routing-ID Interpretation (ARI)\n");
273 if (verbose < 2)
274 return;
275
276 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
277 return;
278
279 w = get_conf_word(d, where + PCI_ARI_CAP);
280 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
281 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
282 PCI_ARI_CAP_NFN(w));
283 w = get_conf_word(d, where + PCI_ARI_CTRL);
284 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
285 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
286 PCI_ARI_CTRL_FG(w));
287 }
288
289 static void
290 cap_ats(struct device *d, int where)
291 {
292 u16 w;
293
294 printf("Address Translation Service (ATS)\n");
295 if (verbose < 2)
296 return;
297
298 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
299 return;
300
301 w = get_conf_word(d, where + PCI_ATS_CAP);
302 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
303 w = get_conf_word(d, where + PCI_ATS_CTRL);
304 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
305 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
306 }
307
308 static void
309 cap_pri(struct device *d, int where)
310 {
311 u16 w;
312 u32 l;
313
314 printf("Page Request Interface (PRI)\n");
315 if (verbose < 2)
316 return;
317
318 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
319 return;
320
321 w = get_conf_word(d, where + PCI_PRI_CTRL);
322 printf("\t\tPRICtl: Enable%c Reset%c\n",
323 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
324 w = get_conf_word(d, where + PCI_PRI_STATUS);
325 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
326 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
327 FLAG(w, PCI_PRI_STATUS_STOPPED));
328 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
329 printf("\t\tPage Request Capacity: %08x, ", l);
330 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
331 printf("Page Request Allocation: %08x\n", l);
332 }
333
334 static void
335 cap_pasid(struct device *d, int where)
336 {
337 u16 w;
338
339 printf("Process Address Space ID (PASID)\n");
340 if (verbose < 2)
341 return;
342
343 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
344 return;
345
346 w = get_conf_word(d, where + PCI_PASID_CAP);
347 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
348 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
349 PCI_PASID_CAP_WIDTH(w));
350 w = get_conf_word(d, where + PCI_PASID_CTRL);
351 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
352 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
353 FLAG(w, PCI_PASID_CTRL_PRIV));
354 }
355
356 static void
357 cap_sriov(struct device *d, int where)
358 {
359 u16 b;
360 u16 w;
361 u32 l;
362 int i;
363
364 printf("Single Root I/O Virtualization (SR-IOV)\n");
365 if (verbose < 2)
366 return;
367
368 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
369 return;
370
371 l = get_conf_long(d, where + PCI_IOV_CAP);
372 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
373 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
374 w = get_conf_word(d, where + PCI_IOV_CTRL);
375 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
376 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
377 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
378 FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
379 w = get_conf_word(d, where + PCI_IOV_STATUS);
380 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
381 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
382 printf("\t\tInitial VFs: %d, ", w);
383 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
384 printf("Total VFs: %d, ", w);
385 w = get_conf_word(d, where + PCI_IOV_NUMVF);
386 printf("Number of VFs: %d, ", w);
387 b = get_conf_byte(d, where + PCI_IOV_FDL);
388 printf("Function Dependency Link: %02x\n", b);
389 w = get_conf_word(d, where + PCI_IOV_OFFSET);
390 printf("\t\tVF offset: %d, ", w);
391 w = get_conf_word(d, where + PCI_IOV_STRIDE);
392 printf("stride: %d, ", w);
393 w = get_conf_word(d, where + PCI_IOV_DID);
394 printf("Device ID: %04x\n", w);
395 l = get_conf_long(d, where + PCI_IOV_SUPPS);
396 printf("\t\tSupported Page Size: %08x, ", l);
397 l = get_conf_long(d, where + PCI_IOV_SYSPS);
398 printf("System Page Size: %08x\n", l);
399
400 for (i=0; i < PCI_IOV_NUM_BAR; i++)
401 {
402 u32 addr;
403 int type;
404 u32 h;
405 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
406 if (l == 0xffffffff)
407 l = 0;
408 if (!l)
409 continue;
410 printf("\t\tRegion %d: Memory at ", i);
411 addr = l & PCI_ADDR_MEM_MASK;
412 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
413 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
414 {
415 i++;
416 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
417 printf("%08x", h);
418 }
419 printf("%08x (%s-bit, %sprefetchable)\n",
420 addr,
421 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
422 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
423 }
424
425 l = get_conf_long(d, where + PCI_IOV_MSAO);
426 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
427 PCI_IOV_MSA_BIR(l));
428 }
429
430 static void
431 cap_multicast(struct device *d, int where, int type)
432 {
433 u16 w;
434 u32 l;
435 u64 bar, rcv, block;
436
437 printf("Multicast\n");
438 if (verbose < 2)
439 return;
440
441 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
442 return;
443
444 w = get_conf_word(d, where + PCI_MCAST_CAP);
445 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
446 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
447 printf(", WindowSz %d (%d bytes)",
448 PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
449 if (type == PCI_EXP_TYPE_ROOT_PORT ||
450 type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
451 printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
452 w = get_conf_word(d, where + PCI_MCAST_CTRL);
453 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
454 PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
455 bar = get_conf_long(d, where + PCI_MCAST_BAR);
456 l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
457 bar |= (u64) l << 32;
458 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
459 PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
460 rcv = get_conf_long(d, where + PCI_MCAST_RCV);
461 l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
462 rcv |= (u64) l << 32;
463 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
464 block = get_conf_long(d, where + PCI_MCAST_BLOCK);
465 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
466 block |= (u64) l << 32;
467 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
468 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
469 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
470 block |= (u64) l << 32;
471 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
472
473 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
474 return;
475 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
476 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
477 bar |= (u64) l << 32;
478 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
479 if (PCI_MCAST_OVL_SIZE(bar) >= 6)
480 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
481 else
482 printf("(disabled)");
483 printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
484 }
485
486 static void
487 cap_vc(struct device *d, int where)
488 {
489 u32 cr1, cr2;
490 u16 ctrl, status;
491 int evc_cnt;
492 int arb_table_pos;
493 int i, j;
494 static const char ref_clocks[][6] = { "100ns" };
495 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
496 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
497 char buf[8];
498
499 printf("Virtual Channel\n");
500 if (verbose < 2)
501 return;
502
503 if (!config_fetch(d, where + 4, 0x1c - 4))
504 return;
505
506 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
507 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
508 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
509 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
510
511 evc_cnt = BITS(cr1, 0, 3);
512 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
513 BITS(cr1, 4, 3),
514 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
515 1 << BITS(cr1, 10, 2));
516
517 printf("\t\tArb:");
518 for (i=0; i<8; i++)
519 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
520 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
521 arb_table_pos = BITS(cr2, 24, 8);
522
523 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
524 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
525
526 if (arb_table_pos)
527 {
528 arb_table_pos = where + 16*arb_table_pos;
529 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
530 }
531
532 for (i=0; i<=evc_cnt; i++)
533 {
534 int pos = where + PCI_VC_RES_CAP + 12*i;
535 u32 rcap, rctrl;
536 u16 rstatus;
537 int pat_pos;
538
539 printf("\t\tVC%d:\t", i);
540 if (!config_fetch(d, pos, 12))
541 {
542 printf("<unreadable>\n");
543 continue;
544 }
545 rcap = get_conf_long(d, pos);
546 rctrl = get_conf_long(d, pos+4);
547 rstatus = get_conf_word(d, pos+10);
548
549 pat_pos = BITS(rcap, 24, 8);
550 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
551 pat_pos,
552 BITS(rcap, 16, 7) + 1,
553 FLAG(rcap, 1 << 15));
554
555 printf("\t\t\tArb:");
556 for (j=0; j<8; j++)
557 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
558 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
559
560 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
561 FLAG(rctrl, 1 << 31),
562 BITS(rctrl, 24, 3),
563 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
564 BITS(rctrl, 0, 8));
565
566 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
567 FLAG(rstatus, 2),
568 FLAG(rstatus, 1));
569
570 if (pat_pos)
571 printf("\t\t\tPort Arbitration Table <?>\n");
572 }
573 }
574
575 static void
576 cap_rclink(struct device *d, int where)
577 {
578 u32 esd;
579 int num_links;
580 int i;
581 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
582 char buf[8];
583
584 printf("Root Complex Link\n");
585 if (verbose < 2)
586 return;
587
588 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
589 return;
590
591 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
592 num_links = BITS(esd, 8, 8);
593 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
594 BITS(esd, 24, 8),
595 BITS(esd, 16, 8),
596 TABLE(elt_types, BITS(esd, 0, 8), buf));
597
598 for (i=0; i<num_links; i++)
599 {
600 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
601 u32 desc;
602 u32 addr_lo, addr_hi;
603
604 printf("\t\tLink%d:\t", i);
605 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
606 {
607 printf("<unreadable>\n");
608 return;
609 }
610 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
611 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
612 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
613
614 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
615 BITS(desc, 24, 8),
616 BITS(desc, 16, 8),
617 FLAG(desc, 4),
618 ((desc & 2) ? "Config" : "MemMapped"),
619 FLAG(desc, 1));
620
621 if (desc & 2)
622 {
623 int n = addr_lo & 7;
624 if (!n)
625 n = 8;
626 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
627 BITS(addr_lo, 20, n),
628 BITS(addr_lo, 15, 5),
629 BITS(addr_lo, 12, 3),
630 addr_hi, addr_lo);
631 }
632 else
633 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
634 }
635 }
636
637 static void
638 cap_rcec(struct device *d, int where)
639 {
640 printf("Root Complex Event Collector Endpoint Association\n");
641 if (verbose < 2)
642 return;
643
644 if (!config_fetch(d, where, 12))
645 return;
646
647 u32 hdr = get_conf_long(d, where);
648 byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
649 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
650 printf("\t\tRCiEPBitmap: ");
651 if (bmap)
652 {
653 int prevmatched=0;
654 int adjcount=0;
655 int prevdev=0;
656 printf("RCiEP at Device(s):");
657 for (int dev=0; dev < 32; dev++)
658 {
659 if (BITS(bmap, dev, 1))
660 {
661 if (!adjcount)
662 printf("%s %u", (prevmatched) ? "," : "", dev);
663 adjcount++;
664 prevdev=dev;
665 prevmatched=1;
666 }
667 else
668 {
669 if (adjcount > 1)
670 printf("-%u", prevdev);
671 adjcount=0;
672 }
673 }
674 }
675 else
676 printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
677 printf("\n");
678
679 if (cap_ver < PCI_RCEC_BUSN_REG_VER)
680 return;
681
682 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
683 u8 lastbusn = BITS(busn, 16, 8);
684 u8 nextbusn = BITS(busn, 8, 8);
685
686 if ((lastbusn == 0x00) && (nextbusn == 0xff))
687 printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
688 else
689 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
690 }
691
692 static void
693 cxl_range(u64 base, u64 size, int n)
694 {
695 u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
696 const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
697 const char *class[] = { "DRAM", "Storage", "CDAT" };
698 u16 w;
699
700 w = (u16) size;
701
702 size &= ~0x0fffffffULL;
703
704 printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X" [size=0x%"PCI_U64_FMT_X"]\n", n, base, base + size - 1, size);
705 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
706 FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
707 type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
708 interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
709 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
710 }
711
712 static void
713 dvsec_cxl_device(struct device *d, int rev, int where, int len)
714 {
715 u32 cache_size, cache_unit_size;
716 u64 range_base, range_size;
717 u16 w;
718
719 if (len < 0x38)
720 return;
721
722 /* Legacy 1.1 revs aren't handled */
723 if (rev == 0)
724 return;
725
726 if (rev >= 1) {
727 w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
728 printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
729 FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
730 FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
731
732 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
733 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
734 FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
735 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
736 FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
737
738 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
739 printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
740
741 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
742 printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
743 FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
744 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
745 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
746 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
747 if (rev >= 2) {
748 printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
749 }
750 printf("\n");
751
752 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
753 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
754 FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
755
756 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
757 printf("\t\tCXLCap2:\t");
758 cache_unit_size = BITS(w, 0, 4);
759 cache_size = BITS(w, 8, 8);
760 switch (cache_unit_size)
761 {
762 case PCI_CXL_DEV_CAP2_CACHE_1M:
763 printf("Cache Size: %08x\n", cache_size * (1<<20));
764 break;
765 case PCI_CXL_DEV_CAP2_CACHE_64K:
766 printf("Cache Size: %08x\n", cache_size * (64<<10));
767 break;
768 case PCI_CXL_DEV_CAP2_CACHE_UNK:
769 printf("Cache Size Not Reported\n");
770 break;
771 default:
772 printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
773 break;
774 }
775
776 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
777 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
778 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
779 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
780 cxl_range(range_base, range_size, 1);
781
782 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
783 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
784 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
785 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
786 cxl_range(range_base, range_size, 2);
787 }
788
789 if (rev >= 2) {
790 w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
791 printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
792 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
793 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
794 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
795 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
796 }
797
798 // Unparsed data
799 if (len > PCI_CXL_DEV_LEN) {
800 printf("\t\t<?>\n");
801 }
802
803 }
804
805 static void
806 dvsec_cxl_port(struct device *d, int where, int len)
807 {
808 u16 w, m1, m2;
809 u8 b1, b2;
810
811 if (len < PCI_CXL_PORT_EXT_LEN)
812 return;
813
814 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
815 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
816
817 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
818 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
819 FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
820 FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
821 FLAG(w, PCI_CXL_PORT_VIRAL_EN));
822
823 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
824 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
825 printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
826 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
827 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
828 printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
829 }
830
831 static void
832 dvsec_cxl_register_locator(struct device *d, int where, int len)
833 {
834 static const char * const id_names[] = {
835 "empty",
836 "component registers",
837 "BAR virtualization",
838 "CXL device registers",
839 "CPMU registers",
840 };
841
842 for (int i=0; ; i++)
843 {
844 int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
845 if (pos + 7 >= where + len)
846 break;
847
848 u32 lo = get_conf_long(d, pos);
849 u32 hi = get_conf_long(d, pos + 4);
850
851 unsigned int bir = BITS(lo, 0, 3);
852 unsigned int block_id = BITS(lo, 8, 8);
853 u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
854
855 if (!block_id)
856 continue;
857
858 const char *id_name;
859 if (block_id < sizeof(id_names) / sizeof(*id_names))
860 id_name = id_names[block_id];
861 else if (block_id == 0xff)
862 id_name = "vendor-specific";
863 else
864 id_name = "<?>";
865
866 printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
867 }
868 }
869
870 static void
871 dvsec_cxl_gpf_device(struct device *d, int where)
872 {
873 u32 l;
874 u16 w, duration;
875 u8 time_base, time_scale;
876
877 w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
878 time_base = BITS(w, 0, 4);
879 time_scale = BITS(w, 8, 4);
880
881 switch (time_scale)
882 {
883 case PCI_CXL_GPF_DEV_100US:
884 case PCI_CXL_GPF_DEV_100MS:
885 duration = time_base * 100;
886 break;
887 case PCI_CXL_GPF_DEV_10US:
888 case PCI_CXL_GPF_DEV_10MS:
889 case PCI_CXL_GPF_DEV_10S:
890 duration = time_base * 10;
891 break;
892 case PCI_CXL_GPF_DEV_1US:
893 case PCI_CXL_GPF_DEV_1MS:
894 case PCI_CXL_GPF_DEV_1S:
895 duration = time_base;
896 break;
897 default:
898 /* Reserved */
899 printf("\t\tReserved time scale encoding %x\n", time_scale);
900 duration = time_base;
901 }
902
903 printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
904 (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
905 (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
906 (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
907
908 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
909 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
910 }
911
912 static void
913 dvsec_cxl_gpf_port(struct device *d, int where)
914 {
915 u16 w, timeout;
916 u8 time_base, time_scale;
917
918 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
919 time_base = BITS(w, 0, 4);
920 time_scale = BITS(w, 8, 4);
921
922 switch (time_scale)
923 {
924 case PCI_CXL_GPF_PORT_100US:
925 case PCI_CXL_GPF_PORT_100MS:
926 timeout = time_base * 100;
927 break;
928 case PCI_CXL_GPF_PORT_10US:
929 case PCI_CXL_GPF_PORT_10MS:
930 case PCI_CXL_GPF_PORT_10S:
931 timeout = time_base * 10;
932 break;
933 case PCI_CXL_GPF_PORT_1US:
934 case PCI_CXL_GPF_PORT_1MS:
935 case PCI_CXL_GPF_PORT_1S:
936 timeout = time_base;
937 break;
938 default:
939 /* Reserved */
940 printf("\t\tReserved time scale encoding %x\n", time_scale);
941 timeout = time_base;
942 }
943
944 printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
945 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
946 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
947 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
948
949 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
950 time_base = BITS(w, 0, 4);
951 time_scale = BITS(w, 8, 4);
952
953 switch (time_scale)
954 {
955 case PCI_CXL_GPF_PORT_100US:
956 case PCI_CXL_GPF_PORT_100MS:
957 timeout = time_base * 100;
958 break;
959 case PCI_CXL_GPF_PORT_10US:
960 case PCI_CXL_GPF_PORT_10MS:
961 case PCI_CXL_GPF_PORT_10S:
962 timeout = time_base * 10;
963 break;
964 case PCI_CXL_GPF_PORT_1US:
965 case PCI_CXL_GPF_PORT_1MS:
966 case PCI_CXL_GPF_PORT_1S:
967 timeout = time_base;
968 break;
969 default:
970 /* Reserved */
971 printf("\t\tReserved time scale encoding %x\n", time_scale);
972 timeout = time_base;
973 }
974
975 printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
976 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
977 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
978 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
979 }
980
981 static void
982 dvsec_cxl_flex_bus(struct device *d, int where, int rev, int len)
983 {
984 u16 w;
985 u32 l, data;
986
987 // Sanity check: Does the length correspond to its revision?
988 switch (rev) {
989 case 0:
990 if (len != PCI_CXL_FB_MOD_TS_DATA) {
991 printf("\t\t<Wrong length for Revision %d>\n", rev);
992 }
993 break;
994 case 1:
995 if (len != PCI_CXL_FB_PORT_CAP2) {
996 printf("\t\t<Wrong length for Revision %d>\n", rev);
997 }
998 break;
999 case 2:
1000 if (len != PCI_CXL_FB_NEXT_UNSUPPORTED) {
1001 printf("\t\t<Wrong length for Revision %d>\n", rev);
1002 }
1003 break;
1004 default:
1005 break;
1006 }
1007
1008 // From Rev 0
1009 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
1010 printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
1011 FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
1012 FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
1013 FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
1014
1015 if (rev > 1)
1016 printf(" 256BFlit%c PBRFlit%c",
1017 FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
1018
1019 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
1020 printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
1021 FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
1022 FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
1023 FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
1024 FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
1025 FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
1026
1027 if (rev > 1)
1028 printf(" 256BFlit%c PBRFlit%c",
1029 FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
1030
1031 w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
1032 printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
1033 FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
1034 FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
1035 FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
1036 FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
1037
1038 if (rev > 1)
1039 printf(" 256BFlit%c PBRFlit%c",
1040 FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
1041 printf("\n");
1042
1043 // From Rev 1
1044 if (rev >= 1)
1045 {
1046 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
1047 data = BITS(l, 0, 24);
1048 printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
1049 }
1050
1051 // From Rev 2
1052 if (rev >= 2)
1053 {
1054 u8 nop;
1055
1056 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
1057 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
1058
1059 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
1060 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
1061
1062 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
1063 nop = BITS(l, 0, 2);
1064 printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
1065 }
1066
1067 // Unparsed data
1068 if (len > PCI_CXL_FB_LEN) {
1069 printf("\t\t<?>\n");
1070 }
1071 }
1072
1073 static void
1074 dvsec_cxl_mld(struct device *d, int where)
1075 {
1076 u16 w;
1077
1078 w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
1079
1080 /* Encodings greater than 16 are reserved */
1081 if (w && w <= PCI_CXL_MLD_MAX_LD)
1082 printf("\t\tNumLogDevs: %d\n", w);
1083 }
1084
1085 static void
1086 dvsec_cxl_function_map(struct device *d, int where)
1087 {
1088
1089 printf("\t\tFuncMap 0: %08x\n",
1090 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
1091
1092 printf("\t\tFuncMap 1: %08x\n",
1093 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
1094
1095 printf("\t\tFuncMap 2: %08x\n",
1096 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
1097
1098 printf("\t\tFuncMap 3: %08x\n",
1099 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
1100
1101 printf("\t\tFuncMap 4: %08x\n",
1102 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
1103
1104 printf("\t\tFuncMap 5: %08x\n",
1105 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
1106
1107 printf("\t\tFuncMap 6: %08x\n",
1108 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
1109
1110 printf("\t\tFuncMap 7: %08x\n",
1111 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
1112 }
1113
1114 static void
1115 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
1116 {
1117 printf(": CXL\n");
1118 if (verbose < 2)
1119 return;
1120
1121 if (!config_fetch(d, where, len))
1122 return;
1123
1124 switch (id)
1125 {
1126 case 0:
1127 printf("\t\tPCIe DVSEC for CXL Devices\n");
1128 dvsec_cxl_device(d, rev, where, len);
1129 break;
1130 case 2:
1131 printf("\t\tNon-CXL Function Map DVSEC\n");
1132 dvsec_cxl_function_map(d, where);
1133 break;
1134 case 3:
1135 printf("\t\tCXL Extensions DVSEC for Ports\n");
1136 dvsec_cxl_port(d, where, len);
1137 break;
1138 case 4:
1139 printf("\t\tGPF DVSEC for CXL Ports\n");
1140 dvsec_cxl_gpf_port(d, where);
1141 break;
1142 case 5:
1143 printf("\t\tGPF DVSEC for CXL Devices\n");
1144 dvsec_cxl_gpf_device(d, where);
1145 break;
1146 case 7:
1147 printf("\t\tPCIe DVSEC for Flex Bus Port\n");
1148 dvsec_cxl_flex_bus(d, where, rev, len);
1149 break;
1150 case 8:
1151 printf("\t\tRegister Locator DVSEC\n");
1152 dvsec_cxl_register_locator(d, where, len);
1153 break;
1154 case 9:
1155 printf("\t\tMLD DVSEC\n");
1156 dvsec_cxl_mld(d, where);
1157 break;
1158 case 0xa:
1159 printf("\t\tPCIe DVSEC for Test Capability <?>\n");
1160 break;
1161 default:
1162 printf("\t\tUnknown ID %04x\n", id);
1163 }
1164 }
1165
1166 static void
1167 cap_dvsec(struct device *d, int where)
1168 {
1169 printf("Designated Vendor-Specific: ");
1170 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
1171 {
1172 printf("<unreadable>\n");
1173 return;
1174 }
1175
1176 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
1177 u16 vendor = BITS(hdr, 0, 16);
1178 byte rev = BITS(hdr, 16, 4);
1179 u16 len = BITS(hdr, 20, 12);
1180
1181 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
1182
1183 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
1184 if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
1185 cap_dvsec_cxl(d, id, rev, where, len);
1186 else
1187 printf(" <?>\n");
1188 }
1189
1190 static void
1191 cap_evendor(struct device *d, int where)
1192 {
1193 u32 hdr;
1194
1195 printf("Vendor Specific Information: ");
1196 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
1197 {
1198 printf("<unreadable>\n");
1199 return;
1200 }
1201
1202 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
1203 printf("ID=%04x Rev=%d Len=%03x <?>\n",
1204 BITS(hdr, 0, 16),
1205 BITS(hdr, 16, 4),
1206 BITS(hdr, 20, 12));
1207 }
1208
1209 static int l1pm_calc_pwron(int scale, int value)
1210 {
1211 switch (scale)
1212 {
1213 case 0:
1214 return 2 * value;
1215 case 1:
1216 return 10 * value;
1217 case 2:
1218 return 100 * value;
1219 }
1220 return -1;
1221 }
1222
1223 static void
1224 cap_l1pm(struct device *d, int where)
1225 {
1226 u32 l1_cap, val, scale;
1227 int time;
1228
1229 printf("L1 PM Substates\n");
1230
1231 if (verbose < 2)
1232 return;
1233
1234 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
1235 {
1236 printf("\t\t<unreadable>\n");
1237 return;
1238 }
1239
1240 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
1241 printf("\t\tL1SubCap: ");
1242 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
1243 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
1244 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
1245 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
1246 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
1247 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
1248
1249 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1250 {
1251 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
1252 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
1253 if (time != -1)
1254 printf("PortTPowerOnTime=%dus\n", time);
1255 else
1256 printf("PortTPowerOnTime=<error>\n");
1257 }
1258
1259 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
1260 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
1261 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
1262 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
1263 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
1264 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
1265
1266 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1267 {
1268 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
1269
1270 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1271 {
1272 scale = BITS(val, 29, 3);
1273 if (scale > 5)
1274 printf(" LTR1.2_Threshold=<error>");
1275 else
1276 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale));
1277 }
1278 printf("\n");
1279 }
1280
1281 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
1282 printf("\t\tL1SubCtl2:");
1283 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1284 {
1285 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
1286 if (time != -1)
1287 printf(" T_PwrOn=%dus", time);
1288 else
1289 printf(" T_PwrOn=<error>");
1290 }
1291 printf("\n");
1292 }
1293
1294 static void
1295 cap_ptm(struct device *d, int where)
1296 {
1297 u32 buff;
1298 u16 clock;
1299
1300 printf("Precision Time Measurement\n");
1301
1302 if (verbose < 2)
1303 return;
1304
1305 if (!config_fetch(d, where + 4, 8))
1306 {
1307 printf("\t\t<unreadable>\n");
1308 return;
1309 }
1310
1311 buff = get_conf_long(d, where + 4);
1312 printf("\t\tPTMCap: ");
1313 printf("Requester:%c Responder:%c Root:%c\n",
1314 FLAG(buff, 0x1),
1315 FLAG(buff, 0x2),
1316 FLAG(buff, 0x4));
1317
1318 clock = BITS(buff, 8, 8);
1319 printf("\t\tPTMClockGranularity: ");
1320 switch (clock)
1321 {
1322 case 0x00:
1323 printf("Unimplemented\n");
1324 break;
1325 case 0xff:
1326 printf("Greater than 254ns\n");
1327 break;
1328 default:
1329 printf("%huns\n", clock);
1330 }
1331
1332 buff = get_conf_long(d, where + 8);
1333 printf("\t\tPTMControl: ");
1334 printf("Enabled:%c RootSelected:%c\n",
1335 FLAG(buff, 0x1),
1336 FLAG(buff, 0x2));
1337
1338 clock = BITS(buff, 8, 8);
1339 printf("\t\tPTMEffectiveGranularity: ");
1340 switch (clock)
1341 {
1342 case 0x00:
1343 printf("Unknown\n");
1344 break;
1345 case 0xff:
1346 printf("Greater than 254ns\n");
1347 break;
1348 default:
1349 printf("%huns\n", clock);
1350 }
1351 }
1352
1353 static void
1354 print_rebar_range_size(int ld2_size)
1355 {
1356 // This function prints the input as a power-of-2 size value
1357 // It is biased with 1MB = 0, ...
1358 // Maximum resizable BAR value supported is 2^63 bytes = 43
1359 // for the extended resizable BAR capability definition
1360 // (otherwise it would stop at 2^28)
1361
1362 if (ld2_size >= 0 && ld2_size < 10)
1363 printf(" %dMB", (1 << ld2_size));
1364 else if (ld2_size >= 10 && ld2_size < 20)
1365 printf(" %dGB", (1 << (ld2_size-10)));
1366 else if (ld2_size >= 20 && ld2_size < 30)
1367 printf(" %dTB", (1 << (ld2_size-20)));
1368 else if (ld2_size >= 30 && ld2_size < 40)
1369 printf(" %dPB", (1 << (ld2_size-30)));
1370 else if (ld2_size >= 40 && ld2_size < 44)
1371 printf(" %dEB", (1 << (ld2_size-40)));
1372 else
1373 printf(" <unknown>");
1374 }
1375
1376 static void
1377 cap_rebar(struct device *d, int where, int virtual)
1378 {
1379 u32 sizes_buffer, control_buffer, ext_sizes, current_size;
1380 u16 bar_index, barcount, i;
1381 // If the structure exists, at least one bar is defined
1382 u16 num_bars = 1;
1383
1384 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1385
1386 if (verbose < 2)
1387 return;
1388
1389 // Go through all defined BAR definitions of the caps, at minimum 1
1390 // (loop also terminates if num_bars read from caps is > 6)
1391 for (barcount = 0; barcount < num_bars; barcount++)
1392 {
1393 where += 4;
1394
1395 // Get the next BAR configuration
1396 if (!config_fetch(d, where, 8))
1397 {
1398 printf("\t\t<unreadable>\n");
1399 return;
1400 }
1401
1402 sizes_buffer = get_conf_long(d, where) >> 4;
1403 where += 4;
1404 control_buffer = get_conf_long(d, where);
1405
1406 bar_index = BITS(control_buffer, 0, 3);
1407 current_size = BITS(control_buffer, 8, 6);
1408 ext_sizes = BITS(control_buffer, 16, 16);
1409
1410 if (barcount == 0)
1411 {
1412 // Only index 0 controlreg has the num_bar count definition
1413 num_bars = BITS(control_buffer, 5, 3);
1414 if (num_bars < 1 || num_bars > 6)
1415 {
1416 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars);
1417 break;
1418 }
1419 }
1420
1421 // Resizable BAR list entry have an arbitrary index and current size
1422 printf("\t\tBAR %d: current size:", bar_index);
1423 print_rebar_range_size(current_size);
1424
1425 if (sizes_buffer || ext_sizes)
1426 {
1427 printf(", supported:");
1428
1429 for (i=0; i<28; i++)
1430 if (sizes_buffer & (1U << i))
1431 print_rebar_range_size(i);
1432
1433 for (i=0; i<16; i++)
1434 if (ext_sizes & (1U << i))
1435 print_rebar_range_size(i + 28);
1436 }
1437
1438 printf("\n");
1439 }
1440 }
1441
1442 static void
1443 cap_doe(struct device *d, int where)
1444 {
1445 u32 l;
1446
1447 printf("Data Object Exchange\n");
1448
1449 if (verbose < 2)
1450 return;
1451
1452 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
1453 {
1454 printf("\t\t<unreadable>\n");
1455 return;
1456 }
1457
1458 l = get_conf_long(d, where + PCI_DOE_CAP);
1459 printf("\t\tDOECap: IntSup%c\n",
1460 FLAG(l, PCI_DOE_CAP_INT_SUPP));
1461 if (l & PCI_DOE_CAP_INT_SUPP)
1462 printf("\t\t\tInterrupt Message Number %03x\n",
1463 PCI_DOE_CAP_INT_MSG(l));
1464
1465 l = get_conf_long(d, where + PCI_DOE_CTL);
1466 printf("\t\tDOECtl: IntEn%c\n",
1467 FLAG(l, PCI_DOE_CTL_INT));
1468
1469 l = get_conf_long(d, where + PCI_DOE_STS);
1470 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1471 FLAG(l, PCI_DOE_STS_BUSY),
1472 FLAG(l, PCI_DOE_STS_INT),
1473 FLAG(l, PCI_DOE_STS_ERROR),
1474 FLAG(l, PCI_DOE_STS_OBJECT_READY));
1475 }
1476
1477 void
1478 show_ext_caps(struct device *d, int type)
1479 {
1480 int where = 0x100;
1481 char been_there[0x1000];
1482 memset(been_there, 0, 0x1000);
1483 do
1484 {
1485 u32 header;
1486 int id, version;
1487
1488 if (!config_fetch(d, where, 4))
1489 break;
1490 header = get_conf_long(d, where);
1491 if (!header || header == 0xffffffff)
1492 break;
1493 id = header & 0xffff;
1494 version = (header >> 16) & 0xf;
1495 printf("\tCapabilities: [%03x", where);
1496 if (verbose > 1)
1497 printf(" v%d", version);
1498 printf("] ");
1499 if (been_there[where]++)
1500 {
1501 printf("<chain looped>\n");
1502 break;
1503 }
1504 switch (id)
1505 {
1506 case PCI_EXT_CAP_ID_NULL:
1507 printf("Null\n");
1508 break;
1509 case PCI_EXT_CAP_ID_AER:
1510 cap_aer(d, where, type);
1511 break;
1512 case PCI_EXT_CAP_ID_DPC:
1513 cap_dpc(d, where);
1514 break;
1515 case PCI_EXT_CAP_ID_VC:
1516 case PCI_EXT_CAP_ID_VC2:
1517 cap_vc(d, where);
1518 break;
1519 case PCI_EXT_CAP_ID_DSN:
1520 cap_dsn(d, where);
1521 break;
1522 case PCI_EXT_CAP_ID_PB:
1523 printf("Power Budgeting <?>\n");
1524 break;
1525 case PCI_EXT_CAP_ID_RCLINK:
1526 cap_rclink(d, where);
1527 break;
1528 case PCI_EXT_CAP_ID_RCILINK:
1529 printf("Root Complex Internal Link <?>\n");
1530 break;
1531 case PCI_EXT_CAP_ID_RCEC:
1532 cap_rcec(d, where);
1533 break;
1534 case PCI_EXT_CAP_ID_MFVC:
1535 printf("Multi-Function Virtual Channel <?>\n");
1536 break;
1537 case PCI_EXT_CAP_ID_RCRB:
1538 printf("Root Complex Register Block <?>\n");
1539 break;
1540 case PCI_EXT_CAP_ID_VNDR:
1541 cap_evendor(d, where);
1542 break;
1543 case PCI_EXT_CAP_ID_ACS:
1544 cap_acs(d, where);
1545 break;
1546 case PCI_EXT_CAP_ID_ARI:
1547 cap_ari(d, where);
1548 break;
1549 case PCI_EXT_CAP_ID_ATS:
1550 cap_ats(d, where);
1551 break;
1552 case PCI_EXT_CAP_ID_SRIOV:
1553 cap_sriov(d, where);
1554 break;
1555 case PCI_EXT_CAP_ID_MRIOV:
1556 printf("Multi-Root I/O Virtualization <?>\n");
1557 break;
1558 case PCI_EXT_CAP_ID_MCAST:
1559 cap_multicast(d, where, type);
1560 break;
1561 case PCI_EXT_CAP_ID_PRI:
1562 cap_pri(d, where);
1563 break;
1564 case PCI_EXT_CAP_ID_REBAR:
1565 cap_rebar(d, where, 0);
1566 break;
1567 case PCI_EXT_CAP_ID_DPA:
1568 printf("Dynamic Power Allocation <?>\n");
1569 break;
1570 case PCI_EXT_CAP_ID_TPH:
1571 cap_tph(d, where);
1572 break;
1573 case PCI_EXT_CAP_ID_LTR:
1574 cap_ltr(d, where);
1575 break;
1576 case PCI_EXT_CAP_ID_SECPCI:
1577 cap_sec(d, where);
1578 break;
1579 case PCI_EXT_CAP_ID_PMUX:
1580 printf("Protocol Multiplexing <?>\n");
1581 break;
1582 case PCI_EXT_CAP_ID_PASID:
1583 cap_pasid(d, where);
1584 break;
1585 case PCI_EXT_CAP_ID_LNR:
1586 printf("LN Requester <?>\n");
1587 break;
1588 case PCI_EXT_CAP_ID_L1PM:
1589 cap_l1pm(d, where);
1590 break;
1591 case PCI_EXT_CAP_ID_PTM:
1592 cap_ptm(d, where);
1593 break;
1594 case PCI_EXT_CAP_ID_M_PCIE:
1595 printf("PCI Express over M_PHY <?>\n");
1596 break;
1597 case PCI_EXT_CAP_ID_FRS:
1598 printf("FRS Queueing <?>\n");
1599 break;
1600 case PCI_EXT_CAP_ID_RTR:
1601 printf("Readiness Time Reporting <?>\n");
1602 break;
1603 case PCI_EXT_CAP_ID_DVSEC:
1604 cap_dvsec(d, where);
1605 break;
1606 case PCI_EXT_CAP_ID_VF_REBAR:
1607 cap_rebar(d, where, 1);
1608 break;
1609 case PCI_EXT_CAP_ID_DLNK:
1610 printf("Data Link Feature <?>\n");
1611 break;
1612 case PCI_EXT_CAP_ID_16GT:
1613 printf("Physical Layer 16.0 GT/s <?>\n");
1614 break;
1615 case PCI_EXT_CAP_ID_LMR:
1616 printf("Lane Margining at the Receiver <?>\n");
1617 break;
1618 case PCI_EXT_CAP_ID_HIER_ID:
1619 printf("Hierarchy ID <?>\n");
1620 break;
1621 case PCI_EXT_CAP_ID_NPEM:
1622 printf("Native PCIe Enclosure Management <?>\n");
1623 break;
1624 case PCI_EXT_CAP_ID_DOE:
1625 cap_doe(d, where);
1626 break;
1627 default:
1628 printf("Extended Capability ID %#02x\n", id);
1629 break;
1630 }
1631 where = (header >> 20) & ~3;
1632 } while (where);
1633 }
Unnamed repository; edit this file 'description' to name the repository.