ls-ecaps.c

   1 /*
   2  *      The PCI Utilities -- Show Extended Capabilities
   3  *
   4  *      Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_tph(struct device *d, int where)
  16 {
  17   u32 tph_cap;
  18   printf("Transaction Processing Hints\n");
  19   if (verbose < 2)
  20     return;
  21
  22   if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
  23     return;
  24
  25   tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
  26
  27   if (tph_cap & PCI_TPH_INTVEC_SUP)
  28     printf("\t\tInterrupt vector mode supported\n");
  29   if (tph_cap & PCI_TPH_DEV_SUP)
  30     printf("\t\tDevice specific mode supported\n");
  31   if (tph_cap & PCI_TPH_EXT_REQ_SUP)
  32     printf("\t\tExtended requester support\n");
  33
  34   switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
  35   case PCI_TPH_ST_NONE:
  36     printf("\t\tNo steering table available\n");
  37     break;
  38   case PCI_TPH_ST_CAP:
  39     printf("\t\tSteering table in TPH capability structure\n");
  40     break;
  41   case PCI_TPH_ST_MSIX:
  42     printf("\t\tSteering table in MSI-X table\n");
  43     break;
  44   default:
  45     printf("\t\tReserved steering table location\n");
  46     break;
  47   }
  48 }
  49
  50 static u32
  51 cap_ltr_scale(u8 scale)
  52 {
  53   return 1 << (scale * 5);
  54 }
  55
  56 static void
  57 cap_ltr(struct device *d, int where)
  58 {
  59   u32 scale;
  60   u16 snoop, nosnoop;
  61   printf("Latency Tolerance Reporting\n");
  62   if (verbose < 2)
  63     return;
  64
  65   if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
  66     return;
  67
  68   snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
  69   scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  70   printf("\t\tMax snoop latency: %lldns\n",
  71          ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
  72
  73   nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
  74   scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  75   printf("\t\tMax no snoop latency: %lldns\n",
  76          ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
  77 }
  78
  79 static void
  80 cap_dsn(struct device *d, int where)
  81 {
  82   u32 t1, t2;
  83   if (!config_fetch(d, where + 4, 8))
  84     return;
  85   t1 = get_conf_long(d, where + 4);
  86   t2 = get_conf_long(d, where + 8);
  87   printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
  88         t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
  89         t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
  90 }
  91
  92 static void
  93 cap_aer(struct device *d, int where, int type)
  94 {
  95   u32 l, l0, l1, l2, l3;
  96   u16 w;
  97
  98   printf("Advanced Error Reporting\n");
  99   if (verbose < 2)
 100     return;
 101
 102   if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
 103     return;
 104
 105   l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
 106   printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 107         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 108         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 109         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 110         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 111         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 112   l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
 113   printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 114         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 115         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 116         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 117         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 118         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 119   l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
 120   printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 121         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 122         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 123         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 124         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 125         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 126   l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
 127   printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 128         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 129         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 130   l = get_conf_long(d, where + PCI_ERR_COR_MASK);
 131   printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 132         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 133         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 134   l = get_conf_long(d, where + PCI_ERR_CAP);
 135   printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
 136         "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
 137         PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
 138         FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
 139         FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
 140         FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
 141
 142   l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
 143   l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
 144   l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
 145   l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
 146   printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
 147
 148   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
 149     {
 150       if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
 151         return;
 152
 153       l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
 154       printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
 155             FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
 156             FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
 157             FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
 158
 159       l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
 160       printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
 161             "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
 162             FLAG(l, PCI_ERR_ROOT_COR_RCV),
 163             FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
 164             FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
 165             FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
 166             FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
 167             FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
 168             FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
 169             PCI_ERR_MSG_NUM(l));
 170
 171       w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
 172       printf("\t\tErrorSrc: ERR_COR: %04x ", w);
 173
 174       w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
 175       printf("ERR_FATAL/NONFATAL: %04x\n", w);
 176     }
 177 }
 178
 179 static void cap_dpc(struct device *d, int where)
 180 {
 181   u16 l;
 182
 183   printf("Downstream Port Containment\n");
 184   if (verbose < 2)
 185     return;
 186
 187   if (!config_fetch(d, where + PCI_DPC_CAP, 8))
 188     return;
 189
 190   l = get_conf_word(d, where + PCI_DPC_CAP);
 191   printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 192     PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
 193     FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
 194
 195   l = get_conf_word(d, where + PCI_DPC_CTL);
 196   printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
 197     PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
 198     FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
 199     FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
 200
 201   l = get_conf_word(d, where + PCI_DPC_STATUS);
 202   printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
 203     FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
 204     FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
 205
 206   l = get_conf_word(d, where + PCI_DPC_SOURCE);
 207   printf("\t\tSource:\t%04x\n", l);
 208 }
 209
 210 static void
 211 cap_acs(struct device *d, int where)
 212 {
 213   u16 w;
 214
 215   printf("Access Control Services\n");
 216   if (verbose < 2)
 217     return;
 218
 219   if (!config_fetch(d, where + PCI_ACS_CAP, 4))
 220     return;
 221
 222   w = get_conf_word(d, where + PCI_ACS_CAP);
 223   printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 224         "DirectTrans%c\n",
 225         FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
 226         FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
 227         FLAG(w, PCI_ACS_CAP_TRANS));
 228   w = get_conf_word(d, where + PCI_ACS_CTRL);
 229   printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 230         "DirectTrans%c\n",
 231         FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
 232         FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
 233         FLAG(w, PCI_ACS_CTRL_TRANS));
 234 }
 235
 236 static void
 237 cap_ari(struct device *d, int where)
 238 {
 239   u16 w;
 240
 241   printf("Alternative Routing-ID Interpretation (ARI)\n");
 242   if (verbose < 2)
 243     return;
 244
 245   if (!config_fetch(d, where + PCI_ARI_CAP, 4))
 246     return;
 247
 248   w = get_conf_word(d, where + PCI_ARI_CAP);
 249   printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
 250         FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
 251         PCI_ARI_CAP_NFN(w));
 252   w = get_conf_word(d, where + PCI_ARI_CTRL);
 253   printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
 254         FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
 255         PCI_ARI_CTRL_FG(w));
 256 }
 257
 258 static void
 259 cap_ats(struct device *d, int where)
 260 {
 261   u16 w;
 262
 263   printf("Address Translation Service (ATS)\n");
 264   if (verbose < 2)
 265     return;
 266
 267   if (!config_fetch(d, where + PCI_ATS_CAP, 4))
 268     return;
 269
 270   w = get_conf_word(d, where + PCI_ATS_CAP);
 271   printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
 272   w = get_conf_word(d, where + PCI_ATS_CTRL);
 273   printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
 274         FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
 275 }
 276
 277 static void
 278 cap_pri(struct device *d, int where)
 279 {
 280   u16 w;
 281   u32 l;
 282
 283   printf("Page Request Interface (PRI)\n");
 284   if (verbose < 2)
 285     return;
 286
 287   if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
 288     return;
 289
 290   w = get_conf_word(d, where + PCI_PRI_CTRL);
 291   printf("\t\tPRICtl: Enable%c Reset%c\n",
 292         FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
 293   w = get_conf_word(d, where + PCI_PRI_STATUS);
 294   printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
 295         FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
 296         FLAG(w, PCI_PRI_STATUS_STOPPED));
 297   l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
 298   printf("\t\tPage Request Capacity: %08x, ", l);
 299   l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
 300   printf("Page Request Allocation: %08x\n", l);
 301 }
 302
 303 static void
 304 cap_pasid(struct device *d, int where)
 305 {
 306   u16 w;
 307
 308   printf("Process Address Space ID (PASID)\n");
 309   if (verbose < 2)
 310     return;
 311
 312   if (!config_fetch(d, where + PCI_PASID_CAP, 4))
 313     return;
 314
 315   w = get_conf_word(d, where + PCI_PASID_CAP);
 316   printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
 317         FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
 318         PCI_PASID_CAP_WIDTH(w));
 319   w = get_conf_word(d, where + PCI_PASID_CTRL);
 320   printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
 321         FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
 322         FLAG(w, PCI_PASID_CTRL_PRIV));
 323 }
 324
 325 static void
 326 cap_sriov(struct device *d, int where)
 327 {
 328   u16 b;
 329   u16 w;
 330   u32 l;
 331   int i;
 332
 333   printf("Single Root I/O Virtualization (SR-IOV)\n");
 334   if (verbose < 2)
 335     return;
 336
 337   if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
 338     return;
 339
 340   l = get_conf_long(d, where + PCI_IOV_CAP);
 341   printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
 342         FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
 343   w = get_conf_word(d, where + PCI_IOV_CTRL);
 344   printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
 345         FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
 346         FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
 347         FLAG(w, PCI_IOV_CTRL_ARI));
 348   w = get_conf_word(d, where + PCI_IOV_STATUS);
 349   printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
 350   w = get_conf_word(d, where + PCI_IOV_INITIALVF);
 351   printf("\t\tInitial VFs: %d, ", w);
 352   w = get_conf_word(d, where + PCI_IOV_TOTALVF);
 353   printf("Total VFs: %d, ", w);
 354   w = get_conf_word(d, where + PCI_IOV_NUMVF);
 355   printf("Number of VFs: %d, ", w);
 356   b = get_conf_byte(d, where + PCI_IOV_FDL);
 357   printf("Function Dependency Link: %02x\n", b);
 358   w = get_conf_word(d, where + PCI_IOV_OFFSET);
 359   printf("\t\tVF offset: %d, ", w);
 360   w = get_conf_word(d, where + PCI_IOV_STRIDE);
 361   printf("stride: %d, ", w);
 362   w = get_conf_word(d, where + PCI_IOV_DID);
 363   printf("Device ID: %04x\n", w);
 364   l = get_conf_long(d, where + PCI_IOV_SUPPS);
 365   printf("\t\tSupported Page Size: %08x, ", l);
 366   l = get_conf_long(d, where + PCI_IOV_SYSPS);
 367   printf("System Page Size: %08x\n", l);
 368
 369   for (i=0; i < PCI_IOV_NUM_BAR; i++)
 370     {
 371       u32 addr;
 372       int type;
 373       u32 h;
 374       l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
 375       if (l == 0xffffffff)
 376         l = 0;
 377       if (!l)
 378         continue;
 379       printf("\t\tRegion %d: Memory at ", i);
 380       addr = l & PCI_ADDR_MEM_MASK;
 381       type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 382       if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
 383         {
 384           i++;
 385           h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
 386           printf("%08x", h);
 387         }
 388       printf("%08x (%s-bit, %sprefetchable)\n",
 389         addr,
 390         (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
 391         (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
 392     }
 393
 394   l = get_conf_long(d, where + PCI_IOV_MSAO);
 395   printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
 396         PCI_IOV_MSA_BIR(l));
 397 }
 398
 399 static void
 400 cap_multicast(struct device *d, int where, int type)
 401 {
 402   u16 w;
 403   u32 l;
 404   u64 bar, rcv, block;
 405
 406   printf("Multicast\n");
 407   if (verbose < 2)
 408     return;
 409
 410   if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
 411     return;
 412
 413   w = get_conf_word(d, where + PCI_MCAST_CAP);
 414   printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
 415   if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
 416     printf(", WindowSz %d (%d bytes)",
 417       PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
 418   if (type == PCI_EXP_TYPE_ROOT_PORT ||
 419       type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
 420     printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
 421   w = get_conf_word(d, where + PCI_MCAST_CTRL);
 422   printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
 423     PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
 424   bar = get_conf_long(d, where + PCI_MCAST_BAR);
 425   l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
 426   bar |= (u64) l << 32;
 427   printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
 428     PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
 429   rcv = get_conf_long(d, where + PCI_MCAST_RCV);
 430   l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
 431   rcv |= (u64) l << 32;
 432   printf("\t\tMcastReceiveVec:      %016" PCI_U64_FMT_X "\n", rcv);
 433   block = get_conf_long(d, where + PCI_MCAST_BLOCK);
 434   l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
 435   block |= (u64) l << 32;
 436   printf("\t\tMcastBlockAllVec:     %016" PCI_U64_FMT_X "\n", block);
 437   block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
 438   l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
 439   block |= (u64) l << 32;
 440   printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
 441
 442   if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
 443     return;
 444   bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
 445   l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
 446   bar |= (u64) l << 32;
 447   printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
 448   if (PCI_MCAST_OVL_SIZE(bar) >= 6)
 449     printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
 450   else
 451     printf("(disabled)");
 452   printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
 453 }
 454
 455 static void
 456 cap_vc(struct device *d, int where)
 457 {
 458   u32 cr1, cr2;
 459   u16 ctrl, status;
 460   int evc_cnt;
 461   int arb_table_pos;
 462   int i, j;
 463   static const char ref_clocks[][6] = { "100ns" };
 464   static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
 465   static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
 466   char buf[8];
 467
 468   printf("Virtual Channel\n");
 469   if (verbose < 2)
 470     return;
 471
 472   if (!config_fetch(d, where + 4, 0x1c - 4))
 473     return;
 474
 475   cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
 476   cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
 477   ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
 478   status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
 479
 480   evc_cnt = BITS(cr1, 0, 3);
 481   printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
 482     BITS(cr1, 4, 3),
 483     TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
 484     1 << BITS(cr1, 10, 2));
 485
 486   printf("\t\tArb:");
 487   for (i=0; i<8; i++)
 488     if (arb_selects[i][0] != '?' || cr2 & (1 << i))
 489       printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
 490   arb_table_pos = BITS(cr2, 24, 8);
 491
 492   printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
 493   printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
 494
 495   if (arb_table_pos)
 496     {
 497       arb_table_pos = where + 16*arb_table_pos;
 498       printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
 499     }
 500
 501   for (i=0; i<=evc_cnt; i++)
 502     {
 503       int pos = where + PCI_VC_RES_CAP + 12*i;
 504       u32 rcap, rctrl;
 505       u16 rstatus;
 506       int pat_pos;
 507
 508       printf("\t\tVC%d:\t", i);
 509       if (!config_fetch(d, pos, 12))
 510         {
 511           printf("<unreadable>\n");
 512           continue;
 513         }
 514       rcap = get_conf_long(d, pos);
 515       rctrl = get_conf_long(d, pos+4);
 516       rstatus = get_conf_word(d, pos+10);
 517
 518       pat_pos = BITS(rcap, 24, 8);
 519       printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
 520         pat_pos,
 521         BITS(rcap, 16, 6) + 1,
 522         FLAG(rcap, 1 << 15));
 523
 524       printf("\t\t\tArb:");
 525       for (j=0; j<8; j++)
 526         if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
 527           printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
 528
 529       printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
 530         FLAG(rctrl, 1 << 31),
 531         BITS(rctrl, 24, 3),
 532         TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
 533         BITS(rctrl, 0, 8));
 534
 535       printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
 536         FLAG(rstatus, 2),
 537         FLAG(rstatus, 1));
 538
 539       if (pat_pos)
 540         printf("\t\t\tPort Arbitration Table <?>\n");
 541     }
 542 }
 543
 544 static void
 545 cap_rclink(struct device *d, int where)
 546 {
 547   u32 esd;
 548   int num_links;
 549   int i;
 550   static const char elt_types[][9] = { "Config", "Egress", "Internal" };
 551   char buf[8];
 552
 553   printf("Root Complex Link\n");
 554   if (verbose < 2)
 555     return;
 556
 557   if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
 558     return;
 559
 560   esd = get_conf_long(d, where + PCI_RCLINK_ESD);
 561   num_links = BITS(esd, 8, 8);
 562   printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
 563     BITS(esd, 24, 8),
 564     BITS(esd, 16, 8),
 565     TABLE(elt_types, BITS(esd, 0, 8), buf));
 566
 567   for (i=0; i<num_links; i++)
 568     {
 569       int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
 570       u32 desc;
 571       u32 addr_lo, addr_hi;
 572
 573       printf("\t\tLink%d:\t", i);
 574       if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
 575         {
 576           printf("<unreadable>\n");
 577           return;
 578         }
 579       desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
 580       addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
 581       addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
 582
 583       printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
 584         BITS(desc, 24, 8),
 585         BITS(desc, 16, 8),
 586         FLAG(desc, 4),
 587         ((desc & 2) ? "Config" : "MemMapped"),
 588         FLAG(desc, 1));
 589
 590       if (desc & 2)
 591         {
 592           int n = addr_lo & 7;
 593           if (!n)
 594             n = 8;
 595           printf("\t\t\tAddr:\t%02x:%02x.%d  CfgSpace=%08x%08x\n",
 596             BITS(addr_lo, 20, n),
 597             BITS(addr_lo, 15, 5),
 598             BITS(addr_lo, 12, 3),
 599             addr_hi, addr_lo);
 600         }
 601       else
 602         printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
 603     }
 604 }
 605
 606 static void
 607 cap_evendor(struct device *d, int where)
 608 {
 609   u32 hdr;
 610
 611   printf("Vendor Specific Information: ");
 612   if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
 613     {
 614       printf("<unreadable>\n");
 615       return;
 616     }
 617
 618   hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
 619   printf("ID=%04x Rev=%d Len=%03x <?>\n",
 620     BITS(hdr, 0, 16),
 621     BITS(hdr, 16, 4),
 622     BITS(hdr, 20, 12));
 623 }
 624
 625 static int l1pm_calc_pwron(int scale, int value)
 626 {
 627   switch (scale)
 628     {
 629       case 0:
 630         return 2 * value;
 631       case 1:
 632         return 10 * value;
 633       case 2:
 634         return 100 * value;
 635     }
 636   return -1;
 637 }
 638
 639 static void
 640 cap_l1pm(struct device *d, int where)
 641 {
 642   u32 l1_cap, val, scale;
 643   int time;
 644
 645   printf("L1 PM Substates\n");
 646
 647   if (verbose < 2)
 648     return;
 649
 650   if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
 651     {
 652       printf("\t\t<unreadable>\n");
 653       return;
 654     }
 655
 656   l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
 657   printf("\t\tL1SubCap: ");
 658   printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
 659     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
 660     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
 661     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
 662     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
 663     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
 664
 665   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 666     {
 667       printf("\t\t\t  PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
 668       time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
 669       if (time != -1)
 670         printf("PortTPowerOnTime=%dus\n", time);
 671       else
 672         printf("PortTPowerOnTime=<error>\n");
 673     }
 674
 675   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
 676   printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
 677     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
 678     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
 679     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
 680     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
 681
 682   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 683     printf("\t\t\t   T_CommonMode=%dus", BITS(val, 8, 8));
 684
 685   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 686     {
 687       scale = BITS(val, 29, 3);
 688       if (scale > 5)
 689         printf(" LTR1.2_Threshold=<error>");
 690       else
 691         printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
 692     }
 693   printf("\n");
 694
 695   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
 696   printf("\t\tL1SubCtl2:");
 697   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 698     {
 699       time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
 700       if (time != -1)
 701         printf(" T_PwrOn=%dus", time);
 702       else
 703         printf(" T_PwrOn=<error>");
 704     }
 705   printf("\n");
 706 }
 707
 708 static void
 709 cap_ptm(struct device *d, int where)
 710 {
 711   u32 buff;
 712   u16 clock;
 713
 714   printf("Precision Time Measurement\n");
 715
 716   if (verbose < 2)
 717     return;
 718
 719   if (!config_fetch(d, where + 4, 8))
 720     {
 721       printf("\t\t<unreadable>\n");
 722       return;
 723     }
 724
 725   buff = get_conf_long(d, where + 4);
 726   printf("\t\tPTMCap: ");
 727   printf("Requester:%c Responder:%c Root:%c\n",
 728     FLAG(buff, 0x1),
 729     FLAG(buff, 0x2),
 730     FLAG(buff, 0x4));
 731
 732   clock = BITS(buff, 8, 8);
 733   printf("\t\tPTMClockGranularity: ");
 734   switch (clock)
 735     {
 736       case 0x00:
 737         printf("Unimplemented\n");
 738         break;
 739       case 0xff:
 740         printf("Greater than 254ns\n");
 741         break;
 742       default:
 743         printf("%huns\n", clock);
 744     }
 745
 746   buff = get_conf_long(d, where + 8);
 747   printf("\t\tPTMControl: ");
 748   printf("Enabled:%c RootSelected:%c\n",
 749     FLAG(buff, 0x1),
 750     FLAG(buff, 0x2));
 751
 752   clock = BITS(buff, 8, 8);
 753   printf("\t\tPTMEffectiveGranularity: ");
 754   switch (clock)
 755     {
 756       case 0x00:
 757         printf("Unknown\n");
 758         break;
 759       case 0xff:
 760         printf("Greater than 254ns\n");
 761         break;
 762       default:
 763         printf("%huns\n", clock);
 764     }
 765 }
 766
 767 void
 768 show_ext_caps(struct device *d, int type)
 769 {
 770   int where = 0x100;
 771   char been_there[0x1000];
 772   memset(been_there, 0, 0x1000);
 773   do
 774     {
 775       u32 header;
 776       int id, version;
 777
 778       if (!config_fetch(d, where, 4))
 779         break;
 780       header = get_conf_long(d, where);
 781       if (!header)
 782         break;
 783       id = header & 0xffff;
 784       version = (header >> 16) & 0xf;
 785       printf("\tCapabilities: [%03x", where);
 786       if (verbose > 1)
 787         printf(" v%d", version);
 788       printf("] ");
 789       if (been_there[where]++)
 790         {
 791           printf("<chain looped>\n");
 792           break;
 793         }
 794       switch (id)
 795         {
 796           case PCI_EXT_CAP_ID_NULL:
 797             printf("Null\n");
 798             break;
 799           case PCI_EXT_CAP_ID_AER:
 800             cap_aer(d, where, type);
 801             break;
 802           case PCI_EXT_CAP_ID_DPC:
 803             cap_dpc(d, where);
 804             break;
 805           case PCI_EXT_CAP_ID_VC:
 806           case PCI_EXT_CAP_ID_VC2:
 807             cap_vc(d, where);
 808             break;
 809           case PCI_EXT_CAP_ID_DSN:
 810             cap_dsn(d, where);
 811             break;
 812           case PCI_EXT_CAP_ID_PB:
 813             printf("Power Budgeting <?>\n");
 814             break;
 815           case PCI_EXT_CAP_ID_RCLINK:
 816             cap_rclink(d, where);
 817             break;
 818           case PCI_EXT_CAP_ID_RCILINK:
 819             printf("Root Complex Internal Link <?>\n");
 820             break;
 821           case PCI_EXT_CAP_ID_RCECOLL:
 822             printf("Root Complex Event Collector <?>\n");
 823             break;
 824           case PCI_EXT_CAP_ID_MFVC:
 825             printf("Multi-Function Virtual Channel <?>\n");
 826             break;
 827           case PCI_EXT_CAP_ID_RCRB:
 828             printf("Root Complex Register Block <?>\n");
 829             break;
 830           case PCI_EXT_CAP_ID_VNDR:
 831             cap_evendor(d, where);
 832             break;
 833           case PCI_EXT_CAP_ID_ACS:
 834             cap_acs(d, where);
 835             break;
 836           case PCI_EXT_CAP_ID_ARI:
 837             cap_ari(d, where);
 838             break;
 839           case PCI_EXT_CAP_ID_ATS:
 840             cap_ats(d, where);
 841             break;
 842           case PCI_EXT_CAP_ID_SRIOV:
 843             cap_sriov(d, where);
 844             break;
 845           case PCI_EXT_CAP_ID_MRIOV:
 846             printf("Multi-Root I/O Virtualization <?>\n");
 847             break;
 848           case PCI_EXT_CAP_ID_MCAST:
 849             cap_multicast(d, where, type);
 850             break;
 851           case PCI_EXT_CAP_ID_PRI:
 852             cap_pri(d, where);
 853             break;
 854           case PCI_EXT_CAP_ID_REBAR:
 855             printf("Resizable BAR <?>\n");
 856             break;
 857           case PCI_EXT_CAP_ID_DPA:
 858             printf("Dynamic Power Allocation <?>\n");
 859             break;
 860           case PCI_EXT_CAP_ID_TPH:
 861             cap_tph(d, where);
 862             break;
 863           case PCI_EXT_CAP_ID_LTR:
 864             cap_ltr(d, where);
 865             break;
 866           case PCI_EXT_CAP_ID_SECPCI:
 867             printf("Secondary PCI Express <?>\n");
 868             break;
 869           case PCI_EXT_CAP_ID_PMUX:
 870             printf("Protocol Multiplexing <?>\n");
 871             break;
 872           case PCI_EXT_CAP_ID_PASID:
 873             cap_pasid(d, where);
 874             break;
 875           case PCI_EXT_CAP_ID_LNR:
 876             printf("LN Requester <?>\n");
 877             break;
 878           case PCI_EXT_CAP_ID_L1PM:
 879             cap_l1pm(d, where);
 880             break;
 881           case PCI_EXT_CAP_ID_PTM:
 882             cap_ptm(d, where);
 883             break;
 884           case PCI_EXT_CAP_ID_M_PCIE:
 885             printf("PCI Express over M_PHY <?>\n");
 886             break;
 887           case PCI_EXT_CAP_ID_FRS:
 888             printf("FRS Queueing <?>\n");
 889             break;
 890           case PCI_EXT_CAP_ID_RTR:
 891             printf("Readiness Time Reporting <?>\n");
 892             break;
 893           case PCI_EXT_CAP_ID_DVSEC:
 894             printf("Designated Vendor-Specific <?>\n");
 895             break;
 896           case PCI_EXT_CAP_ID_VF_REBAR:
 897             printf("VF Resizable BAR <?>\n");
 898             break;
 899           case PCI_EXT_CAP_ID_DLNK:
 900             printf("Data Link Feature <?>\n");
 901             break;
 902           case PCI_EXT_CAP_ID_16GT:
 903             printf("Physical Layer 16.0 GT/s <?>\n");
 904             break;
 905           case PCI_EXT_CAP_ID_LMR:
 906             printf("Lane Margining at the Receiver <?>\n");
 907             break;
 908           case PCI_EXT_CAP_ID_HIER_ID:
 909             printf("Hierarchy ID <?>\n");
 910             break;
 911           case PCI_EXT_CAP_ID_NPEM:
 912             printf("Native PCIe Enclosure Management <?>\n");
 913             break;
 914           default:
 915             printf("Extended Capability ID %#02x\n", id);
 916             break;
 917         }
 918       where = (header >> 20) & ~3;
 919     } while (where);
 920 }