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[thirdparty/pciutils.git] / ls-ecaps.c
1 /*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
4 * Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11
12 #include "lspci.h"
13
14 static void
15 cap_tph(struct device *d, int where)
16 {
17 u32 tph_cap;
18 printf("Transaction Processing Hints\n");
19 if (verbose < 2)
20 return;
21
22 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
23 return;
24
25 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
26
27 if (tph_cap & PCI_TPH_INTVEC_SUP)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap & PCI_TPH_DEV_SUP)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
32 printf("\t\tExtended requester support\n");
33
34 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
35 case PCI_TPH_ST_NONE:
36 printf("\t\tNo steering table available\n");
37 break;
38 case PCI_TPH_ST_CAP:
39 printf("\t\tSteering table in TPH capability structure\n");
40 break;
41 case PCI_TPH_ST_MSIX:
42 printf("\t\tSteering table in MSI-X table\n");
43 break;
44 default:
45 printf("\t\tReserved steering table location\n");
46 break;
47 }
48 }
49
50 static u32
51 cap_ltr_scale(u8 scale)
52 {
53 return 1 << (scale * 5);
54 }
55
56 static void
57 cap_ltr(struct device *d, int where)
58 {
59 u32 scale;
60 u16 snoop, nosnoop;
61 printf("Latency Tolerance Reporting\n");
62 if (verbose < 2)
63 return;
64
65 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
66 return;
67
68 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
69 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
70 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
71 ((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
72
73 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
74 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
75 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
76 ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
77 }
78
79 static void
80 cap_sec(struct device *d, int where)
81 {
82 u32 ctrl3, lane_err_stat;
83 u8 lane;
84 printf("Secondary PCI Express\n");
85 if (verbose < 2)
86 return;
87
88 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
89 return;
90
91 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
92 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
93 FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
94 FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
95
96 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
97 printf("\t\tLaneErrStat: ");
98 if (lane_err_stat)
99 {
100 printf("LaneErr at lane:");
101 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
102 if (BITS(lane_err_stat, 0, 1))
103 printf(" %u", lane);
104 }
105 else
106 printf("0");
107 printf("\n");
108 }
109
110 static void
111 cap_dsn(struct device *d, int where)
112 {
113 u32 t1, t2;
114 if (!config_fetch(d, where + 4, 8))
115 return;
116 t1 = get_conf_long(d, where + 4);
117 t2 = get_conf_long(d, where + 8);
118 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
119 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
120 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
121 }
122
123 static void
124 cap_aer(struct device *d, int where, int type)
125 {
126 u32 l, l0, l1, l2, l3;
127 u16 w;
128
129 printf("Advanced Error Reporting\n");
130 if (verbose < 2)
131 return;
132
133 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
134 return;
135
136 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
137 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
138 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
139 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
140 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
141 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
142 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
143 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
144 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
145 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
146 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
147 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
148 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
149 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
150 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
151 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
152 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
153 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
154 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
155 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
156 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
157 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
158 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
159 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
160 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
161 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
162 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
163 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
164 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
165 l = get_conf_long(d, where + PCI_ERR_CAP);
166 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
167 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
168 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
169 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
170 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
171 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
172
173 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
174 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
175 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
176 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
177 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
178
179 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
180 {
181 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
182 return;
183
184 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
185 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
186 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
187 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
188 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
189
190 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
191 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
192 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
193 FLAG(l, PCI_ERR_ROOT_COR_RCV),
194 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
195 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
196 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
197 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
198 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
199 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
200 PCI_ERR_MSG_NUM(l));
201
202 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
203 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
204
205 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
206 printf("ERR_FATAL/NONFATAL: %04x\n", w);
207 }
208 }
209
210 static void cap_dpc(struct device *d, int where)
211 {
212 u16 l;
213
214 printf("Downstream Port Containment\n");
215 if (verbose < 2)
216 return;
217
218 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
219 return;
220
221 l = get_conf_word(d, where + PCI_DPC_CAP);
222 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
223 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
224 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
225
226 l = get_conf_word(d, where + PCI_DPC_CTL);
227 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
228 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
229 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
230 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
231
232 l = get_conf_word(d, where + PCI_DPC_STATUS);
233 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
234 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
235 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
236
237 l = get_conf_word(d, where + PCI_DPC_SOURCE);
238 printf("\t\tSource:\t%04x\n", l);
239 }
240
241 static void
242 cap_acs(struct device *d, int where)
243 {
244 u16 w;
245
246 printf("Access Control Services\n");
247 if (verbose < 2)
248 return;
249
250 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
251 return;
252
253 w = get_conf_word(d, where + PCI_ACS_CAP);
254 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
255 "DirectTrans%c\n",
256 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
257 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
258 FLAG(w, PCI_ACS_CAP_TRANS));
259 w = get_conf_word(d, where + PCI_ACS_CTRL);
260 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
261 "DirectTrans%c\n",
262 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
263 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
264 FLAG(w, PCI_ACS_CTRL_TRANS));
265 }
266
267 static void
268 cap_ari(struct device *d, int where)
269 {
270 u16 w;
271
272 printf("Alternative Routing-ID Interpretation (ARI)\n");
273 if (verbose < 2)
274 return;
275
276 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
277 return;
278
279 w = get_conf_word(d, where + PCI_ARI_CAP);
280 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
281 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
282 PCI_ARI_CAP_NFN(w));
283 w = get_conf_word(d, where + PCI_ARI_CTRL);
284 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
285 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
286 PCI_ARI_CTRL_FG(w));
287 }
288
289 static void
290 cap_ats(struct device *d, int where)
291 {
292 u16 w;
293
294 printf("Address Translation Service (ATS)\n");
295 if (verbose < 2)
296 return;
297
298 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
299 return;
300
301 w = get_conf_word(d, where + PCI_ATS_CAP);
302 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
303 w = get_conf_word(d, where + PCI_ATS_CTRL);
304 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
305 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
306 }
307
308 static void
309 cap_pri(struct device *d, int where)
310 {
311 u16 w;
312 u32 l;
313
314 printf("Page Request Interface (PRI)\n");
315 if (verbose < 2)
316 return;
317
318 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
319 return;
320
321 w = get_conf_word(d, where + PCI_PRI_CTRL);
322 printf("\t\tPRICtl: Enable%c Reset%c\n",
323 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
324 w = get_conf_word(d, where + PCI_PRI_STATUS);
325 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
326 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
327 FLAG(w, PCI_PRI_STATUS_STOPPED));
328 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
329 printf("\t\tPage Request Capacity: %08x, ", l);
330 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
331 printf("Page Request Allocation: %08x\n", l);
332 }
333
334 static void
335 cap_pasid(struct device *d, int where)
336 {
337 u16 w;
338
339 printf("Process Address Space ID (PASID)\n");
340 if (verbose < 2)
341 return;
342
343 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
344 return;
345
346 w = get_conf_word(d, where + PCI_PASID_CAP);
347 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
348 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
349 PCI_PASID_CAP_WIDTH(w));
350 w = get_conf_word(d, where + PCI_PASID_CTRL);
351 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
352 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
353 FLAG(w, PCI_PASID_CTRL_PRIV));
354 }
355
356 static void
357 cap_sriov(struct device *d, int where)
358 {
359 u16 b;
360 u16 w;
361 u32 l;
362 int i;
363
364 printf("Single Root I/O Virtualization (SR-IOV)\n");
365 if (verbose < 2)
366 return;
367
368 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
369 return;
370
371 l = get_conf_long(d, where + PCI_IOV_CAP);
372 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
373 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
374 w = get_conf_word(d, where + PCI_IOV_CTRL);
375 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
376 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
377 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
378 FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
379 w = get_conf_word(d, where + PCI_IOV_STATUS);
380 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
381 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
382 printf("\t\tInitial VFs: %d, ", w);
383 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
384 printf("Total VFs: %d, ", w);
385 w = get_conf_word(d, where + PCI_IOV_NUMVF);
386 printf("Number of VFs: %d, ", w);
387 b = get_conf_byte(d, where + PCI_IOV_FDL);
388 printf("Function Dependency Link: %02x\n", b);
389 w = get_conf_word(d, where + PCI_IOV_OFFSET);
390 printf("\t\tVF offset: %d, ", w);
391 w = get_conf_word(d, where + PCI_IOV_STRIDE);
392 printf("stride: %d, ", w);
393 w = get_conf_word(d, where + PCI_IOV_DID);
394 printf("Device ID: %04x\n", w);
395 l = get_conf_long(d, where + PCI_IOV_SUPPS);
396 printf("\t\tSupported Page Size: %08x, ", l);
397 l = get_conf_long(d, where + PCI_IOV_SYSPS);
398 printf("System Page Size: %08x\n", l);
399
400 for (i=0; i < PCI_IOV_NUM_BAR; i++)
401 {
402 u32 addr;
403 int type;
404 u32 h;
405 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
406 if (l == 0xffffffff)
407 l = 0;
408 if (!l)
409 continue;
410 printf("\t\tRegion %d: Memory at ", i);
411 addr = l & PCI_ADDR_MEM_MASK;
412 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
413 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
414 {
415 i++;
416 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
417 printf("%08x", h);
418 }
419 printf("%08x (%s-bit, %sprefetchable)\n",
420 addr,
421 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
422 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
423 }
424
425 l = get_conf_long(d, where + PCI_IOV_MSAO);
426 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
427 PCI_IOV_MSA_BIR(l));
428 }
429
430 static void
431 cap_multicast(struct device *d, int where, int type)
432 {
433 u16 w;
434 u32 l;
435 u64 bar, rcv, block;
436
437 printf("Multicast\n");
438 if (verbose < 2)
439 return;
440
441 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
442 return;
443
444 w = get_conf_word(d, where + PCI_MCAST_CAP);
445 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
446 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
447 printf(", WindowSz %d (%d bytes)",
448 PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
449 if (type == PCI_EXP_TYPE_ROOT_PORT ||
450 type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
451 printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
452 w = get_conf_word(d, where + PCI_MCAST_CTRL);
453 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
454 PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
455 bar = get_conf_long(d, where + PCI_MCAST_BAR);
456 l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
457 bar |= (u64) l << 32;
458 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
459 PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
460 rcv = get_conf_long(d, where + PCI_MCAST_RCV);
461 l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
462 rcv |= (u64) l << 32;
463 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
464 block = get_conf_long(d, where + PCI_MCAST_BLOCK);
465 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
466 block |= (u64) l << 32;
467 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
468 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
469 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
470 block |= (u64) l << 32;
471 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
472
473 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
474 return;
475 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
476 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
477 bar |= (u64) l << 32;
478 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
479 if (PCI_MCAST_OVL_SIZE(bar) >= 6)
480 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
481 else
482 printf("(disabled)");
483 printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
484 }
485
486 static void
487 cap_vc(struct device *d, int where)
488 {
489 u32 cr1, cr2;
490 u16 ctrl, status;
491 int evc_cnt;
492 int arb_table_pos;
493 int i, j;
494 static const char ref_clocks[][6] = { "100ns" };
495 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
496 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
497 char buf[8];
498
499 printf("Virtual Channel\n");
500 if (verbose < 2)
501 return;
502
503 if (!config_fetch(d, where + 4, 0x1c - 4))
504 return;
505
506 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
507 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
508 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
509 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
510
511 evc_cnt = BITS(cr1, 0, 3);
512 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
513 BITS(cr1, 4, 3),
514 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
515 1 << BITS(cr1, 10, 2));
516
517 printf("\t\tArb:");
518 for (i=0; i<8; i++)
519 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
520 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
521 arb_table_pos = BITS(cr2, 24, 8);
522
523 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
524 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
525
526 if (arb_table_pos)
527 {
528 arb_table_pos = where + 16*arb_table_pos;
529 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
530 }
531
532 for (i=0; i<=evc_cnt; i++)
533 {
534 int pos = where + PCI_VC_RES_CAP + 12*i;
535 u32 rcap, rctrl;
536 u16 rstatus;
537 int pat_pos;
538
539 printf("\t\tVC%d:\t", i);
540 if (!config_fetch(d, pos, 12))
541 {
542 printf("<unreadable>\n");
543 continue;
544 }
545 rcap = get_conf_long(d, pos);
546 rctrl = get_conf_long(d, pos+4);
547 rstatus = get_conf_word(d, pos+10);
548
549 pat_pos = BITS(rcap, 24, 8);
550 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
551 pat_pos,
552 BITS(rcap, 16, 6) + 1,
553 FLAG(rcap, 1 << 15));
554
555 printf("\t\t\tArb:");
556 for (j=0; j<8; j++)
557 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
558 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
559
560 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
561 FLAG(rctrl, 1 << 31),
562 BITS(rctrl, 24, 3),
563 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
564 BITS(rctrl, 0, 8));
565
566 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
567 FLAG(rstatus, 2),
568 FLAG(rstatus, 1));
569
570 if (pat_pos)
571 printf("\t\t\tPort Arbitration Table <?>\n");
572 }
573 }
574
575 static void
576 cap_rclink(struct device *d, int where)
577 {
578 u32 esd;
579 int num_links;
580 int i;
581 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
582 char buf[8];
583
584 printf("Root Complex Link\n");
585 if (verbose < 2)
586 return;
587
588 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
589 return;
590
591 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
592 num_links = BITS(esd, 8, 8);
593 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
594 BITS(esd, 24, 8),
595 BITS(esd, 16, 8),
596 TABLE(elt_types, BITS(esd, 0, 8), buf));
597
598 for (i=0; i<num_links; i++)
599 {
600 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
601 u32 desc;
602 u32 addr_lo, addr_hi;
603
604 printf("\t\tLink%d:\t", i);
605 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
606 {
607 printf("<unreadable>\n");
608 return;
609 }
610 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
611 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
612 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
613
614 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
615 BITS(desc, 24, 8),
616 BITS(desc, 16, 8),
617 FLAG(desc, 4),
618 ((desc & 2) ? "Config" : "MemMapped"),
619 FLAG(desc, 1));
620
621 if (desc & 2)
622 {
623 int n = addr_lo & 7;
624 if (!n)
625 n = 8;
626 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
627 BITS(addr_lo, 20, n),
628 BITS(addr_lo, 15, 5),
629 BITS(addr_lo, 12, 3),
630 addr_hi, addr_lo);
631 }
632 else
633 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
634 }
635 }
636
637 static void
638 cap_rcec(struct device *d, int where)
639 {
640 printf("Root Complex Event Collector Endpoint Association\n");
641 if (verbose < 2)
642 return;
643
644 if (!config_fetch(d, where, 12))
645 return;
646
647 u32 hdr = get_conf_long(d, where);
648 byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
649 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
650 printf("\t\tRCiEPBitmap: ");
651 if (bmap)
652 {
653 int prevmatched=0;
654 int adjcount=0;
655 int prevdev=0;
656 printf("RCiEP at Device(s):");
657 for (int dev=0; dev < 32; dev++)
658 {
659 if (BITS(bmap, dev, 1))
660 {
661 if (!adjcount)
662 printf("%s %u", (prevmatched) ? "," : "", dev);
663 adjcount++;
664 prevdev=dev;
665 prevmatched=1;
666 }
667 else
668 {
669 if (adjcount > 1)
670 printf("-%u", prevdev);
671 adjcount=0;
672 }
673 }
674 }
675 else
676 printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
677 printf("\n");
678
679 if (cap_ver < PCI_RCEC_BUSN_REG_VER)
680 return;
681
682 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
683 u8 lastbusn = BITS(busn, 16, 8);
684 u8 nextbusn = BITS(busn, 8, 8);
685
686 if ((lastbusn == 0x00) && (nextbusn == 0xff))
687 printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
688 else
689 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
690 }
691
692 static void
693 cxl_range(u64 base, u64 size, int n)
694 {
695 u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
696 const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
697 const char *class[] = { "DRAM", "Storage", "CDAT" };
698 u16 w;
699
700 w = (u16) size;
701
702 size &= ~0x0fffffffULL;
703
704 printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X"\n", n, base, base + size - 1);
705 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
706 FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
707 type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
708 interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
709 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
710 }
711
712 static void
713 dvsec_cxl_device(struct device *d, int where, int rev)
714 {
715 u32 cache_size, cache_unit_size, l;
716 u64 range_base, range_size;
717 u16 w;
718
719 /* Legacy 1.1 revs aren't handled */
720 if (rev < 1)
721 return;
722
723 w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
724 printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
725 FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
726 FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
727
728 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
729 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
730 FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
731 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
732 FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
733
734 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
735 printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
736
737 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
738 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
739 FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
740
741 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
742 cache_unit_size = BITS(w, 0, 4);
743 cache_size = BITS(w, 8, 8);
744 switch (cache_unit_size)
745 {
746 case PCI_CXL_DEV_CAP2_CACHE_1M:
747 printf("\t\tCache Size: %08x\n", cache_size * (1<<20));
748 break;
749 case PCI_CXL_DEV_CAP2_CACHE_64K:
750 printf("\t\tCache Size: %08x\n", cache_size * (64<<10));
751 break;
752 case PCI_CXL_DEV_CAP2_CACHE_UNK:
753 printf("\t\tCache Size Not Reported\n");
754 break;
755 default:
756 printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
757 break;
758 }
759
760 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI);
761 range_size = (u64) l << 32;
762 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
763 range_size |= l;
764 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI);
765 range_base = (u64) l << 32;
766 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
767 range_base |= l;
768 cxl_range(range_base, range_size, 1);
769
770 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI);
771 range_size = (u64) l << 32;
772 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
773 range_size |= l;
774 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI);
775 range_base = (u64) l << 32;
776 l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
777 range_base |= l;
778 cxl_range(range_base, range_size, 2);
779 }
780
781 static void
782 dvsec_cxl_port(struct device *d, int where)
783 {
784 u16 w, m1, m2;
785 u8 b1, b2;
786
787 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
788 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
789
790 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
791 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
792 FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
793 FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
794 FLAG(w, PCI_CXL_PORT_VIRAL_EN));
795
796 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
797 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
798 printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
799 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
800 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
801 printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
802 }
803
804 static const char *id[] = {
805 "empty",
806 "component registers",
807 "BAR virtualization",
808 "CXL device registers"};
809
810 static inline void
811 dvsec_decode_block(uint32_t lo, uint32_t hi, char which)
812 {
813 u64 base_hi = hi, base_lo;
814 u8 bir, block_id;
815
816 bir = BITS(lo, 0, 3);
817 block_id = BITS(lo, 8, 8);
818 base_lo = BITS(lo, 16, 16);
819
820 if (!block_id)
821 return;
822
823 printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]);
824 printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16);
825 }
826
827 static void
828 dvsec_cxl_register_locator(struct device *d, int where, int len)
829 {
830 int i, j;
831
832 for (i = 0xc, j = 1; i < len; i += 8, j++) {
833 dvsec_decode_block(get_conf_long(d, where + i), get_conf_long(d, where + i + 4), j + 0x31);
834 }
835 }
836
837 static void
838 cap_dvsec_cxl(struct device *d, int id, int where)
839 {
840 u16 len;
841 u8 rev;
842
843 printf(": CXL\n");
844 if (verbose < 2)
845 return;
846
847 rev = BITS(get_conf_byte(d, where + 0x6), 0, 4);
848
849 switch (id) {
850 case 0:
851 if (!config_fetch(d, where, PCI_CXL_DEV_LEN))
852 return;
853
854 dvsec_cxl_device(d, where, rev);
855 break;
856 case 3:
857 if (!config_fetch(d, where, PCI_CXL_PORT_EXT_LEN))
858 return;
859
860 dvsec_cxl_port(d, where);
861 break;
862 case 8:
863 len = BITS(get_conf_word(d, where + 0x6), 4, 12);
864 if (!config_fetch(d, where, len))
865 return;
866
867 dvsec_cxl_register_locator(d, where, len);
868 break;
869 case 2:
870 printf("\t\tNon-CXL Function Map DVSEC\n");
871 break;
872 case 4:
873 printf("\t\tGPF DVSEC for Port\n");
874 break;
875 case 5:
876 printf("\t\tGPF DVSEC for Device\n");
877 break;
878 case 7:
879 printf("\t\tPCIe DVSEC Flex Bus Port\n");
880 break;
881 case 9:
882 printf("\t\tMLD DVSEC\n");
883 break;
884 default:
885 break;
886 }
887 }
888
889 static void
890 cap_dvsec(struct device *d, int where)
891 {
892 printf("Designated Vendor-Specific: ");
893 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
894 {
895 printf("<unreadable>\n");
896 return;
897 }
898
899 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
900 u16 vendor = BITS(hdr, 0, 16);
901 byte rev = BITS(hdr, 16, 4);
902 u16 len = BITS(hdr, 20, 12);
903
904 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
905
906 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
907 if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
908 cap_dvsec_cxl(d, id, where);
909 else
910 printf(" <?>\n");
911 }
912
913 static void
914 cap_evendor(struct device *d, int where)
915 {
916 u32 hdr;
917
918 printf("Vendor Specific Information: ");
919 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
920 {
921 printf("<unreadable>\n");
922 return;
923 }
924
925 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
926 printf("ID=%04x Rev=%d Len=%03x <?>\n",
927 BITS(hdr, 0, 16),
928 BITS(hdr, 16, 4),
929 BITS(hdr, 20, 12));
930 }
931
932 static int l1pm_calc_pwron(int scale, int value)
933 {
934 switch (scale)
935 {
936 case 0:
937 return 2 * value;
938 case 1:
939 return 10 * value;
940 case 2:
941 return 100 * value;
942 }
943 return -1;
944 }
945
946 static void
947 cap_l1pm(struct device *d, int where)
948 {
949 u32 l1_cap, val, scale;
950 int time;
951
952 printf("L1 PM Substates\n");
953
954 if (verbose < 2)
955 return;
956
957 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
958 {
959 printf("\t\t<unreadable>\n");
960 return;
961 }
962
963 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
964 printf("\t\tL1SubCap: ");
965 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
966 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
967 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
968 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
969 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
970 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
971
972 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
973 {
974 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
975 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
976 if (time != -1)
977 printf("PortTPowerOnTime=%dus\n", time);
978 else
979 printf("PortTPowerOnTime=<error>\n");
980 }
981
982 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
983 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
984 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
985 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
986 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
987 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
988
989 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
990 {
991 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
992
993 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
994 {
995 scale = BITS(val, 29, 3);
996 if (scale > 5)
997 printf(" LTR1.2_Threshold=<error>");
998 else
999 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale));
1000 }
1001 printf("\n");
1002 }
1003
1004 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
1005 printf("\t\tL1SubCtl2:");
1006 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1007 {
1008 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
1009 if (time != -1)
1010 printf(" T_PwrOn=%dus", time);
1011 else
1012 printf(" T_PwrOn=<error>");
1013 }
1014 printf("\n");
1015 }
1016
1017 static void
1018 cap_ptm(struct device *d, int where)
1019 {
1020 u32 buff;
1021 u16 clock;
1022
1023 printf("Precision Time Measurement\n");
1024
1025 if (verbose < 2)
1026 return;
1027
1028 if (!config_fetch(d, where + 4, 8))
1029 {
1030 printf("\t\t<unreadable>\n");
1031 return;
1032 }
1033
1034 buff = get_conf_long(d, where + 4);
1035 printf("\t\tPTMCap: ");
1036 printf("Requester:%c Responder:%c Root:%c\n",
1037 FLAG(buff, 0x1),
1038 FLAG(buff, 0x2),
1039 FLAG(buff, 0x4));
1040
1041 clock = BITS(buff, 8, 8);
1042 printf("\t\tPTMClockGranularity: ");
1043 switch (clock)
1044 {
1045 case 0x00:
1046 printf("Unimplemented\n");
1047 break;
1048 case 0xff:
1049 printf("Greater than 254ns\n");
1050 break;
1051 default:
1052 printf("%huns\n", clock);
1053 }
1054
1055 buff = get_conf_long(d, where + 8);
1056 printf("\t\tPTMControl: ");
1057 printf("Enabled:%c RootSelected:%c\n",
1058 FLAG(buff, 0x1),
1059 FLAG(buff, 0x2));
1060
1061 clock = BITS(buff, 8, 8);
1062 printf("\t\tPTMEffectiveGranularity: ");
1063 switch (clock)
1064 {
1065 case 0x00:
1066 printf("Unknown\n");
1067 break;
1068 case 0xff:
1069 printf("Greater than 254ns\n");
1070 break;
1071 default:
1072 printf("%huns\n", clock);
1073 }
1074 }
1075
1076 static void
1077 print_rebar_range_size(int ld2_size)
1078 {
1079 // This function prints the input as a power-of-2 size value
1080 // It is biased with 1MB = 0, ...
1081 // Maximum resizable BAR value supported is 2^63 bytes = 43
1082 // for the extended resizable BAR capability definition
1083 // (otherwise it would stop at 2^28)
1084
1085 if (ld2_size >= 0 && ld2_size < 10)
1086 printf(" %dMB", (1 << ld2_size));
1087 else if (ld2_size >= 10 && ld2_size < 20)
1088 printf(" %dGB", (1 << (ld2_size-10)));
1089 else if (ld2_size >= 20 && ld2_size < 30)
1090 printf(" %dTB", (1 << (ld2_size-20)));
1091 else if (ld2_size >= 30 && ld2_size < 40)
1092 printf(" %dPB", (1 << (ld2_size-30)));
1093 else if (ld2_size >= 40 && ld2_size < 44)
1094 printf(" %dEB", (1 << (ld2_size-40)));
1095 else
1096 printf(" <unknown>");
1097 }
1098
1099 static void
1100 cap_rebar(struct device *d, int where, int virtual)
1101 {
1102 u32 sizes_buffer, control_buffer, ext_sizes, current_size;
1103 u16 bar_index, barcount, i;
1104 // If the structure exists, at least one bar is defined
1105 u16 num_bars = 1;
1106
1107 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1108
1109 if (verbose < 2)
1110 return;
1111
1112 // Go through all defined BAR definitions of the caps, at minimum 1
1113 // (loop also terminates if num_bars read from caps is > 6)
1114 for (barcount = 0; barcount < num_bars; barcount++)
1115 {
1116 where += 4;
1117
1118 // Get the next BAR configuration
1119 if (!config_fetch(d, where, 8))
1120 {
1121 printf("\t\t<unreadable>\n");
1122 return;
1123 }
1124
1125 sizes_buffer = get_conf_long(d, where) >> 4;
1126 where += 4;
1127 control_buffer = get_conf_long(d, where);
1128
1129 bar_index = BITS(control_buffer, 0, 3);
1130 current_size = BITS(control_buffer, 8, 6);
1131 ext_sizes = BITS(control_buffer, 16, 16);
1132
1133 if (barcount == 0)
1134 {
1135 // Only index 0 controlreg has the num_bar count definition
1136 num_bars = BITS(control_buffer, 5, 3);
1137 if (num_bars < 1 || num_bars > 6)
1138 {
1139 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars);
1140 break;
1141 }
1142 }
1143
1144 // Resizable BAR list entry have an arbitrary index and current size
1145 printf("\t\tBAR %d: current size:", bar_index);
1146 print_rebar_range_size(current_size);
1147
1148 if (sizes_buffer || ext_sizes)
1149 {
1150 printf(", supported:");
1151
1152 for (i=0; i<28; i++)
1153 if (sizes_buffer & (1U << i))
1154 print_rebar_range_size(i);
1155
1156 for (i=0; i<16; i++)
1157 if (ext_sizes & (1U << i))
1158 print_rebar_range_size(i + 28);
1159 }
1160
1161 printf("\n");
1162 }
1163 }
1164
1165 static void
1166 cap_doe(struct device *d, int where)
1167 {
1168 u32 l;
1169
1170 printf("Data Object Exchange\n");
1171
1172 if (verbose < 2)
1173 return;
1174
1175 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
1176 {
1177 printf("\t\t<unreadable>\n");
1178 return;
1179 }
1180
1181 l = get_conf_long(d, where + PCI_DOE_CAP);
1182 printf("\t\tDOECap: IntSup%c\n",
1183 FLAG(l, PCI_DOE_CAP_INT_SUPP));
1184 if (l & PCI_DOE_CAP_INT_SUPP)
1185 printf("\t\t\tInterrupt Message Number %03x\n",
1186 PCI_DOE_CAP_INT_MSG(l));
1187
1188 l = get_conf_long(d, where + PCI_DOE_CTL);
1189 printf("\t\tDOECtl: IntEn%c\n",
1190 FLAG(l, PCI_DOE_CTL_INT));
1191
1192 l = get_conf_long(d, where + PCI_DOE_STS);
1193 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1194 FLAG(l, PCI_DOE_STS_BUSY),
1195 FLAG(l, PCI_DOE_STS_INT),
1196 FLAG(l, PCI_DOE_STS_ERROR),
1197 FLAG(l, PCI_DOE_STS_OBJECT_READY));
1198 }
1199
1200 void
1201 show_ext_caps(struct device *d, int type)
1202 {
1203 int where = 0x100;
1204 char been_there[0x1000];
1205 memset(been_there, 0, 0x1000);
1206 do
1207 {
1208 u32 header;
1209 int id, version;
1210
1211 if (!config_fetch(d, where, 4))
1212 break;
1213 header = get_conf_long(d, where);
1214 if (!header || header == 0xffffffff)
1215 break;
1216 id = header & 0xffff;
1217 version = (header >> 16) & 0xf;
1218 printf("\tCapabilities: [%03x", where);
1219 if (verbose > 1)
1220 printf(" v%d", version);
1221 printf("] ");
1222 if (been_there[where]++)
1223 {
1224 printf("<chain looped>\n");
1225 break;
1226 }
1227 switch (id)
1228 {
1229 case PCI_EXT_CAP_ID_NULL:
1230 printf("Null\n");
1231 break;
1232 case PCI_EXT_CAP_ID_AER:
1233 cap_aer(d, where, type);
1234 break;
1235 case PCI_EXT_CAP_ID_DPC:
1236 cap_dpc(d, where);
1237 break;
1238 case PCI_EXT_CAP_ID_VC:
1239 case PCI_EXT_CAP_ID_VC2:
1240 cap_vc(d, where);
1241 break;
1242 case PCI_EXT_CAP_ID_DSN:
1243 cap_dsn(d, where);
1244 break;
1245 case PCI_EXT_CAP_ID_PB:
1246 printf("Power Budgeting <?>\n");
1247 break;
1248 case PCI_EXT_CAP_ID_RCLINK:
1249 cap_rclink(d, where);
1250 break;
1251 case PCI_EXT_CAP_ID_RCILINK:
1252 printf("Root Complex Internal Link <?>\n");
1253 break;
1254 case PCI_EXT_CAP_ID_RCEC:
1255 cap_rcec(d, where);
1256 break;
1257 case PCI_EXT_CAP_ID_MFVC:
1258 printf("Multi-Function Virtual Channel <?>\n");
1259 break;
1260 case PCI_EXT_CAP_ID_RCRB:
1261 printf("Root Complex Register Block <?>\n");
1262 break;
1263 case PCI_EXT_CAP_ID_VNDR:
1264 cap_evendor(d, where);
1265 break;
1266 case PCI_EXT_CAP_ID_ACS:
1267 cap_acs(d, where);
1268 break;
1269 case PCI_EXT_CAP_ID_ARI:
1270 cap_ari(d, where);
1271 break;
1272 case PCI_EXT_CAP_ID_ATS:
1273 cap_ats(d, where);
1274 break;
1275 case PCI_EXT_CAP_ID_SRIOV:
1276 cap_sriov(d, where);
1277 break;
1278 case PCI_EXT_CAP_ID_MRIOV:
1279 printf("Multi-Root I/O Virtualization <?>\n");
1280 break;
1281 case PCI_EXT_CAP_ID_MCAST:
1282 cap_multicast(d, where, type);
1283 break;
1284 case PCI_EXT_CAP_ID_PRI:
1285 cap_pri(d, where);
1286 break;
1287 case PCI_EXT_CAP_ID_REBAR:
1288 cap_rebar(d, where, 0);
1289 break;
1290 case PCI_EXT_CAP_ID_DPA:
1291 printf("Dynamic Power Allocation <?>\n");
1292 break;
1293 case PCI_EXT_CAP_ID_TPH:
1294 cap_tph(d, where);
1295 break;
1296 case PCI_EXT_CAP_ID_LTR:
1297 cap_ltr(d, where);
1298 break;
1299 case PCI_EXT_CAP_ID_SECPCI:
1300 cap_sec(d, where);
1301 break;
1302 case PCI_EXT_CAP_ID_PMUX:
1303 printf("Protocol Multiplexing <?>\n");
1304 break;
1305 case PCI_EXT_CAP_ID_PASID:
1306 cap_pasid(d, where);
1307 break;
1308 case PCI_EXT_CAP_ID_LNR:
1309 printf("LN Requester <?>\n");
1310 break;
1311 case PCI_EXT_CAP_ID_L1PM:
1312 cap_l1pm(d, where);
1313 break;
1314 case PCI_EXT_CAP_ID_PTM:
1315 cap_ptm(d, where);
1316 break;
1317 case PCI_EXT_CAP_ID_M_PCIE:
1318 printf("PCI Express over M_PHY <?>\n");
1319 break;
1320 case PCI_EXT_CAP_ID_FRS:
1321 printf("FRS Queueing <?>\n");
1322 break;
1323 case PCI_EXT_CAP_ID_RTR:
1324 printf("Readiness Time Reporting <?>\n");
1325 break;
1326 case PCI_EXT_CAP_ID_DVSEC:
1327 cap_dvsec(d, where);
1328 break;
1329 case PCI_EXT_CAP_ID_VF_REBAR:
1330 cap_rebar(d, where, 1);
1331 break;
1332 case PCI_EXT_CAP_ID_DLNK:
1333 printf("Data Link Feature <?>\n");
1334 break;
1335 case PCI_EXT_CAP_ID_16GT:
1336 printf("Physical Layer 16.0 GT/s <?>\n");
1337 break;
1338 case PCI_EXT_CAP_ID_LMR:
1339 printf("Lane Margining at the Receiver <?>\n");
1340 break;
1341 case PCI_EXT_CAP_ID_HIER_ID:
1342 printf("Hierarchy ID <?>\n");
1343 break;
1344 case PCI_EXT_CAP_ID_NPEM:
1345 printf("Native PCIe Enclosure Management <?>\n");
1346 break;
1347 case PCI_EXT_CAP_ID_DOE:
1348 cap_doe(d, where);
1349 break;
1350 default:
1351 printf("Extended Capability ID %#02x\n", id);
1352 break;
1353 }
1354 where = (header >> 20) & ~3;
1355 } while (where);
1356 }
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