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Resurrected the Windows port.
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26 static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27
28 const char program_name[] = "lspci";
29
30 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
31
32 static char help_msg[] = "\
33 Usage: lspci [<switches>]\n\
34 \n\
35 -v\t\tBe verbose\n\
36 -n\t\tShow numeric ID's\n\
37 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
38 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
39 -x\t\tShow hex-dump of the standard portion of config space\n\
40 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
41 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
42 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
43 -d [<vendor>]:[<device>]\tShow only selected devices\n\
44 -t\t\tShow bus tree\n\
45 -m\t\tProduce machine-readable output\n\
46 -i <file>\tUse specified ID database instead of %s\n\
47 -D\t\tAlways show domain numbers\n\
48 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
49 GENERIC_HELP
50 ;
51
52 /* Communication with libpci */
53
54 static struct pci_access *pacc;
55
56 /*
57 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
58 * This increases our memory footprint, but only slightly since we don't
59 * use alloca() much.
60 */
61
62 #if defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
63 #include <alloca.h>
64 #else
65 #undef alloca
66 #define alloca xmalloc
67 #endif
68
69 /* Our view of the PCI bus */
70
71 struct device {
72 struct device *next;
73 struct pci_dev *dev;
74 unsigned int config_cached, config_bufsize;
75 byte *config; /* Cached configuration space data */
76 byte *present; /* Maps which configuration bytes are present */
77 };
78
79 static struct device *first_dev;
80 static int seen_errors;
81
82 static int
83 config_fetch(struct device *d, unsigned int pos, unsigned int len)
84 {
85 unsigned int end = pos+len;
86 int result;
87
88 while (pos < d->config_bufsize && len && d->present[pos])
89 pos++, len--;
90 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
91 len--;
92 if (!len)
93 return 1;
94
95 if (end > d->config_bufsize)
96 {
97 int orig_size = d->config_bufsize;
98 while (end > d->config_bufsize)
99 d->config_bufsize *= 2;
100 d->config = xrealloc(d->config, d->config_bufsize);
101 d->present = xrealloc(d->present, d->config_bufsize);
102 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
103 }
104 result = pci_read_block(d->dev, pos, d->config + pos, len);
105 if (result)
106 memset(d->present + pos, 1, len);
107 return result;
108 }
109
110 static struct device *
111 scan_device(struct pci_dev *p)
112 {
113 struct device *d;
114
115 if (p->domain && !show_domains)
116 show_domains = 1;
117 if (!pci_filter_match(&filter, p))
118 return NULL;
119 d = xmalloc(sizeof(struct device));
120 memset(d, 0, sizeof(*d));
121 d->dev = p;
122 d->config_cached = d->config_bufsize = 64;
123 d->config = xmalloc(64);
124 d->present = xmalloc(64);
125 memset(d->present, 1, 64);
126 if (!pci_read_block(p, 0, d->config, 64))
127 {
128 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
129 p->domain, p->bus, p->dev, p->func);
130 seen_errors++;
131 return NULL;
132 }
133 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
134 {
135 /* For cardbus bridges, we need to fetch 64 bytes more to get the
136 * full standard header... */
137 if (config_fetch(d, 64, 64))
138 d->config_cached += 64;
139 }
140 pci_setup_cache(p, d->config, d->config_cached);
141 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
142 return d;
143 }
144
145 static void
146 scan_devices(void)
147 {
148 struct device *d;
149 struct pci_dev *p;
150
151 pci_scan_bus(pacc);
152 for(p=pacc->devices; p; p=p->next)
153 if (d = scan_device(p))
154 {
155 d->next = first_dev;
156 first_dev = d;
157 }
158 }
159
160 /* Config space accesses */
161
162 static void
163 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
164 {
165 while (len)
166 if (!d->present[pos])
167 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
168 else
169 pos++, len--;
170 }
171
172 static inline byte
173 get_conf_byte(struct device *d, unsigned int pos)
174 {
175 check_conf_range(d, pos, 1);
176 return d->config[pos];
177 }
178
179 static word
180 get_conf_word(struct device *d, unsigned int pos)
181 {
182 check_conf_range(d, pos, 2);
183 return d->config[pos] | (d->config[pos+1] << 8);
184 }
185
186 static u32
187 get_conf_long(struct device *d, unsigned int pos)
188 {
189 check_conf_range(d, pos, 4);
190 return d->config[pos] |
191 (d->config[pos+1] << 8) |
192 (d->config[pos+2] << 16) |
193 (d->config[pos+3] << 24);
194 }
195
196 /* Sorting */
197
198 static int
199 compare_them(const void *A, const void *B)
200 {
201 const struct pci_dev *a = (*(const struct device **)A)->dev;
202 const struct pci_dev *b = (*(const struct device **)B)->dev;
203
204 if (a->domain < b->domain)
205 return -1;
206 if (a->domain > b->domain)
207 return 1;
208 if (a->bus < b->bus)
209 return -1;
210 if (a->bus > b->bus)
211 return 1;
212 if (a->dev < b->dev)
213 return -1;
214 if (a->dev > b->dev)
215 return 1;
216 if (a->func < b->func)
217 return -1;
218 if (a->func > b->func)
219 return 1;
220 return 0;
221 }
222
223 static void
224 sort_them(void)
225 {
226 struct device **index, **h, **last_dev;
227 int cnt;
228 struct device *d;
229
230 cnt = 0;
231 for(d=first_dev; d; d=d->next)
232 cnt++;
233 h = index = alloca(sizeof(struct device *) * cnt);
234 for(d=first_dev; d; d=d->next)
235 *h++ = d;
236 qsort(index, cnt, sizeof(struct device *), compare_them);
237 last_dev = &first_dev;
238 h = index;
239 while (cnt--)
240 {
241 *last_dev = *h;
242 last_dev = &(*h)->next;
243 h++;
244 }
245 *last_dev = NULL;
246 }
247
248 /* Normal output */
249
250 #define FLAG(x,y) ((x & y) ? '+' : '-')
251
252 static void
253 show_slot_name(struct device *d)
254 {
255 struct pci_dev *p = d->dev;
256
257 if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
258 printf("%04x:", p->domain);
259 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
260 }
261
262 static void
263 show_terse(struct device *d)
264 {
265 int c;
266 struct pci_dev *p = d->dev;
267 char classbuf[128], devbuf[128];
268
269 show_slot_name(d);
270 printf(" %s: %s",
271 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
272 PCI_LOOKUP_CLASS,
273 p->device_class),
274 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
275 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
276 p->vendor_id, p->device_id));
277 if (c = get_conf_byte(d, PCI_REVISION_ID))
278 printf(" (rev %02x)", c);
279 if (verbose)
280 {
281 char *x;
282 c = get_conf_byte(d, PCI_CLASS_PROG);
283 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
284 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
285 p->device_class, c);
286 if (c || x)
287 {
288 printf(" (prog-if %02x", c);
289 if (x)
290 printf(" [%s]", x);
291 putchar(')');
292 }
293 }
294 putchar('\n');
295 }
296
297 static void
298 show_size(pciaddr_t x)
299 {
300 if (!x)
301 return;
302 printf(" [size=");
303 if (x < 1024)
304 printf("%d", (int) x);
305 else if (x < 1048576)
306 printf("%dK", (int)(x / 1024));
307 else if (x < 0x80000000)
308 printf("%dM", (int)(x / 1048576));
309 else
310 printf(PCIADDR_T_FMT, x);
311 putchar(']');
312 }
313
314 static void
315 show_bases(struct device *d, int cnt)
316 {
317 struct pci_dev *p = d->dev;
318 word cmd = get_conf_word(d, PCI_COMMAND);
319 int i;
320
321 for(i=0; i<cnt; i++)
322 {
323 pciaddr_t pos = p->base_addr[i];
324 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
325 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
326 if (flg == 0xffffffff)
327 flg = 0;
328 if (!pos && !flg && !len)
329 continue;
330 if (verbose > 1)
331 printf("\tRegion %d: ", i);
332 else
333 putchar('\t');
334 if (pos && !flg) /* Reported by the OS, but not by the device */
335 {
336 printf("[virtual] ");
337 flg = pos;
338 }
339 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
340 {
341 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
342 printf("I/O ports at ");
343 if (a)
344 printf(PCIADDR_PORT_FMT, a);
345 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
346 printf("<ignored>");
347 else
348 printf("<unassigned>");
349 if (!(cmd & PCI_COMMAND_IO))
350 printf(" [disabled]");
351 }
352 else
353 {
354 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
355 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
356 int done = 0;
357 u32 z = 0;
358
359 printf("Memory at ");
360 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
361 {
362 if (i >= cnt - 1)
363 {
364 printf("<invalid-64bit-slot>");
365 done = 1;
366 }
367 else
368 {
369 i++;
370 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
371 if (buscentric_view)
372 {
373 u32 y = a & 0xffffffff;
374 if (a || z)
375 printf("%08x%08x", z, y);
376 else
377 printf("<unassigned>");
378 done = 1;
379 }
380 }
381 }
382 if (!done)
383 {
384 if (a)
385 printf(PCIADDR_T_FMT, a);
386 else
387 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
388 }
389 printf(" (%s, %sprefetchable)",
390 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
391 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
392 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
393 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
394 if (!(cmd & PCI_COMMAND_MEMORY))
395 printf(" [disabled]");
396 }
397 show_size(len);
398 putchar('\n');
399 }
400 }
401
402 static void
403 show_pm(struct device *d, int where, int cap)
404 {
405 int t, b;
406 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
407
408 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
409 if (verbose < 2)
410 return;
411 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
412 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
413 FLAG(cap, PCI_PM_CAP_DSI),
414 FLAG(cap, PCI_PM_CAP_D1),
415 FLAG(cap, PCI_PM_CAP_D2),
416 pm_aux_current[(cap >> 6) & 7],
417 FLAG(cap, PCI_PM_CAP_PME_D0),
418 FLAG(cap, PCI_PM_CAP_PME_D1),
419 FLAG(cap, PCI_PM_CAP_PME_D2),
420 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
421 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
422 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
423 return;
424 t = get_conf_word(d, where + PCI_PM_CTRL);
425 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
426 t & PCI_PM_CTRL_STATE_MASK,
427 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
428 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
429 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
430 FLAG(t, PCI_PM_CTRL_PME_STATUS));
431 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
432 if (b)
433 printf("\t\tBridge: PM%c B3%c\n",
434 FLAG(t, PCI_PM_BPCC_ENABLE),
435 FLAG(~t, PCI_PM_PPB_B2_B3));
436 }
437
438 static void
439 format_agp_rate(int rate, char *buf, int agp3)
440 {
441 char *c = buf;
442 int i;
443
444 for(i=0; i<=2; i++)
445 if (rate & (1 << i))
446 {
447 if (c != buf)
448 *c++ = ',';
449 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
450 }
451 if (c != buf)
452 *c = 0;
453 else
454 strcpy(buf, "<none>");
455 }
456
457 static void
458 show_agp(struct device *d, int where, int cap)
459 {
460 u32 t;
461 char rate[16];
462 int ver, rev;
463 int agp3 = 0;
464
465 ver = (cap >> 4) & 0x0f;
466 rev = cap & 0x0f;
467 printf("AGP version %x.%x\n", ver, rev);
468 if (verbose < 2)
469 return;
470 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
471 return;
472 t = get_conf_long(d, where + PCI_AGP_STATUS);
473 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
474 agp3 = 1;
475 format_agp_rate(t & 7, rate, agp3);
476 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
477 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
478 FLAG(t, PCI_AGP_STATUS_ISOCH),
479 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
480 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
481 FLAG(t, PCI_AGP_STATUS_SBA),
482 FLAG(t, PCI_AGP_STATUS_ITA_COH),
483 FLAG(t, PCI_AGP_STATUS_GART64),
484 FLAG(t, PCI_AGP_STATUS_HTRANS),
485 FLAG(t, PCI_AGP_STATUS_64BIT),
486 FLAG(t, PCI_AGP_STATUS_FW),
487 FLAG(t, PCI_AGP_STATUS_AGP3),
488 rate);
489 t = get_conf_long(d, where + PCI_AGP_COMMAND);
490 format_agp_rate(t & 7, rate, agp3);
491 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
492 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
493 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
494 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
495 FLAG(t, PCI_AGP_COMMAND_SBA),
496 FLAG(t, PCI_AGP_COMMAND_AGP),
497 FLAG(t, PCI_AGP_COMMAND_GART64),
498 FLAG(t, PCI_AGP_COMMAND_64BIT),
499 FLAG(t, PCI_AGP_COMMAND_FW),
500 rate);
501 }
502
503 static void
504 show_pcix_nobridge(struct device *d, int where)
505 {
506 u16 command;
507 u32 status;
508 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
509
510 printf("PCI-X non-bridge device\n");
511
512 if (verbose < 2)
513 return;
514
515 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
516 return;
517
518 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
519 status = get_conf_long(d, where + PCI_PCIX_STATUS);
520 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
521 FLAG(command, PCI_PCIX_COMMAND_DPERE),
522 FLAG(command, PCI_PCIX_COMMAND_ERO),
523 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
524 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
525 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
526 ((status >> 8) & 0xff),
527 ((status >> 3) & 0x1f),
528 (status & PCI_PCIX_STATUS_FUNCTION),
529 FLAG(status, PCI_PCIX_STATUS_64BIT),
530 FLAG(status, PCI_PCIX_STATUS_133MHZ),
531 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
532 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
533 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
534 1 << (9 + ((status >> 21) & 3U)),
535 max_outstanding[(status >> 23) & 7U],
536 1 << (3 + ((status >> 26) & 7U)),
537 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
538 FLAG(status, PCI_PCIX_STATUS_266MHZ),
539 FLAG(status, PCI_PCIX_STATUS_533MHZ));
540 }
541
542 static void
543 show_pcix_bridge(struct device *d, int where)
544 {
545 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
546 u16 secstatus;
547 u32 status, upstcr, downstcr;
548
549 printf("PCI-X bridge device\n");
550
551 if (verbose < 2)
552 return;
553
554 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
555 return;
556
557 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
558 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
559 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
560 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
561 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
562 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
563 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
564 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
565 sec_clock_freq[(secstatus >> 6) & 7]);
566 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
567 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
568 ((status >> 8) & 0xff),
569 ((status >> 3) & 0x1f),
570 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
571 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
572 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
573 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
574 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
575 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
576 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
577 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
578 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
579 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
580 (upstcr >> 16) & 0xffff);
581 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
582 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
583 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
584 (downstcr >> 16) & 0xffff);
585 }
586
587 static void
588 show_pcix(struct device *d, int where)
589 {
590 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
591 {
592 case PCI_HEADER_TYPE_NORMAL:
593 show_pcix_nobridge(d, where);
594 break;
595 case PCI_HEADER_TYPE_BRIDGE:
596 show_pcix_bridge(d, where);
597 break;
598 }
599 }
600
601 static inline char *
602 ht_link_width(unsigned width)
603 {
604 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
605 return widths[width];
606 }
607
608 static inline char *
609 ht_link_freq(unsigned freq)
610 {
611 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
612 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
613 return freqs[freq];
614 }
615
616 static void
617 show_ht_pri(struct device *d, int where, int cmd)
618 {
619 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
620 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
621 char *fmt;
622
623 printf("HyperTransport: Slave or Primary Interface\n");
624 if (verbose < 2)
625 return;
626
627 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
628 return;
629 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
630 if (rid < 0x23 && rid > 0x11)
631 printf("\t\t!!! Possibly incomplete decoding\n");
632
633 if (rid >= 0x23)
634 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
635 else
636 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
637 printf(fmt,
638 (cmd & PCI_HT_PRI_CMD_BUID),
639 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
640 FLAG(cmd, PCI_HT_PRI_CMD_MH),
641 FLAG(cmd, PCI_HT_PRI_CMD_DD),
642 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
643 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
644 if (rid >= 0x23)
645 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
646 else
647 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
648 printf(fmt,
649 FLAG(lctr0, PCI_HT_LCTR_CFLE),
650 FLAG(lctr0, PCI_HT_LCTR_CST),
651 FLAG(lctr0, PCI_HT_LCTR_CFE),
652 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
653 FLAG(lctr0, PCI_HT_LCTR_INIT),
654 FLAG(lctr0, PCI_HT_LCTR_EOC),
655 FLAG(lctr0, PCI_HT_LCTR_TXO),
656 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
657 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
658 FLAG(lctr0, PCI_HT_LCTR_LSEN),
659 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
660 FLAG(lctr0, PCI_HT_LCTR_64B));
661 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
662 if (rid >= 0x23)
663 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
664 else
665 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
666 printf(fmt,
667 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
668 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
669 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
670 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
671 FLAG(lcnf0, PCI_HT_LCNF_DFI),
672 FLAG(lcnf0, PCI_HT_LCNF_DFO),
673 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
674 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
675 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
676 if (rid >= 0x23)
677 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
678 else
679 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
680 printf(fmt,
681 FLAG(lctr1, PCI_HT_LCTR_CFLE),
682 FLAG(lctr1, PCI_HT_LCTR_CST),
683 FLAG(lctr1, PCI_HT_LCTR_CFE),
684 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
685 FLAG(lctr1, PCI_HT_LCTR_INIT),
686 FLAG(lctr1, PCI_HT_LCTR_EOC),
687 FLAG(lctr1, PCI_HT_LCTR_TXO),
688 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
689 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
690 FLAG(lctr1, PCI_HT_LCTR_LSEN),
691 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
692 FLAG(lctr1, PCI_HT_LCTR_64B));
693 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
694 if (rid >= 0x23)
695 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
696 else
697 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
698 printf(fmt,
699 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
700 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
701 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
702 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
703 FLAG(lcnf1, PCI_HT_LCNF_DFI),
704 FLAG(lcnf1, PCI_HT_LCNF_DFO),
705 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
706 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
707 printf("\t\tRevision ID: %u.%02u\n",
708 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
709 if (rid < 0x23)
710 return;
711 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
712 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
713 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
714 FLAG(lfrer0, PCI_HT_LFRER_PROT),
715 FLAG(lfrer0, PCI_HT_LFRER_OV),
716 FLAG(lfrer0, PCI_HT_LFRER_EOC),
717 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
718 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
719 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
720 FLAG(lfcap0, PCI_HT_LFCAP_200),
721 FLAG(lfcap0, PCI_HT_LFCAP_300),
722 FLAG(lfcap0, PCI_HT_LFCAP_400),
723 FLAG(lfcap0, PCI_HT_LFCAP_500),
724 FLAG(lfcap0, PCI_HT_LFCAP_600),
725 FLAG(lfcap0, PCI_HT_LFCAP_800),
726 FLAG(lfcap0, PCI_HT_LFCAP_1000),
727 FLAG(lfcap0, PCI_HT_LFCAP_1200),
728 FLAG(lfcap0, PCI_HT_LFCAP_1400),
729 FLAG(lfcap0, PCI_HT_LFCAP_1600),
730 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
731 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
732 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
733 FLAG(ftr, PCI_HT_FTR_ISOCFC),
734 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
735 FLAG(ftr, PCI_HT_FTR_CRCTM),
736 FLAG(ftr, PCI_HT_FTR_ECTLT),
737 FLAG(ftr, PCI_HT_FTR_64BA),
738 FLAG(ftr, PCI_HT_FTR_UIDRD));
739 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
740 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
741 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
742 FLAG(lfrer1, PCI_HT_LFRER_PROT),
743 FLAG(lfrer1, PCI_HT_LFRER_OV),
744 FLAG(lfrer1, PCI_HT_LFRER_EOC),
745 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
746 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
747 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
748 FLAG(lfcap1, PCI_HT_LFCAP_200),
749 FLAG(lfcap1, PCI_HT_LFCAP_300),
750 FLAG(lfcap1, PCI_HT_LFCAP_400),
751 FLAG(lfcap1, PCI_HT_LFCAP_500),
752 FLAG(lfcap1, PCI_HT_LFCAP_600),
753 FLAG(lfcap1, PCI_HT_LFCAP_800),
754 FLAG(lfcap1, PCI_HT_LFCAP_1000),
755 FLAG(lfcap1, PCI_HT_LFCAP_1200),
756 FLAG(lfcap1, PCI_HT_LFCAP_1400),
757 FLAG(lfcap1, PCI_HT_LFCAP_1600),
758 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
759 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
760 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
761 FLAG(eh, PCI_HT_EH_PFLE),
762 FLAG(eh, PCI_HT_EH_OFLE),
763 FLAG(eh, PCI_HT_EH_PFE),
764 FLAG(eh, PCI_HT_EH_OFE),
765 FLAG(eh, PCI_HT_EH_EOCFE),
766 FLAG(eh, PCI_HT_EH_RFE),
767 FLAG(eh, PCI_HT_EH_CRCFE),
768 FLAG(eh, PCI_HT_EH_SERRFE),
769 FLAG(eh, PCI_HT_EH_CF),
770 FLAG(eh, PCI_HT_EH_RE),
771 FLAG(eh, PCI_HT_EH_PNFE),
772 FLAG(eh, PCI_HT_EH_ONFE),
773 FLAG(eh, PCI_HT_EH_EOCNFE),
774 FLAG(eh, PCI_HT_EH_RNFE),
775 FLAG(eh, PCI_HT_EH_CRCNFE),
776 FLAG(eh, PCI_HT_EH_SERRNFE));
777 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
778 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
779 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
780 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
781 printf("\t\tBus Number: %02x\n", bn);
782 }
783
784 static void
785 show_ht_sec(struct device *d, int where, int cmd)
786 {
787 u16 lctr, lcnf, ftr, eh;
788 u8 rid, lfrer, lfcap, mbu, mlu;
789 char *fmt;
790
791 printf("HyperTransport: Host or Secondary Interface\n");
792 if (verbose < 2)
793 return;
794
795 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
796 return;
797 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
798 if (rid < 0x23 && rid > 0x11)
799 printf("\t\t!!! Possibly incomplete decoding\n");
800
801 if (rid >= 0x23)
802 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
803 else
804 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
805 printf(fmt,
806 FLAG(cmd, PCI_HT_SEC_CMD_WR),
807 FLAG(cmd, PCI_HT_SEC_CMD_DE),
808 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
809 FLAG(cmd, PCI_HT_SEC_CMD_CS),
810 FLAG(cmd, PCI_HT_SEC_CMD_HH),
811 FLAG(cmd, PCI_HT_SEC_CMD_AS),
812 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
813 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
814 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
815 if (rid >= 0x23)
816 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
817 else
818 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
819 printf(fmt,
820 FLAG(lctr, PCI_HT_LCTR_CFLE),
821 FLAG(lctr, PCI_HT_LCTR_CST),
822 FLAG(lctr, PCI_HT_LCTR_CFE),
823 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
824 FLAG(lctr, PCI_HT_LCTR_INIT),
825 FLAG(lctr, PCI_HT_LCTR_EOC),
826 FLAG(lctr, PCI_HT_LCTR_TXO),
827 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
828 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
829 FLAG(lctr, PCI_HT_LCTR_LSEN),
830 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
831 FLAG(lctr, PCI_HT_LCTR_64B));
832 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
833 if (rid >= 0x23)
834 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
835 else
836 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
837 printf(fmt,
838 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
839 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
840 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
841 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
842 FLAG(lcnf, PCI_HT_LCNF_DFI),
843 FLAG(lcnf, PCI_HT_LCNF_DFO),
844 FLAG(lcnf, PCI_HT_LCNF_DFIE),
845 FLAG(lcnf, PCI_HT_LCNF_DFOE));
846 printf("\t\tRevision ID: %u.%02u\n",
847 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
848 if (rid < 0x23)
849 return;
850 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
851 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
852 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
853 FLAG(lfrer, PCI_HT_LFRER_PROT),
854 FLAG(lfrer, PCI_HT_LFRER_OV),
855 FLAG(lfrer, PCI_HT_LFRER_EOC),
856 FLAG(lfrer, PCI_HT_LFRER_CTLT));
857 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
858 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
859 FLAG(lfcap, PCI_HT_LFCAP_200),
860 FLAG(lfcap, PCI_HT_LFCAP_300),
861 FLAG(lfcap, PCI_HT_LFCAP_400),
862 FLAG(lfcap, PCI_HT_LFCAP_500),
863 FLAG(lfcap, PCI_HT_LFCAP_600),
864 FLAG(lfcap, PCI_HT_LFCAP_800),
865 FLAG(lfcap, PCI_HT_LFCAP_1000),
866 FLAG(lfcap, PCI_HT_LFCAP_1200),
867 FLAG(lfcap, PCI_HT_LFCAP_1400),
868 FLAG(lfcap, PCI_HT_LFCAP_1600),
869 FLAG(lfcap, PCI_HT_LFCAP_VEND));
870 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
871 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
872 FLAG(ftr, PCI_HT_FTR_ISOCFC),
873 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
874 FLAG(ftr, PCI_HT_FTR_CRCTM),
875 FLAG(ftr, PCI_HT_FTR_ECTLT),
876 FLAG(ftr, PCI_HT_FTR_64BA),
877 FLAG(ftr, PCI_HT_FTR_UIDRD),
878 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
879 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
880 if (ftr & PCI_HT_SEC_FTR_EXTRS)
881 {
882 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
883 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
884 FLAG(eh, PCI_HT_EH_PFLE),
885 FLAG(eh, PCI_HT_EH_OFLE),
886 FLAG(eh, PCI_HT_EH_PFE),
887 FLAG(eh, PCI_HT_EH_OFE),
888 FLAG(eh, PCI_HT_EH_EOCFE),
889 FLAG(eh, PCI_HT_EH_RFE),
890 FLAG(eh, PCI_HT_EH_CRCFE),
891 FLAG(eh, PCI_HT_EH_SERRFE),
892 FLAG(eh, PCI_HT_EH_CF),
893 FLAG(eh, PCI_HT_EH_RE),
894 FLAG(eh, PCI_HT_EH_PNFE),
895 FLAG(eh, PCI_HT_EH_ONFE),
896 FLAG(eh, PCI_HT_EH_EOCNFE),
897 FLAG(eh, PCI_HT_EH_RNFE),
898 FLAG(eh, PCI_HT_EH_CRCNFE),
899 FLAG(eh, PCI_HT_EH_SERRNFE));
900 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
901 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
902 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
903 }
904 }
905
906 static void
907 show_ht(struct device *d, int where, int cmd)
908 {
909 int type;
910
911 switch (cmd & PCI_HT_CMD_TYP_HI)
912 {
913 case PCI_HT_CMD_TYP_HI_PRI:
914 show_ht_pri(d, where, cmd);
915 return;
916 case PCI_HT_CMD_TYP_HI_SEC:
917 show_ht_sec(d, where, cmd);
918 return;
919 }
920
921 type = cmd & PCI_HT_CMD_TYP;
922 switch (type)
923 {
924 case PCI_HT_CMD_TYP_SW:
925 printf("HyperTransport: Switch\n");
926 break;
927 case PCI_HT_CMD_TYP_IDC:
928 printf("HyperTransport: Interrupt Discovery and Configuration\n");
929 break;
930 case PCI_HT_CMD_TYP_RID:
931 printf("HyperTransport: Revision ID: %u.%02u\n",
932 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
933 break;
934 case PCI_HT_CMD_TYP_UIDC:
935 printf("HyperTransport: UnitID Clumping\n");
936 break;
937 case PCI_HT_CMD_TYP_ECSA:
938 printf("HyperTransport: Extended Configuration Space Access\n");
939 break;
940 case PCI_HT_CMD_TYP_AM:
941 printf("HyperTransport: Address Mapping\n");
942 break;
943 case PCI_HT_CMD_TYP_MSIM:
944 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
945 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
946 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
947 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
948 {
949 u32 offl, offh;
950 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
951 break;
952 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
953 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
954 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
955 }
956 break;
957 case PCI_HT_CMD_TYP_DR:
958 printf("HyperTransport: DirectRoute\n");
959 break;
960 case PCI_HT_CMD_TYP_VCS:
961 printf("HyperTransport: VCSet\n");
962 break;
963 case PCI_HT_CMD_TYP_RM:
964 printf("HyperTransport: Retry Mode\n");
965 break;
966 case PCI_HT_CMD_TYP_X86:
967 printf("HyperTransport: X86 (reserved)\n");
968 break;
969 default:
970 printf("HyperTransport: #%02x\n", type >> 11);
971 }
972 }
973
974 static void
975 show_rom(struct device *d, int reg)
976 {
977 struct pci_dev *p = d->dev;
978 pciaddr_t rom = p->rom_base_addr;
979 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
980 u32 flg = get_conf_long(d, reg);
981 word cmd = get_conf_word(d, PCI_COMMAND);
982
983 if (!rom && !flg && !len)
984 return;
985 putchar('\t');
986 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
987 {
988 printf("[virtual] ");
989 flg = rom;
990 }
991 printf("Expansion ROM at ");
992 if (rom & PCI_ROM_ADDRESS_MASK)
993 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
994 else if (flg & PCI_ROM_ADDRESS_MASK)
995 printf("<ignored>");
996 else
997 printf("<unassigned>");
998 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
999 printf(" [disabled]");
1000 else if (!(cmd & PCI_COMMAND_MEMORY))
1001 printf(" [disabled by cmd]");
1002 show_size(len);
1003 putchar('\n');
1004 }
1005
1006 static void
1007 show_msi(struct device *d, int where, int cap)
1008 {
1009 int is64;
1010 u32 t;
1011 u16 w;
1012
1013 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
1014 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
1015 FLAG(cap, PCI_MSI_FLAGS_64BIT),
1016 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
1017 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
1018 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
1019 if (verbose < 2)
1020 return;
1021 is64 = cap & PCI_MSI_FLAGS_64BIT;
1022 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1023 return;
1024 printf("\t\tAddress: ");
1025 if (is64)
1026 {
1027 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1028 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1029 printf("%08x", t);
1030 }
1031 else
1032 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1033 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1034 printf("%08x Data: %04x\n", t, w);
1035 if (cap & PCI_MSI_FLAGS_MASK_BIT)
1036 {
1037 u32 mask, pending;
1038
1039 if (is64)
1040 {
1041 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
1042 return;
1043 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
1044 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
1045 }
1046 else
1047 {
1048 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
1049 return;
1050 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
1051 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
1052 }
1053 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
1054 }
1055 }
1056
1057 static void show_vendor(void)
1058 {
1059 printf("Vendor Specific Information\n");
1060 }
1061
1062 static void show_debug(void)
1063 {
1064 printf("Debug port\n");
1065 }
1066
1067 static float power_limit(int value, int scale)
1068 {
1069 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1070 return value * scales[scale];
1071 }
1072
1073 static const char *latency_l0s(int value)
1074 {
1075 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1076 return latencies[value];
1077 }
1078
1079 static const char *latency_l1(int value)
1080 {
1081 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1082 return latencies[value];
1083 }
1084
1085 static void show_express_dev(struct device *d, int where, int type)
1086 {
1087 u32 t;
1088 u16 w;
1089
1090 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1091 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1092 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1093 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1094 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1095 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1096 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1097 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1098 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1099 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1100 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1101 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1102 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1103 if (type == PCI_EXP_TYPE_UPSTREAM)
1104 printf("\t\tDevice: SlotPowerLimit %f\n",
1105 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1106 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1107
1108 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1109 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1110 FLAG(w, PCI_EXP_DEVCTL_CERE),
1111 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1112 FLAG(w, PCI_EXP_DEVCTL_FERE),
1113 FLAG(w, PCI_EXP_DEVCTL_URRE));
1114 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1115 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1116 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1117 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1118 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1119 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1120 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1121 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1122 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1123 }
1124
1125 static char *link_speed(int speed)
1126 {
1127 switch (speed)
1128 {
1129 case 1:
1130 return "2.5Gb/s";
1131 default:
1132 return "unknown";
1133 }
1134 }
1135
1136 static char *aspm_support(int code)
1137 {
1138 switch (code)
1139 {
1140 case 1:
1141 return "L0s";
1142 case 3:
1143 return "L0s L1";
1144 default:
1145 return "unknown";
1146 }
1147 }
1148
1149 static const char *aspm_enabled(int code)
1150 {
1151 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1152 return desc[code];
1153 }
1154
1155 static void show_express_link(struct device *d, int where, int type)
1156 {
1157 u32 t;
1158 u16 w;
1159
1160 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1161 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1162 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1163 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1164 t >> 24);
1165 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1166 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1167 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1168 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1169 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1170 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1171 (type == PCI_EXP_TYPE_LEG_END))
1172 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1173 if (w & PCI_EXP_LNKCTL_DISABLE)
1174 printf(" Disabled");
1175 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1176 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1177 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1178 printf("\t\tLink: Speed %s, Width x%d\n",
1179 link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
1180 }
1181
1182 static const char *indicator(int code)
1183 {
1184 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1185 return names[code];
1186 }
1187
1188 static void show_express_slot(struct device *d, int where)
1189 {
1190 u32 t;
1191 u16 w;
1192
1193 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1194 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1195 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1196 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1197 FLAG(t, PCI_EXP_SLTCAP_MRL),
1198 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1199 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1200 FLAG(t, PCI_EXP_SLTCAP_HPC),
1201 FLAG(t, PCI_EXP_SLTCAP_HPS));
1202 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1203 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1204 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1205 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1206 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1207 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1208 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1209 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1210 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1211 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1212 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1213 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1214 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1215 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1216 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1217 }
1218
1219 static void show_express_root(struct device *d, int where)
1220 {
1221 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1222 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1223 FLAG(w, PCI_EXP_RTCTL_SECEE),
1224 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1225 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1226 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1227 }
1228
1229 static void
1230 show_express(struct device *d, int where, int cap)
1231 {
1232 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1233 int size;
1234 int slot = 0;
1235
1236 printf("Express ");
1237 switch (type)
1238 {
1239 case PCI_EXP_TYPE_ENDPOINT:
1240 printf("Endpoint");
1241 break;
1242 case PCI_EXP_TYPE_LEG_END:
1243 printf("Legacy Endpoint");
1244 break;
1245 case PCI_EXP_TYPE_ROOT_PORT:
1246 slot = cap & PCI_EXP_FLAGS_SLOT;
1247 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1248 break;
1249 case PCI_EXP_TYPE_UPSTREAM:
1250 printf("Upstream Port");
1251 break;
1252 case PCI_EXP_TYPE_DOWNSTREAM:
1253 slot = cap & PCI_EXP_FLAGS_SLOT;
1254 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1255 break;
1256 case PCI_EXP_TYPE_PCI_BRIDGE:
1257 printf("PCI/PCI-X Bridge");
1258 break;
1259 case PCI_EXP_TYPE_PCIE_BRIDGE:
1260 printf("PCI/PCI-X to PCI-Express Bridge");
1261 break;
1262 default:
1263 printf("Unknown type");
1264 }
1265 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1266 if (verbose < 2)
1267 return;
1268
1269 size = 16;
1270 if (slot)
1271 size = 24;
1272 if (type == PCI_EXP_TYPE_ROOT_PORT)
1273 size = 32;
1274 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1275 return;
1276
1277 show_express_dev(d, where, type);
1278 show_express_link(d, where, type);
1279 if (slot)
1280 show_express_slot(d, where);
1281 if (type == PCI_EXP_TYPE_ROOT_PORT)
1282 show_express_root(d, where);
1283 }
1284
1285 static void
1286 show_msix(struct device *d, int where, int cap)
1287 {
1288 u32 off;
1289
1290 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1291 FLAG(cap, PCI_MSIX_ENABLE),
1292 FLAG(cap, PCI_MSIX_MASK),
1293 (cap & PCI_MSIX_TABSIZE) + 1);
1294 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1295 return;
1296
1297 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1298 printf("\t\tVector table: BAR=%d offset=%08x\n",
1299 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1300 off = get_conf_long(d, where + PCI_MSIX_PBA);
1301 printf("\t\tPBA: BAR=%d offset=%08x\n",
1302 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1303 }
1304
1305 static void
1306 show_slotid(int cap)
1307 {
1308 int esr = cap & 0xff;
1309 int chs = cap >> 8;
1310
1311 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1312 esr & PCI_SID_ESR_NSLOTS,
1313 FLAG(esr, PCI_SID_ESR_FIC),
1314 chs);
1315 }
1316
1317 static void
1318 show_ssvid(struct device *d, int where)
1319 {
1320 u16 subsys_v, subsys_d;
1321 char ssnamebuf[256];
1322
1323 if (!config_fetch(d, where, 8))
1324 return;
1325 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1326 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1327 printf("Subsystem: %s\n",
1328 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1329 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1330 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1331 }
1332
1333 static void
1334 show_aer(struct device *d UNUSED, int where UNUSED)
1335 {
1336 printf("Advanced Error Reporting\n");
1337 }
1338
1339 static void
1340 show_vc(struct device *d UNUSED, int where UNUSED)
1341 {
1342 printf("Virtual Channel\n");
1343 }
1344
1345 static void
1346 show_dsn(struct device *d, int where)
1347 {
1348 u32 t1, t2;
1349 if (!config_fetch(d, where + 4, 8))
1350 return;
1351 t1 = get_conf_long(d, where + 4);
1352 t2 = get_conf_long(d, where + 8);
1353 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1354 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1355 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1356 }
1357
1358 static void
1359 show_pb(struct device *d UNUSED, int where UNUSED)
1360 {
1361 printf("Power Budgeting\n");
1362 }
1363
1364 static void
1365 show_ext_caps(struct device *d)
1366 {
1367 int where = 0x100;
1368 do
1369 {
1370 u32 header;
1371 int id;
1372
1373 if (!config_fetch(d, where, 4))
1374 break;
1375 header = get_conf_long(d, where);
1376 if (!header)
1377 break;
1378 id = header & 0xffff;
1379 printf("\tCapabilities: [%03x] ", where);
1380 switch (id)
1381 {
1382 case PCI_EXT_CAP_ID_AER:
1383 show_aer(d, where);
1384 break;
1385 case PCI_EXT_CAP_ID_VC:
1386 show_vc(d, where);
1387 break;
1388 case PCI_EXT_CAP_ID_DSN:
1389 show_dsn(d, where);
1390 break;
1391 case PCI_EXT_CAP_ID_PB:
1392 show_pb(d, where);
1393 break;
1394 default:
1395 printf("Unknown (%d)\n", id);
1396 break;
1397 }
1398 where = header >> 20;
1399 } while (where);
1400 }
1401
1402 static void
1403 show_caps(struct device *d)
1404 {
1405 int can_have_ext_caps = 0;
1406
1407 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1408 {
1409 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1410 while (where)
1411 {
1412 int id, next, cap;
1413 printf("\tCapabilities: ");
1414 if (!config_fetch(d, where, 4))
1415 {
1416 puts("<access denied>");
1417 break;
1418 }
1419 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1420 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1421 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1422 printf("[%02x] ", where);
1423 if (id == 0xff)
1424 {
1425 printf("<chain broken>\n");
1426 break;
1427 }
1428 switch (id)
1429 {
1430 case PCI_CAP_ID_PM:
1431 show_pm(d, where, cap);
1432 break;
1433 case PCI_CAP_ID_AGP:
1434 show_agp(d, where, cap);
1435 break;
1436 case PCI_CAP_ID_VPD:
1437 printf("Vital Product Data\n");
1438 break;
1439 case PCI_CAP_ID_SLOTID:
1440 show_slotid(cap);
1441 break;
1442 case PCI_CAP_ID_MSI:
1443 show_msi(d, where, cap);
1444 break;
1445 case PCI_CAP_ID_PCIX:
1446 show_pcix(d, where);
1447 can_have_ext_caps = 1;
1448 break;
1449 case PCI_CAP_ID_HT:
1450 show_ht(d, where, cap);
1451 break;
1452 case PCI_CAP_ID_VNDR:
1453 show_vendor();
1454 break;
1455 case PCI_CAP_ID_DBG:
1456 show_debug();
1457 break;
1458 case PCI_CAP_ID_SSVID:
1459 show_ssvid(d, where);
1460 break;
1461 case PCI_CAP_ID_EXP:
1462 show_express(d, where, cap);
1463 can_have_ext_caps = 1;
1464 break;
1465 case PCI_CAP_ID_MSIX:
1466 show_msix(d, where, cap);
1467 break;
1468 default:
1469 printf("#%02x [%04x]\n", id, cap);
1470 }
1471 where = next;
1472 }
1473 }
1474 if (can_have_ext_caps)
1475 show_ext_caps(d);
1476 }
1477
1478 static void
1479 show_htype0(struct device *d)
1480 {
1481 show_bases(d, 6);
1482 show_rom(d, PCI_ROM_ADDRESS);
1483 show_caps(d);
1484 }
1485
1486 static void
1487 show_htype1(struct device *d)
1488 {
1489 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1490 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1491 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1492 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1493 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1494 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1495 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1496 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1497 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1498 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1499 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1500 int verb = verbose > 2;
1501
1502 show_bases(d, 2);
1503 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1504 get_conf_byte(d, PCI_PRIMARY_BUS),
1505 get_conf_byte(d, PCI_SECONDARY_BUS),
1506 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1507 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1508
1509 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1510 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1511 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1512 else
1513 {
1514 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1515 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1516 if (io_type == PCI_IO_RANGE_TYPE_32)
1517 {
1518 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1519 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1520 }
1521 if (io_base <= io_limit || verb)
1522 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1523 }
1524
1525 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1526 mem_type)
1527 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1528 else
1529 {
1530 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1531 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1532 if (mem_base <= mem_limit || verb)
1533 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1534 }
1535
1536 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1537 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1538 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1539 else
1540 {
1541 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1542 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1543 if (pref_base <= pref_limit || verb)
1544 {
1545 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1546 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1547 else
1548 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1549 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1550 pref_base,
1551 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1552 pref_limit + 0xfffff);
1553 }
1554 }
1555
1556 if (verbose > 1)
1557 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1558 FLAG(sec_stat, PCI_STATUS_66MHZ),
1559 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1560 FLAG(sec_stat, PCI_STATUS_PARITY),
1561 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1562 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1563 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1564 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1565 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1566 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1567 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1568 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1569
1570 show_rom(d, PCI_ROM_ADDRESS1);
1571
1572 if (verbose > 1)
1573 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1574 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1575 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1576 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1577 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1578 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1579 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1580 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1581
1582 show_caps(d);
1583 }
1584
1585 static void
1586 show_htype2(struct device *d)
1587 {
1588 int i;
1589 word cmd = get_conf_word(d, PCI_COMMAND);
1590 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1591 word exca;
1592 int verb = verbose > 2;
1593
1594 show_bases(d, 1);
1595 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1596 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1597 get_conf_byte(d, PCI_CB_CARD_BUS),
1598 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1599 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1600 for(i=0; i<2; i++)
1601 {
1602 int p = 8*i;
1603 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1604 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1605 if (limit > base || verb)
1606 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1607 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1608 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1609 }
1610 for(i=0; i<2; i++)
1611 {
1612 int p = 8*i;
1613 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1614 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1615 if (!(base & PCI_IO_RANGE_TYPE_32))
1616 {
1617 base &= 0xffff;
1618 limit &= 0xffff;
1619 }
1620 base &= PCI_CB_IO_RANGE_MASK;
1621 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1622 if (base <= limit || verb)
1623 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1624 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1625 }
1626
1627 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1628 printf("\tSecondary status: SERR\n");
1629 if (verbose > 1)
1630 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1631 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1632 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1633 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1634 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1635 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1636 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1637 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1638 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1639
1640 if (d->config_cached < 128)
1641 {
1642 printf("\t<access denied to the rest>\n");
1643 return;
1644 }
1645
1646 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1647 if (exca)
1648 printf("\t16-bit legacy interface ports at %04x\n", exca);
1649 }
1650
1651 static void
1652 show_verbose(struct device *d)
1653 {
1654 struct pci_dev *p = d->dev;
1655 word status = get_conf_word(d, PCI_STATUS);
1656 word cmd = get_conf_word(d, PCI_COMMAND);
1657 word class = p->device_class;
1658 byte bist = get_conf_byte(d, PCI_BIST);
1659 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1660 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1661 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1662 byte max_lat, min_gnt;
1663 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1664 unsigned int irq = p->irq;
1665 word subsys_v = 0, subsys_d = 0;
1666 char ssnamebuf[256];
1667
1668 show_terse(d);
1669
1670 switch (htype)
1671 {
1672 case PCI_HEADER_TYPE_NORMAL:
1673 if (class == PCI_CLASS_BRIDGE_PCI)
1674 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1675 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1676 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1677 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1678 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1679 break;
1680 case PCI_HEADER_TYPE_BRIDGE:
1681 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1682 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1683 irq = int_pin = min_gnt = max_lat = 0;
1684 break;
1685 case PCI_HEADER_TYPE_CARDBUS:
1686 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1687 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1688 min_gnt = max_lat = 0;
1689 if (d->config_cached >= 128)
1690 {
1691 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1692 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1693 }
1694 break;
1695 default:
1696 printf("\t!!! Unknown header type %02x\n", htype);
1697 return;
1698 }
1699
1700 if (subsys_v && subsys_v != 0xffff)
1701 printf("\tSubsystem: %s\n",
1702 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1703 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1704 p->vendor_id, p->device_id, subsys_v, subsys_d));
1705
1706 if (verbose > 1)
1707 {
1708 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1709 FLAG(cmd, PCI_COMMAND_IO),
1710 FLAG(cmd, PCI_COMMAND_MEMORY),
1711 FLAG(cmd, PCI_COMMAND_MASTER),
1712 FLAG(cmd, PCI_COMMAND_SPECIAL),
1713 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1714 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1715 FLAG(cmd, PCI_COMMAND_PARITY),
1716 FLAG(cmd, PCI_COMMAND_WAIT),
1717 FLAG(cmd, PCI_COMMAND_SERR),
1718 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1719 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1720 FLAG(status, PCI_STATUS_CAP_LIST),
1721 FLAG(status, PCI_STATUS_66MHZ),
1722 FLAG(status, PCI_STATUS_UDF),
1723 FLAG(status, PCI_STATUS_FAST_BACK),
1724 FLAG(status, PCI_STATUS_PARITY),
1725 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1726 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1727 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1728 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1729 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1730 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1731 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1732 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1733 if (cmd & PCI_COMMAND_MASTER)
1734 {
1735 printf("\tLatency: %d", latency);
1736 if (min_gnt || max_lat)
1737 {
1738 printf(" (");
1739 if (min_gnt)
1740 printf("%dns min", min_gnt*250);
1741 if (min_gnt && max_lat)
1742 printf(", ");
1743 if (max_lat)
1744 printf("%dns max", max_lat*250);
1745 putchar(')');
1746 }
1747 if (cache_line)
1748 printf(", Cache Line Size: %d bytes", cache_line * 4);
1749 putchar('\n');
1750 }
1751 if (int_pin || irq)
1752 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1753 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1754 }
1755 else
1756 {
1757 printf("\tFlags: ");
1758 if (cmd & PCI_COMMAND_MASTER)
1759 printf("bus master, ");
1760 if (cmd & PCI_COMMAND_VGA_PALETTE)
1761 printf("VGA palette snoop, ");
1762 if (cmd & PCI_COMMAND_WAIT)
1763 printf("stepping, ");
1764 if (cmd & PCI_COMMAND_FAST_BACK)
1765 printf("fast Back2Back, ");
1766 if (status & PCI_STATUS_66MHZ)
1767 printf("66MHz, ");
1768 if (status & PCI_STATUS_UDF)
1769 printf("user-definable features, ");
1770 printf("%s devsel",
1771 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1772 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1773 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1774 if (cmd & PCI_COMMAND_MASTER)
1775 printf(", latency %d", latency);
1776 if (irq)
1777 printf(", IRQ " PCIIRQ_FMT, irq);
1778 putchar('\n');
1779 }
1780
1781 if (bist & PCI_BIST_CAPABLE)
1782 {
1783 if (bist & PCI_BIST_START)
1784 printf("\tBIST is running\n");
1785 else
1786 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1787 }
1788
1789 switch (htype)
1790 {
1791 case PCI_HEADER_TYPE_NORMAL:
1792 show_htype0(d);
1793 break;
1794 case PCI_HEADER_TYPE_BRIDGE:
1795 show_htype1(d);
1796 break;
1797 case PCI_HEADER_TYPE_CARDBUS:
1798 show_htype2(d);
1799 break;
1800 }
1801 }
1802
1803 static void
1804 show_hex_dump(struct device *d)
1805 {
1806 unsigned int i, cnt;
1807
1808 cnt = d->config_cached;
1809 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1810 {
1811 cnt = 256;
1812 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1813 cnt = 4096;
1814 }
1815
1816 for(i=0; i<cnt; i++)
1817 {
1818 if (! (i & 15))
1819 printf("%02x:", i);
1820 printf(" %02x", get_conf_byte(d, i));
1821 if ((i & 15) == 15)
1822 putchar('\n');
1823 }
1824 }
1825
1826 static void
1827 print_shell_escaped(char *c)
1828 {
1829 printf(" \"");
1830 while (*c)
1831 {
1832 if (*c == '"' || *c == '\\')
1833 putchar('\\');
1834 putchar(*c++);
1835 }
1836 putchar('"');
1837 }
1838
1839 static void
1840 show_machine(struct device *d)
1841 {
1842 struct pci_dev *p = d->dev;
1843 int c;
1844 word sv_id=0, sd_id=0;
1845 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1846
1847 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1848 {
1849 case PCI_HEADER_TYPE_NORMAL:
1850 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1851 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1852 break;
1853 case PCI_HEADER_TYPE_CARDBUS:
1854 if (d->config_cached >= 128)
1855 {
1856 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1857 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1858 }
1859 break;
1860 }
1861
1862 if (verbose)
1863 {
1864 printf((machine_readable >= 2) ? "Slot:\t" : "Device:\t");
1865 show_slot_name(d);
1866 putchar('\n');
1867 printf("Class:\t%s\n",
1868 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1869 printf("Vendor:\t%s\n",
1870 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1871 printf("Device:\t%s\n",
1872 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1873 if (sv_id && sv_id != 0xffff)
1874 {
1875 printf("SVendor:\t%s\n",
1876 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1877 printf("SDevice:\t%s\n",
1878 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1879 }
1880 if (c = get_conf_byte(d, PCI_REVISION_ID))
1881 printf("Rev:\t%02x\n", c);
1882 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1883 printf("ProgIf:\t%02x\n", c);
1884 }
1885 else
1886 {
1887 show_slot_name(d);
1888 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1889 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1890 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1891 if (c = get_conf_byte(d, PCI_REVISION_ID))
1892 printf(" -r%02x", c);
1893 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1894 printf(" -p%02x", c);
1895 if (sv_id && sv_id != 0xffff)
1896 {
1897 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1898 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1899 }
1900 else
1901 printf(" \"\" \"\"");
1902 putchar('\n');
1903 }
1904 }
1905
1906 static void
1907 show_device(struct device *d)
1908 {
1909 if (machine_readable)
1910 show_machine(d);
1911 else if (verbose)
1912 show_verbose(d);
1913 else
1914 show_terse(d);
1915 if (show_hex)
1916 show_hex_dump(d);
1917 if (verbose || show_hex)
1918 putchar('\n');
1919 }
1920
1921 static void
1922 show(void)
1923 {
1924 struct device *d;
1925
1926 for(d=first_dev; d; d=d->next)
1927 show_device(d);
1928 }
1929
1930 /* Tree output */
1931
1932 struct bridge {
1933 struct bridge *chain; /* Single-linked list of bridges */
1934 struct bridge *next, *child; /* Tree of bridges */
1935 struct bus *first_bus; /* List of buses connected to this bridge */
1936 unsigned int domain;
1937 unsigned int primary, secondary, subordinate; /* Bus numbers */
1938 struct device *br_dev;
1939 };
1940
1941 struct bus {
1942 unsigned int domain;
1943 unsigned int number;
1944 struct bus *sibling;
1945 struct device *first_dev, **last_dev;
1946 };
1947
1948 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1949
1950 static struct bus *
1951 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1952 {
1953 struct bus *bus;
1954
1955 for(bus=b->first_bus; bus; bus=bus->sibling)
1956 if (bus->domain == domain && bus->number == n)
1957 break;
1958 return bus;
1959 }
1960
1961 static struct bus *
1962 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1963 {
1964 struct bus *bus = xmalloc(sizeof(struct bus));
1965 bus->domain = domain;
1966 bus->number = n;
1967 bus->sibling = b->first_bus;
1968 bus->first_dev = NULL;
1969 bus->last_dev = &bus->first_dev;
1970 b->first_bus = bus;
1971 return bus;
1972 }
1973
1974 static void
1975 insert_dev(struct device *d, struct bridge *b)
1976 {
1977 struct pci_dev *p = d->dev;
1978 struct bus *bus;
1979
1980 if (! (bus = find_bus(b, p->domain, p->bus)))
1981 {
1982 struct bridge *c;
1983 for(c=b->child; c; c=c->next)
1984 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1985 {
1986 insert_dev(d, c);
1987 return;
1988 }
1989 bus = new_bus(b, p->domain, p->bus);
1990 }
1991 /* Simple insertion at the end _does_ guarantee the correct order as the
1992 * original device list was sorted by (domain, bus, devfn) lexicographically
1993 * and all devices on the new list have the same bus number.
1994 */
1995 *bus->last_dev = d;
1996 bus->last_dev = &d->next;
1997 d->next = NULL;
1998 }
1999
2000 static void
2001 grow_tree(void)
2002 {
2003 struct device *d, *d2;
2004 struct bridge **last_br, *b;
2005
2006 /* Build list of bridges */
2007
2008 last_br = &host_bridge.chain;
2009 for(d=first_dev; d; d=d->next)
2010 {
2011 word class = d->dev->device_class;
2012 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2013 if (class == PCI_CLASS_BRIDGE_PCI &&
2014 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2015 {
2016 b = xmalloc(sizeof(struct bridge));
2017 b->domain = d->dev->domain;
2018 if (ht == PCI_HEADER_TYPE_BRIDGE)
2019 {
2020 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2021 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2022 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2023 }
2024 else
2025 {
2026 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2027 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2028 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2029 }
2030 *last_br = b;
2031 last_br = &b->chain;
2032 b->next = b->child = NULL;
2033 b->first_bus = NULL;
2034 b->br_dev = d;
2035 }
2036 }
2037 *last_br = NULL;
2038
2039 /* Create a bridge tree */
2040
2041 for(b=&host_bridge; b; b=b->chain)
2042 {
2043 struct bridge *c, *best;
2044 best = NULL;
2045 for(c=&host_bridge; c; c=c->chain)
2046 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2047 b->primary >= c->secondary && b->primary <= c->subordinate &&
2048 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2049 best = c;
2050 if (best)
2051 {
2052 b->next = best->child;
2053 best->child = b;
2054 }
2055 }
2056
2057 /* Insert secondary bus for each bridge */
2058
2059 for(b=&host_bridge; b; b=b->chain)
2060 if (!find_bus(b, b->domain, b->secondary))
2061 new_bus(b, b->domain, b->secondary);
2062
2063 /* Create bus structs and link devices */
2064
2065 for(d=first_dev; d;)
2066 {
2067 d2 = d->next;
2068 insert_dev(d, &host_bridge);
2069 d = d2;
2070 }
2071 }
2072
2073 static void
2074 print_it(char *line, char *p)
2075 {
2076 *p++ = '\n';
2077 *p = 0;
2078 fputs(line, stdout);
2079 for(p=line; *p; p++)
2080 if (*p == '+' || *p == '|')
2081 *p = '|';
2082 else
2083 *p = ' ';
2084 }
2085
2086 static void show_tree_bridge(struct bridge *, char *, char *);
2087
2088 static void
2089 show_tree_dev(struct device *d, char *line, char *p)
2090 {
2091 struct pci_dev *q = d->dev;
2092 struct bridge *b;
2093 char namebuf[256];
2094
2095 p += sprintf(p, "%02x.%x", q->dev, q->func);
2096 for(b=&host_bridge; b; b=b->chain)
2097 if (b->br_dev == d)
2098 {
2099 if (b->secondary == b->subordinate)
2100 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2101 else
2102 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2103 show_tree_bridge(b, line, p);
2104 return;
2105 }
2106 if (verbose)
2107 p += sprintf(p, " %s",
2108 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2109 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2110 q->vendor_id, q->device_id));
2111 print_it(line, p);
2112 }
2113
2114 static void
2115 show_tree_bus(struct bus *b, char *line, char *p)
2116 {
2117 if (!b->first_dev)
2118 print_it(line, p);
2119 else if (!b->first_dev->next)
2120 {
2121 *p++ = '-';
2122 *p++ = '-';
2123 show_tree_dev(b->first_dev, line, p);
2124 }
2125 else
2126 {
2127 struct device *d = b->first_dev;
2128 while (d->next)
2129 {
2130 p[0] = '+';
2131 p[1] = '-';
2132 show_tree_dev(d, line, p+2);
2133 d = d->next;
2134 }
2135 p[0] = '\\';
2136 p[1] = '-';
2137 show_tree_dev(d, line, p+2);
2138 }
2139 }
2140
2141 static void
2142 show_tree_bridge(struct bridge *b, char *line, char *p)
2143 {
2144 *p++ = '-';
2145 if (!b->first_bus->sibling)
2146 {
2147 if (b == &host_bridge)
2148 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2149 show_tree_bus(b->first_bus, line, p);
2150 }
2151 else
2152 {
2153 struct bus *u = b->first_bus;
2154 char *k;
2155
2156 while (u->sibling)
2157 {
2158 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2159 show_tree_bus(u, line, k);
2160 u = u->sibling;
2161 }
2162 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2163 show_tree_bus(u, line, k);
2164 }
2165 }
2166
2167 static void
2168 show_forest(void)
2169 {
2170 char line[256];
2171
2172 grow_tree();
2173 show_tree_bridge(&host_bridge, line, line);
2174 }
2175
2176 /* Bus mapping mode */
2177
2178 struct bus_bridge {
2179 struct bus_bridge *next;
2180 byte this, dev, func, first, last, bug;
2181 };
2182
2183 struct bus_info {
2184 byte exists;
2185 byte guestbook;
2186 struct bus_bridge *bridges, *via;
2187 };
2188
2189 static struct bus_info *bus_info;
2190
2191 static void
2192 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2193 {
2194 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2195 struct pci_dev *p = d->dev;
2196
2197 b->next = bi->bridges;
2198 bi->bridges = b;
2199 b->this = get_conf_byte(d, np);
2200 b->dev = p->dev;
2201 b->func = p->func;
2202 b->first = get_conf_byte(d, ns);
2203 b->last = get_conf_byte(d, nl);
2204 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2205 p->bus, p->dev, p->func, b->this, b->first, b->last);
2206 if (b->this != p->bus)
2207 printf("!!! Bridge points to invalid primary bus.\n");
2208 if (b->first > b->last)
2209 {
2210 printf("!!! Bridge points to invalid bus range.\n");
2211 b->last = b->first;
2212 }
2213 }
2214
2215 static void
2216 do_map_bus(int bus)
2217 {
2218 int dev, func;
2219 int verbose = pacc->debugging;
2220 struct bus_info *bi = bus_info + bus;
2221 struct device *d;
2222
2223 if (verbose)
2224 printf("Mapping bus %02x\n", bus);
2225 for(dev = 0; dev < 32; dev++)
2226 if (filter.slot < 0 || filter.slot == dev)
2227 {
2228 int func_limit = 1;
2229 for(func = 0; func < func_limit; func++)
2230 if (filter.func < 0 || filter.func == func)
2231 {
2232 /* XXX: Bus mapping supports only domain 0 */
2233 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2234 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2235 if (vendor && vendor != 0xffff)
2236 {
2237 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2238 func_limit = 8;
2239 if (verbose)
2240 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2241 bi->exists = 1;
2242 if (d = scan_device(p))
2243 {
2244 show_device(d);
2245 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2246 {
2247 case PCI_HEADER_TYPE_BRIDGE:
2248 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2249 break;
2250 case PCI_HEADER_TYPE_CARDBUS:
2251 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2252 break;
2253 }
2254 free(d);
2255 }
2256 else if (verbose)
2257 printf("But it was filtered out.\n");
2258 }
2259 pci_free_dev(p);
2260 }
2261 }
2262 }
2263
2264 static void
2265 do_map_bridges(int bus, int min, int max)
2266 {
2267 struct bus_info *bi = bus_info + bus;
2268 struct bus_bridge *b;
2269
2270 bi->guestbook = 1;
2271 for(b=bi->bridges; b; b=b->next)
2272 {
2273 if (bus_info[b->first].guestbook)
2274 b->bug = 1;
2275 else if (b->first < min || b->last > max)
2276 b->bug = 2;
2277 else
2278 {
2279 bus_info[b->first].via = b;
2280 do_map_bridges(b->first, b->first, b->last);
2281 }
2282 }
2283 }
2284
2285 static void
2286 map_bridges(void)
2287 {
2288 int i;
2289
2290 printf("\nSummary of buses:\n\n");
2291 for(i=0; i<256; i++)
2292 if (bus_info[i].exists && !bus_info[i].guestbook)
2293 do_map_bridges(i, 0, 255);
2294 for(i=0; i<256; i++)
2295 {
2296 struct bus_info *bi = bus_info + i;
2297 struct bus_bridge *b = bi->via;
2298
2299 if (bi->exists)
2300 {
2301 printf("%02x: ", i);
2302 if (b)
2303 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2304 else if (!i)
2305 printf("Primary host bus\n");
2306 else
2307 printf("Secondary host bus (?)\n");
2308 }
2309 for(b=bi->bridges; b; b=b->next)
2310 {
2311 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2312 switch (b->bug)
2313 {
2314 case 1:
2315 printf(" <overlap bug>");
2316 break;
2317 case 2:
2318 printf(" <crossing bug>");
2319 break;
2320 }
2321 putchar('\n');
2322 }
2323 }
2324 }
2325
2326 static void
2327 map_the_bus(void)
2328 {
2329 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2330 pacc->method == PCI_ACCESS_DUMP)
2331 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2332 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2333 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2334 if (filter.bus >= 0)
2335 do_map_bus(filter.bus);
2336 else
2337 {
2338 int bus;
2339 for(bus=0; bus<256; bus++)
2340 do_map_bus(bus);
2341 }
2342 map_bridges();
2343 }
2344
2345 /* Main */
2346
2347 int
2348 main(int argc, char **argv)
2349 {
2350 int i;
2351 char *msg;
2352
2353 if (argc == 2 && !strcmp(argv[1], "--version"))
2354 {
2355 puts("lspci version " PCIUTILS_VERSION);
2356 return 0;
2357 }
2358
2359 pacc = pci_alloc();
2360 pacc->error = die;
2361 pci_filter_init(pacc, &filter);
2362
2363 while ((i = getopt(argc, argv, options)) != -1)
2364 switch (i)
2365 {
2366 case 'n':
2367 pacc->numeric_ids++;
2368 break;
2369 case 'v':
2370 verbose++;
2371 break;
2372 case 'b':
2373 pacc->buscentric = 1;
2374 buscentric_view = 1;
2375 break;
2376 case 's':
2377 if (msg = pci_filter_parse_slot(&filter, optarg))
2378 die("-s: %s", msg);
2379 break;
2380 case 'd':
2381 if (msg = pci_filter_parse_id(&filter, optarg))
2382 die("-d: %s", msg);
2383 break;
2384 case 'x':
2385 show_hex++;
2386 break;
2387 case 't':
2388 show_tree++;
2389 break;
2390 case 'i':
2391 pci_set_name_list_path(pacc, optarg, 0);
2392 break;
2393 case 'm':
2394 machine_readable++;
2395 break;
2396 case 'M':
2397 map_mode++;
2398 break;
2399 case 'D':
2400 show_domains = 2;
2401 break;
2402 default:
2403 if (parse_generic_option(i, pacc, optarg))
2404 break;
2405 bad:
2406 fprintf(stderr, help_msg, pacc->id_file_name);
2407 return 1;
2408 }
2409 if (optind < argc)
2410 goto bad;
2411
2412 pci_init(pacc);
2413 if (map_mode)
2414 map_the_bus();
2415 else
2416 {
2417 scan_devices();
2418 sort_them();
2419 if (show_tree)
2420 show_forest();
2421 else
2422 show();
2423 }
2424 pci_cleanup(pacc);
2425
2426 return (seen_errors ? 2 : 0);
2427 }
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