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1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #define PCIUTILS_LSPCI
16 #include "pciutils.h"
17
18 /* Options */
19
20 static int verbose; /* Show detailed information */
21 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
22 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
23 static struct pci_filter filter; /* Device filter */
24 static int opt_tree; /* Show bus tree */
25 static int opt_machine; /* Generate machine-readable output */
26 static int opt_map_mode; /* Bus mapping mode enabled */
27 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 static int opt_kernel; /* Show kernel drivers */
29 static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
30 static int opt_query_all; /* Query the DNS for all entries */
31 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
32
33 const char program_name[] = "lspci";
34
35 static char options[] = "nvbxs:d:ti:mgp:qkMDQ" GENERIC_OPTIONS ;
36
37 static char help_msg[] =
38 "Usage: lspci [<switches>]\n"
39 "\n"
40 "Basic display modes:\n"
41 "-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
42 "-t\t\tShow bus tree\n"
43 "\n"
44 "Display options:\n"
45 "-v\t\tBe verbose (-vv for very verbose)\n"
46 #ifdef PCI_OS_LINUX
47 "-k\t\tShow kernel drivers handling each device\n"
48 #endif
49 "-x\t\tShow hex-dump of the standard part of the config space\n"
50 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
51 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
52 "-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
53 "-D\t\tAlways show domain numbers\n"
54 "\n"
55 "Resolving of device ID's to names:\n"
56 "-n\t\tShow numeric ID's\n"
57 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
58 #ifdef PCI_USE_DNS
59 "-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
60 "-qq\t\tAs above, but re-query locally cached entries\n"
61 "-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
62 #endif
63 "\n"
64 "Selection of devices:\n"
65 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
66 "-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
67 "\n"
68 "Other options:\n"
69 "-i <file>\tUse specified ID database instead of %s\n"
70 #ifdef PCI_OS_LINUX
71 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
72 #endif
73 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
74 "\n"
75 "PCI access options:\n"
76 GENERIC_HELP
77 ;
78
79 /*** Communication with libpci ***/
80
81 static struct pci_access *pacc;
82
83 /*
84 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
85 * This increases our memory footprint, but only slightly since we don't
86 * use alloca() much.
87 */
88 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
89 /* alloca() is defined in stdlib.h */
90 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
91 #include <alloca.h>
92 #else
93 #undef alloca
94 #define alloca xmalloc
95 #endif
96
97 /*** Our view of the PCI bus ***/
98
99 struct device {
100 struct device *next;
101 struct pci_dev *dev;
102 unsigned int config_cached, config_bufsize;
103 byte *config; /* Cached configuration space data */
104 byte *present; /* Maps which configuration bytes are present */
105 };
106
107 static struct device *first_dev;
108 static int seen_errors;
109
110 static int
111 config_fetch(struct device *d, unsigned int pos, unsigned int len)
112 {
113 unsigned int end = pos+len;
114 int result;
115
116 while (pos < d->config_bufsize && len && d->present[pos])
117 pos++, len--;
118 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
119 len--;
120 if (!len)
121 return 1;
122
123 if (end > d->config_bufsize)
124 {
125 int orig_size = d->config_bufsize;
126 while (end > d->config_bufsize)
127 d->config_bufsize *= 2;
128 d->config = xrealloc(d->config, d->config_bufsize);
129 d->present = xrealloc(d->present, d->config_bufsize);
130 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
131 }
132 result = pci_read_block(d->dev, pos, d->config + pos, len);
133 if (result)
134 memset(d->present + pos, 1, len);
135 return result;
136 }
137
138 static struct device *
139 scan_device(struct pci_dev *p)
140 {
141 struct device *d;
142
143 if (p->domain && !opt_domains)
144 opt_domains = 1;
145 if (!pci_filter_match(&filter, p))
146 return NULL;
147 d = xmalloc(sizeof(struct device));
148 memset(d, 0, sizeof(*d));
149 d->dev = p;
150 d->config_cached = d->config_bufsize = 64;
151 d->config = xmalloc(64);
152 d->present = xmalloc(64);
153 memset(d->present, 1, 64);
154 if (!pci_read_block(p, 0, d->config, 64))
155 {
156 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
157 p->domain, p->bus, p->dev, p->func);
158 seen_errors++;
159 return NULL;
160 }
161 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
162 {
163 /* For cardbus bridges, we need to fetch 64 bytes more to get the
164 * full standard header... */
165 if (config_fetch(d, 64, 64))
166 d->config_cached += 64;
167 }
168 pci_setup_cache(p, d->config, d->config_cached);
169 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
170 return d;
171 }
172
173 static void
174 scan_devices(void)
175 {
176 struct device *d;
177 struct pci_dev *p;
178
179 pci_scan_bus(pacc);
180 for (p=pacc->devices; p; p=p->next)
181 if (d = scan_device(p))
182 {
183 d->next = first_dev;
184 first_dev = d;
185 }
186 }
187
188 /*** Config space accesses ***/
189
190 static void
191 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
192 {
193 while (len)
194 if (!d->present[pos])
195 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
196 else
197 pos++, len--;
198 }
199
200 static inline byte
201 get_conf_byte(struct device *d, unsigned int pos)
202 {
203 check_conf_range(d, pos, 1);
204 return d->config[pos];
205 }
206
207 static word
208 get_conf_word(struct device *d, unsigned int pos)
209 {
210 check_conf_range(d, pos, 2);
211 return d->config[pos] | (d->config[pos+1] << 8);
212 }
213
214 static u32
215 get_conf_long(struct device *d, unsigned int pos)
216 {
217 check_conf_range(d, pos, 4);
218 return d->config[pos] |
219 (d->config[pos+1] << 8) |
220 (d->config[pos+2] << 16) |
221 (d->config[pos+3] << 24);
222 }
223
224 /*** Sorting ***/
225
226 static int
227 compare_them(const void *A, const void *B)
228 {
229 const struct pci_dev *a = (*(const struct device **)A)->dev;
230 const struct pci_dev *b = (*(const struct device **)B)->dev;
231
232 if (a->domain < b->domain)
233 return -1;
234 if (a->domain > b->domain)
235 return 1;
236 if (a->bus < b->bus)
237 return -1;
238 if (a->bus > b->bus)
239 return 1;
240 if (a->dev < b->dev)
241 return -1;
242 if (a->dev > b->dev)
243 return 1;
244 if (a->func < b->func)
245 return -1;
246 if (a->func > b->func)
247 return 1;
248 return 0;
249 }
250
251 static void
252 sort_them(void)
253 {
254 struct device **index, **h, **last_dev;
255 int cnt;
256 struct device *d;
257
258 cnt = 0;
259 for (d=first_dev; d; d=d->next)
260 cnt++;
261 h = index = alloca(sizeof(struct device *) * cnt);
262 for (d=first_dev; d; d=d->next)
263 *h++ = d;
264 qsort(index, cnt, sizeof(struct device *), compare_them);
265 last_dev = &first_dev;
266 h = index;
267 while (cnt--)
268 {
269 *last_dev = *h;
270 last_dev = &(*h)->next;
271 h++;
272 }
273 *last_dev = NULL;
274 }
275
276 /*** Normal output ***/
277
278 #define FLAG(x,y) ((x & y) ? '+' : '-')
279
280 static void
281 show_slot_name(struct device *d)
282 {
283 struct pci_dev *p = d->dev;
284
285 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
286 printf("%04x:", p->domain);
287 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
288 }
289
290 static void
291 get_subid(struct device *d, word *subvp, word *subdp)
292 {
293 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
294
295 if (htype == PCI_HEADER_TYPE_NORMAL)
296 {
297 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
298 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
299 }
300 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
301 {
302 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
303 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
304 }
305 else
306 *subvp = *subdp = 0xffff;
307 }
308
309 static void
310 show_terse(struct device *d)
311 {
312 int c;
313 struct pci_dev *p = d->dev;
314 char classbuf[128], devbuf[128];
315
316 show_slot_name(d);
317 printf(" %s: %s",
318 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
319 PCI_LOOKUP_CLASS,
320 p->device_class),
321 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
322 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
323 p->vendor_id, p->device_id));
324 if (c = get_conf_byte(d, PCI_REVISION_ID))
325 printf(" (rev %02x)", c);
326 if (verbose)
327 {
328 char *x;
329 c = get_conf_byte(d, PCI_CLASS_PROG);
330 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
331 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
332 p->device_class, c);
333 if (c || x)
334 {
335 printf(" (prog-if %02x", c);
336 if (x)
337 printf(" [%s]", x);
338 putchar(')');
339 }
340 }
341 putchar('\n');
342
343 if (verbose || opt_kernel)
344 {
345 word subsys_v, subsys_d;
346 char ssnamebuf[256];
347
348 get_subid(d, &subsys_v, &subsys_d);
349 if (subsys_v && subsys_v != 0xffff)
350 printf("\tSubsystem: %s\n",
351 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
352 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
353 p->vendor_id, p->device_id, subsys_v, subsys_d));
354 }
355 }
356
357 /*** Capabilities ***/
358
359 static void
360 cap_pm(struct device *d, int where, int cap)
361 {
362 int t, b;
363 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
364
365 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
366 if (verbose < 2)
367 return;
368 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
369 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
370 FLAG(cap, PCI_PM_CAP_DSI),
371 FLAG(cap, PCI_PM_CAP_D1),
372 FLAG(cap, PCI_PM_CAP_D2),
373 pm_aux_current[(cap >> 6) & 7],
374 FLAG(cap, PCI_PM_CAP_PME_D0),
375 FLAG(cap, PCI_PM_CAP_PME_D1),
376 FLAG(cap, PCI_PM_CAP_PME_D2),
377 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
378 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
379 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
380 return;
381 t = get_conf_word(d, where + PCI_PM_CTRL);
382 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
383 t & PCI_PM_CTRL_STATE_MASK,
384 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
385 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
386 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
387 FLAG(t, PCI_PM_CTRL_PME_STATUS));
388 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
389 if (b)
390 printf("\t\tBridge: PM%c B3%c\n",
391 FLAG(t, PCI_PM_BPCC_ENABLE),
392 FLAG(~t, PCI_PM_PPB_B2_B3));
393 }
394
395 static void
396 format_agp_rate(int rate, char *buf, int agp3)
397 {
398 char *c = buf;
399 int i;
400
401 for (i=0; i<=2; i++)
402 if (rate & (1 << i))
403 {
404 if (c != buf)
405 *c++ = ',';
406 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
407 }
408 if (c != buf)
409 *c = 0;
410 else
411 strcpy(buf, "<none>");
412 }
413
414 static void
415 cap_agp(struct device *d, int where, int cap)
416 {
417 u32 t;
418 char rate[16];
419 int ver, rev;
420 int agp3 = 0;
421
422 ver = (cap >> 4) & 0x0f;
423 rev = cap & 0x0f;
424 printf("AGP version %x.%x\n", ver, rev);
425 if (verbose < 2)
426 return;
427 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
428 return;
429 t = get_conf_long(d, where + PCI_AGP_STATUS);
430 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
431 agp3 = 1;
432 format_agp_rate(t & 7, rate, agp3);
433 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
434 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
435 FLAG(t, PCI_AGP_STATUS_ISOCH),
436 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
437 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
438 FLAG(t, PCI_AGP_STATUS_SBA),
439 FLAG(t, PCI_AGP_STATUS_ITA_COH),
440 FLAG(t, PCI_AGP_STATUS_GART64),
441 FLAG(t, PCI_AGP_STATUS_HTRANS),
442 FLAG(t, PCI_AGP_STATUS_64BIT),
443 FLAG(t, PCI_AGP_STATUS_FW),
444 FLAG(t, PCI_AGP_STATUS_AGP3),
445 rate);
446 t = get_conf_long(d, where + PCI_AGP_COMMAND);
447 format_agp_rate(t & 7, rate, agp3);
448 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
449 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
450 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
451 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
452 FLAG(t, PCI_AGP_COMMAND_SBA),
453 FLAG(t, PCI_AGP_COMMAND_AGP),
454 FLAG(t, PCI_AGP_COMMAND_GART64),
455 FLAG(t, PCI_AGP_COMMAND_64BIT),
456 FLAG(t, PCI_AGP_COMMAND_FW),
457 rate);
458 }
459
460 static void
461 print_vpd_string(const byte *buf, word len)
462 {
463 while (len--)
464 {
465 byte ch = *buf++;
466 if (ch == '\\')
467 printf("\\\\");
468 else if (ch < 32 || ch == 127)
469 printf("\\x%02x", ch);
470 else
471 putchar(ch);
472 }
473 }
474
475 static int
476 read_vpd(struct device *d, int pos, byte *buf, int len, byte *csum)
477 {
478 if (!pci_read_vpd(d->dev, pos, buf, len))
479 return 0;
480 while (len--)
481 *csum += *buf++;
482 return 1;
483 }
484
485 static void
486 cap_vpd(struct device *d)
487 {
488 word res_addr = 0, res_len, part_pos, part_len;
489 byte key[2], buf[256];
490 byte tag;
491 byte csum = 0;
492
493 printf("Vital Product Data\n");
494
495 while (res_addr <= PCI_VPD_ADDR_MASK)
496 {
497 if (!read_vpd(d, res_addr, &tag, 1, &csum))
498 break;
499 if (tag & 0x80)
500 {
501 if (res_addr > PCI_VPD_ADDR_MASK + 1 - 3)
502 break;
503 if (!read_vpd(d, res_addr + 1, buf, 2, &csum))
504 break;
505 res_len = buf[0] + (buf[1] << 8);
506 res_addr += 3;
507 }
508 else
509 {
510 res_len = tag & 7;
511 tag >>= 3;
512 res_addr += 1;
513 }
514 if (res_len > PCI_VPD_ADDR_MASK + 1 - res_addr)
515 break;
516
517 part_pos = 0;
518
519 switch (tag)
520 {
521 case 0x0f:
522 printf("\t\tEnd\n");
523 return;
524
525 case 0x82:
526 printf("\t\tProduct Name: ");
527 while (part_pos < res_len)
528 {
529 part_len = res_len - part_pos;
530 if (part_len > sizeof(buf))
531 part_len = sizeof(buf);
532 if (!read_vpd(d, res_addr + part_pos, buf, part_len, &csum))
533 break;
534 print_vpd_string(buf, part_len);
535 part_pos += part_len;
536 }
537 printf("\n");
538 break;
539
540 case 0x90:
541 case 0x91:
542 printf("\t\t%s fields:\n",
543 (tag == 0x90) ? "Read-only" : "Read/write");
544
545 while (part_pos + 3 <= res_len)
546 {
547 word read_len;
548
549 if (!read_vpd(d, res_addr + part_pos, buf, 3, &csum))
550 break;
551 part_pos += 3;
552 key[0] = buf[0];
553 key[1] = buf[1];
554 part_len = buf[2];
555 if (part_len > res_len - part_pos)
556 break;
557
558 /* Only read the first byte of the RV field because the
559 * remaining bytes are not included in the checksum. */
560 read_len = (key[0] == 'R' && key[1] == 'V') ? 1 : part_len;
561 if (!read_vpd(d, res_addr + part_pos, buf, read_len, &csum))
562 break;
563
564 if ((key[0] == 'E' && key[1] == 'C') ||
565 (key[0] == 'P' && key[1] == 'N') ||
566 (key[0] == 'S' && key[1] == 'N') ||
567 key[0] == 'V' ||
568 key[0] == 'Y')
569 {
570 /* Alphanumeric content */
571 printf("\t\t\t%c%c: ", key[0], key[1]);
572 print_vpd_string(buf, part_len);
573 printf("\n");
574 }
575 else if (key[0] == 'R' && key[1] == 'V')
576 {
577 /* Reserved and checksum */
578 printf("\t\t\tRV: checksum %s, %d byte(s) reserved\n",
579 csum ? "bad" : "good", part_len - 1);
580 }
581 else if (key[0] == 'R' && key[1] == 'W')
582 {
583 /* Read-write area */
584 printf("\t\t\tRW: %d byte(s) free\n", part_len);
585 }
586 else
587 {
588 /* Binary or unknown content */
589 int i;
590 printf("\t\t\t%c%c:", key[0], key[1]);
591 for (i = 0; i < part_len; i++)
592 printf(" %02x", buf[i]);
593 printf("\n");
594 }
595
596 part_pos += part_len;
597 }
598 break;
599
600 default:
601 printf("\t\tUnknown %s resource type %02x\n",
602 (tag & 0x80) ? "large" : "small", tag & ~0x80);
603 break;
604 }
605
606 res_addr += res_len;
607 }
608
609 if (res_addr == 0)
610 printf("\t\tNot readable\n");
611 else
612 printf("\t\tNo end tag found\n");
613 }
614
615 static void
616 cap_pcix_nobridge(struct device *d, int where)
617 {
618 u16 command;
619 u32 status;
620 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
621
622 printf("PCI-X non-bridge device\n");
623
624 if (verbose < 2)
625 return;
626
627 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
628 return;
629
630 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
631 status = get_conf_long(d, where + PCI_PCIX_STATUS);
632 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
633 FLAG(command, PCI_PCIX_COMMAND_DPERE),
634 FLAG(command, PCI_PCIX_COMMAND_ERO),
635 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
636 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
637 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
638 ((status >> 8) & 0xff),
639 ((status >> 3) & 0x1f),
640 (status & PCI_PCIX_STATUS_FUNCTION),
641 FLAG(status, PCI_PCIX_STATUS_64BIT),
642 FLAG(status, PCI_PCIX_STATUS_133MHZ),
643 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
644 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
645 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
646 1 << (9 + ((status >> 21) & 3U)),
647 max_outstanding[(status >> 23) & 7U],
648 1 << (3 + ((status >> 26) & 7U)),
649 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
650 FLAG(status, PCI_PCIX_STATUS_266MHZ),
651 FLAG(status, PCI_PCIX_STATUS_533MHZ));
652 }
653
654 static void
655 cap_pcix_bridge(struct device *d, int where)
656 {
657 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
658 u16 secstatus;
659 u32 status, upstcr, downstcr;
660
661 printf("PCI-X bridge device\n");
662
663 if (verbose < 2)
664 return;
665
666 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
667 return;
668
669 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
670 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
671 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
672 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
673 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
674 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
675 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
676 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
677 sec_clock_freq[(secstatus >> 6) & 7]);
678 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
679 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
680 ((status >> 8) & 0xff),
681 ((status >> 3) & 0x1f),
682 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
683 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
684 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
685 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
686 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
687 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
688 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
689 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
690 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
691 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
692 (upstcr >> 16) & 0xffff);
693 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
694 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
695 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
696 (downstcr >> 16) & 0xffff);
697 }
698
699 static void
700 cap_pcix(struct device *d, int where)
701 {
702 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
703 {
704 case PCI_HEADER_TYPE_NORMAL:
705 cap_pcix_nobridge(d, where);
706 break;
707 case PCI_HEADER_TYPE_BRIDGE:
708 cap_pcix_bridge(d, where);
709 break;
710 }
711 }
712
713 static inline char *
714 ht_link_width(unsigned width)
715 {
716 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
717 return widths[width];
718 }
719
720 static inline char *
721 ht_link_freq(unsigned freq)
722 {
723 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
724 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
725 return freqs[freq];
726 }
727
728 static void
729 cap_ht_pri(struct device *d, int where, int cmd)
730 {
731 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
732 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
733 char *fmt;
734
735 printf("HyperTransport: Slave or Primary Interface\n");
736 if (verbose < 2)
737 return;
738
739 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
740 return;
741 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
742 if (rid < 0x22 && rid > 0x11)
743 printf("\t\t!!! Possibly incomplete decoding\n");
744
745 if (rid >= 0x22)
746 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
747 else
748 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
749 printf(fmt,
750 (cmd & PCI_HT_PRI_CMD_BUID),
751 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
752 FLAG(cmd, PCI_HT_PRI_CMD_MH),
753 FLAG(cmd, PCI_HT_PRI_CMD_DD),
754 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
755 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
756 if (rid >= 0x22)
757 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
758 else
759 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
760 printf(fmt,
761 FLAG(lctr0, PCI_HT_LCTR_CFLE),
762 FLAG(lctr0, PCI_HT_LCTR_CST),
763 FLAG(lctr0, PCI_HT_LCTR_CFE),
764 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
765 FLAG(lctr0, PCI_HT_LCTR_INIT),
766 FLAG(lctr0, PCI_HT_LCTR_EOC),
767 FLAG(lctr0, PCI_HT_LCTR_TXO),
768 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
769 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
770 FLAG(lctr0, PCI_HT_LCTR_LSEN),
771 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
772 FLAG(lctr0, PCI_HT_LCTR_64B));
773 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
774 if (rid >= 0x22)
775 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
776 else
777 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
778 printf(fmt,
779 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
780 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
781 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
782 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
783 FLAG(lcnf0, PCI_HT_LCNF_DFI),
784 FLAG(lcnf0, PCI_HT_LCNF_DFO),
785 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
786 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
787 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
788 if (rid >= 0x22)
789 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
790 else
791 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
792 printf(fmt,
793 FLAG(lctr1, PCI_HT_LCTR_CFLE),
794 FLAG(lctr1, PCI_HT_LCTR_CST),
795 FLAG(lctr1, PCI_HT_LCTR_CFE),
796 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
797 FLAG(lctr1, PCI_HT_LCTR_INIT),
798 FLAG(lctr1, PCI_HT_LCTR_EOC),
799 FLAG(lctr1, PCI_HT_LCTR_TXO),
800 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
801 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
802 FLAG(lctr1, PCI_HT_LCTR_LSEN),
803 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
804 FLAG(lctr1, PCI_HT_LCTR_64B));
805 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
806 if (rid >= 0x22)
807 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
808 else
809 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
810 printf(fmt,
811 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
812 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
813 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
814 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
815 FLAG(lcnf1, PCI_HT_LCNF_DFI),
816 FLAG(lcnf1, PCI_HT_LCNF_DFO),
817 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
818 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
819 printf("\t\tRevision ID: %u.%02u\n",
820 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
821 if (rid < 0x22)
822 return;
823 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
824 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
825 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
826 FLAG(lfrer0, PCI_HT_LFRER_PROT),
827 FLAG(lfrer0, PCI_HT_LFRER_OV),
828 FLAG(lfrer0, PCI_HT_LFRER_EOC),
829 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
830 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
831 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
832 FLAG(lfcap0, PCI_HT_LFCAP_200),
833 FLAG(lfcap0, PCI_HT_LFCAP_300),
834 FLAG(lfcap0, PCI_HT_LFCAP_400),
835 FLAG(lfcap0, PCI_HT_LFCAP_500),
836 FLAG(lfcap0, PCI_HT_LFCAP_600),
837 FLAG(lfcap0, PCI_HT_LFCAP_800),
838 FLAG(lfcap0, PCI_HT_LFCAP_1000),
839 FLAG(lfcap0, PCI_HT_LFCAP_1200),
840 FLAG(lfcap0, PCI_HT_LFCAP_1400),
841 FLAG(lfcap0, PCI_HT_LFCAP_1600),
842 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
843 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
844 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
845 FLAG(ftr, PCI_HT_FTR_ISOCFC),
846 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
847 FLAG(ftr, PCI_HT_FTR_CRCTM),
848 FLAG(ftr, PCI_HT_FTR_ECTLT),
849 FLAG(ftr, PCI_HT_FTR_64BA),
850 FLAG(ftr, PCI_HT_FTR_UIDRD));
851 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
852 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
853 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
854 FLAG(lfrer1, PCI_HT_LFRER_PROT),
855 FLAG(lfrer1, PCI_HT_LFRER_OV),
856 FLAG(lfrer1, PCI_HT_LFRER_EOC),
857 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
858 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
859 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
860 FLAG(lfcap1, PCI_HT_LFCAP_200),
861 FLAG(lfcap1, PCI_HT_LFCAP_300),
862 FLAG(lfcap1, PCI_HT_LFCAP_400),
863 FLAG(lfcap1, PCI_HT_LFCAP_500),
864 FLAG(lfcap1, PCI_HT_LFCAP_600),
865 FLAG(lfcap1, PCI_HT_LFCAP_800),
866 FLAG(lfcap1, PCI_HT_LFCAP_1000),
867 FLAG(lfcap1, PCI_HT_LFCAP_1200),
868 FLAG(lfcap1, PCI_HT_LFCAP_1400),
869 FLAG(lfcap1, PCI_HT_LFCAP_1600),
870 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
871 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
872 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
873 FLAG(eh, PCI_HT_EH_PFLE),
874 FLAG(eh, PCI_HT_EH_OFLE),
875 FLAG(eh, PCI_HT_EH_PFE),
876 FLAG(eh, PCI_HT_EH_OFE),
877 FLAG(eh, PCI_HT_EH_EOCFE),
878 FLAG(eh, PCI_HT_EH_RFE),
879 FLAG(eh, PCI_HT_EH_CRCFE),
880 FLAG(eh, PCI_HT_EH_SERRFE),
881 FLAG(eh, PCI_HT_EH_CF),
882 FLAG(eh, PCI_HT_EH_RE),
883 FLAG(eh, PCI_HT_EH_PNFE),
884 FLAG(eh, PCI_HT_EH_ONFE),
885 FLAG(eh, PCI_HT_EH_EOCNFE),
886 FLAG(eh, PCI_HT_EH_RNFE),
887 FLAG(eh, PCI_HT_EH_CRCNFE),
888 FLAG(eh, PCI_HT_EH_SERRNFE));
889 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
890 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
891 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
892 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
893 printf("\t\tBus Number: %02x\n", bn);
894 }
895
896 static void
897 cap_ht_sec(struct device *d, int where, int cmd)
898 {
899 u16 lctr, lcnf, ftr, eh;
900 u8 rid, lfrer, lfcap, mbu, mlu;
901 char *fmt;
902
903 printf("HyperTransport: Host or Secondary Interface\n");
904 if (verbose < 2)
905 return;
906
907 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
908 return;
909 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
910 if (rid < 0x22 && rid > 0x11)
911 printf("\t\t!!! Possibly incomplete decoding\n");
912
913 if (rid >= 0x22)
914 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
915 else
916 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
917 printf(fmt,
918 FLAG(cmd, PCI_HT_SEC_CMD_WR),
919 FLAG(cmd, PCI_HT_SEC_CMD_DE),
920 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
921 FLAG(cmd, PCI_HT_SEC_CMD_CS),
922 FLAG(cmd, PCI_HT_SEC_CMD_HH),
923 FLAG(cmd, PCI_HT_SEC_CMD_AS),
924 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
925 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
926 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
927 if (rid >= 0x22)
928 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
929 else
930 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
931 printf(fmt,
932 FLAG(lctr, PCI_HT_LCTR_CFLE),
933 FLAG(lctr, PCI_HT_LCTR_CST),
934 FLAG(lctr, PCI_HT_LCTR_CFE),
935 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
936 FLAG(lctr, PCI_HT_LCTR_INIT),
937 FLAG(lctr, PCI_HT_LCTR_EOC),
938 FLAG(lctr, PCI_HT_LCTR_TXO),
939 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
940 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
941 FLAG(lctr, PCI_HT_LCTR_LSEN),
942 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
943 FLAG(lctr, PCI_HT_LCTR_64B));
944 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
945 if (rid >= 0x22)
946 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
947 else
948 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
949 printf(fmt,
950 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
951 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
952 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
953 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
954 FLAG(lcnf, PCI_HT_LCNF_DFI),
955 FLAG(lcnf, PCI_HT_LCNF_DFO),
956 FLAG(lcnf, PCI_HT_LCNF_DFIE),
957 FLAG(lcnf, PCI_HT_LCNF_DFOE));
958 printf("\t\tRevision ID: %u.%02u\n",
959 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
960 if (rid < 0x22)
961 return;
962 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
963 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
964 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
965 FLAG(lfrer, PCI_HT_LFRER_PROT),
966 FLAG(lfrer, PCI_HT_LFRER_OV),
967 FLAG(lfrer, PCI_HT_LFRER_EOC),
968 FLAG(lfrer, PCI_HT_LFRER_CTLT));
969 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
970 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
971 FLAG(lfcap, PCI_HT_LFCAP_200),
972 FLAG(lfcap, PCI_HT_LFCAP_300),
973 FLAG(lfcap, PCI_HT_LFCAP_400),
974 FLAG(lfcap, PCI_HT_LFCAP_500),
975 FLAG(lfcap, PCI_HT_LFCAP_600),
976 FLAG(lfcap, PCI_HT_LFCAP_800),
977 FLAG(lfcap, PCI_HT_LFCAP_1000),
978 FLAG(lfcap, PCI_HT_LFCAP_1200),
979 FLAG(lfcap, PCI_HT_LFCAP_1400),
980 FLAG(lfcap, PCI_HT_LFCAP_1600),
981 FLAG(lfcap, PCI_HT_LFCAP_VEND));
982 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
983 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
984 FLAG(ftr, PCI_HT_FTR_ISOCFC),
985 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
986 FLAG(ftr, PCI_HT_FTR_CRCTM),
987 FLAG(ftr, PCI_HT_FTR_ECTLT),
988 FLAG(ftr, PCI_HT_FTR_64BA),
989 FLAG(ftr, PCI_HT_FTR_UIDRD),
990 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
991 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
992 if (ftr & PCI_HT_SEC_FTR_EXTRS)
993 {
994 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
995 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
996 FLAG(eh, PCI_HT_EH_PFLE),
997 FLAG(eh, PCI_HT_EH_OFLE),
998 FLAG(eh, PCI_HT_EH_PFE),
999 FLAG(eh, PCI_HT_EH_OFE),
1000 FLAG(eh, PCI_HT_EH_EOCFE),
1001 FLAG(eh, PCI_HT_EH_RFE),
1002 FLAG(eh, PCI_HT_EH_CRCFE),
1003 FLAG(eh, PCI_HT_EH_SERRFE),
1004 FLAG(eh, PCI_HT_EH_CF),
1005 FLAG(eh, PCI_HT_EH_RE),
1006 FLAG(eh, PCI_HT_EH_PNFE),
1007 FLAG(eh, PCI_HT_EH_ONFE),
1008 FLAG(eh, PCI_HT_EH_EOCNFE),
1009 FLAG(eh, PCI_HT_EH_RNFE),
1010 FLAG(eh, PCI_HT_EH_CRCNFE),
1011 FLAG(eh, PCI_HT_EH_SERRNFE));
1012 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
1013 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
1014 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
1015 }
1016 }
1017
1018 static void
1019 cap_ht(struct device *d, int where, int cmd)
1020 {
1021 int type;
1022
1023 switch (cmd & PCI_HT_CMD_TYP_HI)
1024 {
1025 case PCI_HT_CMD_TYP_HI_PRI:
1026 cap_ht_pri(d, where, cmd);
1027 return;
1028 case PCI_HT_CMD_TYP_HI_SEC:
1029 cap_ht_sec(d, where, cmd);
1030 return;
1031 }
1032
1033 type = cmd & PCI_HT_CMD_TYP;
1034 switch (type)
1035 {
1036 case PCI_HT_CMD_TYP_SW:
1037 printf("HyperTransport: Switch\n");
1038 break;
1039 case PCI_HT_CMD_TYP_IDC:
1040 printf("HyperTransport: Interrupt Discovery and Configuration\n");
1041 break;
1042 case PCI_HT_CMD_TYP_RID:
1043 printf("HyperTransport: Revision ID: %u.%02u\n",
1044 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
1045 break;
1046 case PCI_HT_CMD_TYP_UIDC:
1047 printf("HyperTransport: UnitID Clumping\n");
1048 break;
1049 case PCI_HT_CMD_TYP_ECSA:
1050 printf("HyperTransport: Extended Configuration Space Access\n");
1051 break;
1052 case PCI_HT_CMD_TYP_AM:
1053 printf("HyperTransport: Address Mapping\n");
1054 break;
1055 case PCI_HT_CMD_TYP_MSIM:
1056 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
1057 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
1058 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
1059 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
1060 {
1061 u32 offl, offh;
1062 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
1063 break;
1064 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
1065 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
1066 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
1067 }
1068 break;
1069 case PCI_HT_CMD_TYP_DR:
1070 printf("HyperTransport: DirectRoute\n");
1071 break;
1072 case PCI_HT_CMD_TYP_VCS:
1073 printf("HyperTransport: VCSet\n");
1074 break;
1075 case PCI_HT_CMD_TYP_RM:
1076 printf("HyperTransport: Retry Mode\n");
1077 break;
1078 case PCI_HT_CMD_TYP_X86:
1079 printf("HyperTransport: X86 (reserved)\n");
1080 break;
1081 default:
1082 printf("HyperTransport: #%02x\n", type >> 11);
1083 }
1084 }
1085
1086 static void
1087 cap_msi(struct device *d, int where, int cap)
1088 {
1089 int is64;
1090 u32 t;
1091 u16 w;
1092
1093 printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
1094 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
1095 FLAG(cap, PCI_MSI_FLAGS_64BIT),
1096 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
1097 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
1098 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
1099 if (verbose < 2)
1100 return;
1101 is64 = cap & PCI_MSI_FLAGS_64BIT;
1102 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1103 return;
1104 printf("\t\tAddress: ");
1105 if (is64)
1106 {
1107 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1108 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1109 printf("%08x", t);
1110 }
1111 else
1112 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1113 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1114 printf("%08x Data: %04x\n", t, w);
1115 if (cap & PCI_MSI_FLAGS_MASK_BIT)
1116 {
1117 u32 mask, pending;
1118
1119 if (is64)
1120 {
1121 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
1122 return;
1123 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
1124 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
1125 }
1126 else
1127 {
1128 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
1129 return;
1130 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
1131 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
1132 }
1133 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
1134 }
1135 }
1136
1137 static float power_limit(int value, int scale)
1138 {
1139 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1140 return value * scales[scale];
1141 }
1142
1143 static const char *latency_l0s(int value)
1144 {
1145 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1146 return latencies[value];
1147 }
1148
1149 static const char *latency_l1(int value)
1150 {
1151 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1152 return latencies[value];
1153 }
1154
1155 static void cap_express_dev(struct device *d, int where, int type)
1156 {
1157 u32 t;
1158 u16 w;
1159
1160 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1161 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
1162 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1163 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1164 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1165 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1166 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1167 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1168 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1169 printf(" AttnBtn%c AttnInd%c PwrInd%c",
1170 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1171 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1172 printf(" RBE%c FLReset%c",
1173 FLAG(t, PCI_EXP_DEVCAP_RBE),
1174 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
1175 if (type == PCI_EXP_TYPE_UPSTREAM)
1176 printf("SlotPowerLimit %fW",
1177 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1178 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1179 printf("\n");
1180
1181 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1182 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1183 FLAG(w, PCI_EXP_DEVCTL_CERE),
1184 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1185 FLAG(w, PCI_EXP_DEVCTL_FERE),
1186 FLAG(w, PCI_EXP_DEVCTL_URRE));
1187 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1188 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1189 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1190 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1191 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1192 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1193 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1194 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1195 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1196 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1197 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1198 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1199 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1200
1201 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1202 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1203 FLAG(w, PCI_EXP_DEVSTA_CED),
1204 FLAG(w, PCI_EXP_DEVSTA_NFED),
1205 FLAG(w, PCI_EXP_DEVSTA_FED),
1206 FLAG(w, PCI_EXP_DEVSTA_URD),
1207 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1208 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1209 }
1210
1211 static char *link_speed(int speed)
1212 {
1213 switch (speed)
1214 {
1215 case 1:
1216 return "2.5GT/s";
1217 case 2:
1218 return "5GT/s";
1219 default:
1220 return "unknown";
1221 }
1222 }
1223
1224 static char *aspm_support(int code)
1225 {
1226 switch (code)
1227 {
1228 case 1:
1229 return "L0s";
1230 case 3:
1231 return "L0s L1";
1232 default:
1233 return "unknown";
1234 }
1235 }
1236
1237 static const char *aspm_enabled(int code)
1238 {
1239 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1240 return desc[code];
1241 }
1242
1243 static void cap_express_link(struct device *d, int where, int type)
1244 {
1245 u32 t;
1246 u16 w;
1247
1248 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1249 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1250 t >> 24,
1251 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1252 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1253 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1254 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1255 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1256 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1257 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1258 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1259 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1260
1261 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1262 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1263 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1264 (type == PCI_EXP_TYPE_LEG_END))
1265 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1266 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1267 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1268 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1269 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1270 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1271 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1272 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1273 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1274 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1275
1276 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1277 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1278 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1279 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1280 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1281 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1282 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1283 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1284 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1285 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1286 }
1287
1288 static const char *indicator(int code)
1289 {
1290 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1291 return names[code];
1292 }
1293
1294 static void cap_express_slot(struct device *d, int where)
1295 {
1296 u32 t;
1297 u16 w;
1298
1299 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1300 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1301 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1302 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1303 FLAG(t, PCI_EXP_SLTCAP_MRL),
1304 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1305 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1306 FLAG(t, PCI_EXP_SLTCAP_HPC),
1307 FLAG(t, PCI_EXP_SLTCAP_HPS));
1308 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1309 t >> 19,
1310 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1311 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1312 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1313
1314 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1315 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1316 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1317 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1318 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1319 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1320 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1321 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1322 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1323 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1324 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1325 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1326 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1327 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1328
1329 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1330 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1331 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1332 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1333 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1334 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1335 FLAG(w, PCI_EXP_SLTSTA_PRES),
1336 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1337 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1338 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1339 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1340 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1341 }
1342
1343 static void cap_express_root(struct device *d, int where)
1344 {
1345 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1346 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1347 FLAG(w, PCI_EXP_RTCTL_SECEE),
1348 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1349 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1350 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1351 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1352
1353 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1354 printf("\t\tRootCap: CRSVisible%c\n",
1355 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1356
1357 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1358 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1359 w & PCI_EXP_RTSTA_PME_REQID,
1360 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1361 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1362 }
1363
1364 static const char *cap_express_dev2_timeout_range(int type)
1365 {
1366 /* Decode Completion Timeout Ranges. */
1367 switch (type)
1368 {
1369 case 0:
1370 return "Not Supported";
1371 case 1:
1372 return "Range A";
1373 case 2:
1374 return "Range B";
1375 case 3:
1376 return "Range AB";
1377 case 6:
1378 return "Range BC";
1379 case 7:
1380 return "Range ABC";
1381 case 14:
1382 return "Range BCD";
1383 case 15:
1384 return "Range ABCD";
1385 default:
1386 return "Unknown";
1387 }
1388 }
1389
1390 static const char *cap_express_dev2_timeout_value(int type)
1391 {
1392 /* Decode Completion Timeout Value. */
1393 switch (type)
1394 {
1395 case 0:
1396 return "50us to 50ms";
1397 case 1:
1398 return "50us to 100us";
1399 case 2:
1400 return "1ms to 10ms";
1401 case 5:
1402 return "16ms to 55ms";
1403 case 6:
1404 return "65ms to 210ms";
1405 case 9:
1406 return "260ms to 900ms";
1407 case 10:
1408 return "1s to 3.5s";
1409 case 13:
1410 return "4s to 13s";
1411 case 14:
1412 return "17s to 64s";
1413 default:
1414 return "Unknown";
1415 }
1416 }
1417
1418 static void cap_express_dev2(struct device *d, int where, int type)
1419 {
1420 u32 l;
1421 u16 w;
1422
1423 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1424 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
1425 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1426 FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
1427 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1428 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1429 else
1430 printf("\n");
1431
1432 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1433 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1434 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1435 FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
1436 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1437 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1438 else
1439 printf("\n");
1440 }
1441
1442 static const char *cap_express_link2_speed(int type)
1443 {
1444 switch (type)
1445 {
1446 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1447 case 1:
1448 return "2.5GT/s";
1449 case 2:
1450 return "5GT/s";
1451 default:
1452 return "Unknown";
1453 }
1454 }
1455
1456 static const char *cap_express_link2_deemphasis(int type)
1457 {
1458 switch (type)
1459 {
1460 case 0:
1461 return "-6dB";
1462 case 1:
1463 return "-3.5dB";
1464 default:
1465 return "Unknown";
1466 }
1467 }
1468
1469 static const char *cap_express_link2_transmargin(int type)
1470 {
1471 switch (type)
1472 {
1473 case 0:
1474 return "Normal Operating Range";
1475 case 1:
1476 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1477 case 2:
1478 case 3:
1479 case 4:
1480 case 5:
1481 return "200-400mV(full-swing)/100-200mV(half-swing)";
1482 default:
1483 return "Unknown";
1484 }
1485 }
1486
1487 static void cap_express_link2(struct device *d, int where, int type UNUSED)
1488 {
1489 u16 w;
1490
1491 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1492 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
1493 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1494 "\t\t\t Compliance De-emphasis: %s\n",
1495 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1496 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1497 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
1498 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
1499 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1500 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1501 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1502 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1503
1504 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1505 printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
1506 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
1507 }
1508
1509 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1510 {
1511 /* No capabilities that require this field in PCIe rev2.0 spec. */
1512 }
1513
1514 static void
1515 cap_express(struct device *d, int where, int cap)
1516 {
1517 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1518 int size;
1519 int slot = 0;
1520
1521 printf("Express ");
1522 if (verbose >= 2)
1523 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1524 switch (type)
1525 {
1526 case PCI_EXP_TYPE_ENDPOINT:
1527 printf("Endpoint");
1528 break;
1529 case PCI_EXP_TYPE_LEG_END:
1530 printf("Legacy Endpoint");
1531 break;
1532 case PCI_EXP_TYPE_ROOT_PORT:
1533 slot = cap & PCI_EXP_FLAGS_SLOT;
1534 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1535 break;
1536 case PCI_EXP_TYPE_UPSTREAM:
1537 printf("Upstream Port");
1538 break;
1539 case PCI_EXP_TYPE_DOWNSTREAM:
1540 slot = cap & PCI_EXP_FLAGS_SLOT;
1541 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1542 break;
1543 case PCI_EXP_TYPE_PCI_BRIDGE:
1544 printf("PCI/PCI-X Bridge");
1545 break;
1546 case PCI_EXP_TYPE_PCIE_BRIDGE:
1547 printf("PCI/PCI-X to PCI-Express Bridge");
1548 break;
1549 case PCI_EXP_TYPE_ROOT_INT_EP:
1550 printf("Root Complex Integrated Endpoint");
1551 break;
1552 case PCI_EXP_TYPE_ROOT_EC:
1553 printf("Root Complex Event Collector");
1554 break;
1555 default:
1556 printf("Unknown type %d", type);
1557 }
1558 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1559 if (verbose < 2)
1560 return;
1561
1562 size = 16;
1563 if (slot)
1564 size = 24;
1565 if (type == PCI_EXP_TYPE_ROOT_PORT)
1566 size = 32;
1567 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1568 return;
1569
1570 cap_express_dev(d, where, type);
1571 cap_express_link(d, where, type);
1572 if (slot)
1573 cap_express_slot(d, where);
1574 if (type == PCI_EXP_TYPE_ROOT_PORT)
1575 cap_express_root(d, where);
1576
1577 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1578 return;
1579
1580 size = 16;
1581 if (slot)
1582 size = 24;
1583 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1584 return;
1585
1586 cap_express_dev2(d, where, type);
1587 cap_express_link2(d, where, type);
1588 if (slot)
1589 cap_express_slot2(d, where);
1590 }
1591
1592 static void
1593 cap_msix(struct device *d, int where, int cap)
1594 {
1595 u32 off;
1596
1597 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1598 FLAG(cap, PCI_MSIX_ENABLE),
1599 FLAG(cap, PCI_MSIX_MASK),
1600 (cap & PCI_MSIX_TABSIZE) + 1);
1601 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1602 return;
1603
1604 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1605 printf("\t\tVector table: BAR=%d offset=%08x\n",
1606 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1607 off = get_conf_long(d, where + PCI_MSIX_PBA);
1608 printf("\t\tPBA: BAR=%d offset=%08x\n",
1609 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1610 }
1611
1612 static void
1613 cap_slotid(int cap)
1614 {
1615 int esr = cap & 0xff;
1616 int chs = cap >> 8;
1617
1618 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1619 esr & PCI_SID_ESR_NSLOTS,
1620 FLAG(esr, PCI_SID_ESR_FIC),
1621 chs);
1622 }
1623
1624 static void
1625 cap_ssvid(struct device *d, int where)
1626 {
1627 u16 subsys_v, subsys_d;
1628 char ssnamebuf[256];
1629
1630 if (!config_fetch(d, where, 8))
1631 return;
1632 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1633 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1634 printf("Subsystem: %s\n",
1635 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1636 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1637 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1638 }
1639
1640 static void
1641 cap_dsn(struct device *d, int where)
1642 {
1643 u32 t1, t2;
1644 if (!config_fetch(d, where + 4, 8))
1645 return;
1646 t1 = get_conf_long(d, where + 4);
1647 t2 = get_conf_long(d, where + 8);
1648 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1649 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1650 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1651 }
1652
1653 static void
1654 cap_debug_port(int cap)
1655 {
1656 int bar = cap >> 13;
1657 int pos = cap & 0x1fff;
1658 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1659 }
1660
1661 static void
1662 cap_aer(struct device *d, int where)
1663 {
1664 u32 l;
1665
1666 printf("Advanced Error Reporting\n");
1667 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
1668 return;
1669
1670 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
1671 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1672 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1673 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1674 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1675 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1676 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1677 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
1678 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1679 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1680 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1681 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1682 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1683 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1684 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
1685 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1686 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1687 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1688 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1689 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1690 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1691 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
1692 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1693 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1694 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1695 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
1696 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1697 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1698 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1699 l = get_conf_long(d, where + PCI_ERR_CAP);
1700 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
1701 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
1702 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
1703
1704 }
1705
1706 static void
1707 cap_acs(struct device *d, int where)
1708 {
1709 u16 w;
1710
1711 printf("Access Control Services\n");
1712 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
1713 return;
1714
1715 w = get_conf_word(d, where + PCI_ACS_CAP);
1716 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1717 "DirectTrans%c\n",
1718 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
1719 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
1720 FLAG(w, PCI_ACS_CAP_TRANS));
1721 w = get_conf_word(d, where + PCI_ACS_CTRL);
1722 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1723 "DirectTrans%c\n",
1724 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
1725 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
1726 FLAG(w, PCI_ACS_CTRL_TRANS));
1727 }
1728
1729 static void
1730 cap_ari(struct device *d, int where)
1731 {
1732 u16 w;
1733
1734 printf("Alternative Routing-ID Interpretation (ARI)\n");
1735 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
1736 return;
1737
1738 w = get_conf_word(d, where + PCI_ARI_CAP);
1739 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
1740 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
1741 PCI_ARI_CAP_NFN(w));
1742 w = get_conf_word(d, where + PCI_ARI_CTRL);
1743 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
1744 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
1745 PCI_ARI_CTRL_FG(w));
1746 }
1747
1748 static void
1749 cap_ats(struct device *d, int where)
1750 {
1751 u16 w;
1752
1753 printf("Address Translation Service (ATS)\n");
1754 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
1755 return;
1756
1757 w = get_conf_word(d, where + PCI_ATS_CAP);
1758 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
1759 w = get_conf_word(d, where + PCI_ATS_CTRL);
1760 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
1761 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
1762 }
1763
1764 static void
1765 cap_sriov(struct device *d, int where)
1766 {
1767 u16 b;
1768 u16 w;
1769 u32 l;
1770
1771 printf("Single Root I/O Virtualization (SR-IOV)\n");
1772 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
1773 return;
1774
1775 l = get_conf_long(d, where + PCI_IOV_CAP);
1776 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
1777 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
1778 w = get_conf_word(d, where + PCI_IOV_CTRL);
1779 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
1780 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
1781 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
1782 FLAG(w, PCI_IOV_CTRL_ARI));
1783 w = get_conf_word(d, where + PCI_IOV_STATUS);
1784 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
1785 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
1786 printf("\t\tInitial VFs: %d, ", w);
1787 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
1788 printf("Total VFs: %d, ", w);
1789 w = get_conf_word(d, where + PCI_IOV_NUMVF);
1790 printf("Number of VFs: %d, ", w);
1791 b = get_conf_byte(d, where + PCI_IOV_FDL);
1792 printf("Function Dependency Link: %02x\n", b);
1793 w = get_conf_word(d, where + PCI_IOV_OFFSET);
1794 printf("\t\tVF offset: %d, ", w);
1795 w = get_conf_word(d, where + PCI_IOV_STRIDE);
1796 printf("stride: %d, ", w);
1797 w = get_conf_word(d, where + PCI_IOV_DID);
1798 printf("Device ID: %04x\n", w);
1799 l = get_conf_long(d, where + PCI_IOV_SUPPS);
1800 printf("\t\tSupported Page Size: %08x, ", l);
1801 l = get_conf_long(d, where + PCI_IOV_SYSPS);
1802 printf("System Page Size: %08x\n", l);
1803 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
1804 PCI_IOV_MSA_BIR(l));
1805 }
1806
1807 static void
1808 show_ext_caps(struct device *d)
1809 {
1810 int where = 0x100;
1811 char been_there[0x1000];
1812 memset(been_there, 0, 0x1000);
1813 do
1814 {
1815 u32 header;
1816 int id;
1817
1818 if (!config_fetch(d, where, 4))
1819 break;
1820 header = get_conf_long(d, where);
1821 if (!header)
1822 break;
1823 id = header & 0xffff;
1824 printf("\tCapabilities: [%03x] ", where);
1825 if (been_there[where]++)
1826 {
1827 printf("<chain looped>\n");
1828 break;
1829 }
1830 switch (id)
1831 {
1832 case PCI_EXT_CAP_ID_AER:
1833 cap_aer(d, where);
1834 break;
1835 case PCI_EXT_CAP_ID_VC:
1836 printf("Virtual Channel <?>\n");
1837 break;
1838 case PCI_EXT_CAP_ID_DSN:
1839 cap_dsn(d, where);
1840 break;
1841 case PCI_EXT_CAP_ID_PB:
1842 printf("Power Budgeting <?>\n");
1843 break;
1844 case PCI_EXT_CAP_ID_RCLINK:
1845 printf("Root Complex Link <?>\n");
1846 break;
1847 case PCI_EXT_CAP_ID_RCILINK:
1848 printf("Root Complex Internal Link <?>\n");
1849 break;
1850 case PCI_EXT_CAP_ID_RCECOLL:
1851 printf("Root Complex Event Collector <?>\n");
1852 break;
1853 case PCI_EXT_CAP_ID_MFVC:
1854 printf("Multi-Function Virtual Channel <?>\n");
1855 break;
1856 case PCI_EXT_CAP_ID_RBCB:
1857 printf("Root Bridge Control Block <?>\n");
1858 break;
1859 case PCI_EXT_CAP_ID_VNDR:
1860 printf("Vendor Specific Information <?>\n");
1861 break;
1862 case PCI_EXT_CAP_ID_ACS:
1863 cap_acs(d, where);
1864 break;
1865 case PCI_EXT_CAP_ID_ARI:
1866 cap_ari(d, where);
1867 break;
1868 case PCI_EXT_CAP_ID_ATS:
1869 cap_ats(d, where);
1870 break;
1871 case PCI_EXT_CAP_ID_SRIOV:
1872 cap_sriov(d, where);
1873 break;
1874 default:
1875 printf("#%02x\n", id);
1876 break;
1877 }
1878 where = header >> 20;
1879 } while (where);
1880 }
1881
1882 static void
1883 show_caps(struct device *d)
1884 {
1885 int can_have_ext_caps = 0;
1886
1887 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1888 {
1889 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1890 byte been_there[256];
1891 memset(been_there, 0, 256);
1892 while (where)
1893 {
1894 int id, next, cap;
1895 printf("\tCapabilities: ");
1896 if (!config_fetch(d, where, 4))
1897 {
1898 puts("<access denied>");
1899 break;
1900 }
1901 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1902 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1903 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1904 printf("[%02x] ", where);
1905 if (been_there[where]++)
1906 {
1907 printf("<chain looped>\n");
1908 break;
1909 }
1910 if (id == 0xff)
1911 {
1912 printf("<chain broken>\n");
1913 break;
1914 }
1915 switch (id)
1916 {
1917 case PCI_CAP_ID_PM:
1918 cap_pm(d, where, cap);
1919 break;
1920 case PCI_CAP_ID_AGP:
1921 cap_agp(d, where, cap);
1922 break;
1923 case PCI_CAP_ID_VPD:
1924 cap_vpd(d);
1925 break;
1926 case PCI_CAP_ID_SLOTID:
1927 cap_slotid(cap);
1928 break;
1929 case PCI_CAP_ID_MSI:
1930 cap_msi(d, where, cap);
1931 break;
1932 case PCI_CAP_ID_CHSWP:
1933 printf("CompactPCI hot-swap <?>\n");
1934 break;
1935 case PCI_CAP_ID_PCIX:
1936 cap_pcix(d, where);
1937 can_have_ext_caps = 1;
1938 break;
1939 case PCI_CAP_ID_HT:
1940 cap_ht(d, where, cap);
1941 break;
1942 case PCI_CAP_ID_VNDR:
1943 printf("Vendor Specific Information <?>\n");
1944 break;
1945 case PCI_CAP_ID_DBG:
1946 cap_debug_port(cap);
1947 break;
1948 case PCI_CAP_ID_CCRC:
1949 printf("CompactPCI central resource control <?>\n");
1950 break;
1951 case PCI_CAP_ID_HOTPLUG:
1952 printf("Hot-plug capable\n");
1953 break;
1954 case PCI_CAP_ID_SSVID:
1955 cap_ssvid(d, where);
1956 break;
1957 case PCI_CAP_ID_AGP3:
1958 printf("AGP3 <?>\n");
1959 break;
1960 case PCI_CAP_ID_SECURE:
1961 printf("Secure device <?>\n");
1962 break;
1963 case PCI_CAP_ID_EXP:
1964 cap_express(d, where, cap);
1965 can_have_ext_caps = 1;
1966 break;
1967 case PCI_CAP_ID_MSIX:
1968 cap_msix(d, where, cap);
1969 break;
1970 case PCI_CAP_ID_SATA:
1971 printf("SATA HBA <?>\n");
1972 break;
1973 case PCI_CAP_ID_AF:
1974 printf("PCIe advanced features <?>\n");
1975 break;
1976 default:
1977 printf("#%02x [%04x]\n", id, cap);
1978 }
1979 where = next;
1980 }
1981 }
1982 if (can_have_ext_caps)
1983 show_ext_caps(d);
1984 }
1985
1986 /*** Kernel drivers ***/
1987
1988 #ifdef PCI_OS_LINUX
1989
1990 #include <sys/utsname.h>
1991
1992 struct pcimap_entry {
1993 struct pcimap_entry *next;
1994 unsigned int vendor, device;
1995 unsigned int subvendor, subdevice;
1996 unsigned int class, class_mask;
1997 char module[1];
1998 };
1999
2000 static struct pcimap_entry *pcimap_head;
2001
2002 static void
2003 load_pcimap(void)
2004 {
2005 static int tried_pcimap;
2006 struct utsname uts;
2007 char *name, line[1024];
2008 FILE *f;
2009
2010 if (tried_pcimap)
2011 return;
2012 tried_pcimap = 1;
2013
2014 if (name = opt_pcimap)
2015 {
2016 f = fopen(name, "r");
2017 if (!f)
2018 die("Cannot open pcimap file %s: %m", name);
2019 }
2020 else
2021 {
2022 if (uname(&uts) < 0)
2023 die("uname() failed: %m");
2024 name = alloca(64 + strlen(uts.release));
2025 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
2026 f = fopen(name, "r");
2027 if (!f)
2028 return;
2029 }
2030
2031 while (fgets(line, sizeof(line), f))
2032 {
2033 char *c = strchr(line, '\n');
2034 struct pcimap_entry *e;
2035
2036 if (!c)
2037 die("Unterminated or too long line in %s", name);
2038 *c = 0;
2039 if (!line[0] || line[0] == '#')
2040 continue;
2041
2042 c = line;
2043 while (*c && *c != ' ' && *c != '\t')
2044 c++;
2045 if (!*c)
2046 continue; /* FIXME: Emit warnings! */
2047 *c++ = 0;
2048
2049 e = xmalloc(sizeof(*e) + strlen(line));
2050 if (sscanf(c, "%i%i%i%i%i%i",
2051 &e->vendor, &e->device,
2052 &e->subvendor, &e->subdevice,
2053 &e->class, &e->class_mask) != 6)
2054 continue;
2055 e->next = pcimap_head;
2056 pcimap_head = e;
2057 strcpy(e->module, line);
2058 }
2059 fclose(f);
2060 }
2061
2062 static int
2063 match_pcimap(struct device *d, struct pcimap_entry *e)
2064 {
2065 struct pci_dev *dev = d->dev;
2066 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
2067 word subv, subd;
2068
2069 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
2070 get_subid(d, &subv, &subd);
2071 return
2072 MATCH(dev->vendor_id, e->vendor) &&
2073 MATCH(dev->device_id, e->device) &&
2074 MATCH(subv, e->subvendor) &&
2075 MATCH(subd, e->subdevice) &&
2076 (class & e->class_mask) == e->class;
2077 #undef MATCH
2078 }
2079
2080 #define DRIVER_BUF_SIZE 1024
2081
2082 static char *
2083 find_driver(struct device *d, char *buf)
2084 {
2085 struct pci_dev *dev = d->dev;
2086 char name[1024], *drv, *base;
2087 int n;
2088
2089 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
2090 return NULL;
2091
2092 base = pci_get_param(dev->access, "sysfs.path");
2093 if (!base || !base[0])
2094 return NULL;
2095
2096 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
2097 base, dev->domain, dev->bus, dev->dev, dev->func);
2098 if (n < 0 || n >= (int)sizeof(name))
2099 die("show_driver: sysfs device name too long, why?");
2100
2101 n = readlink(name, buf, DRIVER_BUF_SIZE);
2102 if (n < 0)
2103 return NULL;
2104 if (n >= DRIVER_BUF_SIZE)
2105 return "<name-too-long>";
2106 buf[n] = 0;
2107
2108 if (drv = strrchr(buf, '/'))
2109 return drv+1;
2110 else
2111 return buf;
2112 }
2113
2114 static void
2115 show_kernel(struct device *d)
2116 {
2117 char buf[DRIVER_BUF_SIZE];
2118 char *driver;
2119 struct pcimap_entry *e, *last = NULL;
2120
2121 if (driver = find_driver(d, buf))
2122 printf("\tKernel driver in use: %s\n", driver);
2123
2124 load_pcimap();
2125 for (e=pcimap_head; e; e=e->next)
2126 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
2127 {
2128 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
2129 last = e;
2130 }
2131 if (last)
2132 putchar('\n');
2133 }
2134
2135 static void
2136 show_kernel_machine(struct device *d)
2137 {
2138 char buf[DRIVER_BUF_SIZE];
2139 char *driver;
2140 struct pcimap_entry *e, *last = NULL;
2141
2142 if (driver = find_driver(d, buf))
2143 printf("Driver:\t%s\n", driver);
2144
2145 load_pcimap();
2146 for (e=pcimap_head; e; e=e->next)
2147 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
2148 {
2149 printf("Module:\t%s\n", e->module);
2150 last = e;
2151 }
2152 }
2153
2154 #else
2155
2156 static void
2157 show_kernel(struct device *d UNUSED)
2158 {
2159 }
2160
2161 static void
2162 show_kernel_machine(struct device *d UNUSED)
2163 {
2164 }
2165
2166 #endif
2167
2168 /*** Verbose output ***/
2169
2170 static void
2171 show_size(pciaddr_t x)
2172 {
2173 if (!x)
2174 return;
2175 printf(" [size=");
2176 if (x < 1024)
2177 printf("%d", (int) x);
2178 else if (x < 1048576)
2179 printf("%dK", (int)(x / 1024));
2180 else if (x < 0x80000000)
2181 printf("%dM", (int)(x / 1048576));
2182 else
2183 printf(PCIADDR_T_FMT, x);
2184 putchar(']');
2185 }
2186
2187 static void
2188 show_bases(struct device *d, int cnt)
2189 {
2190 struct pci_dev *p = d->dev;
2191 word cmd = get_conf_word(d, PCI_COMMAND);
2192 int i;
2193
2194 for (i=0; i<cnt; i++)
2195 {
2196 pciaddr_t pos = p->base_addr[i];
2197 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
2198 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
2199 if (flg == 0xffffffff)
2200 flg = 0;
2201 if (!pos && !flg && !len)
2202 continue;
2203 if (verbose > 1)
2204 printf("\tRegion %d: ", i);
2205 else
2206 putchar('\t');
2207 if (pos && !flg) /* Reported by the OS, but not by the device */
2208 {
2209 printf("[virtual] ");
2210 flg = pos;
2211 }
2212 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
2213 {
2214 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
2215 printf("I/O ports at ");
2216 if (a)
2217 printf(PCIADDR_PORT_FMT, a);
2218 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
2219 printf("<ignored>");
2220 else
2221 printf("<unassigned>");
2222 if (!(cmd & PCI_COMMAND_IO))
2223 printf(" [disabled]");
2224 }
2225 else
2226 {
2227 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
2228 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
2229 int done = 0;
2230 u32 z = 0;
2231
2232 printf("Memory at ");
2233 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
2234 {
2235 if (i >= cnt - 1)
2236 {
2237 printf("<invalid-64bit-slot>");
2238 done = 1;
2239 }
2240 else
2241 {
2242 i++;
2243 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
2244 if (opt_buscentric)
2245 {
2246 u32 y = a & 0xffffffff;
2247 if (a || z)
2248 printf("%08x%08x", z, y);
2249 else
2250 printf("<unassigned>");
2251 done = 1;
2252 }
2253 }
2254 }
2255 if (!done)
2256 {
2257 if (a)
2258 printf(PCIADDR_T_FMT, a);
2259 else
2260 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
2261 }
2262 printf(" (%s, %sprefetchable)",
2263 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
2264 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
2265 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
2266 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
2267 if (!(cmd & PCI_COMMAND_MEMORY))
2268 printf(" [disabled]");
2269 }
2270 show_size(len);
2271 putchar('\n');
2272 }
2273 }
2274
2275 static void
2276 show_rom(struct device *d, int reg)
2277 {
2278 struct pci_dev *p = d->dev;
2279 pciaddr_t rom = p->rom_base_addr;
2280 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
2281 u32 flg = get_conf_long(d, reg);
2282 word cmd = get_conf_word(d, PCI_COMMAND);
2283
2284 if (!rom && !flg && !len)
2285 return;
2286 putchar('\t');
2287 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
2288 {
2289 printf("[virtual] ");
2290 flg = rom;
2291 }
2292 printf("Expansion ROM at ");
2293 if (rom & PCI_ROM_ADDRESS_MASK)
2294 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
2295 else if (flg & PCI_ROM_ADDRESS_MASK)
2296 printf("<ignored>");
2297 else
2298 printf("<unassigned>");
2299 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
2300 printf(" [disabled]");
2301 else if (!(cmd & PCI_COMMAND_MEMORY))
2302 printf(" [disabled by cmd]");
2303 show_size(len);
2304 putchar('\n');
2305 }
2306
2307 static void
2308 show_htype0(struct device *d)
2309 {
2310 show_bases(d, 6);
2311 show_rom(d, PCI_ROM_ADDRESS);
2312 show_caps(d);
2313 }
2314
2315 static void
2316 show_htype1(struct device *d)
2317 {
2318 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
2319 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
2320 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
2321 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
2322 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
2323 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
2324 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
2325 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
2326 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
2327 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
2328 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
2329 int verb = verbose > 2;
2330
2331 show_bases(d, 2);
2332 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2333 get_conf_byte(d, PCI_PRIMARY_BUS),
2334 get_conf_byte(d, PCI_SECONDARY_BUS),
2335 get_conf_byte(d, PCI_SUBORDINATE_BUS),
2336 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
2337
2338 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
2339 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
2340 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
2341 else
2342 {
2343 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
2344 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
2345 if (io_type == PCI_IO_RANGE_TYPE_32)
2346 {
2347 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
2348 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
2349 }
2350 if (io_base <= io_limit || verb)
2351 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
2352 }
2353
2354 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
2355 mem_type)
2356 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
2357 else
2358 {
2359 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
2360 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
2361 if (mem_base <= mem_limit || verb)
2362 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
2363 }
2364
2365 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
2366 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
2367 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
2368 else
2369 {
2370 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
2371 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
2372 if (pref_base <= pref_limit || verb)
2373 {
2374 if (pref_type == PCI_PREF_RANGE_TYPE_32)
2375 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
2376 else
2377 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
2378 get_conf_long(d, PCI_PREF_BASE_UPPER32),
2379 pref_base,
2380 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
2381 pref_limit + 0xfffff);
2382 }
2383 }
2384
2385 if (verbose > 1)
2386 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
2387 FLAG(sec_stat, PCI_STATUS_66MHZ),
2388 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
2389 FLAG(sec_stat, PCI_STATUS_PARITY),
2390 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2391 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2392 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2393 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
2394 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
2395 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
2396 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
2397 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
2398
2399 show_rom(d, PCI_ROM_ADDRESS1);
2400
2401 if (verbose > 1)
2402 {
2403 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
2404 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
2405 FLAG(brc, PCI_BRIDGE_CTL_SERR),
2406 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
2407 FLAG(brc, PCI_BRIDGE_CTL_VGA),
2408 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
2409 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
2410 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
2411 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
2412 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
2413 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
2414 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
2415 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
2416 }
2417
2418 show_caps(d);
2419 }
2420
2421 static void
2422 show_htype2(struct device *d)
2423 {
2424 int i;
2425 word cmd = get_conf_word(d, PCI_COMMAND);
2426 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
2427 word exca;
2428 int verb = verbose > 2;
2429
2430 show_bases(d, 1);
2431 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2432 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
2433 get_conf_byte(d, PCI_CB_CARD_BUS),
2434 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
2435 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
2436 for (i=0; i<2; i++)
2437 {
2438 int p = 8*i;
2439 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
2440 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
2441 if (limit > base || verb)
2442 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
2443 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
2444 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
2445 }
2446 for (i=0; i<2; i++)
2447 {
2448 int p = 8*i;
2449 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
2450 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
2451 if (!(base & PCI_IO_RANGE_TYPE_32))
2452 {
2453 base &= 0xffff;
2454 limit &= 0xffff;
2455 }
2456 base &= PCI_CB_IO_RANGE_MASK;
2457 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
2458 if (base <= limit || verb)
2459 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
2460 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
2461 }
2462
2463 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
2464 printf("\tSecondary status: SERR\n");
2465 if (verbose > 1)
2466 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
2467 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
2468 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
2469 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
2470 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
2471 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
2472 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
2473 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
2474 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
2475
2476 if (d->config_cached < 128)
2477 {
2478 printf("\t<access denied to the rest>\n");
2479 return;
2480 }
2481
2482 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
2483 if (exca)
2484 printf("\t16-bit legacy interface ports at %04x\n", exca);
2485 }
2486
2487 static void
2488 show_verbose(struct device *d)
2489 {
2490 struct pci_dev *p = d->dev;
2491 word status = get_conf_word(d, PCI_STATUS);
2492 word cmd = get_conf_word(d, PCI_COMMAND);
2493 word class = p->device_class;
2494 byte bist = get_conf_byte(d, PCI_BIST);
2495 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2496 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
2497 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
2498 byte max_lat, min_gnt;
2499 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
2500 unsigned int irq = p->irq;
2501
2502 show_terse(d);
2503
2504 switch (htype)
2505 {
2506 case PCI_HEADER_TYPE_NORMAL:
2507 if (class == PCI_CLASS_BRIDGE_PCI)
2508 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2509 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2510 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2511 break;
2512 case PCI_HEADER_TYPE_BRIDGE:
2513 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2514 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2515 irq = int_pin = min_gnt = max_lat = 0;
2516 break;
2517 case PCI_HEADER_TYPE_CARDBUS:
2518 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2519 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2520 min_gnt = max_lat = 0;
2521 break;
2522 default:
2523 printf("\t!!! Unknown header type %02x\n", htype);
2524 return;
2525 }
2526
2527 if (verbose > 1)
2528 {
2529 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2530 FLAG(cmd, PCI_COMMAND_IO),
2531 FLAG(cmd, PCI_COMMAND_MEMORY),
2532 FLAG(cmd, PCI_COMMAND_MASTER),
2533 FLAG(cmd, PCI_COMMAND_SPECIAL),
2534 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2535 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2536 FLAG(cmd, PCI_COMMAND_PARITY),
2537 FLAG(cmd, PCI_COMMAND_WAIT),
2538 FLAG(cmd, PCI_COMMAND_SERR),
2539 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2540 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2541 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2542 FLAG(status, PCI_STATUS_CAP_LIST),
2543 FLAG(status, PCI_STATUS_66MHZ),
2544 FLAG(status, PCI_STATUS_UDF),
2545 FLAG(status, PCI_STATUS_FAST_BACK),
2546 FLAG(status, PCI_STATUS_PARITY),
2547 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2548 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2549 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2550 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2551 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2552 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2553 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2554 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2555 FLAG(status, PCI_STATUS_INTx));
2556 if (cmd & PCI_COMMAND_MASTER)
2557 {
2558 printf("\tLatency: %d", latency);
2559 if (min_gnt || max_lat)
2560 {
2561 printf(" (");
2562 if (min_gnt)
2563 printf("%dns min", min_gnt*250);
2564 if (min_gnt && max_lat)
2565 printf(", ");
2566 if (max_lat)
2567 printf("%dns max", max_lat*250);
2568 putchar(')');
2569 }
2570 if (cache_line)
2571 printf(", Cache Line Size: %d bytes", cache_line * 4);
2572 putchar('\n');
2573 }
2574 if (int_pin || irq)
2575 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2576 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2577 }
2578 else
2579 {
2580 printf("\tFlags: ");
2581 if (cmd & PCI_COMMAND_MASTER)
2582 printf("bus master, ");
2583 if (cmd & PCI_COMMAND_VGA_PALETTE)
2584 printf("VGA palette snoop, ");
2585 if (cmd & PCI_COMMAND_WAIT)
2586 printf("stepping, ");
2587 if (cmd & PCI_COMMAND_FAST_BACK)
2588 printf("fast Back2Back, ");
2589 if (status & PCI_STATUS_66MHZ)
2590 printf("66MHz, ");
2591 if (status & PCI_STATUS_UDF)
2592 printf("user-definable features, ");
2593 printf("%s devsel",
2594 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2595 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2596 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2597 if (cmd & PCI_COMMAND_MASTER)
2598 printf(", latency %d", latency);
2599 if (irq)
2600 printf(", IRQ " PCIIRQ_FMT, irq);
2601 putchar('\n');
2602 }
2603
2604 if (bist & PCI_BIST_CAPABLE)
2605 {
2606 if (bist & PCI_BIST_START)
2607 printf("\tBIST is running\n");
2608 else
2609 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2610 }
2611
2612 switch (htype)
2613 {
2614 case PCI_HEADER_TYPE_NORMAL:
2615 show_htype0(d);
2616 break;
2617 case PCI_HEADER_TYPE_BRIDGE:
2618 show_htype1(d);
2619 break;
2620 case PCI_HEADER_TYPE_CARDBUS:
2621 show_htype2(d);
2622 break;
2623 }
2624 }
2625
2626 /*** Machine-readable dumps ***/
2627
2628 static void
2629 show_hex_dump(struct device *d)
2630 {
2631 unsigned int i, cnt;
2632
2633 cnt = d->config_cached;
2634 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2635 {
2636 cnt = 256;
2637 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2638 cnt = 4096;
2639 }
2640
2641 for (i=0; i<cnt; i++)
2642 {
2643 if (! (i & 15))
2644 printf("%02x:", i);
2645 printf(" %02x", get_conf_byte(d, i));
2646 if ((i & 15) == 15)
2647 putchar('\n');
2648 }
2649 }
2650
2651 static void
2652 print_shell_escaped(char *c)
2653 {
2654 printf(" \"");
2655 while (*c)
2656 {
2657 if (*c == '"' || *c == '\\')
2658 putchar('\\');
2659 putchar(*c++);
2660 }
2661 putchar('"');
2662 }
2663
2664 static void
2665 show_machine(struct device *d)
2666 {
2667 struct pci_dev *p = d->dev;
2668 int c;
2669 word sv_id, sd_id;
2670 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2671
2672 get_subid(d, &sv_id, &sd_id);
2673
2674 if (verbose)
2675 {
2676 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2677 show_slot_name(d);
2678 putchar('\n');
2679 printf("Class:\t%s\n",
2680 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2681 printf("Vendor:\t%s\n",
2682 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2683 printf("Device:\t%s\n",
2684 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2685 if (sv_id && sv_id != 0xffff)
2686 {
2687 printf("SVendor:\t%s\n",
2688 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2689 printf("SDevice:\t%s\n",
2690 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2691 }
2692 if (c = get_conf_byte(d, PCI_REVISION_ID))
2693 printf("Rev:\t%02x\n", c);
2694 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2695 printf("ProgIf:\t%02x\n", c);
2696 if (opt_kernel)
2697 show_kernel_machine(d);
2698 }
2699 else
2700 {
2701 show_slot_name(d);
2702 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2703 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2704 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2705 if (c = get_conf_byte(d, PCI_REVISION_ID))
2706 printf(" -r%02x", c);
2707 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2708 printf(" -p%02x", c);
2709 if (sv_id && sv_id != 0xffff)
2710 {
2711 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2712 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2713 }
2714 else
2715 printf(" \"\" \"\"");
2716 putchar('\n');
2717 }
2718 }
2719
2720 /*** Main show function ***/
2721
2722 static void
2723 show_device(struct device *d)
2724 {
2725 if (opt_machine)
2726 show_machine(d);
2727 else
2728 {
2729 if (verbose)
2730 show_verbose(d);
2731 else
2732 show_terse(d);
2733 if (opt_kernel || verbose)
2734 show_kernel(d);
2735 }
2736 if (opt_hex)
2737 show_hex_dump(d);
2738 if (verbose || opt_hex)
2739 putchar('\n');
2740 }
2741
2742 static void
2743 show(void)
2744 {
2745 struct device *d;
2746
2747 for (d=first_dev; d; d=d->next)
2748 show_device(d);
2749 }
2750
2751 /*** Tree output ***/
2752
2753 struct bridge {
2754 struct bridge *chain; /* Single-linked list of bridges */
2755 struct bridge *next, *child; /* Tree of bridges */
2756 struct bus *first_bus; /* List of buses connected to this bridge */
2757 unsigned int domain;
2758 unsigned int primary, secondary, subordinate; /* Bus numbers */
2759 struct device *br_dev;
2760 };
2761
2762 struct bus {
2763 unsigned int domain;
2764 unsigned int number;
2765 struct bus *sibling;
2766 struct device *first_dev, **last_dev;
2767 };
2768
2769 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2770
2771 static struct bus *
2772 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2773 {
2774 struct bus *bus;
2775
2776 for (bus=b->first_bus; bus; bus=bus->sibling)
2777 if (bus->domain == domain && bus->number == n)
2778 break;
2779 return bus;
2780 }
2781
2782 static struct bus *
2783 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2784 {
2785 struct bus *bus = xmalloc(sizeof(struct bus));
2786 bus->domain = domain;
2787 bus->number = n;
2788 bus->sibling = b->first_bus;
2789 bus->first_dev = NULL;
2790 bus->last_dev = &bus->first_dev;
2791 b->first_bus = bus;
2792 return bus;
2793 }
2794
2795 static void
2796 insert_dev(struct device *d, struct bridge *b)
2797 {
2798 struct pci_dev *p = d->dev;
2799 struct bus *bus;
2800
2801 if (! (bus = find_bus(b, p->domain, p->bus)))
2802 {
2803 struct bridge *c;
2804 for (c=b->child; c; c=c->next)
2805 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2806 {
2807 insert_dev(d, c);
2808 return;
2809 }
2810 bus = new_bus(b, p->domain, p->bus);
2811 }
2812 /* Simple insertion at the end _does_ guarantee the correct order as the
2813 * original device list was sorted by (domain, bus, devfn) lexicographically
2814 * and all devices on the new list have the same bus number.
2815 */
2816 *bus->last_dev = d;
2817 bus->last_dev = &d->next;
2818 d->next = NULL;
2819 }
2820
2821 static void
2822 grow_tree(void)
2823 {
2824 struct device *d, *d2;
2825 struct bridge **last_br, *b;
2826
2827 /* Build list of bridges */
2828
2829 last_br = &host_bridge.chain;
2830 for (d=first_dev; d; d=d->next)
2831 {
2832 word class = d->dev->device_class;
2833 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2834 if (class == PCI_CLASS_BRIDGE_PCI &&
2835 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2836 {
2837 b = xmalloc(sizeof(struct bridge));
2838 b->domain = d->dev->domain;
2839 if (ht == PCI_HEADER_TYPE_BRIDGE)
2840 {
2841 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2842 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2843 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2844 }
2845 else
2846 {
2847 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2848 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2849 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2850 }
2851 *last_br = b;
2852 last_br = &b->chain;
2853 b->next = b->child = NULL;
2854 b->first_bus = NULL;
2855 b->br_dev = d;
2856 }
2857 }
2858 *last_br = NULL;
2859
2860 /* Create a bridge tree */
2861
2862 for (b=&host_bridge; b; b=b->chain)
2863 {
2864 struct bridge *c, *best;
2865 best = NULL;
2866 for (c=&host_bridge; c; c=c->chain)
2867 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2868 b->primary >= c->secondary && b->primary <= c->subordinate &&
2869 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2870 best = c;
2871 if (best)
2872 {
2873 b->next = best->child;
2874 best->child = b;
2875 }
2876 }
2877
2878 /* Insert secondary bus for each bridge */
2879
2880 for (b=&host_bridge; b; b=b->chain)
2881 if (!find_bus(b, b->domain, b->secondary))
2882 new_bus(b, b->domain, b->secondary);
2883
2884 /* Create bus structs and link devices */
2885
2886 for (d=first_dev; d;)
2887 {
2888 d2 = d->next;
2889 insert_dev(d, &host_bridge);
2890 d = d2;
2891 }
2892 }
2893
2894 static void
2895 print_it(char *line, char *p)
2896 {
2897 *p++ = '\n';
2898 *p = 0;
2899 fputs(line, stdout);
2900 for (p=line; *p; p++)
2901 if (*p == '+' || *p == '|')
2902 *p = '|';
2903 else
2904 *p = ' ';
2905 }
2906
2907 static void show_tree_bridge(struct bridge *, char *, char *);
2908
2909 static void
2910 show_tree_dev(struct device *d, char *line, char *p)
2911 {
2912 struct pci_dev *q = d->dev;
2913 struct bridge *b;
2914 char namebuf[256];
2915
2916 p += sprintf(p, "%02x.%x", q->dev, q->func);
2917 for (b=&host_bridge; b; b=b->chain)
2918 if (b->br_dev == d)
2919 {
2920 if (b->secondary == b->subordinate)
2921 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2922 else
2923 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2924 show_tree_bridge(b, line, p);
2925 return;
2926 }
2927 if (verbose)
2928 p += sprintf(p, " %s",
2929 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2930 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2931 q->vendor_id, q->device_id));
2932 print_it(line, p);
2933 }
2934
2935 static void
2936 show_tree_bus(struct bus *b, char *line, char *p)
2937 {
2938 if (!b->first_dev)
2939 print_it(line, p);
2940 else if (!b->first_dev->next)
2941 {
2942 *p++ = '-';
2943 *p++ = '-';
2944 show_tree_dev(b->first_dev, line, p);
2945 }
2946 else
2947 {
2948 struct device *d = b->first_dev;
2949 while (d->next)
2950 {
2951 p[0] = '+';
2952 p[1] = '-';
2953 show_tree_dev(d, line, p+2);
2954 d = d->next;
2955 }
2956 p[0] = '\\';
2957 p[1] = '-';
2958 show_tree_dev(d, line, p+2);
2959 }
2960 }
2961
2962 static void
2963 show_tree_bridge(struct bridge *b, char *line, char *p)
2964 {
2965 *p++ = '-';
2966 if (!b->first_bus->sibling)
2967 {
2968 if (b == &host_bridge)
2969 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2970 show_tree_bus(b->first_bus, line, p);
2971 }
2972 else
2973 {
2974 struct bus *u = b->first_bus;
2975 char *k;
2976
2977 while (u->sibling)
2978 {
2979 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2980 show_tree_bus(u, line, k);
2981 u = u->sibling;
2982 }
2983 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2984 show_tree_bus(u, line, k);
2985 }
2986 }
2987
2988 static void
2989 show_forest(void)
2990 {
2991 char line[256];
2992
2993 grow_tree();
2994 show_tree_bridge(&host_bridge, line, line);
2995 }
2996
2997 /*** Bus mapping mode ***/
2998
2999 struct bus_bridge {
3000 struct bus_bridge *next;
3001 byte this, dev, func, first, last, bug;
3002 };
3003
3004 struct bus_info {
3005 byte exists;
3006 byte guestbook;
3007 struct bus_bridge *bridges, *via;
3008 };
3009
3010 static struct bus_info *bus_info;
3011
3012 static void
3013 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
3014 {
3015 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
3016 struct pci_dev *p = d->dev;
3017
3018 b->next = bi->bridges;
3019 bi->bridges = b;
3020 b->this = get_conf_byte(d, np);
3021 b->dev = p->dev;
3022 b->func = p->func;
3023 b->first = get_conf_byte(d, ns);
3024 b->last = get_conf_byte(d, nl);
3025 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
3026 p->bus, p->dev, p->func, b->this, b->first, b->last);
3027 if (b->this != p->bus)
3028 printf("!!! Bridge points to invalid primary bus.\n");
3029 if (b->first > b->last)
3030 {
3031 printf("!!! Bridge points to invalid bus range.\n");
3032 b->last = b->first;
3033 }
3034 }
3035
3036 static void
3037 do_map_bus(int bus)
3038 {
3039 int dev, func;
3040 int verbose = pacc->debugging;
3041 struct bus_info *bi = bus_info + bus;
3042 struct device *d;
3043
3044 if (verbose)
3045 printf("Mapping bus %02x\n", bus);
3046 for (dev = 0; dev < 32; dev++)
3047 if (filter.slot < 0 || filter.slot == dev)
3048 {
3049 int func_limit = 1;
3050 for (func = 0; func < func_limit; func++)
3051 if (filter.func < 0 || filter.func == func)
3052 {
3053 /* XXX: Bus mapping supports only domain 0 */
3054 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
3055 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
3056 if (vendor && vendor != 0xffff)
3057 {
3058 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
3059 func_limit = 8;
3060 if (verbose)
3061 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
3062 bi->exists = 1;
3063 if (d = scan_device(p))
3064 {
3065 show_device(d);
3066 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
3067 {
3068 case PCI_HEADER_TYPE_BRIDGE:
3069 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
3070 break;
3071 case PCI_HEADER_TYPE_CARDBUS:
3072 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
3073 break;
3074 }
3075 free(d);
3076 }
3077 else if (verbose)
3078 printf("But it was filtered out.\n");
3079 }
3080 pci_free_dev(p);
3081 }
3082 }
3083 }
3084
3085 static void
3086 do_map_bridges(int bus, int min, int max)
3087 {
3088 struct bus_info *bi = bus_info + bus;
3089 struct bus_bridge *b;
3090
3091 bi->guestbook = 1;
3092 for (b=bi->bridges; b; b=b->next)
3093 {
3094 if (bus_info[b->first].guestbook)
3095 b->bug = 1;
3096 else if (b->first < min || b->last > max)
3097 b->bug = 2;
3098 else
3099 {
3100 bus_info[b->first].via = b;
3101 do_map_bridges(b->first, b->first, b->last);
3102 }
3103 }
3104 }
3105
3106 static void
3107 map_bridges(void)
3108 {
3109 int i;
3110
3111 printf("\nSummary of buses:\n\n");
3112 for (i=0; i<256; i++)
3113 if (bus_info[i].exists && !bus_info[i].guestbook)
3114 do_map_bridges(i, 0, 255);
3115 for (i=0; i<256; i++)
3116 {
3117 struct bus_info *bi = bus_info + i;
3118 struct bus_bridge *b = bi->via;
3119
3120 if (bi->exists)
3121 {
3122 printf("%02x: ", i);
3123 if (b)
3124 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
3125 else if (!i)
3126 printf("Primary host bus\n");
3127 else
3128 printf("Secondary host bus (?)\n");
3129 }
3130 for (b=bi->bridges; b; b=b->next)
3131 {
3132 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
3133 switch (b->bug)
3134 {
3135 case 1:
3136 printf(" <overlap bug>");
3137 break;
3138 case 2:
3139 printf(" <crossing bug>");
3140 break;
3141 }
3142 putchar('\n');
3143 }
3144 }
3145 }
3146
3147 static void
3148 map_the_bus(void)
3149 {
3150 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
3151 pacc->method == PCI_ACCESS_DUMP)
3152 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
3153 bus_info = xmalloc(sizeof(struct bus_info) * 256);
3154 memset(bus_info, 0, sizeof(struct bus_info) * 256);
3155 if (filter.bus >= 0)
3156 do_map_bus(filter.bus);
3157 else
3158 {
3159 int bus;
3160 for (bus=0; bus<256; bus++)
3161 do_map_bus(bus);
3162 }
3163 map_bridges();
3164 }
3165
3166 /* Main */
3167
3168 int
3169 main(int argc, char **argv)
3170 {
3171 int i;
3172 char *msg;
3173
3174 if (argc == 2 && !strcmp(argv[1], "--version"))
3175 {
3176 puts("lspci version " PCIUTILS_VERSION);
3177 return 0;
3178 }
3179
3180 pacc = pci_alloc();
3181 pacc->error = die;
3182 pci_filter_init(pacc, &filter);
3183
3184 while ((i = getopt(argc, argv, options)) != -1)
3185 switch (i)
3186 {
3187 case 'n':
3188 pacc->numeric_ids++;
3189 break;
3190 case 'v':
3191 verbose++;
3192 break;
3193 case 'b':
3194 pacc->buscentric = 1;
3195 opt_buscentric = 1;
3196 break;
3197 case 's':
3198 if (msg = pci_filter_parse_slot(&filter, optarg))
3199 die("-s: %s", msg);
3200 break;
3201 case 'd':
3202 if (msg = pci_filter_parse_id(&filter, optarg))
3203 die("-d: %s", msg);
3204 break;
3205 case 'x':
3206 opt_hex++;
3207 break;
3208 case 't':
3209 opt_tree++;
3210 break;
3211 case 'i':
3212 pci_set_name_list_path(pacc, optarg, 0);
3213 break;
3214 case 'm':
3215 opt_machine++;
3216 break;
3217 case 'p':
3218 opt_pcimap = optarg;
3219 break;
3220 #ifdef PCI_OS_LINUX
3221 case 'k':
3222 opt_kernel++;
3223 break;
3224 #endif
3225 case 'M':
3226 opt_map_mode++;
3227 break;
3228 case 'D':
3229 opt_domains = 2;
3230 break;
3231 #ifdef PCI_USE_DNS
3232 case 'q':
3233 opt_query_dns++;
3234 break;
3235 case 'Q':
3236 opt_query_all = 1;
3237 break;
3238 #else
3239 case 'q':
3240 case 'Q':
3241 die("DNS queries are not available in this version");
3242 #endif
3243 default:
3244 if (parse_generic_option(i, pacc, optarg))
3245 break;
3246 bad:
3247 fprintf(stderr, help_msg, pacc->id_file_name);
3248 return 1;
3249 }
3250 if (optind < argc)
3251 goto bad;
3252
3253 if (opt_query_dns)
3254 {
3255 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
3256 if (opt_query_dns > 1)
3257 pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
3258 }
3259 if (opt_query_all)
3260 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
3261
3262 pci_init(pacc);
3263 if (opt_map_mode)
3264 map_the_bus();
3265 else
3266 {
3267 scan_devices();
3268 sort_them();
3269 if (opt_tree)
3270 show_forest();
3271 else
3272 show();
3273 }
3274 pci_cleanup(pacc);
3275
3276 return (seen_errors ? 2 : 0);
3277 }
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