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Implemented searching for kernel modules. Works, but needs cleanup.
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int opt_tree; /* Show bus tree */
24 static int opt_machine; /* Generate machine-readable output */
25 static int opt_map_mode; /* Bus mapping mode enabled */
26 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
28
29 const char program_name[] = "lspci";
30
31 static char options[] = "nvbxs:d:ti:mgp:MD" GENERIC_OPTIONS ;
32
33 static char help_msg[] = "\
34 Usage: lspci [<switches>]\n\
35 \n\
36 -v\t\tBe verbose\n\
37 -n\t\tShow numeric ID's\n\
38 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
39 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
40 -x\t\tShow hex-dump of the standard portion of config space\n\
41 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
42 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
43 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
44 -d [<vendor>]:[<device>]\tShow only selected devices\n\
45 -t\t\tShow bus tree\n\
46 -m\t\tProduce machine-readable output\n\
47 -i <file>\tUse specified ID database instead of %s\n"
48 #ifdef PCI_OS_LINUX
49 "\
50 -p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
51 #endif
52 "\
53 -D\t\tAlways show domain numbers\n\
54 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
55 GENERIC_HELP
56 ;
57
58 /*** Communication with libpci ***/
59
60 static struct pci_access *pacc;
61
62 /*
63 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
64 * This increases our memory footprint, but only slightly since we don't
65 * use alloca() much.
66 */
67 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
68 /* alloca() is defined in stdlib.h */
69 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
70 #include <alloca.h>
71 #else
72 #undef alloca
73 #define alloca xmalloc
74 #endif
75
76 /*** Our view of the PCI bus ***/
77
78 struct device {
79 struct device *next;
80 struct pci_dev *dev;
81 unsigned int config_cached, config_bufsize;
82 byte *config; /* Cached configuration space data */
83 byte *present; /* Maps which configuration bytes are present */
84 };
85
86 static struct device *first_dev;
87 static int seen_errors;
88
89 static int
90 config_fetch(struct device *d, unsigned int pos, unsigned int len)
91 {
92 unsigned int end = pos+len;
93 int result;
94
95 while (pos < d->config_bufsize && len && d->present[pos])
96 pos++, len--;
97 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
98 len--;
99 if (!len)
100 return 1;
101
102 if (end > d->config_bufsize)
103 {
104 int orig_size = d->config_bufsize;
105 while (end > d->config_bufsize)
106 d->config_bufsize *= 2;
107 d->config = xrealloc(d->config, d->config_bufsize);
108 d->present = xrealloc(d->present, d->config_bufsize);
109 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
110 }
111 result = pci_read_block(d->dev, pos, d->config + pos, len);
112 if (result)
113 memset(d->present + pos, 1, len);
114 return result;
115 }
116
117 static struct device *
118 scan_device(struct pci_dev *p)
119 {
120 struct device *d;
121
122 if (p->domain && !opt_domains)
123 opt_domains = 1;
124 if (!pci_filter_match(&filter, p))
125 return NULL;
126 d = xmalloc(sizeof(struct device));
127 memset(d, 0, sizeof(*d));
128 d->dev = p;
129 d->config_cached = d->config_bufsize = 64;
130 d->config = xmalloc(64);
131 d->present = xmalloc(64);
132 memset(d->present, 1, 64);
133 if (!pci_read_block(p, 0, d->config, 64))
134 {
135 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
136 p->domain, p->bus, p->dev, p->func);
137 seen_errors++;
138 return NULL;
139 }
140 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
141 {
142 /* For cardbus bridges, we need to fetch 64 bytes more to get the
143 * full standard header... */
144 if (config_fetch(d, 64, 64))
145 d->config_cached += 64;
146 }
147 pci_setup_cache(p, d->config, d->config_cached);
148 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
149 return d;
150 }
151
152 static void
153 scan_devices(void)
154 {
155 struct device *d;
156 struct pci_dev *p;
157
158 pci_scan_bus(pacc);
159 for(p=pacc->devices; p; p=p->next)
160 if (d = scan_device(p))
161 {
162 d->next = first_dev;
163 first_dev = d;
164 }
165 }
166
167 /*** Config space accesses ***/
168
169 static void
170 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
171 {
172 while (len)
173 if (!d->present[pos])
174 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
175 else
176 pos++, len--;
177 }
178
179 static inline byte
180 get_conf_byte(struct device *d, unsigned int pos)
181 {
182 check_conf_range(d, pos, 1);
183 return d->config[pos];
184 }
185
186 static word
187 get_conf_word(struct device *d, unsigned int pos)
188 {
189 check_conf_range(d, pos, 2);
190 return d->config[pos] | (d->config[pos+1] << 8);
191 }
192
193 static u32
194 get_conf_long(struct device *d, unsigned int pos)
195 {
196 check_conf_range(d, pos, 4);
197 return d->config[pos] |
198 (d->config[pos+1] << 8) |
199 (d->config[pos+2] << 16) |
200 (d->config[pos+3] << 24);
201 }
202
203 /*** Sorting ***/
204
205 static int
206 compare_them(const void *A, const void *B)
207 {
208 const struct pci_dev *a = (*(const struct device **)A)->dev;
209 const struct pci_dev *b = (*(const struct device **)B)->dev;
210
211 if (a->domain < b->domain)
212 return -1;
213 if (a->domain > b->domain)
214 return 1;
215 if (a->bus < b->bus)
216 return -1;
217 if (a->bus > b->bus)
218 return 1;
219 if (a->dev < b->dev)
220 return -1;
221 if (a->dev > b->dev)
222 return 1;
223 if (a->func < b->func)
224 return -1;
225 if (a->func > b->func)
226 return 1;
227 return 0;
228 }
229
230 static void
231 sort_them(void)
232 {
233 struct device **index, **h, **last_dev;
234 int cnt;
235 struct device *d;
236
237 cnt = 0;
238 for(d=first_dev; d; d=d->next)
239 cnt++;
240 h = index = alloca(sizeof(struct device *) * cnt);
241 for(d=first_dev; d; d=d->next)
242 *h++ = d;
243 qsort(index, cnt, sizeof(struct device *), compare_them);
244 last_dev = &first_dev;
245 h = index;
246 while (cnt--)
247 {
248 *last_dev = *h;
249 last_dev = &(*h)->next;
250 h++;
251 }
252 *last_dev = NULL;
253 }
254
255 /*** Normal output ***/
256
257 #define FLAG(x,y) ((x & y) ? '+' : '-')
258
259 static void
260 show_slot_name(struct device *d)
261 {
262 struct pci_dev *p = d->dev;
263
264 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
265 printf("%04x:", p->domain);
266 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
267 }
268
269 static void
270 show_terse(struct device *d)
271 {
272 int c;
273 struct pci_dev *p = d->dev;
274 char classbuf[128], devbuf[128];
275
276 show_slot_name(d);
277 printf(" %s: %s",
278 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
279 PCI_LOOKUP_CLASS,
280 p->device_class),
281 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
282 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
283 p->vendor_id, p->device_id));
284 if (c = get_conf_byte(d, PCI_REVISION_ID))
285 printf(" (rev %02x)", c);
286 if (verbose)
287 {
288 char *x;
289 c = get_conf_byte(d, PCI_CLASS_PROG);
290 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
291 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
292 p->device_class, c);
293 if (c || x)
294 {
295 printf(" (prog-if %02x", c);
296 if (x)
297 printf(" [%s]", x);
298 putchar(')');
299 }
300 }
301 putchar('\n');
302 }
303
304 static void
305 get_subid(struct device *d, word *subvp, word *subdp)
306 {
307 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
308
309 if (htype == PCI_HEADER_TYPE_NORMAL)
310 {
311 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
312 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
313 }
314 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
315 {
316 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
317 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
318 }
319 else
320 *subvp = *subdp = 0xffff;
321 }
322
323 /*** Capabilities ***/
324
325 static void
326 cap_pm(struct device *d, int where, int cap)
327 {
328 int t, b;
329 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
330
331 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
332 if (verbose < 2)
333 return;
334 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
335 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
336 FLAG(cap, PCI_PM_CAP_DSI),
337 FLAG(cap, PCI_PM_CAP_D1),
338 FLAG(cap, PCI_PM_CAP_D2),
339 pm_aux_current[(cap >> 6) & 7],
340 FLAG(cap, PCI_PM_CAP_PME_D0),
341 FLAG(cap, PCI_PM_CAP_PME_D1),
342 FLAG(cap, PCI_PM_CAP_PME_D2),
343 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
344 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
345 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
346 return;
347 t = get_conf_word(d, where + PCI_PM_CTRL);
348 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
349 t & PCI_PM_CTRL_STATE_MASK,
350 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
351 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
352 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
353 FLAG(t, PCI_PM_CTRL_PME_STATUS));
354 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
355 if (b)
356 printf("\t\tBridge: PM%c B3%c\n",
357 FLAG(t, PCI_PM_BPCC_ENABLE),
358 FLAG(~t, PCI_PM_PPB_B2_B3));
359 }
360
361 static void
362 format_agp_rate(int rate, char *buf, int agp3)
363 {
364 char *c = buf;
365 int i;
366
367 for(i=0; i<=2; i++)
368 if (rate & (1 << i))
369 {
370 if (c != buf)
371 *c++ = ',';
372 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
373 }
374 if (c != buf)
375 *c = 0;
376 else
377 strcpy(buf, "<none>");
378 }
379
380 static void
381 cap_agp(struct device *d, int where, int cap)
382 {
383 u32 t;
384 char rate[16];
385 int ver, rev;
386 int agp3 = 0;
387
388 ver = (cap >> 4) & 0x0f;
389 rev = cap & 0x0f;
390 printf("AGP version %x.%x\n", ver, rev);
391 if (verbose < 2)
392 return;
393 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
394 return;
395 t = get_conf_long(d, where + PCI_AGP_STATUS);
396 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
397 agp3 = 1;
398 format_agp_rate(t & 7, rate, agp3);
399 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
400 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
401 FLAG(t, PCI_AGP_STATUS_ISOCH),
402 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
403 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
404 FLAG(t, PCI_AGP_STATUS_SBA),
405 FLAG(t, PCI_AGP_STATUS_ITA_COH),
406 FLAG(t, PCI_AGP_STATUS_GART64),
407 FLAG(t, PCI_AGP_STATUS_HTRANS),
408 FLAG(t, PCI_AGP_STATUS_64BIT),
409 FLAG(t, PCI_AGP_STATUS_FW),
410 FLAG(t, PCI_AGP_STATUS_AGP3),
411 rate);
412 t = get_conf_long(d, where + PCI_AGP_COMMAND);
413 format_agp_rate(t & 7, rate, agp3);
414 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
415 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
416 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
417 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
418 FLAG(t, PCI_AGP_COMMAND_SBA),
419 FLAG(t, PCI_AGP_COMMAND_AGP),
420 FLAG(t, PCI_AGP_COMMAND_GART64),
421 FLAG(t, PCI_AGP_COMMAND_64BIT),
422 FLAG(t, PCI_AGP_COMMAND_FW),
423 rate);
424 }
425
426 static void
427 cap_pcix_nobridge(struct device *d, int where)
428 {
429 u16 command;
430 u32 status;
431 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
432
433 printf("PCI-X non-bridge device\n");
434
435 if (verbose < 2)
436 return;
437
438 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
439 return;
440
441 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
442 status = get_conf_long(d, where + PCI_PCIX_STATUS);
443 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
444 FLAG(command, PCI_PCIX_COMMAND_DPERE),
445 FLAG(command, PCI_PCIX_COMMAND_ERO),
446 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
447 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
448 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
449 ((status >> 8) & 0xff),
450 ((status >> 3) & 0x1f),
451 (status & PCI_PCIX_STATUS_FUNCTION),
452 FLAG(status, PCI_PCIX_STATUS_64BIT),
453 FLAG(status, PCI_PCIX_STATUS_133MHZ),
454 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
455 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
456 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
457 1 << (9 + ((status >> 21) & 3U)),
458 max_outstanding[(status >> 23) & 7U],
459 1 << (3 + ((status >> 26) & 7U)),
460 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
461 FLAG(status, PCI_PCIX_STATUS_266MHZ),
462 FLAG(status, PCI_PCIX_STATUS_533MHZ));
463 }
464
465 static void
466 cap_pcix_bridge(struct device *d, int where)
467 {
468 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
469 u16 secstatus;
470 u32 status, upstcr, downstcr;
471
472 printf("PCI-X bridge device\n");
473
474 if (verbose < 2)
475 return;
476
477 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
478 return;
479
480 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
481 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
482 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
483 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
484 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
485 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
486 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
487 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
488 sec_clock_freq[(secstatus >> 6) & 7]);
489 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
490 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
491 ((status >> 8) & 0xff),
492 ((status >> 3) & 0x1f),
493 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
494 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
495 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
496 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
497 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
498 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
499 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
500 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
501 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
502 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
503 (upstcr >> 16) & 0xffff);
504 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
505 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
506 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
507 (downstcr >> 16) & 0xffff);
508 }
509
510 static void
511 cap_pcix(struct device *d, int where)
512 {
513 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
514 {
515 case PCI_HEADER_TYPE_NORMAL:
516 cap_pcix_nobridge(d, where);
517 break;
518 case PCI_HEADER_TYPE_BRIDGE:
519 cap_pcix_bridge(d, where);
520 break;
521 }
522 }
523
524 static inline char *
525 ht_link_width(unsigned width)
526 {
527 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
528 return widths[width];
529 }
530
531 static inline char *
532 ht_link_freq(unsigned freq)
533 {
534 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
535 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
536 return freqs[freq];
537 }
538
539 static void
540 cap_ht_pri(struct device *d, int where, int cmd)
541 {
542 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
543 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
544 char *fmt;
545
546 printf("HyperTransport: Slave or Primary Interface\n");
547 if (verbose < 2)
548 return;
549
550 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
551 return;
552 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
553 if (rid < 0x23 && rid > 0x11)
554 printf("\t\t!!! Possibly incomplete decoding\n");
555
556 if (rid >= 0x23)
557 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
558 else
559 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
560 printf(fmt,
561 (cmd & PCI_HT_PRI_CMD_BUID),
562 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
563 FLAG(cmd, PCI_HT_PRI_CMD_MH),
564 FLAG(cmd, PCI_HT_PRI_CMD_DD),
565 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
566 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
567 if (rid >= 0x23)
568 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
569 else
570 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
571 printf(fmt,
572 FLAG(lctr0, PCI_HT_LCTR_CFLE),
573 FLAG(lctr0, PCI_HT_LCTR_CST),
574 FLAG(lctr0, PCI_HT_LCTR_CFE),
575 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
576 FLAG(lctr0, PCI_HT_LCTR_INIT),
577 FLAG(lctr0, PCI_HT_LCTR_EOC),
578 FLAG(lctr0, PCI_HT_LCTR_TXO),
579 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
580 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
581 FLAG(lctr0, PCI_HT_LCTR_LSEN),
582 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
583 FLAG(lctr0, PCI_HT_LCTR_64B));
584 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
585 if (rid >= 0x23)
586 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
587 else
588 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
589 printf(fmt,
590 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
591 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
592 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
593 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
594 FLAG(lcnf0, PCI_HT_LCNF_DFI),
595 FLAG(lcnf0, PCI_HT_LCNF_DFO),
596 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
597 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
598 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
599 if (rid >= 0x23)
600 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
601 else
602 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
603 printf(fmt,
604 FLAG(lctr1, PCI_HT_LCTR_CFLE),
605 FLAG(lctr1, PCI_HT_LCTR_CST),
606 FLAG(lctr1, PCI_HT_LCTR_CFE),
607 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
608 FLAG(lctr1, PCI_HT_LCTR_INIT),
609 FLAG(lctr1, PCI_HT_LCTR_EOC),
610 FLAG(lctr1, PCI_HT_LCTR_TXO),
611 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
612 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
613 FLAG(lctr1, PCI_HT_LCTR_LSEN),
614 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
615 FLAG(lctr1, PCI_HT_LCTR_64B));
616 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
617 if (rid >= 0x23)
618 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
619 else
620 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
621 printf(fmt,
622 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
623 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
624 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
625 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
626 FLAG(lcnf1, PCI_HT_LCNF_DFI),
627 FLAG(lcnf1, PCI_HT_LCNF_DFO),
628 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
629 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
630 printf("\t\tRevision ID: %u.%02u\n",
631 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
632 if (rid < 0x23)
633 return;
634 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
635 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
636 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
637 FLAG(lfrer0, PCI_HT_LFRER_PROT),
638 FLAG(lfrer0, PCI_HT_LFRER_OV),
639 FLAG(lfrer0, PCI_HT_LFRER_EOC),
640 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
641 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
642 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
643 FLAG(lfcap0, PCI_HT_LFCAP_200),
644 FLAG(lfcap0, PCI_HT_LFCAP_300),
645 FLAG(lfcap0, PCI_HT_LFCAP_400),
646 FLAG(lfcap0, PCI_HT_LFCAP_500),
647 FLAG(lfcap0, PCI_HT_LFCAP_600),
648 FLAG(lfcap0, PCI_HT_LFCAP_800),
649 FLAG(lfcap0, PCI_HT_LFCAP_1000),
650 FLAG(lfcap0, PCI_HT_LFCAP_1200),
651 FLAG(lfcap0, PCI_HT_LFCAP_1400),
652 FLAG(lfcap0, PCI_HT_LFCAP_1600),
653 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
654 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
655 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
656 FLAG(ftr, PCI_HT_FTR_ISOCFC),
657 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
658 FLAG(ftr, PCI_HT_FTR_CRCTM),
659 FLAG(ftr, PCI_HT_FTR_ECTLT),
660 FLAG(ftr, PCI_HT_FTR_64BA),
661 FLAG(ftr, PCI_HT_FTR_UIDRD));
662 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
663 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
664 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
665 FLAG(lfrer1, PCI_HT_LFRER_PROT),
666 FLAG(lfrer1, PCI_HT_LFRER_OV),
667 FLAG(lfrer1, PCI_HT_LFRER_EOC),
668 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
669 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
670 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
671 FLAG(lfcap1, PCI_HT_LFCAP_200),
672 FLAG(lfcap1, PCI_HT_LFCAP_300),
673 FLAG(lfcap1, PCI_HT_LFCAP_400),
674 FLAG(lfcap1, PCI_HT_LFCAP_500),
675 FLAG(lfcap1, PCI_HT_LFCAP_600),
676 FLAG(lfcap1, PCI_HT_LFCAP_800),
677 FLAG(lfcap1, PCI_HT_LFCAP_1000),
678 FLAG(lfcap1, PCI_HT_LFCAP_1200),
679 FLAG(lfcap1, PCI_HT_LFCAP_1400),
680 FLAG(lfcap1, PCI_HT_LFCAP_1600),
681 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
682 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
683 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
684 FLAG(eh, PCI_HT_EH_PFLE),
685 FLAG(eh, PCI_HT_EH_OFLE),
686 FLAG(eh, PCI_HT_EH_PFE),
687 FLAG(eh, PCI_HT_EH_OFE),
688 FLAG(eh, PCI_HT_EH_EOCFE),
689 FLAG(eh, PCI_HT_EH_RFE),
690 FLAG(eh, PCI_HT_EH_CRCFE),
691 FLAG(eh, PCI_HT_EH_SERRFE),
692 FLAG(eh, PCI_HT_EH_CF),
693 FLAG(eh, PCI_HT_EH_RE),
694 FLAG(eh, PCI_HT_EH_PNFE),
695 FLAG(eh, PCI_HT_EH_ONFE),
696 FLAG(eh, PCI_HT_EH_EOCNFE),
697 FLAG(eh, PCI_HT_EH_RNFE),
698 FLAG(eh, PCI_HT_EH_CRCNFE),
699 FLAG(eh, PCI_HT_EH_SERRNFE));
700 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
701 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
702 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
703 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
704 printf("\t\tBus Number: %02x\n", bn);
705 }
706
707 static void
708 cap_ht_sec(struct device *d, int where, int cmd)
709 {
710 u16 lctr, lcnf, ftr, eh;
711 u8 rid, lfrer, lfcap, mbu, mlu;
712 char *fmt;
713
714 printf("HyperTransport: Host or Secondary Interface\n");
715 if (verbose < 2)
716 return;
717
718 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
719 return;
720 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
721 if (rid < 0x23 && rid > 0x11)
722 printf("\t\t!!! Possibly incomplete decoding\n");
723
724 if (rid >= 0x23)
725 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
726 else
727 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
728 printf(fmt,
729 FLAG(cmd, PCI_HT_SEC_CMD_WR),
730 FLAG(cmd, PCI_HT_SEC_CMD_DE),
731 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
732 FLAG(cmd, PCI_HT_SEC_CMD_CS),
733 FLAG(cmd, PCI_HT_SEC_CMD_HH),
734 FLAG(cmd, PCI_HT_SEC_CMD_AS),
735 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
736 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
737 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
738 if (rid >= 0x23)
739 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
740 else
741 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
742 printf(fmt,
743 FLAG(lctr, PCI_HT_LCTR_CFLE),
744 FLAG(lctr, PCI_HT_LCTR_CST),
745 FLAG(lctr, PCI_HT_LCTR_CFE),
746 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
747 FLAG(lctr, PCI_HT_LCTR_INIT),
748 FLAG(lctr, PCI_HT_LCTR_EOC),
749 FLAG(lctr, PCI_HT_LCTR_TXO),
750 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
751 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
752 FLAG(lctr, PCI_HT_LCTR_LSEN),
753 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
754 FLAG(lctr, PCI_HT_LCTR_64B));
755 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
756 if (rid >= 0x23)
757 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
758 else
759 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
760 printf(fmt,
761 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
762 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
763 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
764 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
765 FLAG(lcnf, PCI_HT_LCNF_DFI),
766 FLAG(lcnf, PCI_HT_LCNF_DFO),
767 FLAG(lcnf, PCI_HT_LCNF_DFIE),
768 FLAG(lcnf, PCI_HT_LCNF_DFOE));
769 printf("\t\tRevision ID: %u.%02u\n",
770 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
771 if (rid < 0x23)
772 return;
773 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
774 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
775 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
776 FLAG(lfrer, PCI_HT_LFRER_PROT),
777 FLAG(lfrer, PCI_HT_LFRER_OV),
778 FLAG(lfrer, PCI_HT_LFRER_EOC),
779 FLAG(lfrer, PCI_HT_LFRER_CTLT));
780 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
781 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
782 FLAG(lfcap, PCI_HT_LFCAP_200),
783 FLAG(lfcap, PCI_HT_LFCAP_300),
784 FLAG(lfcap, PCI_HT_LFCAP_400),
785 FLAG(lfcap, PCI_HT_LFCAP_500),
786 FLAG(lfcap, PCI_HT_LFCAP_600),
787 FLAG(lfcap, PCI_HT_LFCAP_800),
788 FLAG(lfcap, PCI_HT_LFCAP_1000),
789 FLAG(lfcap, PCI_HT_LFCAP_1200),
790 FLAG(lfcap, PCI_HT_LFCAP_1400),
791 FLAG(lfcap, PCI_HT_LFCAP_1600),
792 FLAG(lfcap, PCI_HT_LFCAP_VEND));
793 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
794 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
795 FLAG(ftr, PCI_HT_FTR_ISOCFC),
796 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
797 FLAG(ftr, PCI_HT_FTR_CRCTM),
798 FLAG(ftr, PCI_HT_FTR_ECTLT),
799 FLAG(ftr, PCI_HT_FTR_64BA),
800 FLAG(ftr, PCI_HT_FTR_UIDRD),
801 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
802 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
803 if (ftr & PCI_HT_SEC_FTR_EXTRS)
804 {
805 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
806 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
807 FLAG(eh, PCI_HT_EH_PFLE),
808 FLAG(eh, PCI_HT_EH_OFLE),
809 FLAG(eh, PCI_HT_EH_PFE),
810 FLAG(eh, PCI_HT_EH_OFE),
811 FLAG(eh, PCI_HT_EH_EOCFE),
812 FLAG(eh, PCI_HT_EH_RFE),
813 FLAG(eh, PCI_HT_EH_CRCFE),
814 FLAG(eh, PCI_HT_EH_SERRFE),
815 FLAG(eh, PCI_HT_EH_CF),
816 FLAG(eh, PCI_HT_EH_RE),
817 FLAG(eh, PCI_HT_EH_PNFE),
818 FLAG(eh, PCI_HT_EH_ONFE),
819 FLAG(eh, PCI_HT_EH_EOCNFE),
820 FLAG(eh, PCI_HT_EH_RNFE),
821 FLAG(eh, PCI_HT_EH_CRCNFE),
822 FLAG(eh, PCI_HT_EH_SERRNFE));
823 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
824 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
825 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
826 }
827 }
828
829 static void
830 cap_ht(struct device *d, int where, int cmd)
831 {
832 int type;
833
834 switch (cmd & PCI_HT_CMD_TYP_HI)
835 {
836 case PCI_HT_CMD_TYP_HI_PRI:
837 cap_ht_pri(d, where, cmd);
838 return;
839 case PCI_HT_CMD_TYP_HI_SEC:
840 cap_ht_sec(d, where, cmd);
841 return;
842 }
843
844 type = cmd & PCI_HT_CMD_TYP;
845 switch (type)
846 {
847 case PCI_HT_CMD_TYP_SW:
848 printf("HyperTransport: Switch\n");
849 break;
850 case PCI_HT_CMD_TYP_IDC:
851 printf("HyperTransport: Interrupt Discovery and Configuration\n");
852 break;
853 case PCI_HT_CMD_TYP_RID:
854 printf("HyperTransport: Revision ID: %u.%02u\n",
855 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
856 break;
857 case PCI_HT_CMD_TYP_UIDC:
858 printf("HyperTransport: UnitID Clumping\n");
859 break;
860 case PCI_HT_CMD_TYP_ECSA:
861 printf("HyperTransport: Extended Configuration Space Access\n");
862 break;
863 case PCI_HT_CMD_TYP_AM:
864 printf("HyperTransport: Address Mapping\n");
865 break;
866 case PCI_HT_CMD_TYP_MSIM:
867 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
868 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
869 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
870 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
871 {
872 u32 offl, offh;
873 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
874 break;
875 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
876 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
877 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
878 }
879 break;
880 case PCI_HT_CMD_TYP_DR:
881 printf("HyperTransport: DirectRoute\n");
882 break;
883 case PCI_HT_CMD_TYP_VCS:
884 printf("HyperTransport: VCSet\n");
885 break;
886 case PCI_HT_CMD_TYP_RM:
887 printf("HyperTransport: Retry Mode\n");
888 break;
889 case PCI_HT_CMD_TYP_X86:
890 printf("HyperTransport: X86 (reserved)\n");
891 break;
892 default:
893 printf("HyperTransport: #%02x\n", type >> 11);
894 }
895 }
896
897 static void
898 cap_msi(struct device *d, int where, int cap)
899 {
900 int is64;
901 u32 t;
902 u16 w;
903
904 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
905 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
906 FLAG(cap, PCI_MSI_FLAGS_64BIT),
907 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
908 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
909 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
910 if (verbose < 2)
911 return;
912 is64 = cap & PCI_MSI_FLAGS_64BIT;
913 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
914 return;
915 printf("\t\tAddress: ");
916 if (is64)
917 {
918 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
919 w = get_conf_word(d, where + PCI_MSI_DATA_64);
920 printf("%08x", t);
921 }
922 else
923 w = get_conf_word(d, where + PCI_MSI_DATA_32);
924 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
925 printf("%08x Data: %04x\n", t, w);
926 if (cap & PCI_MSI_FLAGS_MASK_BIT)
927 {
928 u32 mask, pending;
929
930 if (is64)
931 {
932 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
933 return;
934 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
935 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
936 }
937 else
938 {
939 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
940 return;
941 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
942 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
943 }
944 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
945 }
946 }
947
948 static float power_limit(int value, int scale)
949 {
950 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
951 return value * scales[scale];
952 }
953
954 static const char *latency_l0s(int value)
955 {
956 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
957 return latencies[value];
958 }
959
960 static const char *latency_l1(int value)
961 {
962 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
963 return latencies[value];
964 }
965
966 static void cap_express_dev(struct device *d, int where, int type)
967 {
968 u32 t;
969 u16 w;
970
971 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
972 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
973 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
974 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
975 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
976 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
977 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
978 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
979 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
980 printf(" AttnBtn%c AttnInd%c PwrInd%c",
981 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
982 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
983 printf(" RBE%c FLReset%c",
984 FLAG(t, PCI_EXP_DEVCAP_RBE),
985 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
986 if (type == PCI_EXP_TYPE_UPSTREAM)
987 printf("SlotPowerLimit %fW",
988 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
989 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
990 printf("\n");
991
992 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
993 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
994 FLAG(w, PCI_EXP_DEVCTL_CERE),
995 FLAG(w, PCI_EXP_DEVCTL_NFERE),
996 FLAG(w, PCI_EXP_DEVCTL_FERE),
997 FLAG(w, PCI_EXP_DEVCTL_URRE));
998 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
999 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1000 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1001 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1002 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1003 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1004 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1005 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1006 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1007 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1008 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1009 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1010 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1011
1012 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1013 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1014 FLAG(w, PCI_EXP_DEVSTA_CED),
1015 FLAG(w, PCI_EXP_DEVSTA_NFED),
1016 FLAG(w, PCI_EXP_DEVSTA_FED),
1017 FLAG(w, PCI_EXP_DEVSTA_URD),
1018 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1019 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1020
1021 /* FIXME: Second set of control/status registers is not supported yet. */
1022 }
1023
1024 static char *link_speed(int speed)
1025 {
1026 switch (speed)
1027 {
1028 case 1:
1029 return "2.5GT/s";
1030 case 2:
1031 return "5GT/s";
1032 default:
1033 return "unknown";
1034 }
1035 }
1036
1037 static char *aspm_support(int code)
1038 {
1039 switch (code)
1040 {
1041 case 1:
1042 return "L0s";
1043 case 3:
1044 return "L0s L1";
1045 default:
1046 return "unknown";
1047 }
1048 }
1049
1050 static const char *aspm_enabled(int code)
1051 {
1052 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1053 return desc[code];
1054 }
1055
1056 static void cap_express_link(struct device *d, int where, int type)
1057 {
1058 u32 t;
1059 u16 w;
1060
1061 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1062 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1063 t >> 24,
1064 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1065 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1066 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1067 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1068 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1069 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1070 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1071 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1072 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1073
1074 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1075 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1076 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1077 (type == PCI_EXP_TYPE_LEG_END))
1078 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1079 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1080 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1081 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1082 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1083 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1084 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1085 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1086 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1087 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1088
1089 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1090 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1091 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1092 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1093 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1094 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1095 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1096 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1097 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1098 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1099 }
1100
1101 static const char *indicator(int code)
1102 {
1103 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1104 return names[code];
1105 }
1106
1107 static void cap_express_slot(struct device *d, int where)
1108 {
1109 u32 t;
1110 u16 w;
1111
1112 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1113 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1114 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1115 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1116 FLAG(t, PCI_EXP_SLTCAP_MRL),
1117 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1118 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1119 FLAG(t, PCI_EXP_SLTCAP_HPC),
1120 FLAG(t, PCI_EXP_SLTCAP_HPS));
1121 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1122 t >> 19,
1123 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1124 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1125 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1126
1127 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1128 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1129 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1130 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1131 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1132 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1133 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1134 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1135 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1136 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1137 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1138 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1139 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1140 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1141
1142 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1143 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1144 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1145 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1146 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1147 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1148 FLAG(w, PCI_EXP_SLTSTA_PRES),
1149 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1150 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1151 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1152 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1153 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1154 }
1155
1156 static void cap_express_root(struct device *d, int where)
1157 {
1158 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1159 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1160 FLAG(w, PCI_EXP_RTCTL_SECEE),
1161 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1162 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1163 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1164 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1165
1166 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1167 printf("\t\tRootCap: CRSVisible%c\n",
1168 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1169
1170 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1171 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1172 w & PCI_EXP_RTSTA_PME_REQID,
1173 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1174 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1175 }
1176
1177 static void
1178 cap_express(struct device *d, int where, int cap)
1179 {
1180 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1181 int size;
1182 int slot = 0;
1183
1184 printf("Express ");
1185 if (verbose >= 2)
1186 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1187 switch (type)
1188 {
1189 case PCI_EXP_TYPE_ENDPOINT:
1190 printf("Endpoint");
1191 break;
1192 case PCI_EXP_TYPE_LEG_END:
1193 printf("Legacy Endpoint");
1194 break;
1195 case PCI_EXP_TYPE_ROOT_PORT:
1196 slot = cap & PCI_EXP_FLAGS_SLOT;
1197 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1198 break;
1199 case PCI_EXP_TYPE_UPSTREAM:
1200 printf("Upstream Port");
1201 break;
1202 case PCI_EXP_TYPE_DOWNSTREAM:
1203 slot = cap & PCI_EXP_FLAGS_SLOT;
1204 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1205 break;
1206 case PCI_EXP_TYPE_PCI_BRIDGE:
1207 printf("PCI/PCI-X Bridge");
1208 break;
1209 case PCI_EXP_TYPE_PCIE_BRIDGE:
1210 printf("PCI/PCI-X to PCI-Express Bridge");
1211 break;
1212 case PCI_EXP_TYPE_ROOT_INT_EP:
1213 printf("Root Complex Integrated Endpoint");
1214 break;
1215 case PCI_EXP_TYPE_ROOT_EC:
1216 printf("Root Complex Event Collector");
1217 break;
1218 default:
1219 printf("Unknown type %d", type);
1220 }
1221 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1222 if (verbose < 2)
1223 return;
1224
1225 size = 16;
1226 if (slot)
1227 size = 24;
1228 if (type == PCI_EXP_TYPE_ROOT_PORT)
1229 size = 32;
1230 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1231 return;
1232
1233 cap_express_dev(d, where, type);
1234 cap_express_link(d, where, type);
1235 if (slot)
1236 cap_express_slot(d, where);
1237 if (type == PCI_EXP_TYPE_ROOT_PORT)
1238 cap_express_root(d, where);
1239 }
1240
1241 static void
1242 cap_msix(struct device *d, int where, int cap)
1243 {
1244 u32 off;
1245
1246 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1247 FLAG(cap, PCI_MSIX_ENABLE),
1248 FLAG(cap, PCI_MSIX_MASK),
1249 (cap & PCI_MSIX_TABSIZE) + 1);
1250 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1251 return;
1252
1253 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1254 printf("\t\tVector table: BAR=%d offset=%08x\n",
1255 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1256 off = get_conf_long(d, where + PCI_MSIX_PBA);
1257 printf("\t\tPBA: BAR=%d offset=%08x\n",
1258 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1259 }
1260
1261 static void
1262 cap_slotid(int cap)
1263 {
1264 int esr = cap & 0xff;
1265 int chs = cap >> 8;
1266
1267 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1268 esr & PCI_SID_ESR_NSLOTS,
1269 FLAG(esr, PCI_SID_ESR_FIC),
1270 chs);
1271 }
1272
1273 static void
1274 cap_ssvid(struct device *d, int where)
1275 {
1276 u16 subsys_v, subsys_d;
1277 char ssnamebuf[256];
1278
1279 if (!config_fetch(d, where, 8))
1280 return;
1281 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1282 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1283 printf("Subsystem: %s\n",
1284 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1285 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1286 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1287 }
1288
1289 static void
1290 cap_dsn(struct device *d, int where)
1291 {
1292 u32 t1, t2;
1293 if (!config_fetch(d, where + 4, 8))
1294 return;
1295 t1 = get_conf_long(d, where + 4);
1296 t2 = get_conf_long(d, where + 8);
1297 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1298 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1299 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1300 }
1301
1302 static void
1303 cap_debug_port(int cap)
1304 {
1305 int bar = cap >> 13;
1306 int pos = cap & 0x1fff;
1307 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1308 }
1309
1310 static void
1311 show_ext_caps(struct device *d)
1312 {
1313 int where = 0x100;
1314 char been_there[0x1000];
1315 memset(been_there, 0, 0x1000);
1316 do
1317 {
1318 u32 header;
1319 int id;
1320
1321 if (!config_fetch(d, where, 4))
1322 break;
1323 header = get_conf_long(d, where);
1324 if (!header)
1325 break;
1326 id = header & 0xffff;
1327 printf("\tCapabilities: [%03x] ", where);
1328 if (been_there[where]++)
1329 {
1330 printf("<chain looped>\n");
1331 break;
1332 }
1333 switch (id)
1334 {
1335 case PCI_EXT_CAP_ID_AER:
1336 printf("Advanced Error Reporting <?>\n");
1337 break;
1338 case PCI_EXT_CAP_ID_VC:
1339 printf("Virtual Channel <?>\n");
1340 break;
1341 case PCI_EXT_CAP_ID_DSN:
1342 cap_dsn(d, where);
1343 break;
1344 case PCI_EXT_CAP_ID_PB:
1345 printf("Power Budgeting <?>\n");
1346 break;
1347 case PCI_EXT_CAP_ID_RCLINK:
1348 printf("Root Complex Link <?>\n");
1349 break;
1350 case PCI_EXT_CAP_ID_RCILINK:
1351 printf("Root Complex Internal Link <?>\n");
1352 break;
1353 case PCI_EXT_CAP_ID_RCECOLL:
1354 printf("Root Complex Event Collector <?>\n");
1355 break;
1356 case PCI_EXT_CAP_ID_MFVC:
1357 printf("Multi-Function Virtual Channel <?>\n");
1358 break;
1359 case PCI_EXT_CAP_ID_RBCB:
1360 printf("Root Bridge Control Block <?>\n");
1361 break;
1362 case PCI_EXT_CAP_ID_VNDR:
1363 printf("Vendor Specific Information <?>\n");
1364 break;
1365 case PCI_EXT_CAP_ID_ACS:
1366 printf("Access Controls <?>\n");
1367 break;
1368 default:
1369 printf("#%02x\n", id);
1370 break;
1371 }
1372 where = header >> 20;
1373 } while (where);
1374 }
1375
1376 static void
1377 show_caps(struct device *d)
1378 {
1379 int can_have_ext_caps = 0;
1380
1381 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1382 {
1383 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1384 byte been_there[256];
1385 memset(been_there, 0, 256);
1386 while (where)
1387 {
1388 int id, next, cap;
1389 printf("\tCapabilities: ");
1390 if (!config_fetch(d, where, 4))
1391 {
1392 puts("<access denied>");
1393 break;
1394 }
1395 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1396 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1397 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1398 printf("[%02x] ", where);
1399 if (been_there[where]++)
1400 {
1401 printf("<chain looped>\n");
1402 break;
1403 }
1404 if (id == 0xff)
1405 {
1406 printf("<chain broken>\n");
1407 break;
1408 }
1409 switch (id)
1410 {
1411 case PCI_CAP_ID_PM:
1412 cap_pm(d, where, cap);
1413 break;
1414 case PCI_CAP_ID_AGP:
1415 cap_agp(d, where, cap);
1416 break;
1417 case PCI_CAP_ID_VPD:
1418 printf("Vital Product Data <?>\n");
1419 break;
1420 case PCI_CAP_ID_SLOTID:
1421 cap_slotid(cap);
1422 break;
1423 case PCI_CAP_ID_MSI:
1424 cap_msi(d, where, cap);
1425 break;
1426 case PCI_CAP_ID_CHSWP:
1427 printf("CompactPCI hot-swap <?>\n");
1428 break;
1429 case PCI_CAP_ID_PCIX:
1430 cap_pcix(d, where);
1431 can_have_ext_caps = 1;
1432 break;
1433 case PCI_CAP_ID_HT:
1434 cap_ht(d, where, cap);
1435 break;
1436 case PCI_CAP_ID_VNDR:
1437 printf("Vendor Specific Information <?>\n");
1438 break;
1439 case PCI_CAP_ID_DBG:
1440 cap_debug_port(cap);
1441 break;
1442 case PCI_CAP_ID_CCRC:
1443 printf("CompactPCI central resource control <?>\n");
1444 break;
1445 case PCI_CAP_ID_HOTPLUG:
1446 printf("Hot-plug capable\n");
1447 break;
1448 case PCI_CAP_ID_SSVID:
1449 cap_ssvid(d, where);
1450 break;
1451 case PCI_CAP_ID_AGP3:
1452 printf("AGP3 <?>\n");
1453 break;
1454 case PCI_CAP_ID_SECURE:
1455 printf("Secure device <?>\n");
1456 break;
1457 case PCI_CAP_ID_EXP:
1458 cap_express(d, where, cap);
1459 can_have_ext_caps = 1;
1460 break;
1461 case PCI_CAP_ID_MSIX:
1462 cap_msix(d, where, cap);
1463 break;
1464 case PCI_CAP_ID_SATA:
1465 printf("SATA HBA <?>\n");
1466 break;
1467 case PCI_CAP_ID_AF:
1468 printf("PCIe advanced features <?>\n");
1469 break;
1470 default:
1471 printf("#%02x [%04x]\n", id, cap);
1472 }
1473 where = next;
1474 }
1475 }
1476 if (can_have_ext_caps)
1477 show_ext_caps(d);
1478 }
1479
1480 /*** Kernel drivers ***/
1481
1482 #ifdef PCI_OS_LINUX
1483
1484 #include <sys/utsname.h>
1485
1486 struct pcimap_entry {
1487 struct pcimap_entry *next;
1488 unsigned int vendor, device;
1489 unsigned int subvendor, subdevice;
1490 unsigned int class, class_mask;
1491 char module[1];
1492 };
1493
1494 static struct pcimap_entry *pcimap_head;
1495
1496 static void
1497 load_pcimap(void)
1498 {
1499 static int tried_pcimap;
1500 struct utsname uts;
1501 char *name, line[1024];
1502 FILE *f;
1503
1504 if (tried_pcimap)
1505 return;
1506 tried_pcimap = 1;
1507
1508 if (name = opt_pcimap)
1509 {
1510 f = fopen(name, "r");
1511 if (!f)
1512 die("Cannot open pcimap file %s: %m", name);
1513 }
1514 else
1515 {
1516 if (uname(&uts) < 0)
1517 die("uname() failed: %m");
1518 name = alloca(64 + strlen(uts.release));
1519 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1520 f = fopen(name, "r");
1521 if (!f)
1522 return;
1523 }
1524
1525 while (fgets(line, sizeof(line), f))
1526 {
1527 char *c = strchr(line, '\n');
1528 struct pcimap_entry *e;
1529
1530 if (!c)
1531 die("Unterminated or too long line in %s", name);
1532 *c = 0;
1533 if (!line[0] || line[0] == '#')
1534 continue;
1535
1536 c = line;
1537 while (*c && *c != ' ' && *c != '\t')
1538 c++;
1539 if (!*c)
1540 continue; /* FIXME: Emit warnings! */
1541 *c++ = 0;
1542
1543 e = xmalloc(sizeof(*e) + strlen(line));
1544 if (sscanf(c, "%i%i%i%i%i%i",
1545 &e->vendor, &e->device,
1546 &e->subvendor, &e->subdevice,
1547 &e->class, &e->class_mask) != 6)
1548 continue;
1549 e->next = pcimap_head;
1550 pcimap_head = e;
1551 strcpy(e->module, line);
1552 }
1553 fclose(f);
1554 }
1555
1556 static int
1557 match_pcimap(struct device *d, struct pcimap_entry *e)
1558 {
1559 struct pci_dev *dev = d->dev;
1560 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1561 word subv, subd;
1562
1563 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1564 get_subid(d, &subv, &subd);
1565 return
1566 MATCH(dev->vendor_id, e->vendor) &&
1567 MATCH(dev->device_id, e->device) &&
1568 MATCH(subv, e->subvendor) &&
1569 MATCH(subd, e->subdevice) &&
1570 (class & e->class_mask) == e->class;
1571 #undef MATCH
1572 }
1573
1574 static void
1575 show_driver(struct device *d)
1576 {
1577 struct pci_dev *dev = d->dev;
1578 char *base = dev->access->method_params[PCI_ACCESS_SYS_BUS_PCI];
1579 char name[1024], driver[1024], *drv;
1580 int n;
1581
1582 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1583 return;
1584
1585 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1586 base, dev->domain, dev->bus, dev->dev, dev->func);
1587 if (n < 0 || n >= 1024)
1588 die("show_driver: sysfs device name too long, why?");
1589
1590 n = readlink(name, driver, sizeof(driver));
1591 if (n < 0)
1592 return;
1593 if (n >= (int)sizeof(driver))
1594 {
1595 printf("\t!!! Driver name too long\n");
1596 return;
1597 }
1598 driver[n] = 0;
1599
1600 if (drv = strrchr(driver, '/'))
1601 drv++;
1602 else
1603 drv = driver;
1604 printf("\tKernel driver in use: %s\n", drv);
1605 }
1606
1607 static void
1608 show_module(struct device *d)
1609 {
1610 struct pcimap_entry *e, *last = NULL;
1611
1612 load_pcimap();
1613 for (e=pcimap_head; e; e=e->next)
1614 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1615 {
1616 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1617 last = e;
1618 }
1619 if (last)
1620 putchar('\n');
1621 }
1622
1623 #else
1624
1625 static void
1626 show_driver(void)
1627 {
1628 }
1629
1630 static void
1631 show_module(void)
1632 {
1633 }
1634
1635 #endif
1636
1637 /*** Verbose output ***/
1638
1639 static void
1640 show_size(pciaddr_t x)
1641 {
1642 if (!x)
1643 return;
1644 printf(" [size=");
1645 if (x < 1024)
1646 printf("%d", (int) x);
1647 else if (x < 1048576)
1648 printf("%dK", (int)(x / 1024));
1649 else if (x < 0x80000000)
1650 printf("%dM", (int)(x / 1048576));
1651 else
1652 printf(PCIADDR_T_FMT, x);
1653 putchar(']');
1654 }
1655
1656 static void
1657 show_bases(struct device *d, int cnt)
1658 {
1659 struct pci_dev *p = d->dev;
1660 word cmd = get_conf_word(d, PCI_COMMAND);
1661 int i;
1662
1663 for(i=0; i<cnt; i++)
1664 {
1665 pciaddr_t pos = p->base_addr[i];
1666 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1667 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1668 if (flg == 0xffffffff)
1669 flg = 0;
1670 if (!pos && !flg && !len)
1671 continue;
1672 if (verbose > 1)
1673 printf("\tRegion %d: ", i);
1674 else
1675 putchar('\t');
1676 if (pos && !flg) /* Reported by the OS, but not by the device */
1677 {
1678 printf("[virtual] ");
1679 flg = pos;
1680 }
1681 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1682 {
1683 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1684 printf("I/O ports at ");
1685 if (a)
1686 printf(PCIADDR_PORT_FMT, a);
1687 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1688 printf("<ignored>");
1689 else
1690 printf("<unassigned>");
1691 if (!(cmd & PCI_COMMAND_IO))
1692 printf(" [disabled]");
1693 }
1694 else
1695 {
1696 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1697 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1698 int done = 0;
1699 u32 z = 0;
1700
1701 printf("Memory at ");
1702 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
1703 {
1704 if (i >= cnt - 1)
1705 {
1706 printf("<invalid-64bit-slot>");
1707 done = 1;
1708 }
1709 else
1710 {
1711 i++;
1712 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1713 if (opt_buscentric)
1714 {
1715 u32 y = a & 0xffffffff;
1716 if (a || z)
1717 printf("%08x%08x", z, y);
1718 else
1719 printf("<unassigned>");
1720 done = 1;
1721 }
1722 }
1723 }
1724 if (!done)
1725 {
1726 if (a)
1727 printf(PCIADDR_T_FMT, a);
1728 else
1729 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
1730 }
1731 printf(" (%s, %sprefetchable)",
1732 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
1733 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
1734 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
1735 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
1736 if (!(cmd & PCI_COMMAND_MEMORY))
1737 printf(" [disabled]");
1738 }
1739 show_size(len);
1740 putchar('\n');
1741 }
1742 }
1743
1744 static void
1745 show_rom(struct device *d, int reg)
1746 {
1747 struct pci_dev *p = d->dev;
1748 pciaddr_t rom = p->rom_base_addr;
1749 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
1750 u32 flg = get_conf_long(d, reg);
1751 word cmd = get_conf_word(d, PCI_COMMAND);
1752
1753 if (!rom && !flg && !len)
1754 return;
1755 putchar('\t');
1756 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
1757 {
1758 printf("[virtual] ");
1759 flg = rom;
1760 }
1761 printf("Expansion ROM at ");
1762 if (rom & PCI_ROM_ADDRESS_MASK)
1763 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
1764 else if (flg & PCI_ROM_ADDRESS_MASK)
1765 printf("<ignored>");
1766 else
1767 printf("<unassigned>");
1768 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
1769 printf(" [disabled]");
1770 else if (!(cmd & PCI_COMMAND_MEMORY))
1771 printf(" [disabled by cmd]");
1772 show_size(len);
1773 putchar('\n');
1774 }
1775
1776 static void
1777 show_htype0(struct device *d)
1778 {
1779 show_bases(d, 6);
1780 show_rom(d, PCI_ROM_ADDRESS);
1781 show_caps(d);
1782 }
1783
1784 static void
1785 show_htype1(struct device *d)
1786 {
1787 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1788 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1789 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1790 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1791 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1792 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1793 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1794 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1795 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1796 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1797 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1798 int verb = verbose > 2;
1799
1800 show_bases(d, 2);
1801 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1802 get_conf_byte(d, PCI_PRIMARY_BUS),
1803 get_conf_byte(d, PCI_SECONDARY_BUS),
1804 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1805 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1806
1807 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1808 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1809 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1810 else
1811 {
1812 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1813 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1814 if (io_type == PCI_IO_RANGE_TYPE_32)
1815 {
1816 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1817 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1818 }
1819 if (io_base <= io_limit || verb)
1820 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1821 }
1822
1823 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1824 mem_type)
1825 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1826 else
1827 {
1828 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1829 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1830 if (mem_base <= mem_limit || verb)
1831 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1832 }
1833
1834 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1835 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1836 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1837 else
1838 {
1839 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1840 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1841 if (pref_base <= pref_limit || verb)
1842 {
1843 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1844 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1845 else
1846 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1847 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1848 pref_base,
1849 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1850 pref_limit + 0xfffff);
1851 }
1852 }
1853
1854 if (verbose > 1)
1855 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1856 FLAG(sec_stat, PCI_STATUS_66MHZ),
1857 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1858 FLAG(sec_stat, PCI_STATUS_PARITY),
1859 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1860 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1861 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1862 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1863 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1864 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1865 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1866 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1867
1868 show_rom(d, PCI_ROM_ADDRESS1);
1869
1870 if (verbose > 1)
1871 {
1872 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1873 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1874 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1875 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1876 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1877 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1878 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1879 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1880 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
1881 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
1882 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
1883 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
1884 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
1885 }
1886
1887 show_caps(d);
1888 }
1889
1890 static void
1891 show_htype2(struct device *d)
1892 {
1893 int i;
1894 word cmd = get_conf_word(d, PCI_COMMAND);
1895 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1896 word exca;
1897 int verb = verbose > 2;
1898
1899 show_bases(d, 1);
1900 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1901 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1902 get_conf_byte(d, PCI_CB_CARD_BUS),
1903 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1904 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1905 for(i=0; i<2; i++)
1906 {
1907 int p = 8*i;
1908 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1909 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1910 if (limit > base || verb)
1911 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1912 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1913 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1914 }
1915 for(i=0; i<2; i++)
1916 {
1917 int p = 8*i;
1918 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1919 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1920 if (!(base & PCI_IO_RANGE_TYPE_32))
1921 {
1922 base &= 0xffff;
1923 limit &= 0xffff;
1924 }
1925 base &= PCI_CB_IO_RANGE_MASK;
1926 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1927 if (base <= limit || verb)
1928 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1929 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1930 }
1931
1932 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1933 printf("\tSecondary status: SERR\n");
1934 if (verbose > 1)
1935 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1936 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1937 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1938 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1939 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1940 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1941 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1942 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1943 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1944
1945 if (d->config_cached < 128)
1946 {
1947 printf("\t<access denied to the rest>\n");
1948 return;
1949 }
1950
1951 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1952 if (exca)
1953 printf("\t16-bit legacy interface ports at %04x\n", exca);
1954 }
1955
1956 static void
1957 show_verbose(struct device *d)
1958 {
1959 struct pci_dev *p = d->dev;
1960 word status = get_conf_word(d, PCI_STATUS);
1961 word cmd = get_conf_word(d, PCI_COMMAND);
1962 word class = p->device_class;
1963 byte bist = get_conf_byte(d, PCI_BIST);
1964 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1965 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1966 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1967 byte max_lat, min_gnt;
1968 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1969 unsigned int irq = p->irq;
1970 word subsys_v, subsys_d;
1971 char ssnamebuf[256];
1972
1973 show_terse(d);
1974
1975 switch (htype)
1976 {
1977 case PCI_HEADER_TYPE_NORMAL:
1978 if (class == PCI_CLASS_BRIDGE_PCI)
1979 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1980 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1981 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1982 break;
1983 case PCI_HEADER_TYPE_BRIDGE:
1984 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1985 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1986 irq = int_pin = min_gnt = max_lat = 0;
1987 break;
1988 case PCI_HEADER_TYPE_CARDBUS:
1989 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1990 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1991 min_gnt = max_lat = 0;
1992 break;
1993 default:
1994 printf("\t!!! Unknown header type %02x\n", htype);
1995 return;
1996 }
1997
1998 get_subid(d, &subsys_v, &subsys_d);
1999 if (subsys_v && subsys_v != 0xffff)
2000 printf("\tSubsystem: %s\n",
2001 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
2002 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2003 p->vendor_id, p->device_id, subsys_v, subsys_d));
2004
2005 if (verbose > 1)
2006 {
2007 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2008 FLAG(cmd, PCI_COMMAND_IO),
2009 FLAG(cmd, PCI_COMMAND_MEMORY),
2010 FLAG(cmd, PCI_COMMAND_MASTER),
2011 FLAG(cmd, PCI_COMMAND_SPECIAL),
2012 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2013 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2014 FLAG(cmd, PCI_COMMAND_PARITY),
2015 FLAG(cmd, PCI_COMMAND_WAIT),
2016 FLAG(cmd, PCI_COMMAND_SERR),
2017 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2018 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2019 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2020 FLAG(status, PCI_STATUS_CAP_LIST),
2021 FLAG(status, PCI_STATUS_66MHZ),
2022 FLAG(status, PCI_STATUS_UDF),
2023 FLAG(status, PCI_STATUS_FAST_BACK),
2024 FLAG(status, PCI_STATUS_PARITY),
2025 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2026 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2027 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2028 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2029 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2030 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2031 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2032 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2033 FLAG(status, PCI_STATUS_INTx));
2034 if (cmd & PCI_COMMAND_MASTER)
2035 {
2036 printf("\tLatency: %d", latency);
2037 if (min_gnt || max_lat)
2038 {
2039 printf(" (");
2040 if (min_gnt)
2041 printf("%dns min", min_gnt*250);
2042 if (min_gnt && max_lat)
2043 printf(", ");
2044 if (max_lat)
2045 printf("%dns max", max_lat*250);
2046 putchar(')');
2047 }
2048 if (cache_line)
2049 printf(", Cache Line Size: %d bytes", cache_line * 4);
2050 putchar('\n');
2051 }
2052 if (int_pin || irq)
2053 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2054 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2055 }
2056 else
2057 {
2058 printf("\tFlags: ");
2059 if (cmd & PCI_COMMAND_MASTER)
2060 printf("bus master, ");
2061 if (cmd & PCI_COMMAND_VGA_PALETTE)
2062 printf("VGA palette snoop, ");
2063 if (cmd & PCI_COMMAND_WAIT)
2064 printf("stepping, ");
2065 if (cmd & PCI_COMMAND_FAST_BACK)
2066 printf("fast Back2Back, ");
2067 if (status & PCI_STATUS_66MHZ)
2068 printf("66MHz, ");
2069 if (status & PCI_STATUS_UDF)
2070 printf("user-definable features, ");
2071 printf("%s devsel",
2072 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2073 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2074 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2075 if (cmd & PCI_COMMAND_MASTER)
2076 printf(", latency %d", latency);
2077 if (irq)
2078 printf(", IRQ " PCIIRQ_FMT, irq);
2079 putchar('\n');
2080 }
2081
2082 if (bist & PCI_BIST_CAPABLE)
2083 {
2084 if (bist & PCI_BIST_START)
2085 printf("\tBIST is running\n");
2086 else
2087 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2088 }
2089
2090 switch (htype)
2091 {
2092 case PCI_HEADER_TYPE_NORMAL:
2093 show_htype0(d);
2094 break;
2095 case PCI_HEADER_TYPE_BRIDGE:
2096 show_htype1(d);
2097 break;
2098 case PCI_HEADER_TYPE_CARDBUS:
2099 show_htype2(d);
2100 break;
2101 }
2102
2103 show_driver(d);
2104 show_module(d);
2105 }
2106
2107 /*** Machine-readable dumps ***/
2108
2109 static void
2110 show_hex_dump(struct device *d)
2111 {
2112 unsigned int i, cnt;
2113
2114 cnt = d->config_cached;
2115 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2116 {
2117 cnt = 256;
2118 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2119 cnt = 4096;
2120 }
2121
2122 for(i=0; i<cnt; i++)
2123 {
2124 if (! (i & 15))
2125 printf("%02x:", i);
2126 printf(" %02x", get_conf_byte(d, i));
2127 if ((i & 15) == 15)
2128 putchar('\n');
2129 }
2130 }
2131
2132 static void
2133 print_shell_escaped(char *c)
2134 {
2135 printf(" \"");
2136 while (*c)
2137 {
2138 if (*c == '"' || *c == '\\')
2139 putchar('\\');
2140 putchar(*c++);
2141 }
2142 putchar('"');
2143 }
2144
2145 static void
2146 show_machine(struct device *d)
2147 {
2148 struct pci_dev *p = d->dev;
2149 int c;
2150 word sv_id, sd_id;
2151 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2152
2153 get_subid(d, &sv_id, &sd_id);
2154
2155 if (verbose)
2156 {
2157 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2158 show_slot_name(d);
2159 putchar('\n');
2160 printf("Class:\t%s\n",
2161 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2162 printf("Vendor:\t%s\n",
2163 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2164 printf("Device:\t%s\n",
2165 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2166 if (sv_id && sv_id != 0xffff)
2167 {
2168 printf("SVendor:\t%s\n",
2169 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2170 printf("SDevice:\t%s\n",
2171 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2172 }
2173 if (c = get_conf_byte(d, PCI_REVISION_ID))
2174 printf("Rev:\t%02x\n", c);
2175 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2176 printf("ProgIf:\t%02x\n", c);
2177 }
2178 else
2179 {
2180 show_slot_name(d);
2181 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2182 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2183 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2184 if (c = get_conf_byte(d, PCI_REVISION_ID))
2185 printf(" -r%02x", c);
2186 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2187 printf(" -p%02x", c);
2188 if (sv_id && sv_id != 0xffff)
2189 {
2190 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2191 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2192 }
2193 else
2194 printf(" \"\" \"\"");
2195 putchar('\n');
2196 }
2197 }
2198
2199 /*** Main show function ***/
2200
2201 static void
2202 show_device(struct device *d)
2203 {
2204 if (opt_machine)
2205 show_machine(d);
2206 else if (verbose)
2207 show_verbose(d);
2208 else
2209 show_terse(d);
2210 if (opt_hex)
2211 show_hex_dump(d);
2212 if (verbose || opt_hex)
2213 putchar('\n');
2214 }
2215
2216 static void
2217 show(void)
2218 {
2219 struct device *d;
2220
2221 for(d=first_dev; d; d=d->next)
2222 show_device(d);
2223 }
2224
2225 /*** Tree output ***/
2226
2227 struct bridge {
2228 struct bridge *chain; /* Single-linked list of bridges */
2229 struct bridge *next, *child; /* Tree of bridges */
2230 struct bus *first_bus; /* List of buses connected to this bridge */
2231 unsigned int domain;
2232 unsigned int primary, secondary, subordinate; /* Bus numbers */
2233 struct device *br_dev;
2234 };
2235
2236 struct bus {
2237 unsigned int domain;
2238 unsigned int number;
2239 struct bus *sibling;
2240 struct device *first_dev, **last_dev;
2241 };
2242
2243 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2244
2245 static struct bus *
2246 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2247 {
2248 struct bus *bus;
2249
2250 for(bus=b->first_bus; bus; bus=bus->sibling)
2251 if (bus->domain == domain && bus->number == n)
2252 break;
2253 return bus;
2254 }
2255
2256 static struct bus *
2257 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2258 {
2259 struct bus *bus = xmalloc(sizeof(struct bus));
2260 bus->domain = domain;
2261 bus->number = n;
2262 bus->sibling = b->first_bus;
2263 bus->first_dev = NULL;
2264 bus->last_dev = &bus->first_dev;
2265 b->first_bus = bus;
2266 return bus;
2267 }
2268
2269 static void
2270 insert_dev(struct device *d, struct bridge *b)
2271 {
2272 struct pci_dev *p = d->dev;
2273 struct bus *bus;
2274
2275 if (! (bus = find_bus(b, p->domain, p->bus)))
2276 {
2277 struct bridge *c;
2278 for(c=b->child; c; c=c->next)
2279 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2280 {
2281 insert_dev(d, c);
2282 return;
2283 }
2284 bus = new_bus(b, p->domain, p->bus);
2285 }
2286 /* Simple insertion at the end _does_ guarantee the correct order as the
2287 * original device list was sorted by (domain, bus, devfn) lexicographically
2288 * and all devices on the new list have the same bus number.
2289 */
2290 *bus->last_dev = d;
2291 bus->last_dev = &d->next;
2292 d->next = NULL;
2293 }
2294
2295 static void
2296 grow_tree(void)
2297 {
2298 struct device *d, *d2;
2299 struct bridge **last_br, *b;
2300
2301 /* Build list of bridges */
2302
2303 last_br = &host_bridge.chain;
2304 for(d=first_dev; d; d=d->next)
2305 {
2306 word class = d->dev->device_class;
2307 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2308 if (class == PCI_CLASS_BRIDGE_PCI &&
2309 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2310 {
2311 b = xmalloc(sizeof(struct bridge));
2312 b->domain = d->dev->domain;
2313 if (ht == PCI_HEADER_TYPE_BRIDGE)
2314 {
2315 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2316 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2317 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2318 }
2319 else
2320 {
2321 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2322 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2323 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2324 }
2325 *last_br = b;
2326 last_br = &b->chain;
2327 b->next = b->child = NULL;
2328 b->first_bus = NULL;
2329 b->br_dev = d;
2330 }
2331 }
2332 *last_br = NULL;
2333
2334 /* Create a bridge tree */
2335
2336 for(b=&host_bridge; b; b=b->chain)
2337 {
2338 struct bridge *c, *best;
2339 best = NULL;
2340 for(c=&host_bridge; c; c=c->chain)
2341 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2342 b->primary >= c->secondary && b->primary <= c->subordinate &&
2343 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2344 best = c;
2345 if (best)
2346 {
2347 b->next = best->child;
2348 best->child = b;
2349 }
2350 }
2351
2352 /* Insert secondary bus for each bridge */
2353
2354 for(b=&host_bridge; b; b=b->chain)
2355 if (!find_bus(b, b->domain, b->secondary))
2356 new_bus(b, b->domain, b->secondary);
2357
2358 /* Create bus structs and link devices */
2359
2360 for(d=first_dev; d;)
2361 {
2362 d2 = d->next;
2363 insert_dev(d, &host_bridge);
2364 d = d2;
2365 }
2366 }
2367
2368 static void
2369 print_it(char *line, char *p)
2370 {
2371 *p++ = '\n';
2372 *p = 0;
2373 fputs(line, stdout);
2374 for(p=line; *p; p++)
2375 if (*p == '+' || *p == '|')
2376 *p = '|';
2377 else
2378 *p = ' ';
2379 }
2380
2381 static void show_tree_bridge(struct bridge *, char *, char *);
2382
2383 static void
2384 show_tree_dev(struct device *d, char *line, char *p)
2385 {
2386 struct pci_dev *q = d->dev;
2387 struct bridge *b;
2388 char namebuf[256];
2389
2390 p += sprintf(p, "%02x.%x", q->dev, q->func);
2391 for(b=&host_bridge; b; b=b->chain)
2392 if (b->br_dev == d)
2393 {
2394 if (b->secondary == b->subordinate)
2395 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2396 else
2397 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2398 show_tree_bridge(b, line, p);
2399 return;
2400 }
2401 if (verbose)
2402 p += sprintf(p, " %s",
2403 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2404 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2405 q->vendor_id, q->device_id));
2406 print_it(line, p);
2407 }
2408
2409 static void
2410 show_tree_bus(struct bus *b, char *line, char *p)
2411 {
2412 if (!b->first_dev)
2413 print_it(line, p);
2414 else if (!b->first_dev->next)
2415 {
2416 *p++ = '-';
2417 *p++ = '-';
2418 show_tree_dev(b->first_dev, line, p);
2419 }
2420 else
2421 {
2422 struct device *d = b->first_dev;
2423 while (d->next)
2424 {
2425 p[0] = '+';
2426 p[1] = '-';
2427 show_tree_dev(d, line, p+2);
2428 d = d->next;
2429 }
2430 p[0] = '\\';
2431 p[1] = '-';
2432 show_tree_dev(d, line, p+2);
2433 }
2434 }
2435
2436 static void
2437 show_tree_bridge(struct bridge *b, char *line, char *p)
2438 {
2439 *p++ = '-';
2440 if (!b->first_bus->sibling)
2441 {
2442 if (b == &host_bridge)
2443 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2444 show_tree_bus(b->first_bus, line, p);
2445 }
2446 else
2447 {
2448 struct bus *u = b->first_bus;
2449 char *k;
2450
2451 while (u->sibling)
2452 {
2453 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2454 show_tree_bus(u, line, k);
2455 u = u->sibling;
2456 }
2457 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2458 show_tree_bus(u, line, k);
2459 }
2460 }
2461
2462 static void
2463 show_forest(void)
2464 {
2465 char line[256];
2466
2467 grow_tree();
2468 show_tree_bridge(&host_bridge, line, line);
2469 }
2470
2471 /*** Bus mapping mode ***/
2472
2473 struct bus_bridge {
2474 struct bus_bridge *next;
2475 byte this, dev, func, first, last, bug;
2476 };
2477
2478 struct bus_info {
2479 byte exists;
2480 byte guestbook;
2481 struct bus_bridge *bridges, *via;
2482 };
2483
2484 static struct bus_info *bus_info;
2485
2486 static void
2487 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2488 {
2489 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2490 struct pci_dev *p = d->dev;
2491
2492 b->next = bi->bridges;
2493 bi->bridges = b;
2494 b->this = get_conf_byte(d, np);
2495 b->dev = p->dev;
2496 b->func = p->func;
2497 b->first = get_conf_byte(d, ns);
2498 b->last = get_conf_byte(d, nl);
2499 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2500 p->bus, p->dev, p->func, b->this, b->first, b->last);
2501 if (b->this != p->bus)
2502 printf("!!! Bridge points to invalid primary bus.\n");
2503 if (b->first > b->last)
2504 {
2505 printf("!!! Bridge points to invalid bus range.\n");
2506 b->last = b->first;
2507 }
2508 }
2509
2510 static void
2511 do_map_bus(int bus)
2512 {
2513 int dev, func;
2514 int verbose = pacc->debugging;
2515 struct bus_info *bi = bus_info + bus;
2516 struct device *d;
2517
2518 if (verbose)
2519 printf("Mapping bus %02x\n", bus);
2520 for(dev = 0; dev < 32; dev++)
2521 if (filter.slot < 0 || filter.slot == dev)
2522 {
2523 int func_limit = 1;
2524 for(func = 0; func < func_limit; func++)
2525 if (filter.func < 0 || filter.func == func)
2526 {
2527 /* XXX: Bus mapping supports only domain 0 */
2528 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2529 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2530 if (vendor && vendor != 0xffff)
2531 {
2532 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2533 func_limit = 8;
2534 if (verbose)
2535 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2536 bi->exists = 1;
2537 if (d = scan_device(p))
2538 {
2539 show_device(d);
2540 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2541 {
2542 case PCI_HEADER_TYPE_BRIDGE:
2543 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2544 break;
2545 case PCI_HEADER_TYPE_CARDBUS:
2546 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2547 break;
2548 }
2549 free(d);
2550 }
2551 else if (verbose)
2552 printf("But it was filtered out.\n");
2553 }
2554 pci_free_dev(p);
2555 }
2556 }
2557 }
2558
2559 static void
2560 do_map_bridges(int bus, int min, int max)
2561 {
2562 struct bus_info *bi = bus_info + bus;
2563 struct bus_bridge *b;
2564
2565 bi->guestbook = 1;
2566 for(b=bi->bridges; b; b=b->next)
2567 {
2568 if (bus_info[b->first].guestbook)
2569 b->bug = 1;
2570 else if (b->first < min || b->last > max)
2571 b->bug = 2;
2572 else
2573 {
2574 bus_info[b->first].via = b;
2575 do_map_bridges(b->first, b->first, b->last);
2576 }
2577 }
2578 }
2579
2580 static void
2581 map_bridges(void)
2582 {
2583 int i;
2584
2585 printf("\nSummary of buses:\n\n");
2586 for(i=0; i<256; i++)
2587 if (bus_info[i].exists && !bus_info[i].guestbook)
2588 do_map_bridges(i, 0, 255);
2589 for(i=0; i<256; i++)
2590 {
2591 struct bus_info *bi = bus_info + i;
2592 struct bus_bridge *b = bi->via;
2593
2594 if (bi->exists)
2595 {
2596 printf("%02x: ", i);
2597 if (b)
2598 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2599 else if (!i)
2600 printf("Primary host bus\n");
2601 else
2602 printf("Secondary host bus (?)\n");
2603 }
2604 for(b=bi->bridges; b; b=b->next)
2605 {
2606 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2607 switch (b->bug)
2608 {
2609 case 1:
2610 printf(" <overlap bug>");
2611 break;
2612 case 2:
2613 printf(" <crossing bug>");
2614 break;
2615 }
2616 putchar('\n');
2617 }
2618 }
2619 }
2620
2621 static void
2622 map_the_bus(void)
2623 {
2624 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2625 pacc->method == PCI_ACCESS_DUMP)
2626 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2627 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2628 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2629 if (filter.bus >= 0)
2630 do_map_bus(filter.bus);
2631 else
2632 {
2633 int bus;
2634 for(bus=0; bus<256; bus++)
2635 do_map_bus(bus);
2636 }
2637 map_bridges();
2638 }
2639
2640 /* Main */
2641
2642 int
2643 main(int argc, char **argv)
2644 {
2645 int i;
2646 char *msg;
2647
2648 if (argc == 2 && !strcmp(argv[1], "--version"))
2649 {
2650 puts("lspci version " PCIUTILS_VERSION);
2651 return 0;
2652 }
2653
2654 pacc = pci_alloc();
2655 pacc->error = die;
2656 pci_filter_init(pacc, &filter);
2657
2658 while ((i = getopt(argc, argv, options)) != -1)
2659 switch (i)
2660 {
2661 case 'n':
2662 pacc->numeric_ids++;
2663 break;
2664 case 'v':
2665 verbose++;
2666 break;
2667 case 'b':
2668 pacc->buscentric = 1;
2669 opt_buscentric = 1;
2670 break;
2671 case 's':
2672 if (msg = pci_filter_parse_slot(&filter, optarg))
2673 die("-s: %s", msg);
2674 break;
2675 case 'd':
2676 if (msg = pci_filter_parse_id(&filter, optarg))
2677 die("-d: %s", msg);
2678 break;
2679 case 'x':
2680 opt_hex++;
2681 break;
2682 case 't':
2683 opt_tree++;
2684 break;
2685 case 'i':
2686 pci_set_name_list_path(pacc, optarg, 0);
2687 break;
2688 case 'm':
2689 opt_machine++;
2690 break;
2691 case 'p':
2692 opt_pcimap = optarg;
2693 break;
2694 case 'M':
2695 opt_map_mode++;
2696 break;
2697 case 'D':
2698 opt_domains = 2;
2699 break;
2700 default:
2701 if (parse_generic_option(i, pacc, optarg))
2702 break;
2703 bad:
2704 fprintf(stderr, help_msg, pacc->id_file_name);
2705 return 1;
2706 }
2707 if (optind < argc)
2708 goto bad;
2709
2710 pci_init(pacc);
2711 if (opt_map_mode)
2712 map_the_bus();
2713 else
2714 {
2715 scan_devices();
2716 sort_them();
2717 if (opt_tree)
2718 show_forest();
2719 else
2720 show();
2721 }
2722 pci_cleanup(pacc);
2723
2724 return (seen_errors ? 2 : 0);
2725 }
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