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Fixed bug in printing of 64-bit prefetchable memory windows.
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26 static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27
28 const char program_name[] = "lspci";
29
30 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
31
32 static char help_msg[] = "\
33 Usage: lspci [<switches>]\n\
34 \n\
35 -v\t\tBe verbose\n\
36 -n\t\tShow numeric ID's\n\
37 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
38 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
39 -x\t\tShow hex-dump of the standard portion of config space\n\
40 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
41 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
42 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
43 -d [<vendor>]:[<device>]\tShow only selected devices\n\
44 -t\t\tShow bus tree\n\
45 -m\t\tProduce machine-readable output\n\
46 -i <file>\tUse specified ID database instead of %s\n\
47 -D\t\tAlways show domain numbers\n\
48 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
49 GENERIC_HELP
50 ;
51
52 /* Communication with libpci */
53
54 static struct pci_access *pacc;
55
56 /*
57 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
58 * This increases our memory footprint, but only slightly since we don't
59 * use alloca() much.
60 */
61
62 #ifndef __GNUC__
63 #undef alloca
64 #define alloca xmalloc
65 #endif
66
67 /* Our view of the PCI bus */
68
69 struct device {
70 struct device *next;
71 struct pci_dev *dev;
72 unsigned int config_cached, config_bufsize;
73 byte *config; /* Cached configuration space data */
74 byte *present; /* Maps which configuration bytes are present */
75 };
76
77 static struct device *first_dev;
78
79 static int
80 config_fetch(struct device *d, unsigned int pos, unsigned int len)
81 {
82 unsigned int end = pos+len;
83 int result;
84
85 while (pos < d->config_bufsize && len && d->present[pos])
86 pos++, len--;
87 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
88 len--;
89 if (!len)
90 return 1;
91
92 if (end > d->config_bufsize)
93 {
94 int orig_size = d->config_bufsize;
95 while (end > d->config_bufsize)
96 d->config_bufsize *= 2;
97 d->config = xrealloc(d->config, d->config_bufsize);
98 d->present = xrealloc(d->present, d->config_bufsize);
99 bzero(d->present + orig_size, d->config_bufsize - orig_size);
100 }
101 result = pci_read_block(d->dev, pos, d->config + pos, len);
102 if (result)
103 memset(d->present + pos, 1, len);
104 return result;
105 }
106
107 static struct device *
108 scan_device(struct pci_dev *p)
109 {
110 struct device *d;
111
112 if (p->domain && !show_domains)
113 show_domains = 1;
114 if (!pci_filter_match(&filter, p))
115 return NULL;
116 d = xmalloc(sizeof(struct device));
117 bzero(d, sizeof(*d));
118 d->dev = p;
119 d->config_cached = d->config_bufsize = 64;
120 d->config = xmalloc(64);
121 d->present = xmalloc(64);
122 memset(d->present, 1, 64);
123 if (!pci_read_block(p, 0, d->config, 64))
124 die("Unable to read the standard configuration space header");
125 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
126 {
127 /* For cardbus bridges, we need to fetch 64 bytes more to get the
128 * full standard header... */
129 if (config_fetch(d, 64, 64))
130 d->config_cached += 64;
131 }
132 pci_setup_cache(p, d->config, d->config_cached);
133 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
134 return d;
135 }
136
137 static void
138 scan_devices(void)
139 {
140 struct device *d;
141 struct pci_dev *p;
142
143 pci_scan_bus(pacc);
144 for(p=pacc->devices; p; p=p->next)
145 if (d = scan_device(p))
146 {
147 d->next = first_dev;
148 first_dev = d;
149 }
150 }
151
152 /* Config space accesses */
153
154 static void
155 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
156 {
157 while (len)
158 if (!d->present[pos])
159 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
160 else
161 pos++, len--;
162 }
163
164 static inline byte
165 get_conf_byte(struct device *d, unsigned int pos)
166 {
167 check_conf_range(d, pos, 1);
168 return d->config[pos];
169 }
170
171 static word
172 get_conf_word(struct device *d, unsigned int pos)
173 {
174 check_conf_range(d, pos, 2);
175 return d->config[pos] | (d->config[pos+1] << 8);
176 }
177
178 static u32
179 get_conf_long(struct device *d, unsigned int pos)
180 {
181 check_conf_range(d, pos, 4);
182 return d->config[pos] |
183 (d->config[pos+1] << 8) |
184 (d->config[pos+2] << 16) |
185 (d->config[pos+3] << 24);
186 }
187
188 /* Sorting */
189
190 static int
191 compare_them(const void *A, const void *B)
192 {
193 const struct pci_dev *a = (*(const struct device **)A)->dev;
194 const struct pci_dev *b = (*(const struct device **)B)->dev;
195
196 if (a->domain < b->domain)
197 return -1;
198 if (a->domain > b->domain)
199 return 1;
200 if (a->bus < b->bus)
201 return -1;
202 if (a->bus > b->bus)
203 return 1;
204 if (a->dev < b->dev)
205 return -1;
206 if (a->dev > b->dev)
207 return 1;
208 if (a->func < b->func)
209 return -1;
210 if (a->func > b->func)
211 return 1;
212 return 0;
213 }
214
215 static void
216 sort_them(void)
217 {
218 struct device **index, **h, **last_dev;
219 int cnt;
220 struct device *d;
221
222 cnt = 0;
223 for(d=first_dev; d; d=d->next)
224 cnt++;
225 h = index = alloca(sizeof(struct device *) * cnt);
226 for(d=first_dev; d; d=d->next)
227 *h++ = d;
228 qsort(index, cnt, sizeof(struct device *), compare_them);
229 last_dev = &first_dev;
230 h = index;
231 while (cnt--)
232 {
233 *last_dev = *h;
234 last_dev = &(*h)->next;
235 h++;
236 }
237 *last_dev = NULL;
238 }
239
240 /* Normal output */
241
242 #define FLAG(x,y) ((x & y) ? '+' : '-')
243
244 static void
245 show_slot_name(struct device *d)
246 {
247 struct pci_dev *p = d->dev;
248
249 if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
250 printf("%04x:", p->domain);
251 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
252 }
253
254 static void
255 show_terse(struct device *d)
256 {
257 int c;
258 struct pci_dev *p = d->dev;
259 byte classbuf[128], devbuf[128];
260
261 show_slot_name(d);
262 printf(" %s: %s",
263 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
264 PCI_LOOKUP_CLASS,
265 p->device_class),
266 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
267 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
268 p->vendor_id, p->device_id));
269 if (c = get_conf_byte(d, PCI_REVISION_ID))
270 printf(" (rev %02x)", c);
271 if (verbose)
272 {
273 char *x;
274 c = get_conf_byte(d, PCI_CLASS_PROG);
275 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
276 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
277 p->device_class, c);
278 if (c || x)
279 {
280 printf(" (prog-if %02x", c);
281 if (x)
282 printf(" [%s]", x);
283 putchar(')');
284 }
285 }
286 putchar('\n');
287 }
288
289 static void
290 show_size(pciaddr_t x)
291 {
292 if (!x)
293 return;
294 printf(" [size=");
295 if (x < 1024)
296 printf("%d", (int) x);
297 else if (x < 1048576)
298 printf("%dK", (int)(x / 1024));
299 else if (x < 0x80000000)
300 printf("%dM", (int)(x / 1048576));
301 else
302 printf(PCIADDR_T_FMT, x);
303 putchar(']');
304 }
305
306 static void
307 show_bases(struct device *d, int cnt)
308 {
309 struct pci_dev *p = d->dev;
310 word cmd = get_conf_word(d, PCI_COMMAND);
311 int i;
312
313 for(i=0; i<cnt; i++)
314 {
315 pciaddr_t pos = p->base_addr[i];
316 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
317 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
318 if (flg == 0xffffffff)
319 flg = 0;
320 if (!pos && !flg && !len)
321 continue;
322 if (verbose > 1)
323 printf("\tRegion %d: ", i);
324 else
325 putchar('\t');
326 if (pos && !flg) /* Reported by the OS, but not by the device */
327 {
328 printf("[virtual] ");
329 flg = pos;
330 }
331 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
332 {
333 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
334 printf("I/O ports at ");
335 if (a)
336 printf(PCIADDR_PORT_FMT, a);
337 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
338 printf("<ignored>");
339 else
340 printf("<unassigned>");
341 if (!(cmd & PCI_COMMAND_IO))
342 printf(" [disabled]");
343 }
344 else
345 {
346 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
347 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
348 int done = 0;
349 u32 z = 0;
350
351 printf("Memory at ");
352 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
353 {
354 if (i >= cnt - 1)
355 {
356 printf("<invalid-64bit-slot>");
357 done = 1;
358 }
359 else
360 {
361 i++;
362 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
363 if (buscentric_view)
364 {
365 u32 y = a & 0xffffffff;
366 if (a || z)
367 printf("%08x%08x", z, y);
368 else
369 printf("<unassigned>");
370 done = 1;
371 }
372 }
373 }
374 if (!done)
375 {
376 if (a)
377 printf(PCIADDR_T_FMT, a);
378 else
379 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
380 }
381 printf(" (%s, %sprefetchable)",
382 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
383 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
384 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
385 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
386 if (!(cmd & PCI_COMMAND_MEMORY))
387 printf(" [disabled]");
388 }
389 show_size(len);
390 putchar('\n');
391 }
392 }
393
394 static void
395 show_pm(struct device *d, int where, int cap)
396 {
397 int t, b;
398 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
399
400 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
401 if (verbose < 2)
402 return;
403 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
404 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
405 FLAG(cap, PCI_PM_CAP_DSI),
406 FLAG(cap, PCI_PM_CAP_D1),
407 FLAG(cap, PCI_PM_CAP_D2),
408 pm_aux_current[(cap >> 6) & 7],
409 FLAG(cap, PCI_PM_CAP_PME_D0),
410 FLAG(cap, PCI_PM_CAP_PME_D1),
411 FLAG(cap, PCI_PM_CAP_PME_D2),
412 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
413 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
414 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
415 return;
416 t = get_conf_word(d, where + PCI_PM_CTRL);
417 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
418 t & PCI_PM_CTRL_STATE_MASK,
419 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
420 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
421 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
422 FLAG(t, PCI_PM_CTRL_PME_STATUS));
423 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
424 if (b)
425 printf("\t\tBridge: PM%c B3%c\n",
426 FLAG(t, PCI_PM_BPCC_ENABLE),
427 FLAG(~t, PCI_PM_PPB_B2_B3));
428 }
429
430 static void
431 format_agp_rate(int rate, char *buf, int agp3)
432 {
433 char *c = buf;
434 int i;
435
436 for(i=0; i<=2; i++)
437 if (rate & (1 << i))
438 {
439 if (c != buf)
440 *c++ = ',';
441 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
442 }
443 if (c != buf)
444 *c = 0;
445 else
446 strcpy(buf, "<none>");
447 }
448
449 static void
450 show_agp(struct device *d, int where, int cap)
451 {
452 u32 t;
453 char rate[16];
454 int ver, rev;
455 int agp3 = 0;
456
457 ver = (cap >> 4) & 0x0f;
458 rev = cap & 0x0f;
459 printf("AGP version %x.%x\n", ver, rev);
460 if (verbose < 2)
461 return;
462 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
463 return;
464 t = get_conf_long(d, where + PCI_AGP_STATUS);
465 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
466 agp3 = 1;
467 format_agp_rate(t & 7, rate, agp3);
468 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
469 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
470 FLAG(t, PCI_AGP_STATUS_ISOCH),
471 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
472 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
473 FLAG(t, PCI_AGP_STATUS_SBA),
474 FLAG(t, PCI_AGP_STATUS_ITA_COH),
475 FLAG(t, PCI_AGP_STATUS_GART64),
476 FLAG(t, PCI_AGP_STATUS_HTRANS),
477 FLAG(t, PCI_AGP_STATUS_64BIT),
478 FLAG(t, PCI_AGP_STATUS_FW),
479 FLAG(t, PCI_AGP_STATUS_AGP3),
480 rate);
481 t = get_conf_long(d, where + PCI_AGP_COMMAND);
482 format_agp_rate(t & 7, rate, agp3);
483 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
484 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
485 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
486 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
487 FLAG(t, PCI_AGP_COMMAND_SBA),
488 FLAG(t, PCI_AGP_COMMAND_AGP),
489 FLAG(t, PCI_AGP_COMMAND_GART64),
490 FLAG(t, PCI_AGP_COMMAND_64BIT),
491 FLAG(t, PCI_AGP_COMMAND_FW),
492 rate);
493 }
494
495 static void
496 show_pcix_nobridge(struct device *d, int where)
497 {
498 u16 command;
499 u32 status;
500 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
501
502 printf("PCI-X non-bridge device\n");
503
504 if (verbose < 2)
505 return;
506
507 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
508 return;
509
510 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
511 status = get_conf_long(d, where + PCI_PCIX_STATUS);
512 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
513 FLAG(command, PCI_PCIX_COMMAND_DPERE),
514 FLAG(command, PCI_PCIX_COMMAND_ERO),
515 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
516 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
517 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
518 ((status >> 8) & 0xff),
519 ((status >> 3) & 0x1f),
520 (status & PCI_PCIX_STATUS_FUNCTION),
521 FLAG(status, PCI_PCIX_STATUS_64BIT),
522 FLAG(status, PCI_PCIX_STATUS_133MHZ),
523 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
524 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
525 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
526 1 << (9 + ((status >> 21) & 3U)),
527 max_outstanding[(status >> 23) & 7U],
528 1 << (3 + ((status >> 26) & 7U)),
529 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
530 FLAG(status, PCI_PCIX_STATUS_266MHZ),
531 FLAG(status, PCI_PCIX_STATUS_533MHZ));
532 }
533
534 static void
535 show_pcix_bridge(struct device *d, int where)
536 {
537 static const byte * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
538 u16 secstatus;
539 u32 status, upstcr, downstcr;
540
541 printf("PCI-X bridge device\n");
542
543 if (verbose < 2)
544 return;
545
546 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
547 return;
548
549 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
550 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
551 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
552 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
553 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
554 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
555 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
556 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
557 sec_clock_freq[(secstatus >> 6) & 7]);
558 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
559 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
560 ((status >> 8) & 0xff),
561 ((status >> 3) & 0x1f),
562 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
563 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
564 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
565 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
566 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
567 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
568 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
569 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
570 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
571 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
572 (upstcr >> 16) & 0xffff);
573 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
574 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
575 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
576 (downstcr >> 16) & 0xffff);
577 }
578
579 static void
580 show_pcix(struct device *d, int where)
581 {
582 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
583 {
584 case PCI_HEADER_TYPE_NORMAL:
585 show_pcix_nobridge(d, where);
586 break;
587 case PCI_HEADER_TYPE_BRIDGE:
588 show_pcix_bridge(d, where);
589 break;
590 }
591 }
592
593 static inline char *
594 ht_link_width(unsigned width)
595 {
596 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
597 return widths[width];
598 }
599
600 static inline char *
601 ht_link_freq(unsigned freq)
602 {
603 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
604 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
605 return freqs[freq];
606 }
607
608 static void
609 show_ht_pri(struct device *d, int where, int cmd)
610 {
611 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
612 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
613 char *fmt;
614
615 printf("HyperTransport: Slave or Primary Interface\n");
616 if (verbose < 2)
617 return;
618
619 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
620 return;
621 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
622 if (rid < 0x23 && rid > 0x11)
623 printf("\t\t!!! Possibly incomplete decoding\n");
624
625 if (rid >= 0x23)
626 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
627 else
628 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
629 printf(fmt,
630 (cmd & PCI_HT_PRI_CMD_BUID),
631 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
632 FLAG(cmd, PCI_HT_PRI_CMD_MH),
633 FLAG(cmd, PCI_HT_PRI_CMD_DD),
634 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
635 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
636 if (rid >= 0x23)
637 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
638 else
639 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
640 printf(fmt,
641 FLAG(lctr0, PCI_HT_LCTR_CFLE),
642 FLAG(lctr0, PCI_HT_LCTR_CST),
643 FLAG(lctr0, PCI_HT_LCTR_CFE),
644 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
645 FLAG(lctr0, PCI_HT_LCTR_INIT),
646 FLAG(lctr0, PCI_HT_LCTR_EOC),
647 FLAG(lctr0, PCI_HT_LCTR_TXO),
648 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
649 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
650 FLAG(lctr0, PCI_HT_LCTR_LSEN),
651 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
652 FLAG(lctr0, PCI_HT_LCTR_64B));
653 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
654 if (rid >= 0x23)
655 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
656 else
657 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
658 printf(fmt,
659 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
660 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
661 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
662 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
663 FLAG(lcnf0, PCI_HT_LCNF_DFI),
664 FLAG(lcnf0, PCI_HT_LCNF_DFO),
665 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
666 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
667 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
668 if (rid >= 0x23)
669 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
670 else
671 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
672 printf(fmt,
673 FLAG(lctr1, PCI_HT_LCTR_CFLE),
674 FLAG(lctr1, PCI_HT_LCTR_CST),
675 FLAG(lctr1, PCI_HT_LCTR_CFE),
676 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
677 FLAG(lctr1, PCI_HT_LCTR_INIT),
678 FLAG(lctr1, PCI_HT_LCTR_EOC),
679 FLAG(lctr1, PCI_HT_LCTR_TXO),
680 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
681 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
682 FLAG(lctr1, PCI_HT_LCTR_LSEN),
683 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
684 FLAG(lctr1, PCI_HT_LCTR_64B));
685 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
686 if (rid >= 0x23)
687 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
688 else
689 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
690 printf(fmt,
691 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
692 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
693 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
694 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
695 FLAG(lcnf1, PCI_HT_LCNF_DFI),
696 FLAG(lcnf1, PCI_HT_LCNF_DFO),
697 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
698 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
699 printf("\t\tRevision ID: %u.%02u\n",
700 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
701 if (rid < 0x23)
702 return;
703 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
704 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
705 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
706 FLAG(lfrer0, PCI_HT_LFRER_PROT),
707 FLAG(lfrer0, PCI_HT_LFRER_OV),
708 FLAG(lfrer0, PCI_HT_LFRER_EOC),
709 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
710 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
711 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
712 FLAG(lfcap0, PCI_HT_LFCAP_200),
713 FLAG(lfcap0, PCI_HT_LFCAP_300),
714 FLAG(lfcap0, PCI_HT_LFCAP_400),
715 FLAG(lfcap0, PCI_HT_LFCAP_500),
716 FLAG(lfcap0, PCI_HT_LFCAP_600),
717 FLAG(lfcap0, PCI_HT_LFCAP_800),
718 FLAG(lfcap0, PCI_HT_LFCAP_1000),
719 FLAG(lfcap0, PCI_HT_LFCAP_1200),
720 FLAG(lfcap0, PCI_HT_LFCAP_1400),
721 FLAG(lfcap0, PCI_HT_LFCAP_1600),
722 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
723 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
724 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
725 FLAG(ftr, PCI_HT_FTR_ISOCFC),
726 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
727 FLAG(ftr, PCI_HT_FTR_CRCTM),
728 FLAG(ftr, PCI_HT_FTR_ECTLT),
729 FLAG(ftr, PCI_HT_FTR_64BA),
730 FLAG(ftr, PCI_HT_FTR_UIDRD));
731 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
732 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
733 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
734 FLAG(lfrer1, PCI_HT_LFRER_PROT),
735 FLAG(lfrer1, PCI_HT_LFRER_OV),
736 FLAG(lfrer1, PCI_HT_LFRER_EOC),
737 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
738 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
739 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
740 FLAG(lfcap1, PCI_HT_LFCAP_200),
741 FLAG(lfcap1, PCI_HT_LFCAP_300),
742 FLAG(lfcap1, PCI_HT_LFCAP_400),
743 FLAG(lfcap1, PCI_HT_LFCAP_500),
744 FLAG(lfcap1, PCI_HT_LFCAP_600),
745 FLAG(lfcap1, PCI_HT_LFCAP_800),
746 FLAG(lfcap1, PCI_HT_LFCAP_1000),
747 FLAG(lfcap1, PCI_HT_LFCAP_1200),
748 FLAG(lfcap1, PCI_HT_LFCAP_1400),
749 FLAG(lfcap1, PCI_HT_LFCAP_1600),
750 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
751 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
752 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
753 FLAG(eh, PCI_HT_EH_PFLE),
754 FLAG(eh, PCI_HT_EH_OFLE),
755 FLAG(eh, PCI_HT_EH_PFE),
756 FLAG(eh, PCI_HT_EH_OFE),
757 FLAG(eh, PCI_HT_EH_EOCFE),
758 FLAG(eh, PCI_HT_EH_RFE),
759 FLAG(eh, PCI_HT_EH_CRCFE),
760 FLAG(eh, PCI_HT_EH_SERRFE),
761 FLAG(eh, PCI_HT_EH_CF),
762 FLAG(eh, PCI_HT_EH_RE),
763 FLAG(eh, PCI_HT_EH_PNFE),
764 FLAG(eh, PCI_HT_EH_ONFE),
765 FLAG(eh, PCI_HT_EH_EOCNFE),
766 FLAG(eh, PCI_HT_EH_RNFE),
767 FLAG(eh, PCI_HT_EH_CRCNFE),
768 FLAG(eh, PCI_HT_EH_SERRNFE));
769 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
770 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
771 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
772 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
773 printf("\t\tBus Number: %02x\n", bn);
774 }
775
776 static void
777 show_ht_sec(struct device *d, int where, int cmd)
778 {
779 u16 lctr, lcnf, ftr, eh;
780 u8 rid, lfrer, lfcap, mbu, mlu;
781 char *fmt;
782
783 printf("HyperTransport: Host or Secondary Interface\n");
784 if (verbose < 2)
785 return;
786
787 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
788 return;
789 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
790 if (rid < 0x23 && rid > 0x11)
791 printf("\t\t!!! Possibly incomplete decoding\n");
792
793 if (rid >= 0x23)
794 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
795 else
796 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
797 printf(fmt,
798 FLAG(cmd, PCI_HT_SEC_CMD_WR),
799 FLAG(cmd, PCI_HT_SEC_CMD_DE),
800 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
801 FLAG(cmd, PCI_HT_SEC_CMD_CS),
802 FLAG(cmd, PCI_HT_SEC_CMD_HH),
803 FLAG(cmd, PCI_HT_SEC_CMD_AS),
804 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
805 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
806 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
807 if (rid >= 0x23)
808 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
809 else
810 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
811 printf(fmt,
812 FLAG(lctr, PCI_HT_LCTR_CFLE),
813 FLAG(lctr, PCI_HT_LCTR_CST),
814 FLAG(lctr, PCI_HT_LCTR_CFE),
815 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
816 FLAG(lctr, PCI_HT_LCTR_INIT),
817 FLAG(lctr, PCI_HT_LCTR_EOC),
818 FLAG(lctr, PCI_HT_LCTR_TXO),
819 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
820 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
821 FLAG(lctr, PCI_HT_LCTR_LSEN),
822 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
823 FLAG(lctr, PCI_HT_LCTR_64B));
824 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
825 if (rid >= 0x23)
826 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
827 else
828 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
829 printf(fmt,
830 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
831 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
832 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
833 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
834 FLAG(lcnf, PCI_HT_LCNF_DFI),
835 FLAG(lcnf, PCI_HT_LCNF_DFO),
836 FLAG(lcnf, PCI_HT_LCNF_DFIE),
837 FLAG(lcnf, PCI_HT_LCNF_DFOE));
838 printf("\t\tRevision ID: %u.%02u\n",
839 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
840 if (rid < 0x23)
841 return;
842 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
843 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
844 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
845 FLAG(lfrer, PCI_HT_LFRER_PROT),
846 FLAG(lfrer, PCI_HT_LFRER_OV),
847 FLAG(lfrer, PCI_HT_LFRER_EOC),
848 FLAG(lfrer, PCI_HT_LFRER_CTLT));
849 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
850 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
851 FLAG(lfcap, PCI_HT_LFCAP_200),
852 FLAG(lfcap, PCI_HT_LFCAP_300),
853 FLAG(lfcap, PCI_HT_LFCAP_400),
854 FLAG(lfcap, PCI_HT_LFCAP_500),
855 FLAG(lfcap, PCI_HT_LFCAP_600),
856 FLAG(lfcap, PCI_HT_LFCAP_800),
857 FLAG(lfcap, PCI_HT_LFCAP_1000),
858 FLAG(lfcap, PCI_HT_LFCAP_1200),
859 FLAG(lfcap, PCI_HT_LFCAP_1400),
860 FLAG(lfcap, PCI_HT_LFCAP_1600),
861 FLAG(lfcap, PCI_HT_LFCAP_VEND));
862 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
863 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
864 FLAG(ftr, PCI_HT_FTR_ISOCFC),
865 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
866 FLAG(ftr, PCI_HT_FTR_CRCTM),
867 FLAG(ftr, PCI_HT_FTR_ECTLT),
868 FLAG(ftr, PCI_HT_FTR_64BA),
869 FLAG(ftr, PCI_HT_FTR_UIDRD),
870 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
871 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
872 if (ftr & PCI_HT_SEC_FTR_EXTRS)
873 {
874 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
875 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
876 FLAG(eh, PCI_HT_EH_PFLE),
877 FLAG(eh, PCI_HT_EH_OFLE),
878 FLAG(eh, PCI_HT_EH_PFE),
879 FLAG(eh, PCI_HT_EH_OFE),
880 FLAG(eh, PCI_HT_EH_EOCFE),
881 FLAG(eh, PCI_HT_EH_RFE),
882 FLAG(eh, PCI_HT_EH_CRCFE),
883 FLAG(eh, PCI_HT_EH_SERRFE),
884 FLAG(eh, PCI_HT_EH_CF),
885 FLAG(eh, PCI_HT_EH_RE),
886 FLAG(eh, PCI_HT_EH_PNFE),
887 FLAG(eh, PCI_HT_EH_ONFE),
888 FLAG(eh, PCI_HT_EH_EOCNFE),
889 FLAG(eh, PCI_HT_EH_RNFE),
890 FLAG(eh, PCI_HT_EH_CRCNFE),
891 FLAG(eh, PCI_HT_EH_SERRNFE));
892 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
893 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
894 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
895 }
896 }
897
898 static void
899 show_ht(struct device *d, int where, int cmd)
900 {
901 int type;
902
903 switch (cmd & PCI_HT_CMD_TYP_HI)
904 {
905 case PCI_HT_CMD_TYP_HI_PRI:
906 show_ht_pri(d, where, cmd);
907 return;
908 case PCI_HT_CMD_TYP_HI_SEC:
909 show_ht_sec(d, where, cmd);
910 return;
911 }
912
913 type = cmd & PCI_HT_CMD_TYP;
914 switch (type)
915 {
916 case PCI_HT_CMD_TYP_SW:
917 printf("HyperTransport: Switch\n");
918 break;
919 case PCI_HT_CMD_TYP_IDC:
920 printf("HyperTransport: Interrupt Discovery and Configuration\n");
921 break;
922 case PCI_HT_CMD_TYP_RID:
923 printf("HyperTransport: Revision ID: %u.%02u\n",
924 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
925 break;
926 case PCI_HT_CMD_TYP_UIDC:
927 printf("HyperTransport: UnitID Clumping\n");
928 break;
929 case PCI_HT_CMD_TYP_ECSA:
930 printf("HyperTransport: Extended Configuration Space Access\n");
931 break;
932 case PCI_HT_CMD_TYP_AM:
933 printf("HyperTransport: Address Mapping\n");
934 break;
935 case PCI_HT_CMD_TYP_MSIM:
936 printf("HyperTransport: MSI Mapping\n");
937 break;
938 case PCI_HT_CMD_TYP_DR:
939 printf("HyperTransport: DirectRoute\n");
940 break;
941 case PCI_HT_CMD_TYP_VCS:
942 printf("HyperTransport: VCSet\n");
943 break;
944 case PCI_HT_CMD_TYP_RM:
945 printf("HyperTransport: Retry Mode\n");
946 break;
947 case PCI_HT_CMD_TYP_X86:
948 printf("HyperTransport: X86 (reserved)\n");
949 break;
950 default:
951 printf("HyperTransport: #%02x\n", type >> 11);
952 }
953 }
954
955 static void
956 show_rom(struct device *d, int reg)
957 {
958 struct pci_dev *p = d->dev;
959 pciaddr_t rom = p->rom_base_addr;
960 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
961 u32 flg = get_conf_long(d, reg);
962 word cmd = get_conf_word(d, PCI_COMMAND);
963
964 if (!rom && !flg && !len)
965 return;
966 putchar('\t');
967 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
968 {
969 printf("[virtual] ");
970 flg = rom;
971 }
972 printf("Expansion ROM at ");
973 if (rom & PCI_ROM_ADDRESS_MASK)
974 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
975 else if (flg & PCI_ROM_ADDRESS_MASK)
976 printf("<ignored>");
977 else
978 printf("<unassigned>");
979 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
980 printf(" [disabled]");
981 else if (!(cmd & PCI_COMMAND_MEMORY))
982 printf(" [disabled by cmd]");
983 show_size(len);
984 putchar('\n');
985 }
986
987 static void
988 show_msi(struct device *d, int where, int cap)
989 {
990 int is64;
991 u32 t;
992 u16 w;
993
994 printf("Message Signalled Interrupts: 64bit%c Queue=%d/%d Enable%c\n",
995 FLAG(cap, PCI_MSI_FLAGS_64BIT),
996 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
997 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
998 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
999 if (verbose < 2)
1000 return;
1001 is64 = cap & PCI_MSI_FLAGS_64BIT;
1002 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1003 return;
1004 printf("\t\tAddress: ");
1005 if (is64)
1006 {
1007 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1008 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1009 printf("%08x", t);
1010 }
1011 else
1012 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1013 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1014 printf("%08x Data: %04x\n", t, w);
1015 }
1016
1017 static void show_vendor(void)
1018 {
1019 printf("Vendor Specific Information\n");
1020 }
1021
1022 static void show_debug(void)
1023 {
1024 printf("Debug port\n");
1025 }
1026
1027 static float power_limit(int value, int scale)
1028 {
1029 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1030 return value * scales[scale];
1031 }
1032
1033 static const char *latency_l0s(int value)
1034 {
1035 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1036 return latencies[value];
1037 }
1038
1039 static const char *latency_l1(int value)
1040 {
1041 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1042 return latencies[value];
1043 }
1044
1045 static void show_express_dev(struct device *d, int where, int type)
1046 {
1047 u32 t;
1048 u16 w;
1049
1050 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1051 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1052 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1053 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1054 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1055 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1056 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1057 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1058 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1059 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1060 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1061 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1062 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1063 if (type == PCI_EXP_TYPE_UPSTREAM)
1064 printf("\t\tDevice: SlotPowerLimit %f\n",
1065 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1066 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1067
1068 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1069 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1070 FLAG(w, PCI_EXP_DEVCTL_CERE),
1071 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1072 FLAG(w, PCI_EXP_DEVCTL_FERE),
1073 FLAG(w, PCI_EXP_DEVCTL_URRE));
1074 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1075 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1076 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1077 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1078 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1079 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1080 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1081 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1082 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1083 }
1084
1085 static char *link_speed(int speed)
1086 {
1087 switch (speed)
1088 {
1089 case 1:
1090 return "2.5Gb/s";
1091 default:
1092 return "unknown";
1093 }
1094 }
1095
1096 static char *aspm_support(int code)
1097 {
1098 switch (code)
1099 {
1100 case 1:
1101 return "L0s";
1102 case 3:
1103 return "L0s L1";
1104 default:
1105 return "unknown";
1106 }
1107 }
1108
1109 static const char *aspm_enabled(int code)
1110 {
1111 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1112 return desc[code];
1113 }
1114
1115 static void show_express_link(struct device *d, int where, int type)
1116 {
1117 u32 t;
1118 u16 w;
1119
1120 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1121 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1122 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1123 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1124 t >> 24);
1125 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1126 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1127 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1128 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1129 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1130 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1131 (type == PCI_EXP_TYPE_LEG_END))
1132 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1133 if (w & PCI_EXP_LNKCTL_DISABLE)
1134 printf(" Disabled");
1135 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1136 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1137 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1138 printf("\t\tLink: Speed %s, Width x%d\n",
1139 link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
1140 }
1141
1142 static const char *indicator(int code)
1143 {
1144 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1145 return names[code];
1146 }
1147
1148 static void show_express_slot(struct device *d, int where)
1149 {
1150 u32 t;
1151 u16 w;
1152
1153 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1154 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1155 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1156 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1157 FLAG(t, PCI_EXP_SLTCAP_MRL),
1158 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1159 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1160 FLAG(t, PCI_EXP_SLTCAP_HPC),
1161 FLAG(t, PCI_EXP_SLTCAP_HPS));
1162 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1163 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1164 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1165 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1166 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1167 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1168 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1169 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1170 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1171 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1172 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1173 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1174 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1175 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1176 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1177 }
1178
1179 static void show_express_root(struct device *d, int where)
1180 {
1181 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1182 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1183 FLAG(w, PCI_EXP_RTCTL_SECEE),
1184 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1185 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1186 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1187 }
1188
1189 static void
1190 show_express(struct device *d, int where, int cap)
1191 {
1192 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1193 int size;
1194 int slot = 0;
1195
1196 printf("Express ");
1197 switch (type)
1198 {
1199 case PCI_EXP_TYPE_ENDPOINT:
1200 printf("Endpoint");
1201 break;
1202 case PCI_EXP_TYPE_LEG_END:
1203 printf("Legacy Endpoint");
1204 break;
1205 case PCI_EXP_TYPE_ROOT_PORT:
1206 slot = cap & PCI_EXP_FLAGS_SLOT;
1207 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1208 break;
1209 case PCI_EXP_TYPE_UPSTREAM:
1210 printf("Upstream Port");
1211 break;
1212 case PCI_EXP_TYPE_DOWNSTREAM:
1213 slot = cap & PCI_EXP_FLAGS_SLOT;
1214 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1215 break;
1216 case PCI_EXP_TYPE_PCI_BRIDGE:
1217 printf("PCI/PCI-X Bridge");
1218 break;
1219 default:
1220 printf("Unknown type");
1221 }
1222 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1223 if (verbose < 2)
1224 return;
1225
1226 size = 16;
1227 if (slot)
1228 size = 24;
1229 if (type == PCI_EXP_TYPE_ROOT_PORT)
1230 size = 32;
1231 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1232 return;
1233
1234 show_express_dev(d, where, type);
1235 show_express_link(d, where, type);
1236 if (slot)
1237 show_express_slot(d, where);
1238 if (type == PCI_EXP_TYPE_ROOT_PORT)
1239 show_express_root(d, where);
1240 }
1241
1242 static void
1243 show_msix(struct device *d, int where, int cap)
1244 {
1245 u32 off;
1246
1247 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1248 FLAG(cap, PCI_MSIX_ENABLE),
1249 FLAG(cap, PCI_MSIX_MASK),
1250 (cap & PCI_MSIX_TABSIZE) + 1);
1251 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1252 return;
1253
1254 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1255 printf("\t\tVector table: BAR=%d offset=%08x\n",
1256 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1257 off = get_conf_long(d, where + PCI_MSIX_PBA);
1258 printf("\t\tPBA: BAR=%d offset=%08x\n",
1259 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1260 }
1261
1262 static void
1263 show_slotid(int cap)
1264 {
1265 int esr = cap & 0xff;
1266 int chs = cap >> 8;
1267
1268 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1269 esr & PCI_SID_ESR_NSLOTS,
1270 FLAG(esr, PCI_SID_ESR_FIC),
1271 chs);
1272 }
1273
1274 static void
1275 show_aer(struct device *d UNUSED, int where UNUSED)
1276 {
1277 printf("Advanced Error Reporting\n");
1278 }
1279
1280 static void
1281 show_vc(struct device *d UNUSED, int where UNUSED)
1282 {
1283 printf("Virtual Channel\n");
1284 }
1285
1286 static void
1287 show_dsn(struct device *d, int where)
1288 {
1289 u32 t1, t2;
1290 if (!config_fetch(d, where + 4, 8))
1291 return;
1292 t1 = get_conf_long(d, where + 4);
1293 t2 = get_conf_long(d, where + 8);
1294 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1295 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1296 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1297 }
1298
1299 static void
1300 show_pb(struct device *d UNUSED, int where UNUSED)
1301 {
1302 printf("Power Budgeting\n");
1303 }
1304
1305 static void
1306 show_ext_caps(struct device *d)
1307 {
1308 int where = 0x100;
1309 do
1310 {
1311 u32 header;
1312 int id;
1313
1314 if (!config_fetch(d, where, 4))
1315 break;
1316 header = get_conf_long(d, where);
1317 if (!header)
1318 break;
1319 id = header & 0xffff;
1320 printf("\tCapabilities: [%03x] ", where);
1321 switch (id)
1322 {
1323 case PCI_EXT_CAP_ID_AER:
1324 show_aer(d, where);
1325 break;
1326 case PCI_EXT_CAP_ID_VC:
1327 show_vc(d, where);
1328 break;
1329 case PCI_EXT_CAP_ID_DSN:
1330 show_dsn(d, where);
1331 break;
1332 case PCI_EXT_CAP_ID_PB:
1333 show_pb(d, where);
1334 break;
1335 default:
1336 printf("Unknown (%d)\n", id);
1337 break;
1338 }
1339 where = header >> 20;
1340 } while (where);
1341 }
1342
1343 static void
1344 show_caps(struct device *d)
1345 {
1346 int can_have_ext_caps = 0;
1347
1348 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1349 {
1350 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1351 while (where)
1352 {
1353 int id, next, cap;
1354 printf("\tCapabilities: ");
1355 if (!config_fetch(d, where, 4))
1356 {
1357 puts("<access denied>");
1358 break;
1359 }
1360 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1361 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1362 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1363 printf("[%02x] ", where);
1364 if (id == 0xff)
1365 {
1366 printf("<chain broken>\n");
1367 break;
1368 }
1369 switch (id)
1370 {
1371 case PCI_CAP_ID_PM:
1372 show_pm(d, where, cap);
1373 break;
1374 case PCI_CAP_ID_AGP:
1375 show_agp(d, where, cap);
1376 break;
1377 case PCI_CAP_ID_VPD:
1378 printf("Vital Product Data\n");
1379 break;
1380 case PCI_CAP_ID_SLOTID:
1381 show_slotid(cap);
1382 break;
1383 case PCI_CAP_ID_MSI:
1384 show_msi(d, where, cap);
1385 break;
1386 case PCI_CAP_ID_PCIX:
1387 show_pcix(d, where);
1388 can_have_ext_caps = 1;
1389 break;
1390 case PCI_CAP_ID_HT:
1391 show_ht(d, where, cap);
1392 break;
1393 case PCI_CAP_ID_VNDR:
1394 show_vendor();
1395 break;
1396 case PCI_CAP_ID_DBG:
1397 show_debug();
1398 break;
1399 case PCI_CAP_ID_EXP:
1400 show_express(d, where, cap);
1401 can_have_ext_caps = 1;
1402 break;
1403 case PCI_CAP_ID_MSIX:
1404 show_msix(d, where, cap);
1405 break;
1406 default:
1407 printf("#%02x [%04x]\n", id, cap);
1408 }
1409 where = next;
1410 }
1411 }
1412 if (can_have_ext_caps)
1413 show_ext_caps(d);
1414 }
1415
1416 static void
1417 show_htype0(struct device *d)
1418 {
1419 show_bases(d, 6);
1420 show_rom(d, PCI_ROM_ADDRESS);
1421 show_caps(d);
1422 }
1423
1424 static void
1425 show_htype1(struct device *d)
1426 {
1427 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1428 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1429 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1430 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1431 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1432 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1433 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1434 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1435 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1436 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1437 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1438 int verb = verbose > 2;
1439
1440 show_bases(d, 2);
1441 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1442 get_conf_byte(d, PCI_PRIMARY_BUS),
1443 get_conf_byte(d, PCI_SECONDARY_BUS),
1444 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1445 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1446
1447 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1448 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1449 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1450 else
1451 {
1452 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1453 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1454 if (io_type == PCI_IO_RANGE_TYPE_32)
1455 {
1456 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1457 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1458 }
1459 if (io_base <= io_limit || verb)
1460 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1461 }
1462
1463 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1464 mem_type)
1465 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1466 else
1467 {
1468 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1469 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1470 if (mem_base <= mem_limit || verb)
1471 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1472 }
1473
1474 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1475 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1476 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1477 else
1478 {
1479 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1480 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1481 if (pref_base <= pref_limit || verb)
1482 {
1483 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1484 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1485 else
1486 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1487 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1488 pref_base,
1489 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1490 pref_limit + 0xfffff);
1491 }
1492 }
1493
1494 if (verbose > 1)
1495 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1496 FLAG(sec_stat, PCI_STATUS_66MHZ),
1497 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1498 FLAG(sec_stat, PCI_STATUS_PARITY),
1499 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1500 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1501 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1502 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1503 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1504 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1505 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1506 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1507
1508 show_rom(d, PCI_ROM_ADDRESS1);
1509
1510 if (verbose > 1)
1511 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1512 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1513 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1514 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1515 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1516 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1517 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1518 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1519
1520 show_caps(d);
1521 }
1522
1523 static void
1524 show_htype2(struct device *d)
1525 {
1526 int i;
1527 word cmd = get_conf_word(d, PCI_COMMAND);
1528 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1529 word exca;
1530 int verb = verbose > 2;
1531
1532 show_bases(d, 1);
1533 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1534 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1535 get_conf_byte(d, PCI_CB_CARD_BUS),
1536 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1537 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1538 for(i=0; i<2; i++)
1539 {
1540 int p = 8*i;
1541 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1542 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1543 if (limit > base || verb)
1544 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1545 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1546 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1547 }
1548 for(i=0; i<2; i++)
1549 {
1550 int p = 8*i;
1551 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1552 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1553 if (!(base & PCI_IO_RANGE_TYPE_32))
1554 {
1555 base &= 0xffff;
1556 limit &= 0xffff;
1557 }
1558 base &= PCI_CB_IO_RANGE_MASK;
1559 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1560 if (base <= limit || verb)
1561 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1562 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1563 }
1564
1565 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1566 printf("\tSecondary status: SERR\n");
1567 if (verbose > 1)
1568 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1569 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1570 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1571 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1572 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1573 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1574 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1575 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1576 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1577
1578 if (d->config_cached < 128)
1579 {
1580 printf("\t<access denied to the rest>\n");
1581 return;
1582 }
1583
1584 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1585 if (exca)
1586 printf("\t16-bit legacy interface ports at %04x\n", exca);
1587 }
1588
1589 static void
1590 show_verbose(struct device *d)
1591 {
1592 struct pci_dev *p = d->dev;
1593 word status = get_conf_word(d, PCI_STATUS);
1594 word cmd = get_conf_word(d, PCI_COMMAND);
1595 word class = p->device_class;
1596 byte bist = get_conf_byte(d, PCI_BIST);
1597 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1598 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1599 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1600 byte max_lat, min_gnt;
1601 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1602 unsigned int irq = p->irq;
1603 word subsys_v = 0, subsys_d = 0;
1604 char ssnamebuf[256];
1605
1606 show_terse(d);
1607
1608 switch (htype)
1609 {
1610 case PCI_HEADER_TYPE_NORMAL:
1611 if (class == PCI_CLASS_BRIDGE_PCI)
1612 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1613 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1614 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1615 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1616 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1617 break;
1618 case PCI_HEADER_TYPE_BRIDGE:
1619 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1620 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1621 irq = int_pin = min_gnt = max_lat = 0;
1622 break;
1623 case PCI_HEADER_TYPE_CARDBUS:
1624 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1625 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1626 min_gnt = max_lat = 0;
1627 if (d->config_cached >= 128)
1628 {
1629 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1630 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1631 }
1632 break;
1633 default:
1634 printf("\t!!! Unknown header type %02x\n", htype);
1635 return;
1636 }
1637
1638 if (subsys_v && subsys_v != 0xffff)
1639 printf("\tSubsystem: %s\n",
1640 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1641 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1642 p->vendor_id, p->device_id, subsys_v, subsys_d));
1643
1644 if (verbose > 1)
1645 {
1646 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1647 FLAG(cmd, PCI_COMMAND_IO),
1648 FLAG(cmd, PCI_COMMAND_MEMORY),
1649 FLAG(cmd, PCI_COMMAND_MASTER),
1650 FLAG(cmd, PCI_COMMAND_SPECIAL),
1651 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1652 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1653 FLAG(cmd, PCI_COMMAND_PARITY),
1654 FLAG(cmd, PCI_COMMAND_WAIT),
1655 FLAG(cmd, PCI_COMMAND_SERR),
1656 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1657 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1658 FLAG(status, PCI_STATUS_CAP_LIST),
1659 FLAG(status, PCI_STATUS_66MHZ),
1660 FLAG(status, PCI_STATUS_UDF),
1661 FLAG(status, PCI_STATUS_FAST_BACK),
1662 FLAG(status, PCI_STATUS_PARITY),
1663 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1664 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1665 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1666 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1667 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1668 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1669 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1670 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1671 if (cmd & PCI_COMMAND_MASTER)
1672 {
1673 printf("\tLatency: %d", latency);
1674 if (min_gnt || max_lat)
1675 {
1676 printf(" (");
1677 if (min_gnt)
1678 printf("%dns min", min_gnt*250);
1679 if (min_gnt && max_lat)
1680 printf(", ");
1681 if (max_lat)
1682 printf("%dns max", max_lat*250);
1683 putchar(')');
1684 }
1685 if (cache_line)
1686 printf(", Cache Line Size: %d bytes", cache_line * 4);
1687 putchar('\n');
1688 }
1689 if (int_pin || irq)
1690 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1691 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1692 }
1693 else
1694 {
1695 printf("\tFlags: ");
1696 if (cmd & PCI_COMMAND_MASTER)
1697 printf("bus master, ");
1698 if (cmd & PCI_COMMAND_VGA_PALETTE)
1699 printf("VGA palette snoop, ");
1700 if (cmd & PCI_COMMAND_WAIT)
1701 printf("stepping, ");
1702 if (cmd & PCI_COMMAND_FAST_BACK)
1703 printf("fast Back2Back, ");
1704 if (status & PCI_STATUS_66MHZ)
1705 printf("66MHz, ");
1706 if (status & PCI_STATUS_UDF)
1707 printf("user-definable features, ");
1708 printf("%s devsel",
1709 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1710 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1711 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1712 if (cmd & PCI_COMMAND_MASTER)
1713 printf(", latency %d", latency);
1714 if (irq)
1715 printf(", IRQ " PCIIRQ_FMT, irq);
1716 putchar('\n');
1717 }
1718
1719 if (bist & PCI_BIST_CAPABLE)
1720 {
1721 if (bist & PCI_BIST_START)
1722 printf("\tBIST is running\n");
1723 else
1724 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1725 }
1726
1727 switch (htype)
1728 {
1729 case PCI_HEADER_TYPE_NORMAL:
1730 show_htype0(d);
1731 break;
1732 case PCI_HEADER_TYPE_BRIDGE:
1733 show_htype1(d);
1734 break;
1735 case PCI_HEADER_TYPE_CARDBUS:
1736 show_htype2(d);
1737 break;
1738 }
1739 }
1740
1741 static void
1742 show_hex_dump(struct device *d)
1743 {
1744 unsigned int i, cnt;
1745
1746 cnt = d->config_cached;
1747 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1748 {
1749 cnt = 256;
1750 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1751 cnt = 4096;
1752 }
1753
1754 for(i=0; i<cnt; i++)
1755 {
1756 if (! (i & 15))
1757 printf("%02x:", i);
1758 printf(" %02x", get_conf_byte(d, i));
1759 if ((i & 15) == 15)
1760 putchar('\n');
1761 }
1762 }
1763
1764 static void
1765 show_machine(struct device *d)
1766 {
1767 struct pci_dev *p = d->dev;
1768 int c;
1769 word sv_id=0, sd_id=0;
1770 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1771
1772 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1773 {
1774 case PCI_HEADER_TYPE_NORMAL:
1775 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1776 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1777 break;
1778 case PCI_HEADER_TYPE_CARDBUS:
1779 if (d->config_cached >= 128)
1780 {
1781 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1782 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1783 }
1784 break;
1785 }
1786
1787 if (verbose)
1788 {
1789 printf("Device:\t");
1790 show_slot_name(d);
1791 putchar('\n');
1792 printf("Class:\t%s\n",
1793 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1794 printf("Vendor:\t%s\n",
1795 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1796 printf("Device:\t%s\n",
1797 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1798 if (sv_id && sv_id != 0xffff)
1799 {
1800 printf("SVendor:\t%s\n",
1801 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1802 printf("SDevice:\t%s\n",
1803 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1804 }
1805 if (c = get_conf_byte(d, PCI_REVISION_ID))
1806 printf("Rev:\t%02x\n", c);
1807 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1808 printf("ProgIf:\t%02x\n", c);
1809 }
1810 else
1811 {
1812 show_slot_name(d);
1813 printf(" \"%s\" \"%s\" \"%s\"",
1814 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS,
1815 p->device_class),
1816 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR,
1817 p->vendor_id, p->device_id),
1818 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE,
1819 p->vendor_id, p->device_id));
1820 if (c = get_conf_byte(d, PCI_REVISION_ID))
1821 printf(" -r%02x", c);
1822 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1823 printf(" -p%02x", c);
1824 if (sv_id && sv_id != 0xffff)
1825 printf(" \"%s\" \"%s\"",
1826 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id),
1827 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1828 else
1829 printf(" \"\" \"\"");
1830 putchar('\n');
1831 }
1832 }
1833
1834 static void
1835 show_device(struct device *d)
1836 {
1837 if (machine_readable)
1838 show_machine(d);
1839 else if (verbose)
1840 show_verbose(d);
1841 else
1842 show_terse(d);
1843 if (show_hex)
1844 show_hex_dump(d);
1845 if (verbose || show_hex)
1846 putchar('\n');
1847 }
1848
1849 static void
1850 show(void)
1851 {
1852 struct device *d;
1853
1854 for(d=first_dev; d; d=d->next)
1855 show_device(d);
1856 }
1857
1858 /* Tree output */
1859
1860 struct bridge {
1861 struct bridge *chain; /* Single-linked list of bridges */
1862 struct bridge *next, *child; /* Tree of bridges */
1863 struct bus *first_bus; /* List of buses connected to this bridge */
1864 unsigned int domain;
1865 unsigned int primary, secondary, subordinate; /* Bus numbers */
1866 struct device *br_dev;
1867 };
1868
1869 struct bus {
1870 unsigned int domain;
1871 unsigned int number;
1872 struct bus *sibling;
1873 struct device *first_dev, **last_dev;
1874 };
1875
1876 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1877
1878 static struct bus *
1879 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1880 {
1881 struct bus *bus;
1882
1883 for(bus=b->first_bus; bus; bus=bus->sibling)
1884 if (bus->domain == domain && bus->number == n)
1885 break;
1886 return bus;
1887 }
1888
1889 static struct bus *
1890 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1891 {
1892 struct bus *bus = xmalloc(sizeof(struct bus));
1893 bus->domain = domain;
1894 bus->number = n;
1895 bus->sibling = b->first_bus;
1896 bus->first_dev = NULL;
1897 bus->last_dev = &bus->first_dev;
1898 b->first_bus = bus;
1899 return bus;
1900 }
1901
1902 static void
1903 insert_dev(struct device *d, struct bridge *b)
1904 {
1905 struct pci_dev *p = d->dev;
1906 struct bus *bus;
1907
1908 if (! (bus = find_bus(b, p->domain, p->bus)))
1909 {
1910 struct bridge *c;
1911 for(c=b->child; c; c=c->next)
1912 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1913 {
1914 insert_dev(d, c);
1915 return;
1916 }
1917 bus = new_bus(b, p->domain, p->bus);
1918 }
1919 /* Simple insertion at the end _does_ guarantee the correct order as the
1920 * original device list was sorted by (domain, bus, devfn) lexicographically
1921 * and all devices on the new list have the same bus number.
1922 */
1923 *bus->last_dev = d;
1924 bus->last_dev = &d->next;
1925 d->next = NULL;
1926 }
1927
1928 static void
1929 grow_tree(void)
1930 {
1931 struct device *d, *d2;
1932 struct bridge **last_br, *b;
1933
1934 /* Build list of bridges */
1935
1936 last_br = &host_bridge.chain;
1937 for(d=first_dev; d; d=d->next)
1938 {
1939 word class = d->dev->device_class;
1940 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1941 if (class == PCI_CLASS_BRIDGE_PCI &&
1942 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
1943 {
1944 b = xmalloc(sizeof(struct bridge));
1945 b->domain = d->dev->domain;
1946 if (ht == PCI_HEADER_TYPE_BRIDGE)
1947 {
1948 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
1949 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
1950 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
1951 }
1952 else
1953 {
1954 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
1955 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
1956 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
1957 }
1958 *last_br = b;
1959 last_br = &b->chain;
1960 b->next = b->child = NULL;
1961 b->first_bus = NULL;
1962 b->br_dev = d;
1963 }
1964 }
1965 *last_br = NULL;
1966
1967 /* Create a bridge tree */
1968
1969 for(b=&host_bridge; b; b=b->chain)
1970 {
1971 struct bridge *c, *best;
1972 best = NULL;
1973 for(c=&host_bridge; c; c=c->chain)
1974 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
1975 b->primary >= c->secondary && b->primary <= c->subordinate &&
1976 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
1977 best = c;
1978 if (best)
1979 {
1980 b->next = best->child;
1981 best->child = b;
1982 }
1983 }
1984
1985 /* Insert secondary bus for each bridge */
1986
1987 for(b=&host_bridge; b; b=b->chain)
1988 if (!find_bus(b, b->domain, b->secondary))
1989 new_bus(b, b->domain, b->secondary);
1990
1991 /* Create bus structs and link devices */
1992
1993 for(d=first_dev; d;)
1994 {
1995 d2 = d->next;
1996 insert_dev(d, &host_bridge);
1997 d = d2;
1998 }
1999 }
2000
2001 static void
2002 print_it(byte *line, byte *p)
2003 {
2004 *p++ = '\n';
2005 *p = 0;
2006 fputs(line, stdout);
2007 for(p=line; *p; p++)
2008 if (*p == '+' || *p == '|')
2009 *p = '|';
2010 else
2011 *p = ' ';
2012 }
2013
2014 static void show_tree_bridge(struct bridge *, byte *, byte *);
2015
2016 static void
2017 show_tree_dev(struct device *d, byte *line, byte *p)
2018 {
2019 struct pci_dev *q = d->dev;
2020 struct bridge *b;
2021 char namebuf[256];
2022
2023 p += sprintf(p, "%02x.%x", q->dev, q->func);
2024 for(b=&host_bridge; b; b=b->chain)
2025 if (b->br_dev == d)
2026 {
2027 if (b->secondary == b->subordinate)
2028 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2029 else
2030 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2031 show_tree_bridge(b, line, p);
2032 return;
2033 }
2034 if (verbose)
2035 p += sprintf(p, " %s",
2036 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2037 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2038 q->vendor_id, q->device_id));
2039 print_it(line, p);
2040 }
2041
2042 static void
2043 show_tree_bus(struct bus *b, byte *line, byte *p)
2044 {
2045 if (!b->first_dev)
2046 print_it(line, p);
2047 else if (!b->first_dev->next)
2048 {
2049 *p++ = '-';
2050 *p++ = '-';
2051 show_tree_dev(b->first_dev, line, p);
2052 }
2053 else
2054 {
2055 struct device *d = b->first_dev;
2056 while (d->next)
2057 {
2058 p[0] = '+';
2059 p[1] = '-';
2060 show_tree_dev(d, line, p+2);
2061 d = d->next;
2062 }
2063 p[0] = '\\';
2064 p[1] = '-';
2065 show_tree_dev(d, line, p+2);
2066 }
2067 }
2068
2069 static void
2070 show_tree_bridge(struct bridge *b, byte *line, byte *p)
2071 {
2072 *p++ = '-';
2073 if (!b->first_bus->sibling)
2074 {
2075 if (b == &host_bridge)
2076 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2077 show_tree_bus(b->first_bus, line, p);
2078 }
2079 else
2080 {
2081 struct bus *u = b->first_bus;
2082 byte *k;
2083
2084 while (u->sibling)
2085 {
2086 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2087 show_tree_bus(u, line, k);
2088 u = u->sibling;
2089 }
2090 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2091 show_tree_bus(u, line, k);
2092 }
2093 }
2094
2095 static void
2096 show_forest(void)
2097 {
2098 char line[256];
2099
2100 grow_tree();
2101 show_tree_bridge(&host_bridge, line, line);
2102 }
2103
2104 /* Bus mapping mode */
2105
2106 struct bus_bridge {
2107 struct bus_bridge *next;
2108 byte this, dev, func, first, last, bug;
2109 };
2110
2111 struct bus_info {
2112 byte exists;
2113 byte guestbook;
2114 struct bus_bridge *bridges, *via;
2115 };
2116
2117 static struct bus_info *bus_info;
2118
2119 static void
2120 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2121 {
2122 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2123 struct pci_dev *p = d->dev;
2124
2125 b->next = bi->bridges;
2126 bi->bridges = b;
2127 b->this = get_conf_byte(d, np);
2128 b->dev = p->dev;
2129 b->func = p->func;
2130 b->first = get_conf_byte(d, ns);
2131 b->last = get_conf_byte(d, nl);
2132 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2133 p->bus, p->dev, p->func, b->this, b->first, b->last);
2134 if (b->this != p->bus)
2135 printf("!!! Bridge points to invalid primary bus.\n");
2136 if (b->first > b->last)
2137 {
2138 printf("!!! Bridge points to invalid bus range.\n");
2139 b->last = b->first;
2140 }
2141 }
2142
2143 static void
2144 do_map_bus(int bus)
2145 {
2146 int dev, func;
2147 int verbose = pacc->debugging;
2148 struct bus_info *bi = bus_info + bus;
2149 struct device *d;
2150
2151 if (verbose)
2152 printf("Mapping bus %02x\n", bus);
2153 for(dev = 0; dev < 32; dev++)
2154 if (filter.slot < 0 || filter.slot == dev)
2155 {
2156 int func_limit = 1;
2157 for(func = 0; func < func_limit; func++)
2158 if (filter.func < 0 || filter.func == func)
2159 {
2160 /* XXX: Bus mapping supports only domain 0 */
2161 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2162 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2163 if (vendor && vendor != 0xffff)
2164 {
2165 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2166 func_limit = 8;
2167 if (verbose)
2168 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2169 bi->exists = 1;
2170 if (d = scan_device(p))
2171 {
2172 show_device(d);
2173 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2174 {
2175 case PCI_HEADER_TYPE_BRIDGE:
2176 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2177 break;
2178 case PCI_HEADER_TYPE_CARDBUS:
2179 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2180 break;
2181 }
2182 free(d);
2183 }
2184 else if (verbose)
2185 printf("But it was filtered out.\n");
2186 }
2187 pci_free_dev(p);
2188 }
2189 }
2190 }
2191
2192 static void
2193 do_map_bridges(int bus, int min, int max)
2194 {
2195 struct bus_info *bi = bus_info + bus;
2196 struct bus_bridge *b;
2197
2198 bi->guestbook = 1;
2199 for(b=bi->bridges; b; b=b->next)
2200 {
2201 if (bus_info[b->first].guestbook)
2202 b->bug = 1;
2203 else if (b->first < min || b->last > max)
2204 b->bug = 2;
2205 else
2206 {
2207 bus_info[b->first].via = b;
2208 do_map_bridges(b->first, b->first, b->last);
2209 }
2210 }
2211 }
2212
2213 static void
2214 map_bridges(void)
2215 {
2216 int i;
2217
2218 printf("\nSummary of buses:\n\n");
2219 for(i=0; i<256; i++)
2220 if (bus_info[i].exists && !bus_info[i].guestbook)
2221 do_map_bridges(i, 0, 255);
2222 for(i=0; i<256; i++)
2223 {
2224 struct bus_info *bi = bus_info + i;
2225 struct bus_bridge *b = bi->via;
2226
2227 if (bi->exists)
2228 {
2229 printf("%02x: ", i);
2230 if (b)
2231 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2232 else if (!i)
2233 printf("Primary host bus\n");
2234 else
2235 printf("Secondary host bus (?)\n");
2236 }
2237 for(b=bi->bridges; b; b=b->next)
2238 {
2239 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2240 switch (b->bug)
2241 {
2242 case 1:
2243 printf(" <overlap bug>");
2244 break;
2245 case 2:
2246 printf(" <crossing bug>");
2247 break;
2248 }
2249 putchar('\n');
2250 }
2251 }
2252 }
2253
2254 static void
2255 map_the_bus(void)
2256 {
2257 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2258 pacc->method == PCI_ACCESS_DUMP)
2259 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2260 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2261 bzero(bus_info, sizeof(struct bus_info) * 256);
2262 if (filter.bus >= 0)
2263 do_map_bus(filter.bus);
2264 else
2265 {
2266 int bus;
2267 for(bus=0; bus<256; bus++)
2268 do_map_bus(bus);
2269 }
2270 map_bridges();
2271 }
2272
2273 /* Main */
2274
2275 int
2276 main(int argc, char **argv)
2277 {
2278 int i;
2279 char *msg;
2280
2281 if (argc == 2 && !strcmp(argv[1], "--version"))
2282 {
2283 puts("lspci version " PCIUTILS_VERSION);
2284 return 0;
2285 }
2286
2287 pacc = pci_alloc();
2288 pacc->error = die;
2289 pci_filter_init(pacc, &filter);
2290
2291 while ((i = getopt(argc, argv, options)) != -1)
2292 switch (i)
2293 {
2294 case 'n':
2295 pacc->numeric_ids++;
2296 break;
2297 case 'v':
2298 verbose++;
2299 break;
2300 case 'b':
2301 pacc->buscentric = 1;
2302 buscentric_view = 1;
2303 break;
2304 case 's':
2305 if (msg = pci_filter_parse_slot(&filter, optarg))
2306 die("-s: %s", msg);
2307 break;
2308 case 'd':
2309 if (msg = pci_filter_parse_id(&filter, optarg))
2310 die("-d: %s", msg);
2311 break;
2312 case 'x':
2313 show_hex++;
2314 break;
2315 case 't':
2316 show_tree++;
2317 break;
2318 case 'i':
2319 pacc->id_file_name = optarg;
2320 break;
2321 case 'm':
2322 machine_readable++;
2323 break;
2324 case 'M':
2325 map_mode++;
2326 break;
2327 case 'D':
2328 show_domains = 2;
2329 break;
2330 default:
2331 if (parse_generic_option(i, pacc, optarg))
2332 break;
2333 bad:
2334 fprintf(stderr, help_msg, pacc->id_file_name);
2335 return 1;
2336 }
2337 if (optind < argc)
2338 goto bad;
2339
2340 pci_init(pacc);
2341 if (map_mode)
2342 map_the_bus();
2343 else
2344 {
2345 scan_devices();
2346 sort_them();
2347 if (show_tree)
2348 show_forest();
2349 else
2350 show();
2351 }
2352 pci_cleanup(pacc);
2353
2354 return 0;
2355 }
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