[thirdparty/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <wdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
#include <asm/io.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
#endif

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	u32 ver;
	char *name;
	bool evexists;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x10,
		.ver = 0x2c,
		.name = "3cg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x11,
		.ver = 0x2c,
		.name = "2cg",
	},
	{
		.id = 0x20,
		.name = "5ev",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x100,
		.name = "5eg",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x12c,
		.name = "5cg",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.name = "4ev",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x100,
		.name = "4eg",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x12c,
		.name = "4cg",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.name = "7ev",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x100,
		.name = "7eg",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x12c,
		.name = "7cg",
		.evexists = 1,
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x38,
		.ver = 0x2c,
		.name = "9cg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x39,
		.ver = 0x2c,
		.name = "6cg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{ /* For testing purpose only */
		.id = 0x50,
		.ver = 0x2c,
		.name = "15cg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
	{
		.id = 0x61,
		.name = "21dr",
	},
	{
		.id = 0x63,
		.name = "23dr",
	},
	{
		.id = 0x65,
		.name = "25dr",
	},
	{
		.id = 0x64,
		.name = "27dr",
	},
	{
		.id = 0x60,
		.name = "28dr",
	},
	{
		.id = 0x62,
		.name = "29dr",
	},
	{
		.id = 0x66,
		.name = "39dr",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 * regs[1][63:32] = CSU.IDCODE2 register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		case IDCODE2:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#define ZYNQMP_VERSION_SIZE		9
#define ZYNQMP_PL_STATUS_BIT		9
#define ZYNQMP_IPDIS_VCU_BIT		8
#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
#define ZYNQMP_CSU_VCUDIS_VER_MASK	ZYNQMP_CSU_VERSION_MASK & \
					~BIT(ZYNQMP_IPDIS_VCU_BIT)
#define MAX_VARIANTS_EV			3

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id, ver, j;
	char *buf;
	static char name[ZYNQMP_VERSION_SIZE];

	id = chip_id(IDCODE);
	ver = chip_id(IDCODE2);

	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if (zynqmp_devices[i].id == id) {
			if (zynqmp_devices[i].evexists &&
			    !(ver & ZYNQMP_PL_STATUS_MASK))
				break;
			if (zynqmp_devices[i].ver == (ver &
			    ZYNQMP_CSU_VERSION_MASK))
				break;
		}
	}

	if (i >= ARRAY_SIZE(zynqmp_devices))
		return "unknown";

	strncat(name, "zu", 2);
	if (!zynqmp_devices[i].evexists ||
	    (ver & ZYNQMP_PL_STATUS_MASK)) {
		strncat(name, zynqmp_devices[i].name,
			ZYNQMP_VERSION_SIZE - 3);
		return name;
	}

	/*
	 * Here we are means, PL not powered up and ev variant
	 * exists. So, we need to ignore VCU disable bit(8) in
	 * version and findout if its CG or EG/EV variant.
	 */
	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
		if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
		    (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
			strncat(name, zynqmp_devices[i].name,
				ZYNQMP_VERSION_SIZE - 3);
			break;
		}
	}

	if (j >= MAX_VARIANTS_EV)
		return "unknown";

	if (strstr(name, "eg") || strstr(name, "ev")) {
		buf = strstr(name, "e");
		*buf = '\0';
	}

	return name;
}
#endif

int board_early_init_f(void)
{
	int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	u32 pm_api_version;

	pm_api_version = zynqmp_pmufw_version();
	printf("PMUFW:\tv%d.%d\n",
	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);

	if (pm_api_version < ZYNQMP_PM_VERSION)
		panic("PMUFW version error. Expected: v%d.%d\n",
		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
#endif

#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	ret = psu_init();
#endif

	return ret;
}

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		zynqmppl.name = zynqmp_get_silicon_idcode_name();
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
		debug("Watchdog: Not found by seq!\n");
		if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
			puts("Watchdog: Not found!\n");
			return 0;
		}
	}

	wdt_start(watchdog_dev, 0, 0);
	puts("Watchdog: Started\n");
#endif

	return 0;
}

#ifdef CONFIG_WATCHDOG
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
# if !defined(CONFIG_SPL_BUILD)
	static ulong next_reset;
	ulong now;

	if (!watchdog_dev)
		return;

	now = timer_get_us();

	/* Do not reset the watchdog too often */
	if (now > next_reset) {
		wdt_reset(watchdog_dev);
		next_reset = now + 1000;
	}
# endif
}
#endif

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (!val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
			 char * const argv[])
{
	int ret = 0;

	if (current_el() > 1) {
		smp_kick_all_cpus();
		dcache_disable();
		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
				    ES_TO_AARCH64);
	} else {
		printf("FAIL: current EL is not above EL1\n");
		ret = EINVAL;
	}
	return ret;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS)
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = get_effective_memsize();
#endif

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

#if defined(CONFIG_BOARD_LATE_INIT)
static const struct {
	u32 bit;
	const char *name;
} reset_reasons[] = {
	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
	{ RESET_REASON_SOFT, "SOFT" },
	{ RESET_REASON_SRST, "SRST" },
	{ RESET_REASON_PSONLY, "PS-ONLY" },
	{ RESET_REASON_PMU, "PMU" },
	{ RESET_REASON_INTERNAL, "INTERNAL" },
	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
	{}
};

static int reset_reason(void)
{
	u32 reg;
	int i, ret;
	const char *reason = NULL;

	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
	if (ret)
		return -EINVAL;

	puts("Reset reason:\t");

	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
		if (reg & reset_reasons[i].bit) {
			reason = reset_reasons[i].name;
			printf("%s ", reset_reasons[i].name);
			break;
		}
	}

	puts("\n");

	env_set("reset_reason", reason);

	ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
	if (ret)
		return -EINVAL;

	return ret;
}

static int set_fdtfile(void)
{
	char *compatible, *fdtfile;
	const char *suffix = ".dtb";
	const char *vendor = "xilinx/";

	if (env_get("fdtfile"))
		return 0;

	compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
	if (compatible) {
		debug("Compatible: %s\n", compatible);

		/* Discard vendor prefix */
		strsep(&compatible, ",");

		fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
				 strlen(suffix) + 1);
		if (!fdtfile)
			return -ENOMEM;

		sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);

		env_set("fdtfile", fdtfile);
		free(fdtfile);
	}

	return 0;
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;
	int ret;

#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
	usb_ether_init();
#endif

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	ret = set_fdtfile();
	if (ret)
		return ret;

	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	if (ret)
		return -EINVAL;

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		env_set("modeboot", "usb_dfu_spl");
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		env_set("modeboot", "jtagboot");
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		env_set("modeboot", "qspiboot");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "emmcboot");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "mmc@ff160000", &dev) &&
		    uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@ff160000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		env_set("modeboot", "sdboot");
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "mmc@ff170000", &dev) &&
		    uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@ff170000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		env_set("modeboot", "sdboot");
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		env_set("modeboot", "nandboot");
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	reset_reason();

	return 0;
}
#endif

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
84c7204b MS	2	/*
	3	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
84c7204b MS	5	*/
	6
	7	#include <common.h>
679b994a	8	#include <sata.h>
6fe6f135 MS	9	#include <ahci.h>
6fe6f135 MS	10	#include <scsi.h>
b72894f1	11	#include <malloc.h>
4490e013	12	#include <wdt.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
84c7204b MS	15	#include <asm/arch/sys_proto.h>
2ad341ed	16	#include <asm/arch/psu_init_gpl.h>
84c7204b	17	#include <asm/io.h>
2882b39d	18	#include <dm/device.h>
4490e013	19	#include <dm/uclass.h>
16fa00a7 SDPP	20	#include <usb.h>
16fa00a7 SDPP	21	#include <dwc3-uboot.h>
47e60cbd	22	#include <zynqmppl.h>
9feff385	23	#include <g_dnl.h>
84c7204b MS	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
4490e013	27	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
ccd063e9	28	static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
4490e013 MS	29	#endif
4490e013 MS	30
47e60cbd MS	31	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	32	!defined(CONFIG_SPL_BUILD)
	33	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	34
	35	static const struct {
8ebdf9ef	36	u32 id;
494fffe7	37	u32 ver;
47e60cbd	38	char *name;
83bf2ff0	39	bool evexists;
47e60cbd MS	40	} zynqmp_devices[] = {
	41	{
	42	.id = 0x10,
	43	.name = "3eg",
	44	},
494fffe7 MS	45	{
	46	.id = 0x10,
	47	.ver = 0x2c,
	48	.name = "3cg",
	49	},
47e60cbd MS	50	{
	51	.id = 0x11,
	52	.name = "2eg",
	53	},
494fffe7 MS	54	{
	55	.id = 0x11,
	56	.ver = 0x2c,
	57	.name = "2cg",
	58	},
47e60cbd MS	59	{
	60	.id = 0x20,
	61	.name = "5ev",
83bf2ff0	62	.evexists = 1,
47e60cbd	63	},
494fffe7 MS	64	{
	65	.id = 0x20,
	66	.ver = 0x100,
	67	.name = "5eg",
83bf2ff0	68	.evexists = 1,
494fffe7 MS	69	},
	70	{
	71	.id = 0x20,
	72	.ver = 0x12c,
	73	.name = "5cg",
5473f245	74	.evexists = 1,
494fffe7	75	},
47e60cbd MS	76	{
	77	.id = 0x21,
	78	.name = "4ev",
83bf2ff0	79	.evexists = 1,
47e60cbd	80	},
494fffe7 MS	81	{
	82	.id = 0x21,
	83	.ver = 0x100,
	84	.name = "4eg",
83bf2ff0	85	.evexists = 1,
494fffe7 MS	86	},
	87	{
	88	.id = 0x21,
	89	.ver = 0x12c,
	90	.name = "4cg",
5473f245	91	.evexists = 1,
494fffe7	92	},
47e60cbd MS	93	{
	94	.id = 0x30,
	95	.name = "7ev",
83bf2ff0	96	.evexists = 1,
47e60cbd	97	},
494fffe7 MS	98	{
	99	.id = 0x30,
	100	.ver = 0x100,
	101	.name = "7eg",
83bf2ff0	102	.evexists = 1,
494fffe7 MS	103	},
	104	{
	105	.id = 0x30,
	106	.ver = 0x12c,
	107	.name = "7cg",
5473f245	108	.evexists = 1,
494fffe7	109	},
47e60cbd MS	110	{
	111	.id = 0x38,
	112	.name = "9eg",
	113	},
494fffe7 MS	114	{
	115	.id = 0x38,
	116	.ver = 0x2c,
	117	.name = "9cg",
	118	},
47e60cbd MS	119	{
	120	.id = 0x39,
	121	.name = "6eg",
	122	},
494fffe7 MS	123	{
	124	.id = 0x39,
	125	.ver = 0x2c,
	126	.name = "6cg",
	127	},
47e60cbd MS	128	{
	129	.id = 0x40,
	130	.name = "11eg",
	131	},
494fffe7 MS	132	{ /* For testing purpose only */
	133	.id = 0x50,
	134	.ver = 0x2c,
	135	.name = "15cg",
	136	},
47e60cbd MS	137	{
	138	.id = 0x50,
	139	.name = "15eg",
	140	},
	141	{
	142	.id = 0x58,
	143	.name = "19eg",
	144	},
	145	{
	146	.id = 0x59,
	147	.name = "17eg",
	148	},
b030fedf MS	149	{
	150	.id = 0x61,
	151	.name = "21dr",
	152	},
	153	{
	154	.id = 0x63,
	155	.name = "23dr",
	156	},
	157	{
	158	.id = 0x65,
	159	.name = "25dr",
	160	},
	161	{
	162	.id = 0x64,
	163	.name = "27dr",
	164	},
	165	{
	166	.id = 0x60,
	167	.name = "28dr",
	168	},
	169	{
	170	.id = 0x62,
	171	.name = "29dr",
	172	},
c7490907 SDPP	173	{
	174	.id = 0x66,
	175	.name = "39dr",
	176	},
47e60cbd	177	};
74ba69db	178	#endif
47e60cbd	179
f52bf5a3	180	int chip_id(unsigned char id)
47e60cbd MS	181	{
47e60cbd MS	182	struct pt_regs regs;
db3123b4	183	int val = -EINVAL;
47e60cbd	184
74ba69db SDPP	185	if (current_el() != 3) {
	186	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	187	regs.regs[1] = 0;
	188	regs.regs[2] = 0;
	189	regs.regs[3] = 0;
	190
	191	smc_call(&regs);
	192
	193	/*
	194	* SMC returns:
	195	* regs[0][31:0] = status of the operation
	196	* regs[0][63:32] = CSU.IDCODE register
	197	* regs[1][31:0] = CSU.version register
494fffe7	198	* regs[1][63:32] = CSU.IDCODE2 register
74ba69db SDPP	199	*/
	200	switch (id) {
	201	case IDCODE:
	202	regs.regs[0] = upper_32_bits(regs.regs[0]);
	203	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	204	ZYNQMP_CSU_IDCODE_SVD_MASK;
	205	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	206	val = regs.regs[0];
	207	break;
	208	case VERSION:
	209	regs.regs[1] = lower_32_bits(regs.regs[1]);
	210	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	211	val = regs.regs[1];
	212	break;
494fffe7 MS	213	case IDCODE2:
	214	regs.regs[1] = lower_32_bits(regs.regs[1]);
	215	regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
	216	val = regs.regs[1];
	217	break;
74ba69db SDPP	218	default:
	219	printf("%s, Invalid Req:0x%x\n", __func__, id);
	220	}
	221	} else {
	222	switch (id) {
	223	case IDCODE:
	224	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	225	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	226	ZYNQMP_CSU_IDCODE_SVD_MASK;
	227	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	228	break;
	229	case VERSION:
	230	val = readl(ZYNQMP_CSU_VER_ADDR);
	231	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	232	break;
	233	default:
	234	printf("%s, Invalid Req:0x%x\n", __func__, id);
	235	}
db3123b4	236	}
0cba6abb	237
db3123b4	238	return val;
47e60cbd MS	239	}
47e60cbd MS	240
83bf2ff0 SDPP	241	#define ZYNQMP_VERSION_SIZE 9
83bf2ff0 SDPP	242	#define ZYNQMP_PL_STATUS_BIT 9
5473f245	243	#define ZYNQMP_IPDIS_VCU_BIT 8
83bf2ff0 SDPP	244	#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
83bf2ff0 SDPP	245	#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
5473f245 SDPP	246	#define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
	247	~BIT(ZYNQMP_IPDIS_VCU_BIT)
	248	#define MAX_VARIANTS_EV 3
83bf2ff0	249
74ba69db SDPP	250	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	251	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	252	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	253	{
5473f245	254	u32 i, id, ver, j;
83bf2ff0 SDPP	255	char *buf;
83bf2ff0 SDPP	256	static char name[ZYNQMP_VERSION_SIZE];
47e60cbd	257
db3123b4	258	id = chip_id(IDCODE);
494fffe7 MS	259	ver = chip_id(IDCODE2);
494fffe7 MS	260
47e60cbd	261	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
5473f245 SDPP	262	if (zynqmp_devices[i].id == id) {
	263	if (zynqmp_devices[i].evexists &&
	264	!(ver & ZYNQMP_PL_STATUS_MASK))
	265	break;
	266	if (zynqmp_devices[i].ver == (ver &
	267	ZYNQMP_CSU_VERSION_MASK))
	268	break;
83bf2ff0	269	}
47e60cbd	270	}
83bf2ff0 SDPP	271
	272	if (i >= ARRAY_SIZE(zynqmp_devices))
	273	return "unknown";
	274
5473f245 SDPP	275	strncat(name, "zu", 2);
	276	if (!zynqmp_devices[i].evexists \|\|
	277	(ver & ZYNQMP_PL_STATUS_MASK)) {
	278	strncat(name, zynqmp_devices[i].name,
	279	ZYNQMP_VERSION_SIZE - 3);
83bf2ff0	280	return name;
5473f245	281	}
83bf2ff0	282
5473f245 SDPP	283	/*
	284	* Here we are means, PL not powered up and ev variant
	285	* exists. So, we need to ignore VCU disable bit(8) in
	286	* version and findout if its CG or EG/EV variant.
	287	*/
	288	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
	289	if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
	290	(ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
	291	strncat(name, zynqmp_devices[i].name,
	292	ZYNQMP_VERSION_SIZE - 3);
	293	break;
	294	}
	295	}
	296
	297	if (j >= MAX_VARIANTS_EV)
	298	return "unknown";
83bf2ff0 SDPP	299
	300	if (strstr(name, "eg") \|\| strstr(name, "ev")) {
	301	buf = strstr(name, "e");
	302	*buf = '\0';
	303	}
	304
	305	return name;
47e60cbd MS	306	}
	307	#endif
	308
fb4000e8 MS	309	int board_early_init_f(void)
fb4000e8 MS	310	{
f32e79f1	311	int ret = 0;
fb4000e8	312	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
b94a8271 SDPP	313	u32 pm_api_version;
	314
	315	pm_api_version = zynqmp_pmufw_version();
	316	printf("PMUFW:\tv%d.%d\n",
	317	pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
	318	pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
	319
	320	if (pm_api_version < ZYNQMP_PM_VERSION)
	321	panic("PMUFW version error. Expected: v%d.%d\n",
	322	ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
fb4000e8	323	#endif
55de0929	324
88f05a92	325	#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
f32e79f1	326	ret = psu_init();
55de0929 MS	327	#endif
55de0929 MS	328
f32e79f1	329	return ret;
fb4000e8 MS	330	}
fb4000e8 MS	331
84c7204b MS	332	int board_init(void)
84c7204b MS	333	{
a0736efb MS	334	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	335
47e60cbd MS	336	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	337	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	338	defined(CONFIG_SPL_BUILD))
	339	if (current_el() != 3) {
83bf2ff0	340	zynqmppl.name = zynqmp_get_silicon_idcode_name();
47e60cbd MS	341	printf("Chip ID:\t%s\n", zynqmppl.name);
	342	fpga_init();
	343	fpga_add(fpga_xilinx, &zynqmppl);
	344	}
	345	#endif
	346
4490e013	347	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
1fbca0db MS	348	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
	349	debug("Watchdog: Not found by seq!\n");
	350	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
	351	puts("Watchdog: Not found!\n");
	352	return 0;
	353	}
4490e013	354	}
1fbca0db MS	355
	356	wdt_start(watchdog_dev, 0, 0);
	357	puts("Watchdog: Started\n");
4490e013 MS	358	#endif
4490e013 MS	359
84c7204b MS	360	return 0;
	361	}
	362
4490e013 MS	363	#ifdef CONFIG_WATCHDOG
	364	/* Called by macro WATCHDOG_RESET */
	365	void watchdog_reset(void)
	366	{
	367	# if !defined(CONFIG_SPL_BUILD)
	368	static ulong next_reset;
	369	ulong now;
	370
	371	if (!watchdog_dev)
	372	return;
	373
	374	now = timer_get_us();
	375
	376	/* Do not reset the watchdog too often */
	377	if (now > next_reset) {
	378	wdt_reset(watchdog_dev);
	379	next_reset = now + 1000;
	380	}
	381	# endif
	382	}
	383	#endif
	384
84c7204b MS	385	int board_early_init_r(void)
	386	{
	387	u32 val;
	388
ec60a279 SDPP	389	if (current_el() != 3)
	390	return 0;
	391
90a35db4 MS	392	val = readl(&crlapb_base->timestamp_ref_ctrl);
	393	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	394
ec60a279	395	if (!val) {
0785dfd8 MS	396	val = readl(&crlapb_base->timestamp_ref_ctrl);
	397	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	398	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	399
0785dfd8 MS	400	/* Program freq register in System counter */
	401	writel(zynqmp_get_system_timer_freq(),
	402	&iou_scntr_secure->base_frequency_id_register);
	403	/* And enable system counter */
	404	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	405	&iou_scntr_secure->counter_control_register);
	406	}
84c7204b MS	407	return 0;
	408	}
	409
51916864 NJ	410	unsigned long do_go_exec(ulong (entry)(int, char const []), int argc,
	411	char * const argv[])
	412	{
	413	int ret = 0;
	414
	415	if (current_el() > 1) {
	416	smp_kick_all_cpus();
	417	dcache_disable();
	418	armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
	419	ES_TO_AARCH64);
	420	} else {
	421	printf("FAIL: current EL is not above EL1\n");
	422	ret = EINVAL;
	423	}
	424	return ret;
	425	}
	426
8d59d7f6	427	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	428	int dram_init_banksize(void)
361a8799	429	{
0678941a NJ	430	int ret;
	431
	432	ret = fdtdec_setup_memory_banksize();
	433	if (ret)
	434	return ret;
	435
	436	mem_map_fill();
	437
	438	return 0;
8a5db0ab	439	}
8d59d7f6	440
361a8799	441	int dram_init(void)
8a5db0ab	442	{
12308b12	443	if (fdtdec_setup_mem_size_base() != 0)
950f86ca	444	return -EINVAL;
8a5db0ab	445
361a8799	446	return 0;
8d59d7f6 MS	447	}
8d59d7f6 MS	448	#else
0678941a NJ	449	int dram_init_banksize(void)
	450	{
	451	#if defined(CONFIG_NR_DRAM_BANKS)
	452	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	453	gd->bd->bi_dram[0].size = get_effective_memsize();
	454	#endif
	455
	456	mem_map_fill();
	457
	458	return 0;
	459	}
	460
84c7204b MS	461	int dram_init(void)
84c7204b MS	462	{
61dc92a2 MS	463	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
61dc92a2 MS	464	CONFIG_SYS_SDRAM_SIZE);
84c7204b MS	465
	466	return 0;
	467	}
8d59d7f6	468	#endif
84c7204b	469
84c7204b MS	470	void reset_cpu(ulong addr)
	471	{
	472	}
	473
0bf3f9cb	474	#if defined(CONFIG_BOARD_LATE_INIT)
d348beaa MS	475	static const struct {
	476	u32 bit;
	477	const char *name;
	478	} reset_reasons[] = {
	479	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
	480	{ RESET_REASON_SOFT, "SOFT" },
	481	{ RESET_REASON_SRST, "SRST" },
	482	{ RESET_REASON_PSONLY, "PS-ONLY" },
	483	{ RESET_REASON_PMU, "PMU" },
	484	{ RESET_REASON_INTERNAL, "INTERNAL" },
	485	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
	486	{}
	487	};
	488
be52372f	489	static int reset_reason(void)
d348beaa	490	{
be52372f KR	491	u32 reg;
be52372f KR	492	int i, ret;
d348beaa MS	493	const char *reason = NULL;
d348beaa MS	494
be52372f KR	495	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
	496	if (ret)
	497	return -EINVAL;
d348beaa MS	498
	499	puts("Reset reason:\t");
	500
	501	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
be52372f	502	if (reg & reset_reasons[i].bit) {
d348beaa MS	503	reason = reset_reasons[i].name;
	504	printf("%s ", reset_reasons[i].name);
	505	break;
	506	}
	507	}
	508
	509	puts("\n");
	510
	511	env_set("reset_reason", reason);
	512
be52372f KR	513	ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
	514	if (ret)
	515	return -EINVAL;
d348beaa MS	516
	517	return ret;
	518	}
	519
91d7e0c4 MS	520	static int set_fdtfile(void)
	521	{
	522	char compatible, fdtfile;
	523	const char *suffix = ".dtb";
	524	const char *vendor = "xilinx/";
	525
	526	if (env_get("fdtfile"))
	527	return 0;
	528
	529	compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
	530	if (compatible) {
	531	debug("Compatible: %s\n", compatible);
	532
	533	/* Discard vendor prefix */
	534	strsep(&compatible, ",");
	535
	536	fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
	537	strlen(suffix) + 1);
	538	if (!fdtfile)
	539	return -ENOMEM;
	540
	541	sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
	542
	543	env_set("fdtfile", fdtfile);
	544	free(fdtfile);
	545	}
	546
	547	return 0;
	548	}
	549
84c7204b MS	550	int board_late_init(void)
	551	{
	552	u32 reg = 0;
	553	u8 bootmode;
2882b39d MS	554	struct udevice *dev;
	555	int bootseq = -1;
	556	int bootseq_len = 0;
0478b0b9	557	int env_targets_len = 0;
b72894f1 MS	558	const char *mode;
b72894f1 MS	559	char *new_targets;
01c42d3d	560	char *env_targets;
d1db89f4	561	int ret;
b72894f1	562
e615f39e MS	563	#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
	564	usb_ether_init();
	565	#endif
	566
b72894f1 MS	567	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	568	debug("Saved variables - Skipping\n");
	569	return 0;
	570	}
84c7204b	571
91d7e0c4 MS	572	ret = set_fdtfile();
	573	if (ret)
	574	return ret;
	575
d1db89f4 SDPP	576	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	577	if (ret)
	578	return -EINVAL;
	579
47359a03 MS	580	if (reg >> BOOT_MODE_ALT_SHIFT)
	581	reg >>= BOOT_MODE_ALT_SHIFT;
	582
84c7204b MS	583	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	584
fb90917c	585	puts("Bootmode: ");
84c7204b	586	switch (bootmode) {
d58fc12e MS	587	case USB_MODE:
	588	puts("USB_MODE\n");
	589	mode = "usb";
07656ba5	590	env_set("modeboot", "usb_dfu_spl");
d58fc12e	591	break;
0a5bcc8c	592	case JTAG_MODE:
fb90917c	593	puts("JTAG_MODE\n");
b72894f1	594	mode = "pxe dhcp";
07656ba5	595	env_set("modeboot", "jtagboot");
0a5bcc8c SDPP	596	break;
	597	case QSPI_MODE_24BIT:
	598	case QSPI_MODE_32BIT:
b72894f1	599	mode = "qspi0";
fb90917c	600	puts("QSPI_MODE\n");
07656ba5	601	env_set("modeboot", "qspiboot");
0a5bcc8c	602	break;
39c56f55	603	case EMMC_MODE:
78678fee	604	puts("EMMC_MODE\n");
b72894f1	605	mode = "mmc0";
07656ba5	606	env_set("modeboot", "emmcboot");
78678fee MS	607	break;
78678fee MS	608	case SD_MODE:
fb90917c	609	puts("SD_MODE\n");
2882b39d	610	if (uclass_get_device_by_name(UCLASS_MMC,
e7c9de66 SDPP	611	"mmc@ff160000", &dev) &&
e7c9de66 SDPP	612	uclass_get_device_by_name(UCLASS_MMC,
2882b39d MS	613	"sdhci@ff160000", &dev)) {
	614	puts("Boot from SD0 but without SD0 enabled!\n");
	615	return -1;
	616	}
	617	debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
	618
	619	mode = "mmc";
	620	bootseq = dev->seq;
07656ba5	621	env_set("modeboot", "sdboot");
84c7204b	622	break;
e1992276 SDPP	623	case SD1_LSHFT_MODE:
	624	puts("LVL_SHFT_");
	625	/* fall through */
af813acd	626	case SD_MODE1:
fb90917c	627	puts("SD_MODE1\n");
2882b39d	628	if (uclass_get_device_by_name(UCLASS_MMC,
e7c9de66 SDPP	629	"mmc@ff170000", &dev) &&
e7c9de66 SDPP	630	uclass_get_device_by_name(UCLASS_MMC,
2882b39d MS	631	"sdhci@ff170000", &dev)) {
	632	puts("Boot from SD1 but without SD1 enabled!\n");
	633	return -1;
	634	}
	635	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	636
	637	mode = "mmc";
	638	bootseq = dev->seq;
07656ba5	639	env_set("modeboot", "sdboot");
af813acd MS	640	break;
af813acd MS	641	case NAND_MODE:
fb90917c	642	puts("NAND_MODE\n");
b72894f1	643	mode = "nand0";
07656ba5	644	env_set("modeboot", "nandboot");
af813acd	645	break;
84c7204b	646	default:
b72894f1	647	mode = "";
84c7204b MS	648	printf("Invalid Boot Mode:0x%x\n", bootmode);
	649	break;
	650	}
	651
2882b39d MS	652	if (bootseq >= 0) {
	653	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	654	debug("Bootseq len: %x\n", bootseq_len);
	655	}
	656
b72894f1 MS	657	/*
	658	* One terminating char + one byte for space between mode
	659	* and default boot_targets
	660	*/
01c42d3d	661	env_targets = env_get("boot_targets");
0478b0b9 MS	662	if (env_targets)
	663	env_targets_len = strlen(env_targets);
	664
2882b39d MS	665	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
2882b39d MS	666	bootseq_len);
1e3e68f1 MS	667	if (!new_targets)
1e3e68f1 MS	668	return -ENOMEM;
0478b0b9	669
2882b39d MS	670	if (bootseq >= 0)
	671	sprintf(new_targets, "%s%x %s", mode, bootseq,
	672	env_targets ? env_targets : "");
	673	else
	674	sprintf(new_targets, "%s %s", mode,
	675	env_targets ? env_targets : "");
b72894f1	676
382bee57	677	env_set("boot_targets", new_targets);
b72894f1	678
d348beaa MS	679	reset_reason();
d348beaa MS	680
84c7204b MS	681	return 0;
84c7204b MS	682	}
0bf3f9cb	683	#endif
84696ff5 SDPP	684
	685	int checkboard(void)
	686	{
5af08556	687	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	688	return 0;
84696ff5 SDPP	689	}