drivers/clk/at91/compat.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Compatible code for non CCF AT91 platforms.
   4  *
   5  * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
   8  */
   9 #include <common.h>
  10 #include <clk-uclass.h>
  11 #include <dm.h>
  12 #include <asm/global_data.h>
  13 #include <dm/device_compat.h>
  14 #include <dm/lists.h>
  15 #include <dm/util.h>
  16 #include <mach/at91_pmc.h>
  17 #include <mach/at91_sfr.h>
  18 #include <regmap.h>
  19 #include <syscon.h>
  20
  21 #include "pmc.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 struct pmc_plat {
  26         struct at91_pmc *reg_base;
  27         struct regmap *regmap_sfr;
  28 };
  29
  30 static const struct udevice_id at91_pmc_match[] = {
  31         { .compatible = "atmel,at91rm9200-pmc" },
  32         { .compatible = "atmel,at91sam9260-pmc" },
  33         { .compatible = "atmel,at91sam9g45-pmc" },
  34         { .compatible = "atmel,at91sam9n12-pmc" },
  35         { .compatible = "atmel,at91sam9x5-pmc" },
  36         { .compatible = "atmel,sama5d3-pmc" },
  37         { .compatible = "atmel,sama5d2-pmc" },
  38         {}
  39 };
  40
  41 U_BOOT_DRIVER(at91_pmc) = {
  42         .name = "at91-pmc",
  43         .id = UCLASS_SIMPLE_BUS,
  44         .of_match = at91_pmc_match,
  45 };
  46
  47 static int at91_pmc_core_probe(struct udevice *dev)
  48 {
  49         struct pmc_plat *plat = dev_get_plat(dev);
  50
  51         dev = dev_get_parent(dev);
  52
  53         plat->reg_base = dev_read_addr_ptr(dev);
  54
  55         return 0;
  56 }
  57
  58 /**
  59  * at91_clk_sub_device_bind() - for the at91 clock driver
  60  * Recursively bind its children as clk devices.
  61  *
  62  * @return: 0 on success, or negative error code on failure
  63  */
  64 int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  65 {
  66         const void *fdt = gd->fdt_blob;
  67         int offset = dev_of_offset(dev);
  68         bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  69         const char *name;
  70         int ret;
  71
  72         for (offset = fdt_first_subnode(fdt, offset);
  73              offset > 0;
  74              offset = fdt_next_subnode(fdt, offset)) {
  75                 if (pre_reloc_only &&
  76                     !ofnode_pre_reloc(offset_to_ofnode(offset)))
  77                         continue;
  78                 /*
  79                  * If this node has "compatible" property, this is not
  80                  * a clock sub-node, but a normal device. skip.
  81                  */
  82                 fdt_get_property(fdt, offset, "compatible", &ret);
  83                 if (ret >= 0)
  84                         continue;
  85
  86                 if (ret != -FDT_ERR_NOTFOUND)
  87                         return ret;
  88
  89                 name = fdt_get_name(fdt, offset, NULL);
  90                 if (!name)
  91                         return -EINVAL;
  92                 ret = device_bind_driver_to_node(dev, drv_name, name,
  93                                         offset_to_ofnode(offset), NULL);
  94                 if (ret)
  95                         return ret;
  96         }
  97
  98         return 0;
  99 }
 100
 101 int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 102 {
 103         int periph;
 104
 105         if (args->args_count) {
 106                 debug("Invalid args_count: %d\n", args->args_count);
 107                 return -EINVAL;
 108         }
 109
 110         periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
 111                                  -1);
 112         if (periph < 0)
 113                 return -EINVAL;
 114
 115         clk->id = periph;
 116
 117         return 0;
 118 }
 119
 120 int at91_clk_probe(struct udevice *dev)
 121 {
 122         struct udevice *dev_periph_container, *dev_pmc;
 123         struct pmc_plat *plat = dev_get_plat(dev);
 124
 125         dev_periph_container = dev_get_parent(dev);
 126         dev_pmc = dev_get_parent(dev_periph_container);
 127
 128         plat->reg_base = dev_read_addr_ptr(dev_pmc);
 129
 130         return 0;
 131 }
 132
 133 /* SCKC specific code. */
 134 static const struct udevice_id at91_sckc_match[] = {
 135         { .compatible = "atmel,at91sam9x5-sckc" },
 136         {}
 137 };
 138
 139 U_BOOT_DRIVER(at91_sckc) = {
 140         .name = "at91-sckc",
 141         .id = UCLASS_SIMPLE_BUS,
 142         .of_match = at91_sckc_match,
 143 };
 144
 145 /* Slow clock specific code. */
 146 static int at91_slow_clk_enable(struct clk *clk)
 147 {
 148         return 0;
 149 }
 150
 151 static ulong at91_slow_clk_get_rate(struct clk *clk)
 152 {
 153         return CFG_SYS_AT91_SLOW_CLOCK;
 154 }
 155
 156 static struct clk_ops at91_slow_clk_ops = {
 157         .enable = at91_slow_clk_enable,
 158         .get_rate = at91_slow_clk_get_rate,
 159 };
 160
 161 static const struct udevice_id at91_slow_clk_match[] = {
 162         { .compatible = "atmel,at91sam9x5-clk-slow" },
 163         {}
 164 };
 165
 166 U_BOOT_DRIVER(at91_slow_clk) = {
 167         .name = "at91-slow-clk",
 168         .id = UCLASS_CLK,
 169         .of_match = at91_slow_clk_match,
 170         .ops = &at91_slow_clk_ops,
 171 };
 172
 173 /* Master clock specific code. */
 174 static ulong at91_master_clk_get_rate(struct clk *clk)
 175 {
 176         return gd->arch.mck_rate_hz;
 177 }
 178
 179 static struct clk_ops at91_master_clk_ops = {
 180         .get_rate = at91_master_clk_get_rate,
 181 };
 182
 183 static const struct udevice_id at91_master_clk_match[] = {
 184         { .compatible = "atmel,at91rm9200-clk-master" },
 185         { .compatible = "atmel,at91sam9x5-clk-master" },
 186         {}
 187 };
 188
 189 U_BOOT_DRIVER(at91_master_clk) = {
 190         .name = "at91-master-clk",
 191         .id = UCLASS_CLK,
 192         .of_match = at91_master_clk_match,
 193         .ops = &at91_master_clk_ops,
 194 };
 195
 196 /* Main osc clock specific code. */
 197 static int main_osc_clk_enable(struct clk *clk)
 198 {
 199         struct pmc_plat *plat = dev_get_plat(clk->dev);
 200         struct at91_pmc *pmc = plat->reg_base;
 201
 202         if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
 203                 return 0;
 204
 205         return -EINVAL;
 206 }
 207
 208 static ulong main_osc_clk_get_rate(struct clk *clk)
 209 {
 210         return gd->arch.main_clk_rate_hz;
 211 }
 212
 213 static struct clk_ops main_osc_clk_ops = {
 214         .enable = main_osc_clk_enable,
 215         .get_rate = main_osc_clk_get_rate,
 216 };
 217
 218 static int main_osc_clk_probe(struct udevice *dev)
 219 {
 220         return at91_pmc_core_probe(dev);
 221 }
 222
 223 static const struct udevice_id main_osc_clk_match[] = {
 224         { .compatible = "atmel,at91sam9x5-clk-main" },
 225         {}
 226 };
 227
 228 U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
 229         .name = "at91sam9x5-main-osc-clk",
 230         .id = UCLASS_CLK,
 231         .of_match = main_osc_clk_match,
 232         .probe = main_osc_clk_probe,
 233         .plat_auto      = sizeof(struct pmc_plat),
 234         .ops = &main_osc_clk_ops,
 235 };
 236
 237 /* PLLA clock specific code. */
 238 static int plla_clk_enable(struct clk *clk)
 239 {
 240         struct pmc_plat *plat = dev_get_plat(clk->dev);
 241         struct at91_pmc *pmc = plat->reg_base;
 242
 243         if (readl(&pmc->sr) & AT91_PMC_LOCKA)
 244                 return 0;
 245
 246         return -EINVAL;
 247 }
 248
 249 static ulong plla_clk_get_rate(struct clk *clk)
 250 {
 251         return gd->arch.plla_rate_hz;
 252 }
 253
 254 static struct clk_ops plla_clk_ops = {
 255         .enable = plla_clk_enable,
 256         .get_rate = plla_clk_get_rate,
 257 };
 258
 259 static int plla_clk_probe(struct udevice *dev)
 260 {
 261         return at91_pmc_core_probe(dev);
 262 }
 263
 264 static const struct udevice_id plla_clk_match[] = {
 265         { .compatible = "atmel,sama5d3-clk-pll" },
 266         {}
 267 };
 268
 269 U_BOOT_DRIVER(at91_plla_clk) = {
 270         .name = "at91-plla-clk",
 271         .id = UCLASS_CLK,
 272         .of_match = plla_clk_match,
 273         .probe = plla_clk_probe,
 274         .plat_auto      = sizeof(struct pmc_plat),
 275         .ops = &plla_clk_ops,
 276 };
 277
 278 /* PLLA DIV clock specific code. */
 279 static int at91_plladiv_clk_enable(struct clk *clk)
 280 {
 281         return 0;
 282 }
 283
 284 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
 285 {
 286         struct pmc_plat *plat = dev_get_plat(clk->dev);
 287         struct at91_pmc *pmc = plat->reg_base;
 288         struct clk source;
 289         ulong clk_rate;
 290         int ret;
 291
 292         ret = clk_get_by_index(clk->dev, 0, &source);
 293         if (ret)
 294                 return -EINVAL;
 295
 296         clk_rate = clk_get_rate(&source);
 297         if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
 298                 clk_rate /= 2;
 299
 300         return clk_rate;
 301 }
 302
 303 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
 304 {
 305         struct pmc_plat *plat = dev_get_plat(clk->dev);
 306         struct at91_pmc *pmc = plat->reg_base;
 307         struct clk source;
 308         ulong parent_rate;
 309         int ret;
 310
 311         ret = clk_get_by_index(clk->dev, 0, &source);
 312         if (ret)
 313                 return -EINVAL;
 314
 315         parent_rate = clk_get_rate(&source);
 316         if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
 317                 return -EINVAL;
 318
 319         if (parent_rate != rate) {
 320                 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
 321                        &pmc->mckr);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static struct clk_ops at91_plladiv_clk_ops = {
 328         .enable = at91_plladiv_clk_enable,
 329         .get_rate = at91_plladiv_clk_get_rate,
 330         .set_rate = at91_plladiv_clk_set_rate,
 331 };
 332
 333 static int at91_plladiv_clk_probe(struct udevice *dev)
 334 {
 335         return at91_pmc_core_probe(dev);
 336 }
 337
 338 static const struct udevice_id at91_plladiv_clk_match[] = {
 339         { .compatible = "atmel,at91sam9x5-clk-plldiv" },
 340         {}
 341 };
 342
 343 U_BOOT_DRIVER(at91_plladiv_clk) = {
 344         .name = "at91-plladiv-clk",
 345         .id = UCLASS_CLK,
 346         .of_match = at91_plladiv_clk_match,
 347         .probe = at91_plladiv_clk_probe,
 348         .plat_auto      = sizeof(struct pmc_plat),
 349         .ops = &at91_plladiv_clk_ops,
 350 };
 351
 352 /* System clock specific code. */
 353 #define SYSTEM_MAX_ID           31
 354
 355 /**
 356  * at91_system_clk_bind() - for the system clock driver
 357  * Recursively bind its children as clk devices.
 358  *
 359  * @return: 0 on success, or negative error code on failure
 360  */
 361 static int at91_system_clk_bind(struct udevice *dev)
 362 {
 363         return at91_clk_sub_device_bind(dev, "system-clk");
 364 }
 365
 366 static const struct udevice_id at91_system_clk_match[] = {
 367         { .compatible = "atmel,at91rm9200-clk-system" },
 368         {}
 369 };
 370
 371 U_BOOT_DRIVER(at91_system_clk) = {
 372         .name = "at91-system-clk",
 373         .id = UCLASS_MISC,
 374         .of_match = at91_system_clk_match,
 375         .bind = at91_system_clk_bind,
 376 };
 377
 378 static inline int is_pck(int id)
 379 {
 380         return (id >= 8) && (id <= 15);
 381 }
 382
 383 static ulong system_clk_get_rate(struct clk *clk)
 384 {
 385         struct clk clk_dev;
 386         int ret;
 387
 388         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
 389         if (ret)
 390                 return -EINVAL;
 391
 392         return clk_get_rate(&clk_dev);
 393 }
 394
 395 static ulong system_clk_set_rate(struct clk *clk, ulong rate)
 396 {
 397         struct clk clk_dev;
 398         int ret;
 399
 400         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
 401         if (ret)
 402                 return -EINVAL;
 403
 404         return clk_set_rate(&clk_dev, rate);
 405 }
 406
 407 static int system_clk_enable(struct clk *clk)
 408 {
 409         struct pmc_plat *plat = dev_get_plat(clk->dev);
 410         struct at91_pmc *pmc = plat->reg_base;
 411         u32 mask;
 412
 413         if (clk->id > SYSTEM_MAX_ID)
 414                 return -EINVAL;
 415
 416         mask = BIT(clk->id);
 417
 418         writel(mask, &pmc->scer);
 419
 420         /**
 421          * For the programmable clocks the Ready status in the PMC
 422          * status register should be checked after enabling.
 423          * For other clocks this is unnecessary.
 424          */
 425         if (!is_pck(clk->id))
 426                 return 0;
 427
 428         while (!(readl(&pmc->sr) & mask))
 429                 ;
 430
 431         return 0;
 432 }
 433
 434 static struct clk_ops system_clk_ops = {
 435         .of_xlate = at91_clk_of_xlate,
 436         .get_rate = system_clk_get_rate,
 437         .set_rate = system_clk_set_rate,
 438         .enable = system_clk_enable,
 439 };
 440
 441 U_BOOT_DRIVER(system_clk) = {
 442         .name = "system-clk",
 443         .id = UCLASS_CLK,
 444         .probe = at91_clk_probe,
 445         .plat_auto      = sizeof(struct pmc_plat),
 446         .ops = &system_clk_ops,
 447 };
 448
 449 /* Peripheral clock specific code. */
 450 #define PERIPHERAL_ID_MIN       2
 451 #define PERIPHERAL_ID_MAX       31
 452 #define PERIPHERAL_MASK(id)     (1 << ((id) & PERIPHERAL_ID_MAX))
 453
 454 enum periph_clk_type {
 455         CLK_PERIPH_AT91RM9200 = 0,
 456         CLK_PERIPH_AT91SAM9X5,
 457 };
 458
 459 /**
 460  * sam9x5_periph_clk_bind() - for the periph clock driver
 461  * Recursively bind its children as clk devices.
 462  *
 463  * @return: 0 on success, or negative error code on failure
 464  */
 465 static int sam9x5_periph_clk_bind(struct udevice *dev)
 466 {
 467         return at91_clk_sub_device_bind(dev, "periph-clk");
 468 }
 469
 470 static const struct udevice_id sam9x5_periph_clk_match[] = {
 471         {
 472                 .compatible = "atmel,at91rm9200-clk-peripheral",
 473                 .data = CLK_PERIPH_AT91RM9200,
 474         },
 475         {
 476                 .compatible = "atmel,at91sam9x5-clk-peripheral",
 477                 .data = CLK_PERIPH_AT91SAM9X5,
 478         },
 479         {}
 480 };
 481
 482 U_BOOT_DRIVER(sam9x5_periph_clk) = {
 483         .name = "sam9x5-periph-clk",
 484         .id = UCLASS_MISC,
 485         .of_match = sam9x5_periph_clk_match,
 486         .bind = sam9x5_periph_clk_bind,
 487 };
 488
 489 static int periph_clk_enable(struct clk *clk)
 490 {
 491         struct pmc_plat *plat = dev_get_plat(clk->dev);
 492         struct at91_pmc *pmc = plat->reg_base;
 493         enum periph_clk_type clk_type;
 494         void *addr;
 495
 496         if (clk->id < PERIPHERAL_ID_MIN)
 497                 return -1;
 498
 499         clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
 500         if (clk_type == CLK_PERIPH_AT91RM9200) {
 501                 addr = &pmc->pcer;
 502                 if (clk->id > PERIPHERAL_ID_MAX)
 503                         addr = &pmc->pcer1;
 504
 505                 setbits_le32(addr, PERIPHERAL_MASK(clk->id));
 506         } else {
 507                 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 508                 setbits_le32(&pmc->pcr,
 509                              AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
 510         }
 511
 512         return 0;
 513 }
 514
 515 static ulong periph_get_rate(struct clk *clk)
 516 {
 517         struct udevice *dev;
 518         struct clk clk_dev;
 519         int ret;
 520
 521         dev = dev_get_parent(clk->dev);
 522
 523         ret = clk_get_by_index(dev, 0, &clk_dev);
 524         if (ret)
 525                 return ret;
 526
 527         return clk_get_rate(&clk_dev);
 528 }
 529
 530 static struct clk_ops periph_clk_ops = {
 531         .of_xlate = at91_clk_of_xlate,
 532         .enable = periph_clk_enable,
 533         .get_rate = periph_get_rate,
 534 };
 535
 536 U_BOOT_DRIVER(clk_periph) = {
 537         .name   = "periph-clk",
 538         .id     = UCLASS_CLK,
 539         .plat_auto      = sizeof(struct pmc_plat),
 540         .probe = at91_clk_probe,
 541         .ops    = &periph_clk_ops,
 542 };
 543
 544 /* UTMI clock specific code. */
 545 #ifdef CONFIG_AT91_UTMI
 546
 547 /*
 548  * The purpose of this clock is to generate a 480 MHz signal. A different
 549  * rate can't be configured.
 550  */
 551 #define UTMI_RATE       480000000
 552
 553 static int utmi_clk_enable(struct clk *clk)
 554 {
 555         struct pmc_plat *plat = dev_get_plat(clk->dev);
 556         struct at91_pmc *pmc = plat->reg_base;
 557         struct clk clk_dev;
 558         ulong clk_rate;
 559         u32 utmi_ref_clk_freq;
 560         u32 tmp;
 561         int err;
 562         int timeout = 2000000;
 563
 564         if (readl(&pmc->sr) & AT91_PMC_LOCKU)
 565                 return 0;
 566
 567         /*
 568          * If mainck rate is different from 12 MHz, we have to configure the
 569          * FREQ field of the SFR_UTMICKTRIM register to generate properly
 570          * the utmi clock.
 571          */
 572         err = clk_get_by_index(clk->dev, 0, &clk_dev);
 573         if (err)
 574                 return -EINVAL;
 575
 576         clk_rate = clk_get_rate(&clk_dev);
 577         switch (clk_rate) {
 578         case 12000000:
 579                 utmi_ref_clk_freq = 0;
 580                 break;
 581         case 16000000:
 582                 utmi_ref_clk_freq = 1;
 583                 break;
 584         case 24000000:
 585                 utmi_ref_clk_freq = 2;
 586                 break;
 587         /*
 588          * Not supported on SAMA5D2 but it's not an issue since MAINCK
 589          * maximum value is 24 MHz.
 590          */
 591         case 48000000:
 592                 utmi_ref_clk_freq = 3;
 593                 break;
 594         default:
 595                 printf("UTMICK: unsupported mainck rate\n");
 596                 return -EINVAL;
 597         }
 598
 599         if (plat->regmap_sfr) {
 600                 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
 601                 if (err)
 602                         return -EINVAL;
 603
 604                 tmp &= ~AT91_UTMICKTRIM_FREQ;
 605                 tmp |= utmi_ref_clk_freq;
 606                 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
 607                 if (err)
 608                         return -EINVAL;
 609         } else if (utmi_ref_clk_freq) {
 610                 printf("UTMICK: sfr node required\n");
 611                 return -EINVAL;
 612         }
 613
 614         tmp = readl(&pmc->uckr);
 615         tmp |= AT91_PMC_UPLLEN |
 616                AT91_PMC_UPLLCOUNT |
 617                AT91_PMC_BIASEN;
 618         writel(tmp, &pmc->uckr);
 619
 620         while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
 621                 ;
 622         if (!timeout) {
 623                 printf("UTMICK: timeout waiting for UPLL lock\n");
 624                 return -ETIMEDOUT;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static ulong utmi_clk_get_rate(struct clk *clk)
 631 {
 632         /* UTMI clk rate is fixed. */
 633         return UTMI_RATE;
 634 }
 635
 636 static struct clk_ops utmi_clk_ops = {
 637         .enable = utmi_clk_enable,
 638         .get_rate = utmi_clk_get_rate,
 639 };
 640
 641 static int utmi_clk_of_to_plat(struct udevice *dev)
 642 {
 643         struct pmc_plat *plat = dev_get_plat(dev);
 644         struct udevice *syscon;
 645
 646         uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 647                                      "regmap-sfr", &syscon);
 648
 649         if (syscon)
 650                 plat->regmap_sfr = syscon_get_regmap(syscon);
 651
 652         return 0;
 653 }
 654
 655 static int utmi_clk_probe(struct udevice *dev)
 656 {
 657         return at91_pmc_core_probe(dev);
 658 }
 659
 660 static const struct udevice_id utmi_clk_match[] = {
 661         { .compatible = "atmel,at91sam9x5-clk-utmi" },
 662         {}
 663 };
 664
 665 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
 666         .name = "at91sam9x5-utmi-clk",
 667         .id = UCLASS_CLK,
 668         .of_match = utmi_clk_match,
 669         .probe = utmi_clk_probe,
 670         .of_to_plat = utmi_clk_of_to_plat,
 671         .plat_auto      = sizeof(struct pmc_plat),
 672         .ops = &utmi_clk_ops,
 673 };
 674
 675 #endif /* CONFIG_AT91_UTMI */
 676
 677 /* H32MX clock specific code. */
 678 #ifdef CONFIG_AT91_H32MX
 679
 680 #define H32MX_MAX_FREQ  90000000
 681
 682 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
 683 {
 684         struct pmc_plat *plat = dev_get_plat(clk->dev);
 685         struct at91_pmc *pmc = plat->reg_base;
 686         ulong rate = gd->arch.mck_rate_hz;
 687
 688         if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
 689                 rate /= 2;
 690
 691         if (rate > H32MX_MAX_FREQ)
 692                 dev_dbg(clk->dev, "H32MX clock is too fast\n");
 693
 694         return rate;
 695 }
 696
 697 static struct clk_ops sama5d4_h32mx_clk_ops = {
 698         .get_rate = sama5d4_h32mx_clk_get_rate,
 699 };
 700
 701 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
 702 {
 703         return at91_pmc_core_probe(dev);
 704 }
 705
 706 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
 707         { .compatible = "atmel,sama5d4-clk-h32mx" },
 708         {}
 709 };
 710
 711 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
 712         .name = "sama5d4-h32mx-clk",
 713         .id = UCLASS_CLK,
 714         .of_match = sama5d4_h32mx_clk_match,
 715         .probe = sama5d4_h32mx_clk_probe,
 716         .plat_auto      = sizeof(struct pmc_plat),
 717         .ops = &sama5d4_h32mx_clk_ops,
 718 };
 719
 720 #endif /* CONFIG_AT91_H32MX */
 721
 722 /* Generic clock specific code. */
 723 #ifdef CONFIG_AT91_GENERIC_CLK
 724
 725 #define GENERATED_SOURCE_MAX    6
 726 #define GENERATED_MAX_DIV       255
 727
 728 /**
 729  * generated_clk_bind() - for the generated clock driver
 730  * Recursively bind its children as clk devices.
 731  *
 732  * @return: 0 on success, or negative error code on failure
 733  */
 734 static int generated_clk_bind(struct udevice *dev)
 735 {
 736         return at91_clk_sub_device_bind(dev, "generic-clk");
 737 }
 738
 739 static const struct udevice_id generated_clk_match[] = {
 740         { .compatible = "atmel,sama5d2-clk-generated" },
 741         {}
 742 };
 743
 744 U_BOOT_DRIVER(generated_clk) = {
 745         .name = "generated-clk",
 746         .id = UCLASS_MISC,
 747         .of_match = generated_clk_match,
 748         .bind = generated_clk_bind,
 749 };
 750
 751 struct generic_clk_priv {
 752         u32 num_parents;
 753 };
 754
 755 static ulong generic_clk_get_rate(struct clk *clk)
 756 {
 757         struct pmc_plat *plat = dev_get_plat(clk->dev);
 758         struct at91_pmc *pmc = plat->reg_base;
 759         struct clk parent;
 760         u32 tmp, gckdiv;
 761         u8 clock_source, parent_index;
 762         int ret;
 763
 764         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 765         tmp = readl(&pmc->pcr);
 766         clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
 767                     AT91_PMC_PCR_GCKCSS_MASK;
 768         gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
 769
 770         parent_index = clock_source - 1;
 771         ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
 772         if (ret)
 773                 return 0;
 774
 775         return clk_get_rate(&parent) / (gckdiv + 1);
 776 }
 777
 778 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
 779 {
 780         struct pmc_plat *plat = dev_get_plat(clk->dev);
 781         struct at91_pmc *pmc = plat->reg_base;
 782         struct generic_clk_priv *priv = dev_get_priv(clk->dev);
 783         struct clk parent, best_parent;
 784         ulong tmp_rate, best_rate = rate, parent_rate;
 785         int tmp_diff, best_diff = -1;
 786         u32 div, best_div = 0;
 787         u8 best_parent_index, best_clock_source = 0;
 788         u8 i;
 789         u32 tmp;
 790         int ret;
 791
 792         for (i = 0; i < priv->num_parents; i++) {
 793                 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
 794                 if (ret)
 795                         return ret;
 796
 797                 parent_rate = clk_get_rate(&parent);
 798                 if (IS_ERR_VALUE(parent_rate))
 799                         return parent_rate;
 800
 801                 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
 802                         tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
 803                         tmp_diff = abs(rate - tmp_rate);
 804
 805                         if (best_diff < 0 || best_diff > tmp_diff) {
 806                                 best_rate = tmp_rate;
 807                                 best_diff = tmp_diff;
 808
 809                                 best_div = div - 1;
 810                                 best_parent = parent;
 811                                 best_parent_index = i;
 812                                 best_clock_source = best_parent_index + 1;
 813                         }
 814
 815                         if (!best_diff || tmp_rate < rate)
 816                                 break;
 817                 }
 818
 819                 if (!best_diff)
 820                         break;
 821         }
 822
 823         debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
 824               best_parent.dev->name, best_rate, best_div);
 825
 826         ret = clk_enable(&best_parent);
 827         if (ret)
 828                 return ret;
 829
 830         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 831         tmp = readl(&pmc->pcr);
 832         tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
 833         tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
 834                AT91_PMC_PCR_CMD_WRITE |
 835                AT91_PMC_PCR_GCKDIV_(best_div) |
 836                AT91_PMC_PCR_GCKEN;
 837         writel(tmp, &pmc->pcr);
 838
 839         while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
 840                 ;
 841
 842         return 0;
 843 }
 844
 845 static struct clk_ops generic_clk_ops = {
 846         .of_xlate = at91_clk_of_xlate,
 847         .get_rate = generic_clk_get_rate,
 848         .set_rate = generic_clk_set_rate,
 849 };
 850
 851 static int generic_clk_of_to_plat(struct udevice *dev)
 852 {
 853         struct generic_clk_priv *priv = dev_get_priv(dev);
 854         u32 cells[GENERATED_SOURCE_MAX];
 855         u32 num_parents;
 856
 857         num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
 858                         dev_of_offset(dev_get_parent(dev)), "clocks", cells,
 859                         GENERATED_SOURCE_MAX);
 860
 861         if (!num_parents)
 862                 return -1;
 863
 864         priv->num_parents = num_parents;
 865
 866         return 0;
 867 }
 868
 869 U_BOOT_DRIVER(generic_clk) = {
 870         .name = "generic-clk",
 871         .id = UCLASS_CLK,
 872         .probe = at91_clk_probe,
 873         .of_to_plat = generic_clk_of_to_plat,
 874         .priv_auto      = sizeof(struct generic_clk_priv),
 875         .plat_auto      = sizeof(struct pmc_plat),
 876         .ops = &generic_clk_ops,
 877 };
 878
 879 #endif /* CONFIG_AT91_GENERIC_CLK */
 880
 881 /* USB clock specific code. */
 882 #ifdef CONFIG_AT91_USB_CLK
 883
 884 #define AT91_USB_CLK_SOURCE_MAX 2
 885 #define AT91_USB_CLK_MAX_DIV    15
 886
 887 struct at91_usb_clk_priv {
 888         u32 num_clksource;
 889 };
 890
 891 static ulong at91_usb_clk_get_rate(struct clk *clk)
 892 {
 893         struct pmc_plat *plat = dev_get_plat(clk->dev);
 894         struct at91_pmc *pmc = plat->reg_base;
 895         struct clk source;
 896         u32 tmp, usbdiv;
 897         u8 source_index;
 898         int ret;
 899
 900         tmp = readl(&pmc->pcr);
 901         source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
 902                         AT91_PMC_USB_USBS_MASK;
 903         usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
 904
 905         ret = clk_get_by_index(clk->dev, source_index, &source);
 906         if (ret)
 907                 return 0;
 908
 909         return clk_get_rate(&source) / (usbdiv + 1);
 910 }
 911
 912 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
 913 {
 914         struct pmc_plat *plat = dev_get_plat(clk->dev);
 915         struct at91_pmc *pmc = plat->reg_base;
 916         struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
 917         struct clk source, best_source;
 918         ulong tmp_rate, best_rate = rate, source_rate;
 919         int tmp_diff, best_diff = -1;
 920         u32 div, best_div = 0;
 921         u8 best_source_index = 0;
 922         u8 i;
 923         u32 tmp;
 924         int ret;
 925
 926         for (i = 0; i < priv->num_clksource; i++) {
 927                 ret = clk_get_by_index(clk->dev, i, &source);
 928                 if (ret)
 929                         return ret;
 930
 931                 source_rate = clk_get_rate(&source);
 932                 if (IS_ERR_VALUE(source_rate))
 933                         return source_rate;
 934
 935                 for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
 936                         tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
 937                         tmp_diff = abs(rate - tmp_rate);
 938
 939                         if (best_diff < 0 || best_diff > tmp_diff) {
 940                                 best_rate = tmp_rate;
 941                                 best_diff = tmp_diff;
 942
 943                                 best_div = div - 1;
 944                                 best_source = source;
 945                                 best_source_index = i;
 946                         }
 947
 948                         if (!best_diff || tmp_rate < rate)
 949                                 break;
 950                 }
 951
 952                 if (!best_diff)
 953                         break;
 954         }
 955
 956         debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
 957               best_source.dev->name, best_rate, best_div);
 958
 959         ret = clk_enable(&best_source);
 960         if (ret)
 961                 return ret;
 962
 963         tmp = AT91_PMC_USB_USBS_(best_source_index) |
 964               AT91_PMC_USB_DIV_(best_div);
 965         writel(tmp, &pmc->usb);
 966
 967         return 0;
 968 }
 969
 970 static struct clk_ops at91_usb_clk_ops = {
 971         .get_rate = at91_usb_clk_get_rate,
 972         .set_rate = at91_usb_clk_set_rate,
 973 };
 974
 975 static int at91_usb_clk_of_to_plat(struct udevice *dev)
 976 {
 977         struct at91_usb_clk_priv *priv = dev_get_priv(dev);
 978         u32 cells[AT91_USB_CLK_SOURCE_MAX];
 979         u32 num_clksource;
 980
 981         num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
 982                                                    dev_of_offset(dev),
 983                                                    "clocks", cells,
 984                                                    AT91_USB_CLK_SOURCE_MAX);
 985
 986         if (!num_clksource)
 987                 return -1;
 988
 989         priv->num_clksource = num_clksource;
 990
 991         return 0;
 992 }
 993
 994 static int at91_usb_clk_probe(struct udevice *dev)
 995 {
 996         return at91_pmc_core_probe(dev);
 997 }
 998
 999 static const struct udevice_id at91_usb_clk_match[] = {
1000         { .compatible = "atmel,at91sam9x5-clk-usb" },
1001         {}
1002 };
1003
1004 U_BOOT_DRIVER(at91_usb_clk) = {
1005         .name = "at91-usb-clk",
1006         .id = UCLASS_CLK,
1007         .of_match = at91_usb_clk_match,
1008         .probe = at91_usb_clk_probe,
1009         .of_to_plat = at91_usb_clk_of_to_plat,
1010         .priv_auto      = sizeof(struct at91_usb_clk_priv),
1011         .plat_auto      = sizeof(struct pmc_plat),
1012         .ops = &at91_usb_clk_ops,
1013 };
1014
1015 #endif /* CONFIG_AT91_USB_CLK */