include/ddr_spd.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef _DDR_SPD_H_
   7 #define _DDR_SPD_H_
   8
   9 /*
  10  * Format from "JEDEC Standard No. 21-C,
  11  * Appendix D: Rev 1.0: SPD's for DDR SDRAM
  12  */
  13 typedef struct ddr1_spd_eeprom_s {
  14         unsigned char info_size;   /*  0 # bytes written into serial memory */
  15         unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
  16         unsigned char mem_type;    /*  2 Fundamental memory type */
  17         unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
  18         unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
  19         unsigned char nrows;       /*  5 Number of DIMM Banks */
  20         unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
  21         unsigned char dataw_msb;   /*  7 ... Data Width continuation */
  22         unsigned char voltage;     /*  8 Voltage intf std of this assembly */
  23         unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
  24         unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  25         unsigned char config;      /* 11 DIMM Configuration type */
  26         unsigned char refresh;     /* 12 Refresh Rate/Type */
  27         unsigned char primw;       /* 13 Primary SDRAM Width */
  28         unsigned char ecw;         /* 14 Error Checking SDRAM width */
  29         unsigned char min_delay;   /* 15 for Back to Back Random Address */
  30         unsigned char burstl;      /* 16 Burst Lengths Supported */
  31         unsigned char nbanks;      /* 17 # of Banks on SDRAM Device */
  32         unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
  33         unsigned char cs_lat;      /* 19 CS# Latency */
  34         unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
  35         unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
  36         unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
  37         unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
  38         unsigned char clk_access2; /* 24 SDRAM Access from
  39                                          Clk @ CL=X-0.5 (tAC) */
  40         unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
  41         unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
  42         unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
  43         unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
  44         unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
  45         unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
  46         unsigned char bank_dens;   /* 31 Density of each bank on module */
  47         unsigned char ca_setup;    /* 32 Addr + Cmd Setup Time Before Clk */
  48         unsigned char ca_hold;     /* 33 Addr + Cmd Hold Time After Clk */
  49         unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
  50         unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
  51         unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
  52         unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
  53         unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
  54         unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
  55         unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
  56         unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
  57         unsigned char res_46;      /* 46 Reserved */
  58         unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
  59         unsigned char res_48_61[14]; /* 48-61 Reserved */
  60         unsigned char spd_rev;     /* 62 SPD Data Revision Code */
  61         unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
  62         unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
  63         unsigned char mloc;        /* 72 Manufacturing Location */
  64         unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
  65         unsigned char rev[2];      /* 91 Revision Code */
  66         unsigned char mdate[2];    /* 93 Manufacturing Date */
  67         unsigned char sernum[4];   /* 95 Assembly Serial Number */
  68         unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
  69
  70 } ddr1_spd_eeprom_t;
  71
  72 /*
  73  * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
  74  * SPD Revision 1.2
  75  */
  76 typedef struct ddr2_spd_eeprom_s {
  77         unsigned char info_size;   /*  0 # bytes written into serial memory */
  78         unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
  79         unsigned char mem_type;    /*  2 Fundamental memory type */
  80         unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
  81         unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
  82         unsigned char mod_ranks;   /*  5 Number of DIMM Ranks */
  83         unsigned char dataw;       /*  6 Module Data Width */
  84         unsigned char res_7;       /*  7 Reserved */
  85         unsigned char voltage;     /*  8 Voltage intf std of this assembly */
  86         unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
  87         unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
  88         unsigned char config;      /* 11 DIMM Configuration type */
  89         unsigned char refresh;     /* 12 Refresh Rate/Type */
  90         unsigned char primw;       /* 13 Primary SDRAM Width */
  91         unsigned char ecw;         /* 14 Error Checking SDRAM width */
  92         unsigned char res_15;      /* 15 Reserved */
  93         unsigned char burstl;      /* 16 Burst Lengths Supported */
  94         unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
  95         unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
  96         unsigned char mech_char;   /* 19 DIMM Mechanical Characteristics */
  97         unsigned char dimm_type;   /* 20 DIMM type information */
  98         unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
  99         unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
 100         unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
 101         unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
 102         unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
 103         unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
 104         unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
 105         unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
 106         unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
 107         unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
 108         unsigned char rank_dens;   /* 31 Density of each rank on module */
 109         unsigned char ca_setup;    /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
 110         unsigned char ca_hold;     /* 33 Addr+Cmd Hold Time After Clk (tIH) */
 111         unsigned char data_setup;  /* 34 Data Input Setup Time
 112                                          Before Strobe (tDS) */
 113         unsigned char data_hold;   /* 35 Data Input Hold Time
 114                                          After Strobe (tDH) */
 115         unsigned char twr;         /* 36 Write Recovery time tWR */
 116         unsigned char twtr;        /* 37 Int write to read delay tWTR */
 117         unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
 118         unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
 119         unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
 120         unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
 121         unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
 122         unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
 123         unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
 124         unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
 125         unsigned char pll_relock;  /* 46 PLL Relock time */
 126         unsigned char t_casemax;    /* 47 Tcasemax */
 127         unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
 128                                          Top (Case) to Ambient (Psi T-A DRAM) */
 129         unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
 130                                          due to Activate-Precharge/Mode Bits
 131                                          (DT0/Mode Bits) */
 132         unsigned char dt2n_dt2q;   /* 50 DRAM Case Temperature Rise from Ambient
 133                                          due to Precharge/Quiet Standby
 134                                          (DT2N/DT2Q) */
 135         unsigned char dt2p;        /* 51 DRAM Case Temperature Rise from Ambient
 136                                          due to Precharge Power-Down (DT2P) */
 137         unsigned char dt3n;        /* 52 DRAM Case Temperature Rise from Ambient
 138                                          due to Active Standby (DT3N) */
 139         unsigned char dt3pfast;    /* 53 DRAM Case Temperature Rise from Ambient
 140                                          due to Active Power-Down with
 141                                          Fast PDN Exit (DT3Pfast) */
 142         unsigned char dt3pslow;    /* 54 DRAM Case Temperature Rise from Ambient
 143                                          due to Active Power-Down with Slow
 144                                          PDN Exit (DT3Pslow) */
 145         unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
 146                                          due to Page Open Burst Read/DT4R4W
 147                                          Mode Bit (DT4R/DT4R4W Mode Bit) */
 148         unsigned char dt5b;        /* 56 DRAM Case Temperature Rise from Ambient
 149                                          due to Burst Refresh (DT5B) */
 150         unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
 151                                          due to Bank Interleave Reads with
 152                                          Auto-Precharge (DT7) */
 153         unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
 154                                          Top (Case) to Ambient (Psi T-A PLL) */
 155         unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
 156                                          from Top (Case) to Ambient
 157                                          (Psi T-A Register) */
 158         unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
 159                                          due to PLL Active (DT PLL Active) */
 160         unsigned char dtregact;    /* 61 Register Case Temperature Rise from
 161                                          Ambient due to Register Active/Mode Bit
 162                                          (DT Register Active/Mode Bit) */
 163         unsigned char spd_rev;     /* 62 SPD Data Revision Code */
 164         unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
 165         unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
 166         unsigned char mloc;        /* 72 Manufacturing Location */
 167         unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
 168         unsigned char rev[2];      /* 91 Revision Code */
 169         unsigned char mdate[2];    /* 93 Manufacturing Date */
 170         unsigned char sernum[4];   /* 95 Assembly Serial Number */
 171         unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
 172
 173 } ddr2_spd_eeprom_t;
 174
 175 typedef struct ddr3_spd_eeprom_s {
 176         /* General Section: Bytes 0-59 */
 177         unsigned char info_size_crc;   /*  0 # bytes written into serial memory,
 178                                              CRC coverage */
 179         unsigned char spd_rev;         /*  1 Total # bytes of SPD mem device */
 180         unsigned char mem_type;        /*  2 Key Byte / Fundamental mem type */
 181         unsigned char module_type;     /*  3 Key Byte / Module Type */
 182         unsigned char density_banks;   /*  4 SDRAM Density and Banks */
 183         unsigned char addressing;      /*  5 SDRAM Addressing */
 184         unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
 185         unsigned char organization;    /*  7 Module Organization */
 186         unsigned char bus_width;       /*  8 Module Memory Bus Width */
 187         unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
 188                                              Dividend / Divisor */
 189         unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
 190         unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
 191         unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
 192         unsigned char res_13;          /* 13 Reserved */
 193         unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
 194                                              Least Significant Byte */
 195         unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
 196                                              Most Significant Byte */
 197         unsigned char taa_min;         /* 16 Min CAS Latency Time */
 198         unsigned char twr_min;         /* 17 Min Write REcovery Time */
 199         unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
 200         unsigned char trrd_min;        /* 19 Min Row Active to
 201                                              Row Active Delay Time */
 202         unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
 203         unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
 204         unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
 205                                              Delay Time */
 206         unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
 207                                              Delay Time, LSB */
 208         unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
 209         unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
 210         unsigned char twtr_min;        /* 26 Min Internal Write to
 211                                              Read Command Delay Time */
 212         unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
 213                                              Command Delay Time */
 214         unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
 215         unsigned char tfaw_min;        /* 29 Min Four Activate Window
 216                                              Delay Time*/
 217         unsigned char opt_features;    /* 30 SDRAM Optional Features */
 218         unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
 219         unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
 220         unsigned char device_type;     /* 33 SDRAM device type */
 221         int8_t fine_tck_min;           /* 34 Fine offset for tCKmin */
 222         int8_t fine_taa_min;           /* 35 Fine offset for tAAmin */
 223         int8_t fine_trcd_min;          /* 36 Fine offset for tRCDmin */
 224         int8_t fine_trp_min;           /* 37 Fine offset for tRPmin */
 225         int8_t fine_trc_min;           /* 38 Fine offset for tRCmin */
 226         unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 227
 228         /* Module-Specific Section: Bytes 60-116 */
 229         union {
 230                 struct {
 231                         /* 60 (Unbuffered) Module Nominal Height */
 232                         unsigned char mod_height;
 233                         /* 61 (Unbuffered) Module Maximum Thickness */
 234                         unsigned char mod_thickness;
 235                         /* 62 (Unbuffered) Reference Raw Card Used */
 236                         unsigned char ref_raw_card;
 237                         /* 63 (Unbuffered) Address Mapping from
 238                               Edge Connector to DRAM */
 239                         unsigned char addr_mapping;
 240                         /* 64-116 (Unbuffered) Reserved */
 241                         unsigned char res_64_116[53];
 242                 } unbuffered;
 243                 struct {
 244                         /* 60 (Registered) Module Nominal Height */
 245                         unsigned char mod_height;
 246                         /* 61 (Registered) Module Maximum Thickness */
 247                         unsigned char mod_thickness;
 248                         /* 62 (Registered) Reference Raw Card Used */
 249                         unsigned char ref_raw_card;
 250                         /* 63 DIMM Module Attributes */
 251                         unsigned char modu_attr;
 252                         /* 64 RDIMM Thermal Heat Spreader Solution */
 253                         unsigned char thermal;
 254                         /* 65 Register Manufacturer ID Code, Least Significant Byte */
 255                         unsigned char reg_id_lo;
 256                         /* 66 Register Manufacturer ID Code, Most Significant Byte */
 257                         unsigned char reg_id_hi;
 258                         /* 67 Register Revision Number */
 259                         unsigned char reg_rev;
 260                         /* 68 Register Type */
 261                         unsigned char reg_type;
 262                         /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
 263                         unsigned char rcw[8];
 264                 } registered;
 265                 unsigned char uc[57]; /* 60-116 Module-Specific Section */
 266         } mod_section;
 267
 268         /* Unique Module ID: Bytes 117-125 */
 269         unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
 270         unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
 271         unsigned char mloc;            /* 119 Mfg Location */
 272         unsigned char mdate[2];        /* 120-121 Mfg Date */
 273         unsigned char sernum[4];       /* 122-125 Module Serial Number */
 274
 275         /* CRC: Bytes 126-127 */
 276         unsigned char crc[2];          /* 126-127 SPD CRC */
 277
 278         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
 279         unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
 280         unsigned char mrev[2];         /* 146-147 Module Revision Code */
 281
 282         unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
 283         unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
 284
 285         unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
 286         unsigned char cust[80];        /* 176-255 Open for Customer Use */
 287
 288 } ddr3_spd_eeprom_t;
 289
 290 /* From JEEC Standard No. 21-C release 23A */
 291 struct ddr4_spd_eeprom_s {
 292         /* General Section: Bytes 0-127 */
 293         uint8_t info_size_crc;          /*  0 # bytes */
 294         uint8_t spd_rev;                /*  1 Total # bytes of SPD */
 295         uint8_t mem_type;               /*  2 Key Byte / mem type */
 296         uint8_t module_type;            /*  3 Key Byte / Module Type */
 297         uint8_t density_banks;          /*  4 Density and Banks */
 298         uint8_t addressing;             /*  5 Addressing */
 299         uint8_t package_type;           /*  6 Package type */
 300         uint8_t opt_feature;            /*  7 Optional features */
 301         uint8_t thermal_ref;            /*  8 Thermal and refresh */
 302         uint8_t oth_opt_features;       /*  9 Other optional features */
 303         uint8_t res_10;                 /* 10 Reserved */
 304         uint8_t module_vdd;             /* 11 Module nominal voltage */
 305         uint8_t organization;           /* 12 Module Organization */
 306         uint8_t bus_width;              /* 13 Module Memory Bus Width */
 307         uint8_t therm_sensor;           /* 14 Module Thermal Sensor */
 308         uint8_t ext_type;               /* 15 Extended module type */
 309         uint8_t res_16;
 310         uint8_t timebases;              /* 17 MTb and FTB */
 311         uint8_t tck_min;                /* 18 tCKAVGmin */
 312         uint8_t tck_max;                /* 19 TCKAVGmax */
 313         uint8_t caslat_b1;              /* 20 CAS latencies, 1st byte */
 314         uint8_t caslat_b2;              /* 21 CAS latencies, 2nd byte */
 315         uint8_t caslat_b3;              /* 22 CAS latencies, 3rd byte */
 316         uint8_t caslat_b4;              /* 23 CAS latencies, 4th byte */
 317         uint8_t taa_min;                /* 24 Min CAS Latency Time */
 318         uint8_t trcd_min;               /* 25 Min RAS# to CAS# Delay Time */
 319         uint8_t trp_min;                /* 26 Min Row Precharge Delay Time */
 320         uint8_t tras_trc_ext;           /* 27 Upper Nibbles for tRAS and tRC */
 321         uint8_t tras_min_lsb;           /* 28 tRASmin, lsb */
 322         uint8_t trc_min_lsb;            /* 29 tRCmin, lsb */
 323         uint8_t trfc1_min_lsb;          /* 30 Min Refresh Recovery Delay Time */
 324         uint8_t trfc1_min_msb;          /* 31 Min Refresh Recovery Delay Time */
 325         uint8_t trfc2_min_lsb;          /* 32 Min Refresh Recovery Delay Time */
 326         uint8_t trfc2_min_msb;          /* 33 Min Refresh Recovery Delay Time */
 327         uint8_t trfc4_min_lsb;          /* 34 Min Refresh Recovery Delay Time */
 328         uint8_t trfc4_min_msb;          /* 35 Min Refresh Recovery Delay Time */
 329         uint8_t tfaw_msb;               /* 36 Upper Nibble for tFAW */
 330         uint8_t tfaw_min;               /* 37 tFAW, lsb */
 331         uint8_t trrds_min;              /* 38 tRRD_Smin, MTB */
 332         uint8_t trrdl_min;              /* 39 tRRD_Lmin, MTB */
 333         uint8_t tccdl_min;              /* 40 tCCS_Lmin, MTB */
 334         uint8_t res_41[60-41];          /* 41 Rserved */
 335         uint8_t mapping[78-60];         /* 60~77 Connector to SDRAM bit map */
 336         uint8_t res_78[117-78];         /* 78~116, Reserved */
 337         int8_t fine_tccdl_min;          /* 117 Fine offset for tCCD_Lmin */
 338         int8_t fine_trrdl_min;          /* 118 Fine offset for tRRD_Lmin */
 339         int8_t fine_trrds_min;          /* 119 Fine offset for tRRD_Smin */
 340         int8_t fine_trc_min;            /* 120 Fine offset for tRCmin */
 341         int8_t fine_trp_min;            /* 121 Fine offset for tRPmin */
 342         int8_t fine_trcd_min;           /* 122 Fine offset for tRCDmin */
 343         int8_t fine_taa_min;            /* 123 Fine offset for tAAmin */
 344         int8_t fine_tck_max;            /* 124 Fine offset for tCKAVGmax */
 345         int8_t fine_tck_min;            /* 125 Fine offset for tCKAVGmin */
 346         /* CRC: Bytes 126-127 */
 347         uint8_t crc[2];                 /* 126-127 SPD CRC */
 348
 349         /* Module-Specific Section: Bytes 128-255 */
 350         union {
 351                 struct {
 352                         /* 128 (Unbuffered) Module Nominal Height */
 353                         uint8_t mod_height;
 354                         /* 129 (Unbuffered) Module Maximum Thickness */
 355                         uint8_t mod_thickness;
 356                         /* 130 (Unbuffered) Reference Raw Card Used */
 357                         uint8_t ref_raw_card;
 358                         /* 131 (Unbuffered) Address Mapping from
 359                               Edge Connector to DRAM */
 360                         uint8_t addr_mapping;
 361                         /* 132~253 (Unbuffered) Reserved */
 362                         uint8_t res_132[254-132];
 363                         /* 254~255 CRC */
 364                         uint8_t crc[2];
 365                 } unbuffered;
 366                 struct {
 367                         /* 128 (Registered) Module Nominal Height */
 368                         uint8_t mod_height;
 369                         /* 129 (Registered) Module Maximum Thickness */
 370                         uint8_t mod_thickness;
 371                         /* 130 (Registered) Reference Raw Card Used */
 372                         uint8_t ref_raw_card;
 373                         /* 131 DIMM Module Attributes */
 374                         uint8_t modu_attr;
 375                         /* 132 RDIMM Thermal Heat Spreader Solution */
 376                         uint8_t thermal;
 377                         /* 133 Register Manufacturer ID Code, LSB */
 378                         uint8_t reg_id_lo;
 379                         /* 134 Register Manufacturer ID Code, MSB */
 380                         uint8_t reg_id_hi;
 381                         /* 135 Register Revision Number */
 382                         uint8_t reg_rev;
 383                         /* 136 Address mapping from register to DRAM */
 384                         u8 reg_map;
 385                         u8 ca_stren;
 386                         u8 clk_stren;
 387                         /* 139~253 Reserved */
 388                         u8 res_137[254 - 139];
 389                         /* 254~255 CRC */
 390                         uint8_t crc[2];
 391                 } registered;
 392                 struct {
 393                         /* 128 (Loadreduced) Module Nominal Height */
 394                         uint8_t mod_height;
 395                         /* 129 (Loadreduced) Module Maximum Thickness */
 396                         uint8_t mod_thickness;
 397                         /* 130 (Loadreduced) Reference Raw Card Used */
 398                         uint8_t ref_raw_card;
 399                         /* 131 DIMM Module Attributes */
 400                         uint8_t modu_attr;
 401                         /* 132 RDIMM Thermal Heat Spreader Solution */
 402                         uint8_t thermal;
 403                         /* 133 Register Manufacturer ID Code, LSB */
 404                         uint8_t reg_id_lo;
 405                         /* 134 Register Manufacturer ID Code, MSB */
 406                         uint8_t reg_id_hi;
 407                         /* 135 Register Revision Number */
 408                         uint8_t reg_rev;
 409                         /* 136 Address mapping from register to DRAM */
 410                         uint8_t reg_map;
 411                         /* 137 Register Output Drive Strength for CMD/Add*/
 412                         uint8_t reg_drv;
 413                         /* 138 Register Output Drive Strength for CK */
 414                         uint8_t reg_drv_ck;
 415                         /* 139 Data Buffer Revision Number */
 416                         uint8_t data_buf_rev;
 417                         /* 140 DRAM VrefDQ for Package Rank 0 */
 418                         uint8_t vrefqe_r0;
 419                         /* 141 DRAM VrefDQ for Package Rank 1 */
 420                         uint8_t vrefqe_r1;
 421                         /* 142 DRAM VrefDQ for Package Rank 2 */
 422                         uint8_t vrefqe_r2;
 423                         /* 143 DRAM VrefDQ for Package Rank 3 */
 424                         uint8_t vrefqe_r3;
 425                         /* 144 Data Buffer VrefDQ for DRAM Interface */
 426                         uint8_t data_intf;
 427                         /*
 428                          * 145 Data Buffer MDQ Drive Strength and RTT
 429                          * for data rate <= 1866
 430                          */
 431                         uint8_t data_drv_1866;
 432                         /*
 433                          * 146 Data Buffer MDQ Drive Strength and RTT
 434                          * for 1866 < data rate <= 2400
 435                          */
 436                         uint8_t data_drv_2400;
 437                         /*
 438                          * 147 Data Buffer MDQ Drive Strength and RTT
 439                          * for 2400 < data rate <= 3200
 440                          */
 441                         uint8_t data_drv_3200;
 442                         /* 148 DRAM Drive Strength */
 443                         uint8_t dram_drv;
 444                         /*
 445                          * 149 DRAM ODT (RTT_WR, RTT_NOM)
 446                          * for data rate <= 1866
 447                          */
 448                         uint8_t dram_odt_1866;
 449                         /*
 450                          * 150 DRAM ODT (RTT_WR, RTT_NOM)
 451                          * for 1866 < data rate <= 2400
 452                          */
 453                         uint8_t dram_odt_2400;
 454                         /*
 455                          * 151 DRAM ODT (RTT_WR, RTT_NOM)
 456                          * for 2400 < data rate <= 3200
 457                          */
 458                         uint8_t dram_odt_3200;
 459                         /*
 460                          * 152 DRAM ODT (RTT_PARK)
 461                          * for data rate <= 1866
 462                          */
 463                         uint8_t dram_odt_park_1866;
 464                         /*
 465                          * 153 DRAM ODT (RTT_PARK)
 466                          * for 1866 < data rate <= 2400
 467                          */
 468                         uint8_t dram_odt_park_2400;
 469                         /*
 470                          * 154 DRAM ODT (RTT_PARK)
 471                          * for 2400 < data rate <= 3200
 472                          */
 473                         uint8_t dram_odt_park_3200;
 474                         uint8_t res_155[254-155];       /* Reserved */
 475                         /* 254~255 CRC */
 476                         uint8_t crc[2];
 477                 } loadreduced;
 478                 uint8_t uc[128]; /* 128-255 Module-Specific Section */
 479         } mod_section;
 480
 481         uint8_t res_256[320-256];       /* 256~319 Reserved */
 482
 483         /* Module supplier's data: Byte 320~383 */
 484         uint8_t mmid_lsb;               /* 320 Module MfgID Code LSB */
 485         uint8_t mmid_msb;               /* 321 Module MfgID Code MSB */
 486         uint8_t mloc;                   /* 322 Mfg Location */
 487         uint8_t mdate[2];               /* 323~324 Mfg Date */
 488         uint8_t sernum[4];              /* 325~328 Module Serial Number */
 489         uint8_t mpart[20];              /* 329~348 Mfg's Module Part Number */
 490         uint8_t mrev;                   /* 349 Module Revision Code */
 491         uint8_t dmid_lsb;               /* 350 DRAM MfgID Code LSB */
 492         uint8_t dmid_msb;               /* 351 DRAM MfgID Code MSB */
 493         uint8_t stepping;               /* 352 DRAM stepping */
 494         uint8_t msd[29];                /* 353~381 Mfg's Specific Data */
 495         uint8_t res_382[2];             /* 382~383 Reserved */
 496
 497         uint8_t user[512-384];          /* 384~511 End User Programmable */
 498 };
 499
 500 extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
 501 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
 502 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
 503 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
 504 extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 505 unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
 506
 507 /*
 508  * Byte 2 Fundamental Memory Types.
 509  */
 510 #define SPD_MEMTYPE_FPM         (0x01)
 511 #define SPD_MEMTYPE_EDO         (0x02)
 512 #define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
 513 #define SPD_MEMTYPE_SDRAM       (0x04)
 514 #define SPD_MEMTYPE_ROM         (0x05)
 515 #define SPD_MEMTYPE_SGRAM       (0x06)
 516 #define SPD_MEMTYPE_DDR         (0x07)
 517 #define SPD_MEMTYPE_DDR2        (0x08)
 518 #define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
 519 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE   (0x0A)
 520 #define SPD_MEMTYPE_DDR3        (0x0B)
 521 #define SPD_MEMTYPE_DDR4        (0x0C)
 522
 523 /* DIMM Type for DDR2 SPD (according to v1.3) */
 524 #define DDR2_SPD_DIMMTYPE_UNDEFINED     (0x00)
 525 #define DDR2_SPD_DIMMTYPE_RDIMM         (0x01)
 526 #define DDR2_SPD_DIMMTYPE_UDIMM         (0x02)
 527 #define DDR2_SPD_DIMMTYPE_SO_DIMM       (0x04)
 528 #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM  (0x06)
 529 #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM  (0x07)
 530 #define DDR2_SPD_DIMMTYPE_MICRO_DIMM    (0x08)
 531 #define DDR2_SPD_DIMMTYPE_MINI_RDIMM    (0x10)
 532 #define DDR2_SPD_DIMMTYPE_MINI_UDIMM    (0x20)
 533
 534 /* Byte 3 Key Byte / Module Type for DDR3 SPD */
 535 #define DDR3_SPD_MODULETYPE_MASK        (0x0f)
 536 #define DDR3_SPD_MODULETYPE_RDIMM       (0x01)
 537 #define DDR3_SPD_MODULETYPE_UDIMM       (0x02)
 538 #define DDR3_SPD_MODULETYPE_SO_DIMM     (0x03)
 539 #define DDR3_SPD_MODULETYPE_MICRO_DIMM  (0x04)
 540 #define DDR3_SPD_MODULETYPE_MINI_RDIMM  (0x05)
 541 #define DDR3_SPD_MODULETYPE_MINI_UDIMM  (0x06)
 542 #define DDR3_SPD_MODULETYPE_MINI_CDIMM  (0x07)
 543 #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM        (0x08)
 544 #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM        (0x09)
 545 #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM        (0x0A)
 546 #define DDR3_SPD_MODULETYPE_LRDIMM      (0x0B)
 547 #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
 548 #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
 549
 550 /* DIMM Type for DDR4 SPD */
 551 #define DDR4_SPD_MODULETYPE_MASK        (0x0f)
 552 #define DDR4_SPD_MODULETYPE_EXT         (0x00)
 553 #define DDR4_SPD_MODULETYPE_RDIMM       (0x01)
 554 #define DDR4_SPD_MODULETYPE_UDIMM       (0x02)
 555 #define DDR4_SPD_MODULETYPE_SO_DIMM     (0x03)
 556 #define DDR4_SPD_MODULETYPE_LRDIMM      (0x04)
 557 #define DDR4_SPD_MODULETYPE_MINI_RDIMM  (0x05)
 558 #define DDR4_SPD_MODULETYPE_MINI_UDIMM  (0x06)
 559 #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM        (0x08)
 560 #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM        (0x09)
 561 #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
 562 #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
 563
 564 #endif /* _DDR_SPD_H_ */