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7eda085c | 1 | /* |
68a2ade7 KZ |
2 | * SPDX-License-Identifier: GPL-2.0-or-later |
3 | * | |
9abd5e4b KZ |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * | |
ef71b8f1 SK |
10 | * i386 CMOS starts out with 14 bytes clock data alpha has something |
11 | * similar, but with details depending on the machine type. | |
7eda085c | 12 | * |
ef71b8f1 SK |
13 | * byte 0: seconds 0-59 |
14 | * byte 2: minutes 0-59 | |
15 | * byte 4: hours 0-23 in 24hr mode, | |
16 | * 1-12 in 12hr mode, with high bit unset/set | |
17 | * if am/pm. | |
18 | * byte 6: weekday 1-7, Sunday=1 | |
19 | * byte 7: day of the month 1-31 | |
20 | * byte 8: month 1-12 | |
21 | * byte 9: year 0-99 | |
7eda085c | 22 | * |
ef71b8f1 SK |
23 | * Numbers are stored in BCD/binary if bit 2 of byte 11 is unset/set The |
24 | * clock is in 12hr/24hr mode if bit 1 of byte 11 is unset/set The clock is | |
25 | * undefined (being updated) if bit 7 of byte 10 is set. The clock is frozen | |
26 | * (to be updated) by setting bit 7 of byte 11 Bit 7 of byte 14 indicates | |
27 | * whether the CMOS clock is reliable: it is 1 if RTC power has been good | |
28 | * since this bit was last read; it is 0 when the battery is dead and system | |
29 | * power has been off. | |
30 | * | |
31 | * Avoid setting the RTC clock within 2 seconds of the day rollover that | |
32 | * starts a new month or enters daylight saving time. | |
7eda085c KZ |
33 | * |
34 | * The century situation is messy: | |
ef71b8f1 SK |
35 | * |
36 | * Usually byte 50 (0x32) gives the century (in BCD, so 19 or 20 hex), but | |
37 | * IBM PS/2 has (part of) a checksum there and uses byte 55 (0x37). | |
38 | * Sometimes byte 127 (0x7f) or Bank 1, byte 0x48 gives the century. The | |
39 | * original RTC will not access any century byte; some modern versions will. | |
40 | * If a modern RTC or BIOS increments the century byte it may go from 0x19 | |
41 | * to 0x20, but in some buggy cases 0x1a is produced. | |
7eda085c | 42 | */ |
7eda085c KZ |
43 | /* |
44 | * A struct tm has int fields | |
ef71b8f1 SK |
45 | * tm_sec 0-59, 60 or 61 only for leap seconds |
46 | * tm_min 0-59 | |
47 | * tm_hour 0-23 | |
48 | * tm_mday 1-31 | |
49 | * tm_mon 0-11 | |
50 | * tm_year number of years since 1900 | |
51 | * tm_wday 0-6, 0=Sunday | |
52 | * tm_yday 0-365 | |
53 | * tm_isdst >0: yes, 0: no, <0: unknown | |
7eda085c KZ |
54 | */ |
55 | ||
998f392a SK |
56 | #include <fcntl.h> |
57 | #include <stdio.h> | |
58 | #include <string.h> | |
59 | #include <time.h> | |
60 | #include <unistd.h> | |
61 | ||
62 | #include "c.h" | |
7eda085c | 63 | #include "nls.h" |
bd078689 | 64 | #include "pathnames.h" |
7eda085c | 65 | |
6b06669e | 66 | /* for inb, outb */ |
88bc304b CS |
67 | #ifdef HAVE_SYS_IO_H |
68 | # include <sys/io.h> | |
69 | #elif defined(HAVE_ASM_IO_H) | |
70 | # include <asm/io.h> | |
c47a6189 | 71 | #else |
88bc304b CS |
72 | # error "no sys/io.h or asm/io.h" |
73 | #endif /* HAVE_SYS_IO_H, HAVE_ASM_IO_H */ | |
7eda085c | 74 | |
c7f75390 | 75 | #include "hwclock.h" |
7eda085c KZ |
76 | |
77 | #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) | |
78 | #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) | |
79 | ||
0f32118e SK |
80 | #define IOPL_NOT_IMPLEMENTED -2 |
81 | ||
63cccae4 | 82 | /* |
c47a6189 | 83 | * POSIX uses 1900 as epoch for a struct tm, and 1970 for a time_t. |
63cccae4 | 84 | */ |
7eda085c | 85 | #define TM_EPOCH 1900 |
7eda085c | 86 | |
c47a6189 WP |
87 | static unsigned short clock_ctl_addr = 0x70; |
88 | static unsigned short clock_data_addr = 0x71; | |
7eda085c | 89 | |
7eda085c | 90 | /* |
ef71b8f1 | 91 | * Hmmh, this isn't very atomic. Maybe we should force an error instead? |
433c8bea | 92 | * |
ef71b8f1 | 93 | * TODO: optimize the access to CMOS by mlockall(MCL_CURRENT) and SCHED_FIFO |
7eda085c | 94 | */ |
51d94caa WP |
95 | static unsigned long atomic(unsigned long (*op) (unsigned long), |
96 | unsigned long arg) | |
7eda085c | 97 | { |
f252169c | 98 | return (*op) (arg); |
7eda085c KZ |
99 | } |
100 | ||
c47a6189 WP |
101 | /* |
102 | * We only want to read CMOS data, but unfortunately writing to bit 7 | |
103 | * disables (1) or enables (0) NMI; since this bit is read-only we have | |
104 | * to guess the old status. Various docs suggest that one should disable | |
105 | * NMI while reading/writing CMOS data, and enable it again afterwards. | |
106 | * This would yield the sequence | |
107 | * | |
108 | * outb (reg | 0x80, 0x70); | |
109 | * val = inb(0x71); | |
110 | * outb (0x0d, 0x70); // 0x0d: random read-only location | |
111 | * | |
112 | * Other docs state that "any write to 0x70 should be followed by an | |
113 | * action to 0x71 or the RTC will be left in an unknown state". Most | |
114 | * docs say that it doesn't matter at all what one does. | |
115 | * | |
116 | * bit 0x80: disable NMI while reading - should we? Let us follow the | |
117 | * kernel and not disable. Called only with 0 <= reg < 128 | |
118 | */ | |
7eda085c | 119 | |
f252169c | 120 | static inline unsigned long cmos_read(unsigned long reg) |
7eda085c | 121 | { |
c47a6189 WP |
122 | outb(reg, clock_ctl_addr); |
123 | return inb(clock_data_addr); | |
7eda085c KZ |
124 | } |
125 | ||
f252169c | 126 | static inline unsigned long cmos_write(unsigned long reg, unsigned long val) |
7eda085c | 127 | { |
c47a6189 WP |
128 | outb(reg, clock_ctl_addr); |
129 | outb(val, clock_data_addr); | |
ef71b8f1 | 130 | return 0; |
7eda085c KZ |
131 | } |
132 | ||
f252169c | 133 | static unsigned long cmos_set_time(unsigned long arg) |
7eda085c | 134 | { |
ef71b8f1 SK |
135 | unsigned char save_control, save_freq_select, pmbit = 0; |
136 | struct tm tm = *(struct tm *)arg; | |
7eda085c KZ |
137 | |
138 | /* | |
139 | * CMOS byte 10 (clock status register A) has 3 bitfields: | |
140 | * bit 7: 1 if data invalid, update in progress (read-only bit) | |
141 | * (this is raised 224 us before the actual update starts) | |
142 | * 6-4 select base frequency | |
143 | * 010: 32768 Hz time base (default) | |
144 | * 111: reset | |
145 | * all other combinations are manufacturer-dependent | |
146 | * (e.g.: DS1287: 010 = start oscillator, anything else = stop) | |
147 | * 3-0 rate selection bits for interrupt | |
148 | * 0000 none (may stop RTC) | |
149 | * 0001, 0010 give same frequency as 1000, 1001 | |
150 | * 0011 122 microseconds (minimum, 8192 Hz) | |
151 | * .... each increase by 1 halves the frequency, doubles the period | |
152 | * 1111 500 milliseconds (maximum, 2 Hz) | |
153 | * 0110 976.562 microseconds (default 1024 Hz) | |
154 | */ | |
f252169c WP |
155 | save_control = cmos_read(11); /* tell the clock it's being set */ |
156 | cmos_write(11, (save_control | 0x80)); | |
157 | save_freq_select = cmos_read(10); /* stop and reset prescaler */ | |
158 | cmos_write(10, (save_freq_select | 0x70)); | |
ef71b8f1 | 159 | |
ef71b8f1 SK |
160 | tm.tm_year %= 100; |
161 | tm.tm_mon += 1; | |
162 | tm.tm_wday += 1; | |
163 | ||
164 | if (!(save_control & 0x02)) { /* 12hr mode; the default is 24hr mode */ | |
165 | if (tm.tm_hour == 0) | |
166 | tm.tm_hour = 24; | |
167 | if (tm.tm_hour > 12) { | |
168 | tm.tm_hour -= 12; | |
169 | pmbit = 0x80; | |
170 | } | |
171 | } | |
172 | ||
173 | if (!(save_control & 0x04)) { /* BCD mode - the default */ | |
174 | BIN_TO_BCD(tm.tm_sec); | |
175 | BIN_TO_BCD(tm.tm_min); | |
176 | BIN_TO_BCD(tm.tm_hour); | |
177 | BIN_TO_BCD(tm.tm_wday); | |
178 | BIN_TO_BCD(tm.tm_mday); | |
179 | BIN_TO_BCD(tm.tm_mon); | |
180 | BIN_TO_BCD(tm.tm_year); | |
ef71b8f1 | 181 | } |
7eda085c | 182 | |
f252169c WP |
183 | cmos_write(0, tm.tm_sec); |
184 | cmos_write(2, tm.tm_min); | |
185 | cmos_write(4, tm.tm_hour | pmbit); | |
186 | cmos_write(6, tm.tm_wday); | |
187 | cmos_write(7, tm.tm_mday); | |
188 | cmos_write(8, tm.tm_mon); | |
189 | cmos_write(9, tm.tm_year); | |
ef71b8f1 SK |
190 | |
191 | /* | |
192 | * The kernel sources, linux/arch/i386/kernel/time.c, have the | |
193 | * following comment: | |
194 | * | |
195 | * The following flags have to be released exactly in this order, | |
196 | * otherwise the DS12887 (popular MC146818A clone with integrated | |
197 | * battery and quartz) will not reset the oscillator and will not | |
198 | * update precisely 500 ms later. You won't find this mentioned in | |
199 | * the Dallas Semiconductor data sheets, but who believes data | |
200 | * sheets anyway ... -- Markus Kuhn | |
201 | */ | |
f252169c WP |
202 | cmos_write(11, save_control); |
203 | cmos_write(10, save_freq_select); | |
ef71b8f1 | 204 | return 0; |
7eda085c KZ |
205 | } |
206 | ||
f252169c | 207 | static int hclock_read(unsigned long reg) |
ef71b8f1 | 208 | { |
51d94caa | 209 | return atomic(cmos_read, reg); |
7eda085c KZ |
210 | } |
211 | ||
f252169c | 212 | static void hclock_set_time(const struct tm *tm) |
ef71b8f1 | 213 | { |
51d94caa | 214 | atomic(cmos_set_time, (unsigned long)(tm)); |
7eda085c KZ |
215 | } |
216 | ||
f252169c | 217 | static inline int cmos_clock_busy(void) |
ef71b8f1 | 218 | { |
7eda085c | 219 | return |
ef71b8f1 | 220 | /* poll bit 7 (UIP) of Control Register A */ |
f252169c | 221 | (hclock_read(10) & 0x80); |
7eda085c KZ |
222 | } |
223 | ||
336f7c5f SK |
224 | static int synchronize_to_clock_tick_cmos(const struct hwclock_control *ctl |
225 | __attribute__((__unused__))) | |
ef71b8f1 SK |
226 | { |
227 | int i; | |
228 | ||
229 | /* | |
230 | * Wait for rise. Should be within a second, but in case something | |
231 | * weird happens, we have a limit on this loop to reduce the impact | |
232 | * of this failure. | |
233 | */ | |
f252169c | 234 | for (i = 0; !cmos_clock_busy(); i++) |
ef71b8f1 SK |
235 | if (i >= 10000000) |
236 | return 1; | |
237 | ||
238 | /* Wait for fall. Should be within 2.228 ms. */ | |
f252169c | 239 | for (i = 0; cmos_clock_busy(); i++) |
ef71b8f1 SK |
240 | if (i >= 1000000) |
241 | return 1; | |
242 | return 0; | |
7eda085c KZ |
243 | } |
244 | ||
ef71b8f1 SK |
245 | /* |
246 | * Read the hardware clock and return the current time via <tm> argument. | |
247 | * Assume we have an ISA machine and read the clock directly with CPU I/O | |
248 | * instructions. | |
249 | * | |
250 | * This function is not totally reliable. It takes a finite and | |
251 | * unpredictable amount of time to execute the code below. During that time, | |
252 | * the clock may change and we may even read an invalid value in the middle | |
253 | * of an update. We do a few checks to minimize this possibility, but only | |
254 | * the kernel can actually read the clock properly, since it can execute | |
255 | * code in a short and predictable amount of time (by turning of | |
256 | * interrupts). | |
257 | * | |
258 | * In practice, the chance of this function returning the wrong time is | |
259 | * extremely remote. | |
260 | */ | |
336f7c5f SK |
261 | static int read_hardware_clock_cmos(const struct hwclock_control *ctl |
262 | __attribute__((__unused__)), struct tm *tm) | |
ef71b8f1 | 263 | { |
bd078689 | 264 | unsigned char status = 0, pmbit = 0; |
ef71b8f1 | 265 | |
473ec359 | 266 | while (1) { |
ef71b8f1 SK |
267 | /* |
268 | * Bit 7 of Byte 10 of the Hardware Clock value is the | |
269 | * Update In Progress (UIP) bit, which is on while and 244 | |
270 | * uS before the Hardware Clock updates itself. It updates | |
271 | * the counters individually, so reading them during an | |
272 | * update would produce garbage. The update takes 2mS, so we | |
273 | * could be spinning here that long waiting for this bit to | |
274 | * turn off. | |
275 | * | |
276 | * Furthermore, it is pathologically possible for us to be | |
277 | * in this code so long that even if the UIP bit is not on | |
278 | * at first, the clock has changed while we were running. We | |
279 | * check for that too, and if it happens, we start over. | |
280 | */ | |
f252169c | 281 | if (!cmos_clock_busy()) { |
ef71b8f1 | 282 | /* No clock update in progress, go ahead and read */ |
f252169c WP |
283 | tm->tm_sec = hclock_read(0); |
284 | tm->tm_min = hclock_read(2); | |
285 | tm->tm_hour = hclock_read(4); | |
286 | tm->tm_wday = hclock_read(6); | |
287 | tm->tm_mday = hclock_read(7); | |
288 | tm->tm_mon = hclock_read(8); | |
289 | tm->tm_year = hclock_read(9); | |
290 | status = hclock_read(11); | |
ef71b8f1 SK |
291 | /* |
292 | * Unless the clock changed while we were reading, | |
293 | * consider this a good clock read . | |
294 | */ | |
f252169c | 295 | if (tm->tm_sec == hclock_read(0)) |
473ec359 | 296 | break; |
ef71b8f1 SK |
297 | } |
298 | /* | |
299 | * Yes, in theory we could have been running for 60 seconds | |
300 | * and the above test wouldn't work! | |
301 | */ | |
302 | } | |
7eda085c | 303 | |
ef71b8f1 SK |
304 | if (!(status & 0x04)) { /* BCD mode - the default */ |
305 | BCD_TO_BIN(tm->tm_sec); | |
306 | BCD_TO_BIN(tm->tm_min); | |
307 | pmbit = (tm->tm_hour & 0x80); | |
308 | tm->tm_hour &= 0x7f; | |
309 | BCD_TO_BIN(tm->tm_hour); | |
310 | BCD_TO_BIN(tm->tm_wday); | |
311 | BCD_TO_BIN(tm->tm_mday); | |
312 | BCD_TO_BIN(tm->tm_mon); | |
313 | BCD_TO_BIN(tm->tm_year); | |
ef71b8f1 | 314 | } |
7eda085c | 315 | |
ef71b8f1 SK |
316 | /* |
317 | * We don't use the century byte of the Hardware Clock since we | |
318 | * don't know its address (usually 50 or 55). Here, we follow the | |
319 | * advice of the X/Open Base Working Group: "if century is not | |
320 | * specified, then values in the range [69-99] refer to years in the | |
321 | * twentieth century (1969 to 1999 inclusive), and values in the | |
322 | * range [00-68] refer to years in the twenty-first century (2000 to | |
323 | * 2068 inclusive)." | |
324 | */ | |
325 | tm->tm_wday -= 1; | |
326 | tm->tm_mon -= 1; | |
ef71b8f1 SK |
327 | if (tm->tm_year < 69) |
328 | tm->tm_year += 100; | |
329 | if (pmbit) { | |
330 | tm->tm_hour += 12; | |
331 | if (tm->tm_hour == 24) | |
332 | tm->tm_hour = 0; | |
333 | } | |
7eda085c | 334 | |
ef71b8f1 SK |
335 | tm->tm_isdst = -1; /* don't know whether it's daylight */ |
336 | return 0; | |
337 | } | |
7eda085c | 338 | |
336f7c5f SK |
339 | static int set_hardware_clock_cmos(const struct hwclock_control *ctl |
340 | __attribute__((__unused__)), | |
341 | const struct tm *new_broken_time) | |
ef71b8f1 | 342 | { |
f252169c | 343 | hclock_set_time(new_broken_time); |
ef71b8f1 | 344 | return 0; |
7eda085c KZ |
345 | } |
346 | ||
390c72eb | 347 | # if defined(HAVE_IOPL) |
ef71b8f1 SK |
348 | static int i386_iopl(const int level) |
349 | { | |
ef71b8f1 | 350 | return iopl(level); |
390c72eb SK |
351 | } |
352 | # else | |
353 | static int i386_iopl(const int level __attribute__ ((__unused__))) | |
354 | { | |
ef71b8f1 SK |
355 | extern int ioperm(unsigned long from, unsigned long num, int turn_on); |
356 | return ioperm(clock_ctl_addr, 2, 1); | |
390c72eb SK |
357 | } |
358 | # endif | |
7eda085c | 359 | |
ef71b8f1 SK |
360 | static int get_permissions_cmos(void) |
361 | { | |
362 | int rc; | |
363 | ||
c47a6189 WP |
364 | rc = i386_iopl(3); |
365 | if (rc == IOPL_NOT_IMPLEMENTED) { | |
859b0b1a | 366 | warnx(_("ISA port access is not implemented")); |
c47a6189 | 367 | } else if (rc != 0) { |
859b0b1a | 368 | warn(_("iopl() port access failed")); |
ef71b8f1 | 369 | } |
b3e81058 | 370 | return rc; |
7eda085c KZ |
371 | } |
372 | ||
9854912f | 373 | static const char *get_device_path(void) |
df4f1a66 KZ |
374 | { |
375 | return NULL; | |
376 | } | |
377 | ||
e08dddbc | 378 | static const struct clock_ops cmos_interface = { |
859b0b1a | 379 | N_("Using direct ISA access to the clock"), |
7eda085c KZ |
380 | get_permissions_cmos, |
381 | read_hardware_clock_cmos, | |
382 | set_hardware_clock_cmos, | |
383 | synchronize_to_clock_tick_cmos, | |
df4f1a66 | 384 | get_device_path, |
7eda085c KZ |
385 | }; |
386 | ||
ef71b8f1 | 387 | /* |
473ec359 | 388 | * return &cmos if cmos clock present, NULL otherwise. |
ef71b8f1 | 389 | */ |
e08dddbc | 390 | const struct clock_ops *probe_for_cmos_clock(void) |
ef71b8f1 | 391 | { |
473ec359 | 392 | return &cmos_interface; |
7eda085c | 393 | } |