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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
4a94e368 | 3 | Copyright (C) 1988-2022 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
a01567f4 | 41 | #include "dwarf2.h" |
82ca8957 | 42 | #include "dwarf2/frame.h" |
4de283e4 TT |
43 | #include "gdbtypes.h" |
44 | #include "prologue-value.h" | |
45 | #include "remote.h" | |
46 | #include "target-descriptions.h" | |
47 | #include "user-regs.h" | |
48 | #include "observable.h" | |
5f661e03 | 49 | #include "count-one-bits.h" |
4de283e4 | 50 | |
d55e5aa6 | 51 | #include "arch/arm.h" |
4de283e4 | 52 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 53 | #include "arm-tdep.h" |
4de283e4 TT |
54 | #include "gdb/sim-arm.h" |
55 | ||
d55e5aa6 | 56 | #include "elf-bfd.h" |
4de283e4 | 57 | #include "coff/internal.h" |
d55e5aa6 | 58 | #include "elf/arm.h" |
4de283e4 | 59 | |
4de283e4 TT |
60 | #include "record.h" |
61 | #include "record-full.h" | |
62 | #include <algorithm> | |
63 | ||
c2fd7fae AKS |
64 | #include "producer.h" |
65 | ||
b121eeb9 | 66 | #if GDB_SELF_TEST |
268a13a5 | 67 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
68 | #endif |
69 | ||
491144b5 | 70 | static bool arm_debug; |
6529d2dd | 71 | |
7cb6d92a SM |
72 | /* Print an "arm" debug statement. */ |
73 | ||
74 | #define arm_debug_printf(fmt, ...) \ | |
75 | debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__) | |
76 | ||
082fc60d RE |
77 | /* Macros for setting and testing a bit in a minimal symbol that marks |
78 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 79 | is used for this purpose. |
082fc60d RE |
80 | |
81 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 82 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 83 | |
0963b4bd | 84 | #define MSYMBOL_SET_SPECIAL(msym) \ |
e165fcef | 85 | (msym)->set_target_flag_1 (true) |
082fc60d RE |
86 | |
87 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
e165fcef | 88 | (msym)->target_flag_1 () |
082fc60d | 89 | |
60c5725c DJ |
90 | struct arm_mapping_symbol |
91 | { | |
227031b2 | 92 | CORE_ADDR value; |
60c5725c | 93 | char type; |
54cc7474 SM |
94 | |
95 | bool operator< (const arm_mapping_symbol &other) const | |
96 | { return this->value < other.value; } | |
60c5725c | 97 | }; |
54cc7474 SM |
98 | |
99 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 100 | |
bd5766ec | 101 | struct arm_per_bfd |
60c5725c | 102 | { |
bd5766ec | 103 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
104 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
105 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
106 | {} |
107 | ||
bd5766ec | 108 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
109 | |
110 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
111 | ||
112 | The format is an array of vectors of arm_mapping_symbols, there is one | |
113 | vector for each section of the objfile (the array is index by BFD section | |
114 | index). | |
115 | ||
116 | For each section, the vector of arm_mapping_symbol is sorted by | |
117 | symbol value (address). */ | |
118 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
119 | |
120 | /* For each corresponding element of section_maps above, is this vector | |
121 | sorted. */ | |
122 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
123 | }; |
124 | ||
bd5766ec | 125 | /* Per-bfd data used for mapping symbols. */ |
08b8a139 | 126 | static const registry<bfd>::key<arm_per_bfd> arm_bfd_data_key; |
1b7f24cd | 127 | |
afd7eef0 RE |
128 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
129 | static struct cmd_list_element *setarmcmdlist = NULL; | |
130 | static struct cmd_list_element *showarmcmdlist = NULL; | |
131 | ||
fd50bc42 RE |
132 | /* The type of floating-point to use. Keep this in sync with enum |
133 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 134 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
135 | { |
136 | "auto", | |
137 | "softfpa", | |
138 | "fpa", | |
139 | "softvfp", | |
28e97307 DJ |
140 | "vfp", |
141 | NULL | |
fd50bc42 RE |
142 | }; |
143 | ||
144 | /* A variable that can be configured by the user. */ | |
145 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
146 | static const char *current_fp_model = "auto"; | |
147 | ||
28e97307 | 148 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 149 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
150 | { |
151 | "auto", | |
152 | "APCS", | |
153 | "AAPCS", | |
154 | NULL | |
155 | }; | |
156 | ||
157 | /* A variable that can be configured by the user. */ | |
158 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
159 | static const char *arm_abi_string = "auto"; | |
160 | ||
0428b8f5 | 161 | /* The execution mode to assume. */ |
40478521 | 162 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
163 | { |
164 | "auto", | |
165 | "arm", | |
68770265 MGD |
166 | "thumb", |
167 | NULL | |
0428b8f5 DJ |
168 | }; |
169 | ||
170 | static const char *arm_fallback_mode_string = "auto"; | |
171 | static const char *arm_force_mode_string = "auto"; | |
172 | ||
f32bf4a4 YQ |
173 | /* The standard register names, and all the valid aliases for them. Note |
174 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
175 | have been added as builtin user registers in | |
176 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
177 | static const struct |
178 | { | |
179 | const char *name; | |
180 | int regnum; | |
181 | } arm_register_aliases[] = { | |
182 | /* Basic register numbers. */ | |
183 | { "r0", 0 }, | |
184 | { "r1", 1 }, | |
185 | { "r2", 2 }, | |
186 | { "r3", 3 }, | |
187 | { "r4", 4 }, | |
188 | { "r5", 5 }, | |
189 | { "r6", 6 }, | |
190 | { "r7", 7 }, | |
191 | { "r8", 8 }, | |
192 | { "r9", 9 }, | |
193 | { "r10", 10 }, | |
194 | { "r11", 11 }, | |
195 | { "r12", 12 }, | |
196 | { "r13", 13 }, | |
197 | { "r14", 14 }, | |
198 | { "r15", 15 }, | |
199 | /* Synonyms (argument and variable registers). */ | |
200 | { "a1", 0 }, | |
201 | { "a2", 1 }, | |
202 | { "a3", 2 }, | |
203 | { "a4", 3 }, | |
204 | { "v1", 4 }, | |
205 | { "v2", 5 }, | |
206 | { "v3", 6 }, | |
207 | { "v4", 7 }, | |
208 | { "v5", 8 }, | |
209 | { "v6", 9 }, | |
210 | { "v7", 10 }, | |
211 | { "v8", 11 }, | |
212 | /* Other platform-specific names for r9. */ | |
213 | { "sb", 9 }, | |
214 | { "tr", 9 }, | |
215 | /* Special names. */ | |
216 | { "ip", 12 }, | |
123dc839 | 217 | { "lr", 14 }, |
123dc839 DJ |
218 | /* Names used by GCC (not listed in the ARM EABI). */ |
219 | { "sl", 10 }, | |
123dc839 DJ |
220 | /* A special name from the older ATPCS. */ |
221 | { "wr", 7 }, | |
222 | }; | |
bc90b915 | 223 | |
123dc839 | 224 | static const char *const arm_register_names[] = |
da59e081 JM |
225 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
226 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
227 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
228 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
229 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
230 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 231 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 232 | |
65b48a81 PB |
233 | /* Holds the current set of options to be passed to the disassembler. */ |
234 | static char *arm_disassembler_options; | |
235 | ||
afd7eef0 RE |
236 | /* Valid register name styles. */ |
237 | static const char **valid_disassembly_styles; | |
ed9a39eb | 238 | |
afd7eef0 RE |
239 | /* Disassembly style to use. Default to "std" register names. */ |
240 | static const char *disassembly_style; | |
96baa820 | 241 | |
d105cce5 | 242 | /* All possible arm target descriptors. */ |
92d48a1e | 243 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID][2]; |
d105cce5 AH |
244 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; |
245 | ||
ed9a39eb | 246 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 247 | style. */ |
eb4c3f4a | 248 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 249 | struct cmd_list_element *); |
65b48a81 PB |
250 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
251 | struct cmd_list_element *, | |
252 | const char *); | |
ed9a39eb | 253 | |
05d1431c | 254 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 255 | readable_regcache *regcache, |
05d1431c | 256 | int regnum, gdb_byte *buf); |
58d6951d DJ |
257 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
258 | struct regcache *regcache, | |
259 | int regnum, const gdb_byte *buf); | |
260 | ||
e7cf25a8 | 261 | static CORE_ADDR |
553cb527 | 262 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
263 | |
264 | ||
d9311bfa AT |
265 | /* get_next_pcs operations. */ |
266 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
267 | arm_get_next_pcs_read_memory_unsigned_integer, | |
268 | arm_get_next_pcs_syscall_next_pc, | |
269 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
270 | arm_get_next_pcs_is_thumb, |
271 | NULL, | |
d9311bfa AT |
272 | }; |
273 | ||
9b8d791a | 274 | struct arm_prologue_cache |
c3b4394c | 275 | { |
eb5492fa DJ |
276 | /* The stack pointer at the time this frame was created; i.e. the |
277 | caller's stack pointer when this function was called. It is used | |
278 | to identify this frame. */ | |
ae7e2f45 CL |
279 | CORE_ADDR sp; |
280 | ||
281 | /* Additional stack pointers used by M-profile with Security extension. */ | |
282 | /* Use msp_s / psp_s to hold the values of msp / psp when there is | |
283 | no Security extension. */ | |
284 | CORE_ADDR msp_s; | |
285 | CORE_ADDR msp_ns; | |
286 | CORE_ADDR psp_s; | |
287 | CORE_ADDR psp_ns; | |
288 | ||
289 | /* Active stack pointer. */ | |
290 | int active_sp_regnum; | |
0d12d61b YR |
291 | int active_msp_regnum; |
292 | int active_psp_regnum; | |
eb5492fa | 293 | |
4be43953 DJ |
294 | /* The frame base for this frame is just prev_sp - frame size. |
295 | FRAMESIZE is the distance from the frame pointer to the | |
296 | initial stack pointer. */ | |
eb5492fa | 297 | |
c3b4394c | 298 | int framesize; |
eb5492fa DJ |
299 | |
300 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 301 | int framereg; |
eb5492fa | 302 | |
a01567f4 LM |
303 | /* True if the return address is signed, false otherwise. */ |
304 | gdb::optional<bool> ra_signed_state; | |
305 | ||
eb5492fa | 306 | /* Saved register offsets. */ |
098caef4 | 307 | trad_frame_saved_reg *saved_regs; |
0824193f CL |
308 | |
309 | arm_prologue_cache() = default; | |
c3b4394c | 310 | }; |
ed9a39eb | 311 | |
8c9ae6df YR |
312 | |
313 | /* Reconstruct T bit in program status register from LR value. */ | |
314 | ||
315 | static inline ULONGEST | |
316 | reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) | |
317 | { | |
318 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
319 | if (IS_THUMB_ADDR (lr)) | |
320 | psr |= t_bit; | |
321 | else | |
322 | psr &= ~t_bit; | |
323 | ||
324 | return psr; | |
325 | } | |
326 | ||
ae7e2f45 CL |
327 | /* Initialize stack pointers, and flag the active one. */ |
328 | ||
329 | static inline void | |
330 | arm_cache_init_sp (int regnum, CORE_ADDR* member, | |
331 | struct arm_prologue_cache *cache, | |
bd2b40ac | 332 | frame_info_ptr frame) |
ae7e2f45 CL |
333 | { |
334 | CORE_ADDR val = get_frame_register_unsigned (frame, regnum); | |
335 | if (val == cache->sp) | |
336 | cache->active_sp_regnum = regnum; | |
337 | ||
338 | *member = val; | |
339 | } | |
340 | ||
0824193f CL |
341 | /* Initialize CACHE fields for which zero is not adequate (CACHE is |
342 | expected to have been ZALLOC'ed before calling this function). */ | |
343 | ||
344 | static void | |
345 | arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch) | |
346 | { | |
ae7e2f45 CL |
347 | cache->active_sp_regnum = ARM_SP_REGNUM; |
348 | ||
0824193f CL |
349 | cache->saved_regs = trad_frame_alloc_saved_regs (gdbarch); |
350 | } | |
351 | ||
352 | /* Similar to the previous function, but extracts GDBARCH from FRAME. */ | |
353 | ||
354 | static void | |
bd2b40ac | 355 | arm_cache_init (struct arm_prologue_cache *cache, frame_info_ptr frame) |
0824193f CL |
356 | { |
357 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 358 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0824193f CL |
359 | |
360 | arm_cache_init (cache, gdbarch); | |
fe642a5b | 361 | cache->sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
ae7e2f45 CL |
362 | |
363 | if (tdep->have_sec_ext) | |
364 | { | |
0d12d61b YR |
365 | CORE_ADDR msp_val = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); |
366 | CORE_ADDR psp_val = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); | |
367 | ||
ae7e2f45 CL |
368 | arm_cache_init_sp (tdep->m_profile_msp_s_regnum, &cache->msp_s, cache, frame); |
369 | arm_cache_init_sp (tdep->m_profile_psp_s_regnum, &cache->psp_s, cache, frame); | |
370 | arm_cache_init_sp (tdep->m_profile_msp_ns_regnum, &cache->msp_ns, cache, frame); | |
371 | arm_cache_init_sp (tdep->m_profile_psp_ns_regnum, &cache->psp_ns, cache, frame); | |
372 | ||
0d12d61b YR |
373 | if (msp_val == cache->msp_s) |
374 | cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; | |
375 | else if (msp_val == cache->msp_ns) | |
376 | cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; | |
377 | if (psp_val == cache->psp_s) | |
378 | cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; | |
379 | else if (psp_val == cache->psp_ns) | |
380 | cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; | |
381 | ||
ae7e2f45 CL |
382 | /* Use MSP_S as default stack pointer. */ |
383 | if (cache->active_sp_regnum == ARM_SP_REGNUM) | |
384 | cache->active_sp_regnum = tdep->m_profile_msp_s_regnum; | |
385 | } | |
386 | else if (tdep->is_m) | |
387 | { | |
388 | arm_cache_init_sp (tdep->m_profile_msp_regnum, &cache->msp_s, cache, frame); | |
389 | arm_cache_init_sp (tdep->m_profile_psp_regnum, &cache->psp_s, cache, frame); | |
390 | } | |
391 | else | |
392 | arm_cache_init_sp (ARM_SP_REGNUM, &cache->msp_s, cache, frame); | |
393 | } | |
394 | ||
395 | /* Return the requested stack pointer value (in REGNUM), taking into | |
396 | account whether we have a Security extension or an M-profile | |
397 | CPU. */ | |
398 | ||
399 | static CORE_ADDR | |
400 | arm_cache_get_sp_register (struct arm_prologue_cache *cache, | |
401 | arm_gdbarch_tdep *tdep, int regnum) | |
402 | { | |
ae7e2f45 CL |
403 | if (tdep->have_sec_ext) |
404 | { | |
405 | if (regnum == tdep->m_profile_msp_s_regnum) | |
406 | return cache->msp_s; | |
407 | if (regnum == tdep->m_profile_msp_ns_regnum) | |
408 | return cache->msp_ns; | |
409 | if (regnum == tdep->m_profile_psp_s_regnum) | |
410 | return cache->psp_s; | |
411 | if (regnum == tdep->m_profile_psp_ns_regnum) | |
412 | return cache->psp_ns; | |
0d12d61b YR |
413 | if (regnum == tdep->m_profile_msp_regnum) |
414 | return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); | |
415 | if (regnum == tdep->m_profile_psp_regnum) | |
416 | return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); | |
b9b66a3a YR |
417 | if (regnum == ARM_SP_REGNUM) |
418 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 CL |
419 | } |
420 | else if (tdep->is_m) | |
421 | { | |
422 | if (regnum == tdep->m_profile_msp_regnum) | |
423 | return cache->msp_s; | |
424 | if (regnum == tdep->m_profile_psp_regnum) | |
425 | return cache->psp_s; | |
b9b66a3a YR |
426 | if (regnum == ARM_SP_REGNUM) |
427 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 | 428 | } |
b9b66a3a YR |
429 | else if (regnum == ARM_SP_REGNUM) |
430 | return cache->sp; | |
ae7e2f45 CL |
431 | |
432 | gdb_assert_not_reached ("Invalid SP selection"); | |
433 | } | |
434 | ||
435 | /* Return the previous stack address, depending on which SP register | |
436 | is active. */ | |
437 | ||
438 | static CORE_ADDR | |
439 | arm_cache_get_prev_sp_value (struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep) | |
440 | { | |
441 | CORE_ADDR val = arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
442 | return val; | |
443 | } | |
444 | ||
445 | /* Set the active stack pointer to VAL. */ | |
446 | ||
447 | static void | |
448 | arm_cache_set_active_sp_value (struct arm_prologue_cache *cache, | |
449 | arm_gdbarch_tdep *tdep, CORE_ADDR val) | |
450 | { | |
ae7e2f45 CL |
451 | if (tdep->have_sec_ext) |
452 | { | |
453 | if (cache->active_sp_regnum == tdep->m_profile_msp_s_regnum) | |
454 | cache->msp_s = val; | |
455 | else if (cache->active_sp_regnum == tdep->m_profile_msp_ns_regnum) | |
456 | cache->msp_ns = val; | |
457 | else if (cache->active_sp_regnum == tdep->m_profile_psp_s_regnum) | |
458 | cache->psp_s = val; | |
459 | else if (cache->active_sp_regnum == tdep->m_profile_psp_ns_regnum) | |
460 | cache->psp_ns = val; | |
461 | ||
462 | return; | |
463 | } | |
464 | else if (tdep->is_m) | |
465 | { | |
466 | if (cache->active_sp_regnum == tdep->m_profile_msp_regnum) | |
467 | cache->msp_s = val; | |
468 | else if (cache->active_sp_regnum == tdep->m_profile_psp_regnum) | |
469 | cache->psp_s = val; | |
470 | ||
471 | return; | |
472 | } | |
b9b66a3a YR |
473 | else if (cache->active_sp_regnum == ARM_SP_REGNUM) |
474 | { | |
475 | cache->sp = val; | |
476 | return; | |
477 | } | |
ae7e2f45 CL |
478 | |
479 | gdb_assert_not_reached ("Invalid SP selection"); | |
0824193f CL |
480 | } |
481 | ||
d65edaa0 | 482 | /* Return true if REGNUM is one of the alternative stack pointers. */ |
ef273377 CL |
483 | |
484 | static bool | |
d65edaa0 | 485 | arm_is_alternative_sp_register (arm_gdbarch_tdep *tdep, int regnum) |
ef273377 | 486 | { |
d65edaa0 | 487 | if ((regnum == tdep->m_profile_msp_regnum) |
ef273377 CL |
488 | || (regnum == tdep->m_profile_msp_s_regnum) |
489 | || (regnum == tdep->m_profile_msp_ns_regnum) | |
490 | || (regnum == tdep->m_profile_psp_regnum) | |
491 | || (regnum == tdep->m_profile_psp_s_regnum) | |
492 | || (regnum == tdep->m_profile_psp_ns_regnum)) | |
493 | return true; | |
494 | else | |
495 | return false; | |
496 | } | |
497 | ||
498 | /* Set the active stack pointer to SP_REGNUM. */ | |
499 | ||
500 | static void | |
501 | arm_cache_switch_prev_sp (struct arm_prologue_cache *cache, | |
502 | arm_gdbarch_tdep *tdep, int sp_regnum) | |
503 | { | |
d65edaa0 | 504 | gdb_assert (arm_is_alternative_sp_register (tdep, sp_regnum)); |
ef273377 CL |
505 | |
506 | if (tdep->have_sec_ext) | |
507 | gdb_assert (sp_regnum != tdep->m_profile_msp_regnum | |
508 | && sp_regnum != tdep->m_profile_psp_regnum); | |
509 | ||
510 | cache->active_sp_regnum = sp_regnum; | |
511 | } | |
512 | ||
9ecab40c SM |
513 | namespace { |
514 | ||
515 | /* Abstract class to read ARM instructions from memory. */ | |
516 | ||
517 | class arm_instruction_reader | |
518 | { | |
519 | public: | |
2c5b1849 | 520 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
521 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
522 | }; | |
523 | ||
524 | /* Read instructions from target memory. */ | |
525 | ||
526 | class target_arm_instruction_reader : public arm_instruction_reader | |
527 | { | |
528 | public: | |
529 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
530 | { | |
531 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
532 | } | |
533 | }; | |
534 | ||
535 | } /* namespace */ | |
536 | ||
537 | static CORE_ADDR arm_analyze_prologue | |
538 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
539 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 540 | |
cca44b1b JB |
541 | /* Architecture version for displaced stepping. This effects the behaviour of |
542 | certain instructions, and really should not be hard-wired. */ | |
543 | ||
544 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
545 | ||
c7ae7675 | 546 | /* See arm-tdep.h. */ |
c906108c | 547 | |
491144b5 | 548 | bool arm_apcs_32 = true; |
ef273377 | 549 | bool arm_unwind_secure_frames = true; |
c906108c | 550 | |
9779414d DJ |
551 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
552 | ||
478fd957 | 553 | int |
9779414d DJ |
554 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
555 | { | |
08106042 | 556 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
557 | |
558 | if (tdep->is_m) | |
9779414d DJ |
559 | return XPSR_T; |
560 | else | |
561 | return CPSR_T; | |
562 | } | |
563 | ||
d0e59a68 AT |
564 | /* Determine if the processor is currently executing in Thumb mode. */ |
565 | ||
566 | int | |
567 | arm_is_thumb (struct regcache *regcache) | |
568 | { | |
569 | ULONGEST cpsr; | |
ac7936df | 570 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
571 | |
572 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
573 | ||
574 | return (cpsr & t_bit) != 0; | |
575 | } | |
576 | ||
60270718 AB |
577 | /* Determine if FRAME is executing in Thumb mode. FRAME must be an ARM |
578 | frame. */ | |
b39cc962 | 579 | |
25b41d01 | 580 | int |
bd2b40ac | 581 | arm_frame_is_thumb (frame_info_ptr frame) |
b39cc962 | 582 | { |
60270718 AB |
583 | /* Check the architecture of FRAME. */ |
584 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
585 | gdb_assert (gdbarch_bfd_arch_info (gdbarch)->arch == bfd_arch_arm); | |
b39cc962 DJ |
586 | |
587 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
588 | directly (from a signal frame or dummy frame) or by interpreting | |
589 | the saved LR (from a prologue or DWARF frame). So consult it and | |
590 | trust the unwinders. */ | |
60270718 | 591 | CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
b39cc962 | 592 | |
60270718 AB |
593 | /* Find and extract the thumb bit. */ |
594 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
9779414d | 595 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
596 | } |
597 | ||
f9d67f43 DJ |
598 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
599 | return its type. Otherwise, return 0. If START is non-NULL, | |
600 | set *START to the location of the mapping symbol. */ | |
c906108c | 601 | |
f9d67f43 DJ |
602 | static char |
603 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 604 | { |
60c5725c | 605 | struct obj_section *sec; |
0428b8f5 | 606 | |
60c5725c DJ |
607 | /* If there are mapping symbols, consult them. */ |
608 | sec = find_pc_section (memaddr); | |
609 | if (sec != NULL) | |
610 | { | |
98badbfd | 611 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd.get ()); |
60c5725c DJ |
612 | if (data != NULL) |
613 | { | |
4838e44c SM |
614 | unsigned int section_idx = sec->the_bfd_section->index; |
615 | arm_mapping_symbol_vec &map | |
616 | = data->section_maps[section_idx]; | |
617 | ||
618 | /* Sort the vector on first use. */ | |
619 | if (!data->section_maps_sorted[section_idx]) | |
620 | { | |
621 | std::sort (map.begin (), map.end ()); | |
622 | data->section_maps_sorted[section_idx] = true; | |
623 | } | |
624 | ||
0c1bcd23 | 625 | arm_mapping_symbol map_key = { memaddr - sec->addr (), 0 }; |
54cc7474 SM |
626 | arm_mapping_symbol_vec::const_iterator it |
627 | = std::lower_bound (map.begin (), map.end (), map_key); | |
628 | ||
629 | /* std::lower_bound finds the earliest ordered insertion | |
630 | point. If the symbol at this position starts at this exact | |
631 | address, we use that; otherwise, the preceding | |
632 | mapping symbol covers this address. */ | |
633 | if (it < map.end ()) | |
60c5725c | 634 | { |
54cc7474 | 635 | if (it->value == map_key.value) |
60c5725c | 636 | { |
f9d67f43 | 637 | if (start) |
0c1bcd23 | 638 | *start = it->value + sec->addr (); |
54cc7474 | 639 | return it->type; |
60c5725c DJ |
640 | } |
641 | } | |
54cc7474 SM |
642 | |
643 | if (it > map.begin ()) | |
644 | { | |
645 | arm_mapping_symbol_vec::const_iterator prev_it | |
646 | = it - 1; | |
647 | ||
648 | if (start) | |
0c1bcd23 | 649 | *start = prev_it->value + sec->addr (); |
54cc7474 SM |
650 | return prev_it->type; |
651 | } | |
60c5725c DJ |
652 | } |
653 | } | |
654 | ||
f9d67f43 DJ |
655 | return 0; |
656 | } | |
657 | ||
658 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
659 | function. This function should be called for addresses unrelated to | |
660 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
661 | ||
e3039479 | 662 | int |
9779414d | 663 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 664 | { |
7cbd4a93 | 665 | struct bound_minimal_symbol sym; |
f9d67f43 | 666 | char type; |
187b041e | 667 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
08106042 | 668 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
187b041e SM |
669 | |
670 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
671 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
672 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
673 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
674 | |
675 | /* If checking the mode of displaced instruction in copy area, the mode | |
676 | should be determined by instruction on the original address. */ | |
677 | if (dsc) | |
678 | { | |
136821d9 SM |
679 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
680 | (unsigned long) dsc->insn_addr, | |
681 | (unsigned long) memaddr); | |
a42244db YQ |
682 | memaddr = dsc->insn_addr; |
683 | } | |
f9d67f43 DJ |
684 | |
685 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
686 | if (IS_THUMB_ADDR (memaddr)) | |
687 | return 1; | |
688 | ||
689 | /* If the user wants to override the symbol table, let him. */ | |
690 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
691 | return 0; | |
692 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
693 | return 1; | |
694 | ||
9779414d | 695 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
345bd07c | 696 | if (tdep->is_m) |
9779414d DJ |
697 | return 1; |
698 | ||
f9d67f43 DJ |
699 | /* If there are mapping symbols, consult them. */ |
700 | type = arm_find_mapping_symbol (memaddr, NULL); | |
701 | if (type) | |
702 | return type == 't'; | |
703 | ||
ed9a39eb | 704 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 705 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
706 | if (sym.minsym) |
707 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
708 | |
709 | /* If the user wants to override the fallback mode, let them. */ | |
710 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
711 | return 0; | |
712 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
713 | return 1; | |
714 | ||
715 | /* If we couldn't find any symbol, but we're talking to a running | |
716 | target, then trust the current value of $cpsr. This lets | |
717 | "display/i $pc" always show the correct mode (though if there is | |
718 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 719 | displayed in the mode it will be executed). */ |
9dccd06e | 720 | if (target_has_registers ()) |
18819fa6 | 721 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
722 | |
723 | /* Otherwise we're out of luck; we assume ARM. */ | |
724 | return 0; | |
c906108c SS |
725 | } |
726 | ||
ca90e760 | 727 | /* Determine if the address specified equals any of these magic return |
55ea94da | 728 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
ca90e760 FH |
729 | architectures. |
730 | ||
731 | From ARMv6-M Reference Manual B1.5.8 | |
732 | Table B1-5 Exception return behavior | |
733 | ||
734 | EXC_RETURN Return To Return Stack | |
735 | 0xFFFFFFF1 Handler mode Main | |
736 | 0xFFFFFFF9 Thread mode Main | |
737 | 0xFFFFFFFD Thread mode Process | |
738 | ||
739 | From ARMv7-M Reference Manual B1.5.8 | |
740 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
741 | ||
742 | EXC_RETURN Return To Return Stack | |
743 | 0xFFFFFFF1 Handler mode Main | |
744 | 0xFFFFFFF9 Thread mode Main | |
745 | 0xFFFFFFFD Thread mode Process | |
746 | ||
747 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
748 | FP | |
749 | ||
750 | EXC_RETURN Return To Return Stack Frame Type | |
751 | 0xFFFFFFE1 Handler mode Main Extended | |
752 | 0xFFFFFFE9 Thread mode Main Extended | |
753 | 0xFFFFFFED Thread mode Process Extended | |
754 | 0xFFFFFFF1 Handler mode Main Basic | |
755 | 0xFFFFFFF9 Thread mode Main Basic | |
756 | 0xFFFFFFFD Thread mode Process Basic | |
757 | ||
758 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
759 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
760 | ||
761 | In the ARMv8-M Architecture Technical Reference also adds | |
762 | for implementations without the Security Extension: | |
763 | ||
764 | EXC_RETURN Condition | |
765 | 0xFFFFFFB0 Return to Handler mode. | |
766 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
767 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
768 | |
769 | static int | |
ef273377 CL |
770 | arm_m_addr_is_magic (struct gdbarch *gdbarch, CORE_ADDR addr) |
771 | { | |
08106042 | 772 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ef273377 CL |
773 | if (tdep->have_sec_ext) |
774 | { | |
775 | switch ((addr & 0xff000000)) | |
776 | { | |
777 | case 0xff000000: /* EXC_RETURN pattern. */ | |
778 | case 0xfe000000: /* FNC_RETURN pattern. */ | |
779 | return 1; | |
780 | default: | |
781 | return 0; | |
782 | } | |
783 | } | |
784 | else | |
785 | { | |
786 | switch (addr) | |
787 | { | |
788 | /* Values from ARMv8-M Architecture Technical Reference. */ | |
789 | case 0xffffffb0: | |
790 | case 0xffffffb8: | |
791 | case 0xffffffbc: | |
792 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of | |
793 | the exception return behavior. */ | |
794 | case 0xffffffe1: | |
795 | case 0xffffffe9: | |
796 | case 0xffffffed: | |
797 | case 0xfffffff1: | |
798 | case 0xfffffff9: | |
799 | case 0xfffffffd: | |
800 | /* Address is magic. */ | |
801 | return 1; | |
ca90e760 | 802 | |
ef273377 CL |
803 | default: |
804 | /* Address is not magic. */ | |
805 | return 0; | |
806 | } | |
ca90e760 FH |
807 | } |
808 | } | |
809 | ||
181c1381 | 810 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 811 | static CORE_ADDR |
24568a2c | 812 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 813 | { |
08106042 | 814 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 815 | |
2ae28aa9 YQ |
816 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
817 | (the magic exception return address). */ | |
ef273377 | 818 | if (tdep->is_m && arm_m_addr_is_magic (gdbarch, val)) |
2ae28aa9 YQ |
819 | return val; |
820 | ||
a3a2ee65 | 821 | if (arm_apcs_32) |
dd6be234 | 822 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 823 | else |
a3a2ee65 | 824 | return (val & 0x03fffffc); |
c906108c SS |
825 | } |
826 | ||
0d39a070 | 827 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
828 | can be safely ignored during prologue skipping. IS_THUMB is true |
829 | if the function is known to be a Thumb function due to the way it | |
830 | is being called. */ | |
0d39a070 | 831 | static int |
e0634ccf | 832 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 833 | { |
e0634ccf | 834 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 835 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
836 | |
837 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 838 | if (msym.minsym != NULL |
4aeddc50 | 839 | && msym.value_address () == pc |
c9d95fa3 | 840 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 841 | { |
c9d95fa3 | 842 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 843 | |
e0634ccf UW |
844 | /* The GNU linker's Thumb call stub to foo is named |
845 | __foo_from_thumb. */ | |
846 | if (strstr (name, "_from_thumb") != NULL) | |
847 | name += 2; | |
0d39a070 | 848 | |
e0634ccf UW |
849 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
850 | arguments to their argument types in non-prototyped | |
851 | functions. */ | |
61012eef | 852 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 853 | return 1; |
61012eef | 854 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 855 | return 1; |
0d39a070 | 856 | |
e0634ccf | 857 | /* Internal functions related to thread-local storage. */ |
61012eef | 858 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 859 | return 1; |
61012eef | 860 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
861 | return 1; |
862 | } | |
863 | else | |
864 | { | |
865 | /* If we run against a stripped glibc, we may be unable to identify | |
866 | special functions by name. Check for one important case, | |
867 | __aeabi_read_tp, by comparing the *code* against the default | |
868 | implementation (this is hand-written ARM assembler in glibc). */ | |
869 | ||
870 | if (!is_thumb | |
198cd59d | 871 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 872 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 873 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
874 | == 0xe240f01f) /* sub pc, r0, #31 */ |
875 | return 1; | |
876 | } | |
ec3d575a | 877 | |
0d39a070 DJ |
878 | return 0; |
879 | } | |
880 | ||
621c6d5b YQ |
881 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
882 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
883 | instruction. */ | |
884 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
885 | ((bits ((insn1), 0, 3) << 12) \ | |
886 | | (bits ((insn1), 10, 10) << 11) \ | |
887 | | (bits ((insn2), 12, 14) << 8) \ | |
888 | | bits ((insn2), 0, 7)) | |
889 | ||
890 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
891 | the 32-bit instruction. */ | |
892 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
893 | ((bits ((insn), 16, 19) << 12) \ | |
894 | | bits ((insn), 0, 11)) | |
895 | ||
ec3d575a UW |
896 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
897 | ||
898 | static unsigned int | |
899 | thumb_expand_immediate (unsigned int imm) | |
900 | { | |
901 | unsigned int count = imm >> 7; | |
902 | ||
903 | if (count < 8) | |
904 | switch (count / 2) | |
905 | { | |
906 | case 0: | |
907 | return imm & 0xff; | |
908 | case 1: | |
909 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
910 | case 2: | |
911 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
912 | case 3: | |
913 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
914 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
915 | } | |
916 | ||
917 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
918 | } | |
919 | ||
540314bd YQ |
920 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
921 | epilogue, 0 otherwise. */ | |
922 | ||
923 | static int | |
924 | thumb_instruction_restores_sp (unsigned short insn) | |
925 | { | |
926 | return (insn == 0x46bd /* mov sp, r7 */ | |
927 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
928 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
929 | } | |
930 | ||
29d73ae4 DJ |
931 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
932 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
933 | clobber the stack frame unexpectedly, or an unknown instruction. |
934 | Return the last address which is definitely safe to skip for an | |
935 | initial breakpoint. */ | |
c906108c SS |
936 | |
937 | static CORE_ADDR | |
29d73ae4 DJ |
938 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
939 | CORE_ADDR start, CORE_ADDR limit, | |
940 | struct arm_prologue_cache *cache) | |
c906108c | 941 | { |
08106042 | 942 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 | 943 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 944 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
945 | int i; |
946 | pv_t regs[16]; | |
29d73ae4 | 947 | CORE_ADDR offset; |
ec3d575a | 948 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 949 | |
29d73ae4 DJ |
950 | for (i = 0; i < 16; i++) |
951 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 952 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 953 | |
29d73ae4 | 954 | while (start < limit) |
c906108c | 955 | { |
29d73ae4 | 956 | unsigned short insn; |
a01567f4 | 957 | gdb::optional<bool> ra_signed_state; |
29d73ae4 | 958 | |
198cd59d | 959 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 960 | |
94c30b78 | 961 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 962 | { |
29d73ae4 DJ |
963 | int regno; |
964 | int mask; | |
4be43953 | 965 | |
f7b7ed97 | 966 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 967 | break; |
29d73ae4 DJ |
968 | |
969 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
970 | whether to save LR (R14). */ | |
971 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
972 | ||
973 | /* Calculate offsets of saved R0-R7 and LR. */ | |
974 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
975 | if (mask & (1 << regno)) | |
976 | { | |
29d73ae4 DJ |
977 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
978 | -4); | |
f7b7ed97 | 979 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 980 | } |
da59e081 | 981 | } |
1db01f22 | 982 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 983 | { |
29d73ae4 | 984 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
985 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
986 | -offset); | |
da59e081 | 987 | } |
808f7ab1 YQ |
988 | else if (thumb_instruction_restores_sp (insn)) |
989 | { | |
990 | /* Don't scan past the epilogue. */ | |
991 | break; | |
992 | } | |
0d39a070 DJ |
993 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
994 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
995 | (insn & 0xff) << 2); | |
996 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
997 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
998 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
999 | bits (insn, 6, 8)); | |
1000 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
1001 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1002 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
1003 | bits (insn, 0, 7)); | |
1004 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
1005 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
1006 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
1007 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
1008 | regs[bits (insn, 6, 8)]); | |
1009 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
1010 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
1011 | { | |
1012 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
1013 | int rm = bits (insn, 3, 6); | |
1014 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
1015 | } | |
29d73ae4 | 1016 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 1017 | { |
29d73ae4 DJ |
1018 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
1019 | int src_reg = (insn & 0x78) >> 3; | |
1020 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 1021 | } |
29d73ae4 | 1022 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 1023 | { |
29d73ae4 DJ |
1024 | /* Handle stores to the stack. Normally pushes are used, |
1025 | but with GCC -mtpcs-frame, there may be other stores | |
1026 | in the prologue to create the frame. */ | |
1027 | int regno = (insn >> 8) & 0x7; | |
1028 | pv_t addr; | |
1029 | ||
1030 | offset = (insn & 0xff) << 2; | |
1031 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
1032 | ||
f7b7ed97 | 1033 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
1034 | break; |
1035 | ||
f7b7ed97 | 1036 | stack.store (addr, 4, regs[regno]); |
da59e081 | 1037 | } |
0d39a070 DJ |
1038 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
1039 | { | |
1040 | int rd = bits (insn, 0, 2); | |
1041 | int rn = bits (insn, 3, 5); | |
1042 | pv_t addr; | |
1043 | ||
1044 | offset = bits (insn, 6, 10) << 2; | |
1045 | addr = pv_add_constant (regs[rn], offset); | |
1046 | ||
f7b7ed97 | 1047 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
1048 | break; |
1049 | ||
f7b7ed97 | 1050 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
1051 | } |
1052 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
1053 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
1054 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
1055 | /* Ignore stores of argument registers to the stack. */ | |
1056 | ; | |
1057 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
1058 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1059 | /* Ignore block loads from the stack, potentially copying | |
1060 | parameters from memory. */ | |
1061 | ; | |
1062 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
1063 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
1064 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
1065 | /* Similarly ignore single loads from the stack. */ | |
1066 | ; | |
1067 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
1068 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
1069 | /* Skip register copies, i.e. saves to another register | |
1070 | instead of the stack. */ | |
1071 | ; | |
1072 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
1073 | /* Recognize constant loads; even with small stacks these are necessary | |
1074 | on Thumb. */ | |
1075 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
1076 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
1077 | { | |
1078 | /* Constant pool loads, for the same reason. */ | |
1079 | unsigned int constant; | |
1080 | CORE_ADDR loc; | |
1081 | ||
1082 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
1083 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1084 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
1085 | } | |
db24da6d | 1086 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 1087 | { |
0d39a070 DJ |
1088 | unsigned short inst2; |
1089 | ||
198cd59d YQ |
1090 | inst2 = read_code_unsigned_integer (start + 2, 2, |
1091 | byte_order_for_code); | |
a01567f4 | 1092 | uint32_t whole_insn = (insn << 16) | inst2; |
0d39a070 DJ |
1093 | |
1094 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
1095 | { | |
1096 | /* BL, BLX. Allow some special function calls when | |
1097 | skipping the prologue; GCC generates these before | |
1098 | storing arguments to the stack. */ | |
1099 | CORE_ADDR nextpc; | |
1100 | int j1, j2, imm1, imm2; | |
1101 | ||
1102 | imm1 = sbits (insn, 0, 10); | |
1103 | imm2 = bits (inst2, 0, 10); | |
1104 | j1 = bit (inst2, 13); | |
1105 | j2 = bit (inst2, 11); | |
1106 | ||
1107 | offset = ((imm1 << 12) + (imm2 << 1)); | |
1108 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
1109 | ||
1110 | nextpc = start + 4 + offset; | |
1111 | /* For BLX make sure to clear the low bits. */ | |
1112 | if (bit (inst2, 12) == 0) | |
1113 | nextpc = nextpc & 0xfffffffc; | |
1114 | ||
e0634ccf UW |
1115 | if (!skip_prologue_function (gdbarch, nextpc, |
1116 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
1117 | break; |
1118 | } | |
ec3d575a | 1119 | |
0963b4bd MS |
1120 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
1121 | { registers } */ | |
ec3d575a UW |
1122 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1123 | { | |
1124 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1125 | int regno; | |
1126 | ||
f7b7ed97 | 1127 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1128 | break; |
1129 | ||
1130 | /* Calculate offsets of saved registers. */ | |
1131 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
1132 | if (inst2 & (1 << regno)) | |
1133 | { | |
1134 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 1135 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1136 | } |
1137 | ||
1138 | if (insn & 0x0020) | |
1139 | regs[bits (insn, 0, 3)] = addr; | |
1140 | } | |
1141 | ||
fcaa1071 CL |
1142 | /* vstmdb Rn{!}, { D-registers } (aka vpush). */ |
1143 | else if ((insn & 0xff20) == 0xed20 | |
1144 | && (inst2 & 0x0f00) == 0x0b00 | |
1145 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1146 | { | |
1147 | /* Address SP points to. */ | |
1148 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1149 | ||
1150 | /* Number of registers saved. */ | |
1151 | unsigned int number = bits (inst2, 0, 7) >> 1; | |
1152 | ||
1153 | /* First register to save. */ | |
1154 | int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4); | |
1155 | ||
1156 | if (stack.store_would_trash (addr)) | |
1157 | break; | |
1158 | ||
1159 | /* Calculate offsets of saved registers. */ | |
1160 | for (; number > 0; number--) | |
1161 | { | |
1162 | addr = pv_add_constant (addr, -8); | |
1163 | stack.store (addr, 8, pv_register (ARM_D0_REGNUM | |
1164 | + vd + number, 0)); | |
1165 | } | |
1166 | ||
1167 | /* Writeback SP to account for the saved registers. */ | |
1168 | regs[bits (insn, 0, 3)] = addr; | |
1169 | } | |
1170 | ||
0963b4bd MS |
1171 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
1172 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
1173 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1174 | { | |
1175 | int regno1 = bits (inst2, 12, 15); | |
1176 | int regno2 = bits (inst2, 8, 11); | |
1177 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1178 | ||
1179 | offset = inst2 & 0xff; | |
1180 | if (insn & 0x0080) | |
1181 | addr = pv_add_constant (addr, offset); | |
1182 | else | |
1183 | addr = pv_add_constant (addr, -offset); | |
1184 | ||
f7b7ed97 | 1185 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1186 | break; |
1187 | ||
f7b7ed97 TT |
1188 | stack.store (addr, 4, regs[regno1]); |
1189 | stack.store (pv_add_constant (addr, 4), | |
1190 | 4, regs[regno2]); | |
ec3d575a UW |
1191 | |
1192 | if (insn & 0x0020) | |
1193 | regs[bits (insn, 0, 3)] = addr; | |
1194 | } | |
1195 | ||
1196 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
1197 | && (inst2 & 0x0c00) == 0x0c00 | |
1198 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1199 | { | |
1200 | int regno = bits (inst2, 12, 15); | |
1201 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1202 | ||
1203 | offset = inst2 & 0xff; | |
1204 | if (inst2 & 0x0200) | |
1205 | addr = pv_add_constant (addr, offset); | |
1206 | else | |
1207 | addr = pv_add_constant (addr, -offset); | |
1208 | ||
f7b7ed97 | 1209 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1210 | break; |
1211 | ||
f7b7ed97 | 1212 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1213 | |
1214 | if (inst2 & 0x0100) | |
1215 | regs[bits (insn, 0, 3)] = addr; | |
1216 | } | |
1217 | ||
1218 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
1219 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1220 | { | |
1221 | int regno = bits (inst2, 12, 15); | |
1222 | pv_t addr; | |
1223 | ||
1224 | offset = inst2 & 0xfff; | |
1225 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
1226 | ||
f7b7ed97 | 1227 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1228 | break; |
1229 | ||
f7b7ed97 | 1230 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1231 | } |
1232 | ||
1233 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 1234 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1235 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1236 | ; |
ec3d575a UW |
1237 | |
1238 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
1239 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1240 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1241 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1242 | ; |
ec3d575a | 1243 | |
0963b4bd MS |
1244 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
1245 | { registers } */ | |
ec3d575a UW |
1246 | && (inst2 & 0x8000) == 0x0000 |
1247 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1248 | /* Ignore block loads from the stack, potentially copying | |
1249 | parameters from memory. */ | |
0d39a070 | 1250 | ; |
ec3d575a | 1251 | |
f8c6d152 | 1252 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 1253 | [Rn, #+/-imm] */ |
0d39a070 | 1254 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1255 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 1256 | ; |
ec3d575a UW |
1257 | |
1258 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
1259 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1260 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1261 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1262 | ; |
ec3d575a UW |
1263 | |
1264 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 1265 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1266 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1267 | ; |
ec3d575a UW |
1268 | |
1269 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
1270 | && (inst2 & 0x8000) == 0x0000) | |
1271 | { | |
1272 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1273 | | (bits (inst2, 12, 14) << 8) | |
1274 | | bits (inst2, 0, 7)); | |
1275 | ||
1276 | regs[bits (inst2, 8, 11)] | |
1277 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1278 | thumb_expand_immediate (imm)); | |
1279 | } | |
1280 | ||
1281 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1282 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1283 | { |
ec3d575a UW |
1284 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1285 | | (bits (inst2, 12, 14) << 8) | |
1286 | | bits (inst2, 0, 7)); | |
1287 | ||
1288 | regs[bits (inst2, 8, 11)] | |
1289 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1290 | } | |
1291 | ||
1292 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1293 | && (inst2 & 0x8000) == 0x0000) | |
1294 | { | |
1295 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1296 | | (bits (inst2, 12, 14) << 8) | |
1297 | | bits (inst2, 0, 7)); | |
1298 | ||
1299 | regs[bits (inst2, 8, 11)] | |
1300 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1301 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1302 | } | |
1303 | ||
1304 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1305 | && (inst2 & 0x8000) == 0x0000) | |
1306 | { | |
1307 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1308 | | (bits (inst2, 12, 14) << 8) | |
1309 | | bits (inst2, 0, 7)); | |
1310 | ||
1311 | regs[bits (inst2, 8, 11)] | |
1312 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1313 | } | |
1314 | ||
1315 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1316 | { | |
1317 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1318 | | (bits (inst2, 12, 14) << 8) | |
1319 | | bits (inst2, 0, 7)); | |
1320 | ||
1321 | regs[bits (inst2, 8, 11)] | |
1322 | = pv_constant (thumb_expand_immediate (imm)); | |
1323 | } | |
1324 | ||
1325 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1326 | { | |
621c6d5b YQ |
1327 | unsigned int imm |
1328 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1329 | |
1330 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1331 | } | |
1332 | ||
1333 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1334 | && (inst2 & 0xf0f0) == 0) | |
1335 | { | |
1336 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1337 | int src_reg = inst2 & 0xf; | |
1338 | regs[dst_reg] = regs[src_reg]; | |
1339 | } | |
1340 | ||
1341 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1342 | { | |
1343 | /* Constant pool loads. */ | |
1344 | unsigned int constant; | |
1345 | CORE_ADDR loc; | |
1346 | ||
cac395ea | 1347 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1348 | if (insn & 0x0080) |
1349 | loc = start + 4 + offset; | |
1350 | else | |
1351 | loc = start + 4 - offset; | |
1352 | ||
1353 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1354 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1355 | } | |
1356 | ||
1357 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1358 | { | |
1359 | /* Constant pool loads. */ | |
1360 | unsigned int constant; | |
1361 | CORE_ADDR loc; | |
1362 | ||
cac395ea | 1363 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1364 | if (insn & 0x0080) |
1365 | loc = start + 4 + offset; | |
1366 | else | |
1367 | loc = start + 4 - offset; | |
1368 | ||
1369 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1370 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1371 | ||
1372 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1373 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1374 | } | |
a01567f4 LM |
1375 | /* Start of ARMv8.1-m PACBTI extension instructions. */ |
1376 | else if (IS_PAC (whole_insn)) | |
1377 | { | |
1378 | /* LR and SP are input registers. PAC is in R12. LR is | |
1379 | signed from this point onwards. NOP space. */ | |
1380 | ra_signed_state = true; | |
1381 | } | |
1382 | else if (IS_PACBTI (whole_insn)) | |
1383 | { | |
1384 | /* LR and SP are input registers. PAC is in R12 and PC is a | |
1385 | valid BTI landing pad. LR is signed from this point onwards. | |
1386 | NOP space. */ | |
1387 | ra_signed_state = true; | |
1388 | } | |
1389 | else if (IS_BTI (whole_insn)) | |
1390 | { | |
1391 | /* Valid BTI landing pad. NOP space. */ | |
1392 | } | |
1393 | else if (IS_PACG (whole_insn)) | |
1394 | { | |
1395 | /* Sign Rn using Rm and store the PAC in Rd. Rd is signed from | |
1396 | this point onwards. */ | |
1397 | ra_signed_state = true; | |
1398 | } | |
1399 | else if (IS_AUT (whole_insn) || IS_AUTG (whole_insn)) | |
1400 | { | |
1401 | /* These instructions appear close to the epilogue, when signed | |
1402 | pointers are getting authenticated. */ | |
1403 | ra_signed_state = false; | |
1404 | } | |
1405 | /* End of ARMv8.1-m PACBTI extension instructions */ | |
ec3d575a UW |
1406 | else if (thumb2_instruction_changes_pc (insn, inst2)) |
1407 | { | |
1408 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1409 | break; |
1410 | } | |
ec3d575a UW |
1411 | else |
1412 | { | |
1413 | /* The optimizer might shove anything into the prologue, | |
1414 | so we just skip what we don't recognize. */ | |
1415 | unrecognized_pc = start; | |
1416 | } | |
0d39a070 | 1417 | |
a01567f4 LM |
1418 | /* Make sure we are dealing with a target that supports ARMv8.1-m |
1419 | PACBTI. */ | |
1420 | if (cache != nullptr && tdep->have_pacbti | |
1421 | && ra_signed_state.has_value ()) | |
1422 | { | |
1423 | arm_debug_printf ("Found pacbti instruction at %s", | |
1424 | paddress (gdbarch, start)); | |
1425 | arm_debug_printf ("RA is %s", | |
1426 | *ra_signed_state? "signed" : "not signed"); | |
1427 | cache->ra_signed_state = ra_signed_state; | |
1428 | } | |
1429 | ||
0d39a070 DJ |
1430 | start += 2; |
1431 | } | |
ec3d575a | 1432 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1433 | { |
ec3d575a | 1434 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1435 | break; |
3d74b771 | 1436 | } |
ec3d575a UW |
1437 | else |
1438 | { | |
1439 | /* The optimizer might shove anything into the prologue, | |
1440 | so we just skip what we don't recognize. */ | |
1441 | unrecognized_pc = start; | |
1442 | } | |
29d73ae4 DJ |
1443 | |
1444 | start += 2; | |
c906108c SS |
1445 | } |
1446 | ||
7cb6d92a SM |
1447 | arm_debug_printf ("Prologue scan stopped at %s", |
1448 | paddress (gdbarch, start)); | |
0d39a070 | 1449 | |
ec3d575a UW |
1450 | if (unrecognized_pc == 0) |
1451 | unrecognized_pc = start; | |
1452 | ||
29d73ae4 | 1453 | if (cache == NULL) |
f7b7ed97 | 1454 | return unrecognized_pc; |
29d73ae4 | 1455 | |
29d73ae4 DJ |
1456 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1457 | { | |
1458 | /* Frame pointer is fp. Frame size is constant. */ | |
1459 | cache->framereg = ARM_FP_REGNUM; | |
1460 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1461 | } | |
1462 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1463 | { | |
1464 | /* Frame pointer is r7. Frame size is constant. */ | |
1465 | cache->framereg = THUMB_FP_REGNUM; | |
1466 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1467 | } | |
72a2e3dc | 1468 | else |
29d73ae4 DJ |
1469 | { |
1470 | /* Try the stack pointer... this is a bit desperate. */ | |
1471 | cache->framereg = ARM_SP_REGNUM; | |
1472 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1473 | } | |
29d73ae4 | 1474 | |
de76473c | 1475 | for (i = 0; i < gdbarch_num_regs (gdbarch); i++) |
f7b7ed97 | 1476 | if (stack.find_reg (gdbarch, i, &offset)) |
10245fe8 YR |
1477 | { |
1478 | cache->saved_regs[i].set_addr (offset); | |
1479 | if (i == ARM_SP_REGNUM) | |
1480 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
1481 | } | |
29d73ae4 | 1482 | |
ec3d575a | 1483 | return unrecognized_pc; |
c906108c SS |
1484 | } |
1485 | ||
621c6d5b YQ |
1486 | |
1487 | /* Try to analyze the instructions starting from PC, which load symbol | |
1488 | __stack_chk_guard. Return the address of instruction after loading this | |
1489 | symbol, set the dest register number to *BASEREG, and set the size of | |
1490 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1491 | not recognized. */ | |
1492 | ||
1493 | static CORE_ADDR | |
1494 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1495 | unsigned int *destreg, int *offset) | |
1496 | { | |
1497 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1498 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1499 | unsigned int low, high, address; | |
1500 | ||
1501 | address = 0; | |
1502 | if (is_thumb) | |
1503 | { | |
1504 | unsigned short insn1 | |
198cd59d | 1505 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1506 | |
1507 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1508 | { | |
1509 | *destreg = bits (insn1, 8, 10); | |
1510 | *offset = 2; | |
6ae274b7 YQ |
1511 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1512 | address = read_memory_unsigned_integer (address, 4, | |
1513 | byte_order_for_code); | |
621c6d5b YQ |
1514 | } |
1515 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1516 | { | |
1517 | unsigned short insn2 | |
198cd59d | 1518 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1519 | |
1520 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1521 | ||
1522 | insn1 | |
198cd59d | 1523 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1524 | insn2 |
198cd59d | 1525 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1526 | |
1527 | /* movt Rd, #const */ | |
1528 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1529 | { | |
1530 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1531 | *destreg = bits (insn2, 8, 11); | |
1532 | *offset = 8; | |
1533 | address = (high << 16 | low); | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | else | |
1538 | { | |
2e9e421f | 1539 | unsigned int insn |
198cd59d | 1540 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1541 | |
6ae274b7 | 1542 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1543 | { |
6ae274b7 YQ |
1544 | address = bits (insn, 0, 11) + pc + 8; |
1545 | address = read_memory_unsigned_integer (address, 4, | |
1546 | byte_order_for_code); | |
1547 | ||
2e9e421f UW |
1548 | *destreg = bits (insn, 12, 15); |
1549 | *offset = 4; | |
1550 | } | |
1551 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1552 | { | |
1553 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1554 | ||
1555 | insn | |
198cd59d | 1556 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1557 | |
1558 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1559 | { | |
1560 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1561 | *destreg = bits (insn, 12, 15); | |
1562 | *offset = 8; | |
1563 | address = (high << 16 | low); | |
1564 | } | |
1565 | } | |
621c6d5b YQ |
1566 | } |
1567 | ||
1568 | return address; | |
1569 | } | |
1570 | ||
1571 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1572 | points to the first instruction of this sequence, return the address of |
1573 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1574 | |
1575 | On arm, this sequence of instructions is composed of mainly three steps, | |
1576 | Step 1: load symbol __stack_chk_guard, | |
1577 | Step 2: load from address of __stack_chk_guard, | |
1578 | Step 3: store it to somewhere else. | |
1579 | ||
1580 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1581 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1582 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1583 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1584 | they are, | |
1585 | ||
1586 | movw Rn, #:lower16:__stack_chk_guard | |
1587 | movt Rn, #:upper16:__stack_chk_guard | |
1588 | ||
1589 | On ARMv5t, it is, | |
1590 | ||
1591 | ldr Rn, .Label | |
1592 | .... | |
1593 | .Lable: | |
1594 | .word __stack_chk_guard | |
1595 | ||
1596 | Since ldr/str is a very popular instruction, we can't use them as | |
1597 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1598 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1599 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1600 | ||
1601 | static CORE_ADDR | |
1602 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1603 | { | |
1604 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1605 | unsigned int basereg; |
7cbd4a93 | 1606 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1607 | int offset; |
1608 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1609 | CORE_ADDR addr; | |
1610 | ||
1611 | /* Try to parse the instructions in Step 1. */ | |
1612 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1613 | &basereg, &offset); | |
1614 | if (!addr) | |
1615 | return pc; | |
1616 | ||
1617 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1618 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1619 | Otherwise, this sequence cannot be for stack protector. */ | |
1620 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1621 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1622 | return pc; |
1623 | ||
1624 | if (is_thumb) | |
1625 | { | |
1626 | unsigned int destreg; | |
1627 | unsigned short insn | |
198cd59d | 1628 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1629 | |
1630 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1631 | if ((insn & 0xf800) != 0x6800) | |
1632 | return pc; | |
1633 | if (bits (insn, 3, 5) != basereg) | |
1634 | return pc; | |
1635 | destreg = bits (insn, 0, 2); | |
1636 | ||
198cd59d YQ |
1637 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1638 | byte_order_for_code); | |
621c6d5b YQ |
1639 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1640 | if ((insn & 0xf800) != 0x6000) | |
1641 | return pc; | |
1642 | if (destreg != bits (insn, 0, 2)) | |
1643 | return pc; | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | unsigned int destreg; | |
1648 | unsigned int insn | |
198cd59d | 1649 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1650 | |
1651 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1652 | if ((insn & 0x0e500000) != 0x04100000) | |
1653 | return pc; | |
1654 | if (bits (insn, 16, 19) != basereg) | |
1655 | return pc; | |
1656 | destreg = bits (insn, 12, 15); | |
1657 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1658 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1659 | 4, byte_order_for_code); |
1660 | if ((insn & 0x0e500000) != 0x04000000) | |
1661 | return pc; | |
1662 | if (bits (insn, 12, 15) != destreg) | |
1663 | return pc; | |
1664 | } | |
1665 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1666 | on arm. */ | |
1667 | if (is_thumb) | |
1668 | return pc + offset + 4; | |
1669 | else | |
1670 | return pc + offset + 8; | |
1671 | } | |
1672 | ||
da3c6d4a MS |
1673 | /* Advance the PC across any function entry prologue instructions to |
1674 | reach some "real" code. | |
34e8f22d RE |
1675 | |
1676 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1677 | prologue: |
c906108c | 1678 | |
c5aa993b JM |
1679 | mov ip, sp |
1680 | [stmfd sp!, {a1,a2,a3,a4}] | |
1681 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1682 | [stfe f7, [sp, #-12]!] |
1683 | [stfe f6, [sp, #-12]!] | |
1684 | [stfe f5, [sp, #-12]!] | |
1685 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1686 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1687 | |
34e8f22d | 1688 | static CORE_ADDR |
6093d2eb | 1689 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1690 | { |
a89fea3c | 1691 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1692 | |
a89fea3c JL |
1693 | /* See if we can determine the end of the prologue via the symbol table. |
1694 | If so, then return either PC, or the PC after the prologue, whichever | |
1695 | is greater. */ | |
1696 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1697 | { |
d80b854b UW |
1698 | CORE_ADDR post_prologue_pc |
1699 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1700 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1701 | |
621c6d5b YQ |
1702 | if (post_prologue_pc) |
1703 | post_prologue_pc | |
1704 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1705 | ||
1706 | ||
0d39a070 DJ |
1707 | /* GCC always emits a line note before the prologue and another |
1708 | one after, even if the two are at the same address or on the | |
1709 | same line. Take advantage of this so that we do not need to | |
1710 | know every instruction that might appear in the prologue. We | |
1711 | will have producer information for most binaries; if it is | |
1712 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1713 | if (post_prologue_pc | |
43f3e411 | 1714 | && (cust == NULL |
ab5f850e SM |
1715 | || cust->producer () == NULL |
1716 | || startswith (cust->producer (), "GNU ") | |
1717 | || producer_is_llvm (cust->producer ()))) | |
0d39a070 DJ |
1718 | return post_prologue_pc; |
1719 | ||
a89fea3c | 1720 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1721 | { |
1722 | CORE_ADDR analyzed_limit; | |
1723 | ||
1724 | /* For non-GCC compilers, make sure the entire line is an | |
1725 | acceptable prologue; GDB will round this function's | |
1726 | return value up to the end of the following line so we | |
1727 | can not skip just part of a line (and we do not want to). | |
1728 | ||
1729 | RealView does not treat the prologue specially, but does | |
1730 | associate prologue code with the opening brace; so this | |
1731 | lets us skip the first line if we think it is the opening | |
1732 | brace. */ | |
9779414d | 1733 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1734 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1735 | post_prologue_pc, NULL); | |
1736 | else | |
9ecab40c SM |
1737 | analyzed_limit |
1738 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1739 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1740 | |
1741 | if (analyzed_limit != post_prologue_pc) | |
1742 | return func_addr; | |
1743 | ||
1744 | return post_prologue_pc; | |
1745 | } | |
c906108c SS |
1746 | } |
1747 | ||
a89fea3c JL |
1748 | /* Can't determine prologue from the symbol table, need to examine |
1749 | instructions. */ | |
c906108c | 1750 | |
a89fea3c JL |
1751 | /* Find an upper limit on the function prologue using the debug |
1752 | information. If the debug information could not be used to provide | |
1753 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1754 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1755 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1756 | if (limit_pc == 0) |
1757 | limit_pc = pc + 64; /* Magic. */ | |
1758 | ||
c906108c | 1759 | |
29d73ae4 | 1760 | /* Check if this is Thumb code. */ |
9779414d | 1761 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1762 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1763 | else |
9ecab40c SM |
1764 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1765 | target_arm_instruction_reader ()); | |
c906108c | 1766 | } |
94c30b78 | 1767 | |
c5aa993b | 1768 | /* *INDENT-OFF* */ |
c906108c SS |
1769 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1770 | This function decodes a Thumb function prologue to determine: | |
1771 | 1) the size of the stack frame | |
1772 | 2) which registers are saved on it | |
1773 | 3) the offsets of saved regs | |
1774 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1775 | |
da59e081 JM |
1776 | A typical Thumb function prologue would create this stack frame |
1777 | (offsets relative to FP) | |
c906108c SS |
1778 | old SP -> 24 stack parameters |
1779 | 20 LR | |
1780 | 16 R7 | |
1781 | R7 -> 0 local variables (16 bytes) | |
1782 | SP -> -12 additional stack space (12 bytes) | |
1783 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1784 | 12 bytes. The frame register is R7. |
da59e081 | 1785 | |
da3c6d4a MS |
1786 | The comments for thumb_skip_prolog() describe the algorithm we use |
1787 | to detect the end of the prolog. */ | |
c5aa993b JM |
1788 | /* *INDENT-ON* */ |
1789 | ||
c906108c | 1790 | static void |
be8626e0 | 1791 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1792 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1793 | { |
1794 | CORE_ADDR prologue_start; | |
1795 | CORE_ADDR prologue_end; | |
c906108c | 1796 | |
b39cc962 DJ |
1797 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1798 | &prologue_end)) | |
c906108c | 1799 | { |
ec3d575a UW |
1800 | /* See comment in arm_scan_prologue for an explanation of |
1801 | this heuristics. */ | |
1802 | if (prologue_end > prologue_start + 64) | |
1803 | { | |
1804 | prologue_end = prologue_start + 64; | |
1805 | } | |
c906108c SS |
1806 | } |
1807 | else | |
f7060f85 DJ |
1808 | /* We're in the boondocks: we have no idea where the start of the |
1809 | function is. */ | |
1810 | return; | |
c906108c | 1811 | |
325fac50 | 1812 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1813 | |
be8626e0 | 1814 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1815 | } |
1816 | ||
f303bc3e YQ |
1817 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1818 | otherwise. */ | |
1819 | ||
1820 | static int | |
1821 | arm_instruction_restores_sp (unsigned int insn) | |
1822 | { | |
1823 | if (bits (insn, 28, 31) != INST_NV) | |
1824 | { | |
1825 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1826 | /* ADD SP (register or immediate). */ | |
1827 | || (insn & 0x0df0f000) == 0x0040d000 | |
1828 | /* SUB SP (register or immediate). */ | |
1829 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1830 | /* MOV SP. */ | |
1831 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1832 | /* POP (LDMIA). */ | |
1833 | || (insn & 0x0fff0000) == 0x049d0000) | |
1834 | /* POP of a single register. */ | |
1835 | return 1; | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
9ecab40c SM |
1841 | /* Implement immediate value decoding, as described in section A5.2.4 |
1842 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1843 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1844 | ||
1845 | static uint32_t | |
1846 | arm_expand_immediate (uint32_t imm) | |
1847 | { | |
1848 | /* Immediate values are 12 bits long. */ | |
1849 | gdb_assert ((imm & 0xfffff000) == 0); | |
1850 | ||
1851 | uint32_t unrotated_value = imm & 0xff; | |
1852 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1853 | ||
1854 | if (rotate_amount == 0) | |
1855 | return unrotated_value; | |
1856 | ||
1857 | return ((unrotated_value >> rotate_amount) | |
1858 | | (unrotated_value << (32 - rotate_amount))); | |
1859 | } | |
1860 | ||
0d39a070 DJ |
1861 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1862 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1863 | fill it in. Return the first address not recognized as a prologue | |
1864 | instruction. | |
eb5492fa | 1865 | |
0d39a070 DJ |
1866 | We recognize all the instructions typically found in ARM prologues, |
1867 | plus harmless instructions which can be skipped (either for analysis | |
1868 | purposes, or a more restrictive set that can be skipped when finding | |
1869 | the end of the prologue). */ | |
1870 | ||
1871 | static CORE_ADDR | |
1872 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1873 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1874 | struct arm_prologue_cache *cache, |
1875 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1876 | { |
0d39a070 DJ |
1877 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1878 | int regno; | |
1879 | CORE_ADDR offset, current_pc; | |
1880 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 | 1881 | CORE_ADDR unrecognized_pc = 0; |
08106042 | 1882 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
1883 | |
1884 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1885 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1886 | |
96baa820 JM |
1887 | Be careful, however, and if it doesn't look like a prologue, |
1888 | don't try to scan it. If, for instance, a frameless function | |
1889 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1890 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1891 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1892 | traceback. */ |
d4473757 | 1893 | |
4be43953 DJ |
1894 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1895 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1896 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1897 | |
94c30b78 MS |
1898 | for (current_pc = prologue_start; |
1899 | current_pc < prologue_end; | |
f43845b3 | 1900 | current_pc += 4) |
96baa820 | 1901 | { |
9ecab40c | 1902 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1903 | |
94c30b78 | 1904 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1905 | { |
4be43953 | 1906 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1907 | continue; |
1908 | } | |
0d39a070 DJ |
1909 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1910 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1911 | { |
9ecab40c | 1912 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1913 | int rd = bits (insn, 12, 15); |
0d39a070 | 1914 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1915 | continue; |
1916 | } | |
0d39a070 DJ |
1917 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1918 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1919 | { |
9ecab40c | 1920 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1921 | int rd = bits (insn, 12, 15); |
0d39a070 | 1922 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1923 | continue; |
1924 | } | |
0963b4bd MS |
1925 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1926 | [sp, #-4]! */ | |
f43845b3 | 1927 | { |
f7b7ed97 | 1928 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1929 | break; |
1930 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
1931 | stack.store (regs[ARM_SP_REGNUM], 4, |
1932 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1933 | continue; |
1934 | } | |
1935 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1936 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1937 | or | |
1938 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1939 | { |
d4473757 | 1940 | int mask = insn & 0xffff; |
ed9a39eb | 1941 | |
f7b7ed97 | 1942 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1943 | break; |
1944 | ||
94c30b78 | 1945 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1946 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1947 | if (mask & (1 << regno)) |
1948 | { | |
0963b4bd MS |
1949 | regs[ARM_SP_REGNUM] |
1950 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 1951 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1952 | } |
1953 | } | |
0d39a070 DJ |
1954 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1955 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1956 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1957 | { |
1958 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1959 | continue; | |
1960 | } | |
0d39a070 DJ |
1961 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1962 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1963 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1964 | { |
1965 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1966 | continue; | |
1967 | } | |
0963b4bd MS |
1968 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1969 | { registers } */ | |
0d39a070 DJ |
1970 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1971 | { | |
1972 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1973 | continue; | |
1974 | } | |
d4473757 KB |
1975 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1976 | { | |
9ecab40c | 1977 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 1978 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1979 | } |
1980 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1981 | { | |
9ecab40c | 1982 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 1983 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1984 | } |
0963b4bd MS |
1985 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1986 | [sp, -#c]! */ | |
345bd07c | 1987 | && tdep->have_fpa_registers) |
d4473757 | 1988 | { |
f7b7ed97 | 1989 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1990 | break; |
1991 | ||
1992 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1993 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 1994 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1995 | } |
0963b4bd MS |
1996 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1997 | [sp!] */ | |
345bd07c | 1998 | && tdep->have_fpa_registers) |
d4473757 KB |
1999 | { |
2000 | int n_saved_fp_regs; | |
2001 | unsigned int fp_start_reg, fp_bound_reg; | |
2002 | ||
f7b7ed97 | 2003 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2004 | break; |
2005 | ||
94c30b78 | 2006 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 2007 | { |
d4473757 KB |
2008 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2009 | n_saved_fp_regs = 3; | |
2010 | else | |
2011 | n_saved_fp_regs = 1; | |
96baa820 | 2012 | } |
d4473757 | 2013 | else |
96baa820 | 2014 | { |
d4473757 KB |
2015 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2016 | n_saved_fp_regs = 2; | |
2017 | else | |
2018 | n_saved_fp_regs = 4; | |
96baa820 | 2019 | } |
d4473757 | 2020 | |
34e8f22d | 2021 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
2022 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
2023 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 2024 | { |
4be43953 | 2025 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
2026 | stack.store (regs[ARM_SP_REGNUM], 12, |
2027 | regs[fp_start_reg++]); | |
96baa820 | 2028 | } |
c906108c | 2029 | } |
0d39a070 DJ |
2030 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
2031 | { | |
2032 | /* Allow some special function calls when skipping the | |
2033 | prologue; GCC generates these before storing arguments to | |
2034 | the stack. */ | |
2035 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
2036 | ||
e0634ccf | 2037 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
2038 | continue; |
2039 | else | |
2040 | break; | |
2041 | } | |
d4473757 | 2042 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 2043 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
2044 | else if (arm_instruction_changes_pc (insn)) |
2045 | /* Don't scan past anything that might change control flow. */ | |
2046 | break; | |
f303bc3e YQ |
2047 | else if (arm_instruction_restores_sp (insn)) |
2048 | { | |
2049 | /* Don't scan past the epilogue. */ | |
2050 | break; | |
2051 | } | |
d19f7eee UW |
2052 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
2053 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2054 | /* Ignore block loads from the stack, potentially copying | |
2055 | parameters from memory. */ | |
2056 | continue; | |
2057 | else if ((insn & 0xfc500000) == 0xe4100000 | |
2058 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2059 | /* Similarly ignore single loads from the stack. */ | |
2060 | continue; | |
0d39a070 DJ |
2061 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
2062 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
2063 | register instead of the stack. */ | |
d4473757 | 2064 | continue; |
0d39a070 DJ |
2065 | else |
2066 | { | |
21daaaaf YQ |
2067 | /* The optimizer might shove anything into the prologue, if |
2068 | we build up cache (cache != NULL) from scanning prologue, | |
2069 | we just skip what we don't recognize and scan further to | |
2070 | make cache as complete as possible. However, if we skip | |
2071 | prologue, we'll stop immediately on unrecognized | |
2072 | instruction. */ | |
0d39a070 | 2073 | unrecognized_pc = current_pc; |
21daaaaf YQ |
2074 | if (cache != NULL) |
2075 | continue; | |
2076 | else | |
2077 | break; | |
0d39a070 | 2078 | } |
c906108c SS |
2079 | } |
2080 | ||
0d39a070 DJ |
2081 | if (unrecognized_pc == 0) |
2082 | unrecognized_pc = current_pc; | |
2083 | ||
0d39a070 DJ |
2084 | if (cache) |
2085 | { | |
4072f920 YQ |
2086 | int framereg, framesize; |
2087 | ||
2088 | /* The frame size is just the distance from the frame register | |
2089 | to the original stack pointer. */ | |
2090 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
2091 | { | |
2092 | /* Frame pointer is fp. */ | |
2093 | framereg = ARM_FP_REGNUM; | |
2094 | framesize = -regs[ARM_FP_REGNUM].k; | |
2095 | } | |
2096 | else | |
2097 | { | |
2098 | /* Try the stack pointer... this is a bit desperate. */ | |
2099 | framereg = ARM_SP_REGNUM; | |
2100 | framesize = -regs[ARM_SP_REGNUM].k; | |
2101 | } | |
2102 | ||
0d39a070 DJ |
2103 | cache->framereg = framereg; |
2104 | cache->framesize = framesize; | |
2105 | ||
2106 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 2107 | if (stack.find_reg (gdbarch, regno, &offset)) |
10245fe8 YR |
2108 | { |
2109 | cache->saved_regs[regno].set_addr (offset); | |
2110 | if (regno == ARM_SP_REGNUM) | |
2111 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
2112 | } | |
0d39a070 DJ |
2113 | } |
2114 | ||
7cb6d92a SM |
2115 | arm_debug_printf ("Prologue scan stopped at %s", |
2116 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 2117 | |
0d39a070 DJ |
2118 | return unrecognized_pc; |
2119 | } | |
2120 | ||
2121 | static void | |
bd2b40ac | 2122 | arm_scan_prologue (frame_info_ptr this_frame, |
0d39a070 DJ |
2123 | struct arm_prologue_cache *cache) |
2124 | { | |
2125 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2126 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 2127 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
2128 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
2129 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
08106042 | 2130 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
2131 | |
2132 | /* Assume there is no frame until proven otherwise. */ | |
2133 | cache->framereg = ARM_SP_REGNUM; | |
2134 | cache->framesize = 0; | |
2135 | ||
2136 | /* Check for Thumb prologue. */ | |
2137 | if (arm_frame_is_thumb (this_frame)) | |
2138 | { | |
2139 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
2140 | return; | |
2141 | } | |
2142 | ||
2143 | /* Find the function prologue. If we can't find the function in | |
2144 | the symbol table, peek in the stack frame to find the PC. */ | |
2145 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
2146 | &prologue_end)) | |
2147 | { | |
2148 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 2149 | for unoptimized code) is to do the following: |
0d39a070 DJ |
2150 | |
2151 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
2152 | ||
2153 | if (sal.line == 0) | |
2154 | prologue_end = prev_pc; | |
2155 | else if (sal.end < prologue_end) | |
2156 | prologue_end = sal.end; | |
2157 | ||
2158 | This mechanism is very accurate so long as the optimizer | |
2159 | doesn't move any instructions from the function body into the | |
2160 | prologue. If this happens, sal.end will be the last | |
2161 | instruction in the first hunk of prologue code just before | |
2162 | the first instruction that the scheduler has moved from | |
2163 | the body to the prologue. | |
2164 | ||
2165 | In order to make sure that we scan all of the prologue | |
2166 | instructions, we use a slightly less accurate mechanism which | |
2167 | may scan more than necessary. To help compensate for this | |
2168 | lack of accuracy, the prologue scanning loop below contains | |
2169 | several clauses which'll cause the loop to terminate early if | |
2170 | an implausible prologue instruction is encountered. | |
2171 | ||
2172 | The expression | |
2173 | ||
2174 | prologue_start + 64 | |
2175 | ||
2176 | is a suitable endpoint since it accounts for the largest | |
2177 | possible prologue plus up to five instructions inserted by | |
2178 | the scheduler. */ | |
2179 | ||
2180 | if (prologue_end > prologue_start + 64) | |
2181 | { | |
2182 | prologue_end = prologue_start + 64; /* See above. */ | |
2183 | } | |
2184 | } | |
2185 | else | |
2186 | { | |
2187 | /* We have no symbol information. Our only option is to assume this | |
2188 | function has a standard stack frame and the normal frame register. | |
2189 | Then, we can find the value of our frame pointer on entrance to | |
2190 | the callee (or at the present moment if this is the innermost frame). | |
2191 | The value stored there should be the address of the stmfd + 8. */ | |
2192 | CORE_ADDR frame_loc; | |
7913a64c | 2193 | ULONGEST return_value; |
0d39a070 | 2194 | |
9e237747 | 2195 | /* AAPCS does not use a frame register, so we can abort here. */ |
345bd07c | 2196 | if (tdep->arm_abi == ARM_ABI_AAPCS) |
dda83cd7 | 2197 | return; |
9e237747 | 2198 | |
0d39a070 | 2199 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
2200 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
2201 | &return_value)) | |
dda83cd7 | 2202 | return; |
0d39a070 | 2203 | else |
dda83cd7 SM |
2204 | { |
2205 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 2206 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
2207 | prologue_end = prologue_start + 64; /* See above. */ |
2208 | } | |
0d39a070 DJ |
2209 | } |
2210 | ||
2211 | if (prev_pc < prologue_end) | |
2212 | prologue_end = prev_pc; | |
2213 | ||
9ecab40c SM |
2214 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
2215 | target_arm_instruction_reader ()); | |
c906108c SS |
2216 | } |
2217 | ||
eb5492fa | 2218 | static struct arm_prologue_cache * |
bd2b40ac | 2219 | arm_make_prologue_cache (frame_info_ptr this_frame) |
c906108c | 2220 | { |
eb5492fa DJ |
2221 | int reg; |
2222 | struct arm_prologue_cache *cache; | |
1ef3351b | 2223 | CORE_ADDR unwound_fp, prev_sp; |
c5aa993b | 2224 | |
35d5d4ee | 2225 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 2226 | arm_cache_init (cache, this_frame); |
c906108c | 2227 | |
a262aec2 | 2228 | arm_scan_prologue (this_frame, cache); |
848cfffb | 2229 | |
a262aec2 | 2230 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
2231 | if (unwound_fp == 0) |
2232 | return cache; | |
c906108c | 2233 | |
ae7e2f45 | 2234 | arm_gdbarch_tdep *tdep = |
08106042 | 2235 | gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2236 | |
1ef3351b YR |
2237 | prev_sp = unwound_fp + cache->framesize; |
2238 | arm_cache_set_active_sp_value (cache, tdep, prev_sp); | |
c906108c | 2239 | |
eb5492fa DJ |
2240 | /* Calculate actual addresses of saved registers using offsets |
2241 | determined by arm_scan_prologue. */ | |
a262aec2 | 2242 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
a9a87d35 | 2243 | if (cache->saved_regs[reg].is_addr ()) |
1ef3351b YR |
2244 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () + |
2245 | prev_sp); | |
eb5492fa DJ |
2246 | |
2247 | return cache; | |
c906108c SS |
2248 | } |
2249 | ||
c1ee9414 LM |
2250 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
2251 | ||
2252 | static enum unwind_stop_reason | |
bd2b40ac | 2253 | arm_prologue_unwind_stop_reason (frame_info_ptr this_frame, |
c1ee9414 LM |
2254 | void **this_cache) |
2255 | { | |
2256 | struct arm_prologue_cache *cache; | |
2257 | CORE_ADDR pc; | |
2258 | ||
2259 | if (*this_cache == NULL) | |
2260 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 2261 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
2262 | |
2263 | /* This is meant to halt the backtrace at "_start". */ | |
2264 | pc = get_frame_pc (this_frame); | |
345bd07c | 2265 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 2266 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (arch); |
345bd07c | 2267 | if (pc <= tdep->lowest_pc) |
c1ee9414 LM |
2268 | return UNWIND_OUTERMOST; |
2269 | ||
2270 | /* If we've hit a wall, stop. */ | |
ae7e2f45 | 2271 | if (arm_cache_get_prev_sp_value (cache, tdep) == 0) |
c1ee9414 LM |
2272 | return UNWIND_OUTERMOST; |
2273 | ||
2274 | return UNWIND_NO_REASON; | |
2275 | } | |
2276 | ||
eb5492fa DJ |
2277 | /* Our frame ID for a normal frame is the current function's starting PC |
2278 | and the caller's SP when we were called. */ | |
c906108c | 2279 | |
148754e5 | 2280 | static void |
bd2b40ac | 2281 | arm_prologue_this_id (frame_info_ptr this_frame, |
eb5492fa DJ |
2282 | void **this_cache, |
2283 | struct frame_id *this_id) | |
c906108c | 2284 | { |
eb5492fa DJ |
2285 | struct arm_prologue_cache *cache; |
2286 | struct frame_id id; | |
2c404490 | 2287 | CORE_ADDR pc, func; |
f079148d | 2288 | |
eb5492fa | 2289 | if (*this_cache == NULL) |
a262aec2 | 2290 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2291 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 2292 | |
ae7e2f45 | 2293 | arm_gdbarch_tdep *tdep |
08106042 | 2294 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2295 | |
0e9e9abd UW |
2296 | /* Use function start address as part of the frame ID. If we cannot |
2297 | identify the start address (due to missing symbol information), | |
2298 | fall back to just using the current PC. */ | |
c1ee9414 | 2299 | pc = get_frame_pc (this_frame); |
2c404490 | 2300 | func = get_frame_func (this_frame); |
0e9e9abd UW |
2301 | if (!func) |
2302 | func = pc; | |
2303 | ||
ae7e2f45 | 2304 | id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), func); |
eb5492fa | 2305 | *this_id = id; |
c906108c SS |
2306 | } |
2307 | ||
a262aec2 | 2308 | static struct value * |
bd2b40ac | 2309 | arm_prologue_prev_register (frame_info_ptr this_frame, |
eb5492fa | 2310 | void **this_cache, |
a262aec2 | 2311 | int prev_regnum) |
24de872b | 2312 | { |
24568a2c | 2313 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b | 2314 | struct arm_prologue_cache *cache; |
ef273377 | 2315 | CORE_ADDR sp_value; |
24de872b | 2316 | |
eb5492fa | 2317 | if (*this_cache == NULL) |
a262aec2 | 2318 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2319 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 2320 | |
08106042 | 2321 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
2322 | |
2323 | /* If this frame has signed the return address, mark it as so. */ | |
2324 | if (tdep->have_pacbti && cache->ra_signed_state.has_value () | |
2325 | && *cache->ra_signed_state) | |
2326 | set_frame_previous_pc_masked (this_frame); | |
2327 | ||
eb5492fa | 2328 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
2329 | instead. The prologue may save PC, but it will point into this |
2330 | frame's prologue, not the next frame's resume location. Also | |
2331 | strip the saved T bit. A valid LR may have the low bit set, but | |
2332 | a valid PC never does. */ | |
eb5492fa | 2333 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
2334 | { |
2335 | CORE_ADDR lr; | |
2336 | ||
2337 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2338 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 2339 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 2340 | } |
24de872b | 2341 | |
eb5492fa | 2342 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 2343 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2344 | The value was already reconstructed into PREV_SP. */ |
2345 | if (prev_regnum == ARM_SP_REGNUM) | |
ae7e2f45 CL |
2346 | return frame_unwind_got_constant (this_frame, prev_regnum, |
2347 | arm_cache_get_prev_sp_value (cache, tdep)); | |
eb5492fa | 2348 | |
ef273377 CL |
2349 | /* The value might be one of the alternative SP, if so, use the |
2350 | value already constructed. */ | |
d65edaa0 | 2351 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
2352 | { |
2353 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
2354 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
2355 | } | |
2356 | ||
b39cc962 DJ |
2357 | /* The CPSR may have been changed by the call instruction and by the |
2358 | called function. The only bit we can reconstruct is the T bit, | |
2359 | by checking the low bit of LR as of the call. This is a reliable | |
2360 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2361 | Thumb code, which could get away with a clear low bit as long as | |
2362 | the called function did not use bx. Guess that all other | |
2363 | bits are unchanged; the condition flags are presumably lost, | |
2364 | but the processor status is likely valid. */ | |
2365 | if (prev_regnum == ARM_PS_REGNUM) | |
2366 | { | |
8c9ae6df YR |
2367 | ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum); |
2368 | CORE_ADDR lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
b39cc962 | 2369 | |
8c9ae6df | 2370 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
b39cc962 DJ |
2371 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2372 | } | |
2373 | ||
a262aec2 DJ |
2374 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2375 | prev_regnum); | |
eb5492fa DJ |
2376 | } |
2377 | ||
6bd434d6 | 2378 | static frame_unwind arm_prologue_unwind = { |
a154d838 | 2379 | "arm prologue", |
eb5492fa | 2380 | NORMAL_FRAME, |
c1ee9414 | 2381 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2382 | arm_prologue_this_id, |
a262aec2 DJ |
2383 | arm_prologue_prev_register, |
2384 | NULL, | |
2385 | default_frame_sniffer | |
eb5492fa DJ |
2386 | }; |
2387 | ||
0e9e9abd UW |
2388 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2389 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2390 | personality routines; the cache will contain only the frame unwinding | |
2391 | instructions associated with the entry (not the descriptors). */ | |
2392 | ||
0e9e9abd UW |
2393 | struct arm_exidx_entry |
2394 | { | |
227031b2 | 2395 | CORE_ADDR addr; |
0e9e9abd | 2396 | gdb_byte *entry; |
7a5d944b TT |
2397 | |
2398 | bool operator< (const arm_exidx_entry &other) const | |
2399 | { | |
2400 | return addr < other.addr; | |
2401 | } | |
0e9e9abd | 2402 | }; |
0e9e9abd UW |
2403 | |
2404 | struct arm_exidx_data | |
2405 | { | |
7a5d944b | 2406 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2407 | }; |
2408 | ||
a2726d4f | 2409 | /* Per-BFD key to store exception handling information. */ |
08b8a139 | 2410 | static const registry<bfd>::key<arm_exidx_data> arm_exidx_data_key; |
0e9e9abd UW |
2411 | |
2412 | static struct obj_section * | |
2413 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2414 | { | |
2415 | struct obj_section *osect; | |
2416 | ||
2417 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2418 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2419 | { |
2420 | bfd_vma start, size; | |
fd361982 AM |
2421 | start = bfd_section_vma (osect->the_bfd_section); |
2422 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2423 | |
2424 | if (start <= vma && vma < start + size) | |
2425 | return osect; | |
2426 | } | |
2427 | ||
2428 | return NULL; | |
2429 | } | |
2430 | ||
2431 | /* Parse contents of exception table and exception index sections | |
2432 | of OBJFILE, and fill in the exception table entry cache. | |
2433 | ||
2434 | For each entry that refers to a standard ARM-defined personality | |
2435 | routine, extract the frame unwinding instructions (from either | |
2436 | the index or the table section). The unwinding instructions | |
2437 | are normalized by: | |
2438 | - extracting them from the rest of the table data | |
2439 | - converting to host endianness | |
2440 | - appending the implicit 0xb0 ("Finish") code | |
2441 | ||
2442 | The extracted and normalized instructions are stored for later | |
2443 | retrieval by the arm_find_exidx_entry routine. */ | |
2444 | ||
2445 | static void | |
2446 | arm_exidx_new_objfile (struct objfile *objfile) | |
2447 | { | |
0e9e9abd UW |
2448 | struct arm_exidx_data *data; |
2449 | asection *exidx, *extab; | |
2450 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2451 | LONGEST i; |
2452 | ||
2453 | /* If we've already touched this file, do nothing. */ | |
98badbfd | 2454 | if (!objfile || arm_exidx_data_key.get (objfile->obfd.get ()) != NULL) |
0e9e9abd UW |
2455 | return; |
2456 | ||
2457 | /* Read contents of exception table and index. */ | |
98badbfd TT |
2458 | exidx = bfd_get_section_by_name (objfile->obfd.get (), |
2459 | ELF_STRING_ARM_unwind); | |
984c7238 | 2460 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2461 | if (exidx) |
2462 | { | |
fd361982 AM |
2463 | exidx_vma = bfd_section_vma (exidx); |
2464 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd | 2465 | |
98badbfd | 2466 | if (!bfd_get_section_contents (objfile->obfd.get (), exidx, |
984c7238 TT |
2467 | exidx_data.data (), 0, |
2468 | exidx_data.size ())) | |
2469 | return; | |
0e9e9abd UW |
2470 | } |
2471 | ||
98badbfd | 2472 | extab = bfd_get_section_by_name (objfile->obfd.get (), ".ARM.extab"); |
984c7238 | 2473 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2474 | if (extab) |
2475 | { | |
fd361982 AM |
2476 | extab_vma = bfd_section_vma (extab); |
2477 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd | 2478 | |
98badbfd | 2479 | if (!bfd_get_section_contents (objfile->obfd.get (), extab, |
984c7238 TT |
2480 | extab_data.data (), 0, |
2481 | extab_data.size ())) | |
2482 | return; | |
0e9e9abd UW |
2483 | } |
2484 | ||
2485 | /* Allocate exception table data structure. */ | |
98badbfd | 2486 | data = arm_exidx_data_key.emplace (objfile->obfd.get ()); |
7a5d944b | 2487 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2488 | |
2489 | /* Fill in exception table. */ | |
984c7238 | 2490 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2491 | { |
2492 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2493 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2494 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2495 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2496 | bfd_vma addr = 0, word = 0; |
2497 | int n_bytes = 0, n_words = 0; | |
2498 | struct obj_section *sec; | |
2499 | gdb_byte *entry = NULL; | |
2500 | ||
2501 | /* Extract address of start of function. */ | |
2502 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2503 | idx += exidx_vma + i * 8; | |
2504 | ||
2505 | /* Find section containing function and compute section offset. */ | |
2506 | sec = arm_obj_section_from_vma (objfile, idx); | |
2507 | if (sec == NULL) | |
2508 | continue; | |
fd361982 | 2509 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2510 | |
2511 | /* Determine address of exception table entry. */ | |
2512 | if (val == 1) | |
2513 | { | |
2514 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2515 | } | |
2516 | else if ((val & 0xff000000) == 0x80000000) | |
2517 | { | |
2518 | /* Exception table entry embedded in .ARM.exidx | |
2519 | -- must be short form. */ | |
2520 | word = val; | |
2521 | n_bytes = 3; | |
2522 | } | |
2523 | else if (!(val & 0x80000000)) | |
2524 | { | |
2525 | /* Exception table entry in .ARM.extab. */ | |
2526 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2527 | addr += exidx_vma + i * 8 + 4; | |
2528 | ||
984c7238 | 2529 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2530 | { |
2531 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2532 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2533 | addr += 4; |
2534 | ||
2535 | if ((word & 0xff000000) == 0x80000000) | |
2536 | { | |
2537 | /* Short form. */ | |
2538 | n_bytes = 3; | |
2539 | } | |
2540 | else if ((word & 0xff000000) == 0x81000000 | |
2541 | || (word & 0xff000000) == 0x82000000) | |
2542 | { | |
2543 | /* Long form. */ | |
2544 | n_bytes = 2; | |
2545 | n_words = ((word >> 16) & 0xff); | |
2546 | } | |
2547 | else if (!(word & 0x80000000)) | |
2548 | { | |
2549 | bfd_vma pers; | |
2550 | struct obj_section *pers_sec; | |
2551 | int gnu_personality = 0; | |
2552 | ||
2553 | /* Custom personality routine. */ | |
2554 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2555 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2556 | ||
2557 | /* Check whether we've got one of the variants of the | |
2558 | GNU personality routines. */ | |
2559 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2560 | if (pers_sec) | |
2561 | { | |
2562 | static const char *personality[] = | |
2563 | { | |
2564 | "__gcc_personality_v0", | |
2565 | "__gxx_personality_v0", | |
2566 | "__gcj_personality_v0", | |
2567 | "__gnu_objc_personality_v0", | |
2568 | NULL | |
2569 | }; | |
2570 | ||
0c1bcd23 | 2571 | CORE_ADDR pc = pers + pers_sec->offset (); |
0e9e9abd UW |
2572 | int k; |
2573 | ||
2574 | for (k = 0; personality[k]; k++) | |
2575 | if (lookup_minimal_symbol_by_pc_name | |
2576 | (pc, personality[k], objfile)) | |
2577 | { | |
2578 | gnu_personality = 1; | |
2579 | break; | |
2580 | } | |
2581 | } | |
2582 | ||
2583 | /* If so, the next word contains a word count in the high | |
2584 | byte, followed by the same unwind instructions as the | |
2585 | pre-defined forms. */ | |
2586 | if (gnu_personality | |
984c7238 | 2587 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2588 | { |
2589 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2590 | (extab_data.data () |
2591 | + addr - extab_vma)); | |
0e9e9abd UW |
2592 | addr += 4; |
2593 | n_bytes = 3; | |
2594 | n_words = ((word >> 24) & 0xff); | |
2595 | } | |
2596 | } | |
2597 | } | |
2598 | } | |
2599 | ||
2600 | /* Sanity check address. */ | |
2601 | if (n_words) | |
984c7238 TT |
2602 | if (addr < extab_vma |
2603 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2604 | n_words = n_bytes = 0; |
2605 | ||
2606 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2607 | significant bytes are valid), followed by N_WORDS words in the | |
2608 | extab section starting at ADDR. */ | |
2609 | if (n_bytes || n_words) | |
2610 | { | |
224c3ddb SM |
2611 | gdb_byte *p = entry |
2612 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2613 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2614 | |
2615 | while (n_bytes--) | |
2616 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2617 | ||
2618 | while (n_words--) | |
2619 | { | |
2620 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2621 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2622 | addr += 4; |
2623 | ||
2624 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2625 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2626 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2627 | *p++ = (gdb_byte) (word & 0xff); | |
2628 | } | |
2629 | ||
2630 | /* Implied "Finish" to terminate the list. */ | |
2631 | *p++ = 0xb0; | |
2632 | } | |
2633 | ||
2634 | /* Push entry onto vector. They are guaranteed to always | |
2635 | appear in order of increasing addresses. */ | |
2636 | new_exidx_entry.addr = idx; | |
2637 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2638 | data->section_maps[sec->the_bfd_section->index].push_back |
2639 | (new_exidx_entry); | |
0e9e9abd | 2640 | } |
0e9e9abd UW |
2641 | } |
2642 | ||
2643 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2644 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2645 | set *START to the start of the region covered by this entry. */ | |
2646 | ||
2647 | static gdb_byte * | |
2648 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2649 | { | |
2650 | struct obj_section *sec; | |
2651 | ||
2652 | sec = find_pc_section (memaddr); | |
2653 | if (sec != NULL) | |
2654 | { | |
2655 | struct arm_exidx_data *data; | |
0c1bcd23 | 2656 | struct arm_exidx_entry map_key = { memaddr - sec->addr (), 0 }; |
0e9e9abd | 2657 | |
98badbfd | 2658 | data = arm_exidx_data_key.get (sec->objfile->obfd.get ()); |
0e9e9abd UW |
2659 | if (data != NULL) |
2660 | { | |
7a5d944b TT |
2661 | std::vector<arm_exidx_entry> &map |
2662 | = data->section_maps[sec->the_bfd_section->index]; | |
2663 | if (!map.empty ()) | |
0e9e9abd | 2664 | { |
7a5d944b | 2665 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2666 | |
7a5d944b | 2667 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2668 | point. If the following symbol starts at this exact |
2669 | address, we use that; otherwise, the preceding | |
2670 | exception table entry covers this address. */ | |
7a5d944b | 2671 | if (idx < map.end ()) |
0e9e9abd | 2672 | { |
7a5d944b | 2673 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2674 | { |
2675 | if (start) | |
0c1bcd23 | 2676 | *start = idx->addr + sec->addr (); |
7a5d944b | 2677 | return idx->entry; |
0e9e9abd UW |
2678 | } |
2679 | } | |
2680 | ||
7a5d944b | 2681 | if (idx > map.begin ()) |
0e9e9abd | 2682 | { |
7a5d944b | 2683 | idx = idx - 1; |
0e9e9abd | 2684 | if (start) |
0c1bcd23 | 2685 | *start = idx->addr + sec->addr (); |
7a5d944b | 2686 | return idx->entry; |
0e9e9abd UW |
2687 | } |
2688 | } | |
2689 | } | |
2690 | } | |
2691 | ||
2692 | return NULL; | |
2693 | } | |
2694 | ||
2695 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2696 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2697 | return a prologue cache structure describing how to unwind this frame. | |
2698 | ||
2699 | Return NULL if the unwinding instruction list contains a "spare", | |
2700 | "reserved" or "refuse to unwind" instruction as defined in section | |
2701 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2702 | for the ARM Architecture" document. */ | |
2703 | ||
2704 | static struct arm_prologue_cache * | |
bd2b40ac | 2705 | arm_exidx_fill_cache (frame_info_ptr this_frame, gdb_byte *entry) |
0e9e9abd UW |
2706 | { |
2707 | CORE_ADDR vsp = 0; | |
2708 | int vsp_valid = 0; | |
2709 | ||
2710 | struct arm_prologue_cache *cache; | |
2711 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 2712 | arm_cache_init (cache, this_frame); |
0e9e9abd UW |
2713 | |
2714 | for (;;) | |
2715 | { | |
2716 | gdb_byte insn; | |
2717 | ||
2718 | /* Whenever we reload SP, we actually have to retrieve its | |
2719 | actual value in the current frame. */ | |
2720 | if (!vsp_valid) | |
2721 | { | |
a9a87d35 | 2722 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
0e9e9abd | 2723 | { |
098caef4 | 2724 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2725 | vsp = get_frame_register_unsigned (this_frame, reg); |
2726 | } | |
2727 | else | |
2728 | { | |
098caef4 | 2729 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr (); |
0e9e9abd UW |
2730 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); |
2731 | } | |
2732 | ||
2733 | vsp_valid = 1; | |
2734 | } | |
2735 | ||
2736 | /* Decode next unwind instruction. */ | |
2737 | insn = *entry++; | |
2738 | ||
2739 | if ((insn & 0xc0) == 0) | |
2740 | { | |
2741 | int offset = insn & 0x3f; | |
2742 | vsp += (offset << 2) + 4; | |
2743 | } | |
2744 | else if ((insn & 0xc0) == 0x40) | |
2745 | { | |
2746 | int offset = insn & 0x3f; | |
2747 | vsp -= (offset << 2) + 4; | |
2748 | } | |
2749 | else if ((insn & 0xf0) == 0x80) | |
2750 | { | |
2751 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2752 | int i; | |
2753 | ||
2754 | /* The special case of an all-zero mask identifies | |
2755 | "Refuse to unwind". We return NULL to fall back | |
2756 | to the prologue analyzer. */ | |
2757 | if (mask == 0) | |
2758 | return NULL; | |
2759 | ||
2760 | /* Pop registers r4..r15 under mask. */ | |
2761 | for (i = 0; i < 12; i++) | |
2762 | if (mask & (1 << i)) | |
2763 | { | |
098caef4 | 2764 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2765 | vsp += 4; |
2766 | } | |
2767 | ||
2768 | /* Special-case popping SP -- we need to reload vsp. */ | |
2769 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2770 | vsp_valid = 0; | |
2771 | } | |
2772 | else if ((insn & 0xf0) == 0x90) | |
2773 | { | |
2774 | int reg = insn & 0xf; | |
2775 | ||
2776 | /* Reserved cases. */ | |
2777 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2778 | return NULL; | |
2779 | ||
2780 | /* Set SP from another register and mark VSP for reload. */ | |
2781 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2782 | vsp_valid = 0; | |
2783 | } | |
2784 | else if ((insn & 0xf0) == 0xa0) | |
2785 | { | |
2786 | int count = insn & 0x7; | |
2787 | int pop_lr = (insn & 0x8) != 0; | |
2788 | int i; | |
2789 | ||
2790 | /* Pop r4..r[4+count]. */ | |
2791 | for (i = 0; i <= count; i++) | |
2792 | { | |
098caef4 | 2793 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2794 | vsp += 4; |
2795 | } | |
2796 | ||
2797 | /* If indicated by flag, pop LR as well. */ | |
2798 | if (pop_lr) | |
2799 | { | |
098caef4 | 2800 | cache->saved_regs[ARM_LR_REGNUM].set_addr (vsp); |
0e9e9abd UW |
2801 | vsp += 4; |
2802 | } | |
2803 | } | |
2804 | else if (insn == 0xb0) | |
2805 | { | |
2806 | /* We could only have updated PC by popping into it; if so, it | |
2807 | will show up as address. Otherwise, copy LR into PC. */ | |
a9a87d35 | 2808 | if (!cache->saved_regs[ARM_PC_REGNUM].is_addr ()) |
0e9e9abd UW |
2809 | cache->saved_regs[ARM_PC_REGNUM] |
2810 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2811 | ||
2812 | /* We're done. */ | |
2813 | break; | |
2814 | } | |
2815 | else if (insn == 0xb1) | |
2816 | { | |
2817 | int mask = *entry++; | |
2818 | int i; | |
2819 | ||
2820 | /* All-zero mask and mask >= 16 is "spare". */ | |
2821 | if (mask == 0 || mask >= 16) | |
2822 | return NULL; | |
2823 | ||
2824 | /* Pop r0..r3 under mask. */ | |
2825 | for (i = 0; i < 4; i++) | |
2826 | if (mask & (1 << i)) | |
2827 | { | |
098caef4 | 2828 | cache->saved_regs[i].set_addr (vsp); |
0e9e9abd UW |
2829 | vsp += 4; |
2830 | } | |
2831 | } | |
2832 | else if (insn == 0xb2) | |
2833 | { | |
2834 | ULONGEST offset = 0; | |
2835 | unsigned shift = 0; | |
2836 | ||
2837 | do | |
2838 | { | |
2839 | offset |= (*entry & 0x7f) << shift; | |
2840 | shift += 7; | |
2841 | } | |
2842 | while (*entry++ & 0x80); | |
2843 | ||
2844 | vsp += 0x204 + (offset << 2); | |
2845 | } | |
2846 | else if (insn == 0xb3) | |
2847 | { | |
2848 | int start = *entry >> 4; | |
2849 | int count = (*entry++) & 0xf; | |
2850 | int i; | |
2851 | ||
2852 | /* Only registers D0..D15 are valid here. */ | |
2853 | if (start + count >= 16) | |
2854 | return NULL; | |
2855 | ||
2856 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2857 | for (i = 0; i <= count; i++) | |
2858 | { | |
098caef4 | 2859 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2860 | vsp += 8; |
2861 | } | |
2862 | ||
2863 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2864 | vsp += 4; | |
2865 | } | |
2866 | else if ((insn & 0xf8) == 0xb8) | |
2867 | { | |
2868 | int count = insn & 0x7; | |
2869 | int i; | |
2870 | ||
2871 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2872 | for (i = 0; i <= count; i++) | |
2873 | { | |
098caef4 | 2874 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2875 | vsp += 8; |
2876 | } | |
2877 | ||
2878 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2879 | vsp += 4; | |
2880 | } | |
2881 | else if (insn == 0xc6) | |
2882 | { | |
2883 | int start = *entry >> 4; | |
2884 | int count = (*entry++) & 0xf; | |
2885 | int i; | |
2886 | ||
2887 | /* Only registers WR0..WR15 are valid. */ | |
2888 | if (start + count >= 16) | |
2889 | return NULL; | |
2890 | ||
2891 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2892 | for (i = 0; i <= count; i++) | |
2893 | { | |
098caef4 | 2894 | cache->saved_regs[ARM_WR0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2895 | vsp += 8; |
2896 | } | |
2897 | } | |
2898 | else if (insn == 0xc7) | |
2899 | { | |
2900 | int mask = *entry++; | |
2901 | int i; | |
2902 | ||
2903 | /* All-zero mask and mask >= 16 is "spare". */ | |
2904 | if (mask == 0 || mask >= 16) | |
2905 | return NULL; | |
2906 | ||
2907 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2908 | for (i = 0; i < 4; i++) | |
2909 | if (mask & (1 << i)) | |
2910 | { | |
098caef4 | 2911 | cache->saved_regs[ARM_WCGR0_REGNUM + i].set_addr (vsp); |
0e9e9abd UW |
2912 | vsp += 4; |
2913 | } | |
2914 | } | |
2915 | else if ((insn & 0xf8) == 0xc0) | |
2916 | { | |
2917 | int count = insn & 0x7; | |
2918 | int i; | |
2919 | ||
2920 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2921 | for (i = 0; i <= count; i++) | |
2922 | { | |
098caef4 | 2923 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].set_addr (vsp); |
0e9e9abd UW |
2924 | vsp += 8; |
2925 | } | |
2926 | } | |
2927 | else if (insn == 0xc8) | |
2928 | { | |
2929 | int start = *entry >> 4; | |
2930 | int count = (*entry++) & 0xf; | |
2931 | int i; | |
2932 | ||
2933 | /* Only registers D0..D31 are valid. */ | |
2934 | if (start + count >= 16) | |
2935 | return NULL; | |
2936 | ||
2937 | /* Pop VFP double-precision registers | |
2938 | D[16+start]..D[16+start+count]. */ | |
2939 | for (i = 0; i <= count; i++) | |
2940 | { | |
098caef4 | 2941 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].set_addr (vsp); |
0e9e9abd UW |
2942 | vsp += 8; |
2943 | } | |
2944 | } | |
2945 | else if (insn == 0xc9) | |
2946 | { | |
2947 | int start = *entry >> 4; | |
2948 | int count = (*entry++) & 0xf; | |
2949 | int i; | |
2950 | ||
2951 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2952 | for (i = 0; i <= count; i++) | |
2953 | { | |
098caef4 | 2954 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2955 | vsp += 8; |
2956 | } | |
2957 | } | |
2958 | else if ((insn & 0xf8) == 0xd0) | |
2959 | { | |
2960 | int count = insn & 0x7; | |
2961 | int i; | |
2962 | ||
2963 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2964 | for (i = 0; i <= count; i++) | |
2965 | { | |
098caef4 | 2966 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2967 | vsp += 8; |
2968 | } | |
2969 | } | |
2970 | else | |
2971 | { | |
2972 | /* Everything else is "spare". */ | |
2973 | return NULL; | |
2974 | } | |
2975 | } | |
2976 | ||
2977 | /* If we restore SP from a register, assume this was the frame register. | |
2978 | Otherwise just fall back to SP as frame register. */ | |
a9a87d35 | 2979 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
098caef4 | 2980 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2981 | else |
2982 | cache->framereg = ARM_SP_REGNUM; | |
2983 | ||
2984 | /* Determine offset to previous frame. */ | |
2985 | cache->framesize | |
2986 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2987 | ||
2988 | /* We already got the previous SP. */ | |
ae7e2f45 | 2989 | arm_gdbarch_tdep *tdep |
08106042 | 2990 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2991 | arm_cache_set_active_sp_value (cache, tdep, vsp); |
0e9e9abd UW |
2992 | |
2993 | return cache; | |
2994 | } | |
2995 | ||
2996 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2997 | already computes a filled-in prologue cache, which is then used | |
2998 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2999 | routines also used for prologue-parsing based unwinding. */ | |
3000 | ||
3001 | static int | |
3002 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3003 | frame_info_ptr this_frame, |
0e9e9abd UW |
3004 | void **this_prologue_cache) |
3005 | { | |
3006 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3007 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3008 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
3009 | struct arm_prologue_cache *cache; | |
3010 | gdb_byte *entry; | |
3011 | ||
3012 | /* See if we have an ARM exception table entry covering this address. */ | |
3013 | addr_in_block = get_frame_address_in_block (this_frame); | |
3014 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
3015 | if (!entry) | |
3016 | return 0; | |
3017 | ||
3018 | /* The ARM exception table does not describe unwind information | |
3019 | for arbitrary PC values, but is guaranteed to be correct only | |
3020 | at call sites. We have to decide here whether we want to use | |
3021 | ARM exception table information for this frame, or fall back | |
3022 | to using prologue parsing. (Note that if we have DWARF CFI, | |
3023 | this sniffer isn't even called -- CFI is always preferred.) | |
3024 | ||
3025 | Before we make this decision, however, we check whether we | |
3026 | actually have *symbol* information for the current frame. | |
3027 | If not, prologue parsing would not work anyway, so we might | |
3028 | as well use the exception table and hope for the best. */ | |
3029 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
3030 | { | |
3031 | int exc_valid = 0; | |
3032 | ||
3033 | /* If the next frame is "normal", we are at a call site in this | |
3034 | frame, so exception information is guaranteed to be valid. */ | |
3035 | if (get_next_frame (this_frame) | |
3036 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
3037 | exc_valid = 1; | |
3038 | ||
3039 | /* We also assume exception information is valid if we're currently | |
3040 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
3041 | ensure this, so that e.g. pthread cancellation works. */ |
3042 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 3043 | { |
7913a64c | 3044 | ULONGEST insn; |
416dc9c6 | 3045 | |
7913a64c YQ |
3046 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
3047 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
3048 | && (insn & 0xff00) == 0xdf00 /* svc */) |
3049 | exc_valid = 1; | |
0e9e9abd | 3050 | } |
d9311bfa AT |
3051 | else |
3052 | { | |
7913a64c | 3053 | ULONGEST insn; |
416dc9c6 | 3054 | |
7913a64c YQ |
3055 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
3056 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
3057 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
3058 | exc_valid = 1; | |
3059 | } | |
3060 | ||
0e9e9abd UW |
3061 | /* Bail out if we don't know that exception information is valid. */ |
3062 | if (!exc_valid) | |
3063 | return 0; | |
3064 | ||
3065 | /* The ARM exception index does not mark the *end* of the region | |
3066 | covered by the entry, and some functions will not have any entry. | |
3067 | To correctly recognize the end of the covered region, the linker | |
3068 | should have inserted dummy records with a CANTUNWIND marker. | |
3069 | ||
3070 | Unfortunately, current versions of GNU ld do not reliably do | |
3071 | this, and thus we may have found an incorrect entry above. | |
3072 | As a (temporary) sanity check, we only use the entry if it | |
3073 | lies *within* the bounds of the function. Note that this check | |
3074 | might reject perfectly valid entries that just happen to cover | |
3075 | multiple functions; therefore this check ought to be removed | |
3076 | once the linker is fixed. */ | |
3077 | if (func_start > exidx_region) | |
3078 | return 0; | |
3079 | } | |
3080 | ||
3081 | /* Decode the list of unwinding instructions into a prologue cache. | |
3082 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
3083 | cache = arm_exidx_fill_cache (this_frame, entry); | |
3084 | if (!cache) | |
3085 | return 0; | |
3086 | ||
3087 | *this_prologue_cache = cache; | |
3088 | return 1; | |
3089 | } | |
3090 | ||
3091 | struct frame_unwind arm_exidx_unwind = { | |
a154d838 | 3092 | "arm exidx", |
0e9e9abd | 3093 | NORMAL_FRAME, |
8fbca658 | 3094 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
3095 | arm_prologue_this_id, |
3096 | arm_prologue_prev_register, | |
3097 | NULL, | |
3098 | arm_exidx_unwind_sniffer | |
3099 | }; | |
3100 | ||
779aa56f | 3101 | static struct arm_prologue_cache * |
bd2b40ac | 3102 | arm_make_epilogue_frame_cache (frame_info_ptr this_frame) |
779aa56f YQ |
3103 | { |
3104 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
3105 | int reg; |
3106 | ||
3107 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3108 | arm_cache_init (cache, this_frame); |
779aa56f YQ |
3109 | |
3110 | /* Still rely on the offset calculated from prologue. */ | |
3111 | arm_scan_prologue (this_frame, cache); | |
3112 | ||
3113 | /* Since we are in epilogue, the SP has been restored. */ | |
ae7e2f45 | 3114 | arm_gdbarch_tdep *tdep |
08106042 | 3115 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3116 | arm_cache_set_active_sp_value (cache, tdep, |
3117 | get_frame_register_unsigned (this_frame, | |
3118 | ARM_SP_REGNUM)); | |
779aa56f YQ |
3119 | |
3120 | /* Calculate actual addresses of saved registers using offsets | |
3121 | determined by arm_scan_prologue. */ | |
3122 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 3123 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 | 3124 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
ae7e2f45 | 3125 | + arm_cache_get_prev_sp_value (cache, tdep)); |
779aa56f YQ |
3126 | |
3127 | return cache; | |
3128 | } | |
3129 | ||
3130 | /* Implementation of function hook 'this_id' in | |
3131 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3132 | ||
3133 | static void | |
bd2b40ac | 3134 | arm_epilogue_frame_this_id (frame_info_ptr this_frame, |
779aa56f YQ |
3135 | void **this_cache, |
3136 | struct frame_id *this_id) | |
3137 | { | |
3138 | struct arm_prologue_cache *cache; | |
3139 | CORE_ADDR pc, func; | |
3140 | ||
3141 | if (*this_cache == NULL) | |
3142 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
3143 | cache = (struct arm_prologue_cache *) *this_cache; | |
3144 | ||
3145 | /* Use function start address as part of the frame ID. If we cannot | |
3146 | identify the start address (due to missing symbol information), | |
3147 | fall back to just using the current PC. */ | |
3148 | pc = get_frame_pc (this_frame); | |
3149 | func = get_frame_func (this_frame); | |
fb3f3d25 | 3150 | if (func == 0) |
779aa56f YQ |
3151 | func = pc; |
3152 | ||
ae7e2f45 | 3153 | arm_gdbarch_tdep *tdep |
08106042 | 3154 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3155 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), pc); |
779aa56f YQ |
3156 | } |
3157 | ||
3158 | /* Implementation of function hook 'prev_register' in | |
3159 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3160 | ||
3161 | static struct value * | |
bd2b40ac | 3162 | arm_epilogue_frame_prev_register (frame_info_ptr this_frame, |
779aa56f YQ |
3163 | void **this_cache, int regnum) |
3164 | { | |
779aa56f YQ |
3165 | if (*this_cache == NULL) |
3166 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
3167 | |
3168 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
3169 | } | |
3170 | ||
3171 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
3172 | CORE_ADDR pc); | |
3173 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
3174 | CORE_ADDR pc); | |
3175 | ||
3176 | /* Implementation of function hook 'sniffer' in | |
3177 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3178 | ||
3179 | static int | |
3180 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3181 | frame_info_ptr this_frame, |
779aa56f YQ |
3182 | void **this_prologue_cache) |
3183 | { | |
3184 | if (frame_relative_level (this_frame) == 0) | |
3185 | { | |
3186 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3187 | CORE_ADDR pc = get_frame_pc (this_frame); | |
3188 | ||
3189 | if (arm_frame_is_thumb (this_frame)) | |
3190 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3191 | else | |
3192 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3193 | } | |
3194 | else | |
3195 | return 0; | |
3196 | } | |
3197 | ||
3198 | /* Frame unwinder from epilogue. */ | |
3199 | ||
3200 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
3201 | { | |
a154d838 | 3202 | "arm epilogue", |
779aa56f YQ |
3203 | NORMAL_FRAME, |
3204 | default_frame_unwind_stop_reason, | |
3205 | arm_epilogue_frame_this_id, | |
3206 | arm_epilogue_frame_prev_register, | |
3207 | NULL, | |
3208 | arm_epilogue_frame_sniffer, | |
3209 | }; | |
3210 | ||
80d8d390 YQ |
3211 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
3212 | trampoline, return the target PC. Otherwise return 0. | |
3213 | ||
3214 | void call0a (char c, short s, int i, long l) {} | |
3215 | ||
3216 | int main (void) | |
3217 | { | |
3218 | (*pointer_to_call0a) (c, s, i, l); | |
3219 | } | |
3220 | ||
3221 | Instead of calling a stub library function _call_via_xx (xx is | |
3222 | the register name), GCC may inline the trampoline in the object | |
3223 | file as below (register r2 has the address of call0a). | |
3224 | ||
3225 | .global main | |
3226 | .type main, %function | |
3227 | ... | |
3228 | bl .L1 | |
3229 | ... | |
3230 | .size main, .-main | |
3231 | ||
3232 | .L1: | |
3233 | bx r2 | |
3234 | ||
3235 | The trampoline 'bx r2' doesn't belong to main. */ | |
3236 | ||
3237 | static CORE_ADDR | |
bd2b40ac | 3238 | arm_skip_bx_reg (frame_info_ptr frame, CORE_ADDR pc) |
80d8d390 YQ |
3239 | { |
3240 | /* The heuristics of recognizing such trampoline is that FRAME is | |
3241 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
3242 | if (arm_frame_is_thumb (frame)) | |
3243 | { | |
3244 | gdb_byte buf[2]; | |
3245 | ||
3246 | if (target_read_memory (pc, buf, 2) == 0) | |
3247 | { | |
3248 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
3249 | enum bfd_endian byte_order_for_code | |
3250 | = gdbarch_byte_order_for_code (gdbarch); | |
3251 | uint16_t insn | |
3252 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3253 | ||
3254 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3255 | { | |
3256 | CORE_ADDR dest | |
3257 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
3258 | ||
3259 | /* Clear the LSB so that gdb core sets step-resume | |
3260 | breakpoint at the right address. */ | |
3261 | return UNMAKE_THUMB_ADDR (dest); | |
3262 | } | |
3263 | } | |
3264 | } | |
3265 | ||
3266 | return 0; | |
3267 | } | |
3268 | ||
909cf6ea | 3269 | static struct arm_prologue_cache * |
bd2b40ac | 3270 | arm_make_stub_cache (frame_info_ptr this_frame) |
909cf6ea | 3271 | { |
909cf6ea | 3272 | struct arm_prologue_cache *cache; |
909cf6ea | 3273 | |
35d5d4ee | 3274 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 3275 | arm_cache_init (cache, this_frame); |
909cf6ea | 3276 | |
ae7e2f45 | 3277 | arm_gdbarch_tdep *tdep |
08106042 | 3278 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3279 | arm_cache_set_active_sp_value (cache, tdep, |
3280 | get_frame_register_unsigned (this_frame, | |
3281 | ARM_SP_REGNUM)); | |
909cf6ea DJ |
3282 | |
3283 | return cache; | |
3284 | } | |
3285 | ||
3286 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3287 | ||
3288 | static void | |
bd2b40ac | 3289 | arm_stub_this_id (frame_info_ptr this_frame, |
909cf6ea DJ |
3290 | void **this_cache, |
3291 | struct frame_id *this_id) | |
3292 | { | |
3293 | struct arm_prologue_cache *cache; | |
3294 | ||
3295 | if (*this_cache == NULL) | |
a262aec2 | 3296 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 3297 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 3298 | |
ae7e2f45 | 3299 | arm_gdbarch_tdep *tdep |
08106042 | 3300 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3301 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
3302 | get_frame_pc (this_frame)); | |
909cf6ea DJ |
3303 | } |
3304 | ||
a262aec2 DJ |
3305 | static int |
3306 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3307 | frame_info_ptr this_frame, |
a262aec2 | 3308 | void **this_prologue_cache) |
909cf6ea | 3309 | { |
93d42b30 | 3310 | CORE_ADDR addr_in_block; |
948f8e3d | 3311 | gdb_byte dummy[4]; |
18d18ac8 YQ |
3312 | CORE_ADDR pc, start_addr; |
3313 | const char *name; | |
909cf6ea | 3314 | |
a262aec2 | 3315 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 3316 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 3317 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
3318 | /* We also use the stub winder if the target memory is unreadable |
3319 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
3320 | || target_read_memory (pc, dummy, 4) != 0) |
3321 | return 1; | |
3322 | ||
3323 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
3324 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 3325 | return 1; |
909cf6ea | 3326 | |
a262aec2 | 3327 | return 0; |
909cf6ea DJ |
3328 | } |
3329 | ||
a262aec2 | 3330 | struct frame_unwind arm_stub_unwind = { |
a154d838 | 3331 | "arm stub", |
a262aec2 | 3332 | NORMAL_FRAME, |
8fbca658 | 3333 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
3334 | arm_stub_this_id, |
3335 | arm_prologue_prev_register, | |
3336 | NULL, | |
3337 | arm_stub_unwind_sniffer | |
3338 | }; | |
3339 | ||
2ae28aa9 YQ |
3340 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
3341 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
3342 | returned. */ | |
3343 | ||
3344 | static struct arm_prologue_cache * | |
bd2b40ac | 3345 | arm_m_exception_cache (frame_info_ptr this_frame) |
2ae28aa9 YQ |
3346 | { |
3347 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
08106042 | 3348 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
2ae28aa9 | 3349 | struct arm_prologue_cache *cache; |
2ae28aa9 YQ |
3350 | |
3351 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3352 | arm_cache_init (cache, this_frame); |
2ae28aa9 | 3353 | |
55ea94da FH |
3354 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
3355 | describes which bits in LR that define which stack was used prior | |
3356 | to the exception and if FPU is used (causing extended stack frame). */ | |
3357 | ||
df4860da | 3358 | CORE_ADDR lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); |
ef273377 | 3359 | |
148ca9dd YR |
3360 | /* ARMv7-M Architecture Reference "A2.3.1 Arm core registers" |
3361 | states that LR is set to 0xffffffff on reset. ARMv8-M Architecture | |
3362 | Reference "B3.3 Registers" states that LR is set to 0xffffffff on warm | |
3363 | reset if Main Extension is implemented, otherwise the value is unknown. */ | |
3364 | if (lr == 0xffffffff) | |
3365 | { | |
619cce4c TS |
3366 | /* Terminate any further stack unwinding. */ |
3367 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
148ca9dd YR |
3368 | return cache; |
3369 | } | |
3370 | ||
df4860da TS |
3371 | /* Check FNC_RETURN indicator bits (24-31). */ |
3372 | bool fnc_return = (((lr >> 24) & 0xff) == 0xfe); | |
3373 | if (fnc_return) | |
ef273377 | 3374 | { |
df4860da TS |
3375 | /* FNC_RETURN is only valid for targets with Security Extension. */ |
3376 | if (!tdep->have_sec_ext) | |
3377 | { | |
3378 | error (_("While unwinding an exception frame, found unexpected Link " | |
3379 | "Register value %s that requires the security extension, " | |
3380 | "but the extension was not found or is disabled. This " | |
3381 | "should not happen and may be caused by corrupt data or a " | |
3382 | "bug in GDB."), phex (lr, ARM_INT_REGISTER_SIZE)); | |
3383 | } | |
3384 | ||
8c9ae6df YR |
3385 | if (!arm_unwind_secure_frames) |
3386 | { | |
3387 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
ef273377 | 3388 | |
619cce4c TS |
3389 | /* Terminate any further stack unwinding. */ |
3390 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
8c9ae6df YR |
3391 | return cache; |
3392 | } | |
3393 | ||
df4860da | 3394 | ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); |
8c9ae6df YR |
3395 | if ((xpsr & 0xff) != 0) |
3396 | /* Handler mode: This is the mode that exceptions are handled in. */ | |
3397 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); | |
ef273377 | 3398 | else |
8c9ae6df YR |
3399 | /* Thread mode: This is the normal mode that programs run in. */ |
3400 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); | |
ef273377 | 3401 | |
df4860da | 3402 | CORE_ADDR unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); |
55ea94da | 3403 | |
8c9ae6df YR |
3404 | /* Stack layout for a function call from Secure to Non-Secure state |
3405 | (ARMv8-M section B3.16): | |
55ea94da | 3406 | |
8c9ae6df YR |
3407 | SP Offset |
3408 | ||
3409 | +-------------------+ | |
3410 | 0x08 | | | |
3411 | +-------------------+ <-- Original SP | |
3412 | 0x04 | Partial xPSR | | |
3413 | +-------------------+ | |
3414 | 0x00 | Return Address | | |
3415 | +===================+ <-- New SP */ | |
3416 | ||
3417 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 0x00); | |
3418 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 0x00); | |
3419 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 0x04); | |
3420 | ||
3421 | arm_cache_set_active_sp_value (cache, tdep, unwound_sp + 0x08); | |
ef273377 CL |
3422 | |
3423 | return cache; | |
3424 | } | |
3425 | ||
3426 | /* Check EXC_RETURN indicator bits (24-31). */ | |
df4860da | 3427 | bool exc_return = (((lr >> 24) & 0xff) == 0xff); |
ef273377 | 3428 | if (exc_return) |
55ea94da | 3429 | { |
df4860da TS |
3430 | int sp_regnum; |
3431 | bool secure_stack_used = false; | |
3432 | bool default_callee_register_stacking = false; | |
3433 | bool exception_domain_is_secure = false; | |
3434 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3435 | ||
ef273377 | 3436 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ |
df4860da | 3437 | bool process_stack_used = (bit (lr, 2) != 0); |
ef273377 CL |
3438 | |
3439 | if (tdep->have_sec_ext) | |
3440 | { | |
df4860da TS |
3441 | secure_stack_used = (bit (lr, 6) != 0); |
3442 | default_callee_register_stacking = (bit (lr, 5) != 0); | |
3443 | exception_domain_is_secure = (bit (lr, 0) == 0); | |
ef273377 CL |
3444 | |
3445 | /* Unwinding from non-secure to secure can trip security | |
3446 | measures. In order to avoid the debugger being | |
3447 | intrusive, rely on the user to configure the requested | |
3448 | mode. */ | |
3449 | if (secure_stack_used && !exception_domain_is_secure | |
3450 | && !arm_unwind_secure_frames) | |
3451 | { | |
3452 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
3453 | ||
619cce4c TS |
3454 | /* Terminate any further stack unwinding. */ |
3455 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
ef273377 CL |
3456 | return cache; |
3457 | } | |
3458 | ||
3459 | if (process_stack_used) | |
3460 | { | |
3461 | if (secure_stack_used) | |
3462 | /* Secure thread (process) stack used, use PSP_S as SP. */ | |
df4860da | 3463 | sp_regnum = tdep->m_profile_psp_s_regnum; |
ef273377 CL |
3464 | else |
3465 | /* Non-secure thread (process) stack used, use PSP_NS as SP. */ | |
df4860da | 3466 | sp_regnum = tdep->m_profile_psp_ns_regnum; |
ef273377 CL |
3467 | } |
3468 | else | |
3469 | { | |
3470 | if (secure_stack_used) | |
3471 | /* Secure main stack used, use MSP_S as SP. */ | |
df4860da | 3472 | sp_regnum = tdep->m_profile_msp_s_regnum; |
ef273377 CL |
3473 | else |
3474 | /* Non-secure main stack used, use MSP_NS as SP. */ | |
df4860da | 3475 | sp_regnum = tdep->m_profile_msp_ns_regnum; |
ef273377 CL |
3476 | } |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | if (process_stack_used) | |
3481 | /* Thread (process) stack used, use PSP as SP. */ | |
df4860da | 3482 | sp_regnum = tdep->m_profile_psp_regnum; |
ef273377 CL |
3483 | else |
3484 | /* Main stack used, use MSP as SP. */ | |
df4860da TS |
3485 | sp_regnum = tdep->m_profile_msp_regnum; |
3486 | } | |
3487 | ||
3488 | /* Set the active SP regnum. */ | |
3489 | arm_cache_switch_prev_sp (cache, tdep, sp_regnum); | |
3490 | ||
3491 | /* Fetch the SP to use for this frame. */ | |
3492 | CORE_ADDR unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); | |
3493 | ||
3494 | /* Exception entry context stacking are described in ARMv8-M (section | |
3495 | B3.19) and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference | |
3496 | Manuals. | |
3497 | ||
3498 | The following figure shows the structure of the stack frame when | |
3499 | Security and Floating-point extensions are present. | |
3500 | ||
3501 | SP Offsets | |
3502 | Without With | |
3503 | Callee Regs Callee Regs | |
3504 | (Secure -> Non-Secure) | |
3505 | +-------------------+ | |
3506 | 0xA8 | | 0xD0 | |
3507 | +===================+ --+ <-- Original SP | |
3508 | 0xA4 | S31 | 0xCC | | |
3509 | +-------------------+ | | |
3510 | ... | Additional FP context | |
3511 | +-------------------+ | | |
3512 | 0x68 | S16 | 0x90 | | |
3513 | +===================+ --+ | |
3514 | 0x64 | Reserved | 0x8C | | |
3515 | +-------------------+ | | |
3516 | 0x60 | FPSCR | 0x88 | | |
3517 | +-------------------+ | | |
3518 | 0x5C | S15 | 0x84 | FP context | |
3519 | +-------------------+ | | |
3520 | ... | | |
3521 | +-------------------+ | | |
3522 | 0x20 | S0 | 0x48 | | |
3523 | +===================+ --+ | |
3524 | 0x1C | xPSR | 0x44 | | |
3525 | +-------------------+ | | |
3526 | 0x18 | Return address | 0x40 | | |
3527 | +-------------------+ | | |
3528 | 0x14 | LR(R14) | 0x3C | | |
3529 | +-------------------+ | | |
3530 | 0x10 | R12 | 0x38 | State context | |
3531 | +-------------------+ | | |
3532 | 0x0C | R3 | 0x34 | | |
3533 | +-------------------+ | | |
3534 | ... | | |
3535 | +-------------------+ | | |
3536 | 0x00 | R0 | 0x28 | | |
3537 | +===================+ --+ | |
3538 | | R11 | 0x24 | | |
3539 | +-------------------+ | | |
3540 | ... | | |
3541 | +-------------------+ | Additional state | |
3542 | | R4 | 0x08 | context when | |
3543 | +-------------------+ | transitioning from | |
3544 | | Reserved | 0x04 | Secure to Non-Secure | |
3545 | +-------------------+ | | |
3546 | | Magic signature | 0x00 | | |
3547 | +===================+ --+ <-- New SP */ | |
3548 | ||
3549 | uint32_t sp_r0_offset = 0; | |
3550 | ||
3551 | /* With the Security extension, the hardware saves R4..R11 too. */ | |
3552 | if (tdep->have_sec_ext && secure_stack_used | |
3553 | && (!default_callee_register_stacking || exception_domain_is_secure)) | |
3554 | { | |
3555 | /* Read R4..R11 from the integer callee registers. */ | |
3556 | cache->saved_regs[4].set_addr (unwound_sp + 0x08); | |
3557 | cache->saved_regs[5].set_addr (unwound_sp + 0x0C); | |
3558 | cache->saved_regs[6].set_addr (unwound_sp + 0x10); | |
3559 | cache->saved_regs[7].set_addr (unwound_sp + 0x14); | |
3560 | cache->saved_regs[8].set_addr (unwound_sp + 0x18); | |
3561 | cache->saved_regs[9].set_addr (unwound_sp + 0x1C); | |
3562 | cache->saved_regs[10].set_addr (unwound_sp + 0x20); | |
3563 | cache->saved_regs[11].set_addr (unwound_sp + 0x24); | |
3564 | sp_r0_offset = 0x28; | |
3565 | } | |
3566 | ||
3567 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3568 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3569 | "B1.5.6 Exception entry behavior" in | |
3570 | "ARMv7-M Architecture Reference Manual". */ | |
3571 | cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); | |
3572 | cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); | |
3573 | cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); | |
3574 | cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); | |
3575 | cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3576 | + 0x10); | |
3577 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3578 | + 0x14); | |
3579 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3580 | + 0x18); | |
3581 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3582 | + 0x1C); | |
3583 | ||
3584 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) | |
3585 | type used. */ | |
3586 | bool extended_frame_used = (bit (lr, 4) == 0); | |
3587 | if (extended_frame_used) | |
3588 | { | |
3589 | ULONGEST fpccr; | |
60c90d8c | 3590 | ULONGEST fpcar; |
df4860da TS |
3591 | |
3592 | /* Read FPCCR register. */ | |
ce6c3d25 TS |
3593 | if (!safe_read_memory_unsigned_integer (FPCCR, ARM_INT_REGISTER_SIZE, |
3594 | byte_order, &fpccr)) | |
3595 | { | |
3596 | warning (_("Could not fetch required FPCCR content. Further " | |
3597 | "unwinding is impossible.")); | |
3598 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
3599 | return cache; | |
3600 | } | |
df4860da | 3601 | |
60c90d8c TS |
3602 | /* Read FPCAR register. */ |
3603 | if (!safe_read_memory_unsigned_integer (FPCAR, ARM_INT_REGISTER_SIZE, | |
3604 | byte_order, &fpcar)) | |
3605 | { | |
3606 | warning (_("Could not fetch FPCAR content. Further unwinding of " | |
3607 | "FP register values will be unreliable.")); | |
3608 | fpcar = 0; | |
3609 | } | |
3610 | ||
3611 | bool fpccr_aspen = bit (fpccr, 31); | |
3612 | bool fpccr_lspen = bit (fpccr, 30); | |
3613 | bool fpccr_ts = bit (fpccr, 26); | |
3614 | bool fpccr_lspact = bit (fpccr, 0); | |
3615 | ||
3616 | /* The LSPEN and ASPEN bits indicate if the lazy state preservation | |
3617 | for FP registers is enabled or disabled. The LSPACT bit indicate, | |
3618 | together with FPCAR, if the lazy state preservation feature is | |
3619 | active for the current frame or for another frame. | |
3620 | See "Lazy context save of FP state", in B1.5.7, also ARM AN298, | |
3621 | supported by Cortex-M4F architecture for details. */ | |
3622 | bool fpcar_points_to_this_frame = ((unwound_sp + sp_r0_offset + 0x20) | |
3623 | == (fpcar & ~0x7)); | |
3624 | bool read_fp_regs_from_stack = (!(fpccr_aspen && fpccr_lspen | |
3625 | && fpccr_lspact | |
3626 | && fpcar_points_to_this_frame)); | |
df4860da TS |
3627 | |
3628 | /* Extended stack frame type used. */ | |
60c90d8c | 3629 | if (read_fp_regs_from_stack) |
df4860da | 3630 | { |
60c90d8c TS |
3631 | CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20; |
3632 | for (int i = 0; i < 8; i++) | |
3633 | { | |
3634 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); | |
3635 | addr += 8; | |
3636 | } | |
df4860da TS |
3637 | } |
3638 | cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp | |
3639 | + sp_r0_offset + 0x60); | |
ef273377 | 3640 | |
df4860da TS |
3641 | if (tdep->have_sec_ext && !default_callee_register_stacking |
3642 | && fpccr_ts) | |
3643 | { | |
3644 | /* Handle floating-point callee saved registers. */ | |
60c90d8c | 3645 | if (read_fp_regs_from_stack) |
df4860da | 3646 | { |
60c90d8c TS |
3647 | CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x68; |
3648 | for (int i = 8; i < 16; i++) | |
3649 | { | |
3650 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); | |
3651 | addr += 8; | |
3652 | } | |
df4860da | 3653 | } |
2ae28aa9 | 3654 | |
df4860da TS |
3655 | arm_cache_set_active_sp_value (cache, tdep, |
3656 | unwound_sp + sp_r0_offset + 0xA8); | |
3657 | } | |
3658 | else | |
ef273377 | 3659 | { |
df4860da TS |
3660 | /* Offset 0x64 is reserved. */ |
3661 | arm_cache_set_active_sp_value (cache, tdep, | |
3662 | unwound_sp + sp_r0_offset + 0x68); | |
ef273377 | 3663 | } |
ef273377 CL |
3664 | } |
3665 | else | |
3666 | { | |
df4860da | 3667 | /* Standard stack frame type used. */ |
2d9cf99d | 3668 | arm_cache_set_active_sp_value (cache, tdep, |
df4860da | 3669 | unwound_sp + sp_r0_offset + 0x20); |
ef273377 | 3670 | } |
55ea94da | 3671 | |
df4860da TS |
3672 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3673 | aligner between the top of the 32-byte stack frame and the | |
3674 | previous context's stack pointer. */ | |
3675 | ULONGEST xpsr; | |
ce6c3d25 TS |
3676 | if (!safe_read_memory_unsigned_integer (cache->saved_regs[ARM_PS_REGNUM] |
3677 | .addr (), ARM_INT_REGISTER_SIZE, | |
3678 | byte_order, &xpsr)) | |
3679 | { | |
3680 | warning (_("Could not fetch required XPSR content. Further " | |
3681 | "unwinding is impossible.")); | |
3682 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
3683 | return cache; | |
3684 | } | |
3685 | ||
df4860da TS |
3686 | if (bit (xpsr, 9) != 0) |
3687 | { | |
3688 | CORE_ADDR new_sp = arm_cache_get_prev_sp_value (cache, tdep) + 4; | |
3689 | arm_cache_set_active_sp_value (cache, tdep, new_sp); | |
3690 | } | |
2ae28aa9 | 3691 | |
df4860da TS |
3692 | return cache; |
3693 | } | |
3694 | ||
f34652de PA |
3695 | internal_error (_("While unwinding an exception frame, " |
3696 | "found unexpected Link Register value " | |
3697 | "%s. This should not happen and may " | |
3698 | "be caused by corrupt data or a bug in" | |
3699 | " GDB."), | |
df4860da | 3700 | phex (lr, ARM_INT_REGISTER_SIZE)); |
2ae28aa9 YQ |
3701 | } |
3702 | ||
ce6c3d25 TS |
3703 | /* Implementation of the stop_reason hook for arm_m_exception frames. */ |
3704 | ||
3705 | static enum unwind_stop_reason | |
3706 | arm_m_exception_frame_unwind_stop_reason (frame_info_ptr this_frame, | |
3707 | void **this_cache) | |
3708 | { | |
3709 | struct arm_prologue_cache *cache; | |
3710 | arm_gdbarch_tdep *tdep | |
3711 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); | |
3712 | ||
3713 | if (*this_cache == NULL) | |
3714 | *this_cache = arm_m_exception_cache (this_frame); | |
3715 | cache = (struct arm_prologue_cache *) *this_cache; | |
3716 | ||
3717 | /* If we've hit a wall, stop. */ | |
3718 | if (arm_cache_get_prev_sp_value (cache, tdep) == 0) | |
3719 | return UNWIND_OUTERMOST; | |
3720 | ||
3721 | return UNWIND_NO_REASON; | |
3722 | } | |
3723 | ||
2ae28aa9 YQ |
3724 | /* Implementation of function hook 'this_id' in |
3725 | 'struct frame_uwnind'. */ | |
3726 | ||
3727 | static void | |
bd2b40ac | 3728 | arm_m_exception_this_id (frame_info_ptr this_frame, |
2ae28aa9 YQ |
3729 | void **this_cache, |
3730 | struct frame_id *this_id) | |
3731 | { | |
3732 | struct arm_prologue_cache *cache; | |
3733 | ||
3734 | if (*this_cache == NULL) | |
3735 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3736 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3737 | |
3738 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
ae7e2f45 | 3739 | arm_gdbarch_tdep *tdep |
08106042 | 3740 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3741 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
2ae28aa9 YQ |
3742 | get_frame_pc (this_frame)); |
3743 | } | |
3744 | ||
3745 | /* Implementation of function hook 'prev_register' in | |
3746 | 'struct frame_uwnind'. */ | |
3747 | ||
3748 | static struct value * | |
bd2b40ac | 3749 | arm_m_exception_prev_register (frame_info_ptr this_frame, |
2ae28aa9 YQ |
3750 | void **this_cache, |
3751 | int prev_regnum) | |
3752 | { | |
2ae28aa9 | 3753 | struct arm_prologue_cache *cache; |
ef273377 | 3754 | CORE_ADDR sp_value; |
2ae28aa9 YQ |
3755 | |
3756 | if (*this_cache == NULL) | |
3757 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3758 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3759 | |
3760 | /* The value was already reconstructed into PREV_SP. */ | |
ae7e2f45 | 3761 | arm_gdbarch_tdep *tdep |
08106042 | 3762 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
2ae28aa9 YQ |
3763 | if (prev_regnum == ARM_SP_REGNUM) |
3764 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
ae7e2f45 | 3765 | arm_cache_get_prev_sp_value (cache, tdep)); |
2ae28aa9 | 3766 | |
8c9ae6df YR |
3767 | /* If we are asked to unwind the PC, strip the saved T bit. */ |
3768 | if (prev_regnum == ARM_PC_REGNUM) | |
3769 | { | |
3770 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3771 | cache->saved_regs, | |
3772 | prev_regnum); | |
3773 | CORE_ADDR pc = value_as_address (value); | |
3774 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3775 | UNMAKE_THUMB_ADDR (pc)); | |
3776 | } | |
3777 | ||
ef273377 CL |
3778 | /* The value might be one of the alternative SP, if so, use the |
3779 | value already constructed. */ | |
d65edaa0 | 3780 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
3781 | { |
3782 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
3783 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
3784 | } | |
3785 | ||
8c9ae6df YR |
3786 | /* If we are asked to unwind the xPSR, set T bit if PC is in thumb mode. |
3787 | LR register is unreliable as it contains FNC_RETURN or EXC_RETURN | |
3788 | pattern. */ | |
3789 | if (prev_regnum == ARM_PS_REGNUM) | |
3790 | { | |
3791 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3792 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3793 | cache->saved_regs, | |
3794 | ARM_PC_REGNUM); | |
3795 | CORE_ADDR pc = value_as_address (value); | |
3796 | value = trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3797 | ARM_PS_REGNUM); | |
3798 | ULONGEST xpsr = value_as_long (value); | |
3799 | ||
3800 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
3801 | xpsr = reconstruct_t_bit (gdbarch, pc, xpsr); | |
3802 | return frame_unwind_got_constant (this_frame, ARM_PS_REGNUM, xpsr); | |
3803 | } | |
3804 | ||
2ae28aa9 YQ |
3805 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
3806 | prev_regnum); | |
3807 | } | |
3808 | ||
3809 | /* Implementation of function hook 'sniffer' in | |
3810 | 'struct frame_uwnind'. */ | |
3811 | ||
3812 | static int | |
3813 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3814 | frame_info_ptr this_frame, |
2ae28aa9 YQ |
3815 | void **this_prologue_cache) |
3816 | { | |
ef273377 | 3817 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2ae28aa9 YQ |
3818 | CORE_ADDR this_pc = get_frame_pc (this_frame); |
3819 | ||
3820 | /* No need to check is_m; this sniffer is only registered for | |
3821 | M-profile architectures. */ | |
3822 | ||
ca90e760 | 3823 | /* Check if exception frame returns to a magic PC value. */ |
ef273377 | 3824 | return arm_m_addr_is_magic (gdbarch, this_pc); |
2ae28aa9 YQ |
3825 | } |
3826 | ||
3827 | /* Frame unwinder for M-profile exceptions. */ | |
3828 | ||
3829 | struct frame_unwind arm_m_exception_unwind = | |
3830 | { | |
a154d838 | 3831 | "arm m exception", |
2ae28aa9 | 3832 | SIGTRAMP_FRAME, |
ce6c3d25 | 3833 | arm_m_exception_frame_unwind_stop_reason, |
2ae28aa9 YQ |
3834 | arm_m_exception_this_id, |
3835 | arm_m_exception_prev_register, | |
3836 | NULL, | |
3837 | arm_m_exception_unwind_sniffer | |
3838 | }; | |
3839 | ||
24de872b | 3840 | static CORE_ADDR |
bd2b40ac | 3841 | arm_normal_frame_base (frame_info_ptr this_frame, void **this_cache) |
24de872b DJ |
3842 | { |
3843 | struct arm_prologue_cache *cache; | |
3844 | ||
eb5492fa | 3845 | if (*this_cache == NULL) |
a262aec2 | 3846 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3847 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3848 | |
ae7e2f45 | 3849 | arm_gdbarch_tdep *tdep |
08106042 | 3850 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3851 | return arm_cache_get_prev_sp_value (cache, tdep) - cache->framesize; |
24de872b DJ |
3852 | } |
3853 | ||
eb5492fa DJ |
3854 | struct frame_base arm_normal_base = { |
3855 | &arm_prologue_unwind, | |
3856 | arm_normal_frame_base, | |
3857 | arm_normal_frame_base, | |
3858 | arm_normal_frame_base | |
3859 | }; | |
3860 | ||
b39cc962 | 3861 | static struct value * |
bd2b40ac | 3862 | arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, |
b39cc962 DJ |
3863 | int regnum) |
3864 | { | |
24568a2c | 3865 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
08106042 | 3866 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
8c9ae6df YR |
3867 | CORE_ADDR lr; |
3868 | ULONGEST cpsr; | |
b39cc962 | 3869 | |
42e11f36 | 3870 | if (regnum == ARM_PC_REGNUM) |
b39cc962 | 3871 | { |
b39cc962 DJ |
3872 | /* The PC is normally copied from the return column, which |
3873 | describes saves of LR. However, that version may have an | |
3874 | extra bit set to indicate Thumb state. The bit is not | |
3875 | part of the PC. */ | |
a01567f4 LM |
3876 | |
3877 | /* Record in the frame whether the return address was signed. */ | |
3878 | if (tdep->have_pacbti) | |
3879 | { | |
3880 | CORE_ADDR ra_auth_code | |
3881 | = frame_unwind_register_unsigned (this_frame, | |
3882 | tdep->pacbti_pseudo_base); | |
3883 | ||
3884 | if (ra_auth_code != 0) | |
3885 | set_frame_previous_pc_masked (this_frame); | |
3886 | } | |
3887 | ||
b39cc962 DJ |
3888 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3889 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3890 | arm_addr_bits_remove (gdbarch, lr)); |
42e11f36 TS |
3891 | } |
3892 | else if (regnum == ARM_PS_REGNUM) | |
3893 | { | |
b39cc962 | 3894 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ |
ca38c58e | 3895 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 | 3896 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
8c9ae6df | 3897 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
ca38c58e | 3898 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 | 3899 | } |
a6e4a48c YR |
3900 | else if (arm_is_alternative_sp_register (tdep, regnum)) |
3901 | { | |
3902 | /* Handle the alternative SP registers on Cortex-M. */ | |
3903 | bool override_with_sp_value = false; | |
3904 | CORE_ADDR val; | |
3905 | ||
3906 | if (tdep->have_sec_ext) | |
3907 | { | |
3908 | CORE_ADDR sp | |
3909 | = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
3910 | CORE_ADDR msp_s | |
3911 | = get_frame_register_unsigned (this_frame, | |
3912 | tdep->m_profile_msp_s_regnum); | |
3913 | CORE_ADDR msp_ns | |
3914 | = get_frame_register_unsigned (this_frame, | |
3915 | tdep->m_profile_msp_ns_regnum); | |
3916 | CORE_ADDR psp_s | |
3917 | = get_frame_register_unsigned (this_frame, | |
3918 | tdep->m_profile_psp_s_regnum); | |
3919 | CORE_ADDR psp_ns | |
3920 | = get_frame_register_unsigned (this_frame, | |
3921 | tdep->m_profile_psp_ns_regnum); | |
3922 | ||
3923 | bool is_msp = (regnum == tdep->m_profile_msp_regnum) | |
3924 | && (msp_s == sp || msp_ns == sp); | |
3925 | bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) | |
3926 | && (msp_s == sp); | |
3927 | bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) | |
3928 | && (msp_ns == sp); | |
3929 | bool is_psp = (regnum == tdep->m_profile_psp_regnum) | |
3930 | && (psp_s == sp || psp_ns == sp); | |
3931 | bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) | |
3932 | && (psp_s == sp); | |
3933 | bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) | |
3934 | && (psp_ns == sp); | |
3935 | ||
3936 | override_with_sp_value = is_msp || is_msp_s || is_msp_ns | |
3937 | || is_psp || is_psp_s || is_psp_ns; | |
3938 | ||
3939 | } | |
3940 | else if (tdep->is_m) | |
3941 | { | |
3942 | CORE_ADDR sp | |
3943 | = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
3944 | CORE_ADDR msp | |
3945 | = get_frame_register_unsigned (this_frame, | |
3946 | tdep->m_profile_msp_regnum); | |
3947 | CORE_ADDR psp | |
3948 | = get_frame_register_unsigned (this_frame, | |
3949 | tdep->m_profile_psp_regnum); | |
3950 | ||
3951 | bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); | |
3952 | bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); | |
3953 | ||
3954 | override_with_sp_value = is_msp || is_psp; | |
3955 | } | |
3956 | ||
3957 | if (override_with_sp_value) | |
3958 | { | |
3959 | /* Use value of SP from previous frame. */ | |
bd2b40ac | 3960 | frame_info_ptr prev_frame = get_prev_frame (this_frame); |
a6e4a48c YR |
3961 | if (prev_frame) |
3962 | val = get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); | |
3963 | else | |
3964 | val = get_frame_base (this_frame); | |
3965 | } | |
3966 | else | |
3967 | /* Use value for the register from previous frame. */ | |
3968 | val = get_frame_register_unsigned (this_frame, regnum); | |
3969 | ||
3970 | return frame_unwind_got_constant (this_frame, regnum, val); | |
3971 | } | |
42e11f36 | 3972 | |
f34652de | 3973 | internal_error (_("Unexpected register %d"), regnum); |
b39cc962 DJ |
3974 | } |
3975 | ||
c9cf6e20 | 3976 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3977 | |
3978 | static int | |
c9cf6e20 | 3979 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3980 | { |
3981 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3982 | unsigned int insn, insn2; | |
3983 | int found_return = 0, found_stack_adjust = 0; | |
3984 | CORE_ADDR func_start, func_end; | |
3985 | CORE_ADDR scan_pc; | |
3986 | gdb_byte buf[4]; | |
3987 | ||
3988 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3989 | return 0; | |
3990 | ||
3991 | /* The epilogue is a sequence of instructions along the following lines: | |
3992 | ||
3993 | - add stack frame size to SP or FP | |
3994 | - [if frame pointer used] restore SP from FP | |
3995 | - restore registers from SP [may include PC] | |
3996 | - a return-type instruction [if PC wasn't already restored] | |
3997 | ||
3998 | In a first pass, we scan forward from the current PC and verify the | |
3999 | instructions we find as compatible with this sequence, ending in a | |
4000 | return instruction. | |
4001 | ||
4002 | However, this is not sufficient to distinguish indirect function calls | |
4003 | within a function from indirect tail calls in the epilogue in some cases. | |
4004 | Therefore, if we didn't already find any SP-changing instruction during | |
4005 | forward scan, we add a backward scanning heuristic to ensure we actually | |
4006 | are in the epilogue. */ | |
4007 | ||
4008 | scan_pc = pc; | |
4009 | while (scan_pc < func_end && !found_return) | |
4010 | { | |
4011 | if (target_read_memory (scan_pc, buf, 2)) | |
4012 | break; | |
4013 | ||
4014 | scan_pc += 2; | |
4015 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
4016 | ||
4017 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
4018 | found_return = 1; | |
4019 | else if (insn == 0x46f7) /* mov pc, lr */ | |
4020 | found_return = 1; | |
540314bd | 4021 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 4022 | { |
b7576e5c | 4023 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
4024 | found_return = 1; |
4025 | } | |
db24da6d | 4026 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
4027 | { |
4028 | if (target_read_memory (scan_pc, buf, 2)) | |
4029 | break; | |
4030 | ||
4031 | scan_pc += 2; | |
4032 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
4033 | ||
4034 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
4035 | { | |
4024ca99 UW |
4036 | if (insn2 & 0x8000) /* <registers> include PC. */ |
4037 | found_return = 1; | |
4038 | } | |
4039 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
4040 | && (insn2 & 0x0fff) == 0x0b04) | |
4041 | { | |
4024ca99 UW |
4042 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
4043 | found_return = 1; | |
4044 | } | |
4045 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
4046 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 4047 | ; |
4024ca99 UW |
4048 | else |
4049 | break; | |
4050 | } | |
4051 | else | |
4052 | break; | |
4053 | } | |
4054 | ||
4055 | if (!found_return) | |
4056 | return 0; | |
4057 | ||
4058 | /* Since any instruction in the epilogue sequence, with the possible | |
4059 | exception of return itself, updates the stack pointer, we need to | |
4060 | scan backwards for at most one instruction. Try either a 16-bit or | |
4061 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 4062 | too much about false positives. */ |
4024ca99 | 4063 | |
6b65d1b6 YQ |
4064 | if (pc - 4 < func_start) |
4065 | return 0; | |
4066 | if (target_read_memory (pc - 4, buf, 4)) | |
4067 | return 0; | |
4024ca99 | 4068 | |
6b65d1b6 YQ |
4069 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
4070 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
4071 | ||
4072 | if (thumb_instruction_restores_sp (insn2)) | |
4073 | found_stack_adjust = 1; | |
4074 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
4075 | found_stack_adjust = 1; | |
4076 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
4077 | && (insn2 & 0x0fff) == 0x0b04) | |
4078 | found_stack_adjust = 1; | |
4079 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
4080 | && (insn2 & 0x0e00) == 0x0a00) | |
4081 | found_stack_adjust = 1; | |
4024ca99 UW |
4082 | |
4083 | return found_stack_adjust; | |
4084 | } | |
4085 | ||
4024ca99 | 4086 | static int |
c58b006a | 4087 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
4088 | { |
4089 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4090 | unsigned int insn; | |
f303bc3e | 4091 | int found_return; |
4024ca99 UW |
4092 | CORE_ADDR func_start, func_end; |
4093 | ||
4024ca99 UW |
4094 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
4095 | return 0; | |
4096 | ||
4097 | /* We are in the epilogue if the previous instruction was a stack | |
4098 | adjustment and the next instruction is a possible return (bx, mov | |
4099 | pc, or pop). We could have to scan backwards to find the stack | |
4100 | adjustment, or forwards to find the return, but this is a decent | |
4101 | approximation. First scan forwards. */ | |
4102 | ||
4103 | found_return = 0; | |
4104 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
4105 | if (bits (insn, 28, 31) != INST_NV) | |
4106 | { | |
4107 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
4108 | /* BX. */ | |
4109 | found_return = 1; | |
4110 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
4111 | /* MOV PC. */ | |
4112 | found_return = 1; | |
4113 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
4114 | && (insn & 0x0000c000) != 0) | |
4115 | /* POP (LDMIA), including PC or LR. */ | |
4116 | found_return = 1; | |
4117 | } | |
4118 | ||
4119 | if (!found_return) | |
4120 | return 0; | |
4121 | ||
4122 | /* Scan backwards. This is just a heuristic, so do not worry about | |
4123 | false positives from mode changes. */ | |
4124 | ||
4125 | if (pc < func_start + 4) | |
4126 | return 0; | |
4127 | ||
4128 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 4129 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
4130 | return 1; |
4131 | ||
4132 | return 0; | |
4133 | } | |
4134 | ||
c58b006a YQ |
4135 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4136 | ||
4137 | static int | |
4138 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4139 | { | |
4140 | if (arm_pc_is_thumb (gdbarch, pc)) | |
4141 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
4142 | else | |
4143 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
4144 | } | |
4024ca99 | 4145 | |
2dd604e7 RE |
4146 | /* When arguments must be pushed onto the stack, they go on in reverse |
4147 | order. The code below implements a FILO (stack) to do this. */ | |
4148 | ||
0fecb1a7 | 4149 | struct arm_stack_item |
2dd604e7 RE |
4150 | { |
4151 | int len; | |
0fecb1a7 | 4152 | struct arm_stack_item *prev; |
7c543f7b | 4153 | gdb_byte *data; |
2dd604e7 RE |
4154 | }; |
4155 | ||
0fecb1a7 TT |
4156 | static struct arm_stack_item * |
4157 | push_stack_item (struct arm_stack_item *prev, const gdb_byte *contents, | |
4158 | int len) | |
2dd604e7 | 4159 | { |
0fecb1a7 TT |
4160 | struct arm_stack_item *si; |
4161 | si = XNEW (struct arm_stack_item); | |
7c543f7b | 4162 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
4163 | si->len = len; |
4164 | si->prev = prev; | |
4165 | memcpy (si->data, contents, len); | |
4166 | return si; | |
4167 | } | |
4168 | ||
0fecb1a7 TT |
4169 | static struct arm_stack_item * |
4170 | pop_stack_item (struct arm_stack_item *si) | |
2dd604e7 | 4171 | { |
0fecb1a7 | 4172 | struct arm_stack_item *dead = si; |
2dd604e7 RE |
4173 | si = si->prev; |
4174 | xfree (dead->data); | |
4175 | xfree (dead); | |
4176 | return si; | |
4177 | } | |
4178 | ||
030197b4 AB |
4179 | /* Implement the gdbarch type alignment method, overrides the generic |
4180 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 4181 | |
030197b4 AB |
4182 | static ULONGEST |
4183 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 4184 | { |
2af48f68 | 4185 | t = check_typedef (t); |
bd63c870 | 4186 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 4187 | { |
030197b4 AB |
4188 | /* Use the natural alignment for vector types (the same for |
4189 | scalar type), but the maximum alignment is 64-bit. */ | |
df86565b | 4190 | if (t->length () > 8) |
030197b4 | 4191 | return 8; |
c4312b19 | 4192 | else |
df86565b | 4193 | return t->length (); |
2af48f68 | 4194 | } |
030197b4 AB |
4195 | |
4196 | /* Allow the common code to calculate the alignment. */ | |
4197 | return 0; | |
2af48f68 PB |
4198 | } |
4199 | ||
90445bd3 DJ |
4200 | /* Possible base types for a candidate for passing and returning in |
4201 | VFP registers. */ | |
4202 | ||
4203 | enum arm_vfp_cprc_base_type | |
4204 | { | |
4205 | VFP_CPRC_UNKNOWN, | |
4206 | VFP_CPRC_SINGLE, | |
4207 | VFP_CPRC_DOUBLE, | |
4208 | VFP_CPRC_VEC64, | |
4209 | VFP_CPRC_VEC128 | |
4210 | }; | |
4211 | ||
4212 | /* The length of one element of base type B. */ | |
4213 | ||
4214 | static unsigned | |
4215 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
4216 | { | |
4217 | switch (b) | |
4218 | { | |
4219 | case VFP_CPRC_SINGLE: | |
4220 | return 4; | |
4221 | case VFP_CPRC_DOUBLE: | |
4222 | return 8; | |
4223 | case VFP_CPRC_VEC64: | |
4224 | return 8; | |
4225 | case VFP_CPRC_VEC128: | |
4226 | return 16; | |
4227 | default: | |
f34652de | 4228 | internal_error (_("Invalid VFP CPRC type: %d."), |
90445bd3 DJ |
4229 | (int) b); |
4230 | } | |
4231 | } | |
4232 | ||
4233 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
4234 | for passing base type B. */ | |
4235 | ||
4236 | static int | |
4237 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
4238 | { | |
4239 | switch (b) | |
4240 | { | |
4241 | case VFP_CPRC_SINGLE: | |
4242 | return 's'; | |
4243 | case VFP_CPRC_DOUBLE: | |
4244 | return 'd'; | |
4245 | case VFP_CPRC_VEC64: | |
4246 | return 'd'; | |
4247 | case VFP_CPRC_VEC128: | |
4248 | return 'q'; | |
4249 | default: | |
f34652de | 4250 | internal_error (_("Invalid VFP CPRC type: %d."), |
90445bd3 DJ |
4251 | (int) b); |
4252 | } | |
4253 | } | |
4254 | ||
4255 | /* Determine whether T may be part of a candidate for passing and | |
4256 | returning in VFP registers, ignoring the limit on the total number | |
4257 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
4258 | classification of the first valid component found; if it is not | |
4259 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
4260 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
4261 | for passing and returning in VFP registers, a type differently | |
4262 | classified from *BASE_TYPE, or two types differently classified | |
4263 | from each other, return -1, otherwise return the total number of | |
4264 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
4265 | array). Vector types are not currently supported, matching the |
4266 | generic AAPCS support. */ | |
90445bd3 DJ |
4267 | |
4268 | static int | |
4269 | arm_vfp_cprc_sub_candidate (struct type *t, | |
4270 | enum arm_vfp_cprc_base_type *base_type) | |
4271 | { | |
4272 | t = check_typedef (t); | |
78134374 | 4273 | switch (t->code ()) |
90445bd3 DJ |
4274 | { |
4275 | case TYPE_CODE_FLT: | |
df86565b | 4276 | switch (t->length ()) |
90445bd3 DJ |
4277 | { |
4278 | case 4: | |
4279 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4280 | *base_type = VFP_CPRC_SINGLE; | |
4281 | else if (*base_type != VFP_CPRC_SINGLE) | |
4282 | return -1; | |
4283 | return 1; | |
4284 | ||
4285 | case 8: | |
4286 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4287 | *base_type = VFP_CPRC_DOUBLE; | |
4288 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4289 | return -1; | |
4290 | return 1; | |
4291 | ||
4292 | default: | |
4293 | return -1; | |
4294 | } | |
4295 | break; | |
4296 | ||
817e0957 YQ |
4297 | case TYPE_CODE_COMPLEX: |
4298 | /* Arguments of complex T where T is one of the types float or | |
4299 | double get treated as if they are implemented as: | |
4300 | ||
4301 | struct complexT | |
4302 | { | |
4303 | T real; | |
4304 | T imag; | |
5f52445b YQ |
4305 | }; |
4306 | ||
4307 | */ | |
df86565b | 4308 | switch (t->length ()) |
817e0957 YQ |
4309 | { |
4310 | case 8: | |
4311 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4312 | *base_type = VFP_CPRC_SINGLE; | |
4313 | else if (*base_type != VFP_CPRC_SINGLE) | |
4314 | return -1; | |
4315 | return 2; | |
4316 | ||
4317 | case 16: | |
4318 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4319 | *base_type = VFP_CPRC_DOUBLE; | |
4320 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4321 | return -1; | |
4322 | return 2; | |
4323 | ||
4324 | default: | |
4325 | return -1; | |
4326 | } | |
4327 | break; | |
4328 | ||
90445bd3 DJ |
4329 | case TYPE_CODE_ARRAY: |
4330 | { | |
bd63c870 | 4331 | if (t->is_vector ()) |
90445bd3 | 4332 | { |
c4312b19 YQ |
4333 | /* A 64-bit or 128-bit containerized vector type are VFP |
4334 | CPRCs. */ | |
df86565b | 4335 | switch (t->length ()) |
c4312b19 YQ |
4336 | { |
4337 | case 8: | |
4338 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4339 | *base_type = VFP_CPRC_VEC64; | |
4340 | return 1; | |
4341 | case 16: | |
4342 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4343 | *base_type = VFP_CPRC_VEC128; | |
4344 | return 1; | |
4345 | default: | |
4346 | return -1; | |
4347 | } | |
4348 | } | |
4349 | else | |
4350 | { | |
4351 | int count; | |
4352 | unsigned unitlen; | |
4353 | ||
27710edb | 4354 | count = arm_vfp_cprc_sub_candidate (t->target_type (), |
c4312b19 YQ |
4355 | base_type); |
4356 | if (count == -1) | |
4357 | return -1; | |
df86565b | 4358 | if (t->length () == 0) |
c4312b19 YQ |
4359 | { |
4360 | gdb_assert (count == 0); | |
4361 | return 0; | |
4362 | } | |
4363 | else if (count == 0) | |
4364 | return -1; | |
4365 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b SM |
4366 | gdb_assert ((t->length () % unitlen) == 0); |
4367 | return t->length () / unitlen; | |
90445bd3 | 4368 | } |
90445bd3 DJ |
4369 | } |
4370 | break; | |
4371 | ||
4372 | case TYPE_CODE_STRUCT: | |
4373 | { | |
4374 | int count = 0; | |
4375 | unsigned unitlen; | |
4376 | int i; | |
1f704f76 | 4377 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4378 | { |
1040b979 YQ |
4379 | int sub_count = 0; |
4380 | ||
ceacbf6e | 4381 | if (!field_is_static (&t->field (i))) |
940da03e | 4382 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 4383 | base_type); |
90445bd3 DJ |
4384 | if (sub_count == -1) |
4385 | return -1; | |
4386 | count += sub_count; | |
4387 | } | |
df86565b | 4388 | if (t->length () == 0) |
90445bd3 DJ |
4389 | { |
4390 | gdb_assert (count == 0); | |
4391 | return 0; | |
4392 | } | |
4393 | else if (count == 0) | |
4394 | return -1; | |
4395 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b | 4396 | if (t->length () != unitlen * count) |
90445bd3 DJ |
4397 | return -1; |
4398 | return count; | |
4399 | } | |
4400 | ||
4401 | case TYPE_CODE_UNION: | |
4402 | { | |
4403 | int count = 0; | |
4404 | unsigned unitlen; | |
4405 | int i; | |
1f704f76 | 4406 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4407 | { |
940da03e | 4408 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
4409 | base_type); |
4410 | if (sub_count == -1) | |
4411 | return -1; | |
4412 | count = (count > sub_count ? count : sub_count); | |
4413 | } | |
df86565b | 4414 | if (t->length () == 0) |
90445bd3 DJ |
4415 | { |
4416 | gdb_assert (count == 0); | |
4417 | return 0; | |
4418 | } | |
4419 | else if (count == 0) | |
4420 | return -1; | |
4421 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b | 4422 | if (t->length () != unitlen * count) |
90445bd3 DJ |
4423 | return -1; |
4424 | return count; | |
4425 | } | |
4426 | ||
4427 | default: | |
4428 | break; | |
4429 | } | |
4430 | ||
4431 | return -1; | |
4432 | } | |
4433 | ||
4434 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
4435 | if passed to or returned from a non-variadic function with the VFP | |
4436 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
4437 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
4438 | elements of that base type before returning. */ | |
4439 | ||
4440 | static int | |
4441 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
4442 | int *count) | |
4443 | { | |
4444 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
4445 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
4446 | if (c <= 0 || c > 4) | |
4447 | return 0; | |
4448 | *base_type = b; | |
4449 | *count = c; | |
4450 | return 1; | |
4451 | } | |
4452 | ||
4453 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
4454 | returning values from a function of type FUNC_TYPE, 0 | |
4455 | otherwise. */ | |
4456 | ||
4457 | static int | |
4458 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
4459 | { | |
08106042 | 4460 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 4461 | |
90445bd3 DJ |
4462 | /* Variadic functions always use the base ABI. Assume that functions |
4463 | without debug info are not variadic. */ | |
a409645d | 4464 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 | 4465 | return 0; |
345bd07c | 4466 | |
90445bd3 DJ |
4467 | /* The VFP ABI is only supported as a variant of AAPCS. */ |
4468 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
4469 | return 0; | |
345bd07c SM |
4470 | |
4471 | return tdep->fp_model == ARM_FLOAT_VFP; | |
90445bd3 DJ |
4472 | } |
4473 | ||
4474 | /* We currently only support passing parameters in integer registers, which | |
4475 | conforms with GCC's default model, and VFP argument passing following | |
4476 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
4477 | we should probably support some of them based on the selected ABI. */ |
4478 | ||
4479 | static CORE_ADDR | |
7d9b040b | 4480 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 4481 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
4482 | struct value **args, CORE_ADDR sp, |
4483 | function_call_return_method return_method, | |
6a65450a | 4484 | CORE_ADDR struct_addr) |
2dd604e7 | 4485 | { |
e17a4113 | 4486 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
4487 | int argnum; |
4488 | int argreg; | |
4489 | int nstack; | |
0fecb1a7 | 4490 | struct arm_stack_item *si = NULL; |
90445bd3 DJ |
4491 | int use_vfp_abi; |
4492 | struct type *ftype; | |
4493 | unsigned vfp_regs_free = (1 << 16) - 1; | |
08106042 | 4494 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
90445bd3 DJ |
4495 | |
4496 | /* Determine the type of this function and whether the VFP ABI | |
4497 | applies. */ | |
4498 | ftype = check_typedef (value_type (function)); | |
78134374 | 4499 | if (ftype->code () == TYPE_CODE_PTR) |
27710edb | 4500 | ftype = check_typedef (ftype->target_type ()); |
90445bd3 | 4501 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); |
2dd604e7 | 4502 | |
6a65450a AC |
4503 | /* Set the return address. For the ARM, the return breakpoint is |
4504 | always at BP_ADDR. */ | |
9779414d | 4505 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 4506 | bp_addr |= 1; |
6a65450a | 4507 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
4508 | |
4509 | /* Walk through the list of args and determine how large a temporary | |
4510 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 4511 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
4512 | nstack = 0; |
4513 | ||
4514 | argreg = ARM_A1_REGNUM; | |
4515 | nstack = 0; | |
4516 | ||
2dd604e7 RE |
4517 | /* The struct_return pointer occupies the first parameter |
4518 | passing register. */ | |
cf84fa6b | 4519 | if (return_method == return_method_struct) |
2dd604e7 | 4520 | { |
7cb6d92a SM |
4521 | arm_debug_printf ("struct return in %s = %s", |
4522 | gdbarch_register_name (gdbarch, argreg), | |
4523 | paddress (gdbarch, struct_addr)); | |
4524 | ||
2dd604e7 RE |
4525 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
4526 | argreg++; | |
4527 | } | |
4528 | ||
4529 | for (argnum = 0; argnum < nargs; argnum++) | |
4530 | { | |
4531 | int len; | |
4532 | struct type *arg_type; | |
4533 | struct type *target_type; | |
4534 | enum type_code typecode; | |
8c6363cf | 4535 | const bfd_byte *val; |
2af48f68 | 4536 | int align; |
90445bd3 DJ |
4537 | enum arm_vfp_cprc_base_type vfp_base_type; |
4538 | int vfp_base_count; | |
4539 | int may_use_core_reg = 1; | |
2dd604e7 | 4540 | |
df407dfe | 4541 | arg_type = check_typedef (value_type (args[argnum])); |
df86565b | 4542 | len = arg_type->length (); |
27710edb | 4543 | target_type = arg_type->target_type (); |
78134374 | 4544 | typecode = arg_type->code (); |
50888e42 | 4545 | val = value_contents (args[argnum]).data (); |
2dd604e7 | 4546 | |
030197b4 | 4547 | align = type_align (arg_type); |
2af48f68 | 4548 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
4549 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
4550 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 | 4551 | /* Different ABIs have different maximum alignments. */ |
345bd07c | 4552 | if (tdep->arm_abi == ARM_ABI_APCS) |
2af48f68 PB |
4553 | { |
4554 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 4555 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
4556 | } |
4557 | else | |
4558 | { | |
4559 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
4560 | if (align > ARM_INT_REGISTER_SIZE * 2) |
4561 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
4562 | } |
4563 | ||
90445bd3 DJ |
4564 | if (use_vfp_abi |
4565 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
4566 | &vfp_base_count)) | |
4567 | { | |
4568 | int regno; | |
4569 | int unit_length; | |
4570 | int shift; | |
4571 | unsigned mask; | |
4572 | ||
4573 | /* Because this is a CPRC it cannot go in a core register or | |
4574 | cause a core register to be skipped for alignment. | |
4575 | Either it goes in VFP registers and the rest of this loop | |
4576 | iteration is skipped for this argument, or it goes on the | |
4577 | stack (and the stack alignment code is correct for this | |
4578 | case). */ | |
4579 | may_use_core_reg = 0; | |
4580 | ||
4581 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
4582 | shift = unit_length / 4; | |
4583 | mask = (1 << (shift * vfp_base_count)) - 1; | |
4584 | for (regno = 0; regno < 16; regno += shift) | |
4585 | if (((vfp_regs_free >> regno) & mask) == mask) | |
4586 | break; | |
4587 | ||
4588 | if (regno < 16) | |
4589 | { | |
4590 | int reg_char; | |
4591 | int reg_scaled; | |
4592 | int i; | |
4593 | ||
4594 | vfp_regs_free &= ~(mask << regno); | |
4595 | reg_scaled = regno / shift; | |
4596 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
4597 | for (i = 0; i < vfp_base_count; i++) | |
4598 | { | |
4599 | char name_buf[4]; | |
4600 | int regnum; | |
58d6951d DJ |
4601 | if (reg_char == 'q') |
4602 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 4603 | val + i * unit_length); |
58d6951d DJ |
4604 | else |
4605 | { | |
8c042590 PM |
4606 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
4607 | reg_char, reg_scaled + i); | |
58d6951d DJ |
4608 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
4609 | strlen (name_buf)); | |
b66f5587 | 4610 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 4611 | } |
90445bd3 DJ |
4612 | } |
4613 | continue; | |
4614 | } | |
4615 | else | |
4616 | { | |
4617 | /* This CPRC could not go in VFP registers, so all VFP | |
4618 | registers are now marked as used. */ | |
4619 | vfp_regs_free = 0; | |
4620 | } | |
4621 | } | |
4622 | ||
85102364 | 4623 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
4624 | if (nstack & (align - 1)) |
4625 | { | |
f0452268 AH |
4626 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
4627 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
4628 | } |
4629 | ||
4630 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
4631 | if (may_use_core_reg |
4632 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 4633 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
4634 | && argreg & 1) |
4635 | argreg++; | |
4636 | ||
2dd604e7 RE |
4637 | /* If the argument is a pointer to a function, and it is a |
4638 | Thumb function, create a LOCAL copy of the value and set | |
4639 | the THUMB bit in it. */ | |
4640 | if (TYPE_CODE_PTR == typecode | |
4641 | && target_type != NULL | |
78134374 | 4642 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 4643 | { |
e17a4113 | 4644 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 4645 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 4646 | { |
224c3ddb | 4647 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 4648 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 4649 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 4650 | val = copy; |
2dd604e7 RE |
4651 | } |
4652 | } | |
4653 | ||
4654 | /* Copy the argument to general registers or the stack in | |
4655 | register-sized pieces. Large arguments are split between | |
4656 | registers and stack. */ | |
4657 | while (len > 0) | |
4658 | { | |
f0452268 AH |
4659 | int partial_len = len < ARM_INT_REGISTER_SIZE |
4660 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
4661 | CORE_ADDR regval |
4662 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 4663 | |
90445bd3 | 4664 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
4665 | { |
4666 | /* The argument is being passed in a general purpose | |
4667 | register. */ | |
e17a4113 | 4668 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 4669 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
7cb6d92a SM |
4670 | |
4671 | arm_debug_printf ("arg %d in %s = 0x%s", argnum, | |
4672 | gdbarch_register_name (gdbarch, argreg), | |
4673 | phex (regval, ARM_INT_REGISTER_SIZE)); | |
4674 | ||
2dd604e7 RE |
4675 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
4676 | argreg++; | |
4677 | } | |
4678 | else | |
4679 | { | |
f0452268 | 4680 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
4681 | |
4682 | memset (buf, 0, sizeof (buf)); | |
4683 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
4684 | ||
2dd604e7 | 4685 | /* Push the arguments onto the stack. */ |
7cb6d92a | 4686 | arm_debug_printf ("arg %d @ sp + %d", argnum, nstack); |
f0452268 AH |
4687 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
4688 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
4689 | } |
4690 | ||
4691 | len -= partial_len; | |
4692 | val += partial_len; | |
4693 | } | |
4694 | } | |
4695 | /* If we have an odd number of words to push, then decrement the stack | |
4696 | by one word now, so first stack argument will be dword aligned. */ | |
4697 | if (nstack & 4) | |
4698 | sp -= 4; | |
4699 | ||
4700 | while (si) | |
4701 | { | |
4702 | sp -= si->len; | |
4703 | write_memory (sp, si->data, si->len); | |
4704 | si = pop_stack_item (si); | |
4705 | } | |
4706 | ||
4707 | /* Finally, update teh SP register. */ | |
4708 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
4709 | ||
4710 | return sp; | |
4711 | } | |
4712 | ||
f53f0d0b PB |
4713 | |
4714 | /* Always align the frame to an 8-byte boundary. This is required on | |
4715 | some platforms and harmless on the rest. */ | |
4716 | ||
4717 | static CORE_ADDR | |
4718 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
4719 | { | |
4720 | /* Align the stack to eight bytes. */ | |
4721 | return sp & ~ (CORE_ADDR) 7; | |
4722 | } | |
4723 | ||
c906108c | 4724 | static void |
12b27276 | 4725 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 4726 | { |
c5aa993b | 4727 | if (flags & (1 << 0)) |
0426ad51 | 4728 | gdb_puts ("IVO ", file); |
c5aa993b | 4729 | if (flags & (1 << 1)) |
0426ad51 | 4730 | gdb_puts ("DVZ ", file); |
c5aa993b | 4731 | if (flags & (1 << 2)) |
0426ad51 | 4732 | gdb_puts ("OFL ", file); |
c5aa993b | 4733 | if (flags & (1 << 3)) |
0426ad51 | 4734 | gdb_puts ("UFL ", file); |
c5aa993b | 4735 | if (flags & (1 << 4)) |
0426ad51 | 4736 | gdb_puts ("INX ", file); |
a11ac3b3 | 4737 | gdb_putc ('\n', file); |
c906108c SS |
4738 | } |
4739 | ||
5e74b15c RE |
4740 | /* Print interesting information about the floating point processor |
4741 | (if present) or emulator. */ | |
34e8f22d | 4742 | static void |
d855c300 | 4743 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 4744 | frame_info_ptr frame, const char *args) |
c906108c | 4745 | { |
9c9acae0 | 4746 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4747 | int type; |
4748 | ||
4749 | type = (status >> 24) & 127; | |
edefbb7c | 4750 | if (status & (1 << 31)) |
6cb06a8c | 4751 | gdb_printf (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4752 | else |
6cb06a8c | 4753 | gdb_printf (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4754 | /* i18n: [floating point unit] mask */ |
0426ad51 | 4755 | gdb_puts (_("mask: "), file); |
12b27276 | 4756 | print_fpu_flags (file, status >> 16); |
edefbb7c | 4757 | /* i18n: [floating point unit] flags */ |
0426ad51 | 4758 | gdb_puts (_("flags: "), file); |
12b27276 | 4759 | print_fpu_flags (file, status); |
c906108c SS |
4760 | } |
4761 | ||
27067745 UW |
4762 | /* Construct the ARM extended floating point type. */ |
4763 | static struct type * | |
4764 | arm_ext_type (struct gdbarch *gdbarch) | |
4765 | { | |
08106042 | 4766 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
27067745 UW |
4767 | |
4768 | if (!tdep->arm_ext_type) | |
4769 | tdep->arm_ext_type | |
e9bb382b | 4770 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4771 | floatformats_arm_ext); |
4772 | ||
4773 | return tdep->arm_ext_type; | |
4774 | } | |
4775 | ||
58d6951d DJ |
4776 | static struct type * |
4777 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4778 | { | |
08106042 | 4779 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4780 | |
4781 | if (tdep->neon_double_type == NULL) | |
4782 | { | |
4783 | struct type *t, *elem; | |
4784 | ||
4785 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4786 | TYPE_CODE_UNION); | |
4787 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4788 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4789 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4790 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4791 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4792 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4793 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4794 | append_composite_type_field (t, "u64", elem); | |
4795 | elem = builtin_type (gdbarch)->builtin_float; | |
4796 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4797 | elem = builtin_type (gdbarch)->builtin_double; | |
4798 | append_composite_type_field (t, "f64", elem); | |
4799 | ||
2062087b | 4800 | t->set_is_vector (true); |
d0e39ea2 | 4801 | t->set_name ("neon_d"); |
58d6951d DJ |
4802 | tdep->neon_double_type = t; |
4803 | } | |
4804 | ||
4805 | return tdep->neon_double_type; | |
4806 | } | |
4807 | ||
4808 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4809 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4810 | bits of d0 - regardless of what unit size is being held in d0. So | |
4811 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4812 | first float is 4. This code works as-is for little-endian | |
4813 | targets. */ | |
4814 | ||
4815 | static struct type * | |
4816 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4817 | { | |
08106042 | 4818 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4819 | |
4820 | if (tdep->neon_quad_type == NULL) | |
4821 | { | |
4822 | struct type *t, *elem; | |
4823 | ||
4824 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4825 | TYPE_CODE_UNION); | |
4826 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4827 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4828 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4829 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4830 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4831 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4832 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4833 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4834 | elem = builtin_type (gdbarch)->builtin_float; | |
4835 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4836 | elem = builtin_type (gdbarch)->builtin_double; | |
4837 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4838 | ||
2062087b | 4839 | t->set_is_vector (true); |
d0e39ea2 | 4840 | t->set_name ("neon_q"); |
58d6951d DJ |
4841 | tdep->neon_quad_type = t; |
4842 | } | |
4843 | ||
4844 | return tdep->neon_quad_type; | |
4845 | } | |
4846 | ||
ecbf5d4f LM |
4847 | /* Return true if REGNUM is a Q pseudo register. Return false |
4848 | otherwise. | |
4849 | ||
4850 | REGNUM is the raw register number and not a pseudo-relative register | |
4851 | number. */ | |
4852 | ||
4853 | static bool | |
4854 | is_q_pseudo (struct gdbarch *gdbarch, int regnum) | |
4855 | { | |
08106042 | 4856 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f | 4857 | |
ae66a8f1 SP |
4858 | /* Q pseudo registers are available for both NEON (Q0~Q15) and |
4859 | MVE (Q0~Q7) features. */ | |
ecbf5d4f LM |
4860 | if (tdep->have_q_pseudos |
4861 | && regnum >= tdep->q_pseudo_base | |
4862 | && regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count)) | |
4863 | return true; | |
4864 | ||
4865 | return false; | |
4866 | } | |
4867 | ||
4868 | /* Return true if REGNUM is a VFP S pseudo register. Return false | |
4869 | otherwise. | |
4870 | ||
4871 | REGNUM is the raw register number and not a pseudo-relative register | |
4872 | number. */ | |
4873 | ||
4874 | static bool | |
4875 | is_s_pseudo (struct gdbarch *gdbarch, int regnum) | |
4876 | { | |
08106042 | 4877 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f LM |
4878 | |
4879 | if (tdep->have_s_pseudos | |
4880 | && regnum >= tdep->s_pseudo_base | |
4881 | && regnum < (tdep->s_pseudo_base + tdep->s_pseudo_count)) | |
4882 | return true; | |
4883 | ||
4884 | return false; | |
4885 | } | |
4886 | ||
ae66a8f1 SP |
4887 | /* Return true if REGNUM is a MVE pseudo register (P0). Return false |
4888 | otherwise. | |
4889 | ||
4890 | REGNUM is the raw register number and not a pseudo-relative register | |
4891 | number. */ | |
4892 | ||
4893 | static bool | |
4894 | is_mve_pseudo (struct gdbarch *gdbarch, int regnum) | |
4895 | { | |
08106042 | 4896 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
4897 | |
4898 | if (tdep->have_mve | |
4899 | && regnum >= tdep->mve_pseudo_base | |
4900 | && regnum < tdep->mve_pseudo_base + tdep->mve_pseudo_count) | |
4901 | return true; | |
4902 | ||
4903 | return false; | |
4904 | } | |
4905 | ||
a01567f4 LM |
4906 | /* Return true if REGNUM is a PACBTI pseudo register (ra_auth_code). Return |
4907 | false otherwise. | |
4908 | ||
4909 | REGNUM is the raw register number and not a pseudo-relative register | |
4910 | number. */ | |
4911 | ||
4912 | static bool | |
4913 | is_pacbti_pseudo (struct gdbarch *gdbarch, int regnum) | |
4914 | { | |
08106042 | 4915 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
4916 | |
4917 | if (tdep->have_pacbti | |
4918 | && regnum >= tdep->pacbti_pseudo_base | |
4919 | && regnum < tdep->pacbti_pseudo_base + tdep->pacbti_pseudo_count) | |
4920 | return true; | |
4921 | ||
4922 | return false; | |
4923 | } | |
4924 | ||
34e8f22d RE |
4925 | /* Return the GDB type object for the "standard" data type of data in |
4926 | register N. */ | |
4927 | ||
4928 | static struct type * | |
7a5ea0d4 | 4929 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4930 | { |
08106042 | 4931 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 4932 | |
ecbf5d4f | 4933 | if (is_s_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4934 | return builtin_type (gdbarch)->builtin_float; |
4935 | ||
ecbf5d4f | 4936 | if (is_q_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4937 | return arm_neon_quad_type (gdbarch); |
4938 | ||
ae66a8f1 SP |
4939 | if (is_mve_pseudo (gdbarch, regnum)) |
4940 | return builtin_type (gdbarch)->builtin_int16; | |
4941 | ||
a01567f4 LM |
4942 | if (is_pacbti_pseudo (gdbarch, regnum)) |
4943 | return builtin_type (gdbarch)->builtin_uint32; | |
4944 | ||
58d6951d DJ |
4945 | /* If the target description has register information, we are only |
4946 | in this function so that we can override the types of | |
4947 | double-precision registers for NEON. */ | |
4948 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4949 | { | |
4950 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4951 | ||
4952 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 4953 | && t->code () == TYPE_CODE_FLT |
ecbf5d4f | 4954 | && tdep->have_neon) |
58d6951d DJ |
4955 | return arm_neon_double_type (gdbarch); |
4956 | else | |
4957 | return t; | |
4958 | } | |
4959 | ||
34e8f22d | 4960 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d | 4961 | { |
ecbf5d4f | 4962 | if (!tdep->have_fpa_registers) |
58d6951d DJ |
4963 | return builtin_type (gdbarch)->builtin_void; |
4964 | ||
4965 | return arm_ext_type (gdbarch); | |
4966 | } | |
e4c16157 | 4967 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4968 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4969 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4970 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4971 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4972 | /* These registers are only supported on targets which supply | |
4973 | an XML description. */ | |
df4df182 | 4974 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4975 | else |
df4df182 | 4976 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4977 | } |
4978 | ||
ff6f572f DJ |
4979 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4980 | number. */ | |
4981 | ||
4982 | static int | |
d3f73121 | 4983 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4984 | { |
4985 | /* Core integer regs. */ | |
4986 | if (reg >= 0 && reg <= 15) | |
4987 | return reg; | |
4988 | ||
4989 | /* Legacy FPA encoding. These were once used in a way which | |
4990 | overlapped with VFP register numbering, so their use is | |
4991 | discouraged, but GDB doesn't support the ARM toolchain | |
4992 | which used them for VFP. */ | |
4993 | if (reg >= 16 && reg <= 23) | |
4994 | return ARM_F0_REGNUM + reg - 16; | |
4995 | ||
4996 | /* New assignments for the FPA registers. */ | |
4997 | if (reg >= 96 && reg <= 103) | |
4998 | return ARM_F0_REGNUM + reg - 96; | |
4999 | ||
5000 | /* WMMX register assignments. */ | |
5001 | if (reg >= 104 && reg <= 111) | |
5002 | return ARM_WCGR0_REGNUM + reg - 104; | |
5003 | ||
5004 | if (reg >= 112 && reg <= 127) | |
5005 | return ARM_WR0_REGNUM + reg - 112; | |
5006 | ||
a01567f4 LM |
5007 | /* PACBTI register containing the Pointer Authentication Code. */ |
5008 | if (reg == ARM_DWARF_RA_AUTH_CODE) | |
5009 | { | |
08106042 | 5010 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
5011 | |
5012 | if (tdep->have_pacbti) | |
5013 | return tdep->pacbti_pseudo_base; | |
5014 | ||
5015 | return -1; | |
5016 | } | |
5017 | ||
ff6f572f DJ |
5018 | if (reg >= 192 && reg <= 199) |
5019 | return ARM_WC0_REGNUM + reg - 192; | |
5020 | ||
58d6951d DJ |
5021 | /* VFP v2 registers. A double precision value is actually |
5022 | in d1 rather than s2, but the ABI only defines numbering | |
5023 | for the single precision registers. This will "just work" | |
5024 | in GDB for little endian targets (we'll read eight bytes, | |
5025 | starting in s0 and then progressing to s1), but will be | |
5026 | reversed on big endian targets with VFP. This won't | |
5027 | be a problem for the new Neon quad registers; you're supposed | |
5028 | to use DW_OP_piece for those. */ | |
5029 | if (reg >= 64 && reg <= 95) | |
5030 | { | |
5031 | char name_buf[4]; | |
5032 | ||
8c042590 | 5033 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
5034 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
5035 | strlen (name_buf)); | |
5036 | } | |
5037 | ||
5038 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
5039 | registers, except that it now describes d0 instead of s0. */ | |
5040 | if (reg >= 256 && reg <= 287) | |
5041 | { | |
5042 | char name_buf[4]; | |
5043 | ||
8c042590 | 5044 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
5045 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
5046 | strlen (name_buf)); | |
5047 | } | |
5048 | ||
ff6f572f DJ |
5049 | return -1; |
5050 | } | |
5051 | ||
26216b98 AC |
5052 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
5053 | static int | |
e7faf938 | 5054 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
5055 | { |
5056 | int reg = regnum; | |
e7faf938 | 5057 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 5058 | |
ff6f572f DJ |
5059 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
5060 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
5061 | ||
5062 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
5063 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
5064 | ||
5065 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
5066 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
5067 | ||
26216b98 AC |
5068 | if (reg < NUM_GREGS) |
5069 | return SIM_ARM_R0_REGNUM + reg; | |
5070 | reg -= NUM_GREGS; | |
5071 | ||
5072 | if (reg < NUM_FREGS) | |
5073 | return SIM_ARM_FP0_REGNUM + reg; | |
5074 | reg -= NUM_FREGS; | |
5075 | ||
5076 | if (reg < NUM_SREGS) | |
5077 | return SIM_ARM_FPS_REGNUM + reg; | |
5078 | reg -= NUM_SREGS; | |
5079 | ||
f34652de | 5080 | internal_error (_("Bad REGNUM %d"), regnum); |
26216b98 | 5081 | } |
34e8f22d | 5082 | |
a01567f4 LM |
5083 | static const unsigned char op_lit0 = DW_OP_lit0; |
5084 | ||
5085 | static void | |
5086 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
5087 | struct dwarf2_frame_state_reg *reg, | |
bd2b40ac | 5088 | frame_info_ptr this_frame) |
a01567f4 | 5089 | { |
a6e4a48c YR |
5090 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
5091 | ||
a01567f4 LM |
5092 | if (is_pacbti_pseudo (gdbarch, regnum)) |
5093 | { | |
5094 | /* Initialize RA_AUTH_CODE to zero. */ | |
5095 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
5096 | reg->loc.exp.start = &op_lit0; | |
5097 | reg->loc.exp.len = 1; | |
5098 | return; | |
5099 | } | |
5100 | ||
42e11f36 | 5101 | if (regnum == ARM_PC_REGNUM || regnum == ARM_PS_REGNUM) |
a01567f4 | 5102 | { |
a01567f4 LM |
5103 | reg->how = DWARF2_FRAME_REG_FN; |
5104 | reg->loc.fn = arm_dwarf2_prev_register; | |
a01567f4 | 5105 | } |
42e11f36 TS |
5106 | else if (regnum == ARM_SP_REGNUM) |
5107 | reg->how = DWARF2_FRAME_REG_CFA; | |
a6e4a48c YR |
5108 | else if (arm_is_alternative_sp_register (tdep, regnum)) |
5109 | { | |
5110 | /* Handle the alternative SP registers on Cortex-M. */ | |
5111 | reg->how = DWARF2_FRAME_REG_FN; | |
5112 | reg->loc.fn = arm_dwarf2_prev_register; | |
5113 | } | |
a01567f4 LM |
5114 | } |
5115 | ||
d9311bfa AT |
5116 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
5117 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
5118 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 5119 | |
d9311bfa AT |
5120 | static gdb_byte * |
5121 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
5122 | int old_len, int new_len) | |
5123 | { | |
5124 | gdb_byte *new_buf; | |
5125 | int bytes_to_read = new_len - old_len; | |
c906108c | 5126 | |
d9311bfa AT |
5127 | new_buf = (gdb_byte *) xmalloc (new_len); |
5128 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
5129 | xfree (buf); | |
198cd59d | 5130 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
5131 | { |
5132 | xfree (new_buf); | |
5133 | return NULL; | |
c906108c | 5134 | } |
d9311bfa | 5135 | return new_buf; |
c906108c SS |
5136 | } |
5137 | ||
d9311bfa AT |
5138 | /* An IT block is at most the 2-byte IT instruction followed by |
5139 | four 4-byte instructions. The furthest back we must search to | |
5140 | find an IT block that affects the current instruction is thus | |
5141 | 2 + 3 * 4 == 14 bytes. */ | |
5142 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 5143 | |
d9311bfa AT |
5144 | /* Use a quick scan if there are more than this many bytes of |
5145 | code. */ | |
5146 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 5147 | |
d9311bfa AT |
5148 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
5149 | A breakpoint in an IT block may not be hit, depending on the | |
5150 | condition flags. */ | |
ad527d2e | 5151 | static CORE_ADDR |
d9311bfa | 5152 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 5153 | { |
d9311bfa AT |
5154 | gdb_byte *buf; |
5155 | char map_type; | |
5156 | CORE_ADDR boundary, func_start; | |
5157 | int buf_len; | |
5158 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
5159 | int i, any, last_it, last_it_count; | |
08106042 | 5160 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 5161 | |
d9311bfa | 5162 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
345bd07c | 5163 | if (tdep->thumb2_breakpoint == NULL) |
d9311bfa | 5164 | return bpaddr; |
177321bd | 5165 | |
d9311bfa AT |
5166 | /* ARM mode does not have this problem. */ |
5167 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
5168 | return bpaddr; | |
177321bd | 5169 | |
d9311bfa AT |
5170 | /* We are setting a breakpoint in Thumb code that could potentially |
5171 | contain an IT block. The first step is to find how much Thumb | |
5172 | code there is; we do not need to read outside of known Thumb | |
5173 | sequences. */ | |
5174 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
5175 | if (map_type == 0) | |
5176 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
5177 | return bpaddr; | |
9dca5578 | 5178 | |
d9311bfa | 5179 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 5180 | |
d9311bfa AT |
5181 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
5182 | && func_start > boundary) | |
5183 | boundary = func_start; | |
9dca5578 | 5184 | |
d9311bfa AT |
5185 | /* Search for a candidate IT instruction. We have to do some fancy |
5186 | footwork to distinguish a real IT instruction from the second | |
5187 | half of a 32-bit instruction, but there is no need for that if | |
5188 | there's no candidate. */ | |
325fac50 | 5189 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
5190 | if (buf_len == 0) |
5191 | /* No room for an IT instruction. */ | |
5192 | return bpaddr; | |
c906108c | 5193 | |
d9311bfa | 5194 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 5195 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
5196 | return bpaddr; |
5197 | any = 0; | |
5198 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 5199 | { |
d9311bfa AT |
5200 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
5201 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 5202 | { |
d9311bfa AT |
5203 | any = 1; |
5204 | break; | |
25b41d01 | 5205 | } |
c906108c | 5206 | } |
d9311bfa AT |
5207 | |
5208 | if (any == 0) | |
c906108c | 5209 | { |
d9311bfa AT |
5210 | xfree (buf); |
5211 | return bpaddr; | |
f9d67f43 DJ |
5212 | } |
5213 | ||
5214 | /* OK, the code bytes before this instruction contain at least one | |
5215 | halfword which resembles an IT instruction. We know that it's | |
5216 | Thumb code, but there are still two possibilities. Either the | |
5217 | halfword really is an IT instruction, or it is the second half of | |
5218 | a 32-bit Thumb instruction. The only way we can tell is to | |
5219 | scan forwards from a known instruction boundary. */ | |
5220 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
5221 | { | |
5222 | int definite; | |
5223 | ||
5224 | /* There's a lot of code before this instruction. Start with an | |
5225 | optimistic search; it's easy to recognize halfwords that can | |
5226 | not be the start of a 32-bit instruction, and use that to | |
5227 | lock on to the instruction boundaries. */ | |
5228 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
5229 | if (buf == NULL) | |
5230 | return bpaddr; | |
5231 | buf_len = IT_SCAN_THRESHOLD; | |
5232 | ||
5233 | definite = 0; | |
5234 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
5235 | { | |
5236 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5237 | if (thumb_insn_size (inst1) == 2) | |
5238 | { | |
5239 | definite = 1; | |
5240 | break; | |
5241 | } | |
5242 | } | |
5243 | ||
5244 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
5245 | are sure that we know the instruction boundaries, and it is far | |
5246 | enough from BPADDR that we could not miss an IT instruction | |
5247 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
5248 | known boundary. */ | |
5249 | if (! definite) | |
5250 | { | |
0963b4bd MS |
5251 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
5252 | bpaddr - boundary); | |
f9d67f43 DJ |
5253 | if (buf == NULL) |
5254 | return bpaddr; | |
5255 | buf_len = bpaddr - boundary; | |
5256 | i = 0; | |
5257 | } | |
5258 | } | |
5259 | else | |
5260 | { | |
5261 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
5262 | if (buf == NULL) | |
5263 | return bpaddr; | |
5264 | buf_len = bpaddr - boundary; | |
5265 | i = 0; | |
5266 | } | |
5267 | ||
5268 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
5269 | last_it = -1; | |
5270 | last_it_count = 0; | |
5271 | while (i < buf_len) | |
5272 | { | |
5273 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5274 | last_it_count--; | |
5275 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
5276 | { | |
5277 | last_it = i; | |
5278 | if (inst1 & 0x0001) | |
5279 | last_it_count = 4; | |
5280 | else if (inst1 & 0x0002) | |
5281 | last_it_count = 3; | |
5282 | else if (inst1 & 0x0004) | |
5283 | last_it_count = 2; | |
5284 | else | |
5285 | last_it_count = 1; | |
5286 | } | |
5287 | i += thumb_insn_size (inst1); | |
5288 | } | |
5289 | ||
5290 | xfree (buf); | |
5291 | ||
5292 | if (last_it == -1) | |
5293 | /* There wasn't really an IT instruction after all. */ | |
5294 | return bpaddr; | |
5295 | ||
5296 | if (last_it_count < 1) | |
5297 | /* It was too far away. */ | |
5298 | return bpaddr; | |
5299 | ||
5300 | /* This really is a trouble spot. Move the breakpoint to the IT | |
5301 | instruction. */ | |
5302 | return bpaddr - buf_len + last_it; | |
5303 | } | |
5304 | ||
cca44b1b | 5305 | /* ARM displaced stepping support. |
c906108c | 5306 | |
cca44b1b | 5307 | Generally ARM displaced stepping works as follows: |
c906108c | 5308 | |
cca44b1b | 5309 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
5310 | arm_process_displaced_insn. Depending on the type of instruction, it is |
5311 | then copied to a scratch location, possibly in a modified form. The | |
5312 | copy_* set of functions performs such modification, as necessary. A | |
5313 | breakpoint is placed after the modified instruction in the scratch space | |
5314 | to return control to GDB. Note in particular that instructions which | |
5315 | modify the PC will no longer do so after modification. | |
c5aa993b | 5316 | |
cca44b1b JB |
5317 | 2. The instruction is single-stepped, by setting the PC to the scratch |
5318 | location address, and resuming. Control returns to GDB when the | |
5319 | breakpoint is hit. | |
c5aa993b | 5320 | |
cca44b1b JB |
5321 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
5322 | function used for the current instruction. This function's job is to | |
5323 | put the CPU/memory state back to what it would have been if the | |
5324 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 5325 | |
cca44b1b JB |
5326 | /* NOP instruction (mov r0, r0). */ |
5327 | #define ARM_NOP 0xe1a00000 | |
34518530 | 5328 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
5329 | |
5330 | /* Helper for register reads for displaced stepping. In particular, this | |
5331 | returns the PC as it would be seen by the instruction at its original | |
5332 | location. */ | |
5333 | ||
5334 | ULONGEST | |
1152d984 | 5335 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5336 | int regno) |
cca44b1b JB |
5337 | { |
5338 | ULONGEST ret; | |
36073a92 | 5339 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 5340 | |
bf9f652a | 5341 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 5342 | { |
4db71c0b YQ |
5343 | /* Compute pipeline offset: |
5344 | - When executing an ARM instruction, PC reads as the address of the | |
5345 | current instruction plus 8. | |
5346 | - When executing a Thumb instruction, PC reads as the address of the | |
5347 | current instruction plus 4. */ | |
5348 | ||
36073a92 | 5349 | if (!dsc->is_thumb) |
4db71c0b YQ |
5350 | from += 8; |
5351 | else | |
5352 | from += 4; | |
5353 | ||
136821d9 SM |
5354 | displaced_debug_printf ("read pc value %.8lx", |
5355 | (unsigned long) from); | |
4db71c0b | 5356 | return (ULONGEST) from; |
cca44b1b | 5357 | } |
c906108c | 5358 | else |
cca44b1b JB |
5359 | { |
5360 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
5361 | |
5362 | displaced_debug_printf ("read r%d value %.8lx", | |
5363 | regno, (unsigned long) ret); | |
5364 | ||
cca44b1b JB |
5365 | return ret; |
5366 | } | |
c906108c SS |
5367 | } |
5368 | ||
cca44b1b JB |
5369 | static int |
5370 | displaced_in_arm_mode (struct regcache *regs) | |
5371 | { | |
5372 | ULONGEST ps; | |
ac7936df | 5373 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 5374 | |
cca44b1b | 5375 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 5376 | |
9779414d | 5377 | return (ps & t_bit) == 0; |
cca44b1b | 5378 | } |
66e810cd | 5379 | |
cca44b1b | 5380 | /* Write to the PC as from a branch instruction. */ |
c906108c | 5381 | |
cca44b1b | 5382 | static void |
1152d984 | 5383 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5384 | ULONGEST val) |
c906108c | 5385 | { |
36073a92 | 5386 | if (!dsc->is_thumb) |
cca44b1b JB |
5387 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
5388 | architecture versions < 6. */ | |
0963b4bd MS |
5389 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5390 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 5391 | else |
0963b4bd MS |
5392 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5393 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 5394 | } |
66e810cd | 5395 | |
cca44b1b JB |
5396 | /* Write to the PC as from a branch-exchange instruction. */ |
5397 | ||
5398 | static void | |
5399 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
5400 | { | |
5401 | ULONGEST ps; | |
ac7936df | 5402 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
5403 | |
5404 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
5405 | ||
5406 | if ((val & 1) == 1) | |
c906108c | 5407 | { |
9779414d | 5408 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
5409 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
5410 | } | |
5411 | else if ((val & 2) == 0) | |
5412 | { | |
9779414d | 5413 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5414 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
5415 | } |
5416 | else | |
5417 | { | |
cca44b1b JB |
5418 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
5419 | mode, align dest to 4 bytes). */ | |
5420 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 5421 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5422 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
5423 | } |
5424 | } | |
ed9a39eb | 5425 | |
cca44b1b | 5426 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 5427 | |
34e8f22d | 5428 | static void |
1152d984 | 5429 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5430 | ULONGEST val) |
ed9a39eb | 5431 | { |
cca44b1b JB |
5432 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
5433 | bx_write_pc (regs, val); | |
5434 | else | |
36073a92 | 5435 | branch_write_pc (regs, dsc, val); |
cca44b1b | 5436 | } |
be8626e0 | 5437 | |
cca44b1b JB |
5438 | /* Write to the PC as if from an ALU instruction. */ |
5439 | ||
5440 | static void | |
1152d984 | 5441 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5442 | ULONGEST val) |
cca44b1b | 5443 | { |
36073a92 | 5444 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
5445 | bx_write_pc (regs, val); |
5446 | else | |
36073a92 | 5447 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
5448 | } |
5449 | ||
5450 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
5451 | has a varying effects depending on the instruction which does the write: | |
5452 | this is controlled by the WRITE_PC argument. */ | |
5453 | ||
5454 | void | |
1152d984 | 5455 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
5456 | int regno, ULONGEST val, enum pc_write_style write_pc) |
5457 | { | |
bf9f652a | 5458 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 5459 | { |
136821d9 SM |
5460 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
5461 | ||
cca44b1b | 5462 | switch (write_pc) |
08216dd7 | 5463 | { |
cca44b1b | 5464 | case BRANCH_WRITE_PC: |
36073a92 | 5465 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
5466 | break; |
5467 | ||
cca44b1b JB |
5468 | case BX_WRITE_PC: |
5469 | bx_write_pc (regs, val); | |
24b21115 | 5470 | break; |
cca44b1b JB |
5471 | |
5472 | case LOAD_WRITE_PC: | |
36073a92 | 5473 | load_write_pc (regs, dsc, val); |
24b21115 | 5474 | break; |
cca44b1b JB |
5475 | |
5476 | case ALU_WRITE_PC: | |
36073a92 | 5477 | alu_write_pc (regs, dsc, val); |
24b21115 | 5478 | break; |
cca44b1b JB |
5479 | |
5480 | case CANNOT_WRITE_PC: | |
5481 | warning (_("Instruction wrote to PC in an unexpected way when " | |
5482 | "single-stepping")); | |
08216dd7 RE |
5483 | break; |
5484 | ||
5485 | default: | |
f34652de | 5486 | internal_error (_("Invalid argument to displaced_write_reg")); |
08216dd7 | 5487 | } |
b508a996 | 5488 | |
cca44b1b | 5489 | dsc->wrote_to_pc = 1; |
b508a996 | 5490 | } |
ed9a39eb | 5491 | else |
b508a996 | 5492 | { |
136821d9 SM |
5493 | displaced_debug_printf ("writing r%d value %.8lx", |
5494 | regno, (unsigned long) val); | |
cca44b1b | 5495 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 5496 | } |
34e8f22d RE |
5497 | } |
5498 | ||
cca44b1b JB |
5499 | /* This function is used to concisely determine if an instruction INSN |
5500 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
5501 | corresponding fields of BITMASK set to 0b1111. The function |
5502 | returns return 1 if any of these fields in INSN reference the PC | |
5503 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
5504 | |
5505 | static int | |
cca44b1b | 5506 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 5507 | { |
cca44b1b | 5508 | uint32_t lowbit = 1; |
67255d04 | 5509 | |
cca44b1b JB |
5510 | while (bitmask != 0) |
5511 | { | |
5512 | uint32_t mask; | |
44e1a9eb | 5513 | |
cca44b1b JB |
5514 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
5515 | ; | |
67255d04 | 5516 | |
cca44b1b JB |
5517 | if (!lowbit) |
5518 | break; | |
67255d04 | 5519 | |
cca44b1b | 5520 | mask = lowbit * 0xf; |
67255d04 | 5521 | |
cca44b1b JB |
5522 | if ((insn & mask) == mask) |
5523 | return 1; | |
5524 | ||
5525 | bitmask &= ~mask; | |
67255d04 RE |
5526 | } |
5527 | ||
cca44b1b JB |
5528 | return 0; |
5529 | } | |
2af48f68 | 5530 | |
cca44b1b JB |
5531 | /* The simplest copy function. Many instructions have the same effect no |
5532 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 5533 | |
cca44b1b | 5534 | static int |
1152d984 SM |
5535 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
5536 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 5537 | { |
136821d9 SM |
5538 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
5539 | (unsigned long) insn, iname); | |
67255d04 | 5540 | |
cca44b1b | 5541 | dsc->modinsn[0] = insn; |
67255d04 | 5542 | |
cca44b1b JB |
5543 | return 0; |
5544 | } | |
5545 | ||
34518530 YQ |
5546 | static int |
5547 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
5548 | uint16_t insn2, const char *iname, | |
1152d984 | 5549 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5550 | { |
136821d9 SM |
5551 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
5552 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
5553 | |
5554 | dsc->modinsn[0] = insn1; | |
5555 | dsc->modinsn[1] = insn2; | |
5556 | dsc->numinsns = 2; | |
5557 | ||
5558 | return 0; | |
5559 | } | |
5560 | ||
5561 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
5562 | modification. */ | |
5563 | static int | |
615234c1 | 5564 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 5565 | const char *iname, |
1152d984 | 5566 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5567 | { |
136821d9 SM |
5568 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
5569 | insn, iname); | |
34518530 YQ |
5570 | |
5571 | dsc->modinsn[0] = insn; | |
5572 | ||
5573 | return 0; | |
5574 | } | |
5575 | ||
cca44b1b JB |
5576 | /* Preload instructions with immediate offset. */ |
5577 | ||
5578 | static void | |
1152d984 SM |
5579 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
5580 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
5581 | { |
5582 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5583 | if (!dsc->u.preload.immed) | |
5584 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5585 | } | |
5586 | ||
7ff120b4 YQ |
5587 | static void |
5588 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5589 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 5590 | { |
cca44b1b | 5591 | ULONGEST rn_val; |
cca44b1b JB |
5592 | /* Preload instructions: |
5593 | ||
5594 | {pli/pld} [rn, #+/-imm] | |
5595 | -> | |
5596 | {pli/pld} [r0, #+/-imm]. */ | |
5597 | ||
36073a92 YQ |
5598 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5599 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5600 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
5601 | dsc->u.preload.immed = 1; |
5602 | ||
cca44b1b | 5603 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
5604 | } |
5605 | ||
cca44b1b | 5606 | static int |
7ff120b4 | 5607 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5608 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5609 | { |
5610 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 5611 | |
7ff120b4 YQ |
5612 | if (!insn_references_pc (insn, 0x000f0000ul)) |
5613 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 5614 | |
136821d9 | 5615 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 5616 | |
7ff120b4 YQ |
5617 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5618 | ||
5619 | install_preload (gdbarch, regs, dsc, rn); | |
5620 | ||
5621 | return 0; | |
5622 | } | |
5623 | ||
34518530 YQ |
5624 | static int |
5625 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 5626 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5627 | { |
5628 | unsigned int rn = bits (insn1, 0, 3); | |
5629 | unsigned int u_bit = bit (insn1, 7); | |
5630 | int imm12 = bits (insn2, 0, 11); | |
5631 | ULONGEST pc_val; | |
5632 | ||
5633 | if (rn != ARM_PC_REGNUM) | |
5634 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
5635 | ||
5636 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
5637 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
5638 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
5639 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
5640 | imm12); | |
34518530 YQ |
5641 | |
5642 | if (!u_bit) | |
5643 | imm12 = -1 * imm12; | |
5644 | ||
5645 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
5646 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
5647 | ||
5648 | {pli/pld} [r0, r1] | |
5649 | ||
5650 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
5651 | ||
5652 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5653 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5654 | ||
5655 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5656 | ||
5657 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
5658 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
5659 | dsc->u.preload.immed = 0; | |
5660 | ||
5661 | /* {pli/pld} [r0, r1] */ | |
5662 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5663 | dsc->modinsn[1] = 0xf001; | |
5664 | dsc->numinsns = 2; | |
5665 | ||
5666 | dsc->cleanup = &cleanup_preload; | |
5667 | return 0; | |
5668 | } | |
5669 | ||
7ff120b4 YQ |
5670 | /* Preload instructions with register offset. */ |
5671 | ||
5672 | static void | |
5673 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5674 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
5675 | unsigned int rm) |
5676 | { | |
5677 | ULONGEST rn_val, rm_val; | |
5678 | ||
cca44b1b JB |
5679 | /* Preload register-offset instructions: |
5680 | ||
5681 | {pli/pld} [rn, rm {, shift}] | |
5682 | -> | |
5683 | {pli/pld} [r0, r1 {, shift}]. */ | |
5684 | ||
36073a92 YQ |
5685 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5686 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5687 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5688 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5689 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5690 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
5691 | dsc->u.preload.immed = 0; |
5692 | ||
cca44b1b | 5693 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
5694 | } |
5695 | ||
5696 | static int | |
5697 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5698 | struct regcache *regs, | |
1152d984 | 5699 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5700 | { |
5701 | unsigned int rn = bits (insn, 16, 19); | |
5702 | unsigned int rm = bits (insn, 0, 3); | |
5703 | ||
5704 | ||
5705 | if (!insn_references_pc (insn, 0x000f000ful)) | |
5706 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
5707 | ||
136821d9 SM |
5708 | displaced_debug_printf ("copying preload insn %.8lx", |
5709 | (unsigned long) insn); | |
7ff120b4 YQ |
5710 | |
5711 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 5712 | |
7ff120b4 | 5713 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
5714 | return 0; |
5715 | } | |
5716 | ||
5717 | /* Copy/cleanup coprocessor load and store instructions. */ | |
5718 | ||
5719 | static void | |
6e39997a | 5720 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 5721 | struct regcache *regs, |
1152d984 | 5722 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5723 | { |
36073a92 | 5724 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5725 | |
5726 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5727 | ||
5728 | if (dsc->u.ldst.writeback) | |
5729 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
5730 | } | |
5731 | ||
7ff120b4 YQ |
5732 | static void |
5733 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5734 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5735 | int writeback, unsigned int rn) |
cca44b1b | 5736 | { |
cca44b1b | 5737 | ULONGEST rn_val; |
cca44b1b | 5738 | |
cca44b1b JB |
5739 | /* Coprocessor load/store instructions: |
5740 | ||
5741 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
5742 | -> | |
5743 | {stc/stc2} [r0, #+/-imm]. | |
5744 | ||
5745 | ldc/ldc2 are handled identically. */ | |
5746 | ||
36073a92 YQ |
5747 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5748 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
5749 | /* PC should be 4-byte aligned. */ |
5750 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
5751 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5752 | ||
7ff120b4 | 5753 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5754 | dsc->u.ldst.rn = rn; |
5755 | ||
7ff120b4 YQ |
5756 | dsc->cleanup = &cleanup_copro_load_store; |
5757 | } | |
5758 | ||
5759 | static int | |
5760 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
5761 | struct regcache *regs, | |
1152d984 | 5762 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5763 | { |
5764 | unsigned int rn = bits (insn, 16, 19); | |
5765 | ||
5766 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
5767 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
5768 | ||
136821d9 SM |
5769 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
5770 | (unsigned long) insn); | |
7ff120b4 | 5771 | |
cca44b1b JB |
5772 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5773 | ||
7ff120b4 | 5774 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
5775 | |
5776 | return 0; | |
5777 | } | |
5778 | ||
34518530 YQ |
5779 | static int |
5780 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
5781 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5782 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5783 | { |
5784 | unsigned int rn = bits (insn1, 0, 3); | |
5785 | ||
5786 | if (rn != ARM_PC_REGNUM) | |
5787 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
5788 | "copro load/store", dsc); | |
5789 | ||
136821d9 SM |
5790 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
5791 | insn1, insn2); | |
34518530 YQ |
5792 | |
5793 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5794 | dsc->modinsn[1] = insn2; | |
5795 | dsc->numinsns = 2; | |
5796 | ||
5797 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
5798 | doesn't support writeback, so pass 0. */ | |
5799 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
5800 | ||
5801 | return 0; | |
5802 | } | |
5803 | ||
cca44b1b JB |
5804 | /* Clean up branch instructions (actually perform the branch, by setting |
5805 | PC). */ | |
5806 | ||
5807 | static void | |
6e39997a | 5808 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5809 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5810 | { |
36073a92 | 5811 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5812 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
5813 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
5814 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
5815 | ||
5816 | if (!branch_taken) | |
5817 | return; | |
5818 | ||
5819 | if (dsc->u.branch.link) | |
5820 | { | |
8c8dba6d | 5821 | /* The value of LR should be the next insn of current one. In order |
85102364 | 5822 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
5823 | is Thumb, the bit 0 of LR value should be set to 1. */ |
5824 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
5825 | ||
5826 | if (dsc->is_thumb) | |
5827 | next_insn_addr |= 0x1; | |
5828 | ||
5829 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
5830 | CANNOT_WRITE_PC); | |
cca44b1b JB |
5831 | } |
5832 | ||
bf9f652a | 5833 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
5834 | } |
5835 | ||
5836 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
5837 | ||
7ff120b4 YQ |
5838 | static void |
5839 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5840 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5841 | unsigned int cond, int exchange, int link, long offset) |
5842 | { | |
5843 | /* Implement "BL<cond> <label>" as: | |
5844 | ||
5845 | Preparation: cond <- instruction condition | |
5846 | Insn: mov r0, r0 (nop) | |
5847 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
5848 | ||
5849 | B<cond> similar, but don't set r14 in cleanup. */ | |
5850 | ||
5851 | dsc->u.branch.cond = cond; | |
5852 | dsc->u.branch.link = link; | |
5853 | dsc->u.branch.exchange = exchange; | |
5854 | ||
2b16b2e3 YQ |
5855 | dsc->u.branch.dest = dsc->insn_addr; |
5856 | if (link && exchange) | |
5857 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5858 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5859 | ||
7ff120b4 | 5860 | if (dsc->is_thumb) |
2b16b2e3 | 5861 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5862 | else |
2b16b2e3 | 5863 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5864 | |
5865 | dsc->cleanup = &cleanup_branch; | |
5866 | } | |
cca44b1b | 5867 | static int |
7ff120b4 | 5868 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5869 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5870 | { |
5871 | unsigned int cond = bits (insn, 28, 31); | |
5872 | int exchange = (cond == 0xf); | |
5873 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5874 | long offset; |
5875 | ||
136821d9 SM |
5876 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5877 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5878 | (unsigned long) insn); | |
cca44b1b JB |
5879 | if (exchange) |
5880 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5881 | then arrange the switch into Thumb mode. */ | |
5882 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5883 | else | |
5884 | offset = bits (insn, 0, 23) << 2; | |
5885 | ||
5886 | if (bit (offset, 25)) | |
5887 | offset = offset | ~0x3ffffff; | |
5888 | ||
cca44b1b JB |
5889 | dsc->modinsn[0] = ARM_NOP; |
5890 | ||
7ff120b4 | 5891 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5892 | return 0; |
5893 | } | |
5894 | ||
34518530 YQ |
5895 | static int |
5896 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5897 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5898 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5899 | { |
5900 | int link = bit (insn2, 14); | |
5901 | int exchange = link && !bit (insn2, 12); | |
5902 | int cond = INST_AL; | |
5903 | long offset = 0; | |
5904 | int j1 = bit (insn2, 13); | |
5905 | int j2 = bit (insn2, 11); | |
5906 | int s = sbits (insn1, 10, 10); | |
5907 | int i1 = !(j1 ^ bit (insn1, 10)); | |
5908 | int i2 = !(j2 ^ bit (insn1, 10)); | |
5909 | ||
5910 | if (!link && !exchange) /* B */ | |
5911 | { | |
5912 | offset = (bits (insn2, 0, 10) << 1); | |
5913 | if (bit (insn2, 12)) /* Encoding T4 */ | |
5914 | { | |
5915 | offset |= (bits (insn1, 0, 9) << 12) | |
5916 | | (i2 << 22) | |
5917 | | (i1 << 23) | |
5918 | | (s << 24); | |
5919 | cond = INST_AL; | |
5920 | } | |
5921 | else /* Encoding T3 */ | |
5922 | { | |
5923 | offset |= (bits (insn1, 0, 5) << 12) | |
5924 | | (j1 << 18) | |
5925 | | (j2 << 19) | |
5926 | | (s << 20); | |
5927 | cond = bits (insn1, 6, 9); | |
5928 | } | |
5929 | } | |
5930 | else | |
5931 | { | |
5932 | offset = (bits (insn1, 0, 9) << 12); | |
5933 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
5934 | offset |= exchange ? | |
5935 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
5936 | } | |
5937 | ||
136821d9 SM |
5938 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
5939 | link ? (exchange) ? "blx" : "bl" : "b", | |
5940 | insn1, insn2, offset); | |
34518530 YQ |
5941 | |
5942 | dsc->modinsn[0] = THUMB_NOP; | |
5943 | ||
5944 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
5945 | return 0; | |
5946 | } | |
5947 | ||
5948 | /* Copy B Thumb instructions. */ | |
5949 | static int | |
615234c1 | 5950 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 5951 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5952 | { |
5953 | unsigned int cond = 0; | |
5954 | int offset = 0; | |
5955 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
5956 | CORE_ADDR from = dsc->insn_addr; | |
5957 | ||
5958 | if (bit_12_15 == 0xd) | |
5959 | { | |
5960 | /* offset = SignExtend (imm8:0, 32) */ | |
5961 | offset = sbits ((insn << 1), 0, 8); | |
5962 | cond = bits (insn, 8, 11); | |
5963 | } | |
5964 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
5965 | { | |
5966 | offset = sbits ((insn << 1), 0, 11); | |
5967 | cond = INST_AL; | |
5968 | } | |
5969 | ||
136821d9 SM |
5970 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
5971 | insn, offset); | |
34518530 YQ |
5972 | |
5973 | dsc->u.branch.cond = cond; | |
5974 | dsc->u.branch.link = 0; | |
5975 | dsc->u.branch.exchange = 0; | |
5976 | dsc->u.branch.dest = from + 4 + offset; | |
5977 | ||
5978 | dsc->modinsn[0] = THUMB_NOP; | |
5979 | ||
5980 | dsc->cleanup = &cleanup_branch; | |
5981 | ||
5982 | return 0; | |
5983 | } | |
5984 | ||
cca44b1b JB |
5985 | /* Copy BX/BLX with register-specified destinations. */ |
5986 | ||
7ff120b4 YQ |
5987 | static void |
5988 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5989 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 5990 | unsigned int cond, unsigned int rm) |
cca44b1b | 5991 | { |
cca44b1b JB |
5992 | /* Implement {BX,BLX}<cond> <reg>" as: |
5993 | ||
5994 | Preparation: cond <- instruction condition | |
5995 | Insn: mov r0, r0 (nop) | |
5996 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5997 | ||
5998 | Don't set r14 in cleanup for BX. */ | |
5999 | ||
36073a92 | 6000 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6001 | |
6002 | dsc->u.branch.cond = cond; | |
6003 | dsc->u.branch.link = link; | |
cca44b1b | 6004 | |
7ff120b4 | 6005 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
6006 | |
6007 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 6008 | } |
cca44b1b | 6009 | |
7ff120b4 YQ |
6010 | static int |
6011 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 6012 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6013 | { |
6014 | unsigned int cond = bits (insn, 28, 31); | |
6015 | /* BX: x12xxx1x | |
6016 | BLX: x12xxx3x. */ | |
6017 | int link = bit (insn, 5); | |
6018 | unsigned int rm = bits (insn, 0, 3); | |
6019 | ||
136821d9 | 6020 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
6021 | |
6022 | dsc->modinsn[0] = ARM_NOP; | |
6023 | ||
6024 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
6025 | return 0; |
6026 | } | |
6027 | ||
34518530 YQ |
6028 | static int |
6029 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6030 | struct regcache *regs, | |
1152d984 | 6031 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6032 | { |
6033 | int link = bit (insn, 7); | |
6034 | unsigned int rm = bits (insn, 3, 6); | |
6035 | ||
136821d9 | 6036 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
6037 | |
6038 | dsc->modinsn[0] = THUMB_NOP; | |
6039 | ||
6040 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
6041 | ||
6042 | return 0; | |
6043 | } | |
6044 | ||
6045 | ||
0963b4bd | 6046 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
6047 | |
6048 | static void | |
6e39997a | 6049 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 6050 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6051 | { |
36073a92 | 6052 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6053 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
6054 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6055 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6056 | } | |
6057 | ||
6058 | static int | |
7ff120b4 | 6059 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 6060 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6061 | { |
6062 | unsigned int rn = bits (insn, 16, 19); | |
6063 | unsigned int rd = bits (insn, 12, 15); | |
6064 | unsigned int op = bits (insn, 21, 24); | |
6065 | int is_mov = (op == 0xd); | |
6066 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
6067 | |
6068 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 6069 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 6070 | |
136821d9 SM |
6071 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
6072 | is_mov ? "move" : "ALU", | |
6073 | (unsigned long) insn); | |
cca44b1b JB |
6074 | |
6075 | /* Instruction is of form: | |
6076 | ||
6077 | <op><cond> rd, [rn,] #imm | |
6078 | ||
6079 | Rewrite as: | |
6080 | ||
6081 | Preparation: tmp1, tmp2 <- r0, r1; | |
6082 | r0, r1 <- rd, rn | |
6083 | Insn: <op><cond> r0, r1, #imm | |
6084 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6085 | */ | |
6086 | ||
36073a92 YQ |
6087 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6088 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6089 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6090 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
6091 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6092 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6093 | dsc->rd = rd; | |
6094 | ||
6095 | if (is_mov) | |
6096 | dsc->modinsn[0] = insn & 0xfff00fff; | |
6097 | else | |
6098 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
6099 | ||
6100 | dsc->cleanup = &cleanup_alu_imm; | |
6101 | ||
6102 | return 0; | |
6103 | } | |
6104 | ||
34518530 YQ |
6105 | static int |
6106 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6107 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6108 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6109 | { |
6110 | unsigned int op = bits (insn1, 5, 8); | |
6111 | unsigned int rn, rm, rd; | |
6112 | ULONGEST rd_val, rn_val; | |
6113 | ||
6114 | rn = bits (insn1, 0, 3); /* Rn */ | |
6115 | rm = bits (insn2, 0, 3); /* Rm */ | |
6116 | rd = bits (insn2, 8, 11); /* Rd */ | |
6117 | ||
6118 | /* This routine is only called for instruction MOV. */ | |
6119 | gdb_assert (op == 0x2 && rn == 0xf); | |
6120 | ||
6121 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
6122 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
6123 | ||
136821d9 | 6124 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
6125 | |
6126 | /* Instruction is of form: | |
6127 | ||
6128 | <op><cond> rd, [rn,] #imm | |
6129 | ||
6130 | Rewrite as: | |
6131 | ||
6132 | Preparation: tmp1, tmp2 <- r0, r1; | |
6133 | r0, r1 <- rd, rn | |
6134 | Insn: <op><cond> r0, r1, #imm | |
6135 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6136 | */ | |
6137 | ||
6138 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6139 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6140 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6141 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6142 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
6143 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6144 | dsc->rd = rd; | |
6145 | ||
6146 | dsc->modinsn[0] = insn1; | |
6147 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
6148 | dsc->numinsns = 2; | |
6149 | ||
6150 | dsc->cleanup = &cleanup_alu_imm; | |
6151 | ||
6152 | return 0; | |
6153 | } | |
6154 | ||
cca44b1b JB |
6155 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
6156 | ||
6157 | static void | |
6e39997a | 6158 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 6159 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6160 | { |
6161 | ULONGEST rd_val; | |
6162 | int i; | |
6163 | ||
36073a92 | 6164 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6165 | |
6166 | for (i = 0; i < 3; i++) | |
6167 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6168 | ||
6169 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6170 | } | |
6171 | ||
7ff120b4 YQ |
6172 | static void |
6173 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6174 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 6175 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 6176 | { |
cca44b1b | 6177 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 6178 | |
cca44b1b JB |
6179 | /* Instruction is of form: |
6180 | ||
6181 | <op><cond> rd, [rn,] rm [, <shift>] | |
6182 | ||
6183 | Rewrite as: | |
6184 | ||
6185 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
6186 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 6187 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
6188 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
6189 | */ | |
6190 | ||
36073a92 YQ |
6191 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6192 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6193 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6194 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6195 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6196 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
6197 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6198 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6199 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6200 | dsc->rd = rd; | |
6201 | ||
7ff120b4 YQ |
6202 | dsc->cleanup = &cleanup_alu_reg; |
6203 | } | |
6204 | ||
6205 | static int | |
6206 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 6207 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6208 | { |
6209 | unsigned int op = bits (insn, 21, 24); | |
6210 | int is_mov = (op == 0xd); | |
6211 | ||
6212 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6213 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
6214 | ||
136821d9 SM |
6215 | displaced_debug_printf ("copying reg %s insn %.8lx", |
6216 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 6217 | |
cca44b1b JB |
6218 | if (is_mov) |
6219 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
6220 | else | |
6221 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
6222 | ||
7ff120b4 YQ |
6223 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
6224 | bits (insn, 0, 3)); | |
cca44b1b JB |
6225 | return 0; |
6226 | } | |
6227 | ||
34518530 YQ |
6228 | static int |
6229 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6230 | struct regcache *regs, | |
1152d984 | 6231 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 6232 | { |
ef713951 | 6233 | unsigned rm, rd; |
34518530 | 6234 | |
ef713951 YQ |
6235 | rm = bits (insn, 3, 6); |
6236 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 6237 | |
ef713951 | 6238 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
6239 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
6240 | ||
136821d9 | 6241 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 6242 | |
ef713951 | 6243 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 6244 | |
ef713951 | 6245 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
6246 | |
6247 | return 0; | |
6248 | } | |
6249 | ||
cca44b1b JB |
6250 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
6251 | ||
6252 | static void | |
6e39997a | 6253 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 6254 | struct regcache *regs, |
1152d984 | 6255 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6256 | { |
36073a92 | 6257 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6258 | int i; |
6259 | ||
6260 | for (i = 0; i < 4; i++) | |
6261 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6262 | ||
6263 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6264 | } | |
6265 | ||
7ff120b4 YQ |
6266 | static void |
6267 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6268 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
6269 | unsigned int rd, unsigned int rn, unsigned int rm, |
6270 | unsigned rs) | |
cca44b1b | 6271 | { |
7ff120b4 | 6272 | int i; |
cca44b1b | 6273 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 6274 | |
cca44b1b JB |
6275 | /* Instruction is of form: |
6276 | ||
6277 | <op><cond> rd, [rn,] rm, <shift> rs | |
6278 | ||
6279 | Rewrite as: | |
6280 | ||
6281 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
6282 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
6283 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
6284 | Cleanup: tmp5 <- r0 | |
6285 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
6286 | rd <- tmp5 | |
6287 | */ | |
6288 | ||
6289 | for (i = 0; i < 4; i++) | |
36073a92 | 6290 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 6291 | |
36073a92 YQ |
6292 | rd_val = displaced_read_reg (regs, dsc, rd); |
6293 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6294 | rm_val = displaced_read_reg (regs, dsc, rm); | |
6295 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
6296 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6297 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6298 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6299 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
6300 | dsc->rd = rd; | |
7ff120b4 YQ |
6301 | dsc->cleanup = &cleanup_alu_shifted_reg; |
6302 | } | |
6303 | ||
6304 | static int | |
6305 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
6306 | struct regcache *regs, | |
1152d984 | 6307 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6308 | { |
6309 | unsigned int op = bits (insn, 21, 24); | |
6310 | int is_mov = (op == 0xd); | |
6311 | unsigned int rd, rn, rm, rs; | |
6312 | ||
6313 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
6314 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
6315 | ||
136821d9 SM |
6316 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
6317 | is_mov ? "move" : "ALU", | |
6318 | (unsigned long) insn); | |
7ff120b4 YQ |
6319 | |
6320 | rn = bits (insn, 16, 19); | |
6321 | rm = bits (insn, 0, 3); | |
6322 | rs = bits (insn, 8, 11); | |
6323 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
6324 | |
6325 | if (is_mov) | |
6326 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
6327 | else | |
6328 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
6329 | ||
7ff120b4 | 6330 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
6331 | |
6332 | return 0; | |
6333 | } | |
6334 | ||
6335 | /* Clean up load instructions. */ | |
6336 | ||
6337 | static void | |
6e39997a | 6338 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6339 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6340 | { |
6341 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 6342 | |
36073a92 | 6343 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 6344 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
6345 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
6346 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
6347 | |
6348 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6349 | if (dsc->u.ldst.xfersize > 4) | |
6350 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6351 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6352 | if (!dsc->u.ldst.immed) | |
6353 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6354 | ||
6355 | /* Handle register writeback. */ | |
6356 | if (dsc->u.ldst.writeback) | |
6357 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6358 | /* Put result in right place. */ | |
6359 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
6360 | if (dsc->u.ldst.xfersize == 8) | |
6361 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
6362 | } | |
6363 | ||
6364 | /* Clean up store instructions. */ | |
6365 | ||
6366 | static void | |
6e39997a | 6367 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6368 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6369 | { |
36073a92 | 6370 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
6371 | |
6372 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6373 | if (dsc->u.ldst.xfersize > 4) | |
6374 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6375 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6376 | if (!dsc->u.ldst.immed) | |
6377 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6378 | if (!dsc->u.ldst.restore_r4) | |
6379 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
6380 | ||
6381 | /* Writeback. */ | |
6382 | if (dsc->u.ldst.writeback) | |
6383 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6384 | } | |
6385 | ||
6386 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
6387 | transfers, which have a different encoding to byte/word transfers. */ | |
6388 | ||
6389 | static int | |
550dc4e2 | 6390 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 6391 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6392 | { |
6393 | unsigned int op1 = bits (insn, 20, 24); | |
6394 | unsigned int op2 = bits (insn, 5, 6); | |
6395 | unsigned int rt = bits (insn, 12, 15); | |
6396 | unsigned int rn = bits (insn, 16, 19); | |
6397 | unsigned int rm = bits (insn, 0, 3); | |
6398 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
6399 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
6400 | int immed = (op1 & 0x4) != 0; | |
6401 | int opcode; | |
6402 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
6403 | |
6404 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 6405 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 6406 | |
136821d9 SM |
6407 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
6408 | unprivileged ? "unprivileged " : "", | |
6409 | (unsigned long) insn); | |
cca44b1b JB |
6410 | |
6411 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
6412 | ||
6413 | if (opcode < 0) | |
f34652de | 6414 | internal_error (_("copy_extra_ld_st: instruction decode error")); |
cca44b1b | 6415 | |
36073a92 YQ |
6416 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6417 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6418 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6419 | if (!immed) |
36073a92 | 6420 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6421 | |
36073a92 | 6422 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 6423 | if (bytesize[opcode] == 8) |
36073a92 YQ |
6424 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
6425 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6426 | if (!immed) |
36073a92 | 6427 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6428 | |
6429 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6430 | if (bytesize[opcode] == 8) | |
6431 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
6432 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6433 | if (!immed) | |
6434 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
6435 | ||
6436 | dsc->rd = rt; | |
6437 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
6438 | dsc->u.ldst.rn = rn; | |
6439 | dsc->u.ldst.immed = immed; | |
6440 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
6441 | dsc->u.ldst.restore_r4 = 0; | |
6442 | ||
6443 | if (immed) | |
6444 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
6445 | -> | |
6446 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
6447 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6448 | else | |
6449 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
6450 | -> | |
6451 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
6452 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6453 | ||
6454 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
6455 | ||
6456 | return 0; | |
6457 | } | |
6458 | ||
0f6f04ba | 6459 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 6460 | |
7ff120b4 | 6461 | static void |
0f6f04ba | 6462 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6463 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
6464 | int immed, int writeback, int size, int usermode, |
6465 | int rt, int rm, int rn) | |
cca44b1b | 6466 | { |
cca44b1b | 6467 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 6468 | |
36073a92 YQ |
6469 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6470 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6471 | if (!immed) |
36073a92 | 6472 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6473 | if (!load) |
36073a92 | 6474 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 6475 | |
36073a92 YQ |
6476 | rt_val = displaced_read_reg (regs, dsc, rt); |
6477 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6478 | if (!immed) |
36073a92 | 6479 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6480 | |
6481 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6482 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6483 | if (!immed) | |
6484 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 6485 | dsc->rd = rt; |
0f6f04ba | 6486 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
6487 | dsc->u.ldst.rn = rn; |
6488 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 6489 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
6490 | |
6491 | /* To write PC we can do: | |
6492 | ||
494e194e YQ |
6493 | Before this sequence of instructions: |
6494 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 6495 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
6496 | |
6497 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
6498 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
6499 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
6500 | = addr(Insn1) + offset - addr(Insn3) - 8 |
6501 | = offset - 16 | |
494e194e YQ |
6502 | Insn4: add r4, r4, #8 r4 = offset - 8 |
6503 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 6504 | = from + offset |
494e194e | 6505 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
6506 | |
6507 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
6508 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
6509 | of this can be found in Section "Saving from r15" in | |
6510 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 6511 | |
7ff120b4 YQ |
6512 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
6513 | } | |
6514 | ||
34518530 YQ |
6515 | |
6516 | static int | |
6517 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
6518 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6519 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
6520 | { |
6521 | unsigned int u_bit = bit (insn1, 7); | |
6522 | unsigned int rt = bits (insn2, 12, 15); | |
6523 | int imm12 = bits (insn2, 0, 11); | |
6524 | ULONGEST pc_val; | |
6525 | ||
136821d9 SM |
6526 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
6527 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
6528 | imm12); | |
34518530 YQ |
6529 | |
6530 | if (!u_bit) | |
6531 | imm12 = -1 * imm12; | |
6532 | ||
6533 | /* Rewrite instruction LDR Rt imm12 into: | |
6534 | ||
6535 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
6536 | ||
6537 | LDR R0, R2, R3, | |
6538 | ||
6539 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
6540 | ||
6541 | ||
6542 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6543 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6544 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
6545 | ||
6546 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6547 | ||
6548 | pc_val = pc_val & 0xfffffffc; | |
6549 | ||
6550 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
6551 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
6552 | ||
6553 | dsc->rd = rt; | |
6554 | ||
6555 | dsc->u.ldst.xfersize = size; | |
6556 | dsc->u.ldst.immed = 0; | |
6557 | dsc->u.ldst.writeback = 0; | |
6558 | dsc->u.ldst.restore_r4 = 0; | |
6559 | ||
6560 | /* LDR R0, R2, R3 */ | |
6561 | dsc->modinsn[0] = 0xf852; | |
6562 | dsc->modinsn[1] = 0x3; | |
6563 | dsc->numinsns = 2; | |
6564 | ||
6565 | dsc->cleanup = &cleanup_load; | |
6566 | ||
6567 | return 0; | |
6568 | } | |
6569 | ||
6570 | static int | |
6571 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6572 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6573 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
6574 | int writeback, int immed) |
6575 | { | |
6576 | unsigned int rt = bits (insn2, 12, 15); | |
6577 | unsigned int rn = bits (insn1, 0, 3); | |
6578 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
6579 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
6580 | be PC, so we don't have to check it. */ | |
6581 | ||
6582 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
6583 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
6584 | dsc); | |
6585 | ||
136821d9 SM |
6586 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
6587 | rt, rn, insn1, insn2); | |
34518530 YQ |
6588 | |
6589 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
6590 | 0, rt, rm, rn); | |
6591 | ||
6592 | dsc->u.ldst.restore_r4 = 0; | |
6593 | ||
6594 | if (immed) | |
6595 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
6596 | -> | |
6597 | ldr[b]<cond> r0, [r2, #imm]. */ | |
6598 | { | |
6599 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6600 | dsc->modinsn[1] = insn2 & 0x0fff; | |
6601 | } | |
6602 | else | |
6603 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
6604 | -> | |
6605 | ldr[b]<cond> r0, [r2, r3]. */ | |
6606 | { | |
6607 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6608 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
6609 | } | |
6610 | ||
6611 | dsc->numinsns = 2; | |
6612 | ||
6613 | return 0; | |
6614 | } | |
6615 | ||
6616 | ||
7ff120b4 YQ |
6617 | static int |
6618 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
6619 | struct regcache *regs, | |
1152d984 | 6620 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 6621 | int load, int size, int usermode) |
7ff120b4 YQ |
6622 | { |
6623 | int immed = !bit (insn, 25); | |
6624 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
6625 | unsigned int rt = bits (insn, 12, 15); | |
6626 | unsigned int rn = bits (insn, 16, 19); | |
6627 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
6628 | ||
6629 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6630 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
6631 | ||
136821d9 SM |
6632 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
6633 | load ? (size == 1 ? "ldrb" : "ldr") | |
6634 | : (size == 1 ? "strb" : "str"), | |
6635 | usermode ? "t" : "", | |
6636 | rt, rn, | |
6637 | (unsigned long) insn); | |
7ff120b4 | 6638 | |
0f6f04ba YQ |
6639 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
6640 | usermode, rt, rm, rn); | |
7ff120b4 | 6641 | |
bf9f652a | 6642 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
6643 | { |
6644 | dsc->u.ldst.restore_r4 = 0; | |
6645 | ||
6646 | if (immed) | |
6647 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
6648 | -> | |
6649 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
6650 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6651 | else | |
6652 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
6653 | -> | |
6654 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
6655 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6656 | } | |
6657 | else | |
6658 | { | |
6659 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
6660 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
6661 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
6662 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
6663 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
6664 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
6665 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
6666 | ||
6667 | /* As above. */ | |
6668 | if (immed) | |
6669 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
6670 | else | |
6671 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
6672 | ||
cca44b1b JB |
6673 | dsc->numinsns = 6; |
6674 | } | |
6675 | ||
6676 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
6677 | ||
6678 | return 0; | |
6679 | } | |
6680 | ||
6681 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
6682 | unfortunate corner case: it's impossible to implement correctly by modifying | |
6683 | the instruction. The issue is as follows: we have an instruction, | |
6684 | ||
6685 | ldm rN, {r0-r15} | |
6686 | ||
6687 | which we must rewrite to avoid loading PC. A possible solution would be to | |
6688 | do the load in two halves, something like (with suitable cleanup | |
6689 | afterwards): | |
6690 | ||
6691 | mov r8, rN | |
6692 | ldm[id][ab] r8!, {r0-r7} | |
6693 | str r7, <temp> | |
6694 | ldm[id][ab] r8, {r7-r14} | |
6695 | <bkpt> | |
6696 | ||
6697 | but at present there's no suitable place for <temp>, since the scratch space | |
6698 | is overwritten before the cleanup routine is called. For now, we simply | |
6699 | emulate the instruction. */ | |
6700 | ||
6701 | static void | |
6702 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6703 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6704 | { |
cca44b1b JB |
6705 | int inc = dsc->u.block.increment; |
6706 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
6707 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
6708 | uint32_t regmask = dsc->u.block.regmask; | |
6709 | int regno = inc ? 0 : 15; | |
6710 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
6711 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
6712 | && (regmask & 0x8000) != 0; | |
36073a92 | 6713 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6714 | int do_transfer = condition_true (dsc->u.block.cond, status); |
6715 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6716 | ||
6717 | if (!do_transfer) | |
6718 | return; | |
6719 | ||
6720 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
6721 | sensible we can do here. Complain loudly. */ | |
6722 | if (exception_return) | |
6723 | error (_("Cannot single-step exception return")); | |
6724 | ||
6725 | /* We don't handle any stores here for now. */ | |
6726 | gdb_assert (dsc->u.block.load != 0); | |
6727 | ||
136821d9 SM |
6728 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
6729 | dsc->u.block.load ? "ldm" : "stm", | |
6730 | dsc->u.block.increment ? "inc" : "dec", | |
6731 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
6732 | |
6733 | while (regmask) | |
6734 | { | |
6735 | uint32_t memword; | |
6736 | ||
6737 | if (inc) | |
bf9f652a | 6738 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
6739 | regno++; |
6740 | else | |
6741 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
6742 | regno--; | |
6743 | ||
6744 | xfer_addr += bump_before; | |
6745 | ||
6746 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
6747 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
6748 | ||
6749 | xfer_addr += bump_after; | |
6750 | ||
6751 | regmask &= ~(1 << regno); | |
6752 | } | |
6753 | ||
6754 | if (dsc->u.block.writeback) | |
6755 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
6756 | CANNOT_WRITE_PC); | |
6757 | } | |
6758 | ||
6759 | /* Clean up an STM which included the PC in the register list. */ | |
6760 | ||
6761 | static void | |
6762 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6763 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6764 | { |
36073a92 | 6765 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 6766 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
6767 | CORE_ADDR pc_stored_at, transferred_regs |
6768 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
6769 | CORE_ADDR stm_insn_addr; |
6770 | uint32_t pc_val; | |
6771 | long offset; | |
6772 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6773 | ||
6774 | /* If condition code fails, there's nothing else to do. */ | |
6775 | if (!store_executed) | |
6776 | return; | |
6777 | ||
6778 | if (dsc->u.block.increment) | |
6779 | { | |
6780 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
6781 | ||
6782 | if (dsc->u.block.before) | |
6783 | pc_stored_at += 4; | |
6784 | } | |
6785 | else | |
6786 | { | |
6787 | pc_stored_at = dsc->u.block.xfer_addr; | |
6788 | ||
6789 | if (dsc->u.block.before) | |
6790 | pc_stored_at -= 4; | |
6791 | } | |
6792 | ||
6793 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
6794 | stm_insn_addr = dsc->scratch_base; | |
6795 | offset = pc_val - stm_insn_addr; | |
6796 | ||
136821d9 SM |
6797 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
6798 | offset); | |
cca44b1b JB |
6799 | |
6800 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
6801 | instruction. */ | |
6802 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
6803 | dsc->insn_addr + offset); | |
6804 | } | |
6805 | ||
6806 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
6807 | the registers in the transferred list into a contiguous range r0...rX (to | |
6808 | avoid loading PC directly and losing control of the debugged program), so we | |
6809 | must undo that here. */ | |
6810 | ||
6811 | static void | |
6e39997a | 6812 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 6813 | struct regcache *regs, |
1152d984 | 6814 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6815 | { |
36073a92 | 6816 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 6817 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 6818 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 6819 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
6820 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
6821 | ||
6822 | /* The method employed here will fail if the register list is fully populated | |
6823 | (we need to avoid loading PC directly). */ | |
6824 | gdb_assert (num_to_shuffle < 16); | |
6825 | ||
6826 | if (!load_executed) | |
6827 | return; | |
6828 | ||
6829 | clobbered = (1 << num_to_shuffle) - 1; | |
6830 | ||
6831 | while (num_to_shuffle > 0) | |
6832 | { | |
6833 | if ((mask & (1 << write_reg)) != 0) | |
6834 | { | |
6835 | unsigned int read_reg = num_to_shuffle - 1; | |
6836 | ||
6837 | if (read_reg != write_reg) | |
6838 | { | |
36073a92 | 6839 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 6840 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
6841 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
6842 | read_reg, write_reg); | |
cca44b1b | 6843 | } |
136821d9 SM |
6844 | else |
6845 | displaced_debug_printf ("LDM: register r%d already in the right " | |
6846 | "place", write_reg); | |
cca44b1b JB |
6847 | |
6848 | clobbered &= ~(1 << write_reg); | |
6849 | ||
6850 | num_to_shuffle--; | |
6851 | } | |
6852 | ||
6853 | write_reg--; | |
6854 | } | |
6855 | ||
6856 | /* Restore any registers we scribbled over. */ | |
6857 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6858 | { | |
6859 | if ((clobbered & (1 << write_reg)) != 0) | |
6860 | { | |
6861 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6862 | CANNOT_WRITE_PC); | |
136821d9 SM |
6863 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6864 | write_reg); | |
cca44b1b JB |
6865 | clobbered &= ~(1 << write_reg); |
6866 | } | |
6867 | } | |
6868 | ||
6869 | /* Perform register writeback manually. */ | |
6870 | if (dsc->u.block.writeback) | |
6871 | { | |
6872 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6873 | ||
6874 | if (dsc->u.block.increment) | |
6875 | new_rn_val += regs_loaded * 4; | |
6876 | else | |
6877 | new_rn_val -= regs_loaded * 4; | |
6878 | ||
6879 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6880 | CANNOT_WRITE_PC); | |
6881 | } | |
6882 | } | |
6883 | ||
6884 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6885 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6886 | ||
6887 | static int | |
7ff120b4 YQ |
6888 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6889 | struct regcache *regs, | |
1152d984 | 6890 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6891 | { |
6892 | int load = bit (insn, 20); | |
6893 | int user = bit (insn, 22); | |
6894 | int increment = bit (insn, 23); | |
6895 | int before = bit (insn, 24); | |
6896 | int writeback = bit (insn, 21); | |
6897 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6898 | |
0963b4bd MS |
6899 | /* Block transfers which don't mention PC can be run directly |
6900 | out-of-line. */ | |
bf9f652a | 6901 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 6902 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 6903 | |
bf9f652a | 6904 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 6905 | { |
0963b4bd MS |
6906 | warning (_("displaced: Unpredictable LDM or STM with " |
6907 | "base register r15")); | |
7ff120b4 | 6908 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
6909 | } |
6910 | ||
136821d9 SM |
6911 | displaced_debug_printf ("copying block transfer insn %.8lx", |
6912 | (unsigned long) insn); | |
cca44b1b | 6913 | |
36073a92 | 6914 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
6915 | dsc->u.block.rn = rn; |
6916 | ||
6917 | dsc->u.block.load = load; | |
6918 | dsc->u.block.user = user; | |
6919 | dsc->u.block.increment = increment; | |
6920 | dsc->u.block.before = before; | |
6921 | dsc->u.block.writeback = writeback; | |
6922 | dsc->u.block.cond = bits (insn, 28, 31); | |
6923 | ||
6924 | dsc->u.block.regmask = insn & 0xffff; | |
6925 | ||
6926 | if (load) | |
6927 | { | |
6928 | if ((insn & 0xffff) == 0xffff) | |
6929 | { | |
6930 | /* LDM with a fully-populated register list. This case is | |
6931 | particularly tricky. Implement for now by fully emulating the | |
6932 | instruction (which might not behave perfectly in all cases, but | |
6933 | these instructions should be rare enough for that not to matter | |
6934 | too much). */ | |
6935 | dsc->modinsn[0] = ARM_NOP; | |
6936 | ||
6937 | dsc->cleanup = &cleanup_block_load_all; | |
6938 | } | |
6939 | else | |
6940 | { | |
6941 | /* LDM of a list of registers which includes PC. Implement by | |
6942 | rewriting the list of registers to be transferred into a | |
6943 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
6944 | registers into the correct places in the cleanup routine. */ | |
6945 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 6946 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6947 | unsigned int i; |
cca44b1b JB |
6948 | |
6949 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 6950 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
6951 | |
6952 | /* Writeback makes things complicated. We need to avoid clobbering | |
6953 | the base register with one of the registers in our modified | |
6954 | register list, but just using a different register can't work in | |
6955 | all cases, e.g.: | |
6956 | ||
6957 | ldm r14!, {r0-r13,pc} | |
6958 | ||
6959 | which would need to be rewritten as: | |
6960 | ||
6961 | ldm rN!, {r0-r14} | |
6962 | ||
6963 | but that can't work, because there's no free register for N. | |
6964 | ||
6965 | Solve this by turning off the writeback bit, and emulating | |
6966 | writeback manually in the cleanup routine. */ | |
6967 | ||
6968 | if (writeback) | |
6969 | insn &= ~(1 << 21); | |
6970 | ||
6971 | new_regmask = (1 << num_in_list) - 1; | |
6972 | ||
136821d9 SM |
6973 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6974 | "%.4x, modified list %.4x", | |
6975 | rn, writeback ? "!" : "", | |
6976 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
6977 | |
6978 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6979 | ||
6980 | dsc->cleanup = &cleanup_block_load_pc; | |
6981 | } | |
6982 | } | |
6983 | else | |
6984 | { | |
6985 | /* STM of a list of registers which includes PC. Run the instruction | |
6986 | as-is, but out of line: this will store the wrong value for the PC, | |
6987 | so we must manually fix up the memory in the cleanup routine. | |
6988 | Doing things this way has the advantage that we can auto-detect | |
6989 | the offset of the PC write (which is architecture-dependent) in | |
6990 | the cleanup routine. */ | |
6991 | dsc->modinsn[0] = insn; | |
6992 | ||
6993 | dsc->cleanup = &cleanup_block_store_pc; | |
6994 | } | |
6995 | ||
6996 | return 0; | |
6997 | } | |
6998 | ||
34518530 YQ |
6999 | static int |
7000 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
7001 | struct regcache *regs, | |
1152d984 | 7002 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7003 | { |
34518530 YQ |
7004 | int rn = bits (insn1, 0, 3); |
7005 | int load = bit (insn1, 4); | |
7006 | int writeback = bit (insn1, 5); | |
cca44b1b | 7007 | |
34518530 YQ |
7008 | /* Block transfers which don't mention PC can be run directly |
7009 | out-of-line. */ | |
7010 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
7011 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 7012 | |
34518530 YQ |
7013 | if (rn == ARM_PC_REGNUM) |
7014 | { | |
7015 | warning (_("displaced: Unpredictable LDM or STM with " | |
7016 | "base register r15")); | |
7017 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7018 | "unpredictable ldm/stm", dsc); | |
7019 | } | |
cca44b1b | 7020 | |
136821d9 SM |
7021 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
7022 | insn1, insn2); | |
cca44b1b | 7023 | |
34518530 YQ |
7024 | /* Clear bit 13, since it should be always zero. */ |
7025 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
7026 | dsc->u.block.rn = rn; | |
cca44b1b | 7027 | |
34518530 YQ |
7028 | dsc->u.block.load = load; |
7029 | dsc->u.block.user = 0; | |
7030 | dsc->u.block.increment = bit (insn1, 7); | |
7031 | dsc->u.block.before = bit (insn1, 8); | |
7032 | dsc->u.block.writeback = writeback; | |
7033 | dsc->u.block.cond = INST_AL; | |
7034 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 7035 | |
34518530 YQ |
7036 | if (load) |
7037 | { | |
7038 | if (dsc->u.block.regmask == 0xffff) | |
7039 | { | |
7040 | /* This branch is impossible to happen. */ | |
7041 | gdb_assert (0); | |
7042 | } | |
7043 | else | |
7044 | { | |
7045 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 7046 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 7047 | unsigned int i; |
34518530 YQ |
7048 | |
7049 | for (i = 0; i < num_in_list; i++) | |
7050 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7051 | ||
7052 | if (writeback) | |
7053 | insn1 &= ~(1 << 5); | |
7054 | ||
7055 | new_regmask = (1 << num_in_list) - 1; | |
7056 | ||
136821d9 SM |
7057 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
7058 | "%.4x, modified list %.4x", | |
7059 | rn, writeback ? "!" : "", | |
7060 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7061 | |
7062 | dsc->modinsn[0] = insn1; | |
7063 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
7064 | dsc->numinsns = 2; | |
7065 | ||
7066 | dsc->cleanup = &cleanup_block_load_pc; | |
7067 | } | |
7068 | } | |
7069 | else | |
7070 | { | |
7071 | dsc->modinsn[0] = insn1; | |
7072 | dsc->modinsn[1] = insn2; | |
7073 | dsc->numinsns = 2; | |
7074 | dsc->cleanup = &cleanup_block_store_pc; | |
7075 | } | |
7076 | return 0; | |
7077 | } | |
7078 | ||
d9311bfa AT |
7079 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
7080 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
7081 | ||
7082 | ULONGEST | |
7083 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
7084 | int byte_order) | |
7085 | { | |
5f2dfcfd AT |
7086 | return read_memory_unsigned_integer (memaddr, len, |
7087 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
7088 | } |
7089 | ||
7090 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
7091 | ||
7092 | CORE_ADDR | |
7093 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
7094 | CORE_ADDR val) | |
7095 | { | |
ac7936df | 7096 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
7097 | } |
7098 | ||
7099 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
7100 | ||
e7cf25a8 | 7101 | static CORE_ADDR |
553cb527 | 7102 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 7103 | { |
d9311bfa AT |
7104 | return 0; |
7105 | } | |
7106 | ||
7107 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
7108 | ||
7109 | int | |
7110 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
7111 | { | |
7112 | return arm_is_thumb (self->regcache); | |
7113 | } | |
7114 | ||
7115 | /* single_step() is called just before we want to resume the inferior, | |
7116 | if we want to single-step it but there is no hardware or kernel | |
7117 | single-step support. We find the target of the coming instructions | |
7118 | and breakpoint them. */ | |
7119 | ||
a0ff9e1a | 7120 | std::vector<CORE_ADDR> |
f5ea389a | 7121 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 7122 | { |
ac7936df | 7123 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 7124 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
7125 | |
7126 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
7127 | &arm_get_next_pcs_ops, | |
7128 | gdbarch_byte_order (gdbarch), | |
7129 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 7130 | 0, |
d9311bfa AT |
7131 | regcache); |
7132 | ||
a0ff9e1a | 7133 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 7134 | |
a0ff9e1a SM |
7135 | for (CORE_ADDR &pc_ref : next_pcs) |
7136 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 7137 | |
93f9a11f | 7138 | return next_pcs; |
d9311bfa AT |
7139 | } |
7140 | ||
34518530 YQ |
7141 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
7142 | for Linux, where some SVC instructions must be treated specially. */ | |
7143 | ||
7144 | static void | |
7145 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7146 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7147 | { |
7148 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
7149 | ||
136821d9 SM |
7150 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
7151 | (unsigned long) resume_addr); | |
34518530 YQ |
7152 | |
7153 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
7154 | } | |
7155 | ||
7156 | ||
85102364 | 7157 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
7158 | |
7159 | static int | |
7160 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7161 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7162 | { |
7163 | /* Preparation: none. | |
7164 | Insn: unmodified svc. | |
7165 | Cleanup: pc <- insn_addr + insn_size. */ | |
7166 | ||
7167 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
7168 | instruction. */ | |
7169 | dsc->wrote_to_pc = 1; | |
7170 | ||
7171 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
7172 | if (dsc->u.svc.copy_svc_os) |
7173 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
7174 | else | |
7175 | { | |
7176 | dsc->cleanup = &cleanup_svc; | |
7177 | return 0; | |
7178 | } | |
34518530 YQ |
7179 | } |
7180 | ||
7181 | static int | |
7182 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 7183 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7184 | { |
7185 | ||
136821d9 SM |
7186 | displaced_debug_printf ("copying svc insn %.8lx", |
7187 | (unsigned long) insn); | |
34518530 YQ |
7188 | |
7189 | dsc->modinsn[0] = insn; | |
7190 | ||
7191 | return install_svc (gdbarch, regs, dsc); | |
7192 | } | |
7193 | ||
7194 | static int | |
7195 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 7196 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7197 | { |
7198 | ||
136821d9 | 7199 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 7200 | |
34518530 YQ |
7201 | dsc->modinsn[0] = insn; |
7202 | ||
7203 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
7204 | } |
7205 | ||
7206 | /* Copy undefined instructions. */ | |
7207 | ||
7208 | static int | |
7ff120b4 | 7209 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7210 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7211 | { |
136821d9 SM |
7212 | displaced_debug_printf ("copying undefined insn %.8lx", |
7213 | (unsigned long) insn); | |
cca44b1b JB |
7214 | |
7215 | dsc->modinsn[0] = insn; | |
7216 | ||
7217 | return 0; | |
7218 | } | |
7219 | ||
34518530 YQ |
7220 | static int |
7221 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 7222 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7223 | { |
7224 | ||
136821d9 SM |
7225 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
7226 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
7227 | |
7228 | dsc->modinsn[0] = insn1; | |
7229 | dsc->modinsn[1] = insn2; | |
7230 | dsc->numinsns = 2; | |
7231 | ||
7232 | return 0; | |
7233 | } | |
7234 | ||
cca44b1b JB |
7235 | /* Copy unpredictable instructions. */ |
7236 | ||
7237 | static int | |
7ff120b4 | 7238 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7239 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7240 | { |
136821d9 SM |
7241 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
7242 | (unsigned long) insn); | |
cca44b1b JB |
7243 | |
7244 | dsc->modinsn[0] = insn; | |
7245 | ||
7246 | return 0; | |
7247 | } | |
7248 | ||
7249 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
7250 | the presentation in the ARM ARM. */ | |
7251 | ||
7252 | static int | |
7ff120b4 YQ |
7253 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
7254 | struct regcache *regs, | |
1152d984 | 7255 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7256 | { |
7257 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
7258 | unsigned int rn = bits (insn, 16, 19); | |
7259 | ||
2f924de6 | 7260 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 7261 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 7262 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 7263 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 7264 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 7265 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 7266 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
7267 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
7268 | dsc); | |
cca44b1b | 7269 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 7270 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7271 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 7272 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
7273 | else if ((op1 & 0x77) == 0x51) |
7274 | { | |
7275 | if (rn != 0xf) | |
7ff120b4 | 7276 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 7277 | else |
7ff120b4 | 7278 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7279 | } |
7280 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 7281 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
7282 | else if (op1 == 0x57) |
7283 | switch (op2) | |
7284 | { | |
7ff120b4 YQ |
7285 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
7286 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
7287 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
7288 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
7289 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
7290 | } |
7291 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 7292 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7293 | else if ((op2 & 0x1) == 0x0) |
7294 | switch (op1 & ~0x80) | |
7295 | { | |
7296 | case 0x61: | |
7ff120b4 | 7297 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7298 | case 0x65: |
7ff120b4 | 7299 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 7300 | case 0x71: case 0x75: |
dda83cd7 | 7301 | /* pld/pldw reg. */ |
7ff120b4 | 7302 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7303 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 7304 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 7305 | default: |
7ff120b4 | 7306 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7307 | } |
7308 | else | |
7ff120b4 | 7309 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
7310 | } |
7311 | ||
7312 | static int | |
7ff120b4 YQ |
7313 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
7314 | struct regcache *regs, | |
1152d984 | 7315 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7316 | { |
7317 | if (bit (insn, 27) == 0) | |
7ff120b4 | 7318 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7319 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
7320 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
7321 | { | |
7322 | case 0x0: case 0x2: | |
7ff120b4 | 7323 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
7324 | |
7325 | case 0x1: case 0x3: | |
7ff120b4 | 7326 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
7327 | |
7328 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 7329 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7330 | |
7331 | case 0x8: | |
7332 | switch ((insn & 0xe00000) >> 21) | |
7333 | { | |
7334 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
7335 | /* stc/stc2. */ | |
7ff120b4 | 7336 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7337 | |
7338 | case 0x2: | |
7ff120b4 | 7339 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
7340 | |
7341 | default: | |
7ff120b4 | 7342 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7343 | } |
7344 | ||
7345 | case 0x9: | |
7346 | { | |
7347 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
7348 | switch ((insn & 0xe00000) >> 21) | |
7349 | { | |
7350 | case 0x1: case 0x3: | |
7351 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
7352 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
7353 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
7354 | |
7355 | case 0x2: | |
7ff120b4 | 7356 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7357 | |
7358 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7359 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
7360 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
7361 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
7362 | |
7363 | default: | |
7ff120b4 | 7364 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7365 | } |
7366 | } | |
7367 | ||
7368 | case 0xa: | |
7ff120b4 | 7369 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
7370 | |
7371 | case 0xb: | |
7372 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 7373 | /* ldc/ldc2 lit. */ |
7ff120b4 | 7374 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7375 | else |
7ff120b4 | 7376 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7377 | |
7378 | case 0xc: | |
7379 | if (bit (insn, 4)) | |
7ff120b4 | 7380 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7381 | else |
7ff120b4 | 7382 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7383 | |
7384 | case 0xd: | |
7385 | if (bit (insn, 4)) | |
7ff120b4 | 7386 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7387 | else |
7ff120b4 | 7388 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7389 | |
7390 | default: | |
7ff120b4 | 7391 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7392 | } |
7393 | } | |
7394 | ||
7395 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
7396 | ||
7397 | static int | |
7ff120b4 YQ |
7398 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
7399 | struct regcache *regs, | |
1152d984 | 7400 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7401 | { |
7402 | unsigned int op2 = bits (insn, 4, 6); | |
7403 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
7404 | |
7405 | switch (op2) | |
7406 | { | |
7407 | case 0x0: | |
7ff120b4 | 7408 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
7409 | |
7410 | case 0x1: | |
7411 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 7412 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7413 | else if (op == 0x3) |
7ff120b4 | 7414 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 7415 | else |
7ff120b4 | 7416 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7417 | |
7418 | case 0x2: | |
7419 | if (op == 0x1) | |
dda83cd7 | 7420 | /* Not really supported. */ |
7ff120b4 | 7421 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 7422 | else |
7ff120b4 | 7423 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7424 | |
7425 | case 0x3: | |
7426 | if (op == 0x1) | |
7ff120b4 | 7427 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 7428 | regs, dsc); /* blx register. */ |
cca44b1b | 7429 | else |
7ff120b4 | 7430 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7431 | |
7432 | case 0x5: | |
7ff120b4 | 7433 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
7434 | |
7435 | case 0x7: | |
7436 | if (op == 0x1) | |
7ff120b4 | 7437 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 7438 | else if (op == 0x3) |
dda83cd7 | 7439 | /* Not really supported. */ |
7ff120b4 | 7440 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 7441 | /* Fall through. */ |
cca44b1b JB |
7442 | |
7443 | default: | |
7ff120b4 | 7444 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7445 | } |
7446 | } | |
7447 | ||
7448 | static int | |
7ff120b4 YQ |
7449 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
7450 | struct regcache *regs, | |
1152d984 | 7451 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7452 | { |
7453 | if (bit (insn, 25)) | |
7454 | switch (bits (insn, 20, 24)) | |
7455 | { | |
7456 | case 0x10: | |
7ff120b4 | 7457 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
7458 | |
7459 | case 0x14: | |
7ff120b4 | 7460 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
7461 | |
7462 | case 0x12: case 0x16: | |
7ff120b4 | 7463 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
7464 | |
7465 | default: | |
7ff120b4 | 7466 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7467 | } |
7468 | else | |
7469 | { | |
7470 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
7471 | ||
7472 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 7473 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7474 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 7475 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7476 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 7477 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 7478 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 7479 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 7480 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 7481 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 7482 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 7483 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 7484 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 7485 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
7486 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
7487 | dsc); | |
cca44b1b JB |
7488 | } |
7489 | ||
7490 | /* Should be unreachable. */ | |
7491 | return 1; | |
7492 | } | |
7493 | ||
7494 | static int | |
7ff120b4 YQ |
7495 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
7496 | struct regcache *regs, | |
1152d984 | 7497 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7498 | { |
7499 | int a = bit (insn, 25), b = bit (insn, 4); | |
7500 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
7501 | |
7502 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
7503 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 7504 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
7505 | else if ((!a && (op1 & 0x17) == 0x02) |
7506 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 7507 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
7508 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
7509 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 7510 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
7511 | else if ((!a && (op1 & 0x17) == 0x03) |
7512 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 7513 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
7514 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
7515 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 7516 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
7517 | else if ((!a && (op1 & 0x17) == 0x06) |
7518 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 7519 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
7520 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
7521 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 7522 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
7523 | else if ((!a && (op1 & 0x17) == 0x07) |
7524 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 7525 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
7526 | |
7527 | /* Should be unreachable. */ | |
7528 | return 1; | |
7529 | } | |
7530 | ||
7531 | static int | |
7ff120b4 | 7532 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7533 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7534 | { |
7535 | switch (bits (insn, 20, 24)) | |
7536 | { | |
7537 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 7538 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
7539 | |
7540 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 7541 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
7542 | |
7543 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
7544 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 7545 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
7546 | "decode/pack/unpack/saturate/reverse", dsc); |
7547 | ||
7548 | case 0x18: | |
7549 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
7550 | { | |
7551 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 7552 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 7553 | else |
7ff120b4 | 7554 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
7555 | } |
7556 | else | |
7ff120b4 | 7557 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7558 | |
7559 | case 0x1a: case 0x1b: | |
7560 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7561 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 7562 | else |
7ff120b4 | 7563 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7564 | |
7565 | case 0x1c: case 0x1d: | |
7566 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
7567 | { | |
7568 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 7569 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 7570 | else |
7ff120b4 | 7571 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
7572 | } |
7573 | else | |
7ff120b4 | 7574 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7575 | |
7576 | case 0x1e: case 0x1f: | |
7577 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7578 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 7579 | else |
7ff120b4 | 7580 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7581 | } |
7582 | ||
7583 | /* Should be unreachable. */ | |
7584 | return 1; | |
7585 | } | |
7586 | ||
7587 | static int | |
615234c1 | 7588 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 7589 | struct regcache *regs, |
1152d984 | 7590 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7591 | { |
7592 | if (bit (insn, 25)) | |
7ff120b4 | 7593 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 7594 | else |
7ff120b4 | 7595 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7596 | } |
7597 | ||
7598 | static int | |
7ff120b4 YQ |
7599 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
7600 | struct regcache *regs, | |
1152d984 | 7601 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7602 | { |
7603 | unsigned int opcode = bits (insn, 20, 24); | |
7604 | ||
7605 | switch (opcode) | |
7606 | { | |
7607 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 7608 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
7609 | |
7610 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
7611 | case 0x12: case 0x16: | |
7ff120b4 | 7612 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
7613 | |
7614 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
7615 | case 0x13: case 0x17: | |
7ff120b4 | 7616 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
7617 | |
7618 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7619 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7620 | /* Note: no writeback for these instructions. Bit 25 will always be | |
7621 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 7622 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7623 | } |
7624 | ||
7625 | /* Should be unreachable. */ | |
7626 | return 1; | |
7627 | } | |
7628 | ||
34518530 YQ |
7629 | /* Decode shifted register instructions. */ |
7630 | ||
7631 | static int | |
7632 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
7633 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7634 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7635 | { |
7636 | /* PC is only allowed to be used in instruction MOV. */ | |
7637 | ||
7638 | unsigned int op = bits (insn1, 5, 8); | |
7639 | unsigned int rn = bits (insn1, 0, 3); | |
7640 | ||
7641 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
7642 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
7643 | else | |
7644 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7645 | "dp (shift reg)", dsc); | |
7646 | } | |
7647 | ||
7648 | ||
7649 | /* Decode extension register load/store. Exactly the same as | |
7650 | arm_decode_ext_reg_ld_st. */ | |
7651 | ||
7652 | static int | |
7653 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
7654 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7655 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7656 | { |
7657 | unsigned int opcode = bits (insn1, 4, 8); | |
7658 | ||
7659 | switch (opcode) | |
7660 | { | |
7661 | case 0x04: case 0x05: | |
7662 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7663 | "vfp/neon vmov", dsc); | |
7664 | ||
7665 | case 0x08: case 0x0c: /* 01x00 */ | |
7666 | case 0x0a: case 0x0e: /* 01x10 */ | |
7667 | case 0x12: case 0x16: /* 10x10 */ | |
7668 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7669 | "vfp/neon vstm/vpush", dsc); | |
7670 | ||
7671 | case 0x09: case 0x0d: /* 01x01 */ | |
7672 | case 0x0b: case 0x0f: /* 01x11 */ | |
7673 | case 0x13: case 0x17: /* 10x11 */ | |
7674 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7675 | "vfp/neon vldm/vpop", dsc); | |
7676 | ||
7677 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7678 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7679 | "vstr", dsc); | |
7680 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7681 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
7682 | } | |
7683 | ||
7684 | /* Should be unreachable. */ | |
7685 | return 1; | |
7686 | } | |
7687 | ||
cca44b1b | 7688 | static int |
12545665 | 7689 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7690 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7691 | { |
7692 | unsigned int op1 = bits (insn, 20, 25); | |
7693 | int op = bit (insn, 4); | |
7694 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
7695 | |
7696 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 7697 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7698 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
7699 | && (coproc & 0xe) != 0xa) | |
7700 | /* stc/stc2. */ | |
7ff120b4 | 7701 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7702 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
7703 | && (coproc & 0xe) != 0xa) | |
7704 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 7705 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7706 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 7707 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 7708 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 7709 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 7710 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7711 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 7712 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7713 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7714 | else if ((op1 & 0x30) == 0x20 && !op) |
7715 | { | |
7716 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 7717 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 7718 | else |
7ff120b4 | 7719 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7720 | } |
7721 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 7722 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 7723 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7724 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7725 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7726 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7727 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 7728 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 7729 | else |
7ff120b4 | 7730 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
7731 | } |
7732 | ||
34518530 YQ |
7733 | static int |
7734 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
7735 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7736 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7737 | { |
7738 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
7739 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
7740 | unsigned int bit_9 = bit (insn1, 9); | |
7741 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
7742 | |
7743 | if (bit_9 == 0) | |
7744 | { | |
7745 | if (bit_5_8 == 2) | |
7746 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7747 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
7748 | dsc); | |
7749 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
7750 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7751 | else | |
7752 | { | |
7753 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
7754 | if ((coproc & 0xe) == 0xa) | |
7755 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
7756 | dsc); | |
7757 | else /* coproc is not 101x. */ | |
7758 | { | |
7759 | if (bit_4 == 0) /* STC/STC2. */ | |
7760 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7761 | "stc/stc2", dsc); | |
405feb71 | 7762 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
7763 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
7764 | regs, dsc); | |
7765 | } | |
7766 | } | |
7767 | } | |
7768 | else | |
7769 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
7770 | ||
7771 | return 0; | |
7772 | } | |
7773 | ||
7774 | static void | |
7775 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7776 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
7777 | { |
7778 | /* ADR Rd, #imm | |
7779 | ||
7780 | Rewrite as: | |
7781 | ||
7782 | Preparation: Rd <- PC | |
7783 | Insn: ADD Rd, #imm | |
7784 | Cleanup: Null. | |
7785 | */ | |
7786 | ||
7787 | /* Rd <- PC */ | |
7788 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7789 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
7790 | } | |
7791 | ||
7792 | static int | |
7793 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7794 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
7795 | int rd, unsigned int imm) |
7796 | { | |
7797 | ||
7798 | /* Encoding T2: ADDS Rd, #imm */ | |
7799 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
7800 | ||
7801 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7802 | ||
7803 | return 0; | |
7804 | } | |
7805 | ||
7806 | static int | |
7807 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
7808 | struct regcache *regs, | |
1152d984 | 7809 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7810 | { |
7811 | unsigned int rd = bits (insn, 8, 10); | |
7812 | unsigned int imm8 = bits (insn, 0, 7); | |
7813 | ||
136821d9 SM |
7814 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
7815 | rd, imm8, insn); | |
34518530 YQ |
7816 | |
7817 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
7818 | } | |
7819 | ||
7820 | static int | |
7821 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
7822 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7823 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7824 | { |
7825 | unsigned int rd = bits (insn2, 8, 11); | |
7826 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
7827 | extract raw immediate encoding rather than computing immediate. When | |
7828 | generating ADD or SUB instruction, we can simply perform OR operation to | |
7829 | set immediate into ADD. */ | |
7830 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
7831 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
7832 | ||
136821d9 SM |
7833 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
7834 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
7835 | |
7836 | if (bit (insn1, 7)) /* Encoding T2 */ | |
7837 | { | |
7838 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
7839 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
7840 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7841 | } | |
7842 | else /* Encoding T3 */ | |
7843 | { | |
7844 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
7845 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
7846 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7847 | } | |
7848 | dsc->numinsns = 2; | |
7849 | ||
7850 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7851 | ||
7852 | return 0; | |
7853 | } | |
7854 | ||
7855 | static int | |
615234c1 | 7856 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7857 | struct regcache *regs, |
1152d984 | 7858 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7859 | { |
7860 | unsigned int rt = bits (insn1, 8, 10); | |
7861 | unsigned int pc; | |
7862 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7863 | |
7864 | /* LDR Rd, #imm8 | |
7865 | ||
7866 | Rwrite as: | |
7867 | ||
7868 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7869 | ||
7870 | Insn: LDR R0, [R2, R3]; | |
7871 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7872 | ||
136821d9 | 7873 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7874 | |
7875 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7876 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7877 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7878 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7879 | /* The assembler calculates the required value of the offset from the | |
7880 | Align(PC,4) value of this instruction to the label. */ | |
7881 | pc = pc & 0xfffffffc; | |
7882 | ||
7883 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7884 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7885 | ||
7886 | dsc->rd = rt; | |
7887 | dsc->u.ldst.xfersize = 4; | |
7888 | dsc->u.ldst.rn = 0; | |
7889 | dsc->u.ldst.immed = 0; | |
7890 | dsc->u.ldst.writeback = 0; | |
7891 | dsc->u.ldst.restore_r4 = 0; | |
7892 | ||
7893 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7894 | ||
7895 | dsc->cleanup = &cleanup_load; | |
7896 | ||
7897 | return 0; | |
7898 | } | |
7899 | ||
405feb71 | 7900 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
7901 | |
7902 | static int | |
7903 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
7904 | struct regcache *regs, | |
1152d984 | 7905 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7906 | { |
7907 | int non_zero = bit (insn1, 11); | |
7908 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
7909 | CORE_ADDR from = dsc->insn_addr; | |
7910 | int rn = bits (insn1, 0, 2); | |
7911 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
7912 | ||
7913 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
7914 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
7915 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
7916 | condition is false, let it be, cleanup_branch will do nothing. */ | |
7917 | if (dsc->u.branch.cond) | |
7918 | { | |
7919 | dsc->u.branch.cond = INST_AL; | |
7920 | dsc->u.branch.dest = from + 4 + imm5; | |
7921 | } | |
7922 | else | |
7923 | dsc->u.branch.dest = from + 2; | |
7924 | ||
7925 | dsc->u.branch.link = 0; | |
7926 | dsc->u.branch.exchange = 0; | |
7927 | ||
136821d9 SM |
7928 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
7929 | non_zero ? "cbnz" : "cbz", | |
7930 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
7931 | |
7932 | dsc->modinsn[0] = THUMB_NOP; | |
7933 | ||
7934 | dsc->cleanup = &cleanup_branch; | |
7935 | return 0; | |
7936 | } | |
7937 | ||
7938 | /* Copy Table Branch Byte/Halfword */ | |
7939 | static int | |
7940 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7941 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7942 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7943 | { |
7944 | ULONGEST rn_val, rm_val; | |
7945 | int is_tbh = bit (insn2, 4); | |
7946 | CORE_ADDR halfwords = 0; | |
7947 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7948 | ||
7949 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7950 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7951 | ||
7952 | if (is_tbh) | |
7953 | { | |
7954 | gdb_byte buf[2]; | |
7955 | ||
7956 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7957 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7958 | } | |
7959 | else | |
7960 | { | |
7961 | gdb_byte buf[1]; | |
7962 | ||
7963 | target_read_memory (rn_val + rm_val, buf, 1); | |
7964 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7965 | } | |
7966 | ||
136821d9 SM |
7967 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
7968 | is_tbh ? "tbh" : "tbb", | |
7969 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7970 | (unsigned int) halfwords); | |
34518530 YQ |
7971 | |
7972 | dsc->u.branch.cond = INST_AL; | |
7973 | dsc->u.branch.link = 0; | |
7974 | dsc->u.branch.exchange = 0; | |
7975 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7976 | ||
7977 | dsc->cleanup = &cleanup_branch; | |
7978 | ||
7979 | return 0; | |
7980 | } | |
7981 | ||
7982 | static void | |
7983 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7984 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7985 | { |
7986 | /* PC <- r7 */ | |
7987 | int val = displaced_read_reg (regs, dsc, 7); | |
7988 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7989 | ||
7990 | /* r7 <- r8 */ | |
7991 | val = displaced_read_reg (regs, dsc, 8); | |
7992 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7993 | ||
7994 | /* r8 <- tmp[0] */ | |
7995 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7996 | ||
7997 | } | |
7998 | ||
7999 | static int | |
615234c1 | 8000 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 8001 | struct regcache *regs, |
1152d984 | 8002 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8003 | { |
8004 | dsc->u.block.regmask = insn1 & 0x00ff; | |
8005 | ||
8006 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
8007 | to : | |
8008 | ||
8009 | (1) register list is full, that is, r0-r7 are used. | |
8010 | Prepare: tmp[0] <- r8 | |
8011 | ||
8012 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
8013 | MOV r8, r7; Move value of r7 to r8; | |
8014 | POP {r7}; Store PC value into r7. | |
8015 | ||
8016 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
8017 | ||
8018 | (2) register list is not full, supposing there are N registers in | |
8019 | register list (except PC, 0 <= N <= 7). | |
8020 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
8021 | ||
8022 | POP {r0, r1, ...., rN}; | |
8023 | ||
8024 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
8025 | from tmp[] properly. | |
8026 | */ | |
136821d9 SM |
8027 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
8028 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
8029 | |
8030 | if (dsc->u.block.regmask == 0xff) | |
8031 | { | |
8032 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
8033 | ||
8034 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
8035 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
8036 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
8037 | ||
8038 | dsc->numinsns = 3; | |
8039 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
8040 | } | |
8041 | else | |
8042 | { | |
5f661e03 | 8043 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
8044 | unsigned int i; |
8045 | unsigned int new_regmask; | |
34518530 YQ |
8046 | |
8047 | for (i = 0; i < num_in_list + 1; i++) | |
8048 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
8049 | ||
8050 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
8051 | ||
136821d9 SM |
8052 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
8053 | "modified list %.4x", | |
8054 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
8055 | |
8056 | dsc->u.block.regmask |= 0x8000; | |
8057 | dsc->u.block.writeback = 0; | |
8058 | dsc->u.block.cond = INST_AL; | |
8059 | ||
8060 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
8061 | ||
8062 | dsc->cleanup = &cleanup_block_load_pc; | |
8063 | } | |
8064 | ||
8065 | return 0; | |
8066 | } | |
8067 | ||
8068 | static void | |
8069 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8070 | struct regcache *regs, | |
1152d984 | 8071 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8072 | { |
8073 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
8074 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
8075 | int err = 0; | |
8076 | ||
8077 | /* 16-bit thumb instructions. */ | |
8078 | switch (op_bit_12_15) | |
8079 | { | |
8080 | /* Shift (imme), add, subtract, move and compare. */ | |
8081 | case 0: case 1: case 2: case 3: | |
8082 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8083 | "shift/add/sub/mov/cmp", | |
8084 | dsc); | |
8085 | break; | |
8086 | case 4: | |
8087 | switch (op_bit_10_11) | |
8088 | { | |
8089 | case 0: /* Data-processing */ | |
8090 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8091 | "data-processing", | |
8092 | dsc); | |
8093 | break; | |
8094 | case 1: /* Special data instructions and branch and exchange. */ | |
8095 | { | |
8096 | unsigned short op = bits (insn1, 7, 9); | |
8097 | if (op == 6 || op == 7) /* BX or BLX */ | |
8098 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
8099 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
8100 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
8101 | else | |
8102 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
8103 | dsc); | |
8104 | } | |
8105 | break; | |
8106 | default: /* LDR (literal) */ | |
8107 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
8108 | } | |
8109 | break; | |
8110 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
8111 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
8112 | break; | |
8113 | case 10: | |
8114 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
8115 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
8116 | else /* Generate SP-relative address */ | |
8117 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
8118 | break; | |
8119 | case 11: /* Misc 16-bit instructions */ | |
8120 | { | |
8121 | switch (bits (insn1, 8, 11)) | |
8122 | { | |
8123 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
8124 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
8125 | break; | |
8126 | case 12: case 13: /* POP */ | |
8127 | if (bit (insn1, 8)) /* PC is in register list. */ | |
8128 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
8129 | else | |
8130 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
8131 | break; | |
8132 | case 15: /* If-Then, and hints */ | |
8133 | if (bits (insn1, 0, 3)) | |
8134 | /* If-Then makes up to four following instructions conditional. | |
8135 | IT instruction itself is not conditional, so handle it as a | |
8136 | common unmodified instruction. */ | |
8137 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
8138 | dsc); | |
8139 | else | |
8140 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
8141 | break; | |
8142 | default: | |
8143 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
8144 | } | |
8145 | } | |
8146 | break; | |
8147 | case 12: | |
8148 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
8149 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
8150 | else /* Load multiple registers */ | |
8151 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
8152 | break; | |
8153 | case 13: /* Conditional branch and supervisor call */ | |
8154 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
8155 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8156 | else | |
8157 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
8158 | break; | |
8159 | case 14: /* Unconditional branch */ | |
8160 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8161 | break; | |
8162 | default: | |
8163 | err = 1; | |
8164 | } | |
8165 | ||
8166 | if (err) | |
f34652de | 8167 | internal_error (_("thumb_process_displaced_16bit_insn: Instruction decode error")); |
34518530 YQ |
8168 | } |
8169 | ||
8170 | static int | |
8171 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
8172 | uint16_t insn1, uint16_t insn2, | |
8173 | struct regcache *regs, | |
1152d984 | 8174 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8175 | { |
8176 | int rt = bits (insn2, 12, 15); | |
8177 | int rn = bits (insn1, 0, 3); | |
8178 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
8179 | |
8180 | switch (bits (insn1, 5, 6)) | |
8181 | { | |
8182 | case 0: /* Load byte and memory hints */ | |
8183 | if (rt == 0xf) /* PLD/PLI */ | |
8184 | { | |
8185 | if (rn == 0xf) | |
8186 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
8187 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
8188 | else | |
8189 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8190 | "pli/pld", dsc); | |
8191 | } | |
8192 | else | |
8193 | { | |
8194 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
8195 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8196 | 1); | |
8197 | else | |
8198 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8199 | "ldrb{reg, immediate}/ldrbt", | |
8200 | dsc); | |
8201 | } | |
8202 | ||
8203 | break; | |
8204 | case 1: /* Load halfword and memory hints. */ | |
8205 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
8206 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8207 | "pld/unalloc memhint", dsc); | |
8208 | else | |
8209 | { | |
8210 | if (rn == 0xf) | |
8211 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8212 | 2); | |
8213 | else | |
8214 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8215 | "ldrh/ldrht", dsc); | |
8216 | } | |
8217 | break; | |
8218 | case 2: /* Load word */ | |
8219 | { | |
8220 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
8221 | ||
8222 | if (rn == 0xf) | |
8223 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
8224 | else if (op1 == 0x1) /* Encoding T3 */ | |
8225 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
8226 | 0, 1); | |
8227 | else /* op1 == 0x0 */ | |
8228 | { | |
8229 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
8230 | /* LDR (immediate) */ | |
8231 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8232 | dsc, bit (insn2, 8), 1); | |
8233 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
8234 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8235 | "ldrt", dsc); | |
8236 | else | |
8237 | /* LDR (register) */ | |
8238 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8239 | dsc, 0, 0); | |
8240 | } | |
8241 | break; | |
8242 | } | |
8243 | default: | |
8244 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
8245 | break; | |
8246 | } | |
8247 | return 0; | |
8248 | } | |
8249 | ||
8250 | static void | |
8251 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8252 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 8253 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8254 | { |
8255 | int err = 0; | |
8256 | unsigned short op = bit (insn2, 15); | |
8257 | unsigned int op1 = bits (insn1, 11, 12); | |
8258 | ||
8259 | switch (op1) | |
8260 | { | |
8261 | case 1: | |
8262 | { | |
8263 | switch (bits (insn1, 9, 10)) | |
8264 | { | |
8265 | case 0: | |
8266 | if (bit (insn1, 6)) | |
8267 | { | |
405feb71 | 8268 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
8269 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
8270 | && bits (insn2, 5, 7) == 0) | |
8271 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
8272 | dsc); | |
8273 | else | |
8274 | /* PC is not allowed to use in load/store {dual, exclusive} | |
8275 | instructions. */ | |
8276 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8277 | "load/store dual/ex", dsc); | |
8278 | } | |
8279 | else /* load/store multiple */ | |
8280 | { | |
8281 | switch (bits (insn1, 7, 8)) | |
8282 | { | |
8283 | case 0: case 3: /* SRS, RFE */ | |
8284 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8285 | "srs/rfe", dsc); | |
8286 | break; | |
8287 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
8288 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
8289 | break; | |
8290 | } | |
8291 | } | |
8292 | break; | |
8293 | ||
8294 | case 1: | |
8295 | /* Data-processing (shift register). */ | |
8296 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
8297 | dsc); | |
8298 | break; | |
8299 | default: /* Coprocessor instructions. */ | |
8300 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8301 | break; | |
8302 | } | |
8303 | break; | |
8304 | } | |
8305 | case 2: /* op1 = 2 */ | |
8306 | if (op) /* Branch and misc control. */ | |
8307 | { | |
8308 | if (bit (insn2, 14) /* BLX/BL */ | |
8309 | || bit (insn2, 12) /* Unconditional branch */ | |
8310 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
8311 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
8312 | else | |
8313 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8314 | "misc ctrl", dsc); | |
8315 | } | |
8316 | else | |
8317 | { | |
8318 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
8319 | { | |
b926417a | 8320 | int dp_op = bits (insn1, 4, 8); |
34518530 | 8321 | int rn = bits (insn1, 0, 3); |
b926417a | 8322 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
8323 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
8324 | regs, dsc); | |
8325 | else | |
8326 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8327 | "dp/pb", dsc); | |
8328 | } | |
405feb71 | 8329 | else /* Data processing (modified immediate) */ |
34518530 YQ |
8330 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
8331 | "dp/mi", dsc); | |
8332 | } | |
8333 | break; | |
8334 | case 3: /* op1 = 3 */ | |
8335 | switch (bits (insn1, 9, 10)) | |
8336 | { | |
8337 | case 0: | |
8338 | if (bit (insn1, 4)) | |
8339 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
8340 | regs, dsc); | |
8341 | else /* NEON Load/Store and Store single data item */ | |
8342 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8343 | "neon elt/struct load/store", | |
8344 | dsc); | |
8345 | break; | |
8346 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
8347 | switch (bits (insn1, 7, 8)) | |
8348 | { | |
8349 | case 0: case 1: /* Data processing (register) */ | |
8350 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8351 | "dp(reg)", dsc); | |
8352 | break; | |
8353 | case 2: /* Multiply and absolute difference */ | |
8354 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8355 | "mul/mua/diff", dsc); | |
8356 | break; | |
8357 | case 3: /* Long multiply and divide */ | |
8358 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8359 | "lmul/lmua", dsc); | |
8360 | break; | |
8361 | } | |
8362 | break; | |
8363 | default: /* Coprocessor instructions */ | |
8364 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8365 | break; | |
8366 | } | |
8367 | break; | |
8368 | default: | |
8369 | err = 1; | |
8370 | } | |
8371 | ||
8372 | if (err) | |
f34652de | 8373 | internal_error (_("thumb_process_displaced_32bit_insn: Instruction decode error")); |
34518530 YQ |
8374 | |
8375 | } | |
8376 | ||
b434a28f YQ |
8377 | static void |
8378 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 8379 | struct regcache *regs, |
1152d984 | 8380 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 8381 | { |
34518530 YQ |
8382 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8383 | uint16_t insn1 | |
8384 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
8385 | ||
136821d9 SM |
8386 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
8387 | insn1, (unsigned long) from); | |
34518530 YQ |
8388 | |
8389 | dsc->is_thumb = 1; | |
8390 | dsc->insn_size = thumb_insn_size (insn1); | |
8391 | if (thumb_insn_size (insn1) == 4) | |
8392 | { | |
8393 | uint16_t insn2 | |
8394 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
8395 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
8396 | } | |
8397 | else | |
8398 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
8399 | } |
8400 | ||
cca44b1b | 8401 | void |
b434a28f YQ |
8402 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
8403 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 8404 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
8405 | { |
8406 | int err = 0; | |
b434a28f YQ |
8407 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8408 | uint32_t insn; | |
cca44b1b JB |
8409 | |
8410 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
8411 | here and override below if/when necessary. */ | |
8412 | dsc->numinsns = 1; | |
8413 | dsc->insn_addr = from; | |
8414 | dsc->scratch_base = to; | |
8415 | dsc->cleanup = NULL; | |
8416 | dsc->wrote_to_pc = 0; | |
8417 | ||
b434a28f | 8418 | if (!displaced_in_arm_mode (regs)) |
12545665 | 8419 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 8420 | |
4db71c0b YQ |
8421 | dsc->is_thumb = 0; |
8422 | dsc->insn_size = 4; | |
b434a28f | 8423 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
8424 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
8425 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 8426 | |
cca44b1b | 8427 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 8428 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8429 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
8430 | { | |
8431 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 8432 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8433 | break; |
8434 | ||
8435 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 8436 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8437 | break; |
8438 | ||
8439 | case 0x7: | |
7ff120b4 | 8440 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
8441 | break; |
8442 | ||
8443 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 8444 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8445 | break; |
8446 | ||
8447 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 8448 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8449 | break; |
8450 | } | |
8451 | ||
8452 | if (err) | |
f34652de | 8453 | internal_error (_("arm_process_displaced_insn: Instruction decode error")); |
cca44b1b JB |
8454 | } |
8455 | ||
8456 | /* Actually set up the scratch space for a displaced instruction. */ | |
8457 | ||
8458 | void | |
8459 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
8460 | CORE_ADDR to, |
8461 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 8462 | { |
08106042 | 8463 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
4db71c0b | 8464 | unsigned int i, len, offset; |
cca44b1b | 8465 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 8466 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 8467 | const gdb_byte *bkp_insn; |
cca44b1b | 8468 | |
4db71c0b | 8469 | offset = 0; |
cca44b1b JB |
8470 | /* Poke modified instruction(s). */ |
8471 | for (i = 0; i < dsc->numinsns; i++) | |
8472 | { | |
136821d9 SM |
8473 | if (size == 4) |
8474 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
8475 | dsc->modinsn[i], (unsigned long) to + offset); | |
8476 | else if (size == 2) | |
8477 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
8478 | (unsigned short) dsc->modinsn[i], | |
8479 | (unsigned long) to + offset); | |
4db71c0b | 8480 | |
4db71c0b YQ |
8481 | write_memory_unsigned_integer (to + offset, size, |
8482 | byte_order_for_code, | |
cca44b1b | 8483 | dsc->modinsn[i]); |
4db71c0b YQ |
8484 | offset += size; |
8485 | } | |
8486 | ||
8487 | /* Choose the correct breakpoint instruction. */ | |
8488 | if (dsc->is_thumb) | |
8489 | { | |
8490 | bkp_insn = tdep->thumb_breakpoint; | |
8491 | len = tdep->thumb_breakpoint_size; | |
8492 | } | |
8493 | else | |
8494 | { | |
8495 | bkp_insn = tdep->arm_breakpoint; | |
8496 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
8497 | } |
8498 | ||
8499 | /* Put breakpoint afterwards. */ | |
4db71c0b | 8500 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 8501 | |
136821d9 SM |
8502 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
8503 | paddress (gdbarch, to)); | |
cca44b1b JB |
8504 | } |
8505 | ||
cca44b1b JB |
8506 | /* Entry point for cleaning things up after a displaced instruction has been |
8507 | single-stepped. */ | |
8508 | ||
8509 | void | |
8510 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 8511 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
8512 | CORE_ADDR from, CORE_ADDR to, |
8513 | struct regcache *regs) | |
8514 | { | |
1152d984 SM |
8515 | arm_displaced_step_copy_insn_closure *dsc |
8516 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 8517 | |
cca44b1b JB |
8518 | if (dsc->cleanup) |
8519 | dsc->cleanup (gdbarch, regs, dsc); | |
8520 | ||
8521 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
8522 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
8523 | dsc->insn_addr + dsc->insn_size); | |
8524 | ||
cca44b1b JB |
8525 | } |
8526 | ||
8527 | #include "bfd-in2.h" | |
8528 | #include "libcoff.h" | |
8529 | ||
8530 | static int | |
8531 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
8532 | { | |
f0c2e3e0 AB |
8533 | gdb_disassemble_info *di |
8534 | = static_cast<gdb_disassemble_info *> (info->application_data); | |
e47ad6c0 | 8535 | struct gdbarch *gdbarch = di->arch (); |
9779414d DJ |
8536 | |
8537 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
8538 | { |
8539 | static asymbol *asym; | |
8540 | static combined_entry_type ce; | |
8541 | static struct coff_symbol_struct csym; | |
8542 | static struct bfd fake_bfd; | |
8543 | static bfd_target fake_target; | |
8544 | ||
8545 | if (csym.native == NULL) | |
8546 | { | |
8547 | /* Create a fake symbol vector containing a Thumb symbol. | |
8548 | This is solely so that the code in print_insn_little_arm() | |
8549 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
8550 | the presence of a Thumb symbol and switch to decoding | |
8551 | Thumb instructions. */ | |
8552 | ||
8553 | fake_target.flavour = bfd_target_coff_flavour; | |
8554 | fake_bfd.xvec = &fake_target; | |
8555 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
8556 | csym.native = &ce; | |
8557 | csym.symbol.the_bfd = &fake_bfd; | |
8558 | csym.symbol.name = "fake"; | |
8559 | asym = (asymbol *) & csym; | |
8560 | } | |
8561 | ||
8562 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
8563 | info->symbols = &asym; | |
8564 | } | |
8565 | else | |
8566 | info->symbols = NULL; | |
8567 | ||
e60eb288 YQ |
8568 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
8569 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
8570 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
8571 | the assert on the mismatch of info->mach and |
8572 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
8573 | default_print_insn. */ | |
3047c786 TV |
8574 | if (current_program_space->exec_bfd () != NULL |
8575 | && (current_program_space->exec_bfd ()->arch_info | |
8576 | == gdbarch_bfd_arch_info (gdbarch))) | |
e60eb288 YQ |
8577 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
8578 | ||
6394c606 | 8579 | return default_print_insn (memaddr, info); |
cca44b1b JB |
8580 | } |
8581 | ||
8582 | /* The following define instruction sequences that will cause ARM | |
8583 | cpu's to take an undefined instruction trap. These are used to | |
8584 | signal a breakpoint to GDB. | |
8585 | ||
8586 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
8587 | modes. A different instruction is required for each mode. The ARM | |
8588 | cpu's can also be big or little endian. Thus four different | |
8589 | instructions are needed to support all cases. | |
8590 | ||
8591 | Note: ARMv4 defines several new instructions that will take the | |
8592 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
8593 | not in fact add the new instructions. The new undefined | |
8594 | instructions in ARMv4 are all instructions that had no defined | |
8595 | behaviour in earlier chips. There is no guarantee that they will | |
8596 | raise an exception, but may be treated as NOP's. In practice, it | |
8597 | may only safe to rely on instructions matching: | |
8598 | ||
8599 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
8600 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
8601 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
8602 | ||
0963b4bd | 8603 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
8604 | following use a condition predicate of ALWAYS so it is always TRUE. |
8605 | ||
8606 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
8607 | and NetBSD all use a software interrupt rather than an undefined | |
8608 | instruction to force a trap. This can be handled by by the | |
8609 | abi-specific code during establishment of the gdbarch vector. */ | |
8610 | ||
8611 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
8612 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
8613 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
8614 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
8615 | ||
948f8e3d PA |
8616 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
8617 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
8618 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
8619 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 8620 | |
cd6c3b4f YQ |
8621 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
8622 | ||
d19280ad YQ |
8623 | static int |
8624 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b | 8625 | { |
08106042 | 8626 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 8627 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 8628 | |
9779414d | 8629 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
8630 | { |
8631 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
8632 | |
8633 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
8634 | check whether we are replacing a 32-bit instruction. */ | |
8635 | if (tdep->thumb2_breakpoint != NULL) | |
8636 | { | |
8637 | gdb_byte buf[2]; | |
d19280ad | 8638 | |
177321bd DJ |
8639 | if (target_read_memory (*pcptr, buf, 2) == 0) |
8640 | { | |
8641 | unsigned short inst1; | |
d19280ad | 8642 | |
177321bd | 8643 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 8644 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 8645 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
8646 | } |
8647 | } | |
8648 | ||
d19280ad | 8649 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
8650 | } |
8651 | else | |
d19280ad YQ |
8652 | return ARM_BP_KIND_ARM; |
8653 | ||
8654 | } | |
8655 | ||
cd6c3b4f YQ |
8656 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
8657 | ||
d19280ad YQ |
8658 | static const gdb_byte * |
8659 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
8660 | { | |
08106042 | 8661 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
d19280ad YQ |
8662 | |
8663 | switch (kind) | |
cca44b1b | 8664 | { |
d19280ad YQ |
8665 | case ARM_BP_KIND_ARM: |
8666 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 8667 | return tdep->arm_breakpoint; |
d19280ad YQ |
8668 | case ARM_BP_KIND_THUMB: |
8669 | *size = tdep->thumb_breakpoint_size; | |
8670 | return tdep->thumb_breakpoint; | |
8671 | case ARM_BP_KIND_THUMB2: | |
8672 | *size = tdep->thumb2_breakpoint_size; | |
8673 | return tdep->thumb2_breakpoint; | |
8674 | default: | |
8675 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
8676 | } |
8677 | } | |
8678 | ||
833b7ab5 YQ |
8679 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
8680 | ||
8681 | static int | |
8682 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
8683 | struct regcache *regcache, | |
8684 | CORE_ADDR *pcptr) | |
8685 | { | |
8686 | gdb_byte buf[4]; | |
8687 | ||
8688 | /* Check the memory pointed by PC is readable. */ | |
8689 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
8690 | { | |
8691 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
8692 | |
8693 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
8694 | &arm_get_next_pcs_ops, | |
8695 | gdbarch_byte_order (gdbarch), | |
8696 | gdbarch_byte_order_for_code (gdbarch), | |
8697 | 0, | |
8698 | regcache); | |
8699 | ||
a0ff9e1a | 8700 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
8701 | |
8702 | /* If MEMADDR is the next instruction of current pc, do the | |
8703 | software single step computation, and get the thumb mode by | |
8704 | the destination address. */ | |
a0ff9e1a | 8705 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
8706 | { |
8707 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
8708 | { | |
833b7ab5 YQ |
8709 | if (IS_THUMB_ADDR (pc)) |
8710 | { | |
8711 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
8712 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8713 | } | |
8714 | else | |
8715 | return ARM_BP_KIND_ARM; | |
8716 | } | |
8717 | } | |
833b7ab5 YQ |
8718 | } |
8719 | ||
8720 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8721 | } | |
8722 | ||
cca44b1b JB |
8723 | /* Extract from an array REGBUF containing the (raw) register state a |
8724 | function return value of type TYPE, and copy that, in virtual | |
8725 | format, into VALBUF. */ | |
8726 | ||
8727 | static void | |
8728 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
8729 | gdb_byte *valbuf) | |
8730 | { | |
ac7936df | 8731 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b | 8732 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 8733 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
cca44b1b | 8734 | |
78134374 | 8735 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b | 8736 | { |
345bd07c | 8737 | switch (tdep->fp_model) |
cca44b1b JB |
8738 | { |
8739 | case ARM_FLOAT_FPA: | |
8740 | { | |
8741 | /* The value is in register F0 in internal format. We need to | |
8742 | extract the raw value and then convert it to the desired | |
8743 | internal type. */ | |
f0452268 | 8744 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 8745 | |
dca08e1f | 8746 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
8747 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
8748 | valbuf, type); | |
cca44b1b JB |
8749 | } |
8750 | break; | |
8751 | ||
8752 | case ARM_FLOAT_SOFT_FPA: | |
8753 | case ARM_FLOAT_SOFT_VFP: | |
8754 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
8755 | not using the VFP ABI code. */ | |
8756 | case ARM_FLOAT_VFP: | |
dca08e1f | 8757 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
df86565b | 8758 | if (type->length () > 4) |
f0452268 AH |
8759 | regs->cooked_read (ARM_A1_REGNUM + 1, |
8760 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
8761 | break; |
8762 | ||
8763 | default: | |
f34652de | 8764 | internal_error (_("arm_extract_return_value: " |
0963b4bd | 8765 | "Floating point model not supported")); |
cca44b1b JB |
8766 | break; |
8767 | } | |
8768 | } | |
78134374 SM |
8769 | else if (type->code () == TYPE_CODE_INT |
8770 | || type->code () == TYPE_CODE_CHAR | |
8771 | || type->code () == TYPE_CODE_BOOL | |
8772 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8773 | || TYPE_IS_REFERENCE (type) |
a6617193 JB |
8774 | || type->code () == TYPE_CODE_ENUM |
8775 | || is_fixed_point_type (type)) | |
cca44b1b | 8776 | { |
b021a221 MS |
8777 | /* If the type is a plain integer, then the access is |
8778 | straight-forward. Otherwise we have to play around a bit | |
8779 | more. */ | |
df86565b | 8780 | int len = type->length (); |
cca44b1b JB |
8781 | int regno = ARM_A1_REGNUM; |
8782 | ULONGEST tmp; | |
8783 | ||
8784 | while (len > 0) | |
8785 | { | |
8786 | /* By using store_unsigned_integer we avoid having to do | |
8787 | anything special for small big-endian values. */ | |
8788 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
8789 | store_unsigned_integer (valbuf, | |
f0452268 AH |
8790 | (len > ARM_INT_REGISTER_SIZE |
8791 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 8792 | byte_order, tmp); |
f0452268 AH |
8793 | len -= ARM_INT_REGISTER_SIZE; |
8794 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8795 | } |
8796 | } | |
8797 | else | |
8798 | { | |
8799 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8800 | been stored to word-aligned memory and then loaded into |
8801 | registers with 32-bit load instruction(s). */ | |
df86565b | 8802 | int len = type->length (); |
cca44b1b | 8803 | int regno = ARM_A1_REGNUM; |
f0452268 | 8804 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
8805 | |
8806 | while (len > 0) | |
8807 | { | |
dca08e1f | 8808 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 8809 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
8810 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
8811 | len -= ARM_INT_REGISTER_SIZE; | |
8812 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8813 | } |
8814 | } | |
8815 | } | |
8816 | ||
8817 | ||
8818 | /* Will a function return an aggregate type in memory or in a | |
8819 | register? Return 0 if an aggregate type can be returned in a | |
8820 | register, 1 if it must be returned in memory. */ | |
8821 | ||
8822 | static int | |
8823 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
8824 | { | |
cca44b1b JB |
8825 | enum type_code code; |
8826 | ||
f168693b | 8827 | type = check_typedef (type); |
cca44b1b | 8828 | |
b13c8ab2 YQ |
8829 | /* Simple, non-aggregate types (ie not including vectors and |
8830 | complex) are always returned in a register (or registers). */ | |
78134374 | 8831 | code = type->code (); |
b13c8ab2 YQ |
8832 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
8833 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
8834 | return 0; | |
cca44b1b | 8835 | |
bd63c870 | 8836 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
8837 | { |
8838 | /* Vector values should be returned using ARM registers if they | |
8839 | are not over 16 bytes. */ | |
df86565b | 8840 | return (type->length () > 16); |
c4312b19 YQ |
8841 | } |
8842 | ||
08106042 | 8843 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 8844 | if (tdep->arm_abi != ARM_ABI_APCS) |
cca44b1b | 8845 | { |
b13c8ab2 YQ |
8846 | /* The AAPCS says all aggregates not larger than a word are returned |
8847 | in a register. */ | |
df86565b | 8848 | if (type->length () <= ARM_INT_REGISTER_SIZE |
bab22d06 | 8849 | && language_pass_by_reference (type).trivially_copyable) |
b13c8ab2 YQ |
8850 | return 0; |
8851 | ||
cca44b1b JB |
8852 | return 1; |
8853 | } | |
b13c8ab2 YQ |
8854 | else |
8855 | { | |
8856 | int nRc; | |
cca44b1b | 8857 | |
b13c8ab2 YQ |
8858 | /* All aggregate types that won't fit in a register must be returned |
8859 | in memory. */ | |
df86565b | 8860 | if (type->length () > ARM_INT_REGISTER_SIZE |
bab22d06 | 8861 | || !language_pass_by_reference (type).trivially_copyable) |
b13c8ab2 | 8862 | return 1; |
cca44b1b | 8863 | |
b13c8ab2 YQ |
8864 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8865 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8866 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8867 | offset of each addressable subfield must be zero. Note that bit |
8868 | fields are not addressable, and all addressable subfields of | |
8869 | unions always start at offset zero. | |
cca44b1b | 8870 | |
b13c8ab2 YQ |
8871 | This function is based on the behaviour of GCC 2.95.1. |
8872 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8873 | |
b13c8ab2 YQ |
8874 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8875 | parameters correctly for a function returning the following | |
8876 | structure: struct { float f;}; This should be returned in memory, | |
8877 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8878 | know of any way to detect if a function like the above has been | |
8879 | compiled with the correct calling convention. */ | |
8880 | ||
8881 | /* Assume all other aggregate types can be returned in a register. | |
8882 | Run a check for structures, unions and arrays. */ | |
8883 | nRc = 0; | |
67255d04 | 8884 | |
b13c8ab2 YQ |
8885 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8886 | { | |
8887 | int i; | |
8888 | /* Need to check if this struct/union is "integer" like. For | |
8889 | this to be true, its size must be less than or equal to | |
f0452268 | 8890 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8891 | subfield must be zero. Note that bit fields are not |
8892 | addressable, and unions always start at offset zero. If any | |
8893 | of the subfields is a floating point type, the struct/union | |
8894 | cannot be an integer type. */ | |
8895 | ||
8896 | /* For each field in the object, check: | |
8897 | 1) Is it FP? --> yes, nRc = 1; | |
8898 | 2) Is it addressable (bitpos != 0) and | |
8899 | not packed (bitsize == 0)? | |
8900 | --> yes, nRc = 1 | |
8901 | */ | |
8902 | ||
1f704f76 | 8903 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 8904 | { |
b13c8ab2 YQ |
8905 | enum type_code field_type_code; |
8906 | ||
8907 | field_type_code | |
940da03e | 8908 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
8909 | |
8910 | /* Is it a floating point type field? */ | |
8911 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
8912 | { |
8913 | nRc = 1; | |
8914 | break; | |
8915 | } | |
b13c8ab2 YQ |
8916 | |
8917 | /* If bitpos != 0, then we have to care about it. */ | |
b610c045 | 8918 | if (type->field (i).loc_bitpos () != 0) |
b13c8ab2 YQ |
8919 | { |
8920 | /* Bitfields are not addressable. If the field bitsize is | |
8921 | zero, then the field is not packed. Hence it cannot be | |
8922 | a bitfield or any other packed type. */ | |
8923 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
8924 | { | |
8925 | nRc = 1; | |
8926 | break; | |
8927 | } | |
8928 | } | |
67255d04 RE |
8929 | } |
8930 | } | |
67255d04 | 8931 | |
b13c8ab2 YQ |
8932 | return nRc; |
8933 | } | |
67255d04 RE |
8934 | } |
8935 | ||
34e8f22d RE |
8936 | /* Write into appropriate registers a function return value of type |
8937 | TYPE, given in virtual format. */ | |
8938 | ||
8939 | static void | |
b508a996 | 8940 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 8941 | const gdb_byte *valbuf) |
34e8f22d | 8942 | { |
ac7936df | 8943 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 8944 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 8945 | |
78134374 | 8946 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 8947 | { |
f0452268 | 8948 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
08106042 | 8949 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
34e8f22d | 8950 | |
345bd07c | 8951 | switch (tdep->fp_model) |
08216dd7 RE |
8952 | { |
8953 | case ARM_FLOAT_FPA: | |
8954 | ||
3b2ca824 | 8955 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 8956 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
8957 | break; |
8958 | ||
fd50bc42 | 8959 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8960 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8961 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8962 | not using the VFP ABI code. */ | |
8963 | case ARM_FLOAT_VFP: | |
b66f5587 | 8964 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
df86565b | 8965 | if (type->length () > 4) |
f0452268 AH |
8966 | regs->cooked_write (ARM_A1_REGNUM + 1, |
8967 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
8968 | break; |
8969 | ||
8970 | default: | |
f34652de | 8971 | internal_error (_("arm_store_return_value: Floating " |
9b20d036 | 8972 | "point model not supported")); |
08216dd7 RE |
8973 | break; |
8974 | } | |
34e8f22d | 8975 | } |
78134374 SM |
8976 | else if (type->code () == TYPE_CODE_INT |
8977 | || type->code () == TYPE_CODE_CHAR | |
8978 | || type->code () == TYPE_CODE_BOOL | |
8979 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8980 | || TYPE_IS_REFERENCE (type) |
78134374 | 8981 | || type->code () == TYPE_CODE_ENUM) |
b508a996 | 8982 | { |
df86565b | 8983 | if (type->length () <= 4) |
b508a996 RE |
8984 | { |
8985 | /* Values of one word or less are zero/sign-extended and | |
8986 | returned in r0. */ | |
f0452268 | 8987 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8988 | LONGEST val = unpack_long (type, valbuf); |
8989 | ||
f0452268 | 8990 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 8991 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
8992 | } |
8993 | else | |
8994 | { | |
8995 | /* Integral values greater than one word are stored in consecutive | |
8996 | registers starting with r0. This will always be a multiple of | |
8997 | the regiser size. */ | |
df86565b | 8998 | int len = type->length (); |
b508a996 RE |
8999 | int regno = ARM_A1_REGNUM; |
9000 | ||
9001 | while (len > 0) | |
9002 | { | |
b66f5587 | 9003 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
9004 | len -= ARM_INT_REGISTER_SIZE; |
9005 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
9006 | } |
9007 | } | |
9008 | } | |
34e8f22d | 9009 | else |
b508a996 RE |
9010 | { |
9011 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
9012 | been stored to word-aligned memory and then loaded into |
9013 | registers with 32-bit load instruction(s). */ | |
df86565b | 9014 | int len = type->length (); |
b508a996 | 9015 | int regno = ARM_A1_REGNUM; |
f0452268 | 9016 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
9017 | |
9018 | while (len > 0) | |
9019 | { | |
9020 | memcpy (tmpbuf, valbuf, | |
f0452268 | 9021 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 9022 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
9023 | len -= ARM_INT_REGISTER_SIZE; |
9024 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
9025 | } |
9026 | } | |
34e8f22d RE |
9027 | } |
9028 | ||
2af48f68 PB |
9029 | |
9030 | /* Handle function return values. */ | |
9031 | ||
9032 | static enum return_value_convention | |
6a3a010b | 9033 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
9034 | struct type *valtype, struct regcache *regcache, |
9035 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 9036 | { |
08106042 | 9037 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
6a3a010b | 9038 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
9039 | enum arm_vfp_cprc_base_type vfp_base_type; |
9040 | int vfp_base_count; | |
9041 | ||
9042 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
9043 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
9044 | { | |
9045 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
9046 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
9047 | int i; | |
9048 | for (i = 0; i < vfp_base_count; i++) | |
9049 | { | |
58d6951d DJ |
9050 | if (reg_char == 'q') |
9051 | { | |
9052 | if (writebuf) | |
9053 | arm_neon_quad_write (gdbarch, regcache, i, | |
9054 | writebuf + i * unit_length); | |
9055 | ||
9056 | if (readbuf) | |
9057 | arm_neon_quad_read (gdbarch, regcache, i, | |
9058 | readbuf + i * unit_length); | |
9059 | } | |
9060 | else | |
9061 | { | |
9062 | char name_buf[4]; | |
9063 | int regnum; | |
9064 | ||
8c042590 | 9065 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
9066 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9067 | strlen (name_buf)); | |
9068 | if (writebuf) | |
b66f5587 | 9069 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 9070 | if (readbuf) |
dca08e1f | 9071 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 9072 | } |
90445bd3 DJ |
9073 | } |
9074 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9075 | } | |
7c00367c | 9076 | |
78134374 SM |
9077 | if (valtype->code () == TYPE_CODE_STRUCT |
9078 | || valtype->code () == TYPE_CODE_UNION | |
9079 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 9080 | { |
bab22d06 LM |
9081 | /* From the AAPCS document: |
9082 | ||
9083 | Result return: | |
9084 | ||
9085 | A Composite Type larger than 4 bytes, or whose size cannot be | |
9086 | determined statically by both caller and callee, is stored in memory | |
9087 | at an address passed as an extra argument when the function was | |
9088 | called (Parameter Passing, rule A.4). The memory to be used for the | |
9089 | result may be modified at any point during the function call. | |
9090 | ||
9091 | Parameter Passing: | |
9092 | ||
9093 | A.4: If the subroutine is a function that returns a result in memory, | |
9094 | then the address for the result is placed in r0 and the NCRN is set | |
9095 | to r1. */ | |
7c00367c MK |
9096 | if (tdep->struct_return == pcc_struct_return |
9097 | || arm_return_in_memory (gdbarch, valtype)) | |
bab22d06 LM |
9098 | { |
9099 | if (readbuf) | |
9100 | { | |
9101 | CORE_ADDR addr; | |
9102 | ||
9103 | regcache->cooked_read (ARM_A1_REGNUM, &addr); | |
df86565b | 9104 | read_memory (addr, readbuf, valtype->length ()); |
bab22d06 LM |
9105 | } |
9106 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
9107 | } | |
2af48f68 | 9108 | } |
78134374 | 9109 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
9110 | { |
9111 | if (arm_return_in_memory (gdbarch, valtype)) | |
9112 | return RETURN_VALUE_STRUCT_CONVENTION; | |
9113 | } | |
7052e42c | 9114 | |
2af48f68 PB |
9115 | if (writebuf) |
9116 | arm_store_return_value (valtype, regcache, writebuf); | |
9117 | ||
9118 | if (readbuf) | |
9119 | arm_extract_return_value (valtype, regcache, readbuf); | |
9120 | ||
9121 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9122 | } | |
9123 | ||
9124 | ||
9df628e0 | 9125 | static int |
bd2b40ac | 9126 | arm_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
9df628e0 | 9127 | { |
e17a4113 | 9128 | struct gdbarch *gdbarch = get_frame_arch (frame); |
08106042 | 9129 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
e17a4113 | 9130 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9df628e0 | 9131 | CORE_ADDR jb_addr; |
f0452268 | 9132 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 9133 | |
60ade65d | 9134 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
9135 | |
9136 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 9137 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
9138 | return 0; |
9139 | ||
f0452268 | 9140 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
9141 | return 1; |
9142 | } | |
40eadf04 SP |
9143 | /* A call to cmse secure entry function "foo" at "a" is modified by |
9144 | GNU ld as "b". | |
9145 | a) bl xxxx <foo> | |
9146 | ||
9147 | <foo> | |
9148 | xxxx: | |
9149 | ||
9150 | b) bl yyyy <__acle_se_foo> | |
9151 | ||
9152 | section .gnu.sgstubs: | |
9153 | <foo> | |
9154 | yyyy: sg // secure gateway | |
9155 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
9156 | ||
9157 | <__acle_se_foo> | |
9158 | xxxx: | |
9159 | ||
9160 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
9161 | trampoline and does not exist in source code. This function returns the | |
9162 | target pc "xxxx". For more details please refer to section 5.4 | |
9163 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
9164 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
9165 | document on www.developer.arm.com. */ | |
9166 | ||
9167 | static CORE_ADDR | |
9168 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
9169 | { | |
9170 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
9171 | char *target_name = (char *) alloca (target_len); | |
9172 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
9173 | ||
9174 | struct bound_minimal_symbol minsym | |
9175 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
9176 | ||
9177 | if (minsym.minsym != nullptr) | |
4aeddc50 | 9178 | return minsym.value_address (); |
40eadf04 SP |
9179 | |
9180 | return 0; | |
9181 | } | |
9182 | ||
9183 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
9184 | ||
9185 | static bool | |
9186 | arm_is_sgstubs_section (struct obj_section *sec) | |
9187 | { | |
9188 | return (sec != nullptr | |
9189 | && sec->the_bfd_section != nullptr | |
9190 | && sec->the_bfd_section->name != nullptr | |
9191 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
9192 | } | |
9df628e0 | 9193 | |
faa95490 DJ |
9194 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
9195 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
9196 | |
9197 | CORE_ADDR | |
bd2b40ac | 9198 | arm_skip_stub (frame_info_ptr frame, CORE_ADDR pc) |
c906108c | 9199 | { |
2c02bd72 | 9200 | const char *name; |
faa95490 | 9201 | int namelen; |
c906108c SS |
9202 | CORE_ADDR start_addr; |
9203 | ||
9204 | /* Find the starting address and name of the function containing the PC. */ | |
9205 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
9206 | { |
9207 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
9208 | check here. */ | |
9209 | start_addr = arm_skip_bx_reg (frame, pc); | |
9210 | if (start_addr != 0) | |
9211 | return start_addr; | |
9212 | ||
9213 | return 0; | |
9214 | } | |
c906108c | 9215 | |
faa95490 DJ |
9216 | /* If PC is in a Thumb call or return stub, return the address of the |
9217 | target PC, which is in a register. The thunk functions are called | |
9218 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
9219 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
9220 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
9221 | if (startswith (name, "_call_via_") |
9222 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 9223 | { |
ed9a39eb | 9224 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 9225 | target PC. */ |
a121b7c1 | 9226 | static const char *table[15] = |
c5aa993b JM |
9227 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
9228 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
9229 | }; | |
c906108c | 9230 | int regno; |
faa95490 | 9231 | int offset = strlen (name) - 2; |
c906108c SS |
9232 | |
9233 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 9234 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 9235 | return get_frame_register_unsigned (frame, regno); |
c906108c | 9236 | } |
ed9a39eb | 9237 | |
faa95490 DJ |
9238 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
9239 | non-interworking calls to foo. We could decode the stubs | |
9240 | to find the target but it's easier to use the symbol table. */ | |
9241 | namelen = strlen (name); | |
9242 | if (name[0] == '_' && name[1] == '_' | |
9243 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 9244 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 9245 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 9246 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
9247 | { |
9248 | char *target_name; | |
9249 | int target_len = namelen - 2; | |
3b7344d5 | 9250 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
9251 | struct objfile *objfile; |
9252 | struct obj_section *sec; | |
9253 | ||
9254 | if (name[namelen - 1] == 'b') | |
9255 | target_len -= strlen ("_from_thumb"); | |
9256 | else | |
9257 | target_len -= strlen ("_from_arm"); | |
9258 | ||
224c3ddb | 9259 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
9260 | memcpy (target_name, name + 2, target_len); |
9261 | target_name[target_len] = '\0'; | |
9262 | ||
9263 | sec = find_pc_section (pc); | |
9264 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
9265 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 9266 | if (minsym.minsym != NULL) |
4aeddc50 | 9267 | return minsym.value_address (); |
faa95490 DJ |
9268 | else |
9269 | return 0; | |
9270 | } | |
9271 | ||
40eadf04 SP |
9272 | struct obj_section *section = find_pc_section (pc); |
9273 | ||
9274 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
9275 | if (arm_is_sgstubs_section (section)) | |
9276 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
9277 | ||
c5aa993b | 9278 | return 0; /* not a stub */ |
c906108c SS |
9279 | } |
9280 | ||
28e97307 DJ |
9281 | static void |
9282 | arm_update_current_architecture (void) | |
fd50bc42 | 9283 | { |
28e97307 | 9284 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 9285 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 9286 | return; |
fd50bc42 | 9287 | |
28e97307 | 9288 | /* Update the architecture. */ |
b447dd03 | 9289 | gdbarch_info info; |
28e97307 | 9290 | if (!gdbarch_update_p (info)) |
f34652de | 9291 | internal_error (_("could not update architecture")); |
fd50bc42 RE |
9292 | } |
9293 | ||
9294 | static void | |
eb4c3f4a | 9295 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
9296 | struct cmd_list_element *c) |
9297 | { | |
570dc176 | 9298 | int fp_model; |
fd50bc42 RE |
9299 | |
9300 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
9301 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
9302 | { | |
aead7601 | 9303 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
9304 | break; |
9305 | } | |
9306 | ||
9307 | if (fp_model == ARM_FLOAT_LAST) | |
f34652de | 9308 | internal_error (_("Invalid fp model accepted: %s."), |
fd50bc42 RE |
9309 | current_fp_model); |
9310 | ||
28e97307 | 9311 | arm_update_current_architecture (); |
fd50bc42 RE |
9312 | } |
9313 | ||
9314 | static void | |
08546159 AC |
9315 | show_fp_model (struct ui_file *file, int from_tty, |
9316 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 9317 | { |
28e97307 | 9318 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 9319 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9320 | { |
9321 | arm_gdbarch_tdep *tdep | |
08106042 | 9322 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9323 | |
9324 | gdb_printf (file, _("\ | |
28e97307 | 9325 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9326 | fp_model_strings[tdep->fp_model]); |
9327 | } | |
28e97307 | 9328 | else |
6cb06a8c | 9329 | gdb_printf (file, _("\ |
28e97307 | 9330 | The current ARM floating point model is \"%s\".\n"), |
6cb06a8c | 9331 | fp_model_strings[arm_fp_model]); |
28e97307 DJ |
9332 | } |
9333 | ||
9334 | static void | |
eb4c3f4a | 9335 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
9336 | struct cmd_list_element *c) |
9337 | { | |
570dc176 | 9338 | int arm_abi; |
28e97307 DJ |
9339 | |
9340 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
9341 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
9342 | { | |
aead7601 | 9343 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
9344 | break; |
9345 | } | |
9346 | ||
9347 | if (arm_abi == ARM_ABI_LAST) | |
f34652de | 9348 | internal_error (_("Invalid ABI accepted: %s."), |
28e97307 DJ |
9349 | arm_abi_string); |
9350 | ||
9351 | arm_update_current_architecture (); | |
9352 | } | |
9353 | ||
9354 | static void | |
9355 | arm_show_abi (struct ui_file *file, int from_tty, | |
9356 | struct cmd_list_element *c, const char *value) | |
9357 | { | |
28e97307 | 9358 | if (arm_abi_global == ARM_ABI_AUTO |
f5656ead | 9359 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9360 | { |
9361 | arm_gdbarch_tdep *tdep | |
08106042 | 9362 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9363 | |
9364 | gdb_printf (file, _("\ | |
28e97307 | 9365 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9366 | arm_abi_strings[tdep->arm_abi]); |
9367 | } | |
28e97307 | 9368 | else |
6cb06a8c TT |
9369 | gdb_printf (file, _("The current ARM ABI is \"%s\".\n"), |
9370 | arm_abi_string); | |
fd50bc42 RE |
9371 | } |
9372 | ||
0428b8f5 DJ |
9373 | static void |
9374 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
9375 | struct cmd_list_element *c, const char *value) | |
9376 | { | |
6cb06a8c TT |
9377 | gdb_printf (file, |
9378 | _("The current execution mode assumed " | |
9379 | "(when symbols are unavailable) is \"%s\".\n"), | |
9380 | arm_fallback_mode_string); | |
0428b8f5 DJ |
9381 | } |
9382 | ||
9383 | static void | |
9384 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
9385 | struct cmd_list_element *c, const char *value) | |
9386 | { | |
6cb06a8c TT |
9387 | gdb_printf (file, |
9388 | _("The current execution mode assumed " | |
9389 | "(even when symbols are available) is \"%s\".\n"), | |
9390 | arm_force_mode_string); | |
0428b8f5 DJ |
9391 | } |
9392 | ||
ef273377 CL |
9393 | static void |
9394 | arm_show_unwind_secure_frames (struct ui_file *file, int from_tty, | |
9395 | struct cmd_list_element *c, const char *value) | |
9396 | { | |
9397 | gdb_printf (file, | |
9398 | _("Usage of non-secure to secure exception stack unwinding is %s.\n"), | |
9399 | arm_unwind_secure_frames ? "on" : "off"); | |
9400 | } | |
9401 | ||
afd7eef0 RE |
9402 | /* If the user changes the register disassembly style used for info |
9403 | register and other commands, we have to also switch the style used | |
9404 | in opcodes for disassembly output. This function is run in the "set | |
9405 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
9406 | |
9407 | static void | |
eb4c3f4a | 9408 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 9409 | struct cmd_list_element *c) |
bc90b915 | 9410 | { |
65b48a81 PB |
9411 | /* Convert the short style name into the long style name (eg, reg-names-*) |
9412 | before calling the generic set_disassembler_options() function. */ | |
9413 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
9414 | set_disassembler_options (&long_name[0]); | |
9415 | } | |
9416 | ||
9417 | static void | |
9418 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
9419 | struct cmd_list_element *c, const char *value) | |
9420 | { | |
9421 | struct gdbarch *gdbarch = get_current_arch (); | |
9422 | char *options = get_disassembler_options (gdbarch); | |
9423 | const char *style = ""; | |
9424 | int len = 0; | |
f995bbe8 | 9425 | const char *opt; |
65b48a81 PB |
9426 | |
9427 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
08dedd66 | 9428 | if (startswith (opt, "reg-names-")) |
65b48a81 PB |
9429 | { |
9430 | style = &opt[strlen ("reg-names-")]; | |
9431 | len = strcspn (style, ","); | |
9432 | } | |
9433 | ||
6cb06a8c | 9434 | gdb_printf (file, "The disassembly style is \"%.*s\".\n", len, style); |
bc90b915 FN |
9435 | } |
9436 | \f | |
966fbf70 | 9437 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 9438 | static const char * |
d93859e2 | 9439 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 9440 | { |
08106042 | 9441 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 9442 | |
ecbf5d4f | 9443 | if (is_s_pseudo (gdbarch, i)) |
58d6951d | 9444 | { |
ecbf5d4f | 9445 | static const char *const s_pseudo_names[] = { |
58d6951d DJ |
9446 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
9447 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
9448 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
9449 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
9450 | }; | |
9451 | ||
ecbf5d4f | 9452 | return s_pseudo_names[i - tdep->s_pseudo_base]; |
58d6951d DJ |
9453 | } |
9454 | ||
ecbf5d4f | 9455 | if (is_q_pseudo (gdbarch, i)) |
58d6951d | 9456 | { |
ecbf5d4f | 9457 | static const char *const q_pseudo_names[] = { |
58d6951d DJ |
9458 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", |
9459 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
9460 | }; | |
9461 | ||
ecbf5d4f | 9462 | return q_pseudo_names[i - tdep->q_pseudo_base]; |
58d6951d DJ |
9463 | } |
9464 | ||
ae66a8f1 SP |
9465 | if (is_mve_pseudo (gdbarch, i)) |
9466 | return "p0"; | |
9467 | ||
a01567f4 LM |
9468 | /* RA_AUTH_CODE is used for unwinding only. Do not assign it a name. */ |
9469 | if (is_pacbti_pseudo (gdbarch, i)) | |
9470 | return ""; | |
9471 | ||
ff6f572f DJ |
9472 | if (i >= ARRAY_SIZE (arm_register_names)) |
9473 | /* These registers are only supported on targets which supply | |
9474 | an XML description. */ | |
9475 | return ""; | |
9476 | ||
ecbf5d4f | 9477 | /* Non-pseudo registers. */ |
966fbf70 RE |
9478 | return arm_register_names[i]; |
9479 | } | |
9480 | ||
082fc60d RE |
9481 | /* Test whether the coff symbol specific value corresponds to a Thumb |
9482 | function. */ | |
9483 | ||
9484 | static int | |
9485 | coff_sym_is_thumb (int val) | |
9486 | { | |
f8bf5763 PM |
9487 | return (val == C_THUMBEXT |
9488 | || val == C_THUMBSTAT | |
9489 | || val == C_THUMBEXTFUNC | |
9490 | || val == C_THUMBSTATFUNC | |
9491 | || val == C_THUMBLABEL); | |
082fc60d RE |
9492 | } |
9493 | ||
9494 | /* arm_coff_make_msymbol_special() | |
9495 | arm_elf_make_msymbol_special() | |
9496 | ||
9497 | These functions test whether the COFF or ELF symbol corresponds to | |
9498 | an address in thumb code, and set a "special" bit in a minimal | |
9499 | symbol to indicate that it does. */ | |
9500 | ||
34e8f22d | 9501 | static void |
082fc60d RE |
9502 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
9503 | { | |
39d911fc TP |
9504 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
9505 | ||
9506 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 9507 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
9508 | MSYMBOL_SET_SPECIAL (msym); |
9509 | } | |
9510 | ||
34e8f22d | 9511 | static void |
082fc60d RE |
9512 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
9513 | { | |
9514 | if (coff_sym_is_thumb (val)) | |
9515 | MSYMBOL_SET_SPECIAL (msym); | |
9516 | } | |
9517 | ||
60c5725c DJ |
9518 | static void |
9519 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
9520 | asymbol *sym) | |
9521 | { | |
9522 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 9523 | struct arm_per_bfd *data; |
60c5725c DJ |
9524 | struct arm_mapping_symbol new_map_sym; |
9525 | ||
9526 | gdb_assert (name[0] == '$'); | |
9527 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
9528 | return; | |
9529 | ||
98badbfd | 9530 | data = arm_bfd_data_key.get (objfile->obfd.get ()); |
60c5725c | 9531 | if (data == NULL) |
98badbfd | 9532 | data = arm_bfd_data_key.emplace (objfile->obfd.get (), |
bd5766ec | 9533 | objfile->obfd->section_count); |
54cc7474 | 9534 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 9535 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
9536 | |
9537 | new_map_sym.value = sym->value; | |
9538 | new_map_sym.type = name[1]; | |
9539 | ||
4838e44c SM |
9540 | /* Insert at the end, the vector will be sorted on first use. */ |
9541 | map.push_back (new_map_sym); | |
60c5725c DJ |
9542 | } |
9543 | ||
756fe439 | 9544 | static void |
61a1198a | 9545 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 9546 | { |
ac7936df | 9547 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 9548 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
9549 | |
9550 | /* If necessary, set the T bit. */ | |
9551 | if (arm_apcs_32) | |
9552 | { | |
9779414d | 9553 | ULONGEST val, t_bit; |
61a1198a | 9554 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
9555 | t_bit = arm_psr_thumb_bit (gdbarch); |
9556 | if (arm_pc_is_thumb (gdbarch, pc)) | |
9557 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
9558 | val | t_bit); | |
756fe439 | 9559 | else |
61a1198a | 9560 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 9561 | val & ~t_bit); |
756fe439 DJ |
9562 | } |
9563 | } | |
123dc839 | 9564 | |
58d6951d DJ |
9565 | /* Read the contents of a NEON quad register, by reading from two |
9566 | double registers. This is used to implement the quad pseudo | |
9567 | registers, and for argument passing in case the quad registers are | |
9568 | missing; vectors are passed in quad registers when using the VFP | |
9569 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
9570 | the quad register, in [0, 15]. */ | |
9571 | ||
05d1431c | 9572 | static enum register_status |
849d0ba8 | 9573 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9574 | int regnum, gdb_byte *buf) |
9575 | { | |
9576 | char name_buf[4]; | |
9577 | gdb_byte reg_buf[8]; | |
9578 | int offset, double_regnum; | |
05d1431c | 9579 | enum register_status status; |
58d6951d | 9580 | |
8c042590 | 9581 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9582 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9583 | strlen (name_buf)); | |
9584 | ||
9585 | /* d0 is always the least significant half of q0. */ | |
9586 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9587 | offset = 8; | |
9588 | else | |
9589 | offset = 0; | |
9590 | ||
03f50fc8 | 9591 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9592 | if (status != REG_VALID) |
9593 | return status; | |
58d6951d DJ |
9594 | memcpy (buf + offset, reg_buf, 8); |
9595 | ||
9596 | offset = 8 - offset; | |
03f50fc8 | 9597 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
9598 | if (status != REG_VALID) |
9599 | return status; | |
58d6951d | 9600 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
9601 | |
9602 | return REG_VALID; | |
58d6951d DJ |
9603 | } |
9604 | ||
ae66a8f1 SP |
9605 | /* Read the contents of the MVE pseudo register REGNUM and store it |
9606 | in BUF. */ | |
9607 | ||
9608 | static enum register_status | |
9609 | arm_mve_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, | |
9610 | int regnum, gdb_byte *buf) | |
9611 | { | |
08106042 | 9612 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9613 | |
9614 | /* P0 is the first 16 bits of VPR. */ | |
9615 | return regcache->raw_read_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9616 | } | |
9617 | ||
05d1431c | 9618 | static enum register_status |
849d0ba8 | 9619 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9620 | int regnum, gdb_byte *buf) |
9621 | { | |
9622 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9623 | char name_buf[4]; | |
9624 | gdb_byte reg_buf[8]; | |
9625 | int offset, double_regnum; | |
08106042 | 9626 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9627 | |
9628 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9629 | |
ecbf5d4f LM |
9630 | if (is_q_pseudo (gdbarch, regnum)) |
9631 | { | |
9632 | /* Quad-precision register. */ | |
9633 | return arm_neon_quad_read (gdbarch, regcache, | |
9634 | regnum - tdep->q_pseudo_base, buf); | |
9635 | } | |
ae66a8f1 SP |
9636 | else if (is_mve_pseudo (gdbarch, regnum)) |
9637 | return arm_mve_pseudo_read (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9638 | else |
9639 | { | |
05d1431c PA |
9640 | enum register_status status; |
9641 | ||
ecbf5d4f | 9642 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9643 | /* Single-precision register. */ |
9644 | gdb_assert (regnum < 32); | |
9645 | ||
9646 | /* s0 is always the least significant half of d0. */ | |
9647 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9648 | offset = (regnum & 1) ? 0 : 4; | |
9649 | else | |
9650 | offset = (regnum & 1) ? 4 : 0; | |
9651 | ||
8c042590 | 9652 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9653 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9654 | strlen (name_buf)); | |
9655 | ||
03f50fc8 | 9656 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9657 | if (status == REG_VALID) |
9658 | memcpy (buf, reg_buf + offset, 4); | |
9659 | return status; | |
58d6951d DJ |
9660 | } |
9661 | } | |
9662 | ||
9663 | /* Store the contents of BUF to a NEON quad register, by writing to | |
9664 | two double registers. This is used to implement the quad pseudo | |
9665 | registers, and for argument passing in case the quad registers are | |
9666 | missing; vectors are passed in quad registers when using the VFP | |
9667 | ABI, even if a NEON unit is not present. REGNUM is the index | |
9668 | of the quad register, in [0, 15]. */ | |
9669 | ||
9670 | static void | |
9671 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9672 | int regnum, const gdb_byte *buf) | |
9673 | { | |
9674 | char name_buf[4]; | |
58d6951d DJ |
9675 | int offset, double_regnum; |
9676 | ||
8c042590 | 9677 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9678 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9679 | strlen (name_buf)); | |
9680 | ||
9681 | /* d0 is always the least significant half of q0. */ | |
9682 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9683 | offset = 8; | |
9684 | else | |
9685 | offset = 0; | |
9686 | ||
10eaee5f | 9687 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 9688 | offset = 8 - offset; |
10eaee5f | 9689 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
9690 | } |
9691 | ||
ae66a8f1 SP |
9692 | /* Store the contents of BUF to the MVE pseudo register REGNUM. */ |
9693 | ||
9694 | static void | |
9695 | arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9696 | int regnum, const gdb_byte *buf) | |
9697 | { | |
08106042 | 9698 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9699 | |
9700 | /* P0 is the first 16 bits of VPR. */ | |
9701 | regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9702 | } | |
9703 | ||
58d6951d DJ |
9704 | static void |
9705 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9706 | int regnum, const gdb_byte *buf) | |
9707 | { | |
9708 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9709 | char name_buf[4]; | |
9710 | gdb_byte reg_buf[8]; | |
9711 | int offset, double_regnum; | |
08106042 | 9712 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9713 | |
9714 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9715 | |
ecbf5d4f LM |
9716 | if (is_q_pseudo (gdbarch, regnum)) |
9717 | { | |
9718 | /* Quad-precision register. */ | |
9719 | arm_neon_quad_write (gdbarch, regcache, | |
9720 | regnum - tdep->q_pseudo_base, buf); | |
9721 | } | |
ae66a8f1 SP |
9722 | else if (is_mve_pseudo (gdbarch, regnum)) |
9723 | arm_mve_pseudo_write (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9724 | else |
9725 | { | |
ecbf5d4f | 9726 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9727 | /* Single-precision register. */ |
9728 | gdb_assert (regnum < 32); | |
9729 | ||
9730 | /* s0 is always the least significant half of d0. */ | |
9731 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9732 | offset = (regnum & 1) ? 0 : 4; | |
9733 | else | |
9734 | offset = (regnum & 1) ? 4 : 0; | |
9735 | ||
8c042590 | 9736 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9737 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9738 | strlen (name_buf)); | |
9739 | ||
0b883586 | 9740 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 9741 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 9742 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
9743 | } |
9744 | } | |
9745 | ||
123dc839 | 9746 | static struct value * |
bd2b40ac | 9747 | value_of_arm_user_reg (frame_info_ptr frame, const void *baton) |
123dc839 | 9748 | { |
9a3c8263 | 9749 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
9750 | return value_of_register (*reg_p, frame); |
9751 | } | |
97e03143 | 9752 | \f |
70f80edf JT |
9753 | static enum gdb_osabi |
9754 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 9755 | { |
2af48f68 | 9756 | unsigned int elfosabi; |
70f80edf | 9757 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 9758 | |
70f80edf | 9759 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 9760 | |
28e97307 DJ |
9761 | if (elfosabi == ELFOSABI_ARM) |
9762 | /* GNU tools use this value. Check note sections in this case, | |
9763 | as well. */ | |
b35c1d1c TT |
9764 | { |
9765 | for (asection *sect : gdb_bfd_sections (abfd)) | |
9766 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
9767 | } | |
97e03143 | 9768 | |
28e97307 | 9769 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 9770 | return osabi; |
97e03143 RE |
9771 | } |
9772 | ||
54483882 YQ |
9773 | static int |
9774 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 9775 | const struct reggroup *group) |
54483882 | 9776 | { |
2c291032 YQ |
9777 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
9778 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
9779 | all_reggroup, of course. */ | |
54483882 | 9780 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
9781 | return (group == float_reggroup |
9782 | || group == save_reggroup | |
9783 | || group == restore_reggroup | |
9784 | || group == all_reggroup); | |
54483882 YQ |
9785 | else |
9786 | return default_register_reggroup_p (gdbarch, regnum, group); | |
9787 | } | |
9788 | ||
25f8c692 JL |
9789 | /* For backward-compatibility we allow two 'g' packet lengths with |
9790 | the remote protocol depending on whether FPA registers are | |
9791 | supplied. M-profile targets do not have FPA registers, but some | |
9792 | stubs already exist in the wild which use a 'g' packet which | |
9793 | supplies them albeit with dummy values. The packet format which | |
9794 | includes FPA registers should be considered deprecated for | |
9795 | M-profile targets. */ | |
9796 | ||
9797 | static void | |
9798 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
9799 | { | |
08106042 | 9800 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9801 | |
9802 | if (tdep->is_m) | |
25f8c692 | 9803 | { |
d105cce5 AH |
9804 | const target_desc *tdesc; |
9805 | ||
25f8c692 JL |
9806 | /* If we know from the executable this is an M-profile target, |
9807 | cater for remote targets whose register set layout is the | |
9808 | same as the FPA layout. */ | |
d105cce5 | 9809 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 9810 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9811 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 9812 | tdesc); |
25f8c692 JL |
9813 | |
9814 | /* The regular M-profile layout. */ | |
d105cce5 | 9815 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 9816 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 9817 | tdesc); |
3184d3f9 JL |
9818 | |
9819 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 9820 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 9821 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9822 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 9823 | tdesc); |
ae66a8f1 SP |
9824 | /* M-profile plus MVE. */ |
9825 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_MVE); | |
9826 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE | |
9827 | + ARM_VFP2_REGS_SIZE | |
9828 | + ARM_INT_REGISTER_SIZE, tdesc); | |
9074667a CL |
9829 | |
9830 | /* M-profile system (stack pointers). */ | |
9831 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_SYSTEM); | |
9832 | register_remote_g_packet_guess (gdbarch, 2 * ARM_INT_REGISTER_SIZE, tdesc); | |
25f8c692 JL |
9833 | } |
9834 | ||
9835 | /* Otherwise we don't have a useful guess. */ | |
9836 | } | |
9837 | ||
7eb89530 YQ |
9838 | /* Implement the code_of_frame_writable gdbarch method. */ |
9839 | ||
9840 | static int | |
bd2b40ac | 9841 | arm_code_of_frame_writable (struct gdbarch *gdbarch, frame_info_ptr frame) |
7eb89530 | 9842 | { |
08106042 | 9843 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9844 | |
9845 | if (tdep->is_m && get_frame_type (frame) == SIGTRAMP_FRAME) | |
7eb89530 YQ |
9846 | { |
9847 | /* M-profile exception frames return to some magic PCs, where | |
9848 | isn't writable at all. */ | |
9849 | return 0; | |
9850 | } | |
9851 | else | |
9852 | return 1; | |
9853 | } | |
9854 | ||
3426ae57 AH |
9855 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
9856 | to be postfixed by a version (eg armv7hl). */ | |
9857 | ||
9858 | static const char * | |
9859 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
9860 | { | |
9861 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
9862 | return "arm(v[^- ]*)?"; | |
9863 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
9864 | } | |
9865 | ||
a01567f4 LM |
9866 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
9867 | ||
9868 | static std::string | |
bd2b40ac | 9869 | arm_get_pc_address_flags (frame_info_ptr frame, CORE_ADDR pc) |
a01567f4 LM |
9870 | { |
9871 | if (get_frame_pc_masked (frame)) | |
9872 | return "PAC"; | |
9873 | ||
9874 | return ""; | |
9875 | } | |
9876 | ||
da3c6d4a MS |
9877 | /* Initialize the current architecture based on INFO. If possible, |
9878 | re-use an architecture from ARCHES, which is a list of | |
9879 | architectures already created during this debugging session. | |
97e03143 | 9880 | |
da3c6d4a MS |
9881 | Called e.g. at program startup, when reading a core file, and when |
9882 | reading a binary file. */ | |
97e03143 | 9883 | |
39bbf761 RE |
9884 | static struct gdbarch * |
9885 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
9886 | { | |
9887 | struct gdbarch *gdbarch; | |
28e97307 DJ |
9888 | struct gdbarch_list *best_arch; |
9889 | enum arm_abi_kind arm_abi = arm_abi_global; | |
9890 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 9891 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
9892 | int i; |
9893 | bool is_m = false; | |
ae7e2f45 | 9894 | bool have_sec_ext = false; |
7559c217 | 9895 | int vfp_register_count = 0; |
ecbf5d4f | 9896 | bool have_s_pseudos = false, have_q_pseudos = false; |
7559c217 CB |
9897 | bool have_wmmx_registers = false; |
9898 | bool have_neon = false; | |
9899 | bool have_fpa_registers = true; | |
9779414d | 9900 | const struct target_desc *tdesc = info.target_desc; |
ae66a8f1 SP |
9901 | bool have_vfp = false; |
9902 | bool have_mve = false; | |
a01567f4 | 9903 | bool have_pacbti = false; |
ae66a8f1 | 9904 | int mve_vpr_regnum = -1; |
ecbf5d4f | 9905 | int register_count = ARM_NUM_REGS; |
9074667a CL |
9906 | bool have_m_profile_msp = false; |
9907 | int m_profile_msp_regnum = -1; | |
9908 | int m_profile_psp_regnum = -1; | |
ae7e2f45 CL |
9909 | int m_profile_msp_ns_regnum = -1; |
9910 | int m_profile_psp_ns_regnum = -1; | |
9911 | int m_profile_msp_s_regnum = -1; | |
9912 | int m_profile_psp_s_regnum = -1; | |
92d48a1e | 9913 | int tls_regnum = 0; |
9779414d DJ |
9914 | |
9915 | /* If we have an object to base this architecture on, try to determine | |
9916 | its ABI. */ | |
9917 | ||
9918 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
9919 | { | |
9920 | int ei_osabi, e_flags; | |
9921 | ||
9922 | switch (bfd_get_flavour (info.abfd)) | |
9923 | { | |
9779414d DJ |
9924 | case bfd_target_coff_flavour: |
9925 | /* Assume it's an old APCS-style ABI. */ | |
9926 | /* XXX WinCE? */ | |
9927 | arm_abi = ARM_ABI_APCS; | |
9928 | break; | |
9929 | ||
9930 | case bfd_target_elf_flavour: | |
9931 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
9932 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
9933 | ||
9934 | if (ei_osabi == ELFOSABI_ARM) | |
9935 | { | |
9936 | /* GNU tools used to use this value, but do not for EABI | |
9937 | objects. There's nowhere to tag an EABI version | |
9938 | anyway, so assume APCS. */ | |
9939 | arm_abi = ARM_ABI_APCS; | |
9940 | } | |
d403db27 | 9941 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
9942 | { |
9943 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
9944 | |
9945 | switch (eabi_ver) | |
9946 | { | |
9947 | case EF_ARM_EABI_UNKNOWN: | |
9948 | /* Assume GNU tools. */ | |
9949 | arm_abi = ARM_ABI_APCS; | |
9950 | break; | |
9951 | ||
9952 | case EF_ARM_EABI_VER4: | |
9953 | case EF_ARM_EABI_VER5: | |
9954 | arm_abi = ARM_ABI_AAPCS; | |
9955 | /* EABI binaries default to VFP float ordering. | |
9956 | They may also contain build attributes that can | |
9957 | be used to identify if the VFP argument-passing | |
9958 | ABI is in use. */ | |
9959 | if (fp_model == ARM_FLOAT_AUTO) | |
9960 | { | |
9961 | #ifdef HAVE_ELF | |
9962 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
9963 | OBJ_ATTR_PROC, | |
9964 | Tag_ABI_VFP_args)) | |
9965 | { | |
b35b0298 | 9966 | case AEABI_VFP_args_base: |
9779414d DJ |
9967 | /* "The user intended FP parameter/result |
9968 | passing to conform to AAPCS, base | |
9969 | variant". */ | |
9970 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9971 | break; | |
b35b0298 | 9972 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9973 | /* "The user intended FP parameter/result |
9974 | passing to conform to AAPCS, VFP | |
9975 | variant". */ | |
9976 | fp_model = ARM_FLOAT_VFP; | |
9977 | break; | |
b35b0298 | 9978 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9979 | /* "The user intended FP parameter/result |
9980 | passing to conform to tool chain-specific | |
9981 | conventions" - we don't know any such | |
9982 | conventions, so leave it as "auto". */ | |
9983 | break; | |
b35b0298 | 9984 | case AEABI_VFP_args_compatible: |
5c294fee TG |
9985 | /* "Code is compatible with both the base |
9986 | and VFP variants; the user did not permit | |
9987 | non-variadic functions to pass FP | |
9988 | parameters/results" - leave it as | |
9989 | "auto". */ | |
9990 | break; | |
9779414d DJ |
9991 | default: |
9992 | /* Attribute value not mentioned in the | |
5c294fee | 9993 | November 2012 ABI, so leave it as |
9779414d DJ |
9994 | "auto". */ |
9995 | break; | |
9996 | } | |
9997 | #else | |
9998 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9999 | #endif | |
10000 | } | |
10001 | break; | |
10002 | ||
10003 | default: | |
10004 | /* Leave it as "auto". */ | |
10005 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
10006 | break; | |
10007 | } | |
10008 | ||
10009 | #ifdef HAVE_ELF | |
10010 | /* Detect M-profile programs. This only works if the | |
10011 | executable file includes build attributes; GCC does | |
10012 | copy them to the executable, but e.g. RealView does | |
10013 | not. */ | |
17cbafdb SM |
10014 | int attr_arch |
10015 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10016 | Tag_CPU_arch); | |
10017 | int attr_profile | |
10018 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10019 | Tag_CPU_arch_profile); | |
10020 | ||
9779414d DJ |
10021 | /* GCC specifies the profile for v6-M; RealView only |
10022 | specifies the profile for architectures starting with | |
10023 | V7 (as opposed to architectures with a tag | |
10024 | numerically greater than TAG_CPU_ARCH_V7). */ | |
10025 | if (!tdesc_has_registers (tdesc) | |
10026 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
10027 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
131a355f LM |
10028 | || attr_arch == TAG_CPU_ARCH_V7E_M |
10029 | || attr_arch == TAG_CPU_ARCH_V8M_BASE | |
10030 | || attr_arch == TAG_CPU_ARCH_V8M_MAIN | |
ae66a8f1 | 10031 | || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN |
9779414d | 10032 | || attr_profile == 'M')) |
7559c217 | 10033 | is_m = true; |
a01567f4 LM |
10034 | |
10035 | /* Look for attributes that indicate support for ARMv8.1-m | |
10036 | PACBTI. */ | |
10037 | if (!tdesc_has_registers (tdesc) && is_m) | |
10038 | { | |
10039 | int attr_pac_extension | |
10040 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10041 | Tag_PAC_extension); | |
10042 | ||
10043 | int attr_bti_extension | |
10044 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10045 | Tag_BTI_extension); | |
10046 | ||
10047 | int attr_pacret_use | |
10048 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10049 | Tag_PACRET_use); | |
10050 | ||
10051 | int attr_bti_use | |
10052 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10053 | Tag_BTI_use); | |
10054 | ||
10055 | if (attr_pac_extension != 0 || attr_bti_extension != 0 | |
10056 | || attr_pacret_use != 0 || attr_bti_use != 0) | |
10057 | have_pacbti = true; | |
10058 | } | |
9779414d DJ |
10059 | #endif |
10060 | } | |
10061 | ||
10062 | if (fp_model == ARM_FLOAT_AUTO) | |
10063 | { | |
9779414d DJ |
10064 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
10065 | { | |
10066 | case 0: | |
10067 | /* Leave it as "auto". Strictly speaking this case | |
10068 | means FPA, but almost nobody uses that now, and | |
10069 | many toolchains fail to set the appropriate bits | |
10070 | for the floating-point model they use. */ | |
10071 | break; | |
10072 | case EF_ARM_SOFT_FLOAT: | |
10073 | fp_model = ARM_FLOAT_SOFT_FPA; | |
10074 | break; | |
10075 | case EF_ARM_VFP_FLOAT: | |
10076 | fp_model = ARM_FLOAT_VFP; | |
10077 | break; | |
10078 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
10079 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10080 | break; | |
10081 | } | |
10082 | } | |
10083 | ||
10084 | if (e_flags & EF_ARM_BE8) | |
10085 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
10086 | ||
10087 | break; | |
10088 | ||
10089 | default: | |
10090 | /* Leave it as "auto". */ | |
10091 | break; | |
10092 | } | |
10093 | } | |
123dc839 DJ |
10094 | |
10095 | /* Check any target description for validity. */ | |
9779414d | 10096 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
10097 | { |
10098 | /* For most registers we require GDB's default names; but also allow | |
10099 | the numeric names for sp / lr / pc, as a convenience. */ | |
10100 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
10101 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
10102 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
10103 | ||
10104 | const struct tdesc_feature *feature; | |
58d6951d | 10105 | int valid_p; |
123dc839 | 10106 | |
9779414d | 10107 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10108 | "org.gnu.gdb.arm.core"); |
10109 | if (feature == NULL) | |
9779414d DJ |
10110 | { |
10111 | feature = tdesc_find_feature (tdesc, | |
10112 | "org.gnu.gdb.arm.m-profile"); | |
10113 | if (feature == NULL) | |
10114 | return NULL; | |
10115 | else | |
7559c217 | 10116 | is_m = true; |
9779414d | 10117 | } |
123dc839 DJ |
10118 | |
10119 | tdesc_data = tdesc_data_alloc (); | |
10120 | ||
10121 | valid_p = 1; | |
10122 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 10123 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 10124 | arm_register_names[i]); |
c1e1314d | 10125 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10126 | ARM_SP_REGNUM, |
10127 | arm_sp_names); | |
c1e1314d | 10128 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10129 | ARM_LR_REGNUM, |
10130 | arm_lr_names); | |
c1e1314d | 10131 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10132 | ARM_PC_REGNUM, |
10133 | arm_pc_names); | |
9779414d | 10134 | if (is_m) |
c1e1314d | 10135 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
10136 | ARM_PS_REGNUM, "xpsr"); |
10137 | else | |
c1e1314d | 10138 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 10139 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
10140 | |
10141 | if (!valid_p) | |
c1e1314d | 10142 | return NULL; |
123dc839 | 10143 | |
9074667a CL |
10144 | if (is_m) |
10145 | { | |
10146 | feature = tdesc_find_feature (tdesc, | |
10147 | "org.gnu.gdb.arm.m-system"); | |
10148 | if (feature != nullptr) | |
10149 | { | |
10150 | /* MSP */ | |
10151 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10152 | register_count, "msp"); | |
10153 | if (!valid_p) | |
10154 | { | |
10155 | warning (_("M-profile m-system feature is missing required register msp.")); | |
10156 | return nullptr; | |
10157 | } | |
10158 | have_m_profile_msp = true; | |
10159 | m_profile_msp_regnum = register_count++; | |
10160 | ||
10161 | /* PSP */ | |
10162 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10163 | register_count, "psp"); | |
10164 | if (!valid_p) | |
10165 | { | |
10166 | warning (_("M-profile m-system feature is missing required register psp.")); | |
10167 | return nullptr; | |
10168 | } | |
10169 | m_profile_psp_regnum = register_count++; | |
10170 | } | |
10171 | } | |
10172 | ||
9779414d | 10173 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10174 | "org.gnu.gdb.arm.fpa"); |
10175 | if (feature != NULL) | |
10176 | { | |
10177 | valid_p = 1; | |
10178 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 10179 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
10180 | arm_register_names[i]); |
10181 | if (!valid_p) | |
c1e1314d | 10182 | return NULL; |
123dc839 | 10183 | } |
ff6f572f | 10184 | else |
7559c217 | 10185 | have_fpa_registers = false; |
ff6f572f | 10186 | |
9779414d | 10187 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
10188 | "org.gnu.gdb.xscale.iwmmxt"); |
10189 | if (feature != NULL) | |
10190 | { | |
10191 | static const char *const iwmmxt_names[] = { | |
10192 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
10193 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
10194 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
10195 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
10196 | }; | |
10197 | ||
10198 | valid_p = 1; | |
10199 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
10200 | valid_p | |
c1e1314d | 10201 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10202 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10203 | ||
10204 | /* Check for the control registers, but do not fail if they | |
10205 | are missing. */ | |
10206 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 10207 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10208 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10209 | ||
10210 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
10211 | valid_p | |
c1e1314d | 10212 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10213 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10214 | ||
10215 | if (!valid_p) | |
c1e1314d | 10216 | return NULL; |
a56cc1ce | 10217 | |
7559c217 | 10218 | have_wmmx_registers = true; |
ff6f572f | 10219 | } |
58d6951d DJ |
10220 | |
10221 | /* If we have a VFP unit, check whether the single precision registers | |
10222 | are present. If not, then we will synthesize them as pseudo | |
10223 | registers. */ | |
9779414d | 10224 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10225 | "org.gnu.gdb.arm.vfp"); |
10226 | if (feature != NULL) | |
10227 | { | |
10228 | static const char *const vfp_double_names[] = { | |
10229 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
10230 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
10231 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
10232 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
10233 | }; | |
10234 | ||
10235 | /* Require the double precision registers. There must be either | |
10236 | 16 or 32. */ | |
10237 | valid_p = 1; | |
10238 | for (i = 0; i < 32; i++) | |
10239 | { | |
c1e1314d | 10240 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
10241 | ARM_D0_REGNUM + i, |
10242 | vfp_double_names[i]); | |
10243 | if (!valid_p) | |
10244 | break; | |
10245 | } | |
2b9e5ea6 UW |
10246 | if (!valid_p && i == 16) |
10247 | valid_p = 1; | |
58d6951d | 10248 | |
2b9e5ea6 | 10249 | /* Also require FPSCR. */ |
c1e1314d | 10250 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
10251 | ARM_FPSCR_REGNUM, "fpscr"); |
10252 | if (!valid_p) | |
c1e1314d | 10253 | return NULL; |
58d6951d | 10254 | |
ae66a8f1 SP |
10255 | have_vfp = true; |
10256 | ||
58d6951d | 10257 | if (tdesc_unnumbered_register (feature, "s0") == 0) |
ecbf5d4f | 10258 | have_s_pseudos = true; |
58d6951d | 10259 | |
330c6ca9 | 10260 | vfp_register_count = i; |
58d6951d DJ |
10261 | |
10262 | /* If we have VFP, also check for NEON. The architecture allows | |
10263 | NEON without VFP (integer vector operations only), but GDB | |
10264 | does not support that. */ | |
9779414d | 10265 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10266 | "org.gnu.gdb.arm.neon"); |
10267 | if (feature != NULL) | |
10268 | { | |
10269 | /* NEON requires 32 double-precision registers. */ | |
10270 | if (i != 32) | |
c1e1314d | 10271 | return NULL; |
58d6951d DJ |
10272 | |
10273 | /* If there are quad registers defined by the stub, use | |
10274 | their type; otherwise (normally) provide them with | |
10275 | the default type. */ | |
10276 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
ecbf5d4f | 10277 | have_q_pseudos = true; |
ae66a8f1 SP |
10278 | } |
10279 | } | |
10280 | ||
92d48a1e JB |
10281 | /* Check for the TLS register feature. */ |
10282 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.arm.tls"); | |
10283 | if (feature != nullptr) | |
10284 | { | |
10285 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10286 | register_count, "tpidruro"); | |
10287 | if (!valid_p) | |
10288 | return nullptr; | |
10289 | ||
10290 | tls_regnum = register_count; | |
10291 | register_count++; | |
10292 | } | |
10293 | ||
ae66a8f1 SP |
10294 | /* Check for MVE after all the checks for GPR's, VFP and Neon. |
10295 | MVE (Helium) is an M-profile extension. */ | |
10296 | if (is_m) | |
10297 | { | |
10298 | /* Do we have the MVE feature? */ | |
10299 | feature = tdesc_find_feature (tdesc,"org.gnu.gdb.arm.m-profile-mve"); | |
10300 | ||
10301 | if (feature != nullptr) | |
10302 | { | |
10303 | /* If we have MVE, we must always have the VPR register. */ | |
10304 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10305 | register_count, "vpr"); | |
10306 | if (!valid_p) | |
10307 | { | |
10308 | warning (_("MVE feature is missing required register vpr.")); | |
10309 | return nullptr; | |
10310 | } | |
58d6951d | 10311 | |
ae66a8f1 SP |
10312 | have_mve = true; |
10313 | mve_vpr_regnum = register_count; | |
10314 | register_count++; | |
10315 | ||
10316 | /* We can't have Q pseudo registers available here, as that | |
10317 | would mean we have NEON features, and that is only available | |
10318 | on A and R profiles. */ | |
10319 | gdb_assert (!have_q_pseudos); | |
10320 | ||
10321 | /* Given we have a M-profile target description, if MVE is | |
10322 | enabled and there are VFP registers, we should have Q | |
10323 | pseudo registers (Q0 ~ Q7). */ | |
10324 | if (have_vfp) | |
10325 | have_q_pseudos = true; | |
58d6951d | 10326 | } |
a01567f4 LM |
10327 | |
10328 | /* Do we have the ARMv8.1-m PACBTI feature? */ | |
10329 | feature = tdesc_find_feature (tdesc, | |
10330 | "org.gnu.gdb.arm.m-profile-pacbti"); | |
10331 | if (feature != nullptr) | |
10332 | { | |
10333 | /* By advertising this feature, the target acknowledges the | |
10334 | presence of the ARMv8.1-m PACBTI extensions. | |
10335 | ||
10336 | We don't care for any particular registers in this group, so | |
10337 | the target is free to include whatever it deems appropriate. | |
10338 | ||
10339 | The expectation is for this feature to include the PAC | |
10340 | keys. */ | |
10341 | have_pacbti = true; | |
10342 | } | |
ae7e2f45 CL |
10343 | |
10344 | /* Do we have the Security extension? */ | |
10345 | feature = tdesc_find_feature (tdesc, | |
10346 | "org.gnu.gdb.arm.secext"); | |
10347 | if (feature != nullptr) | |
10348 | { | |
10349 | /* Secure/Non-secure stack pointers. */ | |
10350 | /* MSP_NS */ | |
10351 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10352 | register_count, "msp_ns"); | |
10353 | if (!valid_p) | |
10354 | { | |
10355 | warning (_("M-profile secext feature is missing required register msp_ns.")); | |
10356 | return nullptr; | |
10357 | } | |
10358 | m_profile_msp_ns_regnum = register_count++; | |
10359 | ||
10360 | /* PSP_NS */ | |
10361 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10362 | register_count, "psp_ns"); | |
10363 | if (!valid_p) | |
10364 | { | |
10365 | warning (_("M-profile secext feature is missing required register psp_ns.")); | |
10366 | return nullptr; | |
10367 | } | |
10368 | m_profile_psp_ns_regnum = register_count++; | |
10369 | ||
10370 | /* MSP_S */ | |
10371 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10372 | register_count, "msp_s"); | |
10373 | if (!valid_p) | |
10374 | { | |
10375 | warning (_("M-profile secext feature is missing required register msp_s.")); | |
10376 | return nullptr; | |
10377 | } | |
10378 | m_profile_msp_s_regnum = register_count++; | |
10379 | ||
10380 | /* PSP_S */ | |
10381 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10382 | register_count, "psp_s"); | |
10383 | if (!valid_p) | |
10384 | { | |
10385 | warning (_("M-profile secext feature is missing required register psp_s.")); | |
10386 | return nullptr; | |
10387 | } | |
10388 | m_profile_psp_s_regnum = register_count++; | |
10389 | ||
10390 | have_sec_ext = true; | |
10391 | } | |
10392 | ||
58d6951d | 10393 | } |
123dc839 | 10394 | } |
39bbf761 | 10395 | |
28e97307 DJ |
10396 | /* If there is already a candidate, use it. */ |
10397 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
10398 | best_arch != NULL; | |
10399 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
10400 | { | |
345bd07c | 10401 | arm_gdbarch_tdep *tdep |
08106042 | 10402 | = gdbarch_tdep<arm_gdbarch_tdep> (best_arch->gdbarch); |
345bd07c SM |
10403 | |
10404 | if (arm_abi != ARM_ABI_AUTO && arm_abi != tdep->arm_abi) | |
28e97307 DJ |
10405 | continue; |
10406 | ||
345bd07c | 10407 | if (fp_model != ARM_FLOAT_AUTO && fp_model != tdep->fp_model) |
28e97307 DJ |
10408 | continue; |
10409 | ||
58d6951d DJ |
10410 | /* There are various other properties in tdep that we do not |
10411 | need to check here: those derived from a target description, | |
10412 | since gdbarches with a different target description are | |
10413 | automatically disqualified. */ | |
10414 | ||
9779414d | 10415 | /* Do check is_m, though, since it might come from the binary. */ |
345bd07c | 10416 | if (is_m != tdep->is_m) |
9779414d DJ |
10417 | continue; |
10418 | ||
a01567f4 LM |
10419 | /* Also check for ARMv8.1-m PACBTI support, since it might come from |
10420 | the binary. */ | |
10421 | if (have_pacbti != tdep->have_pacbti) | |
10422 | continue; | |
10423 | ||
28e97307 DJ |
10424 | /* Found a match. */ |
10425 | break; | |
10426 | } | |
97e03143 | 10427 | |
28e97307 | 10428 | if (best_arch != NULL) |
c1e1314d | 10429 | return best_arch->gdbarch; |
28e97307 | 10430 | |
345bd07c | 10431 | arm_gdbarch_tdep *tdep = new arm_gdbarch_tdep; |
97e03143 RE |
10432 | gdbarch = gdbarch_alloc (&info, tdep); |
10433 | ||
28e97307 DJ |
10434 | /* Record additional information about the architecture we are defining. |
10435 | These are gdbarch discriminators, like the OSABI. */ | |
10436 | tdep->arm_abi = arm_abi; | |
10437 | tdep->fp_model = fp_model; | |
9779414d | 10438 | tdep->is_m = is_m; |
ae7e2f45 | 10439 | tdep->have_sec_ext = have_sec_ext; |
ff6f572f | 10440 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 10441 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
10442 | gdb_assert (vfp_register_count == 0 |
10443 | || vfp_register_count == 16 | |
10444 | || vfp_register_count == 32); | |
10445 | tdep->vfp_register_count = vfp_register_count; | |
ecbf5d4f LM |
10446 | tdep->have_s_pseudos = have_s_pseudos; |
10447 | tdep->have_q_pseudos = have_q_pseudos; | |
58d6951d | 10448 | tdep->have_neon = have_neon; |
92d48a1e | 10449 | tdep->tls_regnum = tls_regnum; |
08216dd7 | 10450 | |
ae66a8f1 SP |
10451 | /* Adjust the MVE feature settings. */ |
10452 | if (have_mve) | |
10453 | { | |
10454 | tdep->have_mve = true; | |
10455 | tdep->mve_vpr_regnum = mve_vpr_regnum; | |
10456 | } | |
10457 | ||
a01567f4 LM |
10458 | /* Adjust the PACBTI feature settings. */ |
10459 | tdep->have_pacbti = have_pacbti; | |
10460 | ||
9074667a CL |
10461 | /* Adjust the M-profile stack pointers settings. */ |
10462 | if (have_m_profile_msp) | |
10463 | { | |
10464 | tdep->m_profile_msp_regnum = m_profile_msp_regnum; | |
10465 | tdep->m_profile_psp_regnum = m_profile_psp_regnum; | |
ae7e2f45 CL |
10466 | tdep->m_profile_msp_ns_regnum = m_profile_msp_ns_regnum; |
10467 | tdep->m_profile_psp_ns_regnum = m_profile_psp_ns_regnum; | |
10468 | tdep->m_profile_msp_s_regnum = m_profile_msp_s_regnum; | |
10469 | tdep->m_profile_psp_s_regnum = m_profile_psp_s_regnum; | |
9074667a CL |
10470 | } |
10471 | ||
25f8c692 JL |
10472 | arm_register_g_packet_guesses (gdbarch); |
10473 | ||
08216dd7 | 10474 | /* Breakpoints. */ |
9d4fde75 | 10475 | switch (info.byte_order_for_code) |
67255d04 RE |
10476 | { |
10477 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
10478 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
10479 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
10480 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
10481 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
10482 | ||
67255d04 RE |
10483 | break; |
10484 | ||
10485 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
10486 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
10487 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
10488 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
10489 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
10490 | ||
67255d04 RE |
10491 | break; |
10492 | ||
10493 | default: | |
f34652de | 10494 | internal_error (_("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
10495 | } |
10496 | ||
d7b486e7 RE |
10497 | /* On ARM targets char defaults to unsigned. */ |
10498 | set_gdbarch_char_signed (gdbarch, 0); | |
10499 | ||
53375380 PA |
10500 | /* wchar_t is unsigned under the AAPCS. */ |
10501 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
10502 | set_gdbarch_wchar_signed (gdbarch, 0); | |
10503 | else | |
10504 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 10505 | |
030197b4 AB |
10506 | /* Compute type alignment. */ |
10507 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
10508 | ||
cca44b1b JB |
10509 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
10510 | of additional scratch space. This setting isn't used for anything beside | |
10511 | displaced stepping at present. */ | |
e935475c | 10512 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 10513 | |
9df628e0 | 10514 | /* This should be low enough for everything. */ |
97e03143 | 10515 | tdep->lowest_pc = 0x20; |
94c30b78 | 10516 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 10517 | |
7c00367c MK |
10518 | /* The default, for both APCS and AAPCS, is to return small |
10519 | structures in registers. */ | |
10520 | tdep->struct_return = reg_struct_return; | |
10521 | ||
2dd604e7 | 10522 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 10523 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 10524 | |
7eb89530 YQ |
10525 | if (is_m) |
10526 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
10527 | ||
756fe439 DJ |
10528 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
10529 | ||
eb5492fa | 10530 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 10531 | |
34e8f22d | 10532 | /* Address manipulation. */ |
34e8f22d RE |
10533 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
10534 | ||
34e8f22d RE |
10535 | /* Advance PC across function entry code. */ |
10536 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
10537 | ||
c9cf6e20 MG |
10538 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
10539 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 10540 | |
190dce09 UW |
10541 | /* Skip trampolines. */ |
10542 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
10543 | ||
34e8f22d RE |
10544 | /* The stack grows downward. */ |
10545 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
10546 | ||
10547 | /* Breakpoint manipulation. */ | |
04180708 YQ |
10548 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
10549 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
10550 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
10551 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
10552 | |
10553 | /* Information about registers, etc. */ | |
34e8f22d RE |
10554 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
10555 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ecbf5d4f | 10556 | set_gdbarch_num_regs (gdbarch, register_count); |
7a5ea0d4 | 10557 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 10558 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 10559 | |
ff6f572f DJ |
10560 | /* This "info float" is FPA-specific. Use the generic version if we |
10561 | do not have FPA. */ | |
345bd07c | 10562 | if (tdep->have_fpa_registers) |
ff6f572f DJ |
10563 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
10564 | ||
26216b98 | 10565 | /* Internal <-> external register number maps. */ |
ff6f572f | 10566 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
10567 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
10568 | ||
34e8f22d RE |
10569 | set_gdbarch_register_name (gdbarch, arm_register_name); |
10570 | ||
10571 | /* Returning results. */ | |
2af48f68 | 10572 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 10573 | |
03d48a7d RE |
10574 | /* Disassembly. */ |
10575 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
10576 | ||
34e8f22d RE |
10577 | /* Minsymbol frobbing. */ |
10578 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
10579 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
10580 | arm_coff_make_msymbol_special); | |
60c5725c | 10581 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 10582 | |
f9d67f43 DJ |
10583 | /* Thumb-2 IT block support. */ |
10584 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
10585 | arm_adjust_breakpoint_address); | |
10586 | ||
0d5de010 DJ |
10587 | /* Virtual tables. */ |
10588 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
10589 | ||
97e03143 | 10590 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 10591 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 10592 | |
b39cc962 DJ |
10593 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
10594 | ||
eb5492fa | 10595 | /* Add some default predicates. */ |
2ae28aa9 YQ |
10596 | if (is_m) |
10597 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
10598 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
10599 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 10600 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 10601 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 10602 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 10603 | |
97e03143 RE |
10604 | /* Now we have tuned the configuration, set a few final things, |
10605 | based on what the OS ABI has told us. */ | |
10606 | ||
b8926edc DJ |
10607 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
10608 | binaries are always marked. */ | |
10609 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
10610 | tdep->arm_abi = ARM_ABI_APCS; | |
10611 | ||
e3039479 UW |
10612 | /* Watchpoints are not steppable. */ |
10613 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
10614 | ||
b8926edc DJ |
10615 | /* We used to default to FPA for generic ARM, but almost nobody |
10616 | uses that now, and we now provide a way for the user to force | |
10617 | the model. So default to the most useful variant. */ | |
10618 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
10619 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
10620 | ||
9df628e0 RE |
10621 | if (tdep->jb_pc >= 0) |
10622 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
10623 | ||
08216dd7 | 10624 | /* Floating point sizes and format. */ |
8da61cc4 | 10625 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 10626 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 10627 | { |
8da61cc4 DJ |
10628 | set_gdbarch_double_format |
10629 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10630 | set_gdbarch_long_double_format | |
10631 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10632 | } | |
10633 | else | |
10634 | { | |
10635 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
10636 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
10637 | } |
10638 | ||
a01567f4 LM |
10639 | /* Hook used to decorate frames with signed return addresses, only available |
10640 | for ARMv8.1-m PACBTI. */ | |
10641 | if (is_m && have_pacbti) | |
10642 | set_gdbarch_get_pc_address_flags (gdbarch, arm_get_pc_address_flags); | |
10643 | ||
dc22c61a LM |
10644 | if (tdesc_data != nullptr) |
10645 | { | |
10646 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
10647 | ||
10648 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
ecbf5d4f | 10649 | register_count = gdbarch_num_regs (gdbarch); |
dc22c61a LM |
10650 | |
10651 | /* Override tdesc_register_type to adjust the types of VFP | |
10652 | registers for NEON. */ | |
10653 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
10654 | } | |
10655 | ||
ecbf5d4f | 10656 | /* Initialize the pseudo register data. */ |
ae66a8f1 | 10657 | int num_pseudos = 0; |
ecbf5d4f | 10658 | if (tdep->have_s_pseudos) |
58d6951d | 10659 | { |
ecbf5d4f LM |
10660 | /* VFP single precision pseudo registers (S0~S31). */ |
10661 | tdep->s_pseudo_base = register_count; | |
10662 | tdep->s_pseudo_count = 32; | |
ae66a8f1 | 10663 | num_pseudos += tdep->s_pseudo_count; |
ecbf5d4f LM |
10664 | |
10665 | if (tdep->have_q_pseudos) | |
10666 | { | |
10667 | /* NEON quad precision pseudo registers (Q0~Q15). */ | |
10668 | tdep->q_pseudo_base = register_count + num_pseudos; | |
ae66a8f1 SP |
10669 | |
10670 | if (have_neon) | |
10671 | tdep->q_pseudo_count = 16; | |
10672 | else if (have_mve) | |
10673 | tdep->q_pseudo_count = ARM_MVE_NUM_Q_REGS; | |
10674 | ||
ecbf5d4f LM |
10675 | num_pseudos += tdep->q_pseudo_count; |
10676 | } | |
ae66a8f1 SP |
10677 | } |
10678 | ||
10679 | /* Do we have any MVE pseudo registers? */ | |
10680 | if (have_mve) | |
10681 | { | |
10682 | tdep->mve_pseudo_base = register_count + num_pseudos; | |
10683 | tdep->mve_pseudo_count = 1; | |
10684 | num_pseudos += tdep->mve_pseudo_count; | |
10685 | } | |
58d6951d | 10686 | |
a01567f4 LM |
10687 | /* Do we have any ARMv8.1-m PACBTI pseudo registers. */ |
10688 | if (have_pacbti) | |
10689 | { | |
10690 | tdep->pacbti_pseudo_base = register_count + num_pseudos; | |
10691 | tdep->pacbti_pseudo_count = 1; | |
10692 | num_pseudos += tdep->pacbti_pseudo_count; | |
10693 | } | |
10694 | ||
ae66a8f1 | 10695 | /* Set some pseudo register hooks, if we have pseudo registers. */ |
a01567f4 | 10696 | if (tdep->have_s_pseudos || have_mve || have_pacbti) |
ae66a8f1 | 10697 | { |
58d6951d DJ |
10698 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); |
10699 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
10700 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
10701 | } | |
10702 | ||
123dc839 | 10703 | /* Add standard register aliases. We add aliases even for those |
85102364 | 10704 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
10705 | and does no harm, since nothing ever lists user registers. */ |
10706 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
10707 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
10708 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
10709 | ||
65b48a81 PB |
10710 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
10711 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
10712 | ||
3426ae57 AH |
10713 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
10714 | ||
39bbf761 RE |
10715 | return gdbarch; |
10716 | } | |
10717 | ||
97e03143 | 10718 | static void |
2af46ca0 | 10719 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 10720 | { |
08106042 | 10721 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
97e03143 RE |
10722 | |
10723 | if (tdep == NULL) | |
10724 | return; | |
10725 | ||
6cb06a8c TT |
10726 | gdb_printf (file, _("arm_dump_tdep: fp_model = %i\n"), |
10727 | (int) tdep->fp_model); | |
10728 | gdb_printf (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
10729 | (int) tdep->have_fpa_registers); | |
10730 | gdb_printf (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
10731 | (int) tdep->have_wmmx_registers); | |
10732 | gdb_printf (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
10733 | (int) tdep->vfp_register_count); | |
10734 | gdb_printf (file, _("arm_dump_tdep: have_s_pseudos = %s\n"), | |
10735 | tdep->have_s_pseudos? "true" : "false"); | |
10736 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_base = %i\n"), | |
10737 | (int) tdep->s_pseudo_base); | |
10738 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_count = %i\n"), | |
10739 | (int) tdep->s_pseudo_count); | |
10740 | gdb_printf (file, _("arm_dump_tdep: have_q_pseudos = %s\n"), | |
10741 | tdep->have_q_pseudos? "true" : "false"); | |
10742 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_base = %i\n"), | |
10743 | (int) tdep->q_pseudo_base); | |
10744 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_count = %i\n"), | |
10745 | (int) tdep->q_pseudo_count); | |
10746 | gdb_printf (file, _("arm_dump_tdep: have_neon = %i\n"), | |
10747 | (int) tdep->have_neon); | |
10748 | gdb_printf (file, _("arm_dump_tdep: have_mve = %s\n"), | |
10749 | tdep->have_mve? "yes" : "no"); | |
10750 | gdb_printf (file, _("arm_dump_tdep: mve_vpr_regnum = %i\n"), | |
10751 | tdep->mve_vpr_regnum); | |
10752 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_base = %i\n"), | |
10753 | tdep->mve_pseudo_base); | |
10754 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_count = %i\n"), | |
10755 | tdep->mve_pseudo_count); | |
9074667a CL |
10756 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_regnum = %i\n"), |
10757 | tdep->m_profile_msp_regnum); | |
10758 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_regnum = %i\n"), | |
10759 | tdep->m_profile_psp_regnum); | |
ae7e2f45 CL |
10760 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"), |
10761 | tdep->m_profile_msp_ns_regnum); | |
10762 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"), | |
10763 | tdep->m_profile_psp_ns_regnum); | |
10764 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_s_regnum = %i\n"), | |
10765 | tdep->m_profile_msp_s_regnum); | |
10766 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_s_regnum = %i\n"), | |
10767 | tdep->m_profile_psp_s_regnum); | |
6cb06a8c TT |
10768 | gdb_printf (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), |
10769 | (unsigned long) tdep->lowest_pc); | |
a01567f4 LM |
10770 | gdb_printf (file, _("arm_dump_tdep: have_pacbti = %s\n"), |
10771 | tdep->have_pacbti? "yes" : "no"); | |
10772 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_base = %i\n"), | |
10773 | tdep->pacbti_pseudo_base); | |
10774 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_count = %i\n"), | |
10775 | tdep->pacbti_pseudo_count); | |
10776 | gdb_printf (file, _("arm_dump_tdep: is_m = %s\n"), | |
10777 | tdep->is_m? "yes" : "no"); | |
97e03143 RE |
10778 | } |
10779 | ||
0d4c07af | 10780 | #if GDB_SELF_TEST |
b121eeb9 YQ |
10781 | namespace selftests |
10782 | { | |
10783 | static void arm_record_test (void); | |
9ecab40c | 10784 | static void arm_analyze_prologue_test (); |
b121eeb9 | 10785 | } |
0d4c07af | 10786 | #endif |
b121eeb9 | 10787 | |
6c265988 | 10788 | void _initialize_arm_tdep (); |
c906108c | 10789 | void |
6c265988 | 10790 | _initialize_arm_tdep () |
c906108c | 10791 | { |
bc90b915 | 10792 | long length; |
65b48a81 | 10793 | int i, j; |
edefbb7c AC |
10794 | char regdesc[1024], *rdptr = regdesc; |
10795 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 10796 | |
42cf1509 | 10797 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 10798 | |
0e9e9abd | 10799 | /* Add ourselves to objfile event chain. */ |
c90e7d63 | 10800 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile, "arm-tdep"); |
0e9e9abd | 10801 | |
70f80edf JT |
10802 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
10803 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
10804 | bfd_target_elf_flavour, | |
10805 | arm_elf_osabi_sniffer); | |
10806 | ||
afd7eef0 | 10807 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
f54bdb6d SM |
10808 | add_setshow_prefix_cmd ("arm", no_class, |
10809 | _("Various ARM-specific commands."), | |
10810 | _("Various ARM-specific commands."), | |
10811 | &setarmcmdlist, &showarmcmdlist, | |
10812 | &setlist, &showlist); | |
c5aa993b | 10813 | |
65b48a81 | 10814 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
10815 | const disasm_options_t *disasm_options |
10816 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
10817 | int num_disassembly_styles = 0; |
10818 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10819 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10820 | num_disassembly_styles++; |
10821 | ||
10822 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 10823 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
10824 | num_disassembly_styles + 1); |
10825 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10826 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10827 | { |
10828 | size_t offset = strlen ("reg-names-"); | |
10829 | const char *style = disasm_options->name[i]; | |
10830 | valid_disassembly_styles[j++] = &style[offset]; | |
dedb7102 TT |
10831 | if (strcmp (&style[offset], "std") == 0) |
10832 | disassembly_style = &style[offset]; | |
65b48a81 PB |
10833 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], |
10834 | disasm_options->description[i]); | |
10835 | rdptr += length; | |
10836 | rest -= length; | |
10837 | } | |
94c30b78 | 10838 | /* Mark the end of valid options. */ |
65b48a81 | 10839 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 10840 | |
edefbb7c | 10841 | /* Create the help text. */ |
d7e74731 PA |
10842 | std::string helptext = string_printf ("%s%s%s", |
10843 | _("The valid values are:\n"), | |
10844 | regdesc, | |
10845 | _("The default is \"std\".")); | |
ed9a39eb | 10846 | |
edefbb7c AC |
10847 | add_setshow_enum_cmd("disassembler", no_class, |
10848 | valid_disassembly_styles, &disassembly_style, | |
10849 | _("Set the disassembly style."), | |
10850 | _("Show the disassembly style."), | |
09b0e4b0 | 10851 | helptext.c_str (), |
2c5b56ce | 10852 | set_disassembly_style_sfunc, |
65b48a81 | 10853 | show_disassembly_style_sfunc, |
7376b4c2 | 10854 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
10855 | |
10856 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
10857 | _("Set usage of ARM 32-bit mode."), | |
10858 | _("Show usage of ARM 32-bit mode."), | |
10859 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 10860 | NULL, |
0963b4bd MS |
10861 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
10862 | mode is %s. */ | |
26304000 | 10863 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 10864 | |
fd50bc42 | 10865 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
10866 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
10867 | _("Set the floating point type."), | |
10868 | _("Show the floating point type."), | |
10869 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
10870 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
10871 | fpa - FPA co-processor (GCC compiled).\n\ | |
10872 | softvfp - Software FP with pure-endian doubles.\n\ | |
10873 | vfp - VFP co-processor."), | |
edefbb7c | 10874 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 10875 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 10876 | |
28e97307 DJ |
10877 | /* Add a command to allow the user to force the ABI. */ |
10878 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
10879 | _("Set the ABI."), | |
10880 | _("Show the ABI."), | |
10881 | NULL, arm_set_abi, arm_show_abi, | |
10882 | &setarmcmdlist, &showarmcmdlist); | |
10883 | ||
0428b8f5 DJ |
10884 | /* Add two commands to allow the user to force the assumed |
10885 | execution mode. */ | |
10886 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
10887 | arm_mode_strings, &arm_fallback_mode_string, | |
10888 | _("Set the mode assumed when symbols are unavailable."), | |
10889 | _("Show the mode assumed when symbols are unavailable."), | |
10890 | NULL, NULL, arm_show_fallback_mode, | |
10891 | &setarmcmdlist, &showarmcmdlist); | |
10892 | add_setshow_enum_cmd ("force-mode", class_support, | |
10893 | arm_mode_strings, &arm_force_mode_string, | |
10894 | _("Set the mode assumed even when symbols are available."), | |
10895 | _("Show the mode assumed even when symbols are available."), | |
10896 | NULL, NULL, arm_show_force_mode, | |
10897 | &setarmcmdlist, &showarmcmdlist); | |
10898 | ||
ef273377 CL |
10899 | /* Add a command to stop triggering security exceptions when |
10900 | unwinding exception stacks. */ | |
10901 | add_setshow_boolean_cmd ("unwind-secure-frames", no_class, &arm_unwind_secure_frames, | |
10902 | _("Set usage of non-secure to secure exception stack unwinding."), | |
10903 | _("Show usage of non-secure to secure exception stack unwinding."), | |
10904 | _("When on, the debugger can trigger memory access traps."), | |
10905 | NULL, arm_show_unwind_secure_frames, | |
10906 | &setarmcmdlist, &showarmcmdlist); | |
10907 | ||
6529d2dd | 10908 | /* Debugging flag. */ |
edefbb7c AC |
10909 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
10910 | _("Set ARM debugging."), | |
10911 | _("Show ARM debugging."), | |
10912 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 10913 | NULL, |
7915a72c | 10914 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 10915 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
10916 | |
10917 | #if GDB_SELF_TEST | |
1526853e | 10918 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 10919 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
10920 | #endif |
10921 | ||
c906108c | 10922 | } |
72508ac0 PO |
10923 | |
10924 | /* ARM-reversible process record data structures. */ | |
10925 | ||
10926 | #define ARM_INSN_SIZE_BYTES 4 | |
10927 | #define THUMB_INSN_SIZE_BYTES 2 | |
10928 | #define THUMB2_INSN_SIZE_BYTES 4 | |
10929 | ||
10930 | ||
71e396f9 LM |
10931 | /* Position of the bit within a 32-bit ARM instruction |
10932 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
10933 | #define INSN_S_L_BIT_NUM 20 |
10934 | ||
10935 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10936 | do \ |
10937 | { \ | |
10938 | unsigned int reg_len = LENGTH; \ | |
10939 | if (reg_len) \ | |
10940 | { \ | |
10941 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
10942 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
10943 | } \ | |
10944 | } \ | |
10945 | while (0) | |
72508ac0 PO |
10946 | |
10947 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10948 | do \ |
10949 | { \ | |
10950 | unsigned int mem_len = LENGTH; \ | |
10951 | if (mem_len) \ | |
01add95b SM |
10952 | { \ |
10953 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
10954 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
10955 | sizeof(struct arm_mem_r) * LENGTH); \ | |
10956 | } \ | |
dda83cd7 SM |
10957 | } \ |
10958 | while (0) | |
72508ac0 PO |
10959 | |
10960 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
10961 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 10962 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
10963 | |
10964 | /* ARM memory record structure. */ | |
10965 | struct arm_mem_r | |
10966 | { | |
10967 | uint32_t len; /* Record length. */ | |
bfbbec00 | 10968 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
10969 | }; |
10970 | ||
10971 | /* ARM instruction record contains opcode of current insn | |
10972 | and execution state (before entry to decode_insn()), | |
10973 | contains list of to-be-modified registers and | |
10974 | memory blocks (on return from decode_insn()). */ | |
10975 | ||
4748a9be | 10976 | struct arm_insn_decode_record |
72508ac0 PO |
10977 | { |
10978 | struct gdbarch *gdbarch; | |
10979 | struct regcache *regcache; | |
10980 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
10981 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
10982 | uint32_t cond; /* Condition code. */ | |
10983 | uint32_t opcode; /* Insn opcode. */ | |
10984 | uint32_t decode; /* Insn decode bits. */ | |
10985 | uint32_t mem_rec_count; /* No of mem records. */ | |
10986 | uint32_t reg_rec_count; /* No of reg records. */ | |
10987 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
10988 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
4748a9be | 10989 | }; |
72508ac0 PO |
10990 | |
10991 | ||
10992 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
10993 | ||
10994 | static int | |
10995 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
10996 | { | |
10997 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
10998 | ||
10999 | if (!len) | |
11000 | return 1; | |
11001 | ||
11002 | if (!sbo) | |
11003 | ones = ~ones; | |
11004 | ||
11005 | while (ones) | |
11006 | { | |
11007 | if (!(ones & sbo)) | |
dda83cd7 SM |
11008 | { |
11009 | return 0; | |
11010 | } | |
72508ac0 PO |
11011 | ones = ones >> 1; |
11012 | } | |
11013 | return 1; | |
11014 | } | |
11015 | ||
c6ec2b30 OJ |
11016 | enum arm_record_result |
11017 | { | |
11018 | ARM_RECORD_SUCCESS = 0, | |
11019 | ARM_RECORD_FAILURE = 1 | |
11020 | }; | |
11021 | ||
0d1703b8 | 11022 | enum arm_record_strx_t |
72508ac0 PO |
11023 | { |
11024 | ARM_RECORD_STRH=1, | |
11025 | ARM_RECORD_STRD | |
0d1703b8 | 11026 | }; |
72508ac0 | 11027 | |
0d1703b8 | 11028 | enum record_type_t |
72508ac0 PO |
11029 | { |
11030 | ARM_RECORD=1, | |
11031 | THUMB_RECORD, | |
11032 | THUMB2_RECORD | |
0d1703b8 | 11033 | }; |
72508ac0 PO |
11034 | |
11035 | ||
11036 | static int | |
4748a9be | 11037 | arm_record_strx (arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, |
dda83cd7 | 11038 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
11039 | { |
11040 | ||
11041 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11042 | ULONGEST u_regval[2]= {0}; | |
11043 | ||
11044 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
11045 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
11046 | |
11047 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11048 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
11049 | |
11050 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11051 | { | |
11052 | /* 1) Handle misc store, immediate offset. */ | |
11053 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
11054 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
11055 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11056 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 11057 | &u_regval[0]); |
72508ac0 | 11058 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
11059 | { |
11060 | /* If R15 was used as Rn, hence current PC+8. */ | |
11061 | u_regval[0] = u_regval[0] + 8; | |
11062 | } | |
72508ac0 PO |
11063 | offset_8 = (immed_high << 4) | immed_low; |
11064 | /* Calculate target store address. */ | |
11065 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
11066 | { |
11067 | tgt_mem_addr = u_regval[0] + offset_8; | |
11068 | } | |
72508ac0 | 11069 | else |
dda83cd7 SM |
11070 | { |
11071 | tgt_mem_addr = u_regval[0] - offset_8; | |
11072 | } | |
72508ac0 | 11073 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11074 | { |
11075 | record_buf_mem[0] = 2; | |
11076 | record_buf_mem[1] = tgt_mem_addr; | |
11077 | arm_insn_r->mem_rec_count = 1; | |
11078 | } | |
72508ac0 | 11079 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11080 | { |
11081 | record_buf_mem[0] = 4; | |
11082 | record_buf_mem[1] = tgt_mem_addr; | |
11083 | record_buf_mem[2] = 4; | |
11084 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11085 | arm_insn_r->mem_rec_count = 2; | |
11086 | } | |
72508ac0 PO |
11087 | } |
11088 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
11089 | { | |
11090 | /* 2) Store, register offset. */ | |
11091 | /* Get Rm. */ | |
11092 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11093 | /* Get Rn. */ | |
11094 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11095 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11096 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11097 | if (15 == reg_src2) | |
dda83cd7 SM |
11098 | { |
11099 | /* If R15 was used as Rn, hence current PC+8. */ | |
11100 | u_regval[0] = u_regval[0] + 8; | |
11101 | } | |
72508ac0 PO |
11102 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
11103 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
11104 | { |
11105 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11106 | } | |
72508ac0 | 11107 | else |
dda83cd7 SM |
11108 | { |
11109 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11110 | } | |
72508ac0 | 11111 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11112 | { |
11113 | record_buf_mem[0] = 2; | |
11114 | record_buf_mem[1] = tgt_mem_addr; | |
11115 | arm_insn_r->mem_rec_count = 1; | |
11116 | } | |
72508ac0 | 11117 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11118 | { |
11119 | record_buf_mem[0] = 4; | |
11120 | record_buf_mem[1] = tgt_mem_addr; | |
11121 | record_buf_mem[2] = 4; | |
11122 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11123 | arm_insn_r->mem_rec_count = 2; | |
11124 | } | |
72508ac0 PO |
11125 | } |
11126 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 11127 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
11128 | { |
11129 | /* 3) Store, immediate pre-indexed. */ | |
11130 | /* 5) Store, immediate post-indexed. */ | |
11131 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
11132 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
11133 | offset_8 = (immed_high << 4) | immed_low; | |
11134 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11135 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11136 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11137 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
11138 | { |
11139 | tgt_mem_addr = u_regval[0] + offset_8; | |
11140 | } | |
72508ac0 | 11141 | else |
dda83cd7 SM |
11142 | { |
11143 | tgt_mem_addr = u_regval[0] - offset_8; | |
11144 | } | |
72508ac0 | 11145 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11146 | { |
11147 | record_buf_mem[0] = 2; | |
11148 | record_buf_mem[1] = tgt_mem_addr; | |
11149 | arm_insn_r->mem_rec_count = 1; | |
11150 | } | |
72508ac0 | 11151 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11152 | { |
11153 | record_buf_mem[0] = 4; | |
11154 | record_buf_mem[1] = tgt_mem_addr; | |
11155 | record_buf_mem[2] = 4; | |
11156 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11157 | arm_insn_r->mem_rec_count = 2; | |
11158 | } | |
72508ac0 PO |
11159 | /* Record Rn also as it changes. */ |
11160 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11161 | arm_insn_r->reg_rec_count = 1; | |
11162 | } | |
11163 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 11164 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
11165 | { |
11166 | /* 4) Store, register pre-indexed. */ | |
11167 | /* 6) Store, register post -indexed. */ | |
11168 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11169 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11170 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11171 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11172 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11173 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
11174 | { |
11175 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11176 | } | |
72508ac0 | 11177 | else |
dda83cd7 SM |
11178 | { |
11179 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11180 | } | |
72508ac0 | 11181 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11182 | { |
11183 | record_buf_mem[0] = 2; | |
11184 | record_buf_mem[1] = tgt_mem_addr; | |
11185 | arm_insn_r->mem_rec_count = 1; | |
11186 | } | |
72508ac0 | 11187 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11188 | { |
11189 | record_buf_mem[0] = 4; | |
11190 | record_buf_mem[1] = tgt_mem_addr; | |
11191 | record_buf_mem[2] = 4; | |
11192 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11193 | arm_insn_r->mem_rec_count = 2; | |
11194 | } | |
72508ac0 PO |
11195 | /* Record Rn also as it changes. */ |
11196 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11197 | arm_insn_r->reg_rec_count = 1; | |
11198 | } | |
11199 | return 0; | |
11200 | } | |
11201 | ||
11202 | /* Handling ARM extension space insns. */ | |
11203 | ||
11204 | static int | |
4748a9be | 11205 | arm_record_extension_space (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 11206 | { |
df95a9cf | 11207 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
11208 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
11209 | uint32_t record_buf[8], record_buf_mem[8]; | |
11210 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
11211 | struct regcache *reg_cache = arm_insn_r->regcache; |
11212 | ULONGEST u_regval = 0; | |
11213 | ||
11214 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
11215 | /* Handle unconditional insn extension space. */ | |
11216 | ||
11217 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
11218 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11219 | if (arm_insn_r->cond) | |
11220 | { | |
11221 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 11222 | the caches. */ |
72508ac0 | 11223 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
11224 | { |
11225 | /* BLX(1) */ | |
11226 | record_buf[0] = ARM_PS_REGNUM; | |
11227 | record_buf[1] = ARM_LR_REGNUM; | |
11228 | arm_insn_r->reg_rec_count = 2; | |
11229 | } | |
72508ac0 PO |
11230 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
11231 | } | |
11232 | ||
11233 | ||
11234 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11235 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
11236 | { | |
11237 | ret = -1; | |
11238 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 11239 | versions define it. */ |
72508ac0 PO |
11240 | } |
11241 | ||
11242 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
11243 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11244 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11245 | ||
11246 | /* Handle arithmetic insn extension space. */ | |
11247 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
11248 | && !INSN_RECORDED(arm_insn_r)) | |
11249 | { | |
11250 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 11251 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
01add95b SM |
11252 | { |
11253 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11254 | record_buf[1] = ARM_PS_REGNUM; | |
11255 | arm_insn_r->reg_rec_count = 2; | |
11256 | } | |
b020ff80 | 11257 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
01add95b SM |
11258 | { |
11259 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
11260 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11261 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11262 | record_buf[2] = ARM_PS_REGNUM; | |
11263 | arm_insn_r->reg_rec_count = 3; | |
11264 | } | |
72508ac0 PO |
11265 | } |
11266 | ||
11267 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
11268 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
11269 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
11270 | ||
11271 | /* Handle control insn extension space. */ | |
11272 | ||
11273 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
11274 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
11275 | { | |
11276 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
11277 | { |
11278 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
11279 | { | |
11280 | if ((0 == insn_op1) || (2 == insn_op1)) | |
11281 | { | |
11282 | /* MRS. */ | |
11283 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11284 | arm_insn_r->reg_rec_count = 1; | |
11285 | } | |
11286 | else if (1 == insn_op1) | |
11287 | { | |
11288 | /* CSPR is going to be changed. */ | |
11289 | record_buf[0] = ARM_PS_REGNUM; | |
11290 | arm_insn_r->reg_rec_count = 1; | |
11291 | } | |
11292 | else if (3 == insn_op1) | |
11293 | { | |
11294 | /* SPSR is going to be changed. */ | |
11295 | /* We need to get SPSR value, which is yet to be done. */ | |
11296 | return -1; | |
11297 | } | |
11298 | } | |
11299 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11300 | { | |
11301 | if (1 == insn_op1) | |
11302 | { | |
11303 | /* BX. */ | |
11304 | record_buf[0] = ARM_PS_REGNUM; | |
11305 | arm_insn_r->reg_rec_count = 1; | |
11306 | } | |
11307 | else if (3 == insn_op1) | |
11308 | { | |
11309 | /* CLZ. */ | |
11310 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11311 | arm_insn_r->reg_rec_count = 1; | |
11312 | } | |
11313 | } | |
11314 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11315 | { | |
11316 | /* BLX. */ | |
11317 | record_buf[0] = ARM_PS_REGNUM; | |
11318 | record_buf[1] = ARM_LR_REGNUM; | |
11319 | arm_insn_r->reg_rec_count = 2; | |
11320 | } | |
11321 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11322 | { | |
11323 | /* QADD, QSUB, QDADD, QDSUB */ | |
11324 | record_buf[0] = ARM_PS_REGNUM; | |
11325 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11326 | arm_insn_r->reg_rec_count = 2; | |
11327 | } | |
11328 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11329 | { | |
11330 | /* BKPT. */ | |
11331 | record_buf[0] = ARM_PS_REGNUM; | |
11332 | record_buf[1] = ARM_LR_REGNUM; | |
11333 | arm_insn_r->reg_rec_count = 2; | |
11334 | ||
11335 | /* Save SPSR also;how? */ | |
11336 | return -1; | |
11337 | } | |
11338 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
11339 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
11340 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
11341 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
11342 | ) | |
11343 | { | |
11344 | if (0 == insn_op1 || 1 == insn_op1) | |
11345 | { | |
11346 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
11347 | /* We dont do optimization for SMULW<y> where we | |
11348 | need only Rd. */ | |
11349 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11350 | record_buf[1] = ARM_PS_REGNUM; | |
11351 | arm_insn_r->reg_rec_count = 2; | |
11352 | } | |
11353 | else if (2 == insn_op1) | |
11354 | { | |
11355 | /* SMLAL<x><y>. */ | |
11356 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11357 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11358 | arm_insn_r->reg_rec_count = 2; | |
11359 | } | |
11360 | else if (3 == insn_op1) | |
11361 | { | |
11362 | /* SMUL<x><y>. */ | |
11363 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11364 | arm_insn_r->reg_rec_count = 1; | |
11365 | } | |
11366 | } | |
11367 | } | |
72508ac0 | 11368 | else |
dda83cd7 SM |
11369 | { |
11370 | /* MSR : immediate form. */ | |
11371 | if (1 == insn_op1) | |
11372 | { | |
11373 | /* CSPR is going to be changed. */ | |
11374 | record_buf[0] = ARM_PS_REGNUM; | |
11375 | arm_insn_r->reg_rec_count = 1; | |
11376 | } | |
11377 | else if (3 == insn_op1) | |
11378 | { | |
11379 | /* SPSR is going to be changed. */ | |
11380 | /* we need to get SPSR value, which is yet to be done */ | |
11381 | return -1; | |
11382 | } | |
11383 | } | |
72508ac0 PO |
11384 | } |
11385 | ||
11386 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11387 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
11388 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
11389 | ||
11390 | /* Handle load/store insn extension space. */ | |
11391 | ||
11392 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
11393 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
11394 | && !INSN_RECORDED(arm_insn_r)) | |
11395 | { | |
11396 | /* SWP/SWPB. */ | |
11397 | if (0 == insn_op1) | |
dda83cd7 SM |
11398 | { |
11399 | /* These insn, changes register and memory as well. */ | |
11400 | /* SWP or SWPB insn. */ | |
11401 | /* Get memory address given by Rn. */ | |
11402 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11403 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11404 | /* SWP insn ?, swaps word. */ | |
11405 | if (8 == arm_insn_r->opcode) | |
11406 | { | |
11407 | record_buf_mem[0] = 4; | |
11408 | } | |
11409 | else | |
11410 | { | |
11411 | /* SWPB insn, swaps only byte. */ | |
11412 | record_buf_mem[0] = 1; | |
11413 | } | |
11414 | record_buf_mem[1] = u_regval; | |
11415 | arm_insn_r->mem_rec_count = 1; | |
11416 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11417 | arm_insn_r->reg_rec_count = 1; | |
11418 | } | |
72508ac0 | 11419 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11420 | { |
11421 | /* STRH. */ | |
11422 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11423 | ARM_RECORD_STRH); | |
11424 | } | |
72508ac0 | 11425 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11426 | { |
11427 | /* LDRD. */ | |
11428 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11429 | record_buf[1] = record_buf[0] + 1; | |
11430 | arm_insn_r->reg_rec_count = 2; | |
11431 | } | |
72508ac0 | 11432 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11433 | { |
11434 | /* STRD. */ | |
11435 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11436 | ARM_RECORD_STRD); | |
11437 | } | |
72508ac0 | 11438 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
11439 | { |
11440 | /* LDRH, LDRSB, LDRSH. */ | |
11441 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11442 | arm_insn_r->reg_rec_count = 1; | |
11443 | } | |
72508ac0 PO |
11444 | |
11445 | } | |
11446 | ||
11447 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
11448 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
11449 | && !INSN_RECORDED(arm_insn_r)) | |
11450 | { | |
11451 | ret = -1; | |
11452 | /* Handle coprocessor insn extension space. */ | |
11453 | } | |
11454 | ||
11455 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
11456 | if (-1 == ret) | |
ca92db2d | 11457 | return ret; |
72508ac0 PO |
11458 | |
11459 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11460 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11461 | ||
11462 | return ret; | |
11463 | } | |
11464 | ||
11465 | /* Handling opcode 000 insns. */ | |
11466 | ||
11467 | static int | |
4748a9be | 11468 | arm_record_data_proc_misc_ld_str (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11469 | { |
11470 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11471 | uint32_t record_buf[8], record_buf_mem[8]; | |
11472 | ULONGEST u_regval[2] = {0}; | |
11473 | ||
8d49165d | 11474 | uint32_t reg_src1 = 0; |
72508ac0 PO |
11475 | uint32_t opcode1 = 0; |
11476 | ||
11477 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11478 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11479 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
11480 | ||
2d9e6acb | 11481 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11482 | { |
2d9e6acb YQ |
11483 | /* Data-processing (register) and Data-processing (register-shifted |
11484 | register */ | |
11485 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
11486 | register, which is specified by 13-16 decode. */ | |
11487 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11488 | record_buf[1] = ARM_PS_REGNUM; | |
11489 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 11490 | } |
2d9e6acb | 11491 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11492 | { |
2d9e6acb YQ |
11493 | /* Miscellaneous instructions */ |
11494 | ||
11495 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
11496 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11497 | { | |
11498 | /* Handle BLX, branch and link/exchange. */ | |
11499 | if (9 == arm_insn_r->opcode) | |
11500 | { | |
11501 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
11502 | and R14 stores the return address. */ | |
11503 | record_buf[0] = ARM_PS_REGNUM; | |
11504 | record_buf[1] = ARM_LR_REGNUM; | |
11505 | arm_insn_r->reg_rec_count = 2; | |
11506 | } | |
11507 | } | |
11508 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
11509 | { | |
11510 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
11511 | /* CPSR is changed to be executed in ARM state, disabling normal | |
11512 | interrupts, entering abort mode. */ | |
11513 | /* According to high vector configuration PC is set. */ | |
11514 | /* user hit breakpoint and type reverse, in | |
11515 | that case, we need to go back with previous CPSR and | |
11516 | Program Counter. */ | |
11517 | record_buf[0] = ARM_PS_REGNUM; | |
11518 | record_buf[1] = ARM_LR_REGNUM; | |
11519 | arm_insn_r->reg_rec_count = 2; | |
11520 | ||
11521 | /* Save SPSR also; how? */ | |
11522 | return -1; | |
11523 | } | |
11524 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
11525 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11526 | { | |
11527 | /* Handle BX, branch and link/exchange. */ | |
11528 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
11529 | record_buf[0] = ARM_PS_REGNUM; | |
11530 | arm_insn_r->reg_rec_count = 1; | |
11531 | } | |
11532 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
11533 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
11534 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
11535 | { | |
11536 | /* Count leading zeros: CLZ. */ | |
11537 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11538 | arm_insn_r->reg_rec_count = 1; | |
11539 | } | |
11540 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
11541 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11542 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
11543 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
11544 | { | |
11545 | /* Handle MRS insn. */ | |
11546 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11547 | arm_insn_r->reg_rec_count = 1; | |
11548 | } | |
72508ac0 | 11549 | } |
2d9e6acb | 11550 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 11551 | { |
2d9e6acb YQ |
11552 | /* Multiply and multiply-accumulate */ |
11553 | ||
11554 | /* Handle multiply instructions. */ | |
11555 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
11556 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
f2a883a8 SM |
11557 | { |
11558 | /* Handle MLA and MUL. */ | |
11559 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11560 | record_buf[1] = ARM_PS_REGNUM; | |
11561 | arm_insn_r->reg_rec_count = 2; | |
11562 | } | |
11563 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
11564 | { | |
11565 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
11566 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11567 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11568 | record_buf[2] = ARM_PS_REGNUM; | |
11569 | arm_insn_r->reg_rec_count = 3; | |
11570 | } | |
2d9e6acb YQ |
11571 | } |
11572 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
11573 | { | |
11574 | /* Synchronization primitives */ | |
11575 | ||
72508ac0 PO |
11576 | /* Handling SWP, SWPB. */ |
11577 | /* These insn, changes register and memory as well. */ | |
11578 | /* SWP or SWPB insn. */ | |
11579 | ||
11580 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11581 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11582 | /* SWP insn ?, swaps word. */ | |
11583 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
11584 | { |
11585 | record_buf_mem[0] = 4; | |
11586 | } | |
11587 | else | |
11588 | { | |
11589 | /* SWPB insn, swaps only byte. */ | |
11590 | record_buf_mem[0] = 1; | |
11591 | } | |
72508ac0 PO |
11592 | record_buf_mem[1] = u_regval[0]; |
11593 | arm_insn_r->mem_rec_count = 1; | |
11594 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11595 | arm_insn_r->reg_rec_count = 1; | |
11596 | } | |
2d9e6acb YQ |
11597 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
11598 | || 15 == arm_insn_r->decode) | |
72508ac0 | 11599 | { |
2d9e6acb YQ |
11600 | if ((opcode1 & 0x12) == 2) |
11601 | { | |
11602 | /* Extra load/store (unprivileged) */ | |
11603 | return -1; | |
11604 | } | |
11605 | else | |
11606 | { | |
11607 | /* Extra load/store */ | |
11608 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
11609 | { | |
11610 | case 1: | |
11611 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
11612 | { | |
11613 | /* STRH (register), STRH (immediate) */ | |
11614 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11615 | &record_buf_mem[0], ARM_RECORD_STRH); | |
11616 | } | |
11617 | else if ((opcode1 & 0x05) == 0x1) | |
11618 | { | |
11619 | /* LDRH (register) */ | |
11620 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11621 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 11622 | |
2d9e6acb YQ |
11623 | if (bit (arm_insn_r->arm_insn, 21)) |
11624 | { | |
11625 | /* Write back to Rn. */ | |
11626 | record_buf[arm_insn_r->reg_rec_count++] | |
11627 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11628 | } | |
11629 | } | |
11630 | else if ((opcode1 & 0x05) == 0x5) | |
11631 | { | |
11632 | /* LDRH (immediate), LDRH (literal) */ | |
11633 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11634 | |
2d9e6acb YQ |
11635 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11636 | arm_insn_r->reg_rec_count = 1; | |
11637 | ||
11638 | if (rn != 15) | |
11639 | { | |
11640 | /*LDRH (immediate) */ | |
11641 | if (bit (arm_insn_r->arm_insn, 21)) | |
11642 | { | |
11643 | /* Write back to Rn. */ | |
11644 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11645 | } | |
11646 | } | |
11647 | } | |
11648 | else | |
11649 | return -1; | |
11650 | break; | |
11651 | case 2: | |
11652 | if ((opcode1 & 0x05) == 0x0) | |
11653 | { | |
11654 | /* LDRD (register) */ | |
11655 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11656 | record_buf[1] = record_buf[0] + 1; | |
11657 | arm_insn_r->reg_rec_count = 2; | |
11658 | ||
11659 | if (bit (arm_insn_r->arm_insn, 21)) | |
11660 | { | |
11661 | /* Write back to Rn. */ | |
11662 | record_buf[arm_insn_r->reg_rec_count++] | |
11663 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11664 | } | |
11665 | } | |
11666 | else if ((opcode1 & 0x05) == 0x1) | |
11667 | { | |
11668 | /* LDRSB (register) */ | |
11669 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11670 | arm_insn_r->reg_rec_count = 1; | |
11671 | ||
11672 | if (bit (arm_insn_r->arm_insn, 21)) | |
11673 | { | |
11674 | /* Write back to Rn. */ | |
11675 | record_buf[arm_insn_r->reg_rec_count++] | |
11676 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11677 | } | |
11678 | } | |
11679 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
11680 | { | |
11681 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
11682 | LDRSB (literal) */ | |
11683 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11684 | ||
11685 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11686 | arm_insn_r->reg_rec_count = 1; | |
11687 | ||
11688 | if (rn != 15) | |
11689 | { | |
11690 | /*LDRD (immediate), LDRSB (immediate) */ | |
11691 | if (bit (arm_insn_r->arm_insn, 21)) | |
11692 | { | |
11693 | /* Write back to Rn. */ | |
11694 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11695 | } | |
11696 | } | |
11697 | } | |
11698 | else | |
11699 | return -1; | |
11700 | break; | |
11701 | case 3: | |
11702 | if ((opcode1 & 0x05) == 0x0) | |
11703 | { | |
11704 | /* STRD (register) */ | |
11705 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11706 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11707 | } | |
11708 | else if ((opcode1 & 0x05) == 0x1) | |
11709 | { | |
11710 | /* LDRSH (register) */ | |
11711 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11712 | arm_insn_r->reg_rec_count = 1; | |
11713 | ||
11714 | if (bit (arm_insn_r->arm_insn, 21)) | |
11715 | { | |
11716 | /* Write back to Rn. */ | |
11717 | record_buf[arm_insn_r->reg_rec_count++] | |
11718 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11719 | } | |
11720 | } | |
11721 | else if ((opcode1 & 0x05) == 0x4) | |
11722 | { | |
11723 | /* STRD (immediate) */ | |
11724 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11725 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11726 | } | |
11727 | else if ((opcode1 & 0x05) == 0x5) | |
11728 | { | |
11729 | /* LDRSH (immediate), LDRSH (literal) */ | |
11730 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11731 | arm_insn_r->reg_rec_count = 1; | |
11732 | ||
11733 | if (bit (arm_insn_r->arm_insn, 21)) | |
11734 | { | |
11735 | /* Write back to Rn. */ | |
11736 | record_buf[arm_insn_r->reg_rec_count++] | |
11737 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11738 | } | |
11739 | } | |
11740 | else | |
11741 | return -1; | |
11742 | break; | |
11743 | default: | |
11744 | return -1; | |
11745 | } | |
11746 | } | |
72508ac0 PO |
11747 | } |
11748 | else | |
11749 | { | |
11750 | return -1; | |
11751 | } | |
11752 | ||
11753 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11754 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11755 | return 0; | |
11756 | } | |
11757 | ||
11758 | /* Handling opcode 001 insns. */ | |
11759 | ||
11760 | static int | |
4748a9be | 11761 | arm_record_data_proc_imm (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11762 | { |
11763 | uint32_t record_buf[8], record_buf_mem[8]; | |
11764 | ||
11765 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11766 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11767 | ||
11768 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
11769 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
11770 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
11771 | ) | |
11772 | { | |
11773 | /* Handle MSR insn. */ | |
11774 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
11775 | { |
11776 | /* CSPR is going to be changed. */ | |
11777 | record_buf[0] = ARM_PS_REGNUM; | |
11778 | arm_insn_r->reg_rec_count = 1; | |
11779 | } | |
72508ac0 | 11780 | else |
dda83cd7 SM |
11781 | { |
11782 | /* SPSR is going to be changed. */ | |
11783 | } | |
72508ac0 PO |
11784 | } |
11785 | else if (arm_insn_r->opcode <= 15) | |
11786 | { | |
11787 | /* Normal data processing insns. */ | |
11788 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 11789 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
11790 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11791 | record_buf[1] = ARM_PS_REGNUM; | |
11792 | arm_insn_r->reg_rec_count = 2; | |
11793 | } | |
11794 | else | |
11795 | { | |
11796 | return -1; | |
11797 | } | |
11798 | ||
11799 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11800 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11801 | return 0; | |
11802 | } | |
11803 | ||
c55978a6 | 11804 | static int |
4748a9be | 11805 | arm_record_media (arm_insn_decode_record *arm_insn_r) |
c55978a6 YQ |
11806 | { |
11807 | uint32_t record_buf[8]; | |
11808 | ||
11809 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
11810 | { | |
11811 | case 0: | |
11812 | /* Parallel addition and subtraction, signed */ | |
11813 | case 1: | |
11814 | /* Parallel addition and subtraction, unsigned */ | |
11815 | case 2: | |
11816 | case 3: | |
11817 | /* Packing, unpacking, saturation and reversal */ | |
11818 | { | |
11819 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
11820 | ||
11821 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11822 | } | |
11823 | break; | |
11824 | ||
11825 | case 4: | |
11826 | case 5: | |
11827 | /* Signed multiplies */ | |
11828 | { | |
11829 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
11830 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
11831 | ||
11832 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11833 | if (op1 == 0x0) | |
11834 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11835 | else if (op1 == 0x4) | |
11836 | record_buf[arm_insn_r->reg_rec_count++] | |
11837 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11838 | } | |
11839 | break; | |
11840 | ||
11841 | case 6: | |
11842 | { | |
11843 | if (bit (arm_insn_r->arm_insn, 21) | |
11844 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
11845 | { | |
11846 | /* SBFX */ | |
11847 | record_buf[arm_insn_r->reg_rec_count++] | |
11848 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11849 | } | |
11850 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
11851 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
11852 | { | |
11853 | /* USAD8 and USADA8 */ | |
11854 | record_buf[arm_insn_r->reg_rec_count++] | |
11855 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11856 | } | |
11857 | } | |
11858 | break; | |
11859 | ||
11860 | case 7: | |
11861 | { | |
11862 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
11863 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
11864 | { | |
11865 | /* Permanently UNDEFINED */ | |
11866 | return -1; | |
11867 | } | |
11868 | else | |
11869 | { | |
11870 | /* BFC, BFI and UBFX */ | |
11871 | record_buf[arm_insn_r->reg_rec_count++] | |
11872 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11873 | } | |
11874 | } | |
11875 | break; | |
11876 | ||
11877 | default: | |
11878 | return -1; | |
11879 | } | |
11880 | ||
11881 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11882 | ||
11883 | return 0; | |
11884 | } | |
11885 | ||
71e396f9 | 11886 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
11887 | |
11888 | static int | |
4748a9be | 11889 | arm_record_ld_st_imm_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11890 | { |
11891 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11892 | ||
71e396f9 LM |
11893 | uint32_t reg_base , reg_dest; |
11894 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 11895 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
11896 | unsigned char wback; |
11897 | ULONGEST u_regval; | |
72508ac0 | 11898 | |
71e396f9 LM |
11899 | /* Calculate wback. */ |
11900 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
11901 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 11902 | |
71e396f9 LM |
11903 | arm_insn_r->reg_rec_count = 0; |
11904 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
11905 | |
11906 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11907 | { | |
71e396f9 LM |
11908 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
11909 | and LDRT. */ | |
11910 | ||
72508ac0 | 11911 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
11912 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
11913 | ||
11914 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
11915 | preceeds a LDR instruction having R15 as reg_base, it | |
11916 | emulates a branch and link instruction, and hence we need to save | |
11917 | CPSR and PC as well. */ | |
11918 | if (ARM_PC_REGNUM == reg_dest) | |
11919 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11920 | ||
11921 | /* If wback is true, also save the base register, which is going to be | |
11922 | written to. */ | |
11923 | if (wback) | |
11924 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11925 | } |
11926 | else | |
11927 | { | |
71e396f9 LM |
11928 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
11929 | ||
72508ac0 | 11930 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
11931 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
11932 | ||
11933 | /* Handle bit U. */ | |
72508ac0 | 11934 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
11935 | { |
11936 | /* U == 1: Add the offset. */ | |
11937 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
11938 | } | |
72508ac0 | 11939 | else |
71e396f9 LM |
11940 | { |
11941 | /* U == 0: subtract the offset. */ | |
11942 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
11943 | } | |
11944 | ||
11945 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
11946 | bytes. */ | |
11947 | if (bit (arm_insn_r->arm_insn, 22)) | |
11948 | { | |
11949 | /* STRB and STRBT: 1 byte. */ | |
11950 | record_buf_mem[0] = 1; | |
11951 | } | |
11952 | else | |
11953 | { | |
11954 | /* STR and STRT: 4 bytes. */ | |
11955 | record_buf_mem[0] = 4; | |
11956 | } | |
11957 | ||
11958 | /* Handle bit P. */ | |
11959 | if (bit (arm_insn_r->arm_insn, 24)) | |
11960 | record_buf_mem[1] = tgt_mem_addr; | |
11961 | else | |
11962 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 11963 | |
72508ac0 PO |
11964 | arm_insn_r->mem_rec_count = 1; |
11965 | ||
71e396f9 LM |
11966 | /* If wback is true, also save the base register, which is going to be |
11967 | written to. */ | |
11968 | if (wback) | |
11969 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11970 | } |
11971 | ||
11972 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11973 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11974 | return 0; | |
11975 | } | |
11976 | ||
11977 | /* Handling opcode 011 insns. */ | |
11978 | ||
11979 | static int | |
4748a9be | 11980 | arm_record_ld_st_reg_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11981 | { |
11982 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11983 | ||
11984 | uint32_t shift_imm = 0; | |
11985 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
11986 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
11987 | uint32_t record_buf[8], record_buf_mem[8]; | |
11988 | ||
11989 | LONGEST s_word; | |
11990 | ULONGEST u_regval[2]; | |
11991 | ||
c55978a6 YQ |
11992 | if (bit (arm_insn_r->arm_insn, 4)) |
11993 | return arm_record_media (arm_insn_r); | |
11994 | ||
72508ac0 PO |
11995 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
11996 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11997 | ||
11998 | /* Handle enhanced store insns and LDRD DSP insn, | |
11999 | order begins according to addressing modes for store insns | |
12000 | STRH insn. */ | |
12001 | ||
12002 | /* LDR or STR? */ | |
12003 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12004 | { | |
12005 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
12006 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
12007 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
12008 | in that case, it emulates branch and link insn, and hence we | |
12009 | need to save CSPR and PC as well. */ | |
72508ac0 | 12010 | if (15 != reg_dest) |
dda83cd7 SM |
12011 | { |
12012 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12013 | arm_insn_r->reg_rec_count = 1; | |
12014 | } | |
72508ac0 | 12015 | else |
dda83cd7 SM |
12016 | { |
12017 | record_buf[0] = reg_dest; | |
12018 | record_buf[1] = ARM_PS_REGNUM; | |
12019 | arm_insn_r->reg_rec_count = 2; | |
12020 | } | |
72508ac0 PO |
12021 | } |
12022 | else | |
12023 | { | |
12024 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
12025 | { |
12026 | /* Store insn, register offset and register pre-indexed, | |
12027 | register post-indexed. */ | |
12028 | /* Get Rm. */ | |
12029 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
12030 | /* Get Rn. */ | |
12031 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12032 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
12033 | , &u_regval[0]); | |
12034 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
12035 | , &u_regval[1]); | |
12036 | if (15 == reg_src2) | |
12037 | { | |
12038 | /* If R15 was used as Rn, hence current PC+8. */ | |
12039 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
12040 | u_regval[0] = u_regval[0] + 8; | |
12041 | } | |
12042 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
12043 | /* U == 1. */ | |
12044 | if (bit (arm_insn_r->arm_insn, 23)) | |
12045 | { | |
12046 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
12047 | } | |
12048 | else | |
12049 | { | |
12050 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
12051 | } | |
12052 | ||
12053 | switch (arm_insn_r->opcode) | |
12054 | { | |
12055 | /* STR. */ | |
12056 | case 8: | |
12057 | case 12: | |
12058 | /* STR. */ | |
12059 | case 9: | |
12060 | case 13: | |
12061 | /* STRT. */ | |
12062 | case 1: | |
12063 | case 5: | |
12064 | /* STR. */ | |
12065 | case 0: | |
12066 | case 4: | |
12067 | record_buf_mem[0] = 4; | |
12068 | break; | |
12069 | ||
12070 | /* STRB. */ | |
12071 | case 10: | |
12072 | case 14: | |
12073 | /* STRB. */ | |
12074 | case 11: | |
12075 | case 15: | |
12076 | /* STRBT. */ | |
12077 | case 3: | |
12078 | case 7: | |
12079 | /* STRB. */ | |
12080 | case 2: | |
12081 | case 6: | |
12082 | record_buf_mem[0] = 1; | |
12083 | break; | |
12084 | ||
12085 | default: | |
12086 | gdb_assert_not_reached ("no decoding pattern found"); | |
12087 | break; | |
12088 | } | |
12089 | record_buf_mem[1] = tgt_mem_addr; | |
12090 | arm_insn_r->mem_rec_count = 1; | |
12091 | ||
12092 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
12093 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
12094 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
12095 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
12096 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
12097 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
12098 | ) | |
12099 | { | |
12100 | /* Rn is going to be changed in pre-indexed mode and | |
12101 | post-indexed mode as well. */ | |
12102 | record_buf[0] = reg_src2; | |
12103 | arm_insn_r->reg_rec_count = 1; | |
12104 | } | |
12105 | } | |
72508ac0 | 12106 | else |
dda83cd7 SM |
12107 | { |
12108 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
12109 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
12110 | /* Get Rm. */ | |
12111 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
12112 | /* Get Rn. */ | |
12113 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12114 | /* Get shift_imm. */ | |
12115 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
12116 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
12117 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
12118 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12119 | /* Offset_12 used as shift. */ | |
12120 | switch (offset_12) | |
12121 | { | |
12122 | case 0: | |
12123 | /* Offset_12 used as index. */ | |
12124 | offset_12 = u_regval[0] << shift_imm; | |
12125 | break; | |
12126 | ||
12127 | case 1: | |
12128 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
12129 | break; | |
12130 | ||
12131 | case 2: | |
12132 | if (!shift_imm) | |
12133 | { | |
12134 | if (bit (u_regval[0], 31)) | |
12135 | { | |
12136 | offset_12 = 0xFFFFFFFF; | |
12137 | } | |
12138 | else | |
12139 | { | |
12140 | offset_12 = 0; | |
12141 | } | |
12142 | } | |
12143 | else | |
12144 | { | |
12145 | /* This is arithmetic shift. */ | |
12146 | offset_12 = s_word >> shift_imm; | |
12147 | } | |
12148 | break; | |
12149 | ||
12150 | case 3: | |
12151 | if (!shift_imm) | |
12152 | { | |
12153 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
12154 | &u_regval[1]); | |
12155 | /* Get C flag value and shift it by 31. */ | |
12156 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
12157 | | (u_regval[0]) >> 1); | |
12158 | } | |
12159 | else | |
12160 | { | |
12161 | offset_12 = (u_regval[0] >> shift_imm) \ | |
12162 | | (u_regval[0] << | |
12163 | (sizeof(uint32_t) - shift_imm)); | |
12164 | } | |
12165 | break; | |
12166 | ||
12167 | default: | |
12168 | gdb_assert_not_reached ("no decoding pattern found"); | |
12169 | break; | |
12170 | } | |
12171 | ||
12172 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12173 | /* bit U set. */ | |
12174 | if (bit (arm_insn_r->arm_insn, 23)) | |
12175 | { | |
12176 | tgt_mem_addr = u_regval[1] + offset_12; | |
12177 | } | |
12178 | else | |
12179 | { | |
12180 | tgt_mem_addr = u_regval[1] - offset_12; | |
12181 | } | |
12182 | ||
12183 | switch (arm_insn_r->opcode) | |
12184 | { | |
12185 | /* STR. */ | |
12186 | case 8: | |
12187 | case 12: | |
12188 | /* STR. */ | |
12189 | case 9: | |
12190 | case 13: | |
12191 | /* STRT. */ | |
12192 | case 1: | |
12193 | case 5: | |
12194 | /* STR. */ | |
12195 | case 0: | |
12196 | case 4: | |
12197 | record_buf_mem[0] = 4; | |
12198 | break; | |
12199 | ||
12200 | /* STRB. */ | |
12201 | case 10: | |
12202 | case 14: | |
12203 | /* STRB. */ | |
12204 | case 11: | |
12205 | case 15: | |
12206 | /* STRBT. */ | |
12207 | case 3: | |
12208 | case 7: | |
12209 | /* STRB. */ | |
12210 | case 2: | |
12211 | case 6: | |
12212 | record_buf_mem[0] = 1; | |
12213 | break; | |
12214 | ||
12215 | default: | |
12216 | gdb_assert_not_reached ("no decoding pattern found"); | |
12217 | break; | |
12218 | } | |
12219 | record_buf_mem[1] = tgt_mem_addr; | |
12220 | arm_insn_r->mem_rec_count = 1; | |
12221 | ||
12222 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
12223 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
12224 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
12225 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
12226 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
12227 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
12228 | ) | |
12229 | { | |
12230 | /* Rn is going to be changed in register scaled pre-indexed | |
12231 | mode,and scaled post indexed mode. */ | |
12232 | record_buf[0] = reg_src2; | |
12233 | arm_insn_r->reg_rec_count = 1; | |
12234 | } | |
12235 | } | |
72508ac0 PO |
12236 | } |
12237 | ||
12238 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12239 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12240 | return 0; | |
12241 | } | |
12242 | ||
71e396f9 | 12243 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
12244 | |
12245 | static int | |
4748a9be | 12246 | arm_record_ld_st_multiple (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12247 | { |
12248 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
12249 | uint32_t register_count = 0, register_bits; |
12250 | uint32_t reg_base, addr_mode; | |
72508ac0 | 12251 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
12252 | uint32_t wback; |
12253 | ULONGEST u_regval; | |
72508ac0 | 12254 | |
71e396f9 LM |
12255 | /* Fetch the list of registers. */ |
12256 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
12257 | arm_insn_r->reg_rec_count = 0; | |
12258 | ||
12259 | /* Fetch the base register that contains the address we are loading data | |
12260 | to. */ | |
12261 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 12262 | |
71e396f9 LM |
12263 | /* Calculate wback. */ |
12264 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
12265 | |
12266 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12267 | { | |
71e396f9 | 12268 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 12269 | |
71e396f9 | 12270 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 12271 | while (register_bits) |
71e396f9 LM |
12272 | { |
12273 | if (register_bits & 0x00000001) | |
12274 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
12275 | register_bits = register_bits >> 1; | |
12276 | register_count++; | |
12277 | } | |
72508ac0 | 12278 | |
71e396f9 LM |
12279 | |
12280 | /* If wback is true, also save the base register, which is going to be | |
12281 | written to. */ | |
12282 | if (wback) | |
12283 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
12284 | ||
12285 | /* Save the CPSR register. */ | |
12286 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
12287 | } |
12288 | else | |
12289 | { | |
71e396f9 | 12290 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 12291 | |
71e396f9 LM |
12292 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
12293 | ||
12294 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
12295 | ||
12296 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 12297 | while (register_bits) |
71e396f9 LM |
12298 | { |
12299 | if (register_bits & 0x00000001) | |
12300 | register_count++; | |
12301 | register_bits = register_bits >> 1; | |
12302 | } | |
72508ac0 PO |
12303 | |
12304 | switch (addr_mode) | |
71e396f9 LM |
12305 | { |
12306 | /* STMDA (STMED): Decrement after. */ | |
12307 | case 0: | |
12308 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12309 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
12310 | break; |
12311 | /* STM (STMIA, STMEA): Increment after. */ | |
12312 | case 1: | |
12313 | record_buf_mem[1] = (uint32_t) u_regval; | |
12314 | break; | |
12315 | /* STMDB (STMFD): Decrement before. */ | |
12316 | case 2: | |
12317 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12318 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12319 | break; |
12320 | /* STMIB (STMFA): Increment before. */ | |
12321 | case 3: | |
f0452268 | 12322 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12323 | break; |
12324 | default: | |
12325 | gdb_assert_not_reached ("no decoding pattern found"); | |
12326 | break; | |
12327 | } | |
72508ac0 | 12328 | |
f0452268 | 12329 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12330 | arm_insn_r->mem_rec_count = 1; |
12331 | ||
12332 | /* If wback is true, also save the base register, which is going to be | |
12333 | written to. */ | |
12334 | if (wback) | |
12335 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
12336 | } |
12337 | ||
12338 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12339 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12340 | return 0; | |
12341 | } | |
12342 | ||
12343 | /* Handling opcode 101 insns. */ | |
12344 | ||
12345 | static int | |
4748a9be | 12346 | arm_record_b_bl (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12347 | { |
12348 | uint32_t record_buf[8]; | |
12349 | ||
12350 | /* Handle B, BL, BLX(1) insns. */ | |
12351 | /* B simply branches so we do nothing here. */ | |
12352 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
12353 | extension space. */ | |
12354 | if (bit (arm_insn_r->arm_insn, 24)) | |
01add95b SM |
12355 | { |
12356 | record_buf[0] = ARM_LR_REGNUM; | |
12357 | arm_insn_r->reg_rec_count = 1; | |
12358 | } | |
72508ac0 PO |
12359 | |
12360 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12361 | ||
12362 | return 0; | |
12363 | } | |
12364 | ||
72508ac0 | 12365 | static int |
4748a9be | 12366 | arm_record_unsupported_insn (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 12367 | { |
6cb06a8c TT |
12368 | gdb_printf (gdb_stderr, |
12369 | _("Process record does not support instruction " | |
12370 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
12371 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
12372 | |
12373 | return -1; | |
12374 | } | |
12375 | ||
5a578da5 OJ |
12376 | /* Record handler for vector data transfer instructions. */ |
12377 | ||
12378 | static int | |
4748a9be | 12379 | arm_record_vdata_transfer_insn (arm_insn_decode_record *arm_insn_r) |
5a578da5 OJ |
12380 | { |
12381 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
12382 | uint32_t record_buf[4]; | |
12383 | ||
5a578da5 OJ |
12384 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
12385 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
12386 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
12387 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
12388 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
12389 | ||
12390 | /* Handle VMOV instruction. */ | |
12391 | if (bit_l && bit_c) | |
12392 | { | |
12393 | record_buf[0] = reg_t; | |
12394 | arm_insn_r->reg_rec_count = 1; | |
12395 | } | |
12396 | else if (bit_l && !bit_c) | |
12397 | { | |
12398 | /* Handle VMOV instruction. */ | |
12399 | if (bits_a == 0x00) | |
dda83cd7 | 12400 | { |
f1771dce | 12401 | record_buf[0] = reg_t; |
dda83cd7 SM |
12402 | arm_insn_r->reg_rec_count = 1; |
12403 | } | |
5a578da5 OJ |
12404 | /* Handle VMRS instruction. */ |
12405 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12406 | { |
12407 | if (reg_t == 15) | |
12408 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 12409 | |
dda83cd7 SM |
12410 | record_buf[0] = reg_t; |
12411 | arm_insn_r->reg_rec_count = 1; | |
12412 | } | |
5a578da5 OJ |
12413 | } |
12414 | else if (!bit_l && !bit_c) | |
12415 | { | |
12416 | /* Handle VMOV instruction. */ | |
12417 | if (bits_a == 0x00) | |
dda83cd7 | 12418 | { |
f1771dce | 12419 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 12420 | |
dda83cd7 SM |
12421 | arm_insn_r->reg_rec_count = 1; |
12422 | } | |
5a578da5 OJ |
12423 | /* Handle VMSR instruction. */ |
12424 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12425 | { |
12426 | record_buf[0] = ARM_FPSCR_REGNUM; | |
12427 | arm_insn_r->reg_rec_count = 1; | |
12428 | } | |
5a578da5 OJ |
12429 | } |
12430 | else if (!bit_l && bit_c) | |
12431 | { | |
12432 | /* Handle VMOV instruction. */ | |
12433 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
12434 | { |
12435 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
12436 | + ARM_D0_REGNUM; | |
12437 | arm_insn_r->reg_rec_count = 1; | |
12438 | } | |
5a578da5 OJ |
12439 | /* Handle VDUP instruction. */ |
12440 | else | |
dda83cd7 SM |
12441 | { |
12442 | if (bit (arm_insn_r->arm_insn, 21)) | |
12443 | { | |
12444 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12445 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12446 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
12447 | arm_insn_r->reg_rec_count = 2; | |
12448 | } | |
12449 | else | |
12450 | { | |
12451 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12452 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12453 | arm_insn_r->reg_rec_count = 1; | |
12454 | } | |
12455 | } | |
12456 | } | |
12457 | ||
12458 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12459 | return 0; | |
12460 | } | |
12461 | ||
f20f80dd OJ |
12462 | /* Record handler for extension register load/store instructions. */ |
12463 | ||
12464 | static int | |
4748a9be | 12465 | arm_record_exreg_ld_st_insn (arm_insn_decode_record *arm_insn_r) |
f20f80dd OJ |
12466 | { |
12467 | uint32_t opcode, single_reg; | |
12468 | uint8_t op_vldm_vstm; | |
12469 | uint32_t record_buf[8], record_buf_mem[128]; | |
12470 | ULONGEST u_regval = 0; | |
12471 | ||
12472 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
12473 | |
12474 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 12475 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
12476 | op_vldm_vstm = opcode & 0x1b; |
12477 | ||
12478 | /* Handle VMOV instructions. */ | |
12479 | if ((opcode & 0x1e) == 0x04) | |
12480 | { | |
9fde51ed | 12481 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
12482 | { |
12483 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12484 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12485 | arm_insn_r->reg_rec_count = 2; | |
12486 | } | |
f20f80dd | 12487 | else |
01e57735 | 12488 | { |
9fde51ed YQ |
12489 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
12490 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 12491 | |
9fde51ed | 12492 | if (single_reg) |
01e57735 | 12493 | { |
9fde51ed YQ |
12494 | /* The first S register number m is REG_M:M (M is bit 5), |
12495 | the corresponding D register number is REG_M:M / 2, which | |
12496 | is REG_M. */ | |
12497 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
12498 | /* The second S register number is REG_M:M + 1, the | |
12499 | corresponding D register number is (REG_M:M + 1) / 2. | |
12500 | IOW, if bit M is 1, the first and second S registers | |
12501 | are mapped to different D registers, otherwise, they are | |
12502 | in the same D register. */ | |
12503 | if (bit_m) | |
12504 | { | |
12505 | record_buf[arm_insn_r->reg_rec_count++] | |
12506 | = ARM_D0_REGNUM + reg_m + 1; | |
12507 | } | |
01e57735 YQ |
12508 | } |
12509 | else | |
12510 | { | |
9fde51ed | 12511 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
12512 | arm_insn_r->reg_rec_count = 1; |
12513 | } | |
12514 | } | |
f20f80dd OJ |
12515 | } |
12516 | /* Handle VSTM and VPUSH instructions. */ | |
12517 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 12518 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
12519 | { |
12520 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
12521 | uint32_t memory_index = 0; | |
12522 | ||
12523 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12524 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12525 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12526 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12527 | memory_count = imm_off8; |
12528 | ||
12529 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12530 | start_address = u_regval; |
f20f80dd | 12531 | else |
01e57735 | 12532 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12533 | |
12534 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
12535 | { |
12536 | record_buf[0] = reg_rn; | |
12537 | arm_insn_r->reg_rec_count = 1; | |
12538 | } | |
f20f80dd OJ |
12539 | |
12540 | while (memory_count > 0) | |
01e57735 | 12541 | { |
9fde51ed | 12542 | if (single_reg) |
01e57735 | 12543 | { |
9fde51ed YQ |
12544 | record_buf_mem[memory_index] = 4; |
12545 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12546 | start_address = start_address + 4; |
12547 | memory_index = memory_index + 2; | |
12548 | } | |
12549 | else | |
12550 | { | |
9fde51ed YQ |
12551 | record_buf_mem[memory_index] = 4; |
12552 | record_buf_mem[memory_index + 1] = start_address; | |
12553 | record_buf_mem[memory_index + 2] = 4; | |
12554 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12555 | start_address = start_address + 8; |
12556 | memory_index = memory_index + 4; | |
12557 | } | |
12558 | memory_count--; | |
12559 | } | |
f20f80dd OJ |
12560 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
12561 | } | |
12562 | /* Handle VLDM instructions. */ | |
12563 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 12564 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
12565 | { |
12566 | uint32_t reg_count, reg_vd; | |
12567 | uint32_t reg_index = 0; | |
9fde51ed | 12568 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
12569 | |
12570 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12571 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
12572 | ||
9fde51ed YQ |
12573 | /* REG_VD is the first D register number. If the instruction |
12574 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
12575 | number is (REG_VD << 1 | bit D), so the corresponding D | |
12576 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
12577 | if (!single_reg) | |
12578 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 12579 | |
9fde51ed | 12580 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 12581 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 12582 | |
9fde51ed YQ |
12583 | /* If the instruction loads memory to D register, REG_COUNT should |
12584 | be divided by 2, according to the ARM Architecture Reference | |
12585 | Manual. If the instruction loads memory to S register, divide by | |
12586 | 2 as well because two S registers are mapped to D register. */ | |
12587 | reg_count = reg_count / 2; | |
12588 | if (single_reg && bit_d) | |
01e57735 | 12589 | { |
9fde51ed YQ |
12590 | /* Increase the register count if S register list starts from |
12591 | an odd number (bit d is one). */ | |
12592 | reg_count++; | |
12593 | } | |
f20f80dd | 12594 | |
9fde51ed YQ |
12595 | while (reg_count > 0) |
12596 | { | |
12597 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
12598 | reg_count--; |
12599 | } | |
f20f80dd OJ |
12600 | arm_insn_r->reg_rec_count = reg_index; |
12601 | } | |
12602 | /* VSTR Vector store register. */ | |
12603 | else if ((opcode & 0x13) == 0x10) | |
12604 | { | |
bec2ab5a | 12605 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
12606 | uint32_t memory_index = 0; |
12607 | ||
12608 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12609 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12610 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12611 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12612 | |
12613 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12614 | start_address = u_regval + imm_off32; |
f20f80dd | 12615 | else |
01e57735 | 12616 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12617 | |
12618 | if (single_reg) | |
01e57735 | 12619 | { |
9fde51ed YQ |
12620 | record_buf_mem[memory_index] = 4; |
12621 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12622 | arm_insn_r->mem_rec_count = 1; |
12623 | } | |
f20f80dd | 12624 | else |
01e57735 | 12625 | { |
9fde51ed YQ |
12626 | record_buf_mem[memory_index] = 4; |
12627 | record_buf_mem[memory_index + 1] = start_address; | |
12628 | record_buf_mem[memory_index + 2] = 4; | |
12629 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12630 | arm_insn_r->mem_rec_count = 2; |
12631 | } | |
f20f80dd OJ |
12632 | } |
12633 | /* VLDR Vector load register. */ | |
12634 | else if ((opcode & 0x13) == 0x11) | |
12635 | { | |
12636 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12637 | ||
12638 | if (!single_reg) | |
01e57735 YQ |
12639 | { |
12640 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
12641 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
12642 | } | |
f20f80dd | 12643 | else |
01e57735 YQ |
12644 | { |
12645 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
12646 | /* Record register D rather than pseudo register S. */ |
12647 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 12648 | } |
f20f80dd OJ |
12649 | arm_insn_r->reg_rec_count = 1; |
12650 | } | |
12651 | ||
12652 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12653 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12654 | return 0; | |
12655 | } | |
12656 | ||
851f26ae OJ |
12657 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
12658 | ||
12659 | static int | |
4748a9be | 12660 | arm_record_vfp_data_proc_insn (arm_insn_decode_record *arm_insn_r) |
851f26ae OJ |
12661 | { |
12662 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
12663 | uint32_t record_buf[4]; | |
12664 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
12665 | enum insn_types curr_insn_type = INSN_INV; | |
12666 | ||
12667 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12668 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
12669 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12670 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
12671 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
12672 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
12673 | /* Mask off the "D" bit. */ |
12674 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
12675 | |
12676 | /* Handle VMLA, VMLS. */ | |
12677 | if (opc1 == 0x00) | |
12678 | { | |
12679 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12680 | { |
12681 | if (bit (arm_insn_r->arm_insn, 6)) | |
12682 | curr_insn_type = INSN_T0; | |
12683 | else | |
12684 | curr_insn_type = INSN_T1; | |
12685 | } | |
851f26ae | 12686 | else |
dda83cd7 SM |
12687 | { |
12688 | if (dp_op_sz) | |
12689 | curr_insn_type = INSN_T1; | |
12690 | else | |
12691 | curr_insn_type = INSN_T2; | |
12692 | } | |
851f26ae OJ |
12693 | } |
12694 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
12695 | else if (opc1 == 0x01) | |
12696 | { | |
12697 | if (dp_op_sz) | |
dda83cd7 | 12698 | curr_insn_type = INSN_T1; |
851f26ae | 12699 | else |
dda83cd7 | 12700 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12701 | } |
12702 | /* Handle VMUL. */ | |
12703 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
12704 | { | |
12705 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12706 | { |
12707 | if (bit (arm_insn_r->arm_insn, 6)) | |
12708 | curr_insn_type = INSN_T0; | |
12709 | else | |
12710 | curr_insn_type = INSN_T1; | |
12711 | } | |
851f26ae | 12712 | else |
dda83cd7 SM |
12713 | { |
12714 | if (dp_op_sz) | |
12715 | curr_insn_type = INSN_T1; | |
12716 | else | |
12717 | curr_insn_type = INSN_T2; | |
12718 | } | |
851f26ae OJ |
12719 | } |
12720 | /* Handle VADD, VSUB. */ | |
12721 | else if (opc1 == 0x03) | |
12722 | { | |
12723 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
12724 | { |
12725 | if (bit (arm_insn_r->arm_insn, 6)) | |
12726 | curr_insn_type = INSN_T0; | |
12727 | else | |
12728 | curr_insn_type = INSN_T1; | |
12729 | } | |
851f26ae | 12730 | else |
dda83cd7 SM |
12731 | { |
12732 | if (dp_op_sz) | |
12733 | curr_insn_type = INSN_T1; | |
12734 | else | |
12735 | curr_insn_type = INSN_T2; | |
12736 | } | |
851f26ae OJ |
12737 | } |
12738 | /* Handle VDIV. */ | |
ce887586 | 12739 | else if (opc1 == 0x08) |
851f26ae OJ |
12740 | { |
12741 | if (dp_op_sz) | |
dda83cd7 | 12742 | curr_insn_type = INSN_T1; |
851f26ae | 12743 | else |
dda83cd7 | 12744 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12745 | } |
12746 | /* Handle all other vfp data processing instructions. */ | |
12747 | else if (opc1 == 0x0b) | |
12748 | { | |
12749 | /* Handle VMOV. */ | |
12750 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
12751 | { |
12752 | if (bit (arm_insn_r->arm_insn, 4)) | |
12753 | { | |
12754 | if (bit (arm_insn_r->arm_insn, 6)) | |
12755 | curr_insn_type = INSN_T0; | |
12756 | else | |
12757 | curr_insn_type = INSN_T1; | |
12758 | } | |
12759 | else | |
12760 | { | |
12761 | if (dp_op_sz) | |
12762 | curr_insn_type = INSN_T1; | |
12763 | else | |
12764 | curr_insn_type = INSN_T2; | |
12765 | } | |
12766 | } | |
851f26ae OJ |
12767 | /* Handle VNEG and VABS. */ |
12768 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
12769 | || (opc2 == 0x00 && opc3 == 0x03)) |
12770 | { | |
12771 | if (!bit (arm_insn_r->arm_insn, 11)) | |
12772 | { | |
12773 | if (bit (arm_insn_r->arm_insn, 6)) | |
12774 | curr_insn_type = INSN_T0; | |
12775 | else | |
12776 | curr_insn_type = INSN_T1; | |
12777 | } | |
12778 | else | |
12779 | { | |
12780 | if (dp_op_sz) | |
12781 | curr_insn_type = INSN_T1; | |
12782 | else | |
12783 | curr_insn_type = INSN_T2; | |
12784 | } | |
12785 | } | |
851f26ae OJ |
12786 | /* Handle VSQRT. */ |
12787 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
12788 | { |
12789 | if (dp_op_sz) | |
12790 | curr_insn_type = INSN_T1; | |
12791 | else | |
12792 | curr_insn_type = INSN_T2; | |
12793 | } | |
851f26ae OJ |
12794 | /* Handle VCVT. */ |
12795 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
12796 | { |
12797 | if (!dp_op_sz) | |
12798 | curr_insn_type = INSN_T1; | |
12799 | else | |
12800 | curr_insn_type = INSN_T2; | |
12801 | } | |
851f26ae | 12802 | else if (opc3 & 0x01) |
dda83cd7 SM |
12803 | { |
12804 | /* Handle VCVT. */ | |
12805 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
12806 | { | |
12807 | if (!bit (arm_insn_r->arm_insn, 18)) | |
12808 | curr_insn_type = INSN_T2; | |
12809 | else | |
12810 | { | |
12811 | if (dp_op_sz) | |
12812 | curr_insn_type = INSN_T1; | |
12813 | else | |
12814 | curr_insn_type = INSN_T2; | |
12815 | } | |
12816 | } | |
12817 | /* Handle VCVT. */ | |
12818 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
12819 | { | |
12820 | if (dp_op_sz) | |
12821 | curr_insn_type = INSN_T1; | |
12822 | else | |
12823 | curr_insn_type = INSN_T2; | |
12824 | } | |
12825 | /* Handle VCVTB, VCVTT. */ | |
12826 | else if ((opc2 & 0x0e) == 0x02) | |
12827 | curr_insn_type = INSN_T2; | |
12828 | /* Handle VCMP, VCMPE. */ | |
12829 | else if ((opc2 & 0x0e) == 0x04) | |
12830 | curr_insn_type = INSN_T3; | |
12831 | } | |
851f26ae OJ |
12832 | } |
12833 | ||
12834 | switch (curr_insn_type) | |
12835 | { | |
12836 | case INSN_T0: | |
dda83cd7 SM |
12837 | reg_vd = reg_vd | (bit_d << 4); |
12838 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12839 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
12840 | arm_insn_r->reg_rec_count = 2; | |
12841 | break; | |
851f26ae OJ |
12842 | |
12843 | case INSN_T1: | |
dda83cd7 SM |
12844 | reg_vd = reg_vd | (bit_d << 4); |
12845 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12846 | arm_insn_r->reg_rec_count = 1; | |
12847 | break; | |
851f26ae OJ |
12848 | |
12849 | case INSN_T2: | |
dda83cd7 SM |
12850 | reg_vd = (reg_vd << 1) | bit_d; |
12851 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12852 | arm_insn_r->reg_rec_count = 1; | |
12853 | break; | |
851f26ae OJ |
12854 | |
12855 | case INSN_T3: | |
dda83cd7 SM |
12856 | record_buf[0] = ARM_FPSCR_REGNUM; |
12857 | arm_insn_r->reg_rec_count = 1; | |
12858 | break; | |
851f26ae OJ |
12859 | |
12860 | default: | |
dda83cd7 SM |
12861 | gdb_assert_not_reached ("no decoding pattern found"); |
12862 | break; | |
851f26ae OJ |
12863 | } |
12864 | ||
12865 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12866 | return 0; | |
12867 | } | |
12868 | ||
60cc5e93 OJ |
12869 | /* Handling opcode 110 insns. */ |
12870 | ||
12871 | static int | |
4748a9be | 12872 | arm_record_asimd_vfp_coproc (arm_insn_decode_record *arm_insn_r) |
60cc5e93 | 12873 | { |
bec2ab5a | 12874 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
12875 | |
12876 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
12877 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
12878 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12879 | ||
12880 | if ((coproc & 0x0e) == 0x0a) | |
12881 | { | |
12882 | /* Handle extension register ld/st instructions. */ | |
12883 | if (!(op1 & 0x20)) | |
dda83cd7 | 12884 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12885 | |
12886 | /* 64-bit transfers between arm core and extension registers. */ | |
12887 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 12888 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12889 | } |
12890 | else | |
12891 | { | |
12892 | /* Handle coprocessor ld/st instructions. */ | |
12893 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
12894 | { |
12895 | /* Store. */ | |
12896 | if (!op1_ebit) | |
12897 | return arm_record_unsupported_insn (arm_insn_r); | |
12898 | else | |
12899 | /* Load. */ | |
12900 | return arm_record_unsupported_insn (arm_insn_r); | |
12901 | } | |
60cc5e93 OJ |
12902 | |
12903 | /* Move to coprocessor from two arm core registers. */ | |
12904 | if (op1 == 0x4) | |
dda83cd7 | 12905 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
12906 | |
12907 | /* Move to two arm core registers from coprocessor. */ | |
12908 | if (op1 == 0x5) | |
dda83cd7 SM |
12909 | { |
12910 | uint32_t reg_t[2]; | |
60cc5e93 | 12911 | |
dda83cd7 SM |
12912 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
12913 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12914 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 12915 | |
dda83cd7 SM |
12916 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
12917 | return 0; | |
60cc5e93 OJ |
12918 | } |
12919 | } | |
12920 | return arm_record_unsupported_insn (arm_insn_r); | |
12921 | } | |
12922 | ||
72508ac0 PO |
12923 | /* Handling opcode 111 insns. */ |
12924 | ||
12925 | static int | |
4748a9be | 12926 | arm_record_coproc_data_proc (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 12927 | { |
2d9e6acb | 12928 | uint32_t op, op1_ebit, coproc, bits_24_25; |
345bd07c | 12929 | arm_gdbarch_tdep *tdep |
08106042 | 12930 | = gdbarch_tdep<arm_gdbarch_tdep> (arm_insn_r->gdbarch); |
72508ac0 | 12931 | struct regcache *reg_cache = arm_insn_r->regcache; |
72508ac0 PO |
12932 | |
12933 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 12934 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
12935 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
12936 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 12937 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
12938 | |
12939 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 12940 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
12941 | { |
12942 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
12943 | { |
12944 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 12945 | |
dda83cd7 | 12946 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 12947 | |
dda83cd7 SM |
12948 | if (svc_operand) /* OABI. */ |
12949 | svc_number = svc_operand - 0x900000; | |
12950 | else /* EABI. */ | |
12951 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 12952 | |
dda83cd7 SM |
12953 | return tdep->arm_syscall_record (reg_cache, svc_number); |
12954 | } | |
97dfe206 | 12955 | else |
dda83cd7 | 12956 | { |
6cb06a8c | 12957 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
12958 | return -1; |
12959 | } | |
97dfe206 | 12960 | } |
2d9e6acb | 12961 | else if (bits_24_25 == 0x02) |
60cc5e93 | 12962 | { |
2d9e6acb YQ |
12963 | if (op) |
12964 | { | |
12965 | if ((coproc & 0x0e) == 0x0a) | |
12966 | { | |
12967 | /* 8, 16, and 32-bit transfer */ | |
12968 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
12969 | } | |
12970 | else | |
12971 | { | |
12972 | if (op1_ebit) | |
12973 | { | |
12974 | /* MRC, MRC2 */ | |
12975 | uint32_t record_buf[1]; | |
12976 | ||
12977 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12978 | if (record_buf[0] == 15) | |
12979 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 12980 | |
2d9e6acb YQ |
12981 | arm_insn_r->reg_rec_count = 1; |
12982 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
12983 | record_buf); | |
12984 | return 0; | |
12985 | } | |
12986 | else | |
12987 | { | |
12988 | /* MCR, MCR2 */ | |
12989 | return -1; | |
12990 | } | |
12991 | } | |
12992 | } | |
12993 | else | |
12994 | { | |
12995 | if ((coproc & 0x0e) == 0x0a) | |
12996 | { | |
12997 | /* VFP data-processing instructions. */ | |
12998 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
12999 | } | |
13000 | else | |
13001 | { | |
13002 | /* CDP, CDP2 */ | |
13003 | return -1; | |
13004 | } | |
13005 | } | |
60cc5e93 | 13006 | } |
97dfe206 OJ |
13007 | else |
13008 | { | |
2d9e6acb | 13009 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 13010 | |
2d9e6acb YQ |
13011 | if (op1 == 5) |
13012 | { | |
13013 | if ((coproc & 0x0e) != 0x0a) | |
13014 | { | |
13015 | /* MRRC, MRRC2 */ | |
13016 | return -1; | |
13017 | } | |
13018 | } | |
13019 | else if (op1 == 4 || op1 == 5) | |
13020 | { | |
13021 | if ((coproc & 0x0e) == 0x0a) | |
13022 | { | |
13023 | /* 64-bit transfers between ARM core and extension */ | |
13024 | return -1; | |
13025 | } | |
13026 | else if (op1 == 4) | |
13027 | { | |
13028 | /* MCRR, MCRR2 */ | |
13029 | return -1; | |
13030 | } | |
13031 | } | |
13032 | else if (op1 == 0 || op1 == 1) | |
13033 | { | |
13034 | /* UNDEFINED */ | |
13035 | return -1; | |
13036 | } | |
13037 | else | |
13038 | { | |
13039 | if ((coproc & 0x0e) == 0x0a) | |
13040 | { | |
13041 | /* Extension register load/store */ | |
13042 | } | |
13043 | else | |
13044 | { | |
13045 | /* STC, STC2, LDC, LDC2 */ | |
13046 | } | |
13047 | return -1; | |
13048 | } | |
97dfe206 | 13049 | } |
72508ac0 | 13050 | |
2d9e6acb | 13051 | return -1; |
72508ac0 PO |
13052 | } |
13053 | ||
13054 | /* Handling opcode 000 insns. */ | |
13055 | ||
13056 | static int | |
4748a9be | 13057 | thumb_record_shift_add_sub (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13058 | { |
13059 | uint32_t record_buf[8]; | |
13060 | uint32_t reg_src1 = 0; | |
13061 | ||
13062 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13063 | ||
13064 | record_buf[0] = ARM_PS_REGNUM; | |
13065 | record_buf[1] = reg_src1; | |
13066 | thumb_insn_r->reg_rec_count = 2; | |
13067 | ||
13068 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13069 | ||
13070 | return 0; | |
13071 | } | |
13072 | ||
13073 | ||
13074 | /* Handling opcode 001 insns. */ | |
13075 | ||
13076 | static int | |
4748a9be | 13077 | thumb_record_add_sub_cmp_mov (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13078 | { |
13079 | uint32_t record_buf[8]; | |
13080 | uint32_t reg_src1 = 0; | |
13081 | ||
13082 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13083 | ||
13084 | record_buf[0] = ARM_PS_REGNUM; | |
13085 | record_buf[1] = reg_src1; | |
13086 | thumb_insn_r->reg_rec_count = 2; | |
13087 | ||
13088 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13089 | ||
13090 | return 0; | |
13091 | } | |
13092 | ||
13093 | /* Handling opcode 010 insns. */ | |
13094 | ||
13095 | static int | |
4748a9be | 13096 | thumb_record_ld_st_reg_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13097 | { |
13098 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13099 | uint32_t record_buf[8], record_buf_mem[8]; | |
13100 | ||
13101 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
13102 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
13103 | ||
13104 | ULONGEST u_regval[2] = {0}; | |
13105 | ||
13106 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
13107 | ||
13108 | if (bit (thumb_insn_r->arm_insn, 12)) | |
13109 | { | |
13110 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
13111 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
13112 | ||
b020ff80 | 13113 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
13114 | { |
13115 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
13116 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
13117 | record_buf[0] = reg_src1; | |
13118 | thumb_insn_r->reg_rec_count = 1; | |
13119 | } | |
b020ff80 | 13120 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
13121 | { |
13122 | /* STR(2), STRB(2), STRH(2) . */ | |
13123 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13124 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
13125 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
13126 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
13127 | if (0 == opB) | |
13128 | record_buf_mem[0] = 4; /* STR (2). */ | |
13129 | else if (2 == opB) | |
13130 | record_buf_mem[0] = 1; /* STRB (2). */ | |
13131 | else if (1 == opB) | |
13132 | record_buf_mem[0] = 2; /* STRH (2). */ | |
13133 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
13134 | thumb_insn_r->mem_rec_count = 1; | |
13135 | } | |
72508ac0 PO |
13136 | } |
13137 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
13138 | { | |
13139 | /* Handle load from literal pool. */ | |
13140 | /* LDR(3). */ | |
13141 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13142 | record_buf[0] = reg_src1; | |
13143 | thumb_insn_r->reg_rec_count = 1; | |
13144 | } | |
13145 | else if (opcode1) | |
13146 | { | |
b121eeb9 | 13147 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
13148 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
13149 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13150 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
13151 | { |
13152 | /* Branch with exchange. */ | |
13153 | record_buf[0] = ARM_PS_REGNUM; | |
13154 | thumb_insn_r->reg_rec_count = 1; | |
13155 | } | |
72508ac0 | 13156 | else |
dda83cd7 | 13157 | { |
1f33efec YQ |
13158 | /* Format 8; special data processing insns. */ |
13159 | record_buf[0] = ARM_PS_REGNUM; | |
13160 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
13161 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
13162 | thumb_insn_r->reg_rec_count = 2; |
13163 | } | |
72508ac0 PO |
13164 | } |
13165 | else | |
13166 | { | |
13167 | /* Format 5; data processing insns. */ | |
13168 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13169 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
13170 | { |
13171 | reg_src1 = reg_src1 + 8; | |
13172 | } | |
72508ac0 PO |
13173 | record_buf[0] = ARM_PS_REGNUM; |
13174 | record_buf[1] = reg_src1; | |
13175 | thumb_insn_r->reg_rec_count = 2; | |
13176 | } | |
13177 | ||
13178 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13179 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13180 | record_buf_mem); |
72508ac0 PO |
13181 | |
13182 | return 0; | |
13183 | } | |
13184 | ||
13185 | /* Handling opcode 001 insns. */ | |
13186 | ||
13187 | static int | |
4748a9be | 13188 | thumb_record_ld_st_imm_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13189 | { |
13190 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13191 | uint32_t record_buf[8], record_buf_mem[8]; | |
13192 | ||
13193 | uint32_t reg_src1 = 0; | |
13194 | uint32_t opcode = 0, immed_5 = 0; | |
13195 | ||
13196 | ULONGEST u_regval = 0; | |
13197 | ||
13198 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13199 | ||
13200 | if (opcode) | |
13201 | { | |
13202 | /* LDR(1). */ | |
13203 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13204 | record_buf[0] = reg_src1; | |
13205 | thumb_insn_r->reg_rec_count = 1; | |
13206 | } | |
13207 | else | |
13208 | { | |
13209 | /* STR(1). */ | |
13210 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13211 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13212 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13213 | record_buf_mem[0] = 4; | |
13214 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
13215 | thumb_insn_r->mem_rec_count = 1; | |
13216 | } | |
13217 | ||
13218 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13219 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13220 | record_buf_mem); |
72508ac0 PO |
13221 | |
13222 | return 0; | |
13223 | } | |
13224 | ||
13225 | /* Handling opcode 100 insns. */ | |
13226 | ||
13227 | static int | |
4748a9be | 13228 | thumb_record_ld_st_stack (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13229 | { |
13230 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13231 | uint32_t record_buf[8], record_buf_mem[8]; | |
13232 | ||
13233 | uint32_t reg_src1 = 0; | |
13234 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
13235 | ||
13236 | ULONGEST u_regval = 0; | |
13237 | ||
13238 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13239 | ||
13240 | if (3 == opcode) | |
13241 | { | |
13242 | /* LDR(4). */ | |
13243 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13244 | record_buf[0] = reg_src1; | |
13245 | thumb_insn_r->reg_rec_count = 1; | |
13246 | } | |
13247 | else if (1 == opcode) | |
13248 | { | |
13249 | /* LDRH(1). */ | |
13250 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13251 | record_buf[0] = reg_src1; | |
13252 | thumb_insn_r->reg_rec_count = 1; | |
13253 | } | |
13254 | else if (2 == opcode) | |
13255 | { | |
13256 | /* STR(3). */ | |
13257 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
13258 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13259 | record_buf_mem[0] = 4; | |
13260 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
13261 | thumb_insn_r->mem_rec_count = 1; | |
13262 | } | |
13263 | else if (0 == opcode) | |
13264 | { | |
13265 | /* STRH(1). */ | |
13266 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13267 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13268 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13269 | record_buf_mem[0] = 2; | |
13270 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
13271 | thumb_insn_r->mem_rec_count = 1; | |
13272 | } | |
13273 | ||
13274 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13275 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13276 | record_buf_mem); |
72508ac0 PO |
13277 | |
13278 | return 0; | |
13279 | } | |
13280 | ||
13281 | /* Handling opcode 101 insns. */ | |
13282 | ||
13283 | static int | |
4748a9be | 13284 | thumb_record_misc (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13285 | { |
13286 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13287 | ||
b121eeb9 | 13288 | uint32_t opcode = 0; |
72508ac0 | 13289 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 13290 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13291 | uint32_t record_buf[24], record_buf_mem[48]; |
13292 | uint32_t reg_src1; | |
13293 | ||
13294 | ULONGEST u_regval = 0; | |
13295 | ||
13296 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 13297 | |
b121eeb9 | 13298 | if (opcode == 0 || opcode == 1) |
72508ac0 | 13299 | { |
b121eeb9 YQ |
13300 | /* ADR and ADD (SP plus immediate) */ |
13301 | ||
72508ac0 PO |
13302 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
13303 | record_buf[0] = reg_src1; | |
13304 | thumb_insn_r->reg_rec_count = 1; | |
13305 | } | |
b121eeb9 | 13306 | else |
72508ac0 | 13307 | { |
b121eeb9 YQ |
13308 | /* Miscellaneous 16-bit instructions */ |
13309 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
13310 | ||
13311 | switch (opcode2) | |
13312 | { | |
13313 | case 6: | |
13314 | /* SETEND and CPS */ | |
13315 | break; | |
13316 | case 0: | |
13317 | /* ADD/SUB (SP plus immediate) */ | |
13318 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13319 | record_buf[0] = ARM_SP_REGNUM; | |
13320 | thumb_insn_r->reg_rec_count = 1; | |
13321 | break; | |
13322 | case 1: /* fall through */ | |
13323 | case 3: /* fall through */ | |
13324 | case 9: /* fall through */ | |
13325 | case 11: | |
13326 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
13327 | break; |
13328 | case 2: | |
13329 | /* SXTH, SXTB, UXTH, UXTB */ | |
13330 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
13331 | thumb_insn_r->reg_rec_count = 1; | |
13332 | break; | |
13333 | case 4: /* fall through */ | |
13334 | case 5: | |
13335 | /* PUSH. */ | |
13336 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13337 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13338 | while (register_bits) | |
13339 | { | |
13340 | if (register_bits & 0x00000001) | |
13341 | register_count++; | |
13342 | register_bits = register_bits >> 1; | |
13343 | } | |
13344 | start_address = u_regval - \ | |
13345 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
13346 | thumb_insn_r->mem_rec_count = register_count; | |
13347 | while (register_count) | |
13348 | { | |
13349 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13350 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13351 | start_address = start_address + 4; | |
13352 | register_count--; | |
13353 | } | |
13354 | record_buf[0] = ARM_SP_REGNUM; | |
13355 | thumb_insn_r->reg_rec_count = 1; | |
13356 | break; | |
13357 | case 10: | |
13358 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
13359 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
13360 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
13361 | break; |
13362 | case 12: /* fall through */ | |
13363 | case 13: | |
13364 | /* POP. */ | |
13365 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13366 | while (register_bits) | |
13367 | { | |
13368 | if (register_bits & 0x00000001) | |
13369 | record_buf[index++] = register_count; | |
13370 | register_bits = register_bits >> 1; | |
13371 | register_count++; | |
13372 | } | |
13373 | record_buf[index++] = ARM_PS_REGNUM; | |
13374 | record_buf[index++] = ARM_SP_REGNUM; | |
13375 | thumb_insn_r->reg_rec_count = index; | |
13376 | break; | |
13377 | case 0xe: | |
13378 | /* BKPT insn. */ | |
13379 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
13380 | /* CPSR is changed to be executed in ARM state, disabling normal | |
13381 | interrupts, entering abort mode. */ | |
13382 | /* According to high vector configuration PC is set. */ | |
13383 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
13384 | previous CPSR and Program Counter. */ | |
13385 | record_buf[0] = ARM_PS_REGNUM; | |
13386 | record_buf[1] = ARM_LR_REGNUM; | |
13387 | thumb_insn_r->reg_rec_count = 2; | |
13388 | /* We need to save SPSR value, which is not yet done. */ | |
6cb06a8c TT |
13389 | gdb_printf (gdb_stderr, |
13390 | _("Process record does not support instruction " | |
13391 | "0x%0x at address %s.\n"), | |
13392 | thumb_insn_r->arm_insn, | |
13393 | paddress (thumb_insn_r->gdbarch, | |
13394 | thumb_insn_r->this_addr)); | |
b121eeb9 YQ |
13395 | return -1; |
13396 | ||
13397 | case 0xf: | |
13398 | /* If-Then, and hints */ | |
13399 | break; | |
13400 | default: | |
13401 | return -1; | |
13402 | }; | |
72508ac0 PO |
13403 | } |
13404 | ||
13405 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13406 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13407 | record_buf_mem); |
72508ac0 PO |
13408 | |
13409 | return 0; | |
13410 | } | |
13411 | ||
13412 | /* Handling opcode 110 insns. */ | |
13413 | ||
13414 | static int | |
4748a9be | 13415 | thumb_record_ldm_stm_swi (arm_insn_decode_record *thumb_insn_r) |
72508ac0 | 13416 | { |
345bd07c | 13417 | arm_gdbarch_tdep *tdep |
08106042 | 13418 | = gdbarch_tdep<arm_gdbarch_tdep> (thumb_insn_r->gdbarch); |
72508ac0 PO |
13419 | struct regcache *reg_cache = thumb_insn_r->regcache; |
13420 | ||
13421 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
13422 | uint32_t reg_src1 = 0; | |
13423 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 13424 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13425 | uint32_t record_buf[24], record_buf_mem[48]; |
13426 | ||
13427 | ULONGEST u_regval = 0; | |
13428 | ||
13429 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
13430 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
13431 | ||
13432 | if (1 == opcode2) | |
13433 | { | |
13434 | ||
13435 | /* LDMIA. */ | |
13436 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13437 | /* Get Rn. */ | |
13438 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13439 | while (register_bits) | |
dda83cd7 SM |
13440 | { |
13441 | if (register_bits & 0x00000001) | |
13442 | record_buf[index++] = register_count; | |
13443 | register_bits = register_bits >> 1; | |
13444 | register_count++; | |
13445 | } | |
f969241e OJ |
13446 | record_buf[index++] = reg_src1; |
13447 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
13448 | } |
13449 | else if (0 == opcode2) | |
13450 | { | |
13451 | /* It handles both STMIA. */ | |
13452 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13453 | /* Get Rn. */ | |
13454 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13455 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13456 | while (register_bits) | |
dda83cd7 SM |
13457 | { |
13458 | if (register_bits & 0x00000001) | |
13459 | register_count++; | |
13460 | register_bits = register_bits >> 1; | |
13461 | } | |
72508ac0 PO |
13462 | start_address = u_regval; |
13463 | thumb_insn_r->mem_rec_count = register_count; | |
13464 | while (register_count) | |
dda83cd7 SM |
13465 | { |
13466 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13467 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13468 | start_address = start_address + 4; | |
13469 | register_count--; | |
13470 | } | |
72508ac0 PO |
13471 | } |
13472 | else if (0x1F == opcode1) | |
13473 | { | |
dda83cd7 SM |
13474 | /* Handle arm syscall insn. */ |
13475 | if (tdep->arm_syscall_record != NULL) | |
13476 | { | |
13477 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
13478 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
13479 | } | |
13480 | else | |
13481 | { | |
6cb06a8c | 13482 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
13483 | return -1; |
13484 | } | |
72508ac0 PO |
13485 | } |
13486 | ||
13487 | /* B (1), conditional branch is automatically taken care in process_record, | |
13488 | as PC is saved there. */ | |
13489 | ||
13490 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13491 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13492 | record_buf_mem); |
72508ac0 PO |
13493 | |
13494 | return ret; | |
13495 | } | |
13496 | ||
13497 | /* Handling opcode 111 insns. */ | |
13498 | ||
13499 | static int | |
4748a9be | 13500 | thumb_record_branch (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13501 | { |
13502 | uint32_t record_buf[8]; | |
13503 | uint32_t bits_h = 0; | |
13504 | ||
13505 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
13506 | ||
13507 | if (2 == bits_h || 3 == bits_h) | |
13508 | { | |
13509 | /* BL */ | |
13510 | record_buf[0] = ARM_LR_REGNUM; | |
13511 | thumb_insn_r->reg_rec_count = 1; | |
13512 | } | |
13513 | else if (1 == bits_h) | |
13514 | { | |
13515 | /* BLX(1). */ | |
13516 | record_buf[0] = ARM_PS_REGNUM; | |
13517 | record_buf[1] = ARM_LR_REGNUM; | |
13518 | thumb_insn_r->reg_rec_count = 2; | |
13519 | } | |
13520 | ||
13521 | /* B(2) is automatically taken care in process_record, as PC is | |
13522 | saved there. */ | |
13523 | ||
13524 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13525 | ||
13526 | return 0; | |
13527 | } | |
13528 | ||
c6ec2b30 OJ |
13529 | /* Handler for thumb2 load/store multiple instructions. */ |
13530 | ||
13531 | static int | |
4748a9be | 13532 | thumb2_record_ld_st_multiple (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13533 | { |
13534 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13535 | ||
13536 | uint32_t reg_rn, op; | |
13537 | uint32_t register_bits = 0, register_count = 0; | |
13538 | uint32_t index = 0, start_address = 0; | |
13539 | uint32_t record_buf[24], record_buf_mem[48]; | |
13540 | ||
13541 | ULONGEST u_regval = 0; | |
13542 | ||
13543 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13544 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13545 | ||
13546 | if (0 == op || 3 == op) | |
13547 | { | |
13548 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13549 | { |
13550 | /* Handle RFE instruction. */ | |
13551 | record_buf[0] = ARM_PS_REGNUM; | |
13552 | thumb2_insn_r->reg_rec_count = 1; | |
13553 | } | |
c6ec2b30 | 13554 | else |
dda83cd7 SM |
13555 | { |
13556 | /* Handle SRS instruction after reading banked SP. */ | |
13557 | return arm_record_unsupported_insn (thumb2_insn_r); | |
13558 | } | |
c6ec2b30 OJ |
13559 | } |
13560 | else if (1 == op || 2 == op) | |
13561 | { | |
13562 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13563 | { |
13564 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
13565 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13566 | while (register_bits) | |
13567 | { | |
13568 | if (register_bits & 0x00000001) | |
13569 | record_buf[index++] = register_count; | |
13570 | ||
13571 | register_count++; | |
13572 | register_bits = register_bits >> 1; | |
13573 | } | |
13574 | record_buf[index++] = reg_rn; | |
13575 | record_buf[index++] = ARM_PS_REGNUM; | |
13576 | thumb2_insn_r->reg_rec_count = index; | |
13577 | } | |
c6ec2b30 | 13578 | else |
dda83cd7 SM |
13579 | { |
13580 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
13581 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13582 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13583 | while (register_bits) | |
13584 | { | |
13585 | if (register_bits & 0x00000001) | |
13586 | register_count++; | |
13587 | ||
13588 | register_bits = register_bits >> 1; | |
13589 | } | |
13590 | ||
13591 | if (1 == op) | |
13592 | { | |
13593 | /* Start address calculation for LDMDB/LDMEA. */ | |
13594 | start_address = u_regval; | |
13595 | } | |
13596 | else if (2 == op) | |
13597 | { | |
13598 | /* Start address calculation for LDMDB/LDMEA. */ | |
13599 | start_address = u_regval - register_count * 4; | |
13600 | } | |
13601 | ||
13602 | thumb2_insn_r->mem_rec_count = register_count; | |
13603 | while (register_count) | |
13604 | { | |
13605 | record_buf_mem[register_count * 2 - 1] = start_address; | |
13606 | record_buf_mem[register_count * 2 - 2] = 4; | |
13607 | start_address = start_address + 4; | |
13608 | register_count--; | |
13609 | } | |
13610 | record_buf[0] = reg_rn; | |
13611 | record_buf[1] = ARM_PS_REGNUM; | |
13612 | thumb2_insn_r->reg_rec_count = 2; | |
13613 | } | |
c6ec2b30 OJ |
13614 | } |
13615 | ||
13616 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 13617 | record_buf_mem); |
c6ec2b30 | 13618 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 13619 | record_buf); |
c6ec2b30 OJ |
13620 | return ARM_RECORD_SUCCESS; |
13621 | } | |
13622 | ||
13623 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
13624 | instructions. */ | |
13625 | ||
13626 | static int | |
4748a9be | 13627 | thumb2_record_ld_st_dual_ex_tbb (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13628 | { |
13629 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13630 | ||
13631 | uint32_t reg_rd, reg_rn, offset_imm; | |
13632 | uint32_t reg_dest1, reg_dest2; | |
13633 | uint32_t address, offset_addr; | |
13634 | uint32_t record_buf[8], record_buf_mem[8]; | |
13635 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
13636 | |
13637 | ULONGEST u_regval[2]; | |
13638 | ||
13639 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13640 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
13641 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13642 | ||
13643 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13644 | { | |
13645 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
13646 | { |
13647 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13648 | record_buf[0] = reg_dest1; | |
13649 | record_buf[1] = ARM_PS_REGNUM; | |
13650 | thumb2_insn_r->reg_rec_count = 2; | |
13651 | } | |
c6ec2b30 OJ |
13652 | |
13653 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
13654 | { |
13655 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13656 | record_buf[2] = reg_dest2; | |
13657 | thumb2_insn_r->reg_rec_count = 3; | |
13658 | } | |
c6ec2b30 OJ |
13659 | } |
13660 | else | |
13661 | { | |
13662 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13663 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13664 | ||
13665 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
13666 | { |
13667 | /* Handle STREX. */ | |
13668 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13669 | address = u_regval[0] + (offset_imm * 4); | |
13670 | record_buf_mem[0] = 4; | |
13671 | record_buf_mem[1] = address; | |
13672 | thumb2_insn_r->mem_rec_count = 1; | |
13673 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13674 | record_buf[0] = reg_rd; | |
13675 | thumb2_insn_r->reg_rec_count = 1; | |
13676 | } | |
c6ec2b30 | 13677 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
13678 | { |
13679 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13680 | record_buf[0] = reg_rd; | |
13681 | thumb2_insn_r->reg_rec_count = 1; | |
13682 | address = u_regval[0]; | |
13683 | record_buf_mem[1] = address; | |
13684 | ||
13685 | if (4 == op3) | |
13686 | { | |
13687 | /* Handle STREXB. */ | |
13688 | record_buf_mem[0] = 1; | |
13689 | thumb2_insn_r->mem_rec_count = 1; | |
13690 | } | |
13691 | else if (5 == op3) | |
13692 | { | |
13693 | /* Handle STREXH. */ | |
13694 | record_buf_mem[0] = 2 ; | |
13695 | thumb2_insn_r->mem_rec_count = 1; | |
13696 | } | |
13697 | else if (7 == op3) | |
13698 | { | |
13699 | /* Handle STREXD. */ | |
13700 | address = u_regval[0]; | |
13701 | record_buf_mem[0] = 4; | |
13702 | record_buf_mem[2] = 4; | |
13703 | record_buf_mem[3] = address + 4; | |
13704 | thumb2_insn_r->mem_rec_count = 2; | |
13705 | } | |
13706 | } | |
c6ec2b30 | 13707 | else |
dda83cd7 SM |
13708 | { |
13709 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13710 | ||
13711 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
13712 | { | |
13713 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13714 | offset_addr = u_regval[0] + (offset_imm * 4); | |
13715 | else | |
13716 | offset_addr = u_regval[0] - (offset_imm * 4); | |
13717 | ||
13718 | address = offset_addr; | |
13719 | } | |
13720 | else | |
13721 | address = u_regval[0]; | |
13722 | ||
13723 | record_buf_mem[0] = 4; | |
13724 | record_buf_mem[1] = address; | |
13725 | record_buf_mem[2] = 4; | |
13726 | record_buf_mem[3] = address + 4; | |
13727 | thumb2_insn_r->mem_rec_count = 2; | |
13728 | record_buf[0] = reg_rn; | |
13729 | thumb2_insn_r->reg_rec_count = 1; | |
13730 | } | |
c6ec2b30 OJ |
13731 | } |
13732 | ||
13733 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13734 | record_buf); |
c6ec2b30 | 13735 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13736 | record_buf_mem); |
c6ec2b30 OJ |
13737 | return ARM_RECORD_SUCCESS; |
13738 | } | |
13739 | ||
13740 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
13741 | instructions. */ | |
13742 | ||
13743 | static int | |
4748a9be | 13744 | thumb2_record_data_proc_sreg_mimm (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13745 | { |
13746 | uint32_t reg_rd, op; | |
13747 | uint32_t record_buf[8]; | |
13748 | ||
13749 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
13750 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13751 | ||
13752 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
13753 | { | |
13754 | record_buf[0] = ARM_PS_REGNUM; | |
13755 | thumb2_insn_r->reg_rec_count = 1; | |
13756 | } | |
13757 | else | |
13758 | { | |
13759 | record_buf[0] = reg_rd; | |
13760 | record_buf[1] = ARM_PS_REGNUM; | |
13761 | thumb2_insn_r->reg_rec_count = 2; | |
13762 | } | |
13763 | ||
13764 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13765 | record_buf); |
c6ec2b30 OJ |
13766 | return ARM_RECORD_SUCCESS; |
13767 | } | |
13768 | ||
13769 | /* Generic handler for thumb2 instructions which effect destination and PS | |
13770 | registers. */ | |
13771 | ||
13772 | static int | |
4748a9be | 13773 | thumb2_record_ps_dest_generic (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13774 | { |
13775 | uint32_t reg_rd; | |
13776 | uint32_t record_buf[8]; | |
13777 | ||
13778 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13779 | ||
13780 | record_buf[0] = reg_rd; | |
13781 | record_buf[1] = ARM_PS_REGNUM; | |
13782 | thumb2_insn_r->reg_rec_count = 2; | |
13783 | ||
13784 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13785 | record_buf); |
c6ec2b30 OJ |
13786 | return ARM_RECORD_SUCCESS; |
13787 | } | |
13788 | ||
13789 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
13790 | ||
13791 | static int | |
4748a9be | 13792 | thumb2_record_branch_misc_cntrl (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13793 | { |
13794 | uint32_t op, op1, op2; | |
13795 | uint32_t record_buf[8]; | |
13796 | ||
13797 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13798 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
13799 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13800 | ||
13801 | /* Handle MSR insn. */ | |
13802 | if (!(op1 & 0x2) && 0x38 == op) | |
13803 | { | |
13804 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
13805 | { |
13806 | /* CPSR is going to be changed. */ | |
13807 | record_buf[0] = ARM_PS_REGNUM; | |
13808 | thumb2_insn_r->reg_rec_count = 1; | |
13809 | } | |
c6ec2b30 | 13810 | else |
dda83cd7 SM |
13811 | { |
13812 | arm_record_unsupported_insn(thumb2_insn_r); | |
13813 | return -1; | |
13814 | } | |
c6ec2b30 OJ |
13815 | } |
13816 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
13817 | { | |
13818 | /* BLX. */ | |
13819 | record_buf[0] = ARM_PS_REGNUM; | |
13820 | record_buf[1] = ARM_LR_REGNUM; | |
13821 | thumb2_insn_r->reg_rec_count = 2; | |
13822 | } | |
13823 | ||
13824 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13825 | record_buf); |
c6ec2b30 OJ |
13826 | return ARM_RECORD_SUCCESS; |
13827 | } | |
13828 | ||
13829 | /* Handler for thumb2 store single data item instructions. */ | |
13830 | ||
13831 | static int | |
4748a9be | 13832 | thumb2_record_str_single_data (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13833 | { |
13834 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13835 | ||
13836 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
13837 | uint32_t address, offset_addr; | |
13838 | uint32_t record_buf[8], record_buf_mem[8]; | |
13839 | uint32_t op1, op2; | |
13840 | ||
13841 | ULONGEST u_regval[2]; | |
13842 | ||
13843 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
13844 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
13845 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13846 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13847 | ||
13848 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13849 | { | |
13850 | /* T2 encoding. */ | |
13851 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
13852 | offset_addr = u_regval[0] + offset_imm; | |
13853 | address = offset_addr; | |
13854 | } | |
13855 | else | |
13856 | { | |
13857 | /* T3 encoding. */ | |
13858 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
13859 | { |
13860 | /* Handle STRB (register). */ | |
13861 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13862 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
13863 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
13864 | offset_addr = u_regval[1] << shift_imm; | |
13865 | address = u_regval[0] + offset_addr; | |
13866 | } | |
c6ec2b30 | 13867 | else |
dda83cd7 SM |
13868 | { |
13869 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13870 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
13871 | { | |
13872 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
13873 | offset_addr = u_regval[0] + offset_imm; | |
13874 | else | |
13875 | offset_addr = u_regval[0] - offset_imm; | |
13876 | ||
13877 | address = offset_addr; | |
13878 | } | |
13879 | else | |
13880 | address = u_regval[0]; | |
13881 | } | |
c6ec2b30 OJ |
13882 | } |
13883 | ||
13884 | switch (op1) | |
13885 | { | |
13886 | /* Store byte instructions. */ | |
13887 | case 4: | |
13888 | case 0: | |
dda83cd7 SM |
13889 | record_buf_mem[0] = 1; |
13890 | break; | |
c6ec2b30 OJ |
13891 | /* Store half word instructions. */ |
13892 | case 1: | |
13893 | case 5: | |
dda83cd7 SM |
13894 | record_buf_mem[0] = 2; |
13895 | break; | |
c6ec2b30 OJ |
13896 | /* Store word instructions. */ |
13897 | case 2: | |
13898 | case 6: | |
dda83cd7 SM |
13899 | record_buf_mem[0] = 4; |
13900 | break; | |
c6ec2b30 OJ |
13901 | |
13902 | default: | |
dda83cd7 SM |
13903 | gdb_assert_not_reached ("no decoding pattern found"); |
13904 | break; | |
c6ec2b30 OJ |
13905 | } |
13906 | ||
13907 | record_buf_mem[1] = address; | |
13908 | thumb2_insn_r->mem_rec_count = 1; | |
13909 | record_buf[0] = reg_rn; | |
13910 | thumb2_insn_r->reg_rec_count = 1; | |
13911 | ||
13912 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13913 | record_buf); |
c6ec2b30 | 13914 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13915 | record_buf_mem); |
c6ec2b30 OJ |
13916 | return ARM_RECORD_SUCCESS; |
13917 | } | |
13918 | ||
13919 | /* Handler for thumb2 load memory hints instructions. */ | |
13920 | ||
13921 | static int | |
4748a9be | 13922 | thumb2_record_ld_mem_hints (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13923 | { |
13924 | uint32_t record_buf[8]; | |
13925 | uint32_t reg_rt, reg_rn; | |
13926 | ||
13927 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13928 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13929 | ||
13930 | if (ARM_PC_REGNUM != reg_rt) | |
13931 | { | |
13932 | record_buf[0] = reg_rt; | |
13933 | record_buf[1] = reg_rn; | |
13934 | record_buf[2] = ARM_PS_REGNUM; | |
13935 | thumb2_insn_r->reg_rec_count = 3; | |
13936 | ||
13937 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13938 | record_buf); |
c6ec2b30 OJ |
13939 | return ARM_RECORD_SUCCESS; |
13940 | } | |
13941 | ||
13942 | return ARM_RECORD_FAILURE; | |
13943 | } | |
13944 | ||
13945 | /* Handler for thumb2 load word instructions. */ | |
13946 | ||
13947 | static int | |
4748a9be | 13948 | thumb2_record_ld_word (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 | 13949 | { |
c6ec2b30 OJ |
13950 | uint32_t record_buf[8]; |
13951 | ||
13952 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13953 | record_buf[1] = ARM_PS_REGNUM; | |
13954 | thumb2_insn_r->reg_rec_count = 2; | |
13955 | ||
13956 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13957 | record_buf); |
c6ec2b30 OJ |
13958 | return ARM_RECORD_SUCCESS; |
13959 | } | |
13960 | ||
13961 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
13962 | divide instructions. */ | |
13963 | ||
13964 | static int | |
4748a9be | 13965 | thumb2_record_lmul_lmla_div (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13966 | { |
13967 | uint32_t opcode1 = 0, opcode2 = 0; | |
13968 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
13969 | |
13970 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
13971 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13972 | ||
13973 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
13974 | { | |
13975 | /* Handle SMULL, UMULL, SMULAL. */ | |
13976 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
13977 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13978 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13979 | record_buf[2] = ARM_PS_REGNUM; | |
13980 | thumb2_insn_r->reg_rec_count = 3; | |
13981 | } | |
13982 | else if (1 == opcode1 || 3 == opcode2) | |
13983 | { | |
13984 | /* Handle SDIV and UDIV. */ | |
13985 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13986 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13987 | record_buf[2] = ARM_PS_REGNUM; | |
13988 | thumb2_insn_r->reg_rec_count = 3; | |
13989 | } | |
13990 | else | |
13991 | return ARM_RECORD_FAILURE; | |
13992 | ||
13993 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13994 | record_buf); |
c6ec2b30 OJ |
13995 | return ARM_RECORD_SUCCESS; |
13996 | } | |
13997 | ||
60cc5e93 OJ |
13998 | /* Record handler for thumb32 coprocessor instructions. */ |
13999 | ||
14000 | static int | |
4748a9be | 14001 | thumb2_record_coproc_insn (arm_insn_decode_record *thumb2_insn_r) |
60cc5e93 OJ |
14002 | { |
14003 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
14004 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
14005 | else | |
14006 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
14007 | } | |
14008 | ||
1e1b6563 OJ |
14009 | /* Record handler for advance SIMD structure load/store instructions. */ |
14010 | ||
14011 | static int | |
4748a9be | 14012 | thumb2_record_asimd_struct_ld_st (arm_insn_decode_record *thumb2_insn_r) |
1e1b6563 OJ |
14013 | { |
14014 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
14015 | uint32_t l_bit, a_bit, b_bits; | |
14016 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 14017 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
14018 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
14019 | uint8_t f_ebytes; | |
14020 | ||
14021 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
14022 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
14023 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
14024 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
14025 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14026 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
14027 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
14028 | f_elem = 8 / f_ebytes; |
14029 | ||
14030 | if (!l_bit) | |
14031 | { | |
14032 | ULONGEST u_regval = 0; | |
14033 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
14034 | address = u_regval; | |
14035 | ||
14036 | if (!a_bit) | |
dda83cd7 SM |
14037 | { |
14038 | /* Handle VST1. */ | |
14039 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
14040 | { | |
14041 | if (b_bits == 0x07) | |
14042 | bf_regs = 1; | |
14043 | else if (b_bits == 0x0a) | |
14044 | bf_regs = 2; | |
14045 | else if (b_bits == 0x06) | |
14046 | bf_regs = 3; | |
14047 | else if (b_bits == 0x02) | |
14048 | bf_regs = 4; | |
14049 | else | |
14050 | bf_regs = 0; | |
14051 | ||
14052 | for (index_r = 0; index_r < bf_regs; index_r++) | |
14053 | { | |
14054 | for (index_e = 0; index_e < f_elem; index_e++) | |
14055 | { | |
14056 | record_buf_mem[index_m++] = f_ebytes; | |
14057 | record_buf_mem[index_m++] = address; | |
14058 | address = address + f_ebytes; | |
14059 | thumb2_insn_r->mem_rec_count += 1; | |
14060 | } | |
14061 | } | |
14062 | } | |
14063 | /* Handle VST2. */ | |
14064 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
14065 | { | |
14066 | if (b_bits == 0x09 || b_bits == 0x08) | |
14067 | bf_regs = 1; | |
14068 | else if (b_bits == 0x03) | |
14069 | bf_regs = 2; | |
14070 | else | |
14071 | bf_regs = 0; | |
14072 | ||
14073 | for (index_r = 0; index_r < bf_regs; index_r++) | |
14074 | for (index_e = 0; index_e < f_elem; index_e++) | |
14075 | { | |
14076 | for (loop_t = 0; loop_t < 2; loop_t++) | |
14077 | { | |
14078 | record_buf_mem[index_m++] = f_ebytes; | |
14079 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14080 | thumb2_insn_r->mem_rec_count += 1; | |
14081 | } | |
14082 | address = address + (2 * f_ebytes); | |
14083 | } | |
14084 | } | |
14085 | /* Handle VST3. */ | |
14086 | else if ((b_bits & 0x0e) == 0x04) | |
14087 | { | |
14088 | for (index_e = 0; index_e < f_elem; index_e++) | |
14089 | { | |
14090 | for (loop_t = 0; loop_t < 3; loop_t++) | |
14091 | { | |
14092 | record_buf_mem[index_m++] = f_ebytes; | |
14093 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14094 | thumb2_insn_r->mem_rec_count += 1; | |
14095 | } | |
14096 | address = address + (3 * f_ebytes); | |
14097 | } | |
14098 | } | |
14099 | /* Handle VST4. */ | |
14100 | else if (!(b_bits & 0x0e)) | |
14101 | { | |
14102 | for (index_e = 0; index_e < f_elem; index_e++) | |
14103 | { | |
14104 | for (loop_t = 0; loop_t < 4; loop_t++) | |
14105 | { | |
14106 | record_buf_mem[index_m++] = f_ebytes; | |
14107 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14108 | thumb2_insn_r->mem_rec_count += 1; | |
14109 | } | |
14110 | address = address + (4 * f_ebytes); | |
14111 | } | |
14112 | } | |
14113 | } | |
1e1b6563 | 14114 | else |
dda83cd7 SM |
14115 | { |
14116 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
14117 | ||
14118 | if (bft_size == 0x00) | |
14119 | f_ebytes = 1; | |
14120 | else if (bft_size == 0x01) | |
14121 | f_ebytes = 2; | |
14122 | else if (bft_size == 0x02) | |
14123 | f_ebytes = 4; | |
14124 | else | |
14125 | f_ebytes = 0; | |
14126 | ||
14127 | /* Handle VST1. */ | |
14128 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
14129 | thumb2_insn_r->mem_rec_count = 1; | |
14130 | /* Handle VST2. */ | |
14131 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
14132 | thumb2_insn_r->mem_rec_count = 2; | |
14133 | /* Handle VST3. */ | |
14134 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
14135 | thumb2_insn_r->mem_rec_count = 3; | |
14136 | /* Handle VST4. */ | |
14137 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
14138 | thumb2_insn_r->mem_rec_count = 4; | |
14139 | ||
14140 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
14141 | { | |
14142 | record_buf_mem[index_m] = f_ebytes; | |
14143 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
14144 | } | |
14145 | } | |
1e1b6563 OJ |
14146 | } |
14147 | else | |
14148 | { | |
14149 | if (!a_bit) | |
dda83cd7 SM |
14150 | { |
14151 | /* Handle VLD1. */ | |
14152 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
14153 | thumb2_insn_r->reg_rec_count = 1; | |
14154 | /* Handle VLD2. */ | |
14155 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
14156 | thumb2_insn_r->reg_rec_count = 2; | |
14157 | /* Handle VLD3. */ | |
14158 | else if ((b_bits & 0x0e) == 0x04) | |
14159 | thumb2_insn_r->reg_rec_count = 3; | |
14160 | /* Handle VLD4. */ | |
14161 | else if (!(b_bits & 0x0e)) | |
14162 | thumb2_insn_r->reg_rec_count = 4; | |
14163 | } | |
1e1b6563 | 14164 | else |
dda83cd7 SM |
14165 | { |
14166 | /* Handle VLD1. */ | |
14167 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
14168 | thumb2_insn_r->reg_rec_count = 1; | |
14169 | /* Handle VLD2. */ | |
14170 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
14171 | thumb2_insn_r->reg_rec_count = 2; | |
14172 | /* Handle VLD3. */ | |
14173 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
14174 | thumb2_insn_r->reg_rec_count = 3; | |
14175 | /* Handle VLD4. */ | |
14176 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
14177 | thumb2_insn_r->reg_rec_count = 4; | |
14178 | ||
14179 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
14180 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
14181 | } | |
1e1b6563 OJ |
14182 | } |
14183 | ||
14184 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
14185 | { | |
14186 | record_buf[index_r] = reg_rn; | |
14187 | thumb2_insn_r->reg_rec_count += 1; | |
14188 | } | |
14189 | ||
14190 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14191 | record_buf); |
1e1b6563 | 14192 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 14193 | record_buf_mem); |
1e1b6563 OJ |
14194 | return 0; |
14195 | } | |
14196 | ||
c6ec2b30 OJ |
14197 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
14198 | ||
14199 | static unsigned int | |
4748a9be | 14200 | thumb2_record_decode_insn_handler (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
14201 | { |
14202 | uint32_t op, op1, op2; | |
14203 | ||
14204 | op = bit (thumb2_insn_r->arm_insn, 15); | |
14205 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
14206 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
14207 | ||
14208 | if (op1 == 0x01) | |
14209 | { | |
14210 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
14211 | { |
14212 | /* Load/store multiple instruction. */ | |
14213 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
14214 | } | |
b121eeb9 | 14215 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
14216 | { |
14217 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
14218 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
14219 | } | |
b121eeb9 | 14220 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
14221 | { |
14222 | /* Data-processing (shifted register). */ | |
14223 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14224 | } | |
c6ec2b30 | 14225 | else if (op2 & 0x40) |
dda83cd7 SM |
14226 | { |
14227 | /* Co-processor instructions. */ | |
14228 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14229 | } | |
c6ec2b30 OJ |
14230 | } |
14231 | else if (op1 == 0x02) | |
14232 | { | |
14233 | if (op) | |
dda83cd7 SM |
14234 | { |
14235 | /* Branches and miscellaneous control instructions. */ | |
14236 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
14237 | } | |
c6ec2b30 | 14238 | else if (op2 & 0x20) |
dda83cd7 SM |
14239 | { |
14240 | /* Data-processing (plain binary immediate) instruction. */ | |
14241 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14242 | } | |
c6ec2b30 | 14243 | else |
dda83cd7 SM |
14244 | { |
14245 | /* Data-processing (modified immediate). */ | |
14246 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14247 | } | |
c6ec2b30 OJ |
14248 | } |
14249 | else if (op1 == 0x03) | |
14250 | { | |
14251 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
14252 | { |
14253 | /* Store single data item. */ | |
14254 | return thumb2_record_str_single_data (thumb2_insn_r); | |
14255 | } | |
c6ec2b30 | 14256 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
14257 | { |
14258 | /* Advanced SIMD or structure load/store instructions. */ | |
14259 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
14260 | } | |
c6ec2b30 | 14261 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
14262 | { |
14263 | /* Load byte, memory hints instruction. */ | |
14264 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14265 | } | |
c6ec2b30 | 14266 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
14267 | { |
14268 | /* Load halfword, memory hints instruction. */ | |
14269 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14270 | } | |
c6ec2b30 | 14271 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
14272 | { |
14273 | /* Load word instruction. */ | |
14274 | return thumb2_record_ld_word (thumb2_insn_r); | |
14275 | } | |
c6ec2b30 | 14276 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
14277 | { |
14278 | /* Data-processing (register) instruction. */ | |
14279 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14280 | } | |
c6ec2b30 | 14281 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
14282 | { |
14283 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
14284 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14285 | } | |
c6ec2b30 | 14286 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
14287 | { |
14288 | /* Long multiply, long multiply accumulate, and divide. */ | |
14289 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
14290 | } | |
c6ec2b30 | 14291 | else if (op2 & 0x40) |
dda83cd7 SM |
14292 | { |
14293 | /* Co-processor instructions. */ | |
14294 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14295 | } | |
c6ec2b30 OJ |
14296 | } |
14297 | ||
14298 | return -1; | |
14299 | } | |
72508ac0 | 14300 | |
ffdbe864 | 14301 | namespace { |
0833fb8f | 14302 | /* Abstract instruction reader. */ |
728a7913 | 14303 | |
0833fb8f | 14304 | class abstract_instruction_reader |
728a7913 YQ |
14305 | { |
14306 | public: | |
0833fb8f LM |
14307 | /* Read one instruction of size LEN from address MEMADDR and using |
14308 | BYTE_ORDER endianness. */ | |
728a7913 | 14309 | |
0833fb8f LM |
14310 | virtual ULONGEST read (CORE_ADDR memaddr, const size_t len, |
14311 | enum bfd_endian byte_order) = 0; | |
728a7913 YQ |
14312 | }; |
14313 | ||
14314 | /* Instruction reader from real target. */ | |
14315 | ||
0833fb8f | 14316 | class instruction_reader : public abstract_instruction_reader |
728a7913 YQ |
14317 | { |
14318 | public: | |
0833fb8f LM |
14319 | ULONGEST read (CORE_ADDR memaddr, const size_t len, |
14320 | enum bfd_endian byte_order) override | |
728a7913 | 14321 | { |
0833fb8f | 14322 | return read_code_unsigned_integer (memaddr, len, byte_order); |
728a7913 YQ |
14323 | } |
14324 | }; | |
14325 | ||
ffdbe864 YQ |
14326 | } // namespace |
14327 | ||
4748a9be | 14328 | typedef int (*sti_arm_hdl_fp_t) (arm_insn_decode_record*); |
72508ac0 PO |
14329 | |
14330 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
14331 | dispatch it. */ | |
14332 | ||
14333 | static int | |
0833fb8f | 14334 | decode_insn (abstract_instruction_reader &reader, |
4748a9be | 14335 | arm_insn_decode_record *arm_record, |
728a7913 | 14336 | record_type_t record_type, uint32_t insn_size) |
72508ac0 PO |
14337 | { |
14338 | ||
01e57735 YQ |
14339 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
14340 | instruction. */ | |
0fa9c223 | 14341 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
14342 | { |
14343 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
14344 | arm_record_data_proc_imm, /* 001. */ | |
14345 | arm_record_ld_st_imm_offset, /* 010. */ | |
14346 | arm_record_ld_st_reg_offset, /* 011. */ | |
14347 | arm_record_ld_st_multiple, /* 100. */ | |
14348 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 14349 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
14350 | arm_record_coproc_data_proc /* 111. */ |
14351 | }; | |
14352 | ||
01e57735 YQ |
14353 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
14354 | instruction. */ | |
0fa9c223 | 14355 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
14356 | { \ |
14357 | thumb_record_shift_add_sub, /* 000. */ | |
14358 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
14359 | thumb_record_ld_st_reg_offset, /* 010. */ | |
14360 | thumb_record_ld_st_imm_offset, /* 011. */ | |
14361 | thumb_record_ld_st_stack, /* 100. */ | |
14362 | thumb_record_misc, /* 101. */ | |
14363 | thumb_record_ldm_stm_swi, /* 110. */ | |
14364 | thumb_record_branch /* 111. */ | |
14365 | }; | |
14366 | ||
14367 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
14368 | uint32_t insn_id = 0; | |
0833fb8f LM |
14369 | enum bfd_endian code_endian |
14370 | = gdbarch_byte_order_for_code (arm_record->gdbarch); | |
14371 | arm_record->arm_insn | |
14372 | = reader.read (arm_record->this_addr, insn_size, code_endian); | |
72508ac0 | 14373 | |
0833fb8f | 14374 | if (ARM_RECORD == record_type) |
72508ac0 PO |
14375 | { |
14376 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
14377 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
14378 | |
14379 | if (arm_record->cond == 0xf) | |
14380 | ret = arm_record_extension_space (arm_record); | |
14381 | else | |
01e57735 | 14382 | { |
ca92db2d YQ |
14383 | /* If this insn has fallen into extension space |
14384 | then we need not decode it anymore. */ | |
01e57735 YQ |
14385 | ret = arm_handle_insn[insn_id] (arm_record); |
14386 | } | |
ca92db2d YQ |
14387 | if (ret != ARM_RECORD_SUCCESS) |
14388 | { | |
14389 | arm_record_unsupported_insn (arm_record); | |
14390 | ret = -1; | |
14391 | } | |
72508ac0 PO |
14392 | } |
14393 | else if (THUMB_RECORD == record_type) | |
14394 | { | |
14395 | /* As thumb does not have condition codes, we set negative. */ | |
14396 | arm_record->cond = -1; | |
14397 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
14398 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
14399 | if (ret != ARM_RECORD_SUCCESS) |
14400 | { | |
14401 | arm_record_unsupported_insn (arm_record); | |
14402 | ret = -1; | |
14403 | } | |
72508ac0 PO |
14404 | } |
14405 | else if (THUMB2_RECORD == record_type) | |
14406 | { | |
c6ec2b30 OJ |
14407 | /* As thumb does not have condition codes, we set negative. */ |
14408 | arm_record->cond = -1; | |
14409 | ||
14410 | /* Swap first half of 32bit thumb instruction with second half. */ | |
14411 | arm_record->arm_insn | |
01e57735 | 14412 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 14413 | |
ca92db2d | 14414 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 14415 | |
ca92db2d | 14416 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
14417 | { |
14418 | arm_record_unsupported_insn (arm_record); | |
14419 | ret = -1; | |
14420 | } | |
72508ac0 PO |
14421 | } |
14422 | else | |
14423 | { | |
14424 | /* Throw assertion. */ | |
14425 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
14426 | } | |
14427 | ||
14428 | return ret; | |
14429 | } | |
14430 | ||
b121eeb9 YQ |
14431 | #if GDB_SELF_TEST |
14432 | namespace selftests { | |
14433 | ||
0833fb8f LM |
14434 | /* Instruction reader class for selftests. |
14435 | ||
14436 | For 16-bit Thumb instructions, an array of uint16_t should be used. | |
b121eeb9 | 14437 | |
0833fb8f LM |
14438 | For 32-bit Thumb instructions and regular 32-bit Arm instructions, an array |
14439 | of uint32_t should be used. */ | |
14440 | ||
14441 | template<typename T> | |
14442 | class instruction_reader_selftest : public abstract_instruction_reader | |
b121eeb9 YQ |
14443 | { |
14444 | public: | |
14445 | template<size_t SIZE> | |
0833fb8f LM |
14446 | instruction_reader_selftest (const T (&insns)[SIZE]) |
14447 | : m_insns (insns), m_insns_size (SIZE) | |
b121eeb9 YQ |
14448 | {} |
14449 | ||
0833fb8f LM |
14450 | ULONGEST read (CORE_ADDR memaddr, const size_t length, |
14451 | enum bfd_endian byte_order) override | |
b121eeb9 | 14452 | { |
0833fb8f LM |
14453 | SELF_CHECK (length == sizeof (T)); |
14454 | SELF_CHECK (memaddr % sizeof (T) == 0); | |
14455 | SELF_CHECK ((memaddr / sizeof (T)) < m_insns_size); | |
b121eeb9 | 14456 | |
0833fb8f | 14457 | return m_insns[memaddr / sizeof (T)]; |
b121eeb9 YQ |
14458 | } |
14459 | ||
14460 | private: | |
0833fb8f LM |
14461 | const T *m_insns; |
14462 | const size_t m_insns_size; | |
b121eeb9 YQ |
14463 | }; |
14464 | ||
14465 | static void | |
14466 | arm_record_test (void) | |
14467 | { | |
14468 | struct gdbarch_info info; | |
b121eeb9 YQ |
14469 | info.bfd_arch_info = bfd_scan_arch ("arm"); |
14470 | ||
14471 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14472 | ||
14473 | SELF_CHECK (gdbarch != NULL); | |
14474 | ||
14475 | /* 16-bit Thumb instructions. */ | |
14476 | { | |
4748a9be | 14477 | arm_insn_decode_record arm_record; |
b121eeb9 | 14478 | |
4748a9be | 14479 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14480 | arm_record.gdbarch = gdbarch; |
14481 | ||
0833fb8f LM |
14482 | /* Use the endian-free representation of the instructions here. The test |
14483 | will handle endianness conversions. */ | |
b121eeb9 YQ |
14484 | static const uint16_t insns[] = { |
14485 | /* db b2 uxtb r3, r3 */ | |
14486 | 0xb2db, | |
14487 | /* cd 58 ldr r5, [r1, r3] */ | |
14488 | 0x58cd, | |
14489 | }; | |
14490 | ||
0833fb8f | 14491 | instruction_reader_selftest<uint16_t> reader (insns); |
b121eeb9 YQ |
14492 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
14493 | THUMB_INSN_SIZE_BYTES); | |
14494 | ||
14495 | SELF_CHECK (ret == 0); | |
14496 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14497 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14498 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
14499 | ||
14500 | arm_record.this_addr += 2; | |
14501 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
14502 | THUMB_INSN_SIZE_BYTES); | |
14503 | ||
14504 | SELF_CHECK (ret == 0); | |
14505 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14506 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14507 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
14508 | } | |
14509 | ||
14510 | /* 32-bit Thumb-2 instructions. */ | |
14511 | { | |
4748a9be | 14512 | arm_insn_decode_record arm_record; |
b121eeb9 | 14513 | |
4748a9be | 14514 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14515 | arm_record.gdbarch = gdbarch; |
14516 | ||
0833fb8f LM |
14517 | /* Use the endian-free representation of the instruction here. The test |
14518 | will handle endianness conversions. */ | |
14519 | static const uint32_t insns[] = { | |
14520 | /* mrc 15, 0, r7, cr13, cr0, {3} */ | |
14521 | 0x7f70ee1d, | |
b121eeb9 YQ |
14522 | }; |
14523 | ||
0833fb8f | 14524 | instruction_reader_selftest<uint32_t> reader (insns); |
b121eeb9 YQ |
14525 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
14526 | THUMB2_INSN_SIZE_BYTES); | |
14527 | ||
14528 | SELF_CHECK (ret == 0); | |
14529 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14530 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14531 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
14532 | } | |
0833fb8f LM |
14533 | |
14534 | /* 32-bit instructions. */ | |
14535 | { | |
14536 | arm_insn_decode_record arm_record; | |
14537 | ||
14538 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); | |
14539 | arm_record.gdbarch = gdbarch; | |
14540 | ||
14541 | /* Use the endian-free representation of the instruction here. The test | |
14542 | will handle endianness conversions. */ | |
14543 | static const uint32_t insns[] = { | |
14544 | /* mov r5, r0 */ | |
14545 | 0xe1a05000, | |
14546 | }; | |
14547 | ||
14548 | instruction_reader_selftest<uint32_t> reader (insns); | |
14549 | int ret = decode_insn (reader, &arm_record, ARM_RECORD, | |
14550 | ARM_INSN_SIZE_BYTES); | |
14551 | ||
14552 | SELF_CHECK (ret == 0); | |
14553 | } | |
b121eeb9 | 14554 | } |
9ecab40c SM |
14555 | |
14556 | /* Instruction reader from manually cooked instruction sequences. */ | |
14557 | ||
14558 | class test_arm_instruction_reader : public arm_instruction_reader | |
14559 | { | |
14560 | public: | |
14561 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
14562 | : m_insns (insns) | |
14563 | {} | |
14564 | ||
14565 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
14566 | { | |
14567 | SELF_CHECK (memaddr % 4 == 0); | |
14568 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
14569 | ||
14570 | return m_insns[memaddr / 4]; | |
14571 | } | |
14572 | ||
14573 | private: | |
14574 | const gdb::array_view<const uint32_t> m_insns; | |
14575 | }; | |
14576 | ||
14577 | static void | |
14578 | arm_analyze_prologue_test () | |
14579 | { | |
14580 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
14581 | { | |
14582 | struct gdbarch_info info; | |
9ecab40c SM |
14583 | info.byte_order = endianness; |
14584 | info.byte_order_for_code = endianness; | |
14585 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
14586 | ||
14587 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14588 | ||
14589 | SELF_CHECK (gdbarch != NULL); | |
14590 | ||
14591 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
14592 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
14593 | UBSan. */ | |
14594 | const uint32_t insns[] = { | |
14595 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
14596 | 0xe1a05000, /* mov r5, r0 */ | |
14597 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
14598 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
14599 | }; | |
14600 | ||
14601 | test_arm_instruction_reader mem_reader (insns); | |
14602 | arm_prologue_cache cache; | |
0824193f | 14603 | arm_cache_init (&cache, gdbarch); |
9ecab40c SM |
14604 | |
14605 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
14606 | } | |
14607 | } | |
14608 | ||
b121eeb9 YQ |
14609 | } // namespace selftests |
14610 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
14611 | |
14612 | /* Cleans up local record registers and memory allocations. */ | |
14613 | ||
14614 | static void | |
4748a9be | 14615 | deallocate_reg_mem (arm_insn_decode_record *record) |
72508ac0 PO |
14616 | { |
14617 | xfree (record->arm_regs); | |
14618 | xfree (record->arm_mems); | |
14619 | } | |
14620 | ||
14621 | ||
01e57735 | 14622 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
14623 | memory that will be changed in current instruction to record_arch_list". |
14624 | Return -1 if something is wrong. */ | |
14625 | ||
14626 | int | |
01e57735 YQ |
14627 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
14628 | CORE_ADDR insn_addr) | |
72508ac0 PO |
14629 | { |
14630 | ||
72508ac0 PO |
14631 | uint32_t no_of_rec = 0; |
14632 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
14633 | ULONGEST t_bit = 0, insn_id = 0; | |
14634 | ||
14635 | ULONGEST u_regval = 0; | |
14636 | ||
4748a9be | 14637 | arm_insn_decode_record arm_record; |
72508ac0 | 14638 | |
4748a9be | 14639 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
72508ac0 PO |
14640 | arm_record.regcache = regcache; |
14641 | arm_record.this_addr = insn_addr; | |
14642 | arm_record.gdbarch = gdbarch; | |
14643 | ||
14644 | ||
14645 | if (record_debug > 1) | |
14646 | { | |
6cb06a8c TT |
14647 | gdb_printf (gdb_stdlog, "Process record: arm_process_record " |
14648 | "addr = %s\n", | |
14649 | paddress (gdbarch, arm_record.this_addr)); | |
72508ac0 PO |
14650 | } |
14651 | ||
728a7913 | 14652 | instruction_reader reader; |
0833fb8f LM |
14653 | enum bfd_endian code_endian |
14654 | = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
14655 | arm_record.arm_insn | |
14656 | = reader.read (arm_record.this_addr, 2, code_endian); | |
72508ac0 PO |
14657 | |
14658 | /* Check the insn, whether it is thumb or arm one. */ | |
14659 | ||
14660 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
14661 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
14662 | ||
14663 | ||
14664 | if (!(u_regval & t_bit)) | |
14665 | { | |
14666 | /* We are decoding arm insn. */ | |
728a7913 | 14667 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
14668 | } |
14669 | else | |
14670 | { | |
14671 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
14672 | /* is it thumb2 insn? */ | |
14673 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 14674 | { |
728a7913 | 14675 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
14676 | THUMB2_INSN_SIZE_BYTES); |
14677 | } | |
72508ac0 | 14678 | else |
01e57735 YQ |
14679 | { |
14680 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
14681 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
14682 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 14683 | } |
72508ac0 PO |
14684 | } |
14685 | ||
14686 | if (0 == ret) | |
14687 | { | |
14688 | /* Record registers. */ | |
25ea693b | 14689 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 14690 | if (arm_record.arm_regs) |
01e57735 YQ |
14691 | { |
14692 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
14693 | { | |
14694 | if (record_full_arch_list_add_reg | |
25ea693b | 14695 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
14696 | ret = -1; |
14697 | } | |
14698 | } | |
72508ac0 PO |
14699 | /* Record memories. */ |
14700 | if (arm_record.arm_mems) | |
01e57735 YQ |
14701 | { |
14702 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
14703 | { | |
14704 | if (record_full_arch_list_add_mem | |
14705 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 14706 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
14707 | ret = -1; |
14708 | } | |
14709 | } | |
72508ac0 | 14710 | |
25ea693b | 14711 | if (record_full_arch_list_add_end ()) |
01e57735 | 14712 | ret = -1; |
72508ac0 PO |
14713 | } |
14714 | ||
14715 | ||
14716 | deallocate_reg_mem (&arm_record); | |
14717 | ||
14718 | return ret; | |
14719 | } | |
d105cce5 AH |
14720 | |
14721 | /* See arm-tdep.h. */ | |
14722 | ||
14723 | const target_desc * | |
92d48a1e | 14724 | arm_read_description (arm_fp_type fp_type, bool tls) |
d105cce5 | 14725 | { |
92d48a1e | 14726 | struct target_desc *tdesc = tdesc_arm_list[fp_type][tls]; |
d105cce5 AH |
14727 | |
14728 | if (tdesc == nullptr) | |
14729 | { | |
92d48a1e JB |
14730 | tdesc = arm_create_target_description (fp_type, tls); |
14731 | tdesc_arm_list[fp_type][tls] = tdesc; | |
d105cce5 AH |
14732 | } |
14733 | ||
14734 | return tdesc; | |
14735 | } | |
14736 | ||
14737 | /* See arm-tdep.h. */ | |
14738 | ||
14739 | const target_desc * | |
14740 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
14741 | { | |
14742 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
14743 | ||
14744 | if (tdesc == nullptr) | |
14745 | { | |
14746 | tdesc = arm_create_mprofile_target_description (m_type); | |
14747 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
14748 | } | |
14749 | ||
14750 | return tdesc; | |
14751 | } |