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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
4a94e368 | 3 | Copyright (C) 1988-2022 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
a01567f4 | 41 | #include "dwarf2.h" |
82ca8957 | 42 | #include "dwarf2/frame.h" |
4de283e4 TT |
43 | #include "gdbtypes.h" |
44 | #include "prologue-value.h" | |
45 | #include "remote.h" | |
46 | #include "target-descriptions.h" | |
47 | #include "user-regs.h" | |
48 | #include "observable.h" | |
5f661e03 | 49 | #include "count-one-bits.h" |
4de283e4 | 50 | |
d55e5aa6 | 51 | #include "arch/arm.h" |
4de283e4 | 52 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 53 | #include "arm-tdep.h" |
4de283e4 TT |
54 | #include "gdb/sim-arm.h" |
55 | ||
d55e5aa6 | 56 | #include "elf-bfd.h" |
4de283e4 | 57 | #include "coff/internal.h" |
d55e5aa6 | 58 | #include "elf/arm.h" |
4de283e4 | 59 | |
4de283e4 TT |
60 | #include "record.h" |
61 | #include "record-full.h" | |
62 | #include <algorithm> | |
63 | ||
c2fd7fae AKS |
64 | #include "producer.h" |
65 | ||
b121eeb9 | 66 | #if GDB_SELF_TEST |
268a13a5 | 67 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
68 | #endif |
69 | ||
491144b5 | 70 | static bool arm_debug; |
6529d2dd | 71 | |
7cb6d92a SM |
72 | /* Print an "arm" debug statement. */ |
73 | ||
74 | #define arm_debug_printf(fmt, ...) \ | |
75 | debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__) | |
76 | ||
082fc60d RE |
77 | /* Macros for setting and testing a bit in a minimal symbol that marks |
78 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 79 | is used for this purpose. |
082fc60d RE |
80 | |
81 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 82 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 83 | |
0963b4bd | 84 | #define MSYMBOL_SET_SPECIAL(msym) \ |
e165fcef | 85 | (msym)->set_target_flag_1 (true) |
082fc60d RE |
86 | |
87 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
e165fcef | 88 | (msym)->target_flag_1 () |
082fc60d | 89 | |
60c5725c DJ |
90 | struct arm_mapping_symbol |
91 | { | |
227031b2 | 92 | CORE_ADDR value; |
60c5725c | 93 | char type; |
54cc7474 SM |
94 | |
95 | bool operator< (const arm_mapping_symbol &other) const | |
96 | { return this->value < other.value; } | |
60c5725c | 97 | }; |
54cc7474 SM |
98 | |
99 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 100 | |
bd5766ec | 101 | struct arm_per_bfd |
60c5725c | 102 | { |
bd5766ec | 103 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
104 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
105 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
106 | {} |
107 | ||
bd5766ec | 108 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
109 | |
110 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
111 | ||
112 | The format is an array of vectors of arm_mapping_symbols, there is one | |
113 | vector for each section of the objfile (the array is index by BFD section | |
114 | index). | |
115 | ||
116 | For each section, the vector of arm_mapping_symbol is sorted by | |
117 | symbol value (address). */ | |
118 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
119 | |
120 | /* For each corresponding element of section_maps above, is this vector | |
121 | sorted. */ | |
122 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
123 | }; |
124 | ||
bd5766ec | 125 | /* Per-bfd data used for mapping symbols. */ |
08b8a139 | 126 | static const registry<bfd>::key<arm_per_bfd> arm_bfd_data_key; |
1b7f24cd | 127 | |
afd7eef0 RE |
128 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
129 | static struct cmd_list_element *setarmcmdlist = NULL; | |
130 | static struct cmd_list_element *showarmcmdlist = NULL; | |
131 | ||
fd50bc42 RE |
132 | /* The type of floating-point to use. Keep this in sync with enum |
133 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 134 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
135 | { |
136 | "auto", | |
137 | "softfpa", | |
138 | "fpa", | |
139 | "softvfp", | |
28e97307 DJ |
140 | "vfp", |
141 | NULL | |
fd50bc42 RE |
142 | }; |
143 | ||
144 | /* A variable that can be configured by the user. */ | |
145 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
146 | static const char *current_fp_model = "auto"; | |
147 | ||
28e97307 | 148 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 149 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
150 | { |
151 | "auto", | |
152 | "APCS", | |
153 | "AAPCS", | |
154 | NULL | |
155 | }; | |
156 | ||
157 | /* A variable that can be configured by the user. */ | |
158 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
159 | static const char *arm_abi_string = "auto"; | |
160 | ||
0428b8f5 | 161 | /* The execution mode to assume. */ |
40478521 | 162 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
163 | { |
164 | "auto", | |
165 | "arm", | |
68770265 MGD |
166 | "thumb", |
167 | NULL | |
0428b8f5 DJ |
168 | }; |
169 | ||
170 | static const char *arm_fallback_mode_string = "auto"; | |
171 | static const char *arm_force_mode_string = "auto"; | |
172 | ||
f32bf4a4 YQ |
173 | /* The standard register names, and all the valid aliases for them. Note |
174 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
175 | have been added as builtin user registers in | |
176 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
177 | static const struct |
178 | { | |
179 | const char *name; | |
180 | int regnum; | |
181 | } arm_register_aliases[] = { | |
182 | /* Basic register numbers. */ | |
183 | { "r0", 0 }, | |
184 | { "r1", 1 }, | |
185 | { "r2", 2 }, | |
186 | { "r3", 3 }, | |
187 | { "r4", 4 }, | |
188 | { "r5", 5 }, | |
189 | { "r6", 6 }, | |
190 | { "r7", 7 }, | |
191 | { "r8", 8 }, | |
192 | { "r9", 9 }, | |
193 | { "r10", 10 }, | |
194 | { "r11", 11 }, | |
195 | { "r12", 12 }, | |
196 | { "r13", 13 }, | |
197 | { "r14", 14 }, | |
198 | { "r15", 15 }, | |
199 | /* Synonyms (argument and variable registers). */ | |
200 | { "a1", 0 }, | |
201 | { "a2", 1 }, | |
202 | { "a3", 2 }, | |
203 | { "a4", 3 }, | |
204 | { "v1", 4 }, | |
205 | { "v2", 5 }, | |
206 | { "v3", 6 }, | |
207 | { "v4", 7 }, | |
208 | { "v5", 8 }, | |
209 | { "v6", 9 }, | |
210 | { "v7", 10 }, | |
211 | { "v8", 11 }, | |
212 | /* Other platform-specific names for r9. */ | |
213 | { "sb", 9 }, | |
214 | { "tr", 9 }, | |
215 | /* Special names. */ | |
216 | { "ip", 12 }, | |
123dc839 | 217 | { "lr", 14 }, |
123dc839 DJ |
218 | /* Names used by GCC (not listed in the ARM EABI). */ |
219 | { "sl", 10 }, | |
123dc839 DJ |
220 | /* A special name from the older ATPCS. */ |
221 | { "wr", 7 }, | |
222 | }; | |
bc90b915 | 223 | |
123dc839 | 224 | static const char *const arm_register_names[] = |
da59e081 JM |
225 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
226 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
227 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
228 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
229 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
230 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 231 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 232 | |
65b48a81 PB |
233 | /* Holds the current set of options to be passed to the disassembler. */ |
234 | static char *arm_disassembler_options; | |
235 | ||
afd7eef0 RE |
236 | /* Valid register name styles. */ |
237 | static const char **valid_disassembly_styles; | |
ed9a39eb | 238 | |
afd7eef0 RE |
239 | /* Disassembly style to use. Default to "std" register names. */ |
240 | static const char *disassembly_style; | |
96baa820 | 241 | |
d105cce5 | 242 | /* All possible arm target descriptors. */ |
92d48a1e | 243 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID][2]; |
d105cce5 AH |
244 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; |
245 | ||
ed9a39eb | 246 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 247 | style. */ |
eb4c3f4a | 248 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 249 | struct cmd_list_element *); |
65b48a81 PB |
250 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
251 | struct cmd_list_element *, | |
252 | const char *); | |
ed9a39eb | 253 | |
05d1431c | 254 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 255 | readable_regcache *regcache, |
05d1431c | 256 | int regnum, gdb_byte *buf); |
58d6951d DJ |
257 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
258 | struct regcache *regcache, | |
259 | int regnum, const gdb_byte *buf); | |
260 | ||
e7cf25a8 | 261 | static CORE_ADDR |
553cb527 | 262 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
263 | |
264 | ||
d9311bfa AT |
265 | /* get_next_pcs operations. */ |
266 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
267 | arm_get_next_pcs_read_memory_unsigned_integer, | |
268 | arm_get_next_pcs_syscall_next_pc, | |
269 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
270 | arm_get_next_pcs_is_thumb, |
271 | NULL, | |
d9311bfa AT |
272 | }; |
273 | ||
9b8d791a | 274 | struct arm_prologue_cache |
c3b4394c | 275 | { |
eb5492fa DJ |
276 | /* The stack pointer at the time this frame was created; i.e. the |
277 | caller's stack pointer when this function was called. It is used | |
278 | to identify this frame. */ | |
ae7e2f45 CL |
279 | CORE_ADDR sp; |
280 | ||
281 | /* Additional stack pointers used by M-profile with Security extension. */ | |
282 | /* Use msp_s / psp_s to hold the values of msp / psp when there is | |
283 | no Security extension. */ | |
284 | CORE_ADDR msp_s; | |
285 | CORE_ADDR msp_ns; | |
286 | CORE_ADDR psp_s; | |
287 | CORE_ADDR psp_ns; | |
288 | ||
289 | /* Active stack pointer. */ | |
290 | int active_sp_regnum; | |
0d12d61b YR |
291 | int active_msp_regnum; |
292 | int active_psp_regnum; | |
eb5492fa | 293 | |
4be43953 DJ |
294 | /* The frame base for this frame is just prev_sp - frame size. |
295 | FRAMESIZE is the distance from the frame pointer to the | |
296 | initial stack pointer. */ | |
eb5492fa | 297 | |
c3b4394c | 298 | int framesize; |
eb5492fa DJ |
299 | |
300 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 301 | int framereg; |
eb5492fa | 302 | |
a01567f4 LM |
303 | /* True if the return address is signed, false otherwise. */ |
304 | gdb::optional<bool> ra_signed_state; | |
305 | ||
eb5492fa | 306 | /* Saved register offsets. */ |
098caef4 | 307 | trad_frame_saved_reg *saved_regs; |
0824193f CL |
308 | |
309 | arm_prologue_cache() = default; | |
c3b4394c | 310 | }; |
ed9a39eb | 311 | |
8c9ae6df YR |
312 | |
313 | /* Reconstruct T bit in program status register from LR value. */ | |
314 | ||
315 | static inline ULONGEST | |
316 | reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) | |
317 | { | |
318 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
319 | if (IS_THUMB_ADDR (lr)) | |
320 | psr |= t_bit; | |
321 | else | |
322 | psr &= ~t_bit; | |
323 | ||
324 | return psr; | |
325 | } | |
326 | ||
0824193f CL |
327 | /* Initialize CACHE fields for which zero is not adequate (CACHE is |
328 | expected to have been ZALLOC'ed before calling this function). */ | |
329 | ||
330 | static void | |
331 | arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch) | |
332 | { | |
ae7e2f45 CL |
333 | cache->active_sp_regnum = ARM_SP_REGNUM; |
334 | ||
0824193f CL |
335 | cache->saved_regs = trad_frame_alloc_saved_regs (gdbarch); |
336 | } | |
337 | ||
338 | /* Similar to the previous function, but extracts GDBARCH from FRAME. */ | |
339 | ||
340 | static void | |
bd2b40ac | 341 | arm_cache_init (struct arm_prologue_cache *cache, frame_info_ptr frame) |
0824193f CL |
342 | { |
343 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 344 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0824193f CL |
345 | |
346 | arm_cache_init (cache, gdbarch); | |
fe642a5b | 347 | cache->sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
ae7e2f45 CL |
348 | |
349 | if (tdep->have_sec_ext) | |
350 | { | |
b0b23e06 TS |
351 | const CORE_ADDR msp_val |
352 | = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); | |
353 | const CORE_ADDR psp_val | |
354 | = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); | |
355 | ||
356 | cache->msp_s | |
357 | = get_frame_register_unsigned (frame, tdep->m_profile_msp_s_regnum); | |
358 | cache->msp_ns | |
359 | = get_frame_register_unsigned (frame, tdep->m_profile_msp_ns_regnum); | |
360 | cache->psp_s | |
361 | = get_frame_register_unsigned (frame, tdep->m_profile_psp_s_regnum); | |
362 | cache->psp_ns | |
363 | = get_frame_register_unsigned (frame, tdep->m_profile_psp_ns_regnum); | |
364 | ||
365 | /* Identify what msp is alias for (msp_s or msp_ns). */ | |
0d12d61b YR |
366 | if (msp_val == cache->msp_s) |
367 | cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; | |
368 | else if (msp_val == cache->msp_ns) | |
369 | cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; | |
b0b23e06 TS |
370 | else |
371 | { | |
372 | warning (_("Invalid state, unable to determine msp alias, assuming " | |
373 | "msp_s.")); | |
374 | cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; | |
375 | } | |
376 | ||
377 | /* Identify what psp is alias for (psp_s or psp_ns). */ | |
0d12d61b YR |
378 | if (psp_val == cache->psp_s) |
379 | cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; | |
380 | else if (psp_val == cache->psp_ns) | |
381 | cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; | |
b0b23e06 TS |
382 | else |
383 | { | |
384 | warning (_("Invalid state, unable to determine psp alias, assuming " | |
385 | "psp_s.")); | |
386 | cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; | |
387 | } | |
388 | ||
389 | /* Identify what sp is alias for (msp_s, msp_ns, psp_s or psp_ns). */ | |
390 | if (msp_val == cache->sp) | |
391 | cache->active_sp_regnum = cache->active_msp_regnum; | |
392 | else if (psp_val == cache->sp) | |
393 | cache->active_sp_regnum = cache->active_psp_regnum; | |
394 | else | |
395 | { | |
396 | warning (_("Invalid state, unable to determine sp alias, assuming " | |
397 | "msp.")); | |
398 | cache->active_sp_regnum = cache->active_msp_regnum; | |
399 | } | |
ae7e2f45 CL |
400 | } |
401 | else if (tdep->is_m) | |
402 | { | |
b0b23e06 | 403 | cache->msp_s |
f3f7ecc9 | 404 | = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); |
b0b23e06 | 405 | cache->psp_s |
f3f7ecc9 | 406 | = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); |
b0b23e06 TS |
407 | |
408 | /* Identify what sp is alias for (msp or psp). */ | |
409 | if (cache->msp_s == cache->sp) | |
410 | cache->active_sp_regnum = tdep->m_profile_msp_regnum; | |
411 | else if (cache->psp_s == cache->sp) | |
412 | cache->active_sp_regnum = tdep->m_profile_psp_regnum; | |
413 | else | |
414 | { | |
415 | warning (_("Invalid state, unable to determine sp alias, assuming " | |
416 | "msp.")); | |
417 | cache->active_sp_regnum = tdep->m_profile_msp_regnum; | |
418 | } | |
ae7e2f45 CL |
419 | } |
420 | else | |
b0b23e06 TS |
421 | { |
422 | cache->msp_s | |
423 | = get_frame_register_unsigned (frame, ARM_SP_REGNUM); | |
424 | ||
425 | cache->active_sp_regnum = ARM_SP_REGNUM; | |
426 | } | |
ae7e2f45 CL |
427 | } |
428 | ||
429 | /* Return the requested stack pointer value (in REGNUM), taking into | |
430 | account whether we have a Security extension or an M-profile | |
431 | CPU. */ | |
432 | ||
433 | static CORE_ADDR | |
434 | arm_cache_get_sp_register (struct arm_prologue_cache *cache, | |
435 | arm_gdbarch_tdep *tdep, int regnum) | |
436 | { | |
ae7e2f45 CL |
437 | if (tdep->have_sec_ext) |
438 | { | |
439 | if (regnum == tdep->m_profile_msp_s_regnum) | |
440 | return cache->msp_s; | |
441 | if (regnum == tdep->m_profile_msp_ns_regnum) | |
442 | return cache->msp_ns; | |
443 | if (regnum == tdep->m_profile_psp_s_regnum) | |
444 | return cache->psp_s; | |
445 | if (regnum == tdep->m_profile_psp_ns_regnum) | |
446 | return cache->psp_ns; | |
0d12d61b YR |
447 | if (regnum == tdep->m_profile_msp_regnum) |
448 | return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); | |
449 | if (regnum == tdep->m_profile_psp_regnum) | |
450 | return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); | |
b9b66a3a YR |
451 | if (regnum == ARM_SP_REGNUM) |
452 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 CL |
453 | } |
454 | else if (tdep->is_m) | |
455 | { | |
456 | if (regnum == tdep->m_profile_msp_regnum) | |
457 | return cache->msp_s; | |
458 | if (regnum == tdep->m_profile_psp_regnum) | |
459 | return cache->psp_s; | |
b9b66a3a YR |
460 | if (regnum == ARM_SP_REGNUM) |
461 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 | 462 | } |
b9b66a3a YR |
463 | else if (regnum == ARM_SP_REGNUM) |
464 | return cache->sp; | |
ae7e2f45 CL |
465 | |
466 | gdb_assert_not_reached ("Invalid SP selection"); | |
467 | } | |
468 | ||
469 | /* Return the previous stack address, depending on which SP register | |
470 | is active. */ | |
471 | ||
472 | static CORE_ADDR | |
473 | arm_cache_get_prev_sp_value (struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep) | |
474 | { | |
475 | CORE_ADDR val = arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
476 | return val; | |
477 | } | |
478 | ||
479 | /* Set the active stack pointer to VAL. */ | |
480 | ||
481 | static void | |
482 | arm_cache_set_active_sp_value (struct arm_prologue_cache *cache, | |
483 | arm_gdbarch_tdep *tdep, CORE_ADDR val) | |
484 | { | |
ae7e2f45 CL |
485 | if (tdep->have_sec_ext) |
486 | { | |
487 | if (cache->active_sp_regnum == tdep->m_profile_msp_s_regnum) | |
488 | cache->msp_s = val; | |
489 | else if (cache->active_sp_regnum == tdep->m_profile_msp_ns_regnum) | |
490 | cache->msp_ns = val; | |
491 | else if (cache->active_sp_regnum == tdep->m_profile_psp_s_regnum) | |
492 | cache->psp_s = val; | |
493 | else if (cache->active_sp_regnum == tdep->m_profile_psp_ns_regnum) | |
494 | cache->psp_ns = val; | |
495 | ||
496 | return; | |
497 | } | |
498 | else if (tdep->is_m) | |
499 | { | |
500 | if (cache->active_sp_regnum == tdep->m_profile_msp_regnum) | |
501 | cache->msp_s = val; | |
502 | else if (cache->active_sp_regnum == tdep->m_profile_psp_regnum) | |
503 | cache->psp_s = val; | |
504 | ||
505 | return; | |
506 | } | |
b9b66a3a YR |
507 | else if (cache->active_sp_regnum == ARM_SP_REGNUM) |
508 | { | |
509 | cache->sp = val; | |
510 | return; | |
511 | } | |
ae7e2f45 CL |
512 | |
513 | gdb_assert_not_reached ("Invalid SP selection"); | |
0824193f CL |
514 | } |
515 | ||
d65edaa0 | 516 | /* Return true if REGNUM is one of the alternative stack pointers. */ |
ef273377 CL |
517 | |
518 | static bool | |
d65edaa0 | 519 | arm_is_alternative_sp_register (arm_gdbarch_tdep *tdep, int regnum) |
ef273377 | 520 | { |
d65edaa0 | 521 | if ((regnum == tdep->m_profile_msp_regnum) |
ef273377 CL |
522 | || (regnum == tdep->m_profile_msp_s_regnum) |
523 | || (regnum == tdep->m_profile_msp_ns_regnum) | |
524 | || (regnum == tdep->m_profile_psp_regnum) | |
525 | || (regnum == tdep->m_profile_psp_s_regnum) | |
526 | || (regnum == tdep->m_profile_psp_ns_regnum)) | |
527 | return true; | |
528 | else | |
529 | return false; | |
530 | } | |
531 | ||
532 | /* Set the active stack pointer to SP_REGNUM. */ | |
533 | ||
534 | static void | |
535 | arm_cache_switch_prev_sp (struct arm_prologue_cache *cache, | |
536 | arm_gdbarch_tdep *tdep, int sp_regnum) | |
537 | { | |
d65edaa0 | 538 | gdb_assert (arm_is_alternative_sp_register (tdep, sp_regnum)); |
ef273377 CL |
539 | |
540 | if (tdep->have_sec_ext) | |
4d9fd868 TS |
541 | { |
542 | gdb_assert (sp_regnum != tdep->m_profile_msp_regnum | |
543 | && sp_regnum != tdep->m_profile_psp_regnum); | |
544 | ||
545 | if (sp_regnum == tdep->m_profile_msp_s_regnum | |
546 | || sp_regnum == tdep->m_profile_psp_s_regnum) | |
547 | { | |
548 | cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; | |
549 | cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; | |
550 | } | |
551 | else if (sp_regnum == tdep->m_profile_msp_ns_regnum | |
552 | || sp_regnum == tdep->m_profile_psp_ns_regnum) | |
553 | { | |
554 | cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; | |
555 | cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; | |
556 | } | |
557 | } | |
ef273377 CL |
558 | |
559 | cache->active_sp_regnum = sp_regnum; | |
560 | } | |
561 | ||
9ecab40c SM |
562 | namespace { |
563 | ||
564 | /* Abstract class to read ARM instructions from memory. */ | |
565 | ||
566 | class arm_instruction_reader | |
567 | { | |
568 | public: | |
2c5b1849 | 569 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
570 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
571 | }; | |
572 | ||
573 | /* Read instructions from target memory. */ | |
574 | ||
575 | class target_arm_instruction_reader : public arm_instruction_reader | |
576 | { | |
577 | public: | |
578 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
579 | { | |
580 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
581 | } | |
582 | }; | |
583 | ||
584 | } /* namespace */ | |
585 | ||
586 | static CORE_ADDR arm_analyze_prologue | |
587 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
588 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 589 | |
cca44b1b JB |
590 | /* Architecture version for displaced stepping. This effects the behaviour of |
591 | certain instructions, and really should not be hard-wired. */ | |
592 | ||
593 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
594 | ||
c7ae7675 | 595 | /* See arm-tdep.h. */ |
c906108c | 596 | |
491144b5 | 597 | bool arm_apcs_32 = true; |
ef273377 | 598 | bool arm_unwind_secure_frames = true; |
c906108c | 599 | |
9779414d DJ |
600 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
601 | ||
478fd957 | 602 | int |
9779414d DJ |
603 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
604 | { | |
08106042 | 605 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
606 | |
607 | if (tdep->is_m) | |
9779414d DJ |
608 | return XPSR_T; |
609 | else | |
610 | return CPSR_T; | |
611 | } | |
612 | ||
d0e59a68 AT |
613 | /* Determine if the processor is currently executing in Thumb mode. */ |
614 | ||
615 | int | |
616 | arm_is_thumb (struct regcache *regcache) | |
617 | { | |
618 | ULONGEST cpsr; | |
ac7936df | 619 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
620 | |
621 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
622 | ||
623 | return (cpsr & t_bit) != 0; | |
624 | } | |
625 | ||
60270718 AB |
626 | /* Determine if FRAME is executing in Thumb mode. FRAME must be an ARM |
627 | frame. */ | |
b39cc962 | 628 | |
25b41d01 | 629 | int |
bd2b40ac | 630 | arm_frame_is_thumb (frame_info_ptr frame) |
b39cc962 | 631 | { |
60270718 AB |
632 | /* Check the architecture of FRAME. */ |
633 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
634 | gdb_assert (gdbarch_bfd_arch_info (gdbarch)->arch == bfd_arch_arm); | |
b39cc962 DJ |
635 | |
636 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
637 | directly (from a signal frame or dummy frame) or by interpreting | |
638 | the saved LR (from a prologue or DWARF frame). So consult it and | |
639 | trust the unwinders. */ | |
60270718 | 640 | CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
b39cc962 | 641 | |
60270718 AB |
642 | /* Find and extract the thumb bit. */ |
643 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
9779414d | 644 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
645 | } |
646 | ||
f9d67f43 DJ |
647 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
648 | return its type. Otherwise, return 0. If START is non-NULL, | |
649 | set *START to the location of the mapping symbol. */ | |
c906108c | 650 | |
f9d67f43 DJ |
651 | static char |
652 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 653 | { |
60c5725c | 654 | struct obj_section *sec; |
0428b8f5 | 655 | |
60c5725c DJ |
656 | /* If there are mapping symbols, consult them. */ |
657 | sec = find_pc_section (memaddr); | |
658 | if (sec != NULL) | |
659 | { | |
98badbfd | 660 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd.get ()); |
60c5725c DJ |
661 | if (data != NULL) |
662 | { | |
4838e44c SM |
663 | unsigned int section_idx = sec->the_bfd_section->index; |
664 | arm_mapping_symbol_vec &map | |
665 | = data->section_maps[section_idx]; | |
666 | ||
667 | /* Sort the vector on first use. */ | |
668 | if (!data->section_maps_sorted[section_idx]) | |
669 | { | |
670 | std::sort (map.begin (), map.end ()); | |
671 | data->section_maps_sorted[section_idx] = true; | |
672 | } | |
673 | ||
0c1bcd23 | 674 | arm_mapping_symbol map_key = { memaddr - sec->addr (), 0 }; |
54cc7474 SM |
675 | arm_mapping_symbol_vec::const_iterator it |
676 | = std::lower_bound (map.begin (), map.end (), map_key); | |
677 | ||
678 | /* std::lower_bound finds the earliest ordered insertion | |
679 | point. If the symbol at this position starts at this exact | |
680 | address, we use that; otherwise, the preceding | |
681 | mapping symbol covers this address. */ | |
682 | if (it < map.end ()) | |
60c5725c | 683 | { |
54cc7474 | 684 | if (it->value == map_key.value) |
60c5725c | 685 | { |
f9d67f43 | 686 | if (start) |
0c1bcd23 | 687 | *start = it->value + sec->addr (); |
54cc7474 | 688 | return it->type; |
60c5725c DJ |
689 | } |
690 | } | |
54cc7474 SM |
691 | |
692 | if (it > map.begin ()) | |
693 | { | |
694 | arm_mapping_symbol_vec::const_iterator prev_it | |
695 | = it - 1; | |
696 | ||
697 | if (start) | |
0c1bcd23 | 698 | *start = prev_it->value + sec->addr (); |
54cc7474 SM |
699 | return prev_it->type; |
700 | } | |
60c5725c DJ |
701 | } |
702 | } | |
703 | ||
f9d67f43 DJ |
704 | return 0; |
705 | } | |
706 | ||
707 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
708 | function. This function should be called for addresses unrelated to | |
709 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
710 | ||
e3039479 | 711 | int |
9779414d | 712 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 713 | { |
7cbd4a93 | 714 | struct bound_minimal_symbol sym; |
f9d67f43 | 715 | char type; |
187b041e | 716 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
08106042 | 717 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
187b041e SM |
718 | |
719 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
720 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
721 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
722 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
723 | |
724 | /* If checking the mode of displaced instruction in copy area, the mode | |
725 | should be determined by instruction on the original address. */ | |
726 | if (dsc) | |
727 | { | |
136821d9 SM |
728 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
729 | (unsigned long) dsc->insn_addr, | |
730 | (unsigned long) memaddr); | |
a42244db YQ |
731 | memaddr = dsc->insn_addr; |
732 | } | |
f9d67f43 DJ |
733 | |
734 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
735 | if (IS_THUMB_ADDR (memaddr)) | |
736 | return 1; | |
737 | ||
738 | /* If the user wants to override the symbol table, let him. */ | |
739 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
740 | return 0; | |
741 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
742 | return 1; | |
743 | ||
9779414d | 744 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
345bd07c | 745 | if (tdep->is_m) |
9779414d DJ |
746 | return 1; |
747 | ||
f9d67f43 DJ |
748 | /* If there are mapping symbols, consult them. */ |
749 | type = arm_find_mapping_symbol (memaddr, NULL); | |
750 | if (type) | |
751 | return type == 't'; | |
752 | ||
ed9a39eb | 753 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 754 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
755 | if (sym.minsym) |
756 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
757 | |
758 | /* If the user wants to override the fallback mode, let them. */ | |
759 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
760 | return 0; | |
761 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
762 | return 1; | |
763 | ||
764 | /* If we couldn't find any symbol, but we're talking to a running | |
765 | target, then trust the current value of $cpsr. This lets | |
766 | "display/i $pc" always show the correct mode (though if there is | |
767 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 768 | displayed in the mode it will be executed). */ |
9dccd06e | 769 | if (target_has_registers ()) |
18819fa6 | 770 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
771 | |
772 | /* Otherwise we're out of luck; we assume ARM. */ | |
773 | return 0; | |
c906108c SS |
774 | } |
775 | ||
8b73ee20 LM |
776 | static inline bool |
777 | arm_m_addr_is_lockup (CORE_ADDR addr) | |
778 | { | |
779 | switch (addr) | |
780 | { | |
781 | /* Values for lockup state. | |
782 | For more details see "B1.5.15 Unrecoverable exception cases" in | |
783 | both ARMv6-M and ARMv7-M Architecture Reference Manuals, or | |
784 | see "B4.32 Lockup" in ARMv8-M Architecture Reference Manual. */ | |
785 | case 0xeffffffe: | |
786 | case 0xfffffffe: | |
787 | case 0xffffffff: | |
788 | return true; | |
789 | ||
790 | default: | |
791 | /* Address is not lockup. */ | |
792 | return false; | |
793 | } | |
794 | } | |
795 | ||
ca90e760 | 796 | /* Determine if the address specified equals any of these magic return |
55ea94da | 797 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
8b73ee20 LM |
798 | architectures. Also include lockup magic PC value. |
799 | Check also for FNC_RETURN if we have the v8-M security extension. | |
ca90e760 FH |
800 | |
801 | From ARMv6-M Reference Manual B1.5.8 | |
802 | Table B1-5 Exception return behavior | |
803 | ||
804 | EXC_RETURN Return To Return Stack | |
805 | 0xFFFFFFF1 Handler mode Main | |
806 | 0xFFFFFFF9 Thread mode Main | |
807 | 0xFFFFFFFD Thread mode Process | |
808 | ||
809 | From ARMv7-M Reference Manual B1.5.8 | |
810 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
811 | ||
812 | EXC_RETURN Return To Return Stack | |
813 | 0xFFFFFFF1 Handler mode Main | |
814 | 0xFFFFFFF9 Thread mode Main | |
815 | 0xFFFFFFFD Thread mode Process | |
816 | ||
817 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
818 | FP | |
819 | ||
820 | EXC_RETURN Return To Return Stack Frame Type | |
821 | 0xFFFFFFE1 Handler mode Main Extended | |
822 | 0xFFFFFFE9 Thread mode Main Extended | |
823 | 0xFFFFFFED Thread mode Process Extended | |
824 | 0xFFFFFFF1 Handler mode Main Basic | |
825 | 0xFFFFFFF9 Thread mode Main Basic | |
826 | 0xFFFFFFFD Thread mode Process Basic | |
827 | ||
828 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
829 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
830 | ||
831 | In the ARMv8-M Architecture Technical Reference also adds | |
832 | for implementations without the Security Extension: | |
833 | ||
834 | EXC_RETURN Condition | |
835 | 0xFFFFFFB0 Return to Handler mode. | |
836 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
837 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
838 | |
839 | static int | |
ef273377 CL |
840 | arm_m_addr_is_magic (struct gdbarch *gdbarch, CORE_ADDR addr) |
841 | { | |
8b73ee20 LM |
842 | if (arm_m_addr_is_lockup (addr)) |
843 | return 1; | |
844 | ||
08106042 | 845 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ef273377 CL |
846 | if (tdep->have_sec_ext) |
847 | { | |
848 | switch ((addr & 0xff000000)) | |
849 | { | |
850 | case 0xff000000: /* EXC_RETURN pattern. */ | |
851 | case 0xfe000000: /* FNC_RETURN pattern. */ | |
852 | return 1; | |
853 | default: | |
854 | return 0; | |
855 | } | |
856 | } | |
857 | else | |
858 | { | |
859 | switch (addr) | |
860 | { | |
861 | /* Values from ARMv8-M Architecture Technical Reference. */ | |
862 | case 0xffffffb0: | |
863 | case 0xffffffb8: | |
864 | case 0xffffffbc: | |
865 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of | |
866 | the exception return behavior. */ | |
867 | case 0xffffffe1: | |
868 | case 0xffffffe9: | |
869 | case 0xffffffed: | |
870 | case 0xfffffff1: | |
871 | case 0xfffffff9: | |
872 | case 0xfffffffd: | |
873 | /* Address is magic. */ | |
874 | return 1; | |
ca90e760 | 875 | |
ef273377 CL |
876 | default: |
877 | /* Address is not magic. */ | |
878 | return 0; | |
879 | } | |
ca90e760 FH |
880 | } |
881 | } | |
882 | ||
181c1381 | 883 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 884 | static CORE_ADDR |
24568a2c | 885 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 886 | { |
08106042 | 887 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 888 | |
2ae28aa9 YQ |
889 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
890 | (the magic exception return address). */ | |
ef273377 | 891 | if (tdep->is_m && arm_m_addr_is_magic (gdbarch, val)) |
2ae28aa9 YQ |
892 | return val; |
893 | ||
a3a2ee65 | 894 | if (arm_apcs_32) |
dd6be234 | 895 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 896 | else |
a3a2ee65 | 897 | return (val & 0x03fffffc); |
c906108c SS |
898 | } |
899 | ||
0d39a070 | 900 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
901 | can be safely ignored during prologue skipping. IS_THUMB is true |
902 | if the function is known to be a Thumb function due to the way it | |
903 | is being called. */ | |
0d39a070 | 904 | static int |
e0634ccf | 905 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 906 | { |
e0634ccf | 907 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 908 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
909 | |
910 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 911 | if (msym.minsym != NULL |
4aeddc50 | 912 | && msym.value_address () == pc |
c9d95fa3 | 913 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 914 | { |
c9d95fa3 | 915 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 916 | |
e0634ccf UW |
917 | /* The GNU linker's Thumb call stub to foo is named |
918 | __foo_from_thumb. */ | |
919 | if (strstr (name, "_from_thumb") != NULL) | |
920 | name += 2; | |
0d39a070 | 921 | |
e0634ccf UW |
922 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
923 | arguments to their argument types in non-prototyped | |
924 | functions. */ | |
61012eef | 925 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 926 | return 1; |
61012eef | 927 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 928 | return 1; |
0d39a070 | 929 | |
e0634ccf | 930 | /* Internal functions related to thread-local storage. */ |
61012eef | 931 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 932 | return 1; |
61012eef | 933 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
934 | return 1; |
935 | } | |
936 | else | |
937 | { | |
938 | /* If we run against a stripped glibc, we may be unable to identify | |
939 | special functions by name. Check for one important case, | |
940 | __aeabi_read_tp, by comparing the *code* against the default | |
941 | implementation (this is hand-written ARM assembler in glibc). */ | |
942 | ||
943 | if (!is_thumb | |
198cd59d | 944 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 945 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 946 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
947 | == 0xe240f01f) /* sub pc, r0, #31 */ |
948 | return 1; | |
949 | } | |
ec3d575a | 950 | |
0d39a070 DJ |
951 | return 0; |
952 | } | |
953 | ||
621c6d5b YQ |
954 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
955 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
956 | instruction. */ | |
957 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
958 | ((bits ((insn1), 0, 3) << 12) \ | |
959 | | (bits ((insn1), 10, 10) << 11) \ | |
960 | | (bits ((insn2), 12, 14) << 8) \ | |
961 | | bits ((insn2), 0, 7)) | |
962 | ||
963 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
964 | the 32-bit instruction. */ | |
965 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
966 | ((bits ((insn), 16, 19) << 12) \ | |
967 | | bits ((insn), 0, 11)) | |
968 | ||
ec3d575a UW |
969 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
970 | ||
971 | static unsigned int | |
972 | thumb_expand_immediate (unsigned int imm) | |
973 | { | |
974 | unsigned int count = imm >> 7; | |
975 | ||
976 | if (count < 8) | |
977 | switch (count / 2) | |
978 | { | |
979 | case 0: | |
980 | return imm & 0xff; | |
981 | case 1: | |
982 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
983 | case 2: | |
984 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
985 | case 3: | |
986 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
987 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
988 | } | |
989 | ||
990 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
991 | } | |
992 | ||
540314bd YQ |
993 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
994 | epilogue, 0 otherwise. */ | |
995 | ||
996 | static int | |
997 | thumb_instruction_restores_sp (unsigned short insn) | |
998 | { | |
999 | return (insn == 0x46bd /* mov sp, r7 */ | |
1000 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
1001 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
1002 | } | |
1003 | ||
29d73ae4 DJ |
1004 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
1005 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
1006 | clobber the stack frame unexpectedly, or an unknown instruction. |
1007 | Return the last address which is definitely safe to skip for an | |
1008 | initial breakpoint. */ | |
c906108c SS |
1009 | |
1010 | static CORE_ADDR | |
29d73ae4 DJ |
1011 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
1012 | CORE_ADDR start, CORE_ADDR limit, | |
1013 | struct arm_prologue_cache *cache) | |
c906108c | 1014 | { |
08106042 | 1015 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 | 1016 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 1017 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
1018 | int i; |
1019 | pv_t regs[16]; | |
29d73ae4 | 1020 | CORE_ADDR offset; |
ec3d575a | 1021 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 1022 | |
29d73ae4 DJ |
1023 | for (i = 0; i < 16; i++) |
1024 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 1025 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 1026 | |
29d73ae4 | 1027 | while (start < limit) |
c906108c | 1028 | { |
29d73ae4 | 1029 | unsigned short insn; |
a01567f4 | 1030 | gdb::optional<bool> ra_signed_state; |
29d73ae4 | 1031 | |
198cd59d | 1032 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 1033 | |
94c30b78 | 1034 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 1035 | { |
29d73ae4 DJ |
1036 | int regno; |
1037 | int mask; | |
4be43953 | 1038 | |
f7b7ed97 | 1039 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 1040 | break; |
29d73ae4 DJ |
1041 | |
1042 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
1043 | whether to save LR (R14). */ | |
1044 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
1045 | ||
1046 | /* Calculate offsets of saved R0-R7 and LR. */ | |
1047 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
1048 | if (mask & (1 << regno)) | |
1049 | { | |
29d73ae4 DJ |
1050 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
1051 | -4); | |
f7b7ed97 | 1052 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 1053 | } |
da59e081 | 1054 | } |
1db01f22 | 1055 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 1056 | { |
29d73ae4 | 1057 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
1058 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
1059 | -offset); | |
da59e081 | 1060 | } |
808f7ab1 YQ |
1061 | else if (thumb_instruction_restores_sp (insn)) |
1062 | { | |
1063 | /* Don't scan past the epilogue. */ | |
1064 | break; | |
1065 | } | |
0d39a070 DJ |
1066 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
1067 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
1068 | (insn & 0xff) << 2); | |
1069 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
1070 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
1071 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
1072 | bits (insn, 6, 8)); | |
1073 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
1074 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1075 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
1076 | bits (insn, 0, 7)); | |
1077 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
1078 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
1079 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
1080 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
1081 | regs[bits (insn, 6, 8)]); | |
1082 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
1083 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
1084 | { | |
1085 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
1086 | int rm = bits (insn, 3, 6); | |
1087 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
1088 | } | |
29d73ae4 | 1089 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 1090 | { |
29d73ae4 DJ |
1091 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
1092 | int src_reg = (insn & 0x78) >> 3; | |
1093 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 1094 | } |
29d73ae4 | 1095 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 1096 | { |
29d73ae4 DJ |
1097 | /* Handle stores to the stack. Normally pushes are used, |
1098 | but with GCC -mtpcs-frame, there may be other stores | |
1099 | in the prologue to create the frame. */ | |
1100 | int regno = (insn >> 8) & 0x7; | |
1101 | pv_t addr; | |
1102 | ||
1103 | offset = (insn & 0xff) << 2; | |
1104 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
1105 | ||
f7b7ed97 | 1106 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
1107 | break; |
1108 | ||
f7b7ed97 | 1109 | stack.store (addr, 4, regs[regno]); |
da59e081 | 1110 | } |
0d39a070 DJ |
1111 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
1112 | { | |
1113 | int rd = bits (insn, 0, 2); | |
1114 | int rn = bits (insn, 3, 5); | |
1115 | pv_t addr; | |
1116 | ||
1117 | offset = bits (insn, 6, 10) << 2; | |
1118 | addr = pv_add_constant (regs[rn], offset); | |
1119 | ||
f7b7ed97 | 1120 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
1121 | break; |
1122 | ||
f7b7ed97 | 1123 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
1124 | } |
1125 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
1126 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
1127 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
1128 | /* Ignore stores of argument registers to the stack. */ | |
1129 | ; | |
1130 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
1131 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1132 | /* Ignore block loads from the stack, potentially copying | |
1133 | parameters from memory. */ | |
1134 | ; | |
1135 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
1136 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
1137 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
1138 | /* Similarly ignore single loads from the stack. */ | |
1139 | ; | |
1140 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
1141 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
1142 | /* Skip register copies, i.e. saves to another register | |
1143 | instead of the stack. */ | |
1144 | ; | |
1145 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
1146 | /* Recognize constant loads; even with small stacks these are necessary | |
1147 | on Thumb. */ | |
1148 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
1149 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
1150 | { | |
1151 | /* Constant pool loads, for the same reason. */ | |
1152 | unsigned int constant; | |
1153 | CORE_ADDR loc; | |
1154 | ||
1155 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
1156 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1157 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
1158 | } | |
db24da6d | 1159 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 1160 | { |
0d39a070 DJ |
1161 | unsigned short inst2; |
1162 | ||
198cd59d YQ |
1163 | inst2 = read_code_unsigned_integer (start + 2, 2, |
1164 | byte_order_for_code); | |
a01567f4 | 1165 | uint32_t whole_insn = (insn << 16) | inst2; |
0d39a070 DJ |
1166 | |
1167 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
1168 | { | |
1169 | /* BL, BLX. Allow some special function calls when | |
1170 | skipping the prologue; GCC generates these before | |
1171 | storing arguments to the stack. */ | |
1172 | CORE_ADDR nextpc; | |
1173 | int j1, j2, imm1, imm2; | |
1174 | ||
1175 | imm1 = sbits (insn, 0, 10); | |
1176 | imm2 = bits (inst2, 0, 10); | |
1177 | j1 = bit (inst2, 13); | |
1178 | j2 = bit (inst2, 11); | |
1179 | ||
1180 | offset = ((imm1 << 12) + (imm2 << 1)); | |
1181 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
1182 | ||
1183 | nextpc = start + 4 + offset; | |
1184 | /* For BLX make sure to clear the low bits. */ | |
1185 | if (bit (inst2, 12) == 0) | |
1186 | nextpc = nextpc & 0xfffffffc; | |
1187 | ||
e0634ccf UW |
1188 | if (!skip_prologue_function (gdbarch, nextpc, |
1189 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
1190 | break; |
1191 | } | |
ec3d575a | 1192 | |
0963b4bd MS |
1193 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
1194 | { registers } */ | |
ec3d575a UW |
1195 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1196 | { | |
1197 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1198 | int regno; | |
1199 | ||
f7b7ed97 | 1200 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1201 | break; |
1202 | ||
1203 | /* Calculate offsets of saved registers. */ | |
1204 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
1205 | if (inst2 & (1 << regno)) | |
1206 | { | |
1207 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 1208 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1209 | } |
1210 | ||
1211 | if (insn & 0x0020) | |
1212 | regs[bits (insn, 0, 3)] = addr; | |
1213 | } | |
1214 | ||
fcaa1071 CL |
1215 | /* vstmdb Rn{!}, { D-registers } (aka vpush). */ |
1216 | else if ((insn & 0xff20) == 0xed20 | |
1217 | && (inst2 & 0x0f00) == 0x0b00 | |
1218 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1219 | { | |
1220 | /* Address SP points to. */ | |
1221 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1222 | ||
1223 | /* Number of registers saved. */ | |
1224 | unsigned int number = bits (inst2, 0, 7) >> 1; | |
1225 | ||
1226 | /* First register to save. */ | |
1227 | int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4); | |
1228 | ||
1229 | if (stack.store_would_trash (addr)) | |
1230 | break; | |
1231 | ||
1232 | /* Calculate offsets of saved registers. */ | |
1233 | for (; number > 0; number--) | |
1234 | { | |
1235 | addr = pv_add_constant (addr, -8); | |
1236 | stack.store (addr, 8, pv_register (ARM_D0_REGNUM | |
1237 | + vd + number, 0)); | |
1238 | } | |
1239 | ||
1240 | /* Writeback SP to account for the saved registers. */ | |
1241 | regs[bits (insn, 0, 3)] = addr; | |
1242 | } | |
1243 | ||
0963b4bd MS |
1244 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
1245 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
1246 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1247 | { | |
1248 | int regno1 = bits (inst2, 12, 15); | |
1249 | int regno2 = bits (inst2, 8, 11); | |
1250 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1251 | ||
1252 | offset = inst2 & 0xff; | |
1253 | if (insn & 0x0080) | |
1254 | addr = pv_add_constant (addr, offset); | |
1255 | else | |
1256 | addr = pv_add_constant (addr, -offset); | |
1257 | ||
f7b7ed97 | 1258 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1259 | break; |
1260 | ||
f7b7ed97 TT |
1261 | stack.store (addr, 4, regs[regno1]); |
1262 | stack.store (pv_add_constant (addr, 4), | |
1263 | 4, regs[regno2]); | |
ec3d575a UW |
1264 | |
1265 | if (insn & 0x0020) | |
1266 | regs[bits (insn, 0, 3)] = addr; | |
1267 | } | |
1268 | ||
1269 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
1270 | && (inst2 & 0x0c00) == 0x0c00 | |
1271 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1272 | { | |
1273 | int regno = bits (inst2, 12, 15); | |
1274 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1275 | ||
1276 | offset = inst2 & 0xff; | |
1277 | if (inst2 & 0x0200) | |
1278 | addr = pv_add_constant (addr, offset); | |
1279 | else | |
1280 | addr = pv_add_constant (addr, -offset); | |
1281 | ||
f7b7ed97 | 1282 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1283 | break; |
1284 | ||
f7b7ed97 | 1285 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1286 | |
1287 | if (inst2 & 0x0100) | |
1288 | regs[bits (insn, 0, 3)] = addr; | |
1289 | } | |
1290 | ||
1291 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
1292 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1293 | { | |
1294 | int regno = bits (inst2, 12, 15); | |
1295 | pv_t addr; | |
1296 | ||
1297 | offset = inst2 & 0xfff; | |
1298 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
1299 | ||
f7b7ed97 | 1300 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1301 | break; |
1302 | ||
f7b7ed97 | 1303 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1304 | } |
1305 | ||
1306 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 1307 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1308 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1309 | ; |
ec3d575a UW |
1310 | |
1311 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
1312 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1313 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1314 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1315 | ; |
ec3d575a | 1316 | |
0963b4bd MS |
1317 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
1318 | { registers } */ | |
ec3d575a UW |
1319 | && (inst2 & 0x8000) == 0x0000 |
1320 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1321 | /* Ignore block loads from the stack, potentially copying | |
1322 | parameters from memory. */ | |
0d39a070 | 1323 | ; |
ec3d575a | 1324 | |
f8c6d152 | 1325 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 1326 | [Rn, #+/-imm] */ |
0d39a070 | 1327 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1328 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 1329 | ; |
ec3d575a UW |
1330 | |
1331 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
1332 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1333 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1334 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1335 | ; |
ec3d575a UW |
1336 | |
1337 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 1338 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1339 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1340 | ; |
ec3d575a UW |
1341 | |
1342 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
1343 | && (inst2 & 0x8000) == 0x0000) | |
1344 | { | |
1345 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1346 | | (bits (inst2, 12, 14) << 8) | |
1347 | | bits (inst2, 0, 7)); | |
1348 | ||
1349 | regs[bits (inst2, 8, 11)] | |
1350 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1351 | thumb_expand_immediate (imm)); | |
1352 | } | |
1353 | ||
1354 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1355 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1356 | { |
ec3d575a UW |
1357 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1358 | | (bits (inst2, 12, 14) << 8) | |
1359 | | bits (inst2, 0, 7)); | |
1360 | ||
1361 | regs[bits (inst2, 8, 11)] | |
1362 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1363 | } | |
1364 | ||
1365 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1366 | && (inst2 & 0x8000) == 0x0000) | |
1367 | { | |
1368 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1369 | | (bits (inst2, 12, 14) << 8) | |
1370 | | bits (inst2, 0, 7)); | |
1371 | ||
1372 | regs[bits (inst2, 8, 11)] | |
1373 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1374 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1375 | } | |
1376 | ||
1377 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1378 | && (inst2 & 0x8000) == 0x0000) | |
1379 | { | |
1380 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1381 | | (bits (inst2, 12, 14) << 8) | |
1382 | | bits (inst2, 0, 7)); | |
1383 | ||
1384 | regs[bits (inst2, 8, 11)] | |
1385 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1386 | } | |
1387 | ||
1388 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1389 | { | |
1390 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1391 | | (bits (inst2, 12, 14) << 8) | |
1392 | | bits (inst2, 0, 7)); | |
1393 | ||
1394 | regs[bits (inst2, 8, 11)] | |
1395 | = pv_constant (thumb_expand_immediate (imm)); | |
1396 | } | |
1397 | ||
1398 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1399 | { | |
621c6d5b YQ |
1400 | unsigned int imm |
1401 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1402 | |
1403 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1404 | } | |
1405 | ||
1406 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1407 | && (inst2 & 0xf0f0) == 0) | |
1408 | { | |
1409 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1410 | int src_reg = inst2 & 0xf; | |
1411 | regs[dst_reg] = regs[src_reg]; | |
1412 | } | |
1413 | ||
1414 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1415 | { | |
1416 | /* Constant pool loads. */ | |
1417 | unsigned int constant; | |
1418 | CORE_ADDR loc; | |
1419 | ||
cac395ea | 1420 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1421 | if (insn & 0x0080) |
1422 | loc = start + 4 + offset; | |
1423 | else | |
1424 | loc = start + 4 - offset; | |
1425 | ||
1426 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1427 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1428 | } | |
1429 | ||
1430 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1431 | { | |
1432 | /* Constant pool loads. */ | |
1433 | unsigned int constant; | |
1434 | CORE_ADDR loc; | |
1435 | ||
cac395ea | 1436 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1437 | if (insn & 0x0080) |
1438 | loc = start + 4 + offset; | |
1439 | else | |
1440 | loc = start + 4 - offset; | |
1441 | ||
1442 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1443 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1444 | ||
1445 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1446 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1447 | } | |
a01567f4 LM |
1448 | /* Start of ARMv8.1-m PACBTI extension instructions. */ |
1449 | else if (IS_PAC (whole_insn)) | |
1450 | { | |
1451 | /* LR and SP are input registers. PAC is in R12. LR is | |
1452 | signed from this point onwards. NOP space. */ | |
1453 | ra_signed_state = true; | |
1454 | } | |
1455 | else if (IS_PACBTI (whole_insn)) | |
1456 | { | |
1457 | /* LR and SP are input registers. PAC is in R12 and PC is a | |
1458 | valid BTI landing pad. LR is signed from this point onwards. | |
1459 | NOP space. */ | |
1460 | ra_signed_state = true; | |
1461 | } | |
1462 | else if (IS_BTI (whole_insn)) | |
1463 | { | |
1464 | /* Valid BTI landing pad. NOP space. */ | |
1465 | } | |
1466 | else if (IS_PACG (whole_insn)) | |
1467 | { | |
1468 | /* Sign Rn using Rm and store the PAC in Rd. Rd is signed from | |
1469 | this point onwards. */ | |
1470 | ra_signed_state = true; | |
1471 | } | |
1472 | else if (IS_AUT (whole_insn) || IS_AUTG (whole_insn)) | |
1473 | { | |
1474 | /* These instructions appear close to the epilogue, when signed | |
1475 | pointers are getting authenticated. */ | |
1476 | ra_signed_state = false; | |
1477 | } | |
1478 | /* End of ARMv8.1-m PACBTI extension instructions */ | |
ec3d575a UW |
1479 | else if (thumb2_instruction_changes_pc (insn, inst2)) |
1480 | { | |
1481 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1482 | break; |
1483 | } | |
ec3d575a UW |
1484 | else |
1485 | { | |
1486 | /* The optimizer might shove anything into the prologue, | |
1487 | so we just skip what we don't recognize. */ | |
1488 | unrecognized_pc = start; | |
1489 | } | |
0d39a070 | 1490 | |
a01567f4 LM |
1491 | /* Make sure we are dealing with a target that supports ARMv8.1-m |
1492 | PACBTI. */ | |
1493 | if (cache != nullptr && tdep->have_pacbti | |
1494 | && ra_signed_state.has_value ()) | |
1495 | { | |
1496 | arm_debug_printf ("Found pacbti instruction at %s", | |
1497 | paddress (gdbarch, start)); | |
1498 | arm_debug_printf ("RA is %s", | |
1499 | *ra_signed_state? "signed" : "not signed"); | |
1500 | cache->ra_signed_state = ra_signed_state; | |
1501 | } | |
1502 | ||
0d39a070 DJ |
1503 | start += 2; |
1504 | } | |
ec3d575a | 1505 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1506 | { |
ec3d575a | 1507 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1508 | break; |
3d74b771 | 1509 | } |
ec3d575a UW |
1510 | else |
1511 | { | |
1512 | /* The optimizer might shove anything into the prologue, | |
1513 | so we just skip what we don't recognize. */ | |
1514 | unrecognized_pc = start; | |
1515 | } | |
29d73ae4 DJ |
1516 | |
1517 | start += 2; | |
c906108c SS |
1518 | } |
1519 | ||
7cb6d92a SM |
1520 | arm_debug_printf ("Prologue scan stopped at %s", |
1521 | paddress (gdbarch, start)); | |
0d39a070 | 1522 | |
ec3d575a UW |
1523 | if (unrecognized_pc == 0) |
1524 | unrecognized_pc = start; | |
1525 | ||
29d73ae4 | 1526 | if (cache == NULL) |
f7b7ed97 | 1527 | return unrecognized_pc; |
29d73ae4 | 1528 | |
29d73ae4 DJ |
1529 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1530 | { | |
1531 | /* Frame pointer is fp. Frame size is constant. */ | |
1532 | cache->framereg = ARM_FP_REGNUM; | |
1533 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1534 | } | |
1535 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1536 | { | |
1537 | /* Frame pointer is r7. Frame size is constant. */ | |
1538 | cache->framereg = THUMB_FP_REGNUM; | |
1539 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1540 | } | |
72a2e3dc | 1541 | else |
29d73ae4 DJ |
1542 | { |
1543 | /* Try the stack pointer... this is a bit desperate. */ | |
1544 | cache->framereg = ARM_SP_REGNUM; | |
1545 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1546 | } | |
29d73ae4 | 1547 | |
de76473c | 1548 | for (i = 0; i < gdbarch_num_regs (gdbarch); i++) |
f7b7ed97 | 1549 | if (stack.find_reg (gdbarch, i, &offset)) |
10245fe8 YR |
1550 | { |
1551 | cache->saved_regs[i].set_addr (offset); | |
1552 | if (i == ARM_SP_REGNUM) | |
1553 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
1554 | } | |
29d73ae4 | 1555 | |
ec3d575a | 1556 | return unrecognized_pc; |
c906108c SS |
1557 | } |
1558 | ||
621c6d5b YQ |
1559 | |
1560 | /* Try to analyze the instructions starting from PC, which load symbol | |
1561 | __stack_chk_guard. Return the address of instruction after loading this | |
1562 | symbol, set the dest register number to *BASEREG, and set the size of | |
1563 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1564 | not recognized. */ | |
1565 | ||
1566 | static CORE_ADDR | |
1567 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1568 | unsigned int *destreg, int *offset) | |
1569 | { | |
1570 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1571 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1572 | unsigned int low, high, address; | |
1573 | ||
1574 | address = 0; | |
1575 | if (is_thumb) | |
1576 | { | |
1577 | unsigned short insn1 | |
198cd59d | 1578 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1579 | |
1580 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1581 | { | |
1582 | *destreg = bits (insn1, 8, 10); | |
1583 | *offset = 2; | |
6ae274b7 YQ |
1584 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1585 | address = read_memory_unsigned_integer (address, 4, | |
1586 | byte_order_for_code); | |
621c6d5b YQ |
1587 | } |
1588 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1589 | { | |
1590 | unsigned short insn2 | |
198cd59d | 1591 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1592 | |
1593 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1594 | ||
1595 | insn1 | |
198cd59d | 1596 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1597 | insn2 |
198cd59d | 1598 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1599 | |
1600 | /* movt Rd, #const */ | |
1601 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1602 | { | |
1603 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1604 | *destreg = bits (insn2, 8, 11); | |
1605 | *offset = 8; | |
1606 | address = (high << 16 | low); | |
1607 | } | |
1608 | } | |
1609 | } | |
1610 | else | |
1611 | { | |
2e9e421f | 1612 | unsigned int insn |
198cd59d | 1613 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1614 | |
6ae274b7 | 1615 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1616 | { |
6ae274b7 YQ |
1617 | address = bits (insn, 0, 11) + pc + 8; |
1618 | address = read_memory_unsigned_integer (address, 4, | |
1619 | byte_order_for_code); | |
1620 | ||
2e9e421f UW |
1621 | *destreg = bits (insn, 12, 15); |
1622 | *offset = 4; | |
1623 | } | |
1624 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1625 | { | |
1626 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1627 | ||
1628 | insn | |
198cd59d | 1629 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1630 | |
1631 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1632 | { | |
1633 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1634 | *destreg = bits (insn, 12, 15); | |
1635 | *offset = 8; | |
1636 | address = (high << 16 | low); | |
1637 | } | |
1638 | } | |
621c6d5b YQ |
1639 | } |
1640 | ||
1641 | return address; | |
1642 | } | |
1643 | ||
1644 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1645 | points to the first instruction of this sequence, return the address of |
1646 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1647 | |
1648 | On arm, this sequence of instructions is composed of mainly three steps, | |
1649 | Step 1: load symbol __stack_chk_guard, | |
1650 | Step 2: load from address of __stack_chk_guard, | |
1651 | Step 3: store it to somewhere else. | |
1652 | ||
1653 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1654 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1655 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1656 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1657 | they are, | |
1658 | ||
1659 | movw Rn, #:lower16:__stack_chk_guard | |
1660 | movt Rn, #:upper16:__stack_chk_guard | |
1661 | ||
1662 | On ARMv5t, it is, | |
1663 | ||
1664 | ldr Rn, .Label | |
1665 | .... | |
1666 | .Lable: | |
1667 | .word __stack_chk_guard | |
1668 | ||
1669 | Since ldr/str is a very popular instruction, we can't use them as | |
1670 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1671 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1672 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1673 | ||
1674 | static CORE_ADDR | |
1675 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1676 | { | |
1677 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1678 | unsigned int basereg; |
7cbd4a93 | 1679 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1680 | int offset; |
1681 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1682 | CORE_ADDR addr; | |
1683 | ||
1684 | /* Try to parse the instructions in Step 1. */ | |
1685 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1686 | &basereg, &offset); | |
1687 | if (!addr) | |
1688 | return pc; | |
1689 | ||
1690 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1691 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1692 | Otherwise, this sequence cannot be for stack protector. */ | |
1693 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1694 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1695 | return pc; |
1696 | ||
1697 | if (is_thumb) | |
1698 | { | |
1699 | unsigned int destreg; | |
1700 | unsigned short insn | |
198cd59d | 1701 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1702 | |
1703 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1704 | if ((insn & 0xf800) != 0x6800) | |
1705 | return pc; | |
1706 | if (bits (insn, 3, 5) != basereg) | |
1707 | return pc; | |
1708 | destreg = bits (insn, 0, 2); | |
1709 | ||
198cd59d YQ |
1710 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1711 | byte_order_for_code); | |
621c6d5b YQ |
1712 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1713 | if ((insn & 0xf800) != 0x6000) | |
1714 | return pc; | |
1715 | if (destreg != bits (insn, 0, 2)) | |
1716 | return pc; | |
1717 | } | |
1718 | else | |
1719 | { | |
1720 | unsigned int destreg; | |
1721 | unsigned int insn | |
198cd59d | 1722 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1723 | |
1724 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1725 | if ((insn & 0x0e500000) != 0x04100000) | |
1726 | return pc; | |
1727 | if (bits (insn, 16, 19) != basereg) | |
1728 | return pc; | |
1729 | destreg = bits (insn, 12, 15); | |
1730 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1731 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1732 | 4, byte_order_for_code); |
1733 | if ((insn & 0x0e500000) != 0x04000000) | |
1734 | return pc; | |
1735 | if (bits (insn, 12, 15) != destreg) | |
1736 | return pc; | |
1737 | } | |
1738 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1739 | on arm. */ | |
1740 | if (is_thumb) | |
1741 | return pc + offset + 4; | |
1742 | else | |
1743 | return pc + offset + 8; | |
1744 | } | |
1745 | ||
da3c6d4a MS |
1746 | /* Advance the PC across any function entry prologue instructions to |
1747 | reach some "real" code. | |
34e8f22d RE |
1748 | |
1749 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1750 | prologue: |
c906108c | 1751 | |
c5aa993b JM |
1752 | mov ip, sp |
1753 | [stmfd sp!, {a1,a2,a3,a4}] | |
1754 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1755 | [stfe f7, [sp, #-12]!] |
1756 | [stfe f6, [sp, #-12]!] | |
1757 | [stfe f5, [sp, #-12]!] | |
1758 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1759 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1760 | |
34e8f22d | 1761 | static CORE_ADDR |
6093d2eb | 1762 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1763 | { |
a89fea3c | 1764 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1765 | |
a89fea3c JL |
1766 | /* See if we can determine the end of the prologue via the symbol table. |
1767 | If so, then return either PC, or the PC after the prologue, whichever | |
1768 | is greater. */ | |
1769 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1770 | { |
d80b854b UW |
1771 | CORE_ADDR post_prologue_pc |
1772 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1773 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1774 | |
621c6d5b YQ |
1775 | if (post_prologue_pc) |
1776 | post_prologue_pc | |
1777 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1778 | ||
1779 | ||
0d39a070 DJ |
1780 | /* GCC always emits a line note before the prologue and another |
1781 | one after, even if the two are at the same address or on the | |
1782 | same line. Take advantage of this so that we do not need to | |
1783 | know every instruction that might appear in the prologue. We | |
1784 | will have producer information for most binaries; if it is | |
1785 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1786 | if (post_prologue_pc | |
43f3e411 | 1787 | && (cust == NULL |
ab5f850e SM |
1788 | || cust->producer () == NULL |
1789 | || startswith (cust->producer (), "GNU ") | |
1790 | || producer_is_llvm (cust->producer ()))) | |
0d39a070 DJ |
1791 | return post_prologue_pc; |
1792 | ||
a89fea3c | 1793 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1794 | { |
1795 | CORE_ADDR analyzed_limit; | |
1796 | ||
1797 | /* For non-GCC compilers, make sure the entire line is an | |
1798 | acceptable prologue; GDB will round this function's | |
1799 | return value up to the end of the following line so we | |
1800 | can not skip just part of a line (and we do not want to). | |
1801 | ||
1802 | RealView does not treat the prologue specially, but does | |
1803 | associate prologue code with the opening brace; so this | |
1804 | lets us skip the first line if we think it is the opening | |
1805 | brace. */ | |
9779414d | 1806 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1807 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1808 | post_prologue_pc, NULL); | |
1809 | else | |
9ecab40c SM |
1810 | analyzed_limit |
1811 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1812 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1813 | |
1814 | if (analyzed_limit != post_prologue_pc) | |
1815 | return func_addr; | |
1816 | ||
1817 | return post_prologue_pc; | |
1818 | } | |
c906108c SS |
1819 | } |
1820 | ||
a89fea3c JL |
1821 | /* Can't determine prologue from the symbol table, need to examine |
1822 | instructions. */ | |
c906108c | 1823 | |
a89fea3c JL |
1824 | /* Find an upper limit on the function prologue using the debug |
1825 | information. If the debug information could not be used to provide | |
1826 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1827 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1828 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1829 | if (limit_pc == 0) |
1830 | limit_pc = pc + 64; /* Magic. */ | |
1831 | ||
c906108c | 1832 | |
29d73ae4 | 1833 | /* Check if this is Thumb code. */ |
9779414d | 1834 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1835 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1836 | else |
9ecab40c SM |
1837 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1838 | target_arm_instruction_reader ()); | |
c906108c | 1839 | } |
94c30b78 | 1840 | |
c5aa993b | 1841 | /* *INDENT-OFF* */ |
c906108c SS |
1842 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1843 | This function decodes a Thumb function prologue to determine: | |
1844 | 1) the size of the stack frame | |
1845 | 2) which registers are saved on it | |
1846 | 3) the offsets of saved regs | |
1847 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1848 | |
da59e081 JM |
1849 | A typical Thumb function prologue would create this stack frame |
1850 | (offsets relative to FP) | |
c906108c SS |
1851 | old SP -> 24 stack parameters |
1852 | 20 LR | |
1853 | 16 R7 | |
1854 | R7 -> 0 local variables (16 bytes) | |
1855 | SP -> -12 additional stack space (12 bytes) | |
1856 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1857 | 12 bytes. The frame register is R7. |
da59e081 | 1858 | |
da3c6d4a MS |
1859 | The comments for thumb_skip_prolog() describe the algorithm we use |
1860 | to detect the end of the prolog. */ | |
c5aa993b JM |
1861 | /* *INDENT-ON* */ |
1862 | ||
c906108c | 1863 | static void |
be8626e0 | 1864 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1865 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1866 | { |
1867 | CORE_ADDR prologue_start; | |
1868 | CORE_ADDR prologue_end; | |
c906108c | 1869 | |
b39cc962 DJ |
1870 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1871 | &prologue_end)) | |
c906108c | 1872 | { |
ec3d575a UW |
1873 | /* See comment in arm_scan_prologue for an explanation of |
1874 | this heuristics. */ | |
1875 | if (prologue_end > prologue_start + 64) | |
1876 | { | |
1877 | prologue_end = prologue_start + 64; | |
1878 | } | |
c906108c SS |
1879 | } |
1880 | else | |
f7060f85 DJ |
1881 | /* We're in the boondocks: we have no idea where the start of the |
1882 | function is. */ | |
1883 | return; | |
c906108c | 1884 | |
325fac50 | 1885 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1886 | |
be8626e0 | 1887 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1888 | } |
1889 | ||
f303bc3e YQ |
1890 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1891 | otherwise. */ | |
1892 | ||
1893 | static int | |
1894 | arm_instruction_restores_sp (unsigned int insn) | |
1895 | { | |
1896 | if (bits (insn, 28, 31) != INST_NV) | |
1897 | { | |
1898 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1899 | /* ADD SP (register or immediate). */ | |
1900 | || (insn & 0x0df0f000) == 0x0040d000 | |
1901 | /* SUB SP (register or immediate). */ | |
1902 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1903 | /* MOV SP. */ | |
1904 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1905 | /* POP (LDMIA). */ | |
1906 | || (insn & 0x0fff0000) == 0x049d0000) | |
1907 | /* POP of a single register. */ | |
1908 | return 1; | |
1909 | } | |
1910 | ||
1911 | return 0; | |
1912 | } | |
1913 | ||
9ecab40c SM |
1914 | /* Implement immediate value decoding, as described in section A5.2.4 |
1915 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1916 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1917 | ||
1918 | static uint32_t | |
1919 | arm_expand_immediate (uint32_t imm) | |
1920 | { | |
1921 | /* Immediate values are 12 bits long. */ | |
1922 | gdb_assert ((imm & 0xfffff000) == 0); | |
1923 | ||
1924 | uint32_t unrotated_value = imm & 0xff; | |
1925 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1926 | ||
1927 | if (rotate_amount == 0) | |
1928 | return unrotated_value; | |
1929 | ||
1930 | return ((unrotated_value >> rotate_amount) | |
1931 | | (unrotated_value << (32 - rotate_amount))); | |
1932 | } | |
1933 | ||
0d39a070 DJ |
1934 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1935 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1936 | fill it in. Return the first address not recognized as a prologue | |
1937 | instruction. | |
eb5492fa | 1938 | |
0d39a070 DJ |
1939 | We recognize all the instructions typically found in ARM prologues, |
1940 | plus harmless instructions which can be skipped (either for analysis | |
1941 | purposes, or a more restrictive set that can be skipped when finding | |
1942 | the end of the prologue). */ | |
1943 | ||
1944 | static CORE_ADDR | |
1945 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1946 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1947 | struct arm_prologue_cache *cache, |
1948 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1949 | { |
0d39a070 DJ |
1950 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1951 | int regno; | |
1952 | CORE_ADDR offset, current_pc; | |
1953 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 | 1954 | CORE_ADDR unrecognized_pc = 0; |
08106042 | 1955 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
1956 | |
1957 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1958 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1959 | |
96baa820 JM |
1960 | Be careful, however, and if it doesn't look like a prologue, |
1961 | don't try to scan it. If, for instance, a frameless function | |
1962 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1963 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1964 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1965 | traceback. */ |
d4473757 | 1966 | |
4be43953 DJ |
1967 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1968 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1969 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1970 | |
94c30b78 MS |
1971 | for (current_pc = prologue_start; |
1972 | current_pc < prologue_end; | |
f43845b3 | 1973 | current_pc += 4) |
96baa820 | 1974 | { |
9ecab40c | 1975 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1976 | |
94c30b78 | 1977 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1978 | { |
4be43953 | 1979 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1980 | continue; |
1981 | } | |
0d39a070 DJ |
1982 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1983 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1984 | { |
9ecab40c | 1985 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1986 | int rd = bits (insn, 12, 15); |
0d39a070 | 1987 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1988 | continue; |
1989 | } | |
0d39a070 DJ |
1990 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1991 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1992 | { |
9ecab40c | 1993 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1994 | int rd = bits (insn, 12, 15); |
0d39a070 | 1995 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1996 | continue; |
1997 | } | |
0963b4bd MS |
1998 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1999 | [sp, #-4]! */ | |
f43845b3 | 2000 | { |
f7b7ed97 | 2001 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2002 | break; |
2003 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
2004 | stack.store (regs[ARM_SP_REGNUM], 4, |
2005 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
2006 | continue; |
2007 | } | |
2008 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
2009 | /* stmfd sp!, {..., fp, ip, lr, pc} |
2010 | or | |
2011 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 2012 | { |
d4473757 | 2013 | int mask = insn & 0xffff; |
ed9a39eb | 2014 | |
f7b7ed97 | 2015 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2016 | break; |
2017 | ||
94c30b78 | 2018 | /* Calculate offsets of saved registers. */ |
34e8f22d | 2019 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
2020 | if (mask & (1 << regno)) |
2021 | { | |
0963b4bd MS |
2022 | regs[ARM_SP_REGNUM] |
2023 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 2024 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
2025 | } |
2026 | } | |
0d39a070 DJ |
2027 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
2028 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 2029 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
2030 | { |
2031 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
2032 | continue; | |
2033 | } | |
0d39a070 DJ |
2034 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
2035 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 2036 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
2037 | { |
2038 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
2039 | continue; | |
2040 | } | |
0963b4bd MS |
2041 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
2042 | { registers } */ | |
0d39a070 DJ |
2043 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
2044 | { | |
2045 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
2046 | continue; | |
2047 | } | |
d4473757 KB |
2048 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
2049 | { | |
9ecab40c | 2050 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 2051 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
2052 | } |
2053 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
2054 | { | |
9ecab40c | 2055 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 2056 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 2057 | } |
0963b4bd MS |
2058 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
2059 | [sp, -#c]! */ | |
345bd07c | 2060 | && tdep->have_fpa_registers) |
d4473757 | 2061 | { |
f7b7ed97 | 2062 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2063 | break; |
2064 | ||
2065 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 2066 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 2067 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 2068 | } |
0963b4bd MS |
2069 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
2070 | [sp!] */ | |
345bd07c | 2071 | && tdep->have_fpa_registers) |
d4473757 KB |
2072 | { |
2073 | int n_saved_fp_regs; | |
2074 | unsigned int fp_start_reg, fp_bound_reg; | |
2075 | ||
f7b7ed97 | 2076 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2077 | break; |
2078 | ||
94c30b78 | 2079 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 2080 | { |
d4473757 KB |
2081 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2082 | n_saved_fp_regs = 3; | |
2083 | else | |
2084 | n_saved_fp_regs = 1; | |
96baa820 | 2085 | } |
d4473757 | 2086 | else |
96baa820 | 2087 | { |
d4473757 KB |
2088 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2089 | n_saved_fp_regs = 2; | |
2090 | else | |
2091 | n_saved_fp_regs = 4; | |
96baa820 | 2092 | } |
d4473757 | 2093 | |
34e8f22d | 2094 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
2095 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
2096 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 2097 | { |
4be43953 | 2098 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
2099 | stack.store (regs[ARM_SP_REGNUM], 12, |
2100 | regs[fp_start_reg++]); | |
96baa820 | 2101 | } |
c906108c | 2102 | } |
0d39a070 DJ |
2103 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
2104 | { | |
2105 | /* Allow some special function calls when skipping the | |
2106 | prologue; GCC generates these before storing arguments to | |
2107 | the stack. */ | |
2108 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
2109 | ||
e0634ccf | 2110 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
2111 | continue; |
2112 | else | |
2113 | break; | |
2114 | } | |
d4473757 | 2115 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 2116 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
2117 | else if (arm_instruction_changes_pc (insn)) |
2118 | /* Don't scan past anything that might change control flow. */ | |
2119 | break; | |
f303bc3e YQ |
2120 | else if (arm_instruction_restores_sp (insn)) |
2121 | { | |
2122 | /* Don't scan past the epilogue. */ | |
2123 | break; | |
2124 | } | |
d19f7eee UW |
2125 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
2126 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2127 | /* Ignore block loads from the stack, potentially copying | |
2128 | parameters from memory. */ | |
2129 | continue; | |
2130 | else if ((insn & 0xfc500000) == 0xe4100000 | |
2131 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2132 | /* Similarly ignore single loads from the stack. */ | |
2133 | continue; | |
0d39a070 DJ |
2134 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
2135 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
2136 | register instead of the stack. */ | |
d4473757 | 2137 | continue; |
0d39a070 DJ |
2138 | else |
2139 | { | |
21daaaaf YQ |
2140 | /* The optimizer might shove anything into the prologue, if |
2141 | we build up cache (cache != NULL) from scanning prologue, | |
2142 | we just skip what we don't recognize and scan further to | |
2143 | make cache as complete as possible. However, if we skip | |
2144 | prologue, we'll stop immediately on unrecognized | |
2145 | instruction. */ | |
0d39a070 | 2146 | unrecognized_pc = current_pc; |
21daaaaf YQ |
2147 | if (cache != NULL) |
2148 | continue; | |
2149 | else | |
2150 | break; | |
0d39a070 | 2151 | } |
c906108c SS |
2152 | } |
2153 | ||
0d39a070 DJ |
2154 | if (unrecognized_pc == 0) |
2155 | unrecognized_pc = current_pc; | |
2156 | ||
0d39a070 DJ |
2157 | if (cache) |
2158 | { | |
4072f920 YQ |
2159 | int framereg, framesize; |
2160 | ||
2161 | /* The frame size is just the distance from the frame register | |
2162 | to the original stack pointer. */ | |
2163 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
2164 | { | |
2165 | /* Frame pointer is fp. */ | |
2166 | framereg = ARM_FP_REGNUM; | |
2167 | framesize = -regs[ARM_FP_REGNUM].k; | |
2168 | } | |
2169 | else | |
2170 | { | |
2171 | /* Try the stack pointer... this is a bit desperate. */ | |
2172 | framereg = ARM_SP_REGNUM; | |
2173 | framesize = -regs[ARM_SP_REGNUM].k; | |
2174 | } | |
2175 | ||
0d39a070 DJ |
2176 | cache->framereg = framereg; |
2177 | cache->framesize = framesize; | |
2178 | ||
2179 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 2180 | if (stack.find_reg (gdbarch, regno, &offset)) |
10245fe8 YR |
2181 | { |
2182 | cache->saved_regs[regno].set_addr (offset); | |
2183 | if (regno == ARM_SP_REGNUM) | |
2184 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
2185 | } | |
0d39a070 DJ |
2186 | } |
2187 | ||
7cb6d92a SM |
2188 | arm_debug_printf ("Prologue scan stopped at %s", |
2189 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 2190 | |
0d39a070 DJ |
2191 | return unrecognized_pc; |
2192 | } | |
2193 | ||
2194 | static void | |
bd2b40ac | 2195 | arm_scan_prologue (frame_info_ptr this_frame, |
0d39a070 DJ |
2196 | struct arm_prologue_cache *cache) |
2197 | { | |
2198 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2199 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 2200 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
2201 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
2202 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
08106042 | 2203 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
2204 | |
2205 | /* Assume there is no frame until proven otherwise. */ | |
2206 | cache->framereg = ARM_SP_REGNUM; | |
2207 | cache->framesize = 0; | |
2208 | ||
2209 | /* Check for Thumb prologue. */ | |
2210 | if (arm_frame_is_thumb (this_frame)) | |
2211 | { | |
2212 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
2213 | return; | |
2214 | } | |
2215 | ||
2216 | /* Find the function prologue. If we can't find the function in | |
2217 | the symbol table, peek in the stack frame to find the PC. */ | |
2218 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
2219 | &prologue_end)) | |
2220 | { | |
2221 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 2222 | for unoptimized code) is to do the following: |
0d39a070 DJ |
2223 | |
2224 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
2225 | ||
2226 | if (sal.line == 0) | |
2227 | prologue_end = prev_pc; | |
2228 | else if (sal.end < prologue_end) | |
2229 | prologue_end = sal.end; | |
2230 | ||
2231 | This mechanism is very accurate so long as the optimizer | |
2232 | doesn't move any instructions from the function body into the | |
2233 | prologue. If this happens, sal.end will be the last | |
2234 | instruction in the first hunk of prologue code just before | |
2235 | the first instruction that the scheduler has moved from | |
2236 | the body to the prologue. | |
2237 | ||
2238 | In order to make sure that we scan all of the prologue | |
2239 | instructions, we use a slightly less accurate mechanism which | |
2240 | may scan more than necessary. To help compensate for this | |
2241 | lack of accuracy, the prologue scanning loop below contains | |
2242 | several clauses which'll cause the loop to terminate early if | |
2243 | an implausible prologue instruction is encountered. | |
2244 | ||
2245 | The expression | |
2246 | ||
2247 | prologue_start + 64 | |
2248 | ||
2249 | is a suitable endpoint since it accounts for the largest | |
2250 | possible prologue plus up to five instructions inserted by | |
2251 | the scheduler. */ | |
2252 | ||
2253 | if (prologue_end > prologue_start + 64) | |
2254 | { | |
2255 | prologue_end = prologue_start + 64; /* See above. */ | |
2256 | } | |
2257 | } | |
2258 | else | |
2259 | { | |
2260 | /* We have no symbol information. Our only option is to assume this | |
2261 | function has a standard stack frame and the normal frame register. | |
2262 | Then, we can find the value of our frame pointer on entrance to | |
2263 | the callee (or at the present moment if this is the innermost frame). | |
2264 | The value stored there should be the address of the stmfd + 8. */ | |
2265 | CORE_ADDR frame_loc; | |
7913a64c | 2266 | ULONGEST return_value; |
0d39a070 | 2267 | |
9e237747 | 2268 | /* AAPCS does not use a frame register, so we can abort here. */ |
345bd07c | 2269 | if (tdep->arm_abi == ARM_ABI_AAPCS) |
dda83cd7 | 2270 | return; |
9e237747 | 2271 | |
0d39a070 | 2272 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
2273 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
2274 | &return_value)) | |
dda83cd7 | 2275 | return; |
0d39a070 | 2276 | else |
dda83cd7 SM |
2277 | { |
2278 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 2279 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
2280 | prologue_end = prologue_start + 64; /* See above. */ |
2281 | } | |
0d39a070 DJ |
2282 | } |
2283 | ||
2284 | if (prev_pc < prologue_end) | |
2285 | prologue_end = prev_pc; | |
2286 | ||
9ecab40c SM |
2287 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
2288 | target_arm_instruction_reader ()); | |
c906108c SS |
2289 | } |
2290 | ||
eb5492fa | 2291 | static struct arm_prologue_cache * |
bd2b40ac | 2292 | arm_make_prologue_cache (frame_info_ptr this_frame) |
c906108c | 2293 | { |
eb5492fa DJ |
2294 | int reg; |
2295 | struct arm_prologue_cache *cache; | |
1ef3351b | 2296 | CORE_ADDR unwound_fp, prev_sp; |
c5aa993b | 2297 | |
35d5d4ee | 2298 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 2299 | arm_cache_init (cache, this_frame); |
c906108c | 2300 | |
a262aec2 | 2301 | arm_scan_prologue (this_frame, cache); |
848cfffb | 2302 | |
a262aec2 | 2303 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
2304 | if (unwound_fp == 0) |
2305 | return cache; | |
c906108c | 2306 | |
ae7e2f45 | 2307 | arm_gdbarch_tdep *tdep = |
08106042 | 2308 | gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2309 | |
1ef3351b YR |
2310 | prev_sp = unwound_fp + cache->framesize; |
2311 | arm_cache_set_active_sp_value (cache, tdep, prev_sp); | |
c906108c | 2312 | |
eb5492fa DJ |
2313 | /* Calculate actual addresses of saved registers using offsets |
2314 | determined by arm_scan_prologue. */ | |
a262aec2 | 2315 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
a9a87d35 | 2316 | if (cache->saved_regs[reg].is_addr ()) |
1ef3351b YR |
2317 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () + |
2318 | prev_sp); | |
eb5492fa DJ |
2319 | |
2320 | return cache; | |
c906108c SS |
2321 | } |
2322 | ||
c1ee9414 LM |
2323 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
2324 | ||
2325 | static enum unwind_stop_reason | |
bd2b40ac | 2326 | arm_prologue_unwind_stop_reason (frame_info_ptr this_frame, |
c1ee9414 LM |
2327 | void **this_cache) |
2328 | { | |
2329 | struct arm_prologue_cache *cache; | |
2330 | CORE_ADDR pc; | |
2331 | ||
2332 | if (*this_cache == NULL) | |
2333 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 2334 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
2335 | |
2336 | /* This is meant to halt the backtrace at "_start". */ | |
2337 | pc = get_frame_pc (this_frame); | |
345bd07c | 2338 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 2339 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (arch); |
345bd07c | 2340 | if (pc <= tdep->lowest_pc) |
c1ee9414 LM |
2341 | return UNWIND_OUTERMOST; |
2342 | ||
2343 | /* If we've hit a wall, stop. */ | |
ae7e2f45 | 2344 | if (arm_cache_get_prev_sp_value (cache, tdep) == 0) |
c1ee9414 LM |
2345 | return UNWIND_OUTERMOST; |
2346 | ||
2347 | return UNWIND_NO_REASON; | |
2348 | } | |
2349 | ||
eb5492fa DJ |
2350 | /* Our frame ID for a normal frame is the current function's starting PC |
2351 | and the caller's SP when we were called. */ | |
c906108c | 2352 | |
148754e5 | 2353 | static void |
bd2b40ac | 2354 | arm_prologue_this_id (frame_info_ptr this_frame, |
eb5492fa DJ |
2355 | void **this_cache, |
2356 | struct frame_id *this_id) | |
c906108c | 2357 | { |
eb5492fa DJ |
2358 | struct arm_prologue_cache *cache; |
2359 | struct frame_id id; | |
2c404490 | 2360 | CORE_ADDR pc, func; |
f079148d | 2361 | |
eb5492fa | 2362 | if (*this_cache == NULL) |
a262aec2 | 2363 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2364 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 2365 | |
ae7e2f45 | 2366 | arm_gdbarch_tdep *tdep |
08106042 | 2367 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2368 | |
0e9e9abd UW |
2369 | /* Use function start address as part of the frame ID. If we cannot |
2370 | identify the start address (due to missing symbol information), | |
2371 | fall back to just using the current PC. */ | |
c1ee9414 | 2372 | pc = get_frame_pc (this_frame); |
2c404490 | 2373 | func = get_frame_func (this_frame); |
0e9e9abd UW |
2374 | if (!func) |
2375 | func = pc; | |
2376 | ||
ae7e2f45 | 2377 | id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), func); |
eb5492fa | 2378 | *this_id = id; |
c906108c SS |
2379 | } |
2380 | ||
a262aec2 | 2381 | static struct value * |
bd2b40ac | 2382 | arm_prologue_prev_register (frame_info_ptr this_frame, |
eb5492fa | 2383 | void **this_cache, |
a262aec2 | 2384 | int prev_regnum) |
24de872b | 2385 | { |
24568a2c | 2386 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b | 2387 | struct arm_prologue_cache *cache; |
ef273377 | 2388 | CORE_ADDR sp_value; |
24de872b | 2389 | |
eb5492fa | 2390 | if (*this_cache == NULL) |
a262aec2 | 2391 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2392 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 2393 | |
08106042 | 2394 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
2395 | |
2396 | /* If this frame has signed the return address, mark it as so. */ | |
2397 | if (tdep->have_pacbti && cache->ra_signed_state.has_value () | |
2398 | && *cache->ra_signed_state) | |
2399 | set_frame_previous_pc_masked (this_frame); | |
2400 | ||
eb5492fa | 2401 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
2402 | instead. The prologue may save PC, but it will point into this |
2403 | frame's prologue, not the next frame's resume location. Also | |
2404 | strip the saved T bit. A valid LR may have the low bit set, but | |
2405 | a valid PC never does. */ | |
eb5492fa | 2406 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
2407 | { |
2408 | CORE_ADDR lr; | |
2409 | ||
2410 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2411 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 2412 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 2413 | } |
24de872b | 2414 | |
eb5492fa | 2415 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 2416 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2417 | The value was already reconstructed into PREV_SP. */ |
2418 | if (prev_regnum == ARM_SP_REGNUM) | |
ae7e2f45 CL |
2419 | return frame_unwind_got_constant (this_frame, prev_regnum, |
2420 | arm_cache_get_prev_sp_value (cache, tdep)); | |
eb5492fa | 2421 | |
ef273377 CL |
2422 | /* The value might be one of the alternative SP, if so, use the |
2423 | value already constructed. */ | |
d65edaa0 | 2424 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
2425 | { |
2426 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
2427 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
2428 | } | |
2429 | ||
b39cc962 DJ |
2430 | /* The CPSR may have been changed by the call instruction and by the |
2431 | called function. The only bit we can reconstruct is the T bit, | |
2432 | by checking the low bit of LR as of the call. This is a reliable | |
2433 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2434 | Thumb code, which could get away with a clear low bit as long as | |
2435 | the called function did not use bx. Guess that all other | |
2436 | bits are unchanged; the condition flags are presumably lost, | |
2437 | but the processor status is likely valid. */ | |
2438 | if (prev_regnum == ARM_PS_REGNUM) | |
2439 | { | |
8c9ae6df YR |
2440 | ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum); |
2441 | CORE_ADDR lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
b39cc962 | 2442 | |
8c9ae6df | 2443 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
b39cc962 DJ |
2444 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2445 | } | |
2446 | ||
a262aec2 DJ |
2447 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2448 | prev_regnum); | |
eb5492fa DJ |
2449 | } |
2450 | ||
6bd434d6 | 2451 | static frame_unwind arm_prologue_unwind = { |
a154d838 | 2452 | "arm prologue", |
eb5492fa | 2453 | NORMAL_FRAME, |
c1ee9414 | 2454 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2455 | arm_prologue_this_id, |
a262aec2 DJ |
2456 | arm_prologue_prev_register, |
2457 | NULL, | |
2458 | default_frame_sniffer | |
eb5492fa DJ |
2459 | }; |
2460 | ||
0e9e9abd UW |
2461 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2462 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2463 | personality routines; the cache will contain only the frame unwinding | |
2464 | instructions associated with the entry (not the descriptors). */ | |
2465 | ||
0e9e9abd UW |
2466 | struct arm_exidx_entry |
2467 | { | |
227031b2 | 2468 | CORE_ADDR addr; |
0e9e9abd | 2469 | gdb_byte *entry; |
7a5d944b TT |
2470 | |
2471 | bool operator< (const arm_exidx_entry &other) const | |
2472 | { | |
2473 | return addr < other.addr; | |
2474 | } | |
0e9e9abd | 2475 | }; |
0e9e9abd UW |
2476 | |
2477 | struct arm_exidx_data | |
2478 | { | |
7a5d944b | 2479 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2480 | }; |
2481 | ||
a2726d4f | 2482 | /* Per-BFD key to store exception handling information. */ |
08b8a139 | 2483 | static const registry<bfd>::key<arm_exidx_data> arm_exidx_data_key; |
0e9e9abd UW |
2484 | |
2485 | static struct obj_section * | |
2486 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2487 | { | |
2488 | struct obj_section *osect; | |
2489 | ||
2490 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2491 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2492 | { |
2493 | bfd_vma start, size; | |
fd361982 AM |
2494 | start = bfd_section_vma (osect->the_bfd_section); |
2495 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2496 | |
2497 | if (start <= vma && vma < start + size) | |
2498 | return osect; | |
2499 | } | |
2500 | ||
2501 | return NULL; | |
2502 | } | |
2503 | ||
2504 | /* Parse contents of exception table and exception index sections | |
2505 | of OBJFILE, and fill in the exception table entry cache. | |
2506 | ||
2507 | For each entry that refers to a standard ARM-defined personality | |
2508 | routine, extract the frame unwinding instructions (from either | |
2509 | the index or the table section). The unwinding instructions | |
2510 | are normalized by: | |
2511 | - extracting them from the rest of the table data | |
2512 | - converting to host endianness | |
2513 | - appending the implicit 0xb0 ("Finish") code | |
2514 | ||
2515 | The extracted and normalized instructions are stored for later | |
2516 | retrieval by the arm_find_exidx_entry routine. */ | |
2517 | ||
2518 | static void | |
2519 | arm_exidx_new_objfile (struct objfile *objfile) | |
2520 | { | |
0e9e9abd UW |
2521 | struct arm_exidx_data *data; |
2522 | asection *exidx, *extab; | |
2523 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2524 | LONGEST i; |
2525 | ||
2526 | /* If we've already touched this file, do nothing. */ | |
98badbfd | 2527 | if (!objfile || arm_exidx_data_key.get (objfile->obfd.get ()) != NULL) |
0e9e9abd UW |
2528 | return; |
2529 | ||
2530 | /* Read contents of exception table and index. */ | |
98badbfd TT |
2531 | exidx = bfd_get_section_by_name (objfile->obfd.get (), |
2532 | ELF_STRING_ARM_unwind); | |
984c7238 | 2533 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2534 | if (exidx) |
2535 | { | |
fd361982 AM |
2536 | exidx_vma = bfd_section_vma (exidx); |
2537 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd | 2538 | |
98badbfd | 2539 | if (!bfd_get_section_contents (objfile->obfd.get (), exidx, |
984c7238 TT |
2540 | exidx_data.data (), 0, |
2541 | exidx_data.size ())) | |
2542 | return; | |
0e9e9abd UW |
2543 | } |
2544 | ||
98badbfd | 2545 | extab = bfd_get_section_by_name (objfile->obfd.get (), ".ARM.extab"); |
984c7238 | 2546 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2547 | if (extab) |
2548 | { | |
fd361982 AM |
2549 | extab_vma = bfd_section_vma (extab); |
2550 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd | 2551 | |
98badbfd | 2552 | if (!bfd_get_section_contents (objfile->obfd.get (), extab, |
984c7238 TT |
2553 | extab_data.data (), 0, |
2554 | extab_data.size ())) | |
2555 | return; | |
0e9e9abd UW |
2556 | } |
2557 | ||
2558 | /* Allocate exception table data structure. */ | |
98badbfd | 2559 | data = arm_exidx_data_key.emplace (objfile->obfd.get ()); |
7a5d944b | 2560 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2561 | |
2562 | /* Fill in exception table. */ | |
984c7238 | 2563 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2564 | { |
2565 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2566 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2567 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2568 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2569 | bfd_vma addr = 0, word = 0; |
2570 | int n_bytes = 0, n_words = 0; | |
2571 | struct obj_section *sec; | |
2572 | gdb_byte *entry = NULL; | |
2573 | ||
2574 | /* Extract address of start of function. */ | |
2575 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2576 | idx += exidx_vma + i * 8; | |
2577 | ||
2578 | /* Find section containing function and compute section offset. */ | |
2579 | sec = arm_obj_section_from_vma (objfile, idx); | |
2580 | if (sec == NULL) | |
2581 | continue; | |
fd361982 | 2582 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2583 | |
2584 | /* Determine address of exception table entry. */ | |
2585 | if (val == 1) | |
2586 | { | |
2587 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2588 | } | |
2589 | else if ((val & 0xff000000) == 0x80000000) | |
2590 | { | |
2591 | /* Exception table entry embedded in .ARM.exidx | |
2592 | -- must be short form. */ | |
2593 | word = val; | |
2594 | n_bytes = 3; | |
2595 | } | |
2596 | else if (!(val & 0x80000000)) | |
2597 | { | |
2598 | /* Exception table entry in .ARM.extab. */ | |
2599 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2600 | addr += exidx_vma + i * 8 + 4; | |
2601 | ||
984c7238 | 2602 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2603 | { |
2604 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2605 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2606 | addr += 4; |
2607 | ||
2608 | if ((word & 0xff000000) == 0x80000000) | |
2609 | { | |
2610 | /* Short form. */ | |
2611 | n_bytes = 3; | |
2612 | } | |
2613 | else if ((word & 0xff000000) == 0x81000000 | |
2614 | || (word & 0xff000000) == 0x82000000) | |
2615 | { | |
2616 | /* Long form. */ | |
2617 | n_bytes = 2; | |
2618 | n_words = ((word >> 16) & 0xff); | |
2619 | } | |
2620 | else if (!(word & 0x80000000)) | |
2621 | { | |
2622 | bfd_vma pers; | |
2623 | struct obj_section *pers_sec; | |
2624 | int gnu_personality = 0; | |
2625 | ||
2626 | /* Custom personality routine. */ | |
2627 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2628 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2629 | ||
2630 | /* Check whether we've got one of the variants of the | |
2631 | GNU personality routines. */ | |
2632 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2633 | if (pers_sec) | |
2634 | { | |
2635 | static const char *personality[] = | |
2636 | { | |
2637 | "__gcc_personality_v0", | |
2638 | "__gxx_personality_v0", | |
2639 | "__gcj_personality_v0", | |
2640 | "__gnu_objc_personality_v0", | |
2641 | NULL | |
2642 | }; | |
2643 | ||
0c1bcd23 | 2644 | CORE_ADDR pc = pers + pers_sec->offset (); |
0e9e9abd UW |
2645 | int k; |
2646 | ||
2647 | for (k = 0; personality[k]; k++) | |
2648 | if (lookup_minimal_symbol_by_pc_name | |
2649 | (pc, personality[k], objfile)) | |
2650 | { | |
2651 | gnu_personality = 1; | |
2652 | break; | |
2653 | } | |
2654 | } | |
2655 | ||
2656 | /* If so, the next word contains a word count in the high | |
2657 | byte, followed by the same unwind instructions as the | |
2658 | pre-defined forms. */ | |
2659 | if (gnu_personality | |
984c7238 | 2660 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2661 | { |
2662 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2663 | (extab_data.data () |
2664 | + addr - extab_vma)); | |
0e9e9abd UW |
2665 | addr += 4; |
2666 | n_bytes = 3; | |
2667 | n_words = ((word >> 24) & 0xff); | |
2668 | } | |
2669 | } | |
2670 | } | |
2671 | } | |
2672 | ||
2673 | /* Sanity check address. */ | |
2674 | if (n_words) | |
984c7238 TT |
2675 | if (addr < extab_vma |
2676 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2677 | n_words = n_bytes = 0; |
2678 | ||
2679 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2680 | significant bytes are valid), followed by N_WORDS words in the | |
2681 | extab section starting at ADDR. */ | |
2682 | if (n_bytes || n_words) | |
2683 | { | |
224c3ddb SM |
2684 | gdb_byte *p = entry |
2685 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2686 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2687 | |
2688 | while (n_bytes--) | |
2689 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2690 | ||
2691 | while (n_words--) | |
2692 | { | |
2693 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2694 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2695 | addr += 4; |
2696 | ||
2697 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2698 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2699 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2700 | *p++ = (gdb_byte) (word & 0xff); | |
2701 | } | |
2702 | ||
2703 | /* Implied "Finish" to terminate the list. */ | |
2704 | *p++ = 0xb0; | |
2705 | } | |
2706 | ||
2707 | /* Push entry onto vector. They are guaranteed to always | |
2708 | appear in order of increasing addresses. */ | |
2709 | new_exidx_entry.addr = idx; | |
2710 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2711 | data->section_maps[sec->the_bfd_section->index].push_back |
2712 | (new_exidx_entry); | |
0e9e9abd | 2713 | } |
0e9e9abd UW |
2714 | } |
2715 | ||
2716 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2717 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2718 | set *START to the start of the region covered by this entry. */ | |
2719 | ||
2720 | static gdb_byte * | |
2721 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2722 | { | |
2723 | struct obj_section *sec; | |
2724 | ||
2725 | sec = find_pc_section (memaddr); | |
2726 | if (sec != NULL) | |
2727 | { | |
2728 | struct arm_exidx_data *data; | |
0c1bcd23 | 2729 | struct arm_exidx_entry map_key = { memaddr - sec->addr (), 0 }; |
0e9e9abd | 2730 | |
98badbfd | 2731 | data = arm_exidx_data_key.get (sec->objfile->obfd.get ()); |
0e9e9abd UW |
2732 | if (data != NULL) |
2733 | { | |
7a5d944b TT |
2734 | std::vector<arm_exidx_entry> &map |
2735 | = data->section_maps[sec->the_bfd_section->index]; | |
2736 | if (!map.empty ()) | |
0e9e9abd | 2737 | { |
7a5d944b | 2738 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2739 | |
7a5d944b | 2740 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2741 | point. If the following symbol starts at this exact |
2742 | address, we use that; otherwise, the preceding | |
2743 | exception table entry covers this address. */ | |
7a5d944b | 2744 | if (idx < map.end ()) |
0e9e9abd | 2745 | { |
7a5d944b | 2746 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2747 | { |
2748 | if (start) | |
0c1bcd23 | 2749 | *start = idx->addr + sec->addr (); |
7a5d944b | 2750 | return idx->entry; |
0e9e9abd UW |
2751 | } |
2752 | } | |
2753 | ||
7a5d944b | 2754 | if (idx > map.begin ()) |
0e9e9abd | 2755 | { |
7a5d944b | 2756 | idx = idx - 1; |
0e9e9abd | 2757 | if (start) |
0c1bcd23 | 2758 | *start = idx->addr + sec->addr (); |
7a5d944b | 2759 | return idx->entry; |
0e9e9abd UW |
2760 | } |
2761 | } | |
2762 | } | |
2763 | } | |
2764 | ||
2765 | return NULL; | |
2766 | } | |
2767 | ||
2768 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2769 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2770 | return a prologue cache structure describing how to unwind this frame. | |
2771 | ||
2772 | Return NULL if the unwinding instruction list contains a "spare", | |
2773 | "reserved" or "refuse to unwind" instruction as defined in section | |
2774 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2775 | for the ARM Architecture" document. */ | |
2776 | ||
2777 | static struct arm_prologue_cache * | |
bd2b40ac | 2778 | arm_exidx_fill_cache (frame_info_ptr this_frame, gdb_byte *entry) |
0e9e9abd UW |
2779 | { |
2780 | CORE_ADDR vsp = 0; | |
2781 | int vsp_valid = 0; | |
2782 | ||
2783 | struct arm_prologue_cache *cache; | |
2784 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 2785 | arm_cache_init (cache, this_frame); |
0e9e9abd UW |
2786 | |
2787 | for (;;) | |
2788 | { | |
2789 | gdb_byte insn; | |
2790 | ||
2791 | /* Whenever we reload SP, we actually have to retrieve its | |
2792 | actual value in the current frame. */ | |
2793 | if (!vsp_valid) | |
2794 | { | |
a9a87d35 | 2795 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
0e9e9abd | 2796 | { |
098caef4 | 2797 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2798 | vsp = get_frame_register_unsigned (this_frame, reg); |
2799 | } | |
2800 | else | |
2801 | { | |
098caef4 | 2802 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr (); |
0e9e9abd UW |
2803 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); |
2804 | } | |
2805 | ||
2806 | vsp_valid = 1; | |
2807 | } | |
2808 | ||
2809 | /* Decode next unwind instruction. */ | |
2810 | insn = *entry++; | |
2811 | ||
2812 | if ((insn & 0xc0) == 0) | |
2813 | { | |
2814 | int offset = insn & 0x3f; | |
2815 | vsp += (offset << 2) + 4; | |
2816 | } | |
2817 | else if ((insn & 0xc0) == 0x40) | |
2818 | { | |
2819 | int offset = insn & 0x3f; | |
2820 | vsp -= (offset << 2) + 4; | |
2821 | } | |
2822 | else if ((insn & 0xf0) == 0x80) | |
2823 | { | |
2824 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2825 | int i; | |
2826 | ||
2827 | /* The special case of an all-zero mask identifies | |
2828 | "Refuse to unwind". We return NULL to fall back | |
2829 | to the prologue analyzer. */ | |
2830 | if (mask == 0) | |
2831 | return NULL; | |
2832 | ||
2833 | /* Pop registers r4..r15 under mask. */ | |
2834 | for (i = 0; i < 12; i++) | |
2835 | if (mask & (1 << i)) | |
2836 | { | |
098caef4 | 2837 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2838 | vsp += 4; |
2839 | } | |
2840 | ||
2841 | /* Special-case popping SP -- we need to reload vsp. */ | |
2842 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2843 | vsp_valid = 0; | |
2844 | } | |
2845 | else if ((insn & 0xf0) == 0x90) | |
2846 | { | |
2847 | int reg = insn & 0xf; | |
2848 | ||
2849 | /* Reserved cases. */ | |
2850 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2851 | return NULL; | |
2852 | ||
2853 | /* Set SP from another register and mark VSP for reload. */ | |
2854 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2855 | vsp_valid = 0; | |
2856 | } | |
2857 | else if ((insn & 0xf0) == 0xa0) | |
2858 | { | |
2859 | int count = insn & 0x7; | |
2860 | int pop_lr = (insn & 0x8) != 0; | |
2861 | int i; | |
2862 | ||
2863 | /* Pop r4..r[4+count]. */ | |
2864 | for (i = 0; i <= count; i++) | |
2865 | { | |
098caef4 | 2866 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2867 | vsp += 4; |
2868 | } | |
2869 | ||
2870 | /* If indicated by flag, pop LR as well. */ | |
2871 | if (pop_lr) | |
2872 | { | |
098caef4 | 2873 | cache->saved_regs[ARM_LR_REGNUM].set_addr (vsp); |
0e9e9abd UW |
2874 | vsp += 4; |
2875 | } | |
2876 | } | |
2877 | else if (insn == 0xb0) | |
2878 | { | |
2879 | /* We could only have updated PC by popping into it; if so, it | |
2880 | will show up as address. Otherwise, copy LR into PC. */ | |
a9a87d35 | 2881 | if (!cache->saved_regs[ARM_PC_REGNUM].is_addr ()) |
0e9e9abd UW |
2882 | cache->saved_regs[ARM_PC_REGNUM] |
2883 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2884 | ||
2885 | /* We're done. */ | |
2886 | break; | |
2887 | } | |
2888 | else if (insn == 0xb1) | |
2889 | { | |
2890 | int mask = *entry++; | |
2891 | int i; | |
2892 | ||
2893 | /* All-zero mask and mask >= 16 is "spare". */ | |
2894 | if (mask == 0 || mask >= 16) | |
2895 | return NULL; | |
2896 | ||
2897 | /* Pop r0..r3 under mask. */ | |
2898 | for (i = 0; i < 4; i++) | |
2899 | if (mask & (1 << i)) | |
2900 | { | |
098caef4 | 2901 | cache->saved_regs[i].set_addr (vsp); |
0e9e9abd UW |
2902 | vsp += 4; |
2903 | } | |
2904 | } | |
2905 | else if (insn == 0xb2) | |
2906 | { | |
2907 | ULONGEST offset = 0; | |
2908 | unsigned shift = 0; | |
2909 | ||
2910 | do | |
2911 | { | |
2912 | offset |= (*entry & 0x7f) << shift; | |
2913 | shift += 7; | |
2914 | } | |
2915 | while (*entry++ & 0x80); | |
2916 | ||
2917 | vsp += 0x204 + (offset << 2); | |
2918 | } | |
2919 | else if (insn == 0xb3) | |
2920 | { | |
2921 | int start = *entry >> 4; | |
2922 | int count = (*entry++) & 0xf; | |
2923 | int i; | |
2924 | ||
2925 | /* Only registers D0..D15 are valid here. */ | |
2926 | if (start + count >= 16) | |
2927 | return NULL; | |
2928 | ||
2929 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2930 | for (i = 0; i <= count; i++) | |
2931 | { | |
098caef4 | 2932 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2933 | vsp += 8; |
2934 | } | |
2935 | ||
2936 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2937 | vsp += 4; | |
2938 | } | |
2939 | else if ((insn & 0xf8) == 0xb8) | |
2940 | { | |
2941 | int count = insn & 0x7; | |
2942 | int i; | |
2943 | ||
2944 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2945 | for (i = 0; i <= count; i++) | |
2946 | { | |
098caef4 | 2947 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2948 | vsp += 8; |
2949 | } | |
2950 | ||
2951 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2952 | vsp += 4; | |
2953 | } | |
2954 | else if (insn == 0xc6) | |
2955 | { | |
2956 | int start = *entry >> 4; | |
2957 | int count = (*entry++) & 0xf; | |
2958 | int i; | |
2959 | ||
2960 | /* Only registers WR0..WR15 are valid. */ | |
2961 | if (start + count >= 16) | |
2962 | return NULL; | |
2963 | ||
2964 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2965 | for (i = 0; i <= count; i++) | |
2966 | { | |
098caef4 | 2967 | cache->saved_regs[ARM_WR0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2968 | vsp += 8; |
2969 | } | |
2970 | } | |
2971 | else if (insn == 0xc7) | |
2972 | { | |
2973 | int mask = *entry++; | |
2974 | int i; | |
2975 | ||
2976 | /* All-zero mask and mask >= 16 is "spare". */ | |
2977 | if (mask == 0 || mask >= 16) | |
2978 | return NULL; | |
2979 | ||
2980 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2981 | for (i = 0; i < 4; i++) | |
2982 | if (mask & (1 << i)) | |
2983 | { | |
098caef4 | 2984 | cache->saved_regs[ARM_WCGR0_REGNUM + i].set_addr (vsp); |
0e9e9abd UW |
2985 | vsp += 4; |
2986 | } | |
2987 | } | |
2988 | else if ((insn & 0xf8) == 0xc0) | |
2989 | { | |
2990 | int count = insn & 0x7; | |
2991 | int i; | |
2992 | ||
2993 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2994 | for (i = 0; i <= count; i++) | |
2995 | { | |
098caef4 | 2996 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].set_addr (vsp); |
0e9e9abd UW |
2997 | vsp += 8; |
2998 | } | |
2999 | } | |
3000 | else if (insn == 0xc8) | |
3001 | { | |
3002 | int start = *entry >> 4; | |
3003 | int count = (*entry++) & 0xf; | |
3004 | int i; | |
3005 | ||
3006 | /* Only registers D0..D31 are valid. */ | |
3007 | if (start + count >= 16) | |
3008 | return NULL; | |
3009 | ||
3010 | /* Pop VFP double-precision registers | |
3011 | D[16+start]..D[16+start+count]. */ | |
3012 | for (i = 0; i <= count; i++) | |
3013 | { | |
098caef4 | 3014 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].set_addr (vsp); |
0e9e9abd UW |
3015 | vsp += 8; |
3016 | } | |
3017 | } | |
3018 | else if (insn == 0xc9) | |
3019 | { | |
3020 | int start = *entry >> 4; | |
3021 | int count = (*entry++) & 0xf; | |
3022 | int i; | |
3023 | ||
3024 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
3025 | for (i = 0; i <= count; i++) | |
3026 | { | |
098caef4 | 3027 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
3028 | vsp += 8; |
3029 | } | |
3030 | } | |
3031 | else if ((insn & 0xf8) == 0xd0) | |
3032 | { | |
3033 | int count = insn & 0x7; | |
3034 | int i; | |
3035 | ||
3036 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
3037 | for (i = 0; i <= count; i++) | |
3038 | { | |
098caef4 | 3039 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
3040 | vsp += 8; |
3041 | } | |
3042 | } | |
3043 | else | |
3044 | { | |
3045 | /* Everything else is "spare". */ | |
3046 | return NULL; | |
3047 | } | |
3048 | } | |
3049 | ||
3050 | /* If we restore SP from a register, assume this was the frame register. | |
3051 | Otherwise just fall back to SP as frame register. */ | |
a9a87d35 | 3052 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
098caef4 | 3053 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
3054 | else |
3055 | cache->framereg = ARM_SP_REGNUM; | |
3056 | ||
3057 | /* Determine offset to previous frame. */ | |
3058 | cache->framesize | |
3059 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
3060 | ||
3061 | /* We already got the previous SP. */ | |
ae7e2f45 | 3062 | arm_gdbarch_tdep *tdep |
08106042 | 3063 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3064 | arm_cache_set_active_sp_value (cache, tdep, vsp); |
0e9e9abd UW |
3065 | |
3066 | return cache; | |
3067 | } | |
3068 | ||
3069 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
3070 | already computes a filled-in prologue cache, which is then used | |
3071 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
3072 | routines also used for prologue-parsing based unwinding. */ | |
3073 | ||
3074 | static int | |
3075 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3076 | frame_info_ptr this_frame, |
0e9e9abd UW |
3077 | void **this_prologue_cache) |
3078 | { | |
3079 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3080 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3081 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
3082 | struct arm_prologue_cache *cache; | |
3083 | gdb_byte *entry; | |
3084 | ||
3085 | /* See if we have an ARM exception table entry covering this address. */ | |
3086 | addr_in_block = get_frame_address_in_block (this_frame); | |
3087 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
3088 | if (!entry) | |
3089 | return 0; | |
3090 | ||
3091 | /* The ARM exception table does not describe unwind information | |
3092 | for arbitrary PC values, but is guaranteed to be correct only | |
3093 | at call sites. We have to decide here whether we want to use | |
3094 | ARM exception table information for this frame, or fall back | |
3095 | to using prologue parsing. (Note that if we have DWARF CFI, | |
3096 | this sniffer isn't even called -- CFI is always preferred.) | |
3097 | ||
3098 | Before we make this decision, however, we check whether we | |
3099 | actually have *symbol* information for the current frame. | |
3100 | If not, prologue parsing would not work anyway, so we might | |
3101 | as well use the exception table and hope for the best. */ | |
3102 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
3103 | { | |
3104 | int exc_valid = 0; | |
3105 | ||
3106 | /* If the next frame is "normal", we are at a call site in this | |
3107 | frame, so exception information is guaranteed to be valid. */ | |
3108 | if (get_next_frame (this_frame) | |
3109 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
3110 | exc_valid = 1; | |
3111 | ||
3112 | /* We also assume exception information is valid if we're currently | |
3113 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
3114 | ensure this, so that e.g. pthread cancellation works. */ |
3115 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 3116 | { |
7913a64c | 3117 | ULONGEST insn; |
416dc9c6 | 3118 | |
7913a64c YQ |
3119 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
3120 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
3121 | && (insn & 0xff00) == 0xdf00 /* svc */) |
3122 | exc_valid = 1; | |
0e9e9abd | 3123 | } |
d9311bfa AT |
3124 | else |
3125 | { | |
7913a64c | 3126 | ULONGEST insn; |
416dc9c6 | 3127 | |
7913a64c YQ |
3128 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
3129 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
3130 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
3131 | exc_valid = 1; | |
3132 | } | |
3133 | ||
0e9e9abd UW |
3134 | /* Bail out if we don't know that exception information is valid. */ |
3135 | if (!exc_valid) | |
3136 | return 0; | |
3137 | ||
3138 | /* The ARM exception index does not mark the *end* of the region | |
3139 | covered by the entry, and some functions will not have any entry. | |
3140 | To correctly recognize the end of the covered region, the linker | |
3141 | should have inserted dummy records with a CANTUNWIND marker. | |
3142 | ||
3143 | Unfortunately, current versions of GNU ld do not reliably do | |
3144 | this, and thus we may have found an incorrect entry above. | |
3145 | As a (temporary) sanity check, we only use the entry if it | |
3146 | lies *within* the bounds of the function. Note that this check | |
3147 | might reject perfectly valid entries that just happen to cover | |
3148 | multiple functions; therefore this check ought to be removed | |
3149 | once the linker is fixed. */ | |
3150 | if (func_start > exidx_region) | |
3151 | return 0; | |
3152 | } | |
3153 | ||
3154 | /* Decode the list of unwinding instructions into a prologue cache. | |
3155 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
3156 | cache = arm_exidx_fill_cache (this_frame, entry); | |
3157 | if (!cache) | |
3158 | return 0; | |
3159 | ||
3160 | *this_prologue_cache = cache; | |
3161 | return 1; | |
3162 | } | |
3163 | ||
3164 | struct frame_unwind arm_exidx_unwind = { | |
a154d838 | 3165 | "arm exidx", |
0e9e9abd | 3166 | NORMAL_FRAME, |
8fbca658 | 3167 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
3168 | arm_prologue_this_id, |
3169 | arm_prologue_prev_register, | |
3170 | NULL, | |
3171 | arm_exidx_unwind_sniffer | |
3172 | }; | |
3173 | ||
779aa56f | 3174 | static struct arm_prologue_cache * |
bd2b40ac | 3175 | arm_make_epilogue_frame_cache (frame_info_ptr this_frame) |
779aa56f YQ |
3176 | { |
3177 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
3178 | int reg; |
3179 | ||
3180 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3181 | arm_cache_init (cache, this_frame); |
779aa56f YQ |
3182 | |
3183 | /* Still rely on the offset calculated from prologue. */ | |
3184 | arm_scan_prologue (this_frame, cache); | |
3185 | ||
3186 | /* Since we are in epilogue, the SP has been restored. */ | |
ae7e2f45 | 3187 | arm_gdbarch_tdep *tdep |
08106042 | 3188 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3189 | arm_cache_set_active_sp_value (cache, tdep, |
3190 | get_frame_register_unsigned (this_frame, | |
3191 | ARM_SP_REGNUM)); | |
779aa56f YQ |
3192 | |
3193 | /* Calculate actual addresses of saved registers using offsets | |
3194 | determined by arm_scan_prologue. */ | |
3195 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 3196 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 | 3197 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
ae7e2f45 | 3198 | + arm_cache_get_prev_sp_value (cache, tdep)); |
779aa56f YQ |
3199 | |
3200 | return cache; | |
3201 | } | |
3202 | ||
3203 | /* Implementation of function hook 'this_id' in | |
3204 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3205 | ||
3206 | static void | |
bd2b40ac | 3207 | arm_epilogue_frame_this_id (frame_info_ptr this_frame, |
779aa56f YQ |
3208 | void **this_cache, |
3209 | struct frame_id *this_id) | |
3210 | { | |
3211 | struct arm_prologue_cache *cache; | |
3212 | CORE_ADDR pc, func; | |
3213 | ||
3214 | if (*this_cache == NULL) | |
3215 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
3216 | cache = (struct arm_prologue_cache *) *this_cache; | |
3217 | ||
3218 | /* Use function start address as part of the frame ID. If we cannot | |
3219 | identify the start address (due to missing symbol information), | |
3220 | fall back to just using the current PC. */ | |
3221 | pc = get_frame_pc (this_frame); | |
3222 | func = get_frame_func (this_frame); | |
fb3f3d25 | 3223 | if (func == 0) |
779aa56f YQ |
3224 | func = pc; |
3225 | ||
ae7e2f45 | 3226 | arm_gdbarch_tdep *tdep |
08106042 | 3227 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3228 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), pc); |
779aa56f YQ |
3229 | } |
3230 | ||
3231 | /* Implementation of function hook 'prev_register' in | |
3232 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3233 | ||
3234 | static struct value * | |
bd2b40ac | 3235 | arm_epilogue_frame_prev_register (frame_info_ptr this_frame, |
779aa56f YQ |
3236 | void **this_cache, int regnum) |
3237 | { | |
779aa56f YQ |
3238 | if (*this_cache == NULL) |
3239 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
3240 | |
3241 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
3242 | } | |
3243 | ||
3244 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
3245 | CORE_ADDR pc); | |
3246 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
3247 | CORE_ADDR pc); | |
3248 | ||
3249 | /* Implementation of function hook 'sniffer' in | |
3250 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3251 | ||
3252 | static int | |
3253 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3254 | frame_info_ptr this_frame, |
779aa56f YQ |
3255 | void **this_prologue_cache) |
3256 | { | |
3257 | if (frame_relative_level (this_frame) == 0) | |
3258 | { | |
3259 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3260 | CORE_ADDR pc = get_frame_pc (this_frame); | |
3261 | ||
3262 | if (arm_frame_is_thumb (this_frame)) | |
3263 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3264 | else | |
3265 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3266 | } | |
3267 | else | |
3268 | return 0; | |
3269 | } | |
3270 | ||
3271 | /* Frame unwinder from epilogue. */ | |
3272 | ||
3273 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
3274 | { | |
a154d838 | 3275 | "arm epilogue", |
779aa56f YQ |
3276 | NORMAL_FRAME, |
3277 | default_frame_unwind_stop_reason, | |
3278 | arm_epilogue_frame_this_id, | |
3279 | arm_epilogue_frame_prev_register, | |
3280 | NULL, | |
3281 | arm_epilogue_frame_sniffer, | |
3282 | }; | |
3283 | ||
80d8d390 YQ |
3284 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
3285 | trampoline, return the target PC. Otherwise return 0. | |
3286 | ||
3287 | void call0a (char c, short s, int i, long l) {} | |
3288 | ||
3289 | int main (void) | |
3290 | { | |
3291 | (*pointer_to_call0a) (c, s, i, l); | |
3292 | } | |
3293 | ||
3294 | Instead of calling a stub library function _call_via_xx (xx is | |
3295 | the register name), GCC may inline the trampoline in the object | |
3296 | file as below (register r2 has the address of call0a). | |
3297 | ||
3298 | .global main | |
3299 | .type main, %function | |
3300 | ... | |
3301 | bl .L1 | |
3302 | ... | |
3303 | .size main, .-main | |
3304 | ||
3305 | .L1: | |
3306 | bx r2 | |
3307 | ||
3308 | The trampoline 'bx r2' doesn't belong to main. */ | |
3309 | ||
3310 | static CORE_ADDR | |
bd2b40ac | 3311 | arm_skip_bx_reg (frame_info_ptr frame, CORE_ADDR pc) |
80d8d390 YQ |
3312 | { |
3313 | /* The heuristics of recognizing such trampoline is that FRAME is | |
3314 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
3315 | if (arm_frame_is_thumb (frame)) | |
3316 | { | |
3317 | gdb_byte buf[2]; | |
3318 | ||
3319 | if (target_read_memory (pc, buf, 2) == 0) | |
3320 | { | |
3321 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
3322 | enum bfd_endian byte_order_for_code | |
3323 | = gdbarch_byte_order_for_code (gdbarch); | |
3324 | uint16_t insn | |
3325 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3326 | ||
3327 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3328 | { | |
3329 | CORE_ADDR dest | |
3330 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
3331 | ||
3332 | /* Clear the LSB so that gdb core sets step-resume | |
3333 | breakpoint at the right address. */ | |
3334 | return UNMAKE_THUMB_ADDR (dest); | |
3335 | } | |
3336 | } | |
3337 | } | |
3338 | ||
3339 | return 0; | |
3340 | } | |
3341 | ||
909cf6ea | 3342 | static struct arm_prologue_cache * |
bd2b40ac | 3343 | arm_make_stub_cache (frame_info_ptr this_frame) |
909cf6ea | 3344 | { |
909cf6ea | 3345 | struct arm_prologue_cache *cache; |
909cf6ea | 3346 | |
35d5d4ee | 3347 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 3348 | arm_cache_init (cache, this_frame); |
909cf6ea | 3349 | |
ae7e2f45 | 3350 | arm_gdbarch_tdep *tdep |
08106042 | 3351 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3352 | arm_cache_set_active_sp_value (cache, tdep, |
3353 | get_frame_register_unsigned (this_frame, | |
3354 | ARM_SP_REGNUM)); | |
909cf6ea DJ |
3355 | |
3356 | return cache; | |
3357 | } | |
3358 | ||
3359 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3360 | ||
3361 | static void | |
bd2b40ac | 3362 | arm_stub_this_id (frame_info_ptr this_frame, |
909cf6ea DJ |
3363 | void **this_cache, |
3364 | struct frame_id *this_id) | |
3365 | { | |
3366 | struct arm_prologue_cache *cache; | |
3367 | ||
3368 | if (*this_cache == NULL) | |
a262aec2 | 3369 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 3370 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 3371 | |
ae7e2f45 | 3372 | arm_gdbarch_tdep *tdep |
08106042 | 3373 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3374 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
3375 | get_frame_pc (this_frame)); | |
909cf6ea DJ |
3376 | } |
3377 | ||
a262aec2 DJ |
3378 | static int |
3379 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3380 | frame_info_ptr this_frame, |
a262aec2 | 3381 | void **this_prologue_cache) |
909cf6ea | 3382 | { |
93d42b30 | 3383 | CORE_ADDR addr_in_block; |
948f8e3d | 3384 | gdb_byte dummy[4]; |
18d18ac8 YQ |
3385 | CORE_ADDR pc, start_addr; |
3386 | const char *name; | |
909cf6ea | 3387 | |
a262aec2 | 3388 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 3389 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 3390 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
3391 | /* We also use the stub winder if the target memory is unreadable |
3392 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
3393 | || target_read_memory (pc, dummy, 4) != 0) |
3394 | return 1; | |
3395 | ||
3396 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
3397 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 3398 | return 1; |
909cf6ea | 3399 | |
a262aec2 | 3400 | return 0; |
909cf6ea DJ |
3401 | } |
3402 | ||
a262aec2 | 3403 | struct frame_unwind arm_stub_unwind = { |
a154d838 | 3404 | "arm stub", |
a262aec2 | 3405 | NORMAL_FRAME, |
8fbca658 | 3406 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
3407 | arm_stub_this_id, |
3408 | arm_prologue_prev_register, | |
3409 | NULL, | |
3410 | arm_stub_unwind_sniffer | |
3411 | }; | |
3412 | ||
2ae28aa9 YQ |
3413 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
3414 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
3415 | returned. */ | |
3416 | ||
3417 | static struct arm_prologue_cache * | |
bd2b40ac | 3418 | arm_m_exception_cache (frame_info_ptr this_frame) |
2ae28aa9 YQ |
3419 | { |
3420 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
08106042 | 3421 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
2ae28aa9 | 3422 | struct arm_prologue_cache *cache; |
2ae28aa9 YQ |
3423 | |
3424 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3425 | arm_cache_init (cache, this_frame); |
2ae28aa9 | 3426 | |
55ea94da FH |
3427 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
3428 | describes which bits in LR that define which stack was used prior | |
3429 | to the exception and if FPU is used (causing extended stack frame). */ | |
3430 | ||
8b73ee20 LM |
3431 | /* In the lockup state PC contains a lockup magic value. |
3432 | The PC value of the the next outer frame is irreversibly | |
3433 | lost. The other registers are intact so LR likely contains | |
3434 | PC of some frame next to the outer one, but we cannot analyze | |
3435 | the next outer frame without knowing its PC | |
3436 | therefore we do not know SP fixup for this frame. | |
3437 | Some heuristics to resynchronize SP might be possible. | |
3438 | For simplicity, just terminate the unwinding to prevent it going | |
3439 | astray and attempting to read data/addresses it shouldn't, | |
3440 | which may cause further issues due to side-effects. */ | |
3441 | CORE_ADDR pc = get_frame_pc (this_frame); | |
3442 | if (arm_m_addr_is_lockup (pc)) | |
3443 | { | |
3444 | /* The lockup can be real just in the innermost frame | |
3445 | as the CPU is stopped and cannot create more frames. | |
3446 | If we hit lockup magic PC in the other frame, it is | |
3447 | just a sentinel at the top of stack: do not warn then. */ | |
3448 | if (frame_relative_level (this_frame) == 0) | |
3449 | warning (_("ARM M in lockup state, stack unwinding terminated.")); | |
3450 | ||
3451 | /* Terminate any further stack unwinding. */ | |
3452 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
3453 | return cache; | |
3454 | } | |
3455 | ||
df4860da | 3456 | CORE_ADDR lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); |
ef273377 | 3457 | |
148ca9dd YR |
3458 | /* ARMv7-M Architecture Reference "A2.3.1 Arm core registers" |
3459 | states that LR is set to 0xffffffff on reset. ARMv8-M Architecture | |
3460 | Reference "B3.3 Registers" states that LR is set to 0xffffffff on warm | |
3461 | reset if Main Extension is implemented, otherwise the value is unknown. */ | |
3462 | if (lr == 0xffffffff) | |
3463 | { | |
619cce4c TS |
3464 | /* Terminate any further stack unwinding. */ |
3465 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
148ca9dd YR |
3466 | return cache; |
3467 | } | |
3468 | ||
df4860da TS |
3469 | /* Check FNC_RETURN indicator bits (24-31). */ |
3470 | bool fnc_return = (((lr >> 24) & 0xff) == 0xfe); | |
3471 | if (fnc_return) | |
ef273377 | 3472 | { |
df4860da TS |
3473 | /* FNC_RETURN is only valid for targets with Security Extension. */ |
3474 | if (!tdep->have_sec_ext) | |
3475 | { | |
3476 | error (_("While unwinding an exception frame, found unexpected Link " | |
3477 | "Register value %s that requires the security extension, " | |
3478 | "but the extension was not found or is disabled. This " | |
3479 | "should not happen and may be caused by corrupt data or a " | |
3480 | "bug in GDB."), phex (lr, ARM_INT_REGISTER_SIZE)); | |
3481 | } | |
3482 | ||
8c9ae6df YR |
3483 | if (!arm_unwind_secure_frames) |
3484 | { | |
3485 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
ef273377 | 3486 | |
619cce4c TS |
3487 | /* Terminate any further stack unwinding. */ |
3488 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
8c9ae6df YR |
3489 | return cache; |
3490 | } | |
3491 | ||
df4860da | 3492 | ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); |
b2e9e754 | 3493 | if ((xpsr & 0x1ff) != 0) |
8c9ae6df YR |
3494 | /* Handler mode: This is the mode that exceptions are handled in. */ |
3495 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); | |
ef273377 | 3496 | else |
8c9ae6df YR |
3497 | /* Thread mode: This is the normal mode that programs run in. */ |
3498 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); | |
ef273377 | 3499 | |
df4860da | 3500 | CORE_ADDR unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); |
55ea94da | 3501 | |
8c9ae6df YR |
3502 | /* Stack layout for a function call from Secure to Non-Secure state |
3503 | (ARMv8-M section B3.16): | |
55ea94da | 3504 | |
8c9ae6df YR |
3505 | SP Offset |
3506 | ||
3507 | +-------------------+ | |
3508 | 0x08 | | | |
3509 | +-------------------+ <-- Original SP | |
3510 | 0x04 | Partial xPSR | | |
3511 | +-------------------+ | |
3512 | 0x00 | Return Address | | |
3513 | +===================+ <-- New SP */ | |
3514 | ||
3515 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 0x00); | |
3516 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 0x00); | |
3517 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 0x04); | |
3518 | ||
3519 | arm_cache_set_active_sp_value (cache, tdep, unwound_sp + 0x08); | |
ef273377 CL |
3520 | |
3521 | return cache; | |
3522 | } | |
3523 | ||
3524 | /* Check EXC_RETURN indicator bits (24-31). */ | |
df4860da | 3525 | bool exc_return = (((lr >> 24) & 0xff) == 0xff); |
ef273377 | 3526 | if (exc_return) |
55ea94da | 3527 | { |
df4860da TS |
3528 | int sp_regnum; |
3529 | bool secure_stack_used = false; | |
3530 | bool default_callee_register_stacking = false; | |
3531 | bool exception_domain_is_secure = false; | |
3532 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3533 | ||
ef273377 | 3534 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ |
df4860da | 3535 | bool process_stack_used = (bit (lr, 2) != 0); |
ef273377 CL |
3536 | |
3537 | if (tdep->have_sec_ext) | |
3538 | { | |
df4860da TS |
3539 | secure_stack_used = (bit (lr, 6) != 0); |
3540 | default_callee_register_stacking = (bit (lr, 5) != 0); | |
23295de1 | 3541 | exception_domain_is_secure = (bit (lr, 0) != 0); |
ef273377 CL |
3542 | |
3543 | /* Unwinding from non-secure to secure can trip security | |
3544 | measures. In order to avoid the debugger being | |
3545 | intrusive, rely on the user to configure the requested | |
3546 | mode. */ | |
3547 | if (secure_stack_used && !exception_domain_is_secure | |
3548 | && !arm_unwind_secure_frames) | |
3549 | { | |
3550 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
3551 | ||
619cce4c TS |
3552 | /* Terminate any further stack unwinding. */ |
3553 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
ef273377 CL |
3554 | return cache; |
3555 | } | |
3556 | ||
3557 | if (process_stack_used) | |
3558 | { | |
3559 | if (secure_stack_used) | |
3560 | /* Secure thread (process) stack used, use PSP_S as SP. */ | |
df4860da | 3561 | sp_regnum = tdep->m_profile_psp_s_regnum; |
ef273377 CL |
3562 | else |
3563 | /* Non-secure thread (process) stack used, use PSP_NS as SP. */ | |
df4860da | 3564 | sp_regnum = tdep->m_profile_psp_ns_regnum; |
ef273377 CL |
3565 | } |
3566 | else | |
3567 | { | |
3568 | if (secure_stack_used) | |
3569 | /* Secure main stack used, use MSP_S as SP. */ | |
df4860da | 3570 | sp_regnum = tdep->m_profile_msp_s_regnum; |
ef273377 CL |
3571 | else |
3572 | /* Non-secure main stack used, use MSP_NS as SP. */ | |
df4860da | 3573 | sp_regnum = tdep->m_profile_msp_ns_regnum; |
ef273377 CL |
3574 | } |
3575 | } | |
3576 | else | |
3577 | { | |
3578 | if (process_stack_used) | |
3579 | /* Thread (process) stack used, use PSP as SP. */ | |
df4860da | 3580 | sp_regnum = tdep->m_profile_psp_regnum; |
ef273377 CL |
3581 | else |
3582 | /* Main stack used, use MSP as SP. */ | |
df4860da TS |
3583 | sp_regnum = tdep->m_profile_msp_regnum; |
3584 | } | |
3585 | ||
3586 | /* Set the active SP regnum. */ | |
3587 | arm_cache_switch_prev_sp (cache, tdep, sp_regnum); | |
3588 | ||
3589 | /* Fetch the SP to use for this frame. */ | |
3590 | CORE_ADDR unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); | |
3591 | ||
3592 | /* Exception entry context stacking are described in ARMv8-M (section | |
3593 | B3.19) and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference | |
3594 | Manuals. | |
3595 | ||
3596 | The following figure shows the structure of the stack frame when | |
3597 | Security and Floating-point extensions are present. | |
3598 | ||
3599 | SP Offsets | |
3600 | Without With | |
3601 | Callee Regs Callee Regs | |
3602 | (Secure -> Non-Secure) | |
3603 | +-------------------+ | |
3604 | 0xA8 | | 0xD0 | |
3605 | +===================+ --+ <-- Original SP | |
3606 | 0xA4 | S31 | 0xCC | | |
3607 | +-------------------+ | | |
3608 | ... | Additional FP context | |
3609 | +-------------------+ | | |
3610 | 0x68 | S16 | 0x90 | | |
3611 | +===================+ --+ | |
3612 | 0x64 | Reserved | 0x8C | | |
3613 | +-------------------+ | | |
3614 | 0x60 | FPSCR | 0x88 | | |
3615 | +-------------------+ | | |
3616 | 0x5C | S15 | 0x84 | FP context | |
3617 | +-------------------+ | | |
3618 | ... | | |
3619 | +-------------------+ | | |
3620 | 0x20 | S0 | 0x48 | | |
3621 | +===================+ --+ | |
3622 | 0x1C | xPSR | 0x44 | | |
3623 | +-------------------+ | | |
3624 | 0x18 | Return address | 0x40 | | |
3625 | +-------------------+ | | |
3626 | 0x14 | LR(R14) | 0x3C | | |
3627 | +-------------------+ | | |
3628 | 0x10 | R12 | 0x38 | State context | |
3629 | +-------------------+ | | |
3630 | 0x0C | R3 | 0x34 | | |
3631 | +-------------------+ | | |
3632 | ... | | |
3633 | +-------------------+ | | |
3634 | 0x00 | R0 | 0x28 | | |
3635 | +===================+ --+ | |
3636 | | R11 | 0x24 | | |
3637 | +-------------------+ | | |
3638 | ... | | |
3639 | +-------------------+ | Additional state | |
3640 | | R4 | 0x08 | context when | |
3641 | +-------------------+ | transitioning from | |
3642 | | Reserved | 0x04 | Secure to Non-Secure | |
3643 | +-------------------+ | | |
3644 | | Magic signature | 0x00 | | |
3645 | +===================+ --+ <-- New SP */ | |
3646 | ||
3647 | uint32_t sp_r0_offset = 0; | |
3648 | ||
3649 | /* With the Security extension, the hardware saves R4..R11 too. */ | |
3650 | if (tdep->have_sec_ext && secure_stack_used | |
23295de1 | 3651 | && (!default_callee_register_stacking || !exception_domain_is_secure)) |
df4860da TS |
3652 | { |
3653 | /* Read R4..R11 from the integer callee registers. */ | |
3654 | cache->saved_regs[4].set_addr (unwound_sp + 0x08); | |
3655 | cache->saved_regs[5].set_addr (unwound_sp + 0x0C); | |
3656 | cache->saved_regs[6].set_addr (unwound_sp + 0x10); | |
3657 | cache->saved_regs[7].set_addr (unwound_sp + 0x14); | |
3658 | cache->saved_regs[8].set_addr (unwound_sp + 0x18); | |
3659 | cache->saved_regs[9].set_addr (unwound_sp + 0x1C); | |
3660 | cache->saved_regs[10].set_addr (unwound_sp + 0x20); | |
3661 | cache->saved_regs[11].set_addr (unwound_sp + 0x24); | |
3662 | sp_r0_offset = 0x28; | |
3663 | } | |
3664 | ||
3665 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3666 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3667 | "B1.5.6 Exception entry behavior" in | |
3668 | "ARMv7-M Architecture Reference Manual". */ | |
3669 | cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); | |
3670 | cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); | |
3671 | cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); | |
3672 | cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); | |
3673 | cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3674 | + 0x10); | |
3675 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3676 | + 0x14); | |
3677 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3678 | + 0x18); | |
3679 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset | |
3680 | + 0x1C); | |
3681 | ||
3682 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) | |
3683 | type used. */ | |
3684 | bool extended_frame_used = (bit (lr, 4) == 0); | |
3685 | if (extended_frame_used) | |
3686 | { | |
3687 | ULONGEST fpccr; | |
60c90d8c | 3688 | ULONGEST fpcar; |
df4860da TS |
3689 | |
3690 | /* Read FPCCR register. */ | |
ce6c3d25 TS |
3691 | if (!safe_read_memory_unsigned_integer (FPCCR, ARM_INT_REGISTER_SIZE, |
3692 | byte_order, &fpccr)) | |
3693 | { | |
3694 | warning (_("Could not fetch required FPCCR content. Further " | |
3695 | "unwinding is impossible.")); | |
3696 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
3697 | return cache; | |
3698 | } | |
df4860da | 3699 | |
60c90d8c TS |
3700 | /* Read FPCAR register. */ |
3701 | if (!safe_read_memory_unsigned_integer (FPCAR, ARM_INT_REGISTER_SIZE, | |
3702 | byte_order, &fpcar)) | |
3703 | { | |
3704 | warning (_("Could not fetch FPCAR content. Further unwinding of " | |
3705 | "FP register values will be unreliable.")); | |
3706 | fpcar = 0; | |
3707 | } | |
3708 | ||
3709 | bool fpccr_aspen = bit (fpccr, 31); | |
3710 | bool fpccr_lspen = bit (fpccr, 30); | |
3711 | bool fpccr_ts = bit (fpccr, 26); | |
3712 | bool fpccr_lspact = bit (fpccr, 0); | |
3713 | ||
3714 | /* The LSPEN and ASPEN bits indicate if the lazy state preservation | |
3715 | for FP registers is enabled or disabled. The LSPACT bit indicate, | |
3716 | together with FPCAR, if the lazy state preservation feature is | |
3717 | active for the current frame or for another frame. | |
3718 | See "Lazy context save of FP state", in B1.5.7, also ARM AN298, | |
3719 | supported by Cortex-M4F architecture for details. */ | |
3720 | bool fpcar_points_to_this_frame = ((unwound_sp + sp_r0_offset + 0x20) | |
3721 | == (fpcar & ~0x7)); | |
3722 | bool read_fp_regs_from_stack = (!(fpccr_aspen && fpccr_lspen | |
3723 | && fpccr_lspact | |
3724 | && fpcar_points_to_this_frame)); | |
df4860da TS |
3725 | |
3726 | /* Extended stack frame type used. */ | |
60c90d8c | 3727 | if (read_fp_regs_from_stack) |
df4860da | 3728 | { |
60c90d8c TS |
3729 | CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20; |
3730 | for (int i = 0; i < 8; i++) | |
3731 | { | |
3732 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); | |
3733 | addr += 8; | |
3734 | } | |
df4860da TS |
3735 | } |
3736 | cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp | |
3737 | + sp_r0_offset + 0x60); | |
ef273377 | 3738 | |
df4860da TS |
3739 | if (tdep->have_sec_ext && !default_callee_register_stacking |
3740 | && fpccr_ts) | |
3741 | { | |
3742 | /* Handle floating-point callee saved registers. */ | |
60c90d8c | 3743 | if (read_fp_regs_from_stack) |
df4860da | 3744 | { |
60c90d8c TS |
3745 | CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x68; |
3746 | for (int i = 8; i < 16; i++) | |
3747 | { | |
3748 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); | |
3749 | addr += 8; | |
3750 | } | |
df4860da | 3751 | } |
2ae28aa9 | 3752 | |
df4860da TS |
3753 | arm_cache_set_active_sp_value (cache, tdep, |
3754 | unwound_sp + sp_r0_offset + 0xA8); | |
3755 | } | |
3756 | else | |
ef273377 | 3757 | { |
df4860da TS |
3758 | /* Offset 0x64 is reserved. */ |
3759 | arm_cache_set_active_sp_value (cache, tdep, | |
3760 | unwound_sp + sp_r0_offset + 0x68); | |
ef273377 | 3761 | } |
ef273377 CL |
3762 | } |
3763 | else | |
3764 | { | |
df4860da | 3765 | /* Standard stack frame type used. */ |
2d9cf99d | 3766 | arm_cache_set_active_sp_value (cache, tdep, |
df4860da | 3767 | unwound_sp + sp_r0_offset + 0x20); |
ef273377 | 3768 | } |
55ea94da | 3769 | |
df4860da TS |
3770 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3771 | aligner between the top of the 32-byte stack frame and the | |
3772 | previous context's stack pointer. */ | |
3773 | ULONGEST xpsr; | |
ce6c3d25 TS |
3774 | if (!safe_read_memory_unsigned_integer (cache->saved_regs[ARM_PS_REGNUM] |
3775 | .addr (), ARM_INT_REGISTER_SIZE, | |
3776 | byte_order, &xpsr)) | |
3777 | { | |
3778 | warning (_("Could not fetch required XPSR content. Further " | |
3779 | "unwinding is impossible.")); | |
3780 | arm_cache_set_active_sp_value (cache, tdep, 0); | |
3781 | return cache; | |
3782 | } | |
3783 | ||
df4860da TS |
3784 | if (bit (xpsr, 9) != 0) |
3785 | { | |
3786 | CORE_ADDR new_sp = arm_cache_get_prev_sp_value (cache, tdep) + 4; | |
3787 | arm_cache_set_active_sp_value (cache, tdep, new_sp); | |
3788 | } | |
2ae28aa9 | 3789 | |
df4860da TS |
3790 | return cache; |
3791 | } | |
3792 | ||
f34652de PA |
3793 | internal_error (_("While unwinding an exception frame, " |
3794 | "found unexpected Link Register value " | |
3795 | "%s. This should not happen and may " | |
3796 | "be caused by corrupt data or a bug in" | |
3797 | " GDB."), | |
df4860da | 3798 | phex (lr, ARM_INT_REGISTER_SIZE)); |
2ae28aa9 YQ |
3799 | } |
3800 | ||
ce6c3d25 TS |
3801 | /* Implementation of the stop_reason hook for arm_m_exception frames. */ |
3802 | ||
3803 | static enum unwind_stop_reason | |
3804 | arm_m_exception_frame_unwind_stop_reason (frame_info_ptr this_frame, | |
3805 | void **this_cache) | |
3806 | { | |
3807 | struct arm_prologue_cache *cache; | |
3808 | arm_gdbarch_tdep *tdep | |
3809 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); | |
3810 | ||
3811 | if (*this_cache == NULL) | |
3812 | *this_cache = arm_m_exception_cache (this_frame); | |
3813 | cache = (struct arm_prologue_cache *) *this_cache; | |
3814 | ||
3815 | /* If we've hit a wall, stop. */ | |
3816 | if (arm_cache_get_prev_sp_value (cache, tdep) == 0) | |
3817 | return UNWIND_OUTERMOST; | |
3818 | ||
3819 | return UNWIND_NO_REASON; | |
3820 | } | |
3821 | ||
2ae28aa9 YQ |
3822 | /* Implementation of function hook 'this_id' in |
3823 | 'struct frame_uwnind'. */ | |
3824 | ||
3825 | static void | |
bd2b40ac | 3826 | arm_m_exception_this_id (frame_info_ptr this_frame, |
2ae28aa9 YQ |
3827 | void **this_cache, |
3828 | struct frame_id *this_id) | |
3829 | { | |
3830 | struct arm_prologue_cache *cache; | |
3831 | ||
3832 | if (*this_cache == NULL) | |
3833 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3834 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3835 | |
3836 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
ae7e2f45 | 3837 | arm_gdbarch_tdep *tdep |
08106042 | 3838 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3839 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
2ae28aa9 YQ |
3840 | get_frame_pc (this_frame)); |
3841 | } | |
3842 | ||
3843 | /* Implementation of function hook 'prev_register' in | |
3844 | 'struct frame_uwnind'. */ | |
3845 | ||
3846 | static struct value * | |
bd2b40ac | 3847 | arm_m_exception_prev_register (frame_info_ptr this_frame, |
2ae28aa9 YQ |
3848 | void **this_cache, |
3849 | int prev_regnum) | |
3850 | { | |
2ae28aa9 | 3851 | struct arm_prologue_cache *cache; |
ef273377 | 3852 | CORE_ADDR sp_value; |
2ae28aa9 YQ |
3853 | |
3854 | if (*this_cache == NULL) | |
3855 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3856 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3857 | |
3858 | /* The value was already reconstructed into PREV_SP. */ | |
ae7e2f45 | 3859 | arm_gdbarch_tdep *tdep |
08106042 | 3860 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
2ae28aa9 YQ |
3861 | if (prev_regnum == ARM_SP_REGNUM) |
3862 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
ae7e2f45 | 3863 | arm_cache_get_prev_sp_value (cache, tdep)); |
2ae28aa9 | 3864 | |
8c9ae6df YR |
3865 | /* If we are asked to unwind the PC, strip the saved T bit. */ |
3866 | if (prev_regnum == ARM_PC_REGNUM) | |
3867 | { | |
3868 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3869 | cache->saved_regs, | |
3870 | prev_regnum); | |
3871 | CORE_ADDR pc = value_as_address (value); | |
3872 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3873 | UNMAKE_THUMB_ADDR (pc)); | |
3874 | } | |
3875 | ||
ef273377 CL |
3876 | /* The value might be one of the alternative SP, if so, use the |
3877 | value already constructed. */ | |
d65edaa0 | 3878 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
3879 | { |
3880 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
3881 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
3882 | } | |
3883 | ||
8c9ae6df YR |
3884 | /* If we are asked to unwind the xPSR, set T bit if PC is in thumb mode. |
3885 | LR register is unreliable as it contains FNC_RETURN or EXC_RETURN | |
3886 | pattern. */ | |
3887 | if (prev_regnum == ARM_PS_REGNUM) | |
3888 | { | |
3889 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3890 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3891 | cache->saved_regs, | |
3892 | ARM_PC_REGNUM); | |
3893 | CORE_ADDR pc = value_as_address (value); | |
3894 | value = trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3895 | ARM_PS_REGNUM); | |
3896 | ULONGEST xpsr = value_as_long (value); | |
3897 | ||
3898 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
3899 | xpsr = reconstruct_t_bit (gdbarch, pc, xpsr); | |
3900 | return frame_unwind_got_constant (this_frame, ARM_PS_REGNUM, xpsr); | |
3901 | } | |
3902 | ||
2ae28aa9 YQ |
3903 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
3904 | prev_regnum); | |
3905 | } | |
3906 | ||
3907 | /* Implementation of function hook 'sniffer' in | |
3908 | 'struct frame_uwnind'. */ | |
3909 | ||
3910 | static int | |
3911 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3912 | frame_info_ptr this_frame, |
2ae28aa9 YQ |
3913 | void **this_prologue_cache) |
3914 | { | |
ef273377 | 3915 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2ae28aa9 YQ |
3916 | CORE_ADDR this_pc = get_frame_pc (this_frame); |
3917 | ||
3918 | /* No need to check is_m; this sniffer is only registered for | |
3919 | M-profile architectures. */ | |
3920 | ||
ca90e760 | 3921 | /* Check if exception frame returns to a magic PC value. */ |
ef273377 | 3922 | return arm_m_addr_is_magic (gdbarch, this_pc); |
2ae28aa9 YQ |
3923 | } |
3924 | ||
8b73ee20 LM |
3925 | /* Frame unwinder for M-profile exceptions (EXC_RETURN on stack), |
3926 | lockup and secure/nonsecure interstate function calls (FNC_RETURN). */ | |
2ae28aa9 YQ |
3927 | |
3928 | struct frame_unwind arm_m_exception_unwind = | |
3929 | { | |
8b73ee20 | 3930 | "arm m exception lockup sec_fnc", |
2ae28aa9 | 3931 | SIGTRAMP_FRAME, |
ce6c3d25 | 3932 | arm_m_exception_frame_unwind_stop_reason, |
2ae28aa9 YQ |
3933 | arm_m_exception_this_id, |
3934 | arm_m_exception_prev_register, | |
3935 | NULL, | |
3936 | arm_m_exception_unwind_sniffer | |
3937 | }; | |
3938 | ||
24de872b | 3939 | static CORE_ADDR |
bd2b40ac | 3940 | arm_normal_frame_base (frame_info_ptr this_frame, void **this_cache) |
24de872b DJ |
3941 | { |
3942 | struct arm_prologue_cache *cache; | |
3943 | ||
eb5492fa | 3944 | if (*this_cache == NULL) |
a262aec2 | 3945 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3946 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3947 | |
ae7e2f45 | 3948 | arm_gdbarch_tdep *tdep |
08106042 | 3949 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3950 | return arm_cache_get_prev_sp_value (cache, tdep) - cache->framesize; |
24de872b DJ |
3951 | } |
3952 | ||
eb5492fa DJ |
3953 | struct frame_base arm_normal_base = { |
3954 | &arm_prologue_unwind, | |
3955 | arm_normal_frame_base, | |
3956 | arm_normal_frame_base, | |
3957 | arm_normal_frame_base | |
3958 | }; | |
3959 | ||
b39cc962 | 3960 | static struct value * |
bd2b40ac | 3961 | arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, |
b39cc962 DJ |
3962 | int regnum) |
3963 | { | |
24568a2c | 3964 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
08106042 | 3965 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
8c9ae6df YR |
3966 | CORE_ADDR lr; |
3967 | ULONGEST cpsr; | |
b39cc962 | 3968 | |
42e11f36 | 3969 | if (regnum == ARM_PC_REGNUM) |
b39cc962 | 3970 | { |
b39cc962 DJ |
3971 | /* The PC is normally copied from the return column, which |
3972 | describes saves of LR. However, that version may have an | |
3973 | extra bit set to indicate Thumb state. The bit is not | |
3974 | part of the PC. */ | |
a01567f4 LM |
3975 | |
3976 | /* Record in the frame whether the return address was signed. */ | |
3977 | if (tdep->have_pacbti) | |
3978 | { | |
3979 | CORE_ADDR ra_auth_code | |
3980 | = frame_unwind_register_unsigned (this_frame, | |
3981 | tdep->pacbti_pseudo_base); | |
3982 | ||
3983 | if (ra_auth_code != 0) | |
3984 | set_frame_previous_pc_masked (this_frame); | |
3985 | } | |
3986 | ||
b39cc962 DJ |
3987 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3988 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3989 | arm_addr_bits_remove (gdbarch, lr)); |
42e11f36 TS |
3990 | } |
3991 | else if (regnum == ARM_PS_REGNUM) | |
3992 | { | |
b39cc962 | 3993 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ |
ca38c58e | 3994 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 | 3995 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
8c9ae6df | 3996 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
ca38c58e | 3997 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 | 3998 | } |
a6e4a48c YR |
3999 | else if (arm_is_alternative_sp_register (tdep, regnum)) |
4000 | { | |
4001 | /* Handle the alternative SP registers on Cortex-M. */ | |
4002 | bool override_with_sp_value = false; | |
4003 | CORE_ADDR val; | |
4004 | ||
4005 | if (tdep->have_sec_ext) | |
4006 | { | |
4007 | CORE_ADDR sp | |
4008 | = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
4009 | CORE_ADDR msp_s | |
4010 | = get_frame_register_unsigned (this_frame, | |
4011 | tdep->m_profile_msp_s_regnum); | |
4012 | CORE_ADDR msp_ns | |
4013 | = get_frame_register_unsigned (this_frame, | |
4014 | tdep->m_profile_msp_ns_regnum); | |
4015 | CORE_ADDR psp_s | |
4016 | = get_frame_register_unsigned (this_frame, | |
4017 | tdep->m_profile_psp_s_regnum); | |
4018 | CORE_ADDR psp_ns | |
4019 | = get_frame_register_unsigned (this_frame, | |
4020 | tdep->m_profile_psp_ns_regnum); | |
4021 | ||
4022 | bool is_msp = (regnum == tdep->m_profile_msp_regnum) | |
4023 | && (msp_s == sp || msp_ns == sp); | |
4024 | bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) | |
4025 | && (msp_s == sp); | |
4026 | bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) | |
4027 | && (msp_ns == sp); | |
4028 | bool is_psp = (regnum == tdep->m_profile_psp_regnum) | |
4029 | && (psp_s == sp || psp_ns == sp); | |
4030 | bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) | |
4031 | && (psp_s == sp); | |
4032 | bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) | |
4033 | && (psp_ns == sp); | |
4034 | ||
4035 | override_with_sp_value = is_msp || is_msp_s || is_msp_ns | |
4036 | || is_psp || is_psp_s || is_psp_ns; | |
4037 | ||
4038 | } | |
4039 | else if (tdep->is_m) | |
4040 | { | |
4041 | CORE_ADDR sp | |
4042 | = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
4043 | CORE_ADDR msp | |
4044 | = get_frame_register_unsigned (this_frame, | |
4045 | tdep->m_profile_msp_regnum); | |
4046 | CORE_ADDR psp | |
4047 | = get_frame_register_unsigned (this_frame, | |
4048 | tdep->m_profile_psp_regnum); | |
4049 | ||
4050 | bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); | |
4051 | bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); | |
4052 | ||
4053 | override_with_sp_value = is_msp || is_psp; | |
4054 | } | |
4055 | ||
4056 | if (override_with_sp_value) | |
4057 | { | |
4058 | /* Use value of SP from previous frame. */ | |
bd2b40ac | 4059 | frame_info_ptr prev_frame = get_prev_frame (this_frame); |
a6e4a48c YR |
4060 | if (prev_frame) |
4061 | val = get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); | |
4062 | else | |
4063 | val = get_frame_base (this_frame); | |
4064 | } | |
4065 | else | |
4066 | /* Use value for the register from previous frame. */ | |
4067 | val = get_frame_register_unsigned (this_frame, regnum); | |
4068 | ||
4069 | return frame_unwind_got_constant (this_frame, regnum, val); | |
4070 | } | |
42e11f36 | 4071 | |
f34652de | 4072 | internal_error (_("Unexpected register %d"), regnum); |
b39cc962 DJ |
4073 | } |
4074 | ||
c9cf6e20 | 4075 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
4076 | |
4077 | static int | |
c9cf6e20 | 4078 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
4079 | { |
4080 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4081 | unsigned int insn, insn2; | |
4082 | int found_return = 0, found_stack_adjust = 0; | |
4083 | CORE_ADDR func_start, func_end; | |
4084 | CORE_ADDR scan_pc; | |
4085 | gdb_byte buf[4]; | |
4086 | ||
4087 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
4088 | return 0; | |
4089 | ||
4090 | /* The epilogue is a sequence of instructions along the following lines: | |
4091 | ||
4092 | - add stack frame size to SP or FP | |
4093 | - [if frame pointer used] restore SP from FP | |
4094 | - restore registers from SP [may include PC] | |
4095 | - a return-type instruction [if PC wasn't already restored] | |
4096 | ||
4097 | In a first pass, we scan forward from the current PC and verify the | |
4098 | instructions we find as compatible with this sequence, ending in a | |
4099 | return instruction. | |
4100 | ||
4101 | However, this is not sufficient to distinguish indirect function calls | |
4102 | within a function from indirect tail calls in the epilogue in some cases. | |
4103 | Therefore, if we didn't already find any SP-changing instruction during | |
4104 | forward scan, we add a backward scanning heuristic to ensure we actually | |
4105 | are in the epilogue. */ | |
4106 | ||
4107 | scan_pc = pc; | |
4108 | while (scan_pc < func_end && !found_return) | |
4109 | { | |
4110 | if (target_read_memory (scan_pc, buf, 2)) | |
4111 | break; | |
4112 | ||
4113 | scan_pc += 2; | |
4114 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
4115 | ||
4116 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
4117 | found_return = 1; | |
4118 | else if (insn == 0x46f7) /* mov pc, lr */ | |
4119 | found_return = 1; | |
540314bd | 4120 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 4121 | { |
b7576e5c | 4122 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
4123 | found_return = 1; |
4124 | } | |
db24da6d | 4125 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
4126 | { |
4127 | if (target_read_memory (scan_pc, buf, 2)) | |
4128 | break; | |
4129 | ||
4130 | scan_pc += 2; | |
4131 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
4132 | ||
4133 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
4134 | { | |
4024ca99 UW |
4135 | if (insn2 & 0x8000) /* <registers> include PC. */ |
4136 | found_return = 1; | |
4137 | } | |
4138 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
4139 | && (insn2 & 0x0fff) == 0x0b04) | |
4140 | { | |
4024ca99 UW |
4141 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
4142 | found_return = 1; | |
4143 | } | |
4144 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
4145 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 4146 | ; |
4024ca99 UW |
4147 | else |
4148 | break; | |
4149 | } | |
4150 | else | |
4151 | break; | |
4152 | } | |
4153 | ||
4154 | if (!found_return) | |
4155 | return 0; | |
4156 | ||
4157 | /* Since any instruction in the epilogue sequence, with the possible | |
4158 | exception of return itself, updates the stack pointer, we need to | |
4159 | scan backwards for at most one instruction. Try either a 16-bit or | |
4160 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 4161 | too much about false positives. */ |
4024ca99 | 4162 | |
6b65d1b6 YQ |
4163 | if (pc - 4 < func_start) |
4164 | return 0; | |
4165 | if (target_read_memory (pc - 4, buf, 4)) | |
4166 | return 0; | |
4024ca99 | 4167 | |
6b65d1b6 YQ |
4168 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
4169 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
4170 | ||
4171 | if (thumb_instruction_restores_sp (insn2)) | |
4172 | found_stack_adjust = 1; | |
4173 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
4174 | found_stack_adjust = 1; | |
4175 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
4176 | && (insn2 & 0x0fff) == 0x0b04) | |
4177 | found_stack_adjust = 1; | |
4178 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
4179 | && (insn2 & 0x0e00) == 0x0a00) | |
4180 | found_stack_adjust = 1; | |
4024ca99 UW |
4181 | |
4182 | return found_stack_adjust; | |
4183 | } | |
4184 | ||
4024ca99 | 4185 | static int |
c58b006a | 4186 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
4187 | { |
4188 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
4189 | unsigned int insn; | |
f303bc3e | 4190 | int found_return; |
4024ca99 UW |
4191 | CORE_ADDR func_start, func_end; |
4192 | ||
4024ca99 UW |
4193 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
4194 | return 0; | |
4195 | ||
4196 | /* We are in the epilogue if the previous instruction was a stack | |
4197 | adjustment and the next instruction is a possible return (bx, mov | |
4198 | pc, or pop). We could have to scan backwards to find the stack | |
4199 | adjustment, or forwards to find the return, but this is a decent | |
4200 | approximation. First scan forwards. */ | |
4201 | ||
4202 | found_return = 0; | |
4203 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
4204 | if (bits (insn, 28, 31) != INST_NV) | |
4205 | { | |
4206 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
4207 | /* BX. */ | |
4208 | found_return = 1; | |
4209 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
4210 | /* MOV PC. */ | |
4211 | found_return = 1; | |
4212 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
4213 | && (insn & 0x0000c000) != 0) | |
4214 | /* POP (LDMIA), including PC or LR. */ | |
4215 | found_return = 1; | |
4216 | } | |
4217 | ||
4218 | if (!found_return) | |
4219 | return 0; | |
4220 | ||
4221 | /* Scan backwards. This is just a heuristic, so do not worry about | |
4222 | false positives from mode changes. */ | |
4223 | ||
4224 | if (pc < func_start + 4) | |
4225 | return 0; | |
4226 | ||
4227 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 4228 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
4229 | return 1; |
4230 | ||
4231 | return 0; | |
4232 | } | |
4233 | ||
c58b006a YQ |
4234 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4235 | ||
4236 | static int | |
4237 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4238 | { | |
4239 | if (arm_pc_is_thumb (gdbarch, pc)) | |
4240 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
4241 | else | |
4242 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
4243 | } | |
4024ca99 | 4244 | |
2dd604e7 RE |
4245 | /* When arguments must be pushed onto the stack, they go on in reverse |
4246 | order. The code below implements a FILO (stack) to do this. */ | |
4247 | ||
0fecb1a7 | 4248 | struct arm_stack_item |
2dd604e7 RE |
4249 | { |
4250 | int len; | |
0fecb1a7 | 4251 | struct arm_stack_item *prev; |
7c543f7b | 4252 | gdb_byte *data; |
2dd604e7 RE |
4253 | }; |
4254 | ||
0fecb1a7 TT |
4255 | static struct arm_stack_item * |
4256 | push_stack_item (struct arm_stack_item *prev, const gdb_byte *contents, | |
4257 | int len) | |
2dd604e7 | 4258 | { |
0fecb1a7 TT |
4259 | struct arm_stack_item *si; |
4260 | si = XNEW (struct arm_stack_item); | |
7c543f7b | 4261 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
4262 | si->len = len; |
4263 | si->prev = prev; | |
4264 | memcpy (si->data, contents, len); | |
4265 | return si; | |
4266 | } | |
4267 | ||
0fecb1a7 TT |
4268 | static struct arm_stack_item * |
4269 | pop_stack_item (struct arm_stack_item *si) | |
2dd604e7 | 4270 | { |
0fecb1a7 | 4271 | struct arm_stack_item *dead = si; |
2dd604e7 RE |
4272 | si = si->prev; |
4273 | xfree (dead->data); | |
4274 | xfree (dead); | |
4275 | return si; | |
4276 | } | |
4277 | ||
030197b4 AB |
4278 | /* Implement the gdbarch type alignment method, overrides the generic |
4279 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 4280 | |
030197b4 AB |
4281 | static ULONGEST |
4282 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 4283 | { |
2af48f68 | 4284 | t = check_typedef (t); |
bd63c870 | 4285 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 4286 | { |
030197b4 AB |
4287 | /* Use the natural alignment for vector types (the same for |
4288 | scalar type), but the maximum alignment is 64-bit. */ | |
df86565b | 4289 | if (t->length () > 8) |
030197b4 | 4290 | return 8; |
c4312b19 | 4291 | else |
df86565b | 4292 | return t->length (); |
2af48f68 | 4293 | } |
030197b4 AB |
4294 | |
4295 | /* Allow the common code to calculate the alignment. */ | |
4296 | return 0; | |
2af48f68 PB |
4297 | } |
4298 | ||
90445bd3 DJ |
4299 | /* Possible base types for a candidate for passing and returning in |
4300 | VFP registers. */ | |
4301 | ||
4302 | enum arm_vfp_cprc_base_type | |
4303 | { | |
4304 | VFP_CPRC_UNKNOWN, | |
4305 | VFP_CPRC_SINGLE, | |
4306 | VFP_CPRC_DOUBLE, | |
4307 | VFP_CPRC_VEC64, | |
4308 | VFP_CPRC_VEC128 | |
4309 | }; | |
4310 | ||
4311 | /* The length of one element of base type B. */ | |
4312 | ||
4313 | static unsigned | |
4314 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
4315 | { | |
4316 | switch (b) | |
4317 | { | |
4318 | case VFP_CPRC_SINGLE: | |
4319 | return 4; | |
4320 | case VFP_CPRC_DOUBLE: | |
4321 | return 8; | |
4322 | case VFP_CPRC_VEC64: | |
4323 | return 8; | |
4324 | case VFP_CPRC_VEC128: | |
4325 | return 16; | |
4326 | default: | |
f34652de | 4327 | internal_error (_("Invalid VFP CPRC type: %d."), |
90445bd3 DJ |
4328 | (int) b); |
4329 | } | |
4330 | } | |
4331 | ||
4332 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
4333 | for passing base type B. */ | |
4334 | ||
4335 | static int | |
4336 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
4337 | { | |
4338 | switch (b) | |
4339 | { | |
4340 | case VFP_CPRC_SINGLE: | |
4341 | return 's'; | |
4342 | case VFP_CPRC_DOUBLE: | |
4343 | return 'd'; | |
4344 | case VFP_CPRC_VEC64: | |
4345 | return 'd'; | |
4346 | case VFP_CPRC_VEC128: | |
4347 | return 'q'; | |
4348 | default: | |
f34652de | 4349 | internal_error (_("Invalid VFP CPRC type: %d."), |
90445bd3 DJ |
4350 | (int) b); |
4351 | } | |
4352 | } | |
4353 | ||
4354 | /* Determine whether T may be part of a candidate for passing and | |
4355 | returning in VFP registers, ignoring the limit on the total number | |
4356 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
4357 | classification of the first valid component found; if it is not | |
4358 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
4359 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
4360 | for passing and returning in VFP registers, a type differently | |
4361 | classified from *BASE_TYPE, or two types differently classified | |
4362 | from each other, return -1, otherwise return the total number of | |
4363 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
4364 | array). Vector types are not currently supported, matching the |
4365 | generic AAPCS support. */ | |
90445bd3 DJ |
4366 | |
4367 | static int | |
4368 | arm_vfp_cprc_sub_candidate (struct type *t, | |
4369 | enum arm_vfp_cprc_base_type *base_type) | |
4370 | { | |
4371 | t = check_typedef (t); | |
78134374 | 4372 | switch (t->code ()) |
90445bd3 DJ |
4373 | { |
4374 | case TYPE_CODE_FLT: | |
df86565b | 4375 | switch (t->length ()) |
90445bd3 DJ |
4376 | { |
4377 | case 4: | |
4378 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4379 | *base_type = VFP_CPRC_SINGLE; | |
4380 | else if (*base_type != VFP_CPRC_SINGLE) | |
4381 | return -1; | |
4382 | return 1; | |
4383 | ||
4384 | case 8: | |
4385 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4386 | *base_type = VFP_CPRC_DOUBLE; | |
4387 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4388 | return -1; | |
4389 | return 1; | |
4390 | ||
4391 | default: | |
4392 | return -1; | |
4393 | } | |
4394 | break; | |
4395 | ||
817e0957 YQ |
4396 | case TYPE_CODE_COMPLEX: |
4397 | /* Arguments of complex T where T is one of the types float or | |
4398 | double get treated as if they are implemented as: | |
4399 | ||
4400 | struct complexT | |
4401 | { | |
4402 | T real; | |
4403 | T imag; | |
5f52445b YQ |
4404 | }; |
4405 | ||
4406 | */ | |
df86565b | 4407 | switch (t->length ()) |
817e0957 YQ |
4408 | { |
4409 | case 8: | |
4410 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4411 | *base_type = VFP_CPRC_SINGLE; | |
4412 | else if (*base_type != VFP_CPRC_SINGLE) | |
4413 | return -1; | |
4414 | return 2; | |
4415 | ||
4416 | case 16: | |
4417 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4418 | *base_type = VFP_CPRC_DOUBLE; | |
4419 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4420 | return -1; | |
4421 | return 2; | |
4422 | ||
4423 | default: | |
4424 | return -1; | |
4425 | } | |
4426 | break; | |
4427 | ||
90445bd3 DJ |
4428 | case TYPE_CODE_ARRAY: |
4429 | { | |
bd63c870 | 4430 | if (t->is_vector ()) |
90445bd3 | 4431 | { |
c4312b19 YQ |
4432 | /* A 64-bit or 128-bit containerized vector type are VFP |
4433 | CPRCs. */ | |
df86565b | 4434 | switch (t->length ()) |
c4312b19 YQ |
4435 | { |
4436 | case 8: | |
4437 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4438 | *base_type = VFP_CPRC_VEC64; | |
4439 | return 1; | |
4440 | case 16: | |
4441 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4442 | *base_type = VFP_CPRC_VEC128; | |
4443 | return 1; | |
4444 | default: | |
4445 | return -1; | |
4446 | } | |
4447 | } | |
4448 | else | |
4449 | { | |
4450 | int count; | |
4451 | unsigned unitlen; | |
4452 | ||
27710edb | 4453 | count = arm_vfp_cprc_sub_candidate (t->target_type (), |
c4312b19 YQ |
4454 | base_type); |
4455 | if (count == -1) | |
4456 | return -1; | |
df86565b | 4457 | if (t->length () == 0) |
c4312b19 YQ |
4458 | { |
4459 | gdb_assert (count == 0); | |
4460 | return 0; | |
4461 | } | |
4462 | else if (count == 0) | |
4463 | return -1; | |
4464 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b SM |
4465 | gdb_assert ((t->length () % unitlen) == 0); |
4466 | return t->length () / unitlen; | |
90445bd3 | 4467 | } |
90445bd3 DJ |
4468 | } |
4469 | break; | |
4470 | ||
4471 | case TYPE_CODE_STRUCT: | |
4472 | { | |
4473 | int count = 0; | |
4474 | unsigned unitlen; | |
4475 | int i; | |
1f704f76 | 4476 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4477 | { |
1040b979 YQ |
4478 | int sub_count = 0; |
4479 | ||
ceacbf6e | 4480 | if (!field_is_static (&t->field (i))) |
940da03e | 4481 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 4482 | base_type); |
90445bd3 DJ |
4483 | if (sub_count == -1) |
4484 | return -1; | |
4485 | count += sub_count; | |
4486 | } | |
df86565b | 4487 | if (t->length () == 0) |
90445bd3 DJ |
4488 | { |
4489 | gdb_assert (count == 0); | |
4490 | return 0; | |
4491 | } | |
4492 | else if (count == 0) | |
4493 | return -1; | |
4494 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b | 4495 | if (t->length () != unitlen * count) |
90445bd3 DJ |
4496 | return -1; |
4497 | return count; | |
4498 | } | |
4499 | ||
4500 | case TYPE_CODE_UNION: | |
4501 | { | |
4502 | int count = 0; | |
4503 | unsigned unitlen; | |
4504 | int i; | |
1f704f76 | 4505 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4506 | { |
940da03e | 4507 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
4508 | base_type); |
4509 | if (sub_count == -1) | |
4510 | return -1; | |
4511 | count = (count > sub_count ? count : sub_count); | |
4512 | } | |
df86565b | 4513 | if (t->length () == 0) |
90445bd3 DJ |
4514 | { |
4515 | gdb_assert (count == 0); | |
4516 | return 0; | |
4517 | } | |
4518 | else if (count == 0) | |
4519 | return -1; | |
4520 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
df86565b | 4521 | if (t->length () != unitlen * count) |
90445bd3 DJ |
4522 | return -1; |
4523 | return count; | |
4524 | } | |
4525 | ||
4526 | default: | |
4527 | break; | |
4528 | } | |
4529 | ||
4530 | return -1; | |
4531 | } | |
4532 | ||
4533 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
4534 | if passed to or returned from a non-variadic function with the VFP | |
4535 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
4536 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
4537 | elements of that base type before returning. */ | |
4538 | ||
4539 | static int | |
4540 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
4541 | int *count) | |
4542 | { | |
4543 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
4544 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
4545 | if (c <= 0 || c > 4) | |
4546 | return 0; | |
4547 | *base_type = b; | |
4548 | *count = c; | |
4549 | return 1; | |
4550 | } | |
4551 | ||
4552 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
4553 | returning values from a function of type FUNC_TYPE, 0 | |
4554 | otherwise. */ | |
4555 | ||
4556 | static int | |
4557 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
4558 | { | |
08106042 | 4559 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 4560 | |
90445bd3 DJ |
4561 | /* Variadic functions always use the base ABI. Assume that functions |
4562 | without debug info are not variadic. */ | |
a409645d | 4563 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 | 4564 | return 0; |
345bd07c | 4565 | |
90445bd3 DJ |
4566 | /* The VFP ABI is only supported as a variant of AAPCS. */ |
4567 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
4568 | return 0; | |
345bd07c SM |
4569 | |
4570 | return tdep->fp_model == ARM_FLOAT_VFP; | |
90445bd3 DJ |
4571 | } |
4572 | ||
4573 | /* We currently only support passing parameters in integer registers, which | |
4574 | conforms with GCC's default model, and VFP argument passing following | |
4575 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
4576 | we should probably support some of them based on the selected ABI. */ |
4577 | ||
4578 | static CORE_ADDR | |
7d9b040b | 4579 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 4580 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
4581 | struct value **args, CORE_ADDR sp, |
4582 | function_call_return_method return_method, | |
6a65450a | 4583 | CORE_ADDR struct_addr) |
2dd604e7 | 4584 | { |
e17a4113 | 4585 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
4586 | int argnum; |
4587 | int argreg; | |
4588 | int nstack; | |
0fecb1a7 | 4589 | struct arm_stack_item *si = NULL; |
90445bd3 DJ |
4590 | int use_vfp_abi; |
4591 | struct type *ftype; | |
4592 | unsigned vfp_regs_free = (1 << 16) - 1; | |
08106042 | 4593 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
90445bd3 DJ |
4594 | |
4595 | /* Determine the type of this function and whether the VFP ABI | |
4596 | applies. */ | |
4597 | ftype = check_typedef (value_type (function)); | |
78134374 | 4598 | if (ftype->code () == TYPE_CODE_PTR) |
27710edb | 4599 | ftype = check_typedef (ftype->target_type ()); |
90445bd3 | 4600 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); |
2dd604e7 | 4601 | |
6a65450a AC |
4602 | /* Set the return address. For the ARM, the return breakpoint is |
4603 | always at BP_ADDR. */ | |
9779414d | 4604 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 4605 | bp_addr |= 1; |
6a65450a | 4606 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
4607 | |
4608 | /* Walk through the list of args and determine how large a temporary | |
4609 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 4610 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
4611 | nstack = 0; |
4612 | ||
4613 | argreg = ARM_A1_REGNUM; | |
4614 | nstack = 0; | |
4615 | ||
2dd604e7 RE |
4616 | /* The struct_return pointer occupies the first parameter |
4617 | passing register. */ | |
cf84fa6b | 4618 | if (return_method == return_method_struct) |
2dd604e7 | 4619 | { |
7cb6d92a SM |
4620 | arm_debug_printf ("struct return in %s = %s", |
4621 | gdbarch_register_name (gdbarch, argreg), | |
4622 | paddress (gdbarch, struct_addr)); | |
4623 | ||
2dd604e7 RE |
4624 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
4625 | argreg++; | |
4626 | } | |
4627 | ||
4628 | for (argnum = 0; argnum < nargs; argnum++) | |
4629 | { | |
4630 | int len; | |
4631 | struct type *arg_type; | |
4632 | struct type *target_type; | |
4633 | enum type_code typecode; | |
8c6363cf | 4634 | const bfd_byte *val; |
2af48f68 | 4635 | int align; |
90445bd3 DJ |
4636 | enum arm_vfp_cprc_base_type vfp_base_type; |
4637 | int vfp_base_count; | |
4638 | int may_use_core_reg = 1; | |
2dd604e7 | 4639 | |
df407dfe | 4640 | arg_type = check_typedef (value_type (args[argnum])); |
df86565b | 4641 | len = arg_type->length (); |
27710edb | 4642 | target_type = arg_type->target_type (); |
78134374 | 4643 | typecode = arg_type->code (); |
50888e42 | 4644 | val = value_contents (args[argnum]).data (); |
2dd604e7 | 4645 | |
030197b4 | 4646 | align = type_align (arg_type); |
2af48f68 | 4647 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
4648 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
4649 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 | 4650 | /* Different ABIs have different maximum alignments. */ |
345bd07c | 4651 | if (tdep->arm_abi == ARM_ABI_APCS) |
2af48f68 PB |
4652 | { |
4653 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 4654 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
4655 | } |
4656 | else | |
4657 | { | |
4658 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
4659 | if (align > ARM_INT_REGISTER_SIZE * 2) |
4660 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
4661 | } |
4662 | ||
90445bd3 DJ |
4663 | if (use_vfp_abi |
4664 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
4665 | &vfp_base_count)) | |
4666 | { | |
4667 | int regno; | |
4668 | int unit_length; | |
4669 | int shift; | |
4670 | unsigned mask; | |
4671 | ||
4672 | /* Because this is a CPRC it cannot go in a core register or | |
4673 | cause a core register to be skipped for alignment. | |
4674 | Either it goes in VFP registers and the rest of this loop | |
4675 | iteration is skipped for this argument, or it goes on the | |
4676 | stack (and the stack alignment code is correct for this | |
4677 | case). */ | |
4678 | may_use_core_reg = 0; | |
4679 | ||
4680 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
4681 | shift = unit_length / 4; | |
4682 | mask = (1 << (shift * vfp_base_count)) - 1; | |
4683 | for (regno = 0; regno < 16; regno += shift) | |
4684 | if (((vfp_regs_free >> regno) & mask) == mask) | |
4685 | break; | |
4686 | ||
4687 | if (regno < 16) | |
4688 | { | |
4689 | int reg_char; | |
4690 | int reg_scaled; | |
4691 | int i; | |
4692 | ||
4693 | vfp_regs_free &= ~(mask << regno); | |
4694 | reg_scaled = regno / shift; | |
4695 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
4696 | for (i = 0; i < vfp_base_count; i++) | |
4697 | { | |
4698 | char name_buf[4]; | |
4699 | int regnum; | |
58d6951d DJ |
4700 | if (reg_char == 'q') |
4701 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 4702 | val + i * unit_length); |
58d6951d DJ |
4703 | else |
4704 | { | |
8c042590 PM |
4705 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
4706 | reg_char, reg_scaled + i); | |
58d6951d DJ |
4707 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
4708 | strlen (name_buf)); | |
b66f5587 | 4709 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 4710 | } |
90445bd3 DJ |
4711 | } |
4712 | continue; | |
4713 | } | |
4714 | else | |
4715 | { | |
4716 | /* This CPRC could not go in VFP registers, so all VFP | |
4717 | registers are now marked as used. */ | |
4718 | vfp_regs_free = 0; | |
4719 | } | |
4720 | } | |
4721 | ||
85102364 | 4722 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
4723 | if (nstack & (align - 1)) |
4724 | { | |
f0452268 AH |
4725 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
4726 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
4727 | } |
4728 | ||
4729 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
4730 | if (may_use_core_reg |
4731 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 4732 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
4733 | && argreg & 1) |
4734 | argreg++; | |
4735 | ||
2dd604e7 RE |
4736 | /* If the argument is a pointer to a function, and it is a |
4737 | Thumb function, create a LOCAL copy of the value and set | |
4738 | the THUMB bit in it. */ | |
4739 | if (TYPE_CODE_PTR == typecode | |
4740 | && target_type != NULL | |
78134374 | 4741 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 4742 | { |
e17a4113 | 4743 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 4744 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 4745 | { |
224c3ddb | 4746 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 4747 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 4748 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 4749 | val = copy; |
2dd604e7 RE |
4750 | } |
4751 | } | |
4752 | ||
4753 | /* Copy the argument to general registers or the stack in | |
4754 | register-sized pieces. Large arguments are split between | |
4755 | registers and stack. */ | |
4756 | while (len > 0) | |
4757 | { | |
f0452268 AH |
4758 | int partial_len = len < ARM_INT_REGISTER_SIZE |
4759 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
4760 | CORE_ADDR regval |
4761 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 4762 | |
90445bd3 | 4763 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
4764 | { |
4765 | /* The argument is being passed in a general purpose | |
4766 | register. */ | |
e17a4113 | 4767 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 4768 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
7cb6d92a SM |
4769 | |
4770 | arm_debug_printf ("arg %d in %s = 0x%s", argnum, | |
4771 | gdbarch_register_name (gdbarch, argreg), | |
4772 | phex (regval, ARM_INT_REGISTER_SIZE)); | |
4773 | ||
2dd604e7 RE |
4774 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
4775 | argreg++; | |
4776 | } | |
4777 | else | |
4778 | { | |
f0452268 | 4779 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
4780 | |
4781 | memset (buf, 0, sizeof (buf)); | |
4782 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
4783 | ||
2dd604e7 | 4784 | /* Push the arguments onto the stack. */ |
7cb6d92a | 4785 | arm_debug_printf ("arg %d @ sp + %d", argnum, nstack); |
f0452268 AH |
4786 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
4787 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
4788 | } |
4789 | ||
4790 | len -= partial_len; | |
4791 | val += partial_len; | |
4792 | } | |
4793 | } | |
4794 | /* If we have an odd number of words to push, then decrement the stack | |
4795 | by one word now, so first stack argument will be dword aligned. */ | |
4796 | if (nstack & 4) | |
4797 | sp -= 4; | |
4798 | ||
4799 | while (si) | |
4800 | { | |
4801 | sp -= si->len; | |
4802 | write_memory (sp, si->data, si->len); | |
4803 | si = pop_stack_item (si); | |
4804 | } | |
4805 | ||
4806 | /* Finally, update teh SP register. */ | |
4807 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
4808 | ||
4809 | return sp; | |
4810 | } | |
4811 | ||
f53f0d0b PB |
4812 | |
4813 | /* Always align the frame to an 8-byte boundary. This is required on | |
4814 | some platforms and harmless on the rest. */ | |
4815 | ||
4816 | static CORE_ADDR | |
4817 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
4818 | { | |
4819 | /* Align the stack to eight bytes. */ | |
4820 | return sp & ~ (CORE_ADDR) 7; | |
4821 | } | |
4822 | ||
c906108c | 4823 | static void |
12b27276 | 4824 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 4825 | { |
c5aa993b | 4826 | if (flags & (1 << 0)) |
0426ad51 | 4827 | gdb_puts ("IVO ", file); |
c5aa993b | 4828 | if (flags & (1 << 1)) |
0426ad51 | 4829 | gdb_puts ("DVZ ", file); |
c5aa993b | 4830 | if (flags & (1 << 2)) |
0426ad51 | 4831 | gdb_puts ("OFL ", file); |
c5aa993b | 4832 | if (flags & (1 << 3)) |
0426ad51 | 4833 | gdb_puts ("UFL ", file); |
c5aa993b | 4834 | if (flags & (1 << 4)) |
0426ad51 | 4835 | gdb_puts ("INX ", file); |
a11ac3b3 | 4836 | gdb_putc ('\n', file); |
c906108c SS |
4837 | } |
4838 | ||
5e74b15c RE |
4839 | /* Print interesting information about the floating point processor |
4840 | (if present) or emulator. */ | |
34e8f22d | 4841 | static void |
d855c300 | 4842 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 4843 | frame_info_ptr frame, const char *args) |
c906108c | 4844 | { |
9c9acae0 | 4845 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4846 | int type; |
4847 | ||
4848 | type = (status >> 24) & 127; | |
edefbb7c | 4849 | if (status & (1 << 31)) |
6cb06a8c | 4850 | gdb_printf (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4851 | else |
6cb06a8c | 4852 | gdb_printf (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4853 | /* i18n: [floating point unit] mask */ |
0426ad51 | 4854 | gdb_puts (_("mask: "), file); |
12b27276 | 4855 | print_fpu_flags (file, status >> 16); |
edefbb7c | 4856 | /* i18n: [floating point unit] flags */ |
0426ad51 | 4857 | gdb_puts (_("flags: "), file); |
12b27276 | 4858 | print_fpu_flags (file, status); |
c906108c SS |
4859 | } |
4860 | ||
27067745 UW |
4861 | /* Construct the ARM extended floating point type. */ |
4862 | static struct type * | |
4863 | arm_ext_type (struct gdbarch *gdbarch) | |
4864 | { | |
08106042 | 4865 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
27067745 UW |
4866 | |
4867 | if (!tdep->arm_ext_type) | |
4868 | tdep->arm_ext_type | |
e9bb382b | 4869 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4870 | floatformats_arm_ext); |
4871 | ||
4872 | return tdep->arm_ext_type; | |
4873 | } | |
4874 | ||
58d6951d DJ |
4875 | static struct type * |
4876 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4877 | { | |
08106042 | 4878 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4879 | |
4880 | if (tdep->neon_double_type == NULL) | |
4881 | { | |
4882 | struct type *t, *elem; | |
4883 | ||
4884 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4885 | TYPE_CODE_UNION); | |
4886 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4887 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4888 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4889 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4890 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4891 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4892 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4893 | append_composite_type_field (t, "u64", elem); | |
4894 | elem = builtin_type (gdbarch)->builtin_float; | |
4895 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4896 | elem = builtin_type (gdbarch)->builtin_double; | |
4897 | append_composite_type_field (t, "f64", elem); | |
4898 | ||
2062087b | 4899 | t->set_is_vector (true); |
d0e39ea2 | 4900 | t->set_name ("neon_d"); |
58d6951d DJ |
4901 | tdep->neon_double_type = t; |
4902 | } | |
4903 | ||
4904 | return tdep->neon_double_type; | |
4905 | } | |
4906 | ||
4907 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4908 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4909 | bits of d0 - regardless of what unit size is being held in d0. So | |
4910 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4911 | first float is 4. This code works as-is for little-endian | |
4912 | targets. */ | |
4913 | ||
4914 | static struct type * | |
4915 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4916 | { | |
08106042 | 4917 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4918 | |
4919 | if (tdep->neon_quad_type == NULL) | |
4920 | { | |
4921 | struct type *t, *elem; | |
4922 | ||
4923 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4924 | TYPE_CODE_UNION); | |
4925 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4926 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4927 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4928 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4929 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4930 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4931 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4932 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4933 | elem = builtin_type (gdbarch)->builtin_float; | |
4934 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4935 | elem = builtin_type (gdbarch)->builtin_double; | |
4936 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4937 | ||
2062087b | 4938 | t->set_is_vector (true); |
d0e39ea2 | 4939 | t->set_name ("neon_q"); |
58d6951d DJ |
4940 | tdep->neon_quad_type = t; |
4941 | } | |
4942 | ||
4943 | return tdep->neon_quad_type; | |
4944 | } | |
4945 | ||
ecbf5d4f LM |
4946 | /* Return true if REGNUM is a Q pseudo register. Return false |
4947 | otherwise. | |
4948 | ||
4949 | REGNUM is the raw register number and not a pseudo-relative register | |
4950 | number. */ | |
4951 | ||
4952 | static bool | |
4953 | is_q_pseudo (struct gdbarch *gdbarch, int regnum) | |
4954 | { | |
08106042 | 4955 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f | 4956 | |
ae66a8f1 SP |
4957 | /* Q pseudo registers are available for both NEON (Q0~Q15) and |
4958 | MVE (Q0~Q7) features. */ | |
ecbf5d4f LM |
4959 | if (tdep->have_q_pseudos |
4960 | && regnum >= tdep->q_pseudo_base | |
4961 | && regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count)) | |
4962 | return true; | |
4963 | ||
4964 | return false; | |
4965 | } | |
4966 | ||
4967 | /* Return true if REGNUM is a VFP S pseudo register. Return false | |
4968 | otherwise. | |
4969 | ||
4970 | REGNUM is the raw register number and not a pseudo-relative register | |
4971 | number. */ | |
4972 | ||
4973 | static bool | |
4974 | is_s_pseudo (struct gdbarch *gdbarch, int regnum) | |
4975 | { | |
08106042 | 4976 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f LM |
4977 | |
4978 | if (tdep->have_s_pseudos | |
4979 | && regnum >= tdep->s_pseudo_base | |
4980 | && regnum < (tdep->s_pseudo_base + tdep->s_pseudo_count)) | |
4981 | return true; | |
4982 | ||
4983 | return false; | |
4984 | } | |
4985 | ||
ae66a8f1 SP |
4986 | /* Return true if REGNUM is a MVE pseudo register (P0). Return false |
4987 | otherwise. | |
4988 | ||
4989 | REGNUM is the raw register number and not a pseudo-relative register | |
4990 | number. */ | |
4991 | ||
4992 | static bool | |
4993 | is_mve_pseudo (struct gdbarch *gdbarch, int regnum) | |
4994 | { | |
08106042 | 4995 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
4996 | |
4997 | if (tdep->have_mve | |
4998 | && regnum >= tdep->mve_pseudo_base | |
4999 | && regnum < tdep->mve_pseudo_base + tdep->mve_pseudo_count) | |
5000 | return true; | |
5001 | ||
5002 | return false; | |
5003 | } | |
5004 | ||
a01567f4 LM |
5005 | /* Return true if REGNUM is a PACBTI pseudo register (ra_auth_code). Return |
5006 | false otherwise. | |
5007 | ||
5008 | REGNUM is the raw register number and not a pseudo-relative register | |
5009 | number. */ | |
5010 | ||
5011 | static bool | |
5012 | is_pacbti_pseudo (struct gdbarch *gdbarch, int regnum) | |
5013 | { | |
08106042 | 5014 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
5015 | |
5016 | if (tdep->have_pacbti | |
5017 | && regnum >= tdep->pacbti_pseudo_base | |
5018 | && regnum < tdep->pacbti_pseudo_base + tdep->pacbti_pseudo_count) | |
5019 | return true; | |
5020 | ||
5021 | return false; | |
5022 | } | |
5023 | ||
34e8f22d RE |
5024 | /* Return the GDB type object for the "standard" data type of data in |
5025 | register N. */ | |
5026 | ||
5027 | static struct type * | |
7a5ea0d4 | 5028 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 5029 | { |
08106042 | 5030 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 5031 | |
ecbf5d4f | 5032 | if (is_s_pseudo (gdbarch, regnum)) |
58d6951d DJ |
5033 | return builtin_type (gdbarch)->builtin_float; |
5034 | ||
ecbf5d4f | 5035 | if (is_q_pseudo (gdbarch, regnum)) |
58d6951d DJ |
5036 | return arm_neon_quad_type (gdbarch); |
5037 | ||
ae66a8f1 SP |
5038 | if (is_mve_pseudo (gdbarch, regnum)) |
5039 | return builtin_type (gdbarch)->builtin_int16; | |
5040 | ||
a01567f4 LM |
5041 | if (is_pacbti_pseudo (gdbarch, regnum)) |
5042 | return builtin_type (gdbarch)->builtin_uint32; | |
5043 | ||
58d6951d DJ |
5044 | /* If the target description has register information, we are only |
5045 | in this function so that we can override the types of | |
5046 | double-precision registers for NEON. */ | |
5047 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
5048 | { | |
5049 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
5050 | ||
5051 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 5052 | && t->code () == TYPE_CODE_FLT |
ecbf5d4f | 5053 | && tdep->have_neon) |
58d6951d DJ |
5054 | return arm_neon_double_type (gdbarch); |
5055 | else | |
5056 | return t; | |
5057 | } | |
5058 | ||
34e8f22d | 5059 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d | 5060 | { |
ecbf5d4f | 5061 | if (!tdep->have_fpa_registers) |
58d6951d DJ |
5062 | return builtin_type (gdbarch)->builtin_void; |
5063 | ||
5064 | return arm_ext_type (gdbarch); | |
5065 | } | |
e4c16157 | 5066 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 5067 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 5068 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 5069 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
5070 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
5071 | /* These registers are only supported on targets which supply | |
5072 | an XML description. */ | |
df4df182 | 5073 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 5074 | else |
df4df182 | 5075 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
5076 | } |
5077 | ||
ff6f572f DJ |
5078 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
5079 | number. */ | |
5080 | ||
5081 | static int | |
d3f73121 | 5082 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
5083 | { |
5084 | /* Core integer regs. */ | |
5085 | if (reg >= 0 && reg <= 15) | |
5086 | return reg; | |
5087 | ||
5088 | /* Legacy FPA encoding. These were once used in a way which | |
5089 | overlapped with VFP register numbering, so their use is | |
5090 | discouraged, but GDB doesn't support the ARM toolchain | |
5091 | which used them for VFP. */ | |
5092 | if (reg >= 16 && reg <= 23) | |
5093 | return ARM_F0_REGNUM + reg - 16; | |
5094 | ||
5095 | /* New assignments for the FPA registers. */ | |
5096 | if (reg >= 96 && reg <= 103) | |
5097 | return ARM_F0_REGNUM + reg - 96; | |
5098 | ||
5099 | /* WMMX register assignments. */ | |
5100 | if (reg >= 104 && reg <= 111) | |
5101 | return ARM_WCGR0_REGNUM + reg - 104; | |
5102 | ||
5103 | if (reg >= 112 && reg <= 127) | |
5104 | return ARM_WR0_REGNUM + reg - 112; | |
5105 | ||
a01567f4 LM |
5106 | /* PACBTI register containing the Pointer Authentication Code. */ |
5107 | if (reg == ARM_DWARF_RA_AUTH_CODE) | |
5108 | { | |
08106042 | 5109 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
5110 | |
5111 | if (tdep->have_pacbti) | |
5112 | return tdep->pacbti_pseudo_base; | |
5113 | ||
5114 | return -1; | |
5115 | } | |
5116 | ||
ff6f572f DJ |
5117 | if (reg >= 192 && reg <= 199) |
5118 | return ARM_WC0_REGNUM + reg - 192; | |
5119 | ||
58d6951d DJ |
5120 | /* VFP v2 registers. A double precision value is actually |
5121 | in d1 rather than s2, but the ABI only defines numbering | |
5122 | for the single precision registers. This will "just work" | |
5123 | in GDB for little endian targets (we'll read eight bytes, | |
5124 | starting in s0 and then progressing to s1), but will be | |
5125 | reversed on big endian targets with VFP. This won't | |
5126 | be a problem for the new Neon quad registers; you're supposed | |
5127 | to use DW_OP_piece for those. */ | |
5128 | if (reg >= 64 && reg <= 95) | |
5129 | { | |
5130 | char name_buf[4]; | |
5131 | ||
8c042590 | 5132 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
5133 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
5134 | strlen (name_buf)); | |
5135 | } | |
5136 | ||
5137 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
5138 | registers, except that it now describes d0 instead of s0. */ | |
5139 | if (reg >= 256 && reg <= 287) | |
5140 | { | |
5141 | char name_buf[4]; | |
5142 | ||
8c042590 | 5143 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
5144 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
5145 | strlen (name_buf)); | |
5146 | } | |
5147 | ||
ff6f572f DJ |
5148 | return -1; |
5149 | } | |
5150 | ||
26216b98 AC |
5151 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
5152 | static int | |
e7faf938 | 5153 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
5154 | { |
5155 | int reg = regnum; | |
e7faf938 | 5156 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 5157 | |
ff6f572f DJ |
5158 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
5159 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
5160 | ||
5161 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
5162 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
5163 | ||
5164 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
5165 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
5166 | ||
26216b98 AC |
5167 | if (reg < NUM_GREGS) |
5168 | return SIM_ARM_R0_REGNUM + reg; | |
5169 | reg -= NUM_GREGS; | |
5170 | ||
5171 | if (reg < NUM_FREGS) | |
5172 | return SIM_ARM_FP0_REGNUM + reg; | |
5173 | reg -= NUM_FREGS; | |
5174 | ||
5175 | if (reg < NUM_SREGS) | |
5176 | return SIM_ARM_FPS_REGNUM + reg; | |
5177 | reg -= NUM_SREGS; | |
5178 | ||
f34652de | 5179 | internal_error (_("Bad REGNUM %d"), regnum); |
26216b98 | 5180 | } |
34e8f22d | 5181 | |
a01567f4 LM |
5182 | static const unsigned char op_lit0 = DW_OP_lit0; |
5183 | ||
5184 | static void | |
5185 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
5186 | struct dwarf2_frame_state_reg *reg, | |
bd2b40ac | 5187 | frame_info_ptr this_frame) |
a01567f4 | 5188 | { |
a6e4a48c YR |
5189 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
5190 | ||
a01567f4 LM |
5191 | if (is_pacbti_pseudo (gdbarch, regnum)) |
5192 | { | |
5193 | /* Initialize RA_AUTH_CODE to zero. */ | |
5194 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
5195 | reg->loc.exp.start = &op_lit0; | |
5196 | reg->loc.exp.len = 1; | |
5197 | return; | |
5198 | } | |
5199 | ||
42e11f36 | 5200 | if (regnum == ARM_PC_REGNUM || regnum == ARM_PS_REGNUM) |
a01567f4 | 5201 | { |
a01567f4 LM |
5202 | reg->how = DWARF2_FRAME_REG_FN; |
5203 | reg->loc.fn = arm_dwarf2_prev_register; | |
a01567f4 | 5204 | } |
42e11f36 TS |
5205 | else if (regnum == ARM_SP_REGNUM) |
5206 | reg->how = DWARF2_FRAME_REG_CFA; | |
a6e4a48c YR |
5207 | else if (arm_is_alternative_sp_register (tdep, regnum)) |
5208 | { | |
5209 | /* Handle the alternative SP registers on Cortex-M. */ | |
5210 | reg->how = DWARF2_FRAME_REG_FN; | |
5211 | reg->loc.fn = arm_dwarf2_prev_register; | |
5212 | } | |
a01567f4 LM |
5213 | } |
5214 | ||
d9311bfa AT |
5215 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
5216 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
5217 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 5218 | |
d9311bfa AT |
5219 | static gdb_byte * |
5220 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
5221 | int old_len, int new_len) | |
5222 | { | |
5223 | gdb_byte *new_buf; | |
5224 | int bytes_to_read = new_len - old_len; | |
c906108c | 5225 | |
d9311bfa AT |
5226 | new_buf = (gdb_byte *) xmalloc (new_len); |
5227 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
5228 | xfree (buf); | |
198cd59d | 5229 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
5230 | { |
5231 | xfree (new_buf); | |
5232 | return NULL; | |
c906108c | 5233 | } |
d9311bfa | 5234 | return new_buf; |
c906108c SS |
5235 | } |
5236 | ||
d9311bfa AT |
5237 | /* An IT block is at most the 2-byte IT instruction followed by |
5238 | four 4-byte instructions. The furthest back we must search to | |
5239 | find an IT block that affects the current instruction is thus | |
5240 | 2 + 3 * 4 == 14 bytes. */ | |
5241 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 5242 | |
d9311bfa AT |
5243 | /* Use a quick scan if there are more than this many bytes of |
5244 | code. */ | |
5245 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 5246 | |
d9311bfa AT |
5247 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
5248 | A breakpoint in an IT block may not be hit, depending on the | |
5249 | condition flags. */ | |
ad527d2e | 5250 | static CORE_ADDR |
d9311bfa | 5251 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 5252 | { |
d9311bfa AT |
5253 | gdb_byte *buf; |
5254 | char map_type; | |
5255 | CORE_ADDR boundary, func_start; | |
5256 | int buf_len; | |
5257 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
5258 | int i, any, last_it, last_it_count; | |
08106042 | 5259 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 5260 | |
d9311bfa | 5261 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
345bd07c | 5262 | if (tdep->thumb2_breakpoint == NULL) |
d9311bfa | 5263 | return bpaddr; |
177321bd | 5264 | |
d9311bfa AT |
5265 | /* ARM mode does not have this problem. */ |
5266 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
5267 | return bpaddr; | |
177321bd | 5268 | |
d9311bfa AT |
5269 | /* We are setting a breakpoint in Thumb code that could potentially |
5270 | contain an IT block. The first step is to find how much Thumb | |
5271 | code there is; we do not need to read outside of known Thumb | |
5272 | sequences. */ | |
5273 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
5274 | if (map_type == 0) | |
5275 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
5276 | return bpaddr; | |
9dca5578 | 5277 | |
d9311bfa | 5278 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 5279 | |
d9311bfa AT |
5280 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
5281 | && func_start > boundary) | |
5282 | boundary = func_start; | |
9dca5578 | 5283 | |
d9311bfa AT |
5284 | /* Search for a candidate IT instruction. We have to do some fancy |
5285 | footwork to distinguish a real IT instruction from the second | |
5286 | half of a 32-bit instruction, but there is no need for that if | |
5287 | there's no candidate. */ | |
325fac50 | 5288 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
5289 | if (buf_len == 0) |
5290 | /* No room for an IT instruction. */ | |
5291 | return bpaddr; | |
c906108c | 5292 | |
d9311bfa | 5293 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 5294 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
5295 | return bpaddr; |
5296 | any = 0; | |
5297 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 5298 | { |
d9311bfa AT |
5299 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
5300 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 5301 | { |
d9311bfa AT |
5302 | any = 1; |
5303 | break; | |
25b41d01 | 5304 | } |
c906108c | 5305 | } |
d9311bfa AT |
5306 | |
5307 | if (any == 0) | |
c906108c | 5308 | { |
d9311bfa AT |
5309 | xfree (buf); |
5310 | return bpaddr; | |
f9d67f43 DJ |
5311 | } |
5312 | ||
5313 | /* OK, the code bytes before this instruction contain at least one | |
5314 | halfword which resembles an IT instruction. We know that it's | |
5315 | Thumb code, but there are still two possibilities. Either the | |
5316 | halfword really is an IT instruction, or it is the second half of | |
5317 | a 32-bit Thumb instruction. The only way we can tell is to | |
5318 | scan forwards from a known instruction boundary. */ | |
5319 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
5320 | { | |
5321 | int definite; | |
5322 | ||
5323 | /* There's a lot of code before this instruction. Start with an | |
5324 | optimistic search; it's easy to recognize halfwords that can | |
5325 | not be the start of a 32-bit instruction, and use that to | |
5326 | lock on to the instruction boundaries. */ | |
5327 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
5328 | if (buf == NULL) | |
5329 | return bpaddr; | |
5330 | buf_len = IT_SCAN_THRESHOLD; | |
5331 | ||
5332 | definite = 0; | |
5333 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
5334 | { | |
5335 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5336 | if (thumb_insn_size (inst1) == 2) | |
5337 | { | |
5338 | definite = 1; | |
5339 | break; | |
5340 | } | |
5341 | } | |
5342 | ||
5343 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
5344 | are sure that we know the instruction boundaries, and it is far | |
5345 | enough from BPADDR that we could not miss an IT instruction | |
5346 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
5347 | known boundary. */ | |
5348 | if (! definite) | |
5349 | { | |
0963b4bd MS |
5350 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
5351 | bpaddr - boundary); | |
f9d67f43 DJ |
5352 | if (buf == NULL) |
5353 | return bpaddr; | |
5354 | buf_len = bpaddr - boundary; | |
5355 | i = 0; | |
5356 | } | |
5357 | } | |
5358 | else | |
5359 | { | |
5360 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
5361 | if (buf == NULL) | |
5362 | return bpaddr; | |
5363 | buf_len = bpaddr - boundary; | |
5364 | i = 0; | |
5365 | } | |
5366 | ||
5367 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
5368 | last_it = -1; | |
5369 | last_it_count = 0; | |
5370 | while (i < buf_len) | |
5371 | { | |
5372 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5373 | last_it_count--; | |
5374 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
5375 | { | |
5376 | last_it = i; | |
5377 | if (inst1 & 0x0001) | |
5378 | last_it_count = 4; | |
5379 | else if (inst1 & 0x0002) | |
5380 | last_it_count = 3; | |
5381 | else if (inst1 & 0x0004) | |
5382 | last_it_count = 2; | |
5383 | else | |
5384 | last_it_count = 1; | |
5385 | } | |
5386 | i += thumb_insn_size (inst1); | |
5387 | } | |
5388 | ||
5389 | xfree (buf); | |
5390 | ||
5391 | if (last_it == -1) | |
5392 | /* There wasn't really an IT instruction after all. */ | |
5393 | return bpaddr; | |
5394 | ||
5395 | if (last_it_count < 1) | |
5396 | /* It was too far away. */ | |
5397 | return bpaddr; | |
5398 | ||
5399 | /* This really is a trouble spot. Move the breakpoint to the IT | |
5400 | instruction. */ | |
5401 | return bpaddr - buf_len + last_it; | |
5402 | } | |
5403 | ||
cca44b1b | 5404 | /* ARM displaced stepping support. |
c906108c | 5405 | |
cca44b1b | 5406 | Generally ARM displaced stepping works as follows: |
c906108c | 5407 | |
cca44b1b | 5408 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
5409 | arm_process_displaced_insn. Depending on the type of instruction, it is |
5410 | then copied to a scratch location, possibly in a modified form. The | |
5411 | copy_* set of functions performs such modification, as necessary. A | |
5412 | breakpoint is placed after the modified instruction in the scratch space | |
5413 | to return control to GDB. Note in particular that instructions which | |
5414 | modify the PC will no longer do so after modification. | |
c5aa993b | 5415 | |
cca44b1b JB |
5416 | 2. The instruction is single-stepped, by setting the PC to the scratch |
5417 | location address, and resuming. Control returns to GDB when the | |
5418 | breakpoint is hit. | |
c5aa993b | 5419 | |
cca44b1b JB |
5420 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
5421 | function used for the current instruction. This function's job is to | |
5422 | put the CPU/memory state back to what it would have been if the | |
5423 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 5424 | |
cca44b1b JB |
5425 | /* NOP instruction (mov r0, r0). */ |
5426 | #define ARM_NOP 0xe1a00000 | |
34518530 | 5427 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
5428 | |
5429 | /* Helper for register reads for displaced stepping. In particular, this | |
5430 | returns the PC as it would be seen by the instruction at its original | |
5431 | location. */ | |
5432 | ||
5433 | ULONGEST | |
1152d984 | 5434 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5435 | int regno) |
cca44b1b JB |
5436 | { |
5437 | ULONGEST ret; | |
36073a92 | 5438 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 5439 | |
bf9f652a | 5440 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 5441 | { |
4db71c0b YQ |
5442 | /* Compute pipeline offset: |
5443 | - When executing an ARM instruction, PC reads as the address of the | |
5444 | current instruction plus 8. | |
5445 | - When executing a Thumb instruction, PC reads as the address of the | |
5446 | current instruction plus 4. */ | |
5447 | ||
36073a92 | 5448 | if (!dsc->is_thumb) |
4db71c0b YQ |
5449 | from += 8; |
5450 | else | |
5451 | from += 4; | |
5452 | ||
136821d9 SM |
5453 | displaced_debug_printf ("read pc value %.8lx", |
5454 | (unsigned long) from); | |
4db71c0b | 5455 | return (ULONGEST) from; |
cca44b1b | 5456 | } |
c906108c | 5457 | else |
cca44b1b JB |
5458 | { |
5459 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
5460 | |
5461 | displaced_debug_printf ("read r%d value %.8lx", | |
5462 | regno, (unsigned long) ret); | |
5463 | ||
cca44b1b JB |
5464 | return ret; |
5465 | } | |
c906108c SS |
5466 | } |
5467 | ||
cca44b1b JB |
5468 | static int |
5469 | displaced_in_arm_mode (struct regcache *regs) | |
5470 | { | |
5471 | ULONGEST ps; | |
ac7936df | 5472 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 5473 | |
cca44b1b | 5474 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 5475 | |
9779414d | 5476 | return (ps & t_bit) == 0; |
cca44b1b | 5477 | } |
66e810cd | 5478 | |
cca44b1b | 5479 | /* Write to the PC as from a branch instruction. */ |
c906108c | 5480 | |
cca44b1b | 5481 | static void |
1152d984 | 5482 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5483 | ULONGEST val) |
c906108c | 5484 | { |
36073a92 | 5485 | if (!dsc->is_thumb) |
cca44b1b JB |
5486 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
5487 | architecture versions < 6. */ | |
0963b4bd MS |
5488 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5489 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 5490 | else |
0963b4bd MS |
5491 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5492 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 5493 | } |
66e810cd | 5494 | |
cca44b1b JB |
5495 | /* Write to the PC as from a branch-exchange instruction. */ |
5496 | ||
5497 | static void | |
5498 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
5499 | { | |
5500 | ULONGEST ps; | |
ac7936df | 5501 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
5502 | |
5503 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
5504 | ||
5505 | if ((val & 1) == 1) | |
c906108c | 5506 | { |
9779414d | 5507 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
5508 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
5509 | } | |
5510 | else if ((val & 2) == 0) | |
5511 | { | |
9779414d | 5512 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5513 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
5514 | } |
5515 | else | |
5516 | { | |
cca44b1b JB |
5517 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
5518 | mode, align dest to 4 bytes). */ | |
5519 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 5520 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5521 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
5522 | } |
5523 | } | |
ed9a39eb | 5524 | |
cca44b1b | 5525 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 5526 | |
34e8f22d | 5527 | static void |
1152d984 | 5528 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5529 | ULONGEST val) |
ed9a39eb | 5530 | { |
cca44b1b JB |
5531 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
5532 | bx_write_pc (regs, val); | |
5533 | else | |
36073a92 | 5534 | branch_write_pc (regs, dsc, val); |
cca44b1b | 5535 | } |
be8626e0 | 5536 | |
cca44b1b JB |
5537 | /* Write to the PC as if from an ALU instruction. */ |
5538 | ||
5539 | static void | |
1152d984 | 5540 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5541 | ULONGEST val) |
cca44b1b | 5542 | { |
36073a92 | 5543 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
5544 | bx_write_pc (regs, val); |
5545 | else | |
36073a92 | 5546 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
5547 | } |
5548 | ||
5549 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
5550 | has a varying effects depending on the instruction which does the write: | |
5551 | this is controlled by the WRITE_PC argument. */ | |
5552 | ||
5553 | void | |
1152d984 | 5554 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
5555 | int regno, ULONGEST val, enum pc_write_style write_pc) |
5556 | { | |
bf9f652a | 5557 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 5558 | { |
136821d9 SM |
5559 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
5560 | ||
cca44b1b | 5561 | switch (write_pc) |
08216dd7 | 5562 | { |
cca44b1b | 5563 | case BRANCH_WRITE_PC: |
36073a92 | 5564 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
5565 | break; |
5566 | ||
cca44b1b JB |
5567 | case BX_WRITE_PC: |
5568 | bx_write_pc (regs, val); | |
24b21115 | 5569 | break; |
cca44b1b JB |
5570 | |
5571 | case LOAD_WRITE_PC: | |
36073a92 | 5572 | load_write_pc (regs, dsc, val); |
24b21115 | 5573 | break; |
cca44b1b JB |
5574 | |
5575 | case ALU_WRITE_PC: | |
36073a92 | 5576 | alu_write_pc (regs, dsc, val); |
24b21115 | 5577 | break; |
cca44b1b JB |
5578 | |
5579 | case CANNOT_WRITE_PC: | |
5580 | warning (_("Instruction wrote to PC in an unexpected way when " | |
5581 | "single-stepping")); | |
08216dd7 RE |
5582 | break; |
5583 | ||
5584 | default: | |
f34652de | 5585 | internal_error (_("Invalid argument to displaced_write_reg")); |
08216dd7 | 5586 | } |
b508a996 | 5587 | |
cca44b1b | 5588 | dsc->wrote_to_pc = 1; |
b508a996 | 5589 | } |
ed9a39eb | 5590 | else |
b508a996 | 5591 | { |
136821d9 SM |
5592 | displaced_debug_printf ("writing r%d value %.8lx", |
5593 | regno, (unsigned long) val); | |
cca44b1b | 5594 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 5595 | } |
34e8f22d RE |
5596 | } |
5597 | ||
cca44b1b JB |
5598 | /* This function is used to concisely determine if an instruction INSN |
5599 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
5600 | corresponding fields of BITMASK set to 0b1111. The function |
5601 | returns return 1 if any of these fields in INSN reference the PC | |
5602 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
5603 | |
5604 | static int | |
cca44b1b | 5605 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 5606 | { |
cca44b1b | 5607 | uint32_t lowbit = 1; |
67255d04 | 5608 | |
cca44b1b JB |
5609 | while (bitmask != 0) |
5610 | { | |
5611 | uint32_t mask; | |
44e1a9eb | 5612 | |
cca44b1b JB |
5613 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
5614 | ; | |
67255d04 | 5615 | |
cca44b1b JB |
5616 | if (!lowbit) |
5617 | break; | |
67255d04 | 5618 | |
cca44b1b | 5619 | mask = lowbit * 0xf; |
67255d04 | 5620 | |
cca44b1b JB |
5621 | if ((insn & mask) == mask) |
5622 | return 1; | |
5623 | ||
5624 | bitmask &= ~mask; | |
67255d04 RE |
5625 | } |
5626 | ||
cca44b1b JB |
5627 | return 0; |
5628 | } | |
2af48f68 | 5629 | |
cca44b1b JB |
5630 | /* The simplest copy function. Many instructions have the same effect no |
5631 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 5632 | |
cca44b1b | 5633 | static int |
1152d984 SM |
5634 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
5635 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 5636 | { |
136821d9 SM |
5637 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
5638 | (unsigned long) insn, iname); | |
67255d04 | 5639 | |
cca44b1b | 5640 | dsc->modinsn[0] = insn; |
67255d04 | 5641 | |
cca44b1b JB |
5642 | return 0; |
5643 | } | |
5644 | ||
34518530 YQ |
5645 | static int |
5646 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
5647 | uint16_t insn2, const char *iname, | |
1152d984 | 5648 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5649 | { |
136821d9 SM |
5650 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
5651 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
5652 | |
5653 | dsc->modinsn[0] = insn1; | |
5654 | dsc->modinsn[1] = insn2; | |
5655 | dsc->numinsns = 2; | |
5656 | ||
5657 | return 0; | |
5658 | } | |
5659 | ||
5660 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
5661 | modification. */ | |
5662 | static int | |
615234c1 | 5663 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 5664 | const char *iname, |
1152d984 | 5665 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5666 | { |
136821d9 SM |
5667 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
5668 | insn, iname); | |
34518530 YQ |
5669 | |
5670 | dsc->modinsn[0] = insn; | |
5671 | ||
5672 | return 0; | |
5673 | } | |
5674 | ||
cca44b1b JB |
5675 | /* Preload instructions with immediate offset. */ |
5676 | ||
5677 | static void | |
1152d984 SM |
5678 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
5679 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
5680 | { |
5681 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5682 | if (!dsc->u.preload.immed) | |
5683 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5684 | } | |
5685 | ||
7ff120b4 YQ |
5686 | static void |
5687 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5688 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 5689 | { |
cca44b1b | 5690 | ULONGEST rn_val; |
cca44b1b JB |
5691 | /* Preload instructions: |
5692 | ||
5693 | {pli/pld} [rn, #+/-imm] | |
5694 | -> | |
5695 | {pli/pld} [r0, #+/-imm]. */ | |
5696 | ||
36073a92 YQ |
5697 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5698 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5699 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
5700 | dsc->u.preload.immed = 1; |
5701 | ||
cca44b1b | 5702 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
5703 | } |
5704 | ||
cca44b1b | 5705 | static int |
7ff120b4 | 5706 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5707 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5708 | { |
5709 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 5710 | |
7ff120b4 YQ |
5711 | if (!insn_references_pc (insn, 0x000f0000ul)) |
5712 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 5713 | |
136821d9 | 5714 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 5715 | |
7ff120b4 YQ |
5716 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5717 | ||
5718 | install_preload (gdbarch, regs, dsc, rn); | |
5719 | ||
5720 | return 0; | |
5721 | } | |
5722 | ||
34518530 YQ |
5723 | static int |
5724 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 5725 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5726 | { |
5727 | unsigned int rn = bits (insn1, 0, 3); | |
5728 | unsigned int u_bit = bit (insn1, 7); | |
5729 | int imm12 = bits (insn2, 0, 11); | |
5730 | ULONGEST pc_val; | |
5731 | ||
5732 | if (rn != ARM_PC_REGNUM) | |
5733 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
5734 | ||
5735 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
5736 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
5737 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
5738 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
5739 | imm12); | |
34518530 YQ |
5740 | |
5741 | if (!u_bit) | |
5742 | imm12 = -1 * imm12; | |
5743 | ||
5744 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
5745 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
5746 | ||
5747 | {pli/pld} [r0, r1] | |
5748 | ||
5749 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
5750 | ||
5751 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5752 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5753 | ||
5754 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5755 | ||
5756 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
5757 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
5758 | dsc->u.preload.immed = 0; | |
5759 | ||
5760 | /* {pli/pld} [r0, r1] */ | |
5761 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5762 | dsc->modinsn[1] = 0xf001; | |
5763 | dsc->numinsns = 2; | |
5764 | ||
5765 | dsc->cleanup = &cleanup_preload; | |
5766 | return 0; | |
5767 | } | |
5768 | ||
7ff120b4 YQ |
5769 | /* Preload instructions with register offset. */ |
5770 | ||
5771 | static void | |
5772 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5773 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
5774 | unsigned int rm) |
5775 | { | |
5776 | ULONGEST rn_val, rm_val; | |
5777 | ||
cca44b1b JB |
5778 | /* Preload register-offset instructions: |
5779 | ||
5780 | {pli/pld} [rn, rm {, shift}] | |
5781 | -> | |
5782 | {pli/pld} [r0, r1 {, shift}]. */ | |
5783 | ||
36073a92 YQ |
5784 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5785 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5786 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5787 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5788 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5789 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
5790 | dsc->u.preload.immed = 0; |
5791 | ||
cca44b1b | 5792 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
5793 | } |
5794 | ||
5795 | static int | |
5796 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5797 | struct regcache *regs, | |
1152d984 | 5798 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5799 | { |
5800 | unsigned int rn = bits (insn, 16, 19); | |
5801 | unsigned int rm = bits (insn, 0, 3); | |
5802 | ||
5803 | ||
5804 | if (!insn_references_pc (insn, 0x000f000ful)) | |
5805 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
5806 | ||
136821d9 SM |
5807 | displaced_debug_printf ("copying preload insn %.8lx", |
5808 | (unsigned long) insn); | |
7ff120b4 YQ |
5809 | |
5810 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 5811 | |
7ff120b4 | 5812 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
5813 | return 0; |
5814 | } | |
5815 | ||
5816 | /* Copy/cleanup coprocessor load and store instructions. */ | |
5817 | ||
5818 | static void | |
6e39997a | 5819 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 5820 | struct regcache *regs, |
1152d984 | 5821 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5822 | { |
36073a92 | 5823 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5824 | |
5825 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5826 | ||
5827 | if (dsc->u.ldst.writeback) | |
5828 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
5829 | } | |
5830 | ||
7ff120b4 YQ |
5831 | static void |
5832 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5833 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5834 | int writeback, unsigned int rn) |
cca44b1b | 5835 | { |
cca44b1b | 5836 | ULONGEST rn_val; |
cca44b1b | 5837 | |
cca44b1b JB |
5838 | /* Coprocessor load/store instructions: |
5839 | ||
5840 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
5841 | -> | |
5842 | {stc/stc2} [r0, #+/-imm]. | |
5843 | ||
5844 | ldc/ldc2 are handled identically. */ | |
5845 | ||
36073a92 YQ |
5846 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5847 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
5848 | /* PC should be 4-byte aligned. */ |
5849 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
5850 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5851 | ||
7ff120b4 | 5852 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5853 | dsc->u.ldst.rn = rn; |
5854 | ||
7ff120b4 YQ |
5855 | dsc->cleanup = &cleanup_copro_load_store; |
5856 | } | |
5857 | ||
5858 | static int | |
5859 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
5860 | struct regcache *regs, | |
1152d984 | 5861 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5862 | { |
5863 | unsigned int rn = bits (insn, 16, 19); | |
5864 | ||
5865 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
5866 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
5867 | ||
136821d9 SM |
5868 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
5869 | (unsigned long) insn); | |
7ff120b4 | 5870 | |
cca44b1b JB |
5871 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5872 | ||
7ff120b4 | 5873 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
5874 | |
5875 | return 0; | |
5876 | } | |
5877 | ||
34518530 YQ |
5878 | static int |
5879 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
5880 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5881 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5882 | { |
5883 | unsigned int rn = bits (insn1, 0, 3); | |
5884 | ||
5885 | if (rn != ARM_PC_REGNUM) | |
5886 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
5887 | "copro load/store", dsc); | |
5888 | ||
136821d9 SM |
5889 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
5890 | insn1, insn2); | |
34518530 YQ |
5891 | |
5892 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5893 | dsc->modinsn[1] = insn2; | |
5894 | dsc->numinsns = 2; | |
5895 | ||
5896 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
5897 | doesn't support writeback, so pass 0. */ | |
5898 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
5899 | ||
5900 | return 0; | |
5901 | } | |
5902 | ||
cca44b1b JB |
5903 | /* Clean up branch instructions (actually perform the branch, by setting |
5904 | PC). */ | |
5905 | ||
5906 | static void | |
6e39997a | 5907 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5908 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5909 | { |
36073a92 | 5910 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5911 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
5912 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
5913 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
5914 | ||
5915 | if (!branch_taken) | |
5916 | return; | |
5917 | ||
5918 | if (dsc->u.branch.link) | |
5919 | { | |
8c8dba6d | 5920 | /* The value of LR should be the next insn of current one. In order |
85102364 | 5921 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
5922 | is Thumb, the bit 0 of LR value should be set to 1. */ |
5923 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
5924 | ||
5925 | if (dsc->is_thumb) | |
5926 | next_insn_addr |= 0x1; | |
5927 | ||
5928 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
5929 | CANNOT_WRITE_PC); | |
cca44b1b JB |
5930 | } |
5931 | ||
bf9f652a | 5932 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
5933 | } |
5934 | ||
5935 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
5936 | ||
7ff120b4 YQ |
5937 | static void |
5938 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5939 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5940 | unsigned int cond, int exchange, int link, long offset) |
5941 | { | |
5942 | /* Implement "BL<cond> <label>" as: | |
5943 | ||
5944 | Preparation: cond <- instruction condition | |
5945 | Insn: mov r0, r0 (nop) | |
5946 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
5947 | ||
5948 | B<cond> similar, but don't set r14 in cleanup. */ | |
5949 | ||
5950 | dsc->u.branch.cond = cond; | |
5951 | dsc->u.branch.link = link; | |
5952 | dsc->u.branch.exchange = exchange; | |
5953 | ||
2b16b2e3 YQ |
5954 | dsc->u.branch.dest = dsc->insn_addr; |
5955 | if (link && exchange) | |
5956 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5957 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5958 | ||
7ff120b4 | 5959 | if (dsc->is_thumb) |
2b16b2e3 | 5960 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5961 | else |
2b16b2e3 | 5962 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5963 | |
5964 | dsc->cleanup = &cleanup_branch; | |
5965 | } | |
cca44b1b | 5966 | static int |
7ff120b4 | 5967 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5968 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5969 | { |
5970 | unsigned int cond = bits (insn, 28, 31); | |
5971 | int exchange = (cond == 0xf); | |
5972 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5973 | long offset; |
5974 | ||
136821d9 SM |
5975 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5976 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5977 | (unsigned long) insn); | |
cca44b1b JB |
5978 | if (exchange) |
5979 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5980 | then arrange the switch into Thumb mode. */ | |
5981 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5982 | else | |
5983 | offset = bits (insn, 0, 23) << 2; | |
5984 | ||
5985 | if (bit (offset, 25)) | |
5986 | offset = offset | ~0x3ffffff; | |
5987 | ||
cca44b1b JB |
5988 | dsc->modinsn[0] = ARM_NOP; |
5989 | ||
7ff120b4 | 5990 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5991 | return 0; |
5992 | } | |
5993 | ||
34518530 YQ |
5994 | static int |
5995 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5996 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5997 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5998 | { |
5999 | int link = bit (insn2, 14); | |
6000 | int exchange = link && !bit (insn2, 12); | |
6001 | int cond = INST_AL; | |
6002 | long offset = 0; | |
6003 | int j1 = bit (insn2, 13); | |
6004 | int j2 = bit (insn2, 11); | |
6005 | int s = sbits (insn1, 10, 10); | |
6006 | int i1 = !(j1 ^ bit (insn1, 10)); | |
6007 | int i2 = !(j2 ^ bit (insn1, 10)); | |
6008 | ||
6009 | if (!link && !exchange) /* B */ | |
6010 | { | |
6011 | offset = (bits (insn2, 0, 10) << 1); | |
6012 | if (bit (insn2, 12)) /* Encoding T4 */ | |
6013 | { | |
6014 | offset |= (bits (insn1, 0, 9) << 12) | |
6015 | | (i2 << 22) | |
6016 | | (i1 << 23) | |
6017 | | (s << 24); | |
6018 | cond = INST_AL; | |
6019 | } | |
6020 | else /* Encoding T3 */ | |
6021 | { | |
6022 | offset |= (bits (insn1, 0, 5) << 12) | |
6023 | | (j1 << 18) | |
6024 | | (j2 << 19) | |
6025 | | (s << 20); | |
6026 | cond = bits (insn1, 6, 9); | |
6027 | } | |
6028 | } | |
6029 | else | |
6030 | { | |
6031 | offset = (bits (insn1, 0, 9) << 12); | |
6032 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
6033 | offset |= exchange ? | |
6034 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
6035 | } | |
6036 | ||
136821d9 SM |
6037 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
6038 | link ? (exchange) ? "blx" : "bl" : "b", | |
6039 | insn1, insn2, offset); | |
34518530 YQ |
6040 | |
6041 | dsc->modinsn[0] = THUMB_NOP; | |
6042 | ||
6043 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
6044 | return 0; | |
6045 | } | |
6046 | ||
6047 | /* Copy B Thumb instructions. */ | |
6048 | static int | |
615234c1 | 6049 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 6050 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6051 | { |
6052 | unsigned int cond = 0; | |
6053 | int offset = 0; | |
6054 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
6055 | CORE_ADDR from = dsc->insn_addr; | |
6056 | ||
6057 | if (bit_12_15 == 0xd) | |
6058 | { | |
6059 | /* offset = SignExtend (imm8:0, 32) */ | |
6060 | offset = sbits ((insn << 1), 0, 8); | |
6061 | cond = bits (insn, 8, 11); | |
6062 | } | |
6063 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
6064 | { | |
6065 | offset = sbits ((insn << 1), 0, 11); | |
6066 | cond = INST_AL; | |
6067 | } | |
6068 | ||
136821d9 SM |
6069 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
6070 | insn, offset); | |
34518530 YQ |
6071 | |
6072 | dsc->u.branch.cond = cond; | |
6073 | dsc->u.branch.link = 0; | |
6074 | dsc->u.branch.exchange = 0; | |
6075 | dsc->u.branch.dest = from + 4 + offset; | |
6076 | ||
6077 | dsc->modinsn[0] = THUMB_NOP; | |
6078 | ||
6079 | dsc->cleanup = &cleanup_branch; | |
6080 | ||
6081 | return 0; | |
6082 | } | |
6083 | ||
cca44b1b JB |
6084 | /* Copy BX/BLX with register-specified destinations. */ |
6085 | ||
7ff120b4 YQ |
6086 | static void |
6087 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6088 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 6089 | unsigned int cond, unsigned int rm) |
cca44b1b | 6090 | { |
cca44b1b JB |
6091 | /* Implement {BX,BLX}<cond> <reg>" as: |
6092 | ||
6093 | Preparation: cond <- instruction condition | |
6094 | Insn: mov r0, r0 (nop) | |
6095 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
6096 | ||
6097 | Don't set r14 in cleanup for BX. */ | |
6098 | ||
36073a92 | 6099 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6100 | |
6101 | dsc->u.branch.cond = cond; | |
6102 | dsc->u.branch.link = link; | |
cca44b1b | 6103 | |
7ff120b4 | 6104 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
6105 | |
6106 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 6107 | } |
cca44b1b | 6108 | |
7ff120b4 YQ |
6109 | static int |
6110 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 6111 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6112 | { |
6113 | unsigned int cond = bits (insn, 28, 31); | |
6114 | /* BX: x12xxx1x | |
6115 | BLX: x12xxx3x. */ | |
6116 | int link = bit (insn, 5); | |
6117 | unsigned int rm = bits (insn, 0, 3); | |
6118 | ||
136821d9 | 6119 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
6120 | |
6121 | dsc->modinsn[0] = ARM_NOP; | |
6122 | ||
6123 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
6124 | return 0; |
6125 | } | |
6126 | ||
34518530 YQ |
6127 | static int |
6128 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6129 | struct regcache *regs, | |
1152d984 | 6130 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6131 | { |
6132 | int link = bit (insn, 7); | |
6133 | unsigned int rm = bits (insn, 3, 6); | |
6134 | ||
136821d9 | 6135 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
6136 | |
6137 | dsc->modinsn[0] = THUMB_NOP; | |
6138 | ||
6139 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
6140 | ||
6141 | return 0; | |
6142 | } | |
6143 | ||
6144 | ||
0963b4bd | 6145 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
6146 | |
6147 | static void | |
6e39997a | 6148 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 6149 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6150 | { |
36073a92 | 6151 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6152 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
6153 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6154 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6155 | } | |
6156 | ||
6157 | static int | |
7ff120b4 | 6158 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 6159 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6160 | { |
6161 | unsigned int rn = bits (insn, 16, 19); | |
6162 | unsigned int rd = bits (insn, 12, 15); | |
6163 | unsigned int op = bits (insn, 21, 24); | |
6164 | int is_mov = (op == 0xd); | |
6165 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
6166 | |
6167 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 6168 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 6169 | |
136821d9 SM |
6170 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
6171 | is_mov ? "move" : "ALU", | |
6172 | (unsigned long) insn); | |
cca44b1b JB |
6173 | |
6174 | /* Instruction is of form: | |
6175 | ||
6176 | <op><cond> rd, [rn,] #imm | |
6177 | ||
6178 | Rewrite as: | |
6179 | ||
6180 | Preparation: tmp1, tmp2 <- r0, r1; | |
6181 | r0, r1 <- rd, rn | |
6182 | Insn: <op><cond> r0, r1, #imm | |
6183 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6184 | */ | |
6185 | ||
36073a92 YQ |
6186 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6187 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6188 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6189 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
6190 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6191 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6192 | dsc->rd = rd; | |
6193 | ||
6194 | if (is_mov) | |
6195 | dsc->modinsn[0] = insn & 0xfff00fff; | |
6196 | else | |
6197 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
6198 | ||
6199 | dsc->cleanup = &cleanup_alu_imm; | |
6200 | ||
6201 | return 0; | |
6202 | } | |
6203 | ||
34518530 YQ |
6204 | static int |
6205 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6206 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6207 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6208 | { |
6209 | unsigned int op = bits (insn1, 5, 8); | |
6210 | unsigned int rn, rm, rd; | |
6211 | ULONGEST rd_val, rn_val; | |
6212 | ||
6213 | rn = bits (insn1, 0, 3); /* Rn */ | |
6214 | rm = bits (insn2, 0, 3); /* Rm */ | |
6215 | rd = bits (insn2, 8, 11); /* Rd */ | |
6216 | ||
6217 | /* This routine is only called for instruction MOV. */ | |
6218 | gdb_assert (op == 0x2 && rn == 0xf); | |
6219 | ||
6220 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
6221 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
6222 | ||
136821d9 | 6223 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
6224 | |
6225 | /* Instruction is of form: | |
6226 | ||
6227 | <op><cond> rd, [rn,] #imm | |
6228 | ||
6229 | Rewrite as: | |
6230 | ||
6231 | Preparation: tmp1, tmp2 <- r0, r1; | |
6232 | r0, r1 <- rd, rn | |
6233 | Insn: <op><cond> r0, r1, #imm | |
6234 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
6235 | */ | |
6236 | ||
6237 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6238 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6239 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6240 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6241 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
6242 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6243 | dsc->rd = rd; | |
6244 | ||
6245 | dsc->modinsn[0] = insn1; | |
6246 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
6247 | dsc->numinsns = 2; | |
6248 | ||
6249 | dsc->cleanup = &cleanup_alu_imm; | |
6250 | ||
6251 | return 0; | |
6252 | } | |
6253 | ||
cca44b1b JB |
6254 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
6255 | ||
6256 | static void | |
6e39997a | 6257 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 6258 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6259 | { |
6260 | ULONGEST rd_val; | |
6261 | int i; | |
6262 | ||
36073a92 | 6263 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6264 | |
6265 | for (i = 0; i < 3; i++) | |
6266 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6267 | ||
6268 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6269 | } | |
6270 | ||
7ff120b4 YQ |
6271 | static void |
6272 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6273 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 6274 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 6275 | { |
cca44b1b | 6276 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 6277 | |
cca44b1b JB |
6278 | /* Instruction is of form: |
6279 | ||
6280 | <op><cond> rd, [rn,] rm [, <shift>] | |
6281 | ||
6282 | Rewrite as: | |
6283 | ||
6284 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
6285 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 6286 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
6287 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
6288 | */ | |
6289 | ||
36073a92 YQ |
6290 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6291 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6292 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6293 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6294 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6295 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
6296 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6297 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6298 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6299 | dsc->rd = rd; | |
6300 | ||
7ff120b4 YQ |
6301 | dsc->cleanup = &cleanup_alu_reg; |
6302 | } | |
6303 | ||
6304 | static int | |
6305 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 6306 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6307 | { |
6308 | unsigned int op = bits (insn, 21, 24); | |
6309 | int is_mov = (op == 0xd); | |
6310 | ||
6311 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6312 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
6313 | ||
136821d9 SM |
6314 | displaced_debug_printf ("copying reg %s insn %.8lx", |
6315 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 6316 | |
cca44b1b JB |
6317 | if (is_mov) |
6318 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
6319 | else | |
6320 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
6321 | ||
7ff120b4 YQ |
6322 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
6323 | bits (insn, 0, 3)); | |
cca44b1b JB |
6324 | return 0; |
6325 | } | |
6326 | ||
34518530 YQ |
6327 | static int |
6328 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6329 | struct regcache *regs, | |
1152d984 | 6330 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 6331 | { |
ef713951 | 6332 | unsigned rm, rd; |
34518530 | 6333 | |
ef713951 YQ |
6334 | rm = bits (insn, 3, 6); |
6335 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 6336 | |
ef713951 | 6337 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
6338 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
6339 | ||
136821d9 | 6340 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 6341 | |
ef713951 | 6342 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 6343 | |
ef713951 | 6344 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
6345 | |
6346 | return 0; | |
6347 | } | |
6348 | ||
cca44b1b JB |
6349 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
6350 | ||
6351 | static void | |
6e39997a | 6352 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 6353 | struct regcache *regs, |
1152d984 | 6354 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6355 | { |
36073a92 | 6356 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6357 | int i; |
6358 | ||
6359 | for (i = 0; i < 4; i++) | |
6360 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6361 | ||
6362 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6363 | } | |
6364 | ||
7ff120b4 YQ |
6365 | static void |
6366 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6367 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
6368 | unsigned int rd, unsigned int rn, unsigned int rm, |
6369 | unsigned rs) | |
cca44b1b | 6370 | { |
7ff120b4 | 6371 | int i; |
cca44b1b | 6372 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 6373 | |
cca44b1b JB |
6374 | /* Instruction is of form: |
6375 | ||
6376 | <op><cond> rd, [rn,] rm, <shift> rs | |
6377 | ||
6378 | Rewrite as: | |
6379 | ||
6380 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
6381 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
6382 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
6383 | Cleanup: tmp5 <- r0 | |
6384 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
6385 | rd <- tmp5 | |
6386 | */ | |
6387 | ||
6388 | for (i = 0; i < 4; i++) | |
36073a92 | 6389 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 6390 | |
36073a92 YQ |
6391 | rd_val = displaced_read_reg (regs, dsc, rd); |
6392 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6393 | rm_val = displaced_read_reg (regs, dsc, rm); | |
6394 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
6395 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6396 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6397 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6398 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
6399 | dsc->rd = rd; | |
7ff120b4 YQ |
6400 | dsc->cleanup = &cleanup_alu_shifted_reg; |
6401 | } | |
6402 | ||
6403 | static int | |
6404 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
6405 | struct regcache *regs, | |
1152d984 | 6406 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6407 | { |
6408 | unsigned int op = bits (insn, 21, 24); | |
6409 | int is_mov = (op == 0xd); | |
6410 | unsigned int rd, rn, rm, rs; | |
6411 | ||
6412 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
6413 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
6414 | ||
136821d9 SM |
6415 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
6416 | is_mov ? "move" : "ALU", | |
6417 | (unsigned long) insn); | |
7ff120b4 YQ |
6418 | |
6419 | rn = bits (insn, 16, 19); | |
6420 | rm = bits (insn, 0, 3); | |
6421 | rs = bits (insn, 8, 11); | |
6422 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
6423 | |
6424 | if (is_mov) | |
6425 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
6426 | else | |
6427 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
6428 | ||
7ff120b4 | 6429 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
6430 | |
6431 | return 0; | |
6432 | } | |
6433 | ||
6434 | /* Clean up load instructions. */ | |
6435 | ||
6436 | static void | |
6e39997a | 6437 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6438 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6439 | { |
6440 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 6441 | |
36073a92 | 6442 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 6443 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
6444 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
6445 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
6446 | |
6447 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6448 | if (dsc->u.ldst.xfersize > 4) | |
6449 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6450 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6451 | if (!dsc->u.ldst.immed) | |
6452 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6453 | ||
6454 | /* Handle register writeback. */ | |
6455 | if (dsc->u.ldst.writeback) | |
6456 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6457 | /* Put result in right place. */ | |
6458 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
6459 | if (dsc->u.ldst.xfersize == 8) | |
6460 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
6461 | } | |
6462 | ||
6463 | /* Clean up store instructions. */ | |
6464 | ||
6465 | static void | |
6e39997a | 6466 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6467 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6468 | { |
36073a92 | 6469 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
6470 | |
6471 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6472 | if (dsc->u.ldst.xfersize > 4) | |
6473 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6474 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6475 | if (!dsc->u.ldst.immed) | |
6476 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6477 | if (!dsc->u.ldst.restore_r4) | |
6478 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
6479 | ||
6480 | /* Writeback. */ | |
6481 | if (dsc->u.ldst.writeback) | |
6482 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6483 | } | |
6484 | ||
6485 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
6486 | transfers, which have a different encoding to byte/word transfers. */ | |
6487 | ||
6488 | static int | |
550dc4e2 | 6489 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 6490 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6491 | { |
6492 | unsigned int op1 = bits (insn, 20, 24); | |
6493 | unsigned int op2 = bits (insn, 5, 6); | |
6494 | unsigned int rt = bits (insn, 12, 15); | |
6495 | unsigned int rn = bits (insn, 16, 19); | |
6496 | unsigned int rm = bits (insn, 0, 3); | |
6497 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
6498 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
6499 | int immed = (op1 & 0x4) != 0; | |
6500 | int opcode; | |
6501 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
6502 | |
6503 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 6504 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 6505 | |
136821d9 SM |
6506 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
6507 | unprivileged ? "unprivileged " : "", | |
6508 | (unsigned long) insn); | |
cca44b1b JB |
6509 | |
6510 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
6511 | ||
6512 | if (opcode < 0) | |
f34652de | 6513 | internal_error (_("copy_extra_ld_st: instruction decode error")); |
cca44b1b | 6514 | |
36073a92 YQ |
6515 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6516 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6517 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6518 | if (!immed) |
36073a92 | 6519 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6520 | |
36073a92 | 6521 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 6522 | if (bytesize[opcode] == 8) |
36073a92 YQ |
6523 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
6524 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6525 | if (!immed) |
36073a92 | 6526 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6527 | |
6528 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6529 | if (bytesize[opcode] == 8) | |
6530 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
6531 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6532 | if (!immed) | |
6533 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
6534 | ||
6535 | dsc->rd = rt; | |
6536 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
6537 | dsc->u.ldst.rn = rn; | |
6538 | dsc->u.ldst.immed = immed; | |
6539 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
6540 | dsc->u.ldst.restore_r4 = 0; | |
6541 | ||
6542 | if (immed) | |
6543 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
6544 | -> | |
6545 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
6546 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6547 | else | |
6548 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
6549 | -> | |
6550 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
6551 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6552 | ||
6553 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
6554 | ||
6555 | return 0; | |
6556 | } | |
6557 | ||
0f6f04ba | 6558 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 6559 | |
7ff120b4 | 6560 | static void |
0f6f04ba | 6561 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6562 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
6563 | int immed, int writeback, int size, int usermode, |
6564 | int rt, int rm, int rn) | |
cca44b1b | 6565 | { |
cca44b1b | 6566 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 6567 | |
36073a92 YQ |
6568 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6569 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6570 | if (!immed) |
36073a92 | 6571 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6572 | if (!load) |
36073a92 | 6573 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 6574 | |
36073a92 YQ |
6575 | rt_val = displaced_read_reg (regs, dsc, rt); |
6576 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6577 | if (!immed) |
36073a92 | 6578 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6579 | |
6580 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6581 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6582 | if (!immed) | |
6583 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 6584 | dsc->rd = rt; |
0f6f04ba | 6585 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
6586 | dsc->u.ldst.rn = rn; |
6587 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 6588 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
6589 | |
6590 | /* To write PC we can do: | |
6591 | ||
494e194e YQ |
6592 | Before this sequence of instructions: |
6593 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 6594 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
6595 | |
6596 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
6597 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
6598 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
6599 | = addr(Insn1) + offset - addr(Insn3) - 8 |
6600 | = offset - 16 | |
494e194e YQ |
6601 | Insn4: add r4, r4, #8 r4 = offset - 8 |
6602 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 6603 | = from + offset |
494e194e | 6604 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
6605 | |
6606 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
6607 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
6608 | of this can be found in Section "Saving from r15" in | |
6609 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 6610 | |
7ff120b4 YQ |
6611 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
6612 | } | |
6613 | ||
34518530 YQ |
6614 | |
6615 | static int | |
6616 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
6617 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6618 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
6619 | { |
6620 | unsigned int u_bit = bit (insn1, 7); | |
6621 | unsigned int rt = bits (insn2, 12, 15); | |
6622 | int imm12 = bits (insn2, 0, 11); | |
6623 | ULONGEST pc_val; | |
6624 | ||
136821d9 SM |
6625 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
6626 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
6627 | imm12); | |
34518530 YQ |
6628 | |
6629 | if (!u_bit) | |
6630 | imm12 = -1 * imm12; | |
6631 | ||
6632 | /* Rewrite instruction LDR Rt imm12 into: | |
6633 | ||
6634 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
6635 | ||
6636 | LDR R0, R2, R3, | |
6637 | ||
6638 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
6639 | ||
6640 | ||
6641 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6642 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6643 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
6644 | ||
6645 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6646 | ||
6647 | pc_val = pc_val & 0xfffffffc; | |
6648 | ||
6649 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
6650 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
6651 | ||
6652 | dsc->rd = rt; | |
6653 | ||
6654 | dsc->u.ldst.xfersize = size; | |
6655 | dsc->u.ldst.immed = 0; | |
6656 | dsc->u.ldst.writeback = 0; | |
6657 | dsc->u.ldst.restore_r4 = 0; | |
6658 | ||
6659 | /* LDR R0, R2, R3 */ | |
6660 | dsc->modinsn[0] = 0xf852; | |
6661 | dsc->modinsn[1] = 0x3; | |
6662 | dsc->numinsns = 2; | |
6663 | ||
6664 | dsc->cleanup = &cleanup_load; | |
6665 | ||
6666 | return 0; | |
6667 | } | |
6668 | ||
6669 | static int | |
6670 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6671 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6672 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
6673 | int writeback, int immed) |
6674 | { | |
6675 | unsigned int rt = bits (insn2, 12, 15); | |
6676 | unsigned int rn = bits (insn1, 0, 3); | |
6677 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
6678 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
6679 | be PC, so we don't have to check it. */ | |
6680 | ||
6681 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
6682 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
6683 | dsc); | |
6684 | ||
136821d9 SM |
6685 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
6686 | rt, rn, insn1, insn2); | |
34518530 YQ |
6687 | |
6688 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
6689 | 0, rt, rm, rn); | |
6690 | ||
6691 | dsc->u.ldst.restore_r4 = 0; | |
6692 | ||
6693 | if (immed) | |
6694 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
6695 | -> | |
6696 | ldr[b]<cond> r0, [r2, #imm]. */ | |
6697 | { | |
6698 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6699 | dsc->modinsn[1] = insn2 & 0x0fff; | |
6700 | } | |
6701 | else | |
6702 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
6703 | -> | |
6704 | ldr[b]<cond> r0, [r2, r3]. */ | |
6705 | { | |
6706 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6707 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
6708 | } | |
6709 | ||
6710 | dsc->numinsns = 2; | |
6711 | ||
6712 | return 0; | |
6713 | } | |
6714 | ||
6715 | ||
7ff120b4 YQ |
6716 | static int |
6717 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
6718 | struct regcache *regs, | |
1152d984 | 6719 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 6720 | int load, int size, int usermode) |
7ff120b4 YQ |
6721 | { |
6722 | int immed = !bit (insn, 25); | |
6723 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
6724 | unsigned int rt = bits (insn, 12, 15); | |
6725 | unsigned int rn = bits (insn, 16, 19); | |
6726 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
6727 | ||
6728 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6729 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
6730 | ||
136821d9 SM |
6731 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
6732 | load ? (size == 1 ? "ldrb" : "ldr") | |
6733 | : (size == 1 ? "strb" : "str"), | |
6734 | usermode ? "t" : "", | |
6735 | rt, rn, | |
6736 | (unsigned long) insn); | |
7ff120b4 | 6737 | |
0f6f04ba YQ |
6738 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
6739 | usermode, rt, rm, rn); | |
7ff120b4 | 6740 | |
bf9f652a | 6741 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
6742 | { |
6743 | dsc->u.ldst.restore_r4 = 0; | |
6744 | ||
6745 | if (immed) | |
6746 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
6747 | -> | |
6748 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
6749 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6750 | else | |
6751 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
6752 | -> | |
6753 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
6754 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6755 | } | |
6756 | else | |
6757 | { | |
6758 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
6759 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
6760 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
6761 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
6762 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
6763 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
6764 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
6765 | ||
6766 | /* As above. */ | |
6767 | if (immed) | |
6768 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
6769 | else | |
6770 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
6771 | ||
cca44b1b JB |
6772 | dsc->numinsns = 6; |
6773 | } | |
6774 | ||
6775 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
6776 | ||
6777 | return 0; | |
6778 | } | |
6779 | ||
6780 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
6781 | unfortunate corner case: it's impossible to implement correctly by modifying | |
6782 | the instruction. The issue is as follows: we have an instruction, | |
6783 | ||
6784 | ldm rN, {r0-r15} | |
6785 | ||
6786 | which we must rewrite to avoid loading PC. A possible solution would be to | |
6787 | do the load in two halves, something like (with suitable cleanup | |
6788 | afterwards): | |
6789 | ||
6790 | mov r8, rN | |
6791 | ldm[id][ab] r8!, {r0-r7} | |
6792 | str r7, <temp> | |
6793 | ldm[id][ab] r8, {r7-r14} | |
6794 | <bkpt> | |
6795 | ||
6796 | but at present there's no suitable place for <temp>, since the scratch space | |
6797 | is overwritten before the cleanup routine is called. For now, we simply | |
6798 | emulate the instruction. */ | |
6799 | ||
6800 | static void | |
6801 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6802 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6803 | { |
cca44b1b JB |
6804 | int inc = dsc->u.block.increment; |
6805 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
6806 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
6807 | uint32_t regmask = dsc->u.block.regmask; | |
6808 | int regno = inc ? 0 : 15; | |
6809 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
6810 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
6811 | && (regmask & 0x8000) != 0; | |
36073a92 | 6812 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6813 | int do_transfer = condition_true (dsc->u.block.cond, status); |
6814 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6815 | ||
6816 | if (!do_transfer) | |
6817 | return; | |
6818 | ||
6819 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
6820 | sensible we can do here. Complain loudly. */ | |
6821 | if (exception_return) | |
6822 | error (_("Cannot single-step exception return")); | |
6823 | ||
6824 | /* We don't handle any stores here for now. */ | |
6825 | gdb_assert (dsc->u.block.load != 0); | |
6826 | ||
136821d9 SM |
6827 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
6828 | dsc->u.block.load ? "ldm" : "stm", | |
6829 | dsc->u.block.increment ? "inc" : "dec", | |
6830 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
6831 | |
6832 | while (regmask) | |
6833 | { | |
6834 | uint32_t memword; | |
6835 | ||
6836 | if (inc) | |
bf9f652a | 6837 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
6838 | regno++; |
6839 | else | |
6840 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
6841 | regno--; | |
6842 | ||
6843 | xfer_addr += bump_before; | |
6844 | ||
6845 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
6846 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
6847 | ||
6848 | xfer_addr += bump_after; | |
6849 | ||
6850 | regmask &= ~(1 << regno); | |
6851 | } | |
6852 | ||
6853 | if (dsc->u.block.writeback) | |
6854 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
6855 | CANNOT_WRITE_PC); | |
6856 | } | |
6857 | ||
6858 | /* Clean up an STM which included the PC in the register list. */ | |
6859 | ||
6860 | static void | |
6861 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6862 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6863 | { |
36073a92 | 6864 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 6865 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
6866 | CORE_ADDR pc_stored_at, transferred_regs |
6867 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
6868 | CORE_ADDR stm_insn_addr; |
6869 | uint32_t pc_val; | |
6870 | long offset; | |
6871 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6872 | ||
6873 | /* If condition code fails, there's nothing else to do. */ | |
6874 | if (!store_executed) | |
6875 | return; | |
6876 | ||
6877 | if (dsc->u.block.increment) | |
6878 | { | |
6879 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
6880 | ||
6881 | if (dsc->u.block.before) | |
6882 | pc_stored_at += 4; | |
6883 | } | |
6884 | else | |
6885 | { | |
6886 | pc_stored_at = dsc->u.block.xfer_addr; | |
6887 | ||
6888 | if (dsc->u.block.before) | |
6889 | pc_stored_at -= 4; | |
6890 | } | |
6891 | ||
6892 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
6893 | stm_insn_addr = dsc->scratch_base; | |
6894 | offset = pc_val - stm_insn_addr; | |
6895 | ||
136821d9 SM |
6896 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
6897 | offset); | |
cca44b1b JB |
6898 | |
6899 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
6900 | instruction. */ | |
6901 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
6902 | dsc->insn_addr + offset); | |
6903 | } | |
6904 | ||
6905 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
6906 | the registers in the transferred list into a contiguous range r0...rX (to | |
6907 | avoid loading PC directly and losing control of the debugged program), so we | |
6908 | must undo that here. */ | |
6909 | ||
6910 | static void | |
6e39997a | 6911 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 6912 | struct regcache *regs, |
1152d984 | 6913 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6914 | { |
36073a92 | 6915 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 6916 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 6917 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 6918 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
6919 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
6920 | ||
6921 | /* The method employed here will fail if the register list is fully populated | |
6922 | (we need to avoid loading PC directly). */ | |
6923 | gdb_assert (num_to_shuffle < 16); | |
6924 | ||
6925 | if (!load_executed) | |
6926 | return; | |
6927 | ||
6928 | clobbered = (1 << num_to_shuffle) - 1; | |
6929 | ||
6930 | while (num_to_shuffle > 0) | |
6931 | { | |
6932 | if ((mask & (1 << write_reg)) != 0) | |
6933 | { | |
6934 | unsigned int read_reg = num_to_shuffle - 1; | |
6935 | ||
6936 | if (read_reg != write_reg) | |
6937 | { | |
36073a92 | 6938 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 6939 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
6940 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
6941 | read_reg, write_reg); | |
cca44b1b | 6942 | } |
136821d9 SM |
6943 | else |
6944 | displaced_debug_printf ("LDM: register r%d already in the right " | |
6945 | "place", write_reg); | |
cca44b1b JB |
6946 | |
6947 | clobbered &= ~(1 << write_reg); | |
6948 | ||
6949 | num_to_shuffle--; | |
6950 | } | |
6951 | ||
6952 | write_reg--; | |
6953 | } | |
6954 | ||
6955 | /* Restore any registers we scribbled over. */ | |
6956 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6957 | { | |
6958 | if ((clobbered & (1 << write_reg)) != 0) | |
6959 | { | |
6960 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6961 | CANNOT_WRITE_PC); | |
136821d9 SM |
6962 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6963 | write_reg); | |
cca44b1b JB |
6964 | clobbered &= ~(1 << write_reg); |
6965 | } | |
6966 | } | |
6967 | ||
6968 | /* Perform register writeback manually. */ | |
6969 | if (dsc->u.block.writeback) | |
6970 | { | |
6971 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6972 | ||
6973 | if (dsc->u.block.increment) | |
6974 | new_rn_val += regs_loaded * 4; | |
6975 | else | |
6976 | new_rn_val -= regs_loaded * 4; | |
6977 | ||
6978 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6979 | CANNOT_WRITE_PC); | |
6980 | } | |
6981 | } | |
6982 | ||
6983 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6984 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6985 | ||
6986 | static int | |
7ff120b4 YQ |
6987 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6988 | struct regcache *regs, | |
1152d984 | 6989 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6990 | { |
6991 | int load = bit (insn, 20); | |
6992 | int user = bit (insn, 22); | |
6993 | int increment = bit (insn, 23); | |
6994 | int before = bit (insn, 24); | |
6995 | int writeback = bit (insn, 21); | |
6996 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6997 | |
0963b4bd MS |
6998 | /* Block transfers which don't mention PC can be run directly |
6999 | out-of-line. */ | |
bf9f652a | 7000 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 7001 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 7002 | |
bf9f652a | 7003 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 7004 | { |
0963b4bd MS |
7005 | warning (_("displaced: Unpredictable LDM or STM with " |
7006 | "base register r15")); | |
7ff120b4 | 7007 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
7008 | } |
7009 | ||
136821d9 SM |
7010 | displaced_debug_printf ("copying block transfer insn %.8lx", |
7011 | (unsigned long) insn); | |
cca44b1b | 7012 | |
36073a92 | 7013 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
7014 | dsc->u.block.rn = rn; |
7015 | ||
7016 | dsc->u.block.load = load; | |
7017 | dsc->u.block.user = user; | |
7018 | dsc->u.block.increment = increment; | |
7019 | dsc->u.block.before = before; | |
7020 | dsc->u.block.writeback = writeback; | |
7021 | dsc->u.block.cond = bits (insn, 28, 31); | |
7022 | ||
7023 | dsc->u.block.regmask = insn & 0xffff; | |
7024 | ||
7025 | if (load) | |
7026 | { | |
7027 | if ((insn & 0xffff) == 0xffff) | |
7028 | { | |
7029 | /* LDM with a fully-populated register list. This case is | |
7030 | particularly tricky. Implement for now by fully emulating the | |
7031 | instruction (which might not behave perfectly in all cases, but | |
7032 | these instructions should be rare enough for that not to matter | |
7033 | too much). */ | |
7034 | dsc->modinsn[0] = ARM_NOP; | |
7035 | ||
7036 | dsc->cleanup = &cleanup_block_load_all; | |
7037 | } | |
7038 | else | |
7039 | { | |
7040 | /* LDM of a list of registers which includes PC. Implement by | |
7041 | rewriting the list of registers to be transferred into a | |
7042 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
7043 | registers into the correct places in the cleanup routine. */ | |
7044 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 7045 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 7046 | unsigned int i; |
cca44b1b JB |
7047 | |
7048 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 7049 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
7050 | |
7051 | /* Writeback makes things complicated. We need to avoid clobbering | |
7052 | the base register with one of the registers in our modified | |
7053 | register list, but just using a different register can't work in | |
7054 | all cases, e.g.: | |
7055 | ||
7056 | ldm r14!, {r0-r13,pc} | |
7057 | ||
7058 | which would need to be rewritten as: | |
7059 | ||
7060 | ldm rN!, {r0-r14} | |
7061 | ||
7062 | but that can't work, because there's no free register for N. | |
7063 | ||
7064 | Solve this by turning off the writeback bit, and emulating | |
7065 | writeback manually in the cleanup routine. */ | |
7066 | ||
7067 | if (writeback) | |
7068 | insn &= ~(1 << 21); | |
7069 | ||
7070 | new_regmask = (1 << num_in_list) - 1; | |
7071 | ||
136821d9 SM |
7072 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
7073 | "%.4x, modified list %.4x", | |
7074 | rn, writeback ? "!" : "", | |
7075 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
7076 | |
7077 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
7078 | ||
7079 | dsc->cleanup = &cleanup_block_load_pc; | |
7080 | } | |
7081 | } | |
7082 | else | |
7083 | { | |
7084 | /* STM of a list of registers which includes PC. Run the instruction | |
7085 | as-is, but out of line: this will store the wrong value for the PC, | |
7086 | so we must manually fix up the memory in the cleanup routine. | |
7087 | Doing things this way has the advantage that we can auto-detect | |
7088 | the offset of the PC write (which is architecture-dependent) in | |
7089 | the cleanup routine. */ | |
7090 | dsc->modinsn[0] = insn; | |
7091 | ||
7092 | dsc->cleanup = &cleanup_block_store_pc; | |
7093 | } | |
7094 | ||
7095 | return 0; | |
7096 | } | |
7097 | ||
34518530 YQ |
7098 | static int |
7099 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
7100 | struct regcache *regs, | |
1152d984 | 7101 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7102 | { |
34518530 YQ |
7103 | int rn = bits (insn1, 0, 3); |
7104 | int load = bit (insn1, 4); | |
7105 | int writeback = bit (insn1, 5); | |
cca44b1b | 7106 | |
34518530 YQ |
7107 | /* Block transfers which don't mention PC can be run directly |
7108 | out-of-line. */ | |
7109 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
7110 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 7111 | |
34518530 YQ |
7112 | if (rn == ARM_PC_REGNUM) |
7113 | { | |
7114 | warning (_("displaced: Unpredictable LDM or STM with " | |
7115 | "base register r15")); | |
7116 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7117 | "unpredictable ldm/stm", dsc); | |
7118 | } | |
cca44b1b | 7119 | |
136821d9 SM |
7120 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
7121 | insn1, insn2); | |
cca44b1b | 7122 | |
34518530 YQ |
7123 | /* Clear bit 13, since it should be always zero. */ |
7124 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
7125 | dsc->u.block.rn = rn; | |
cca44b1b | 7126 | |
34518530 YQ |
7127 | dsc->u.block.load = load; |
7128 | dsc->u.block.user = 0; | |
7129 | dsc->u.block.increment = bit (insn1, 7); | |
7130 | dsc->u.block.before = bit (insn1, 8); | |
7131 | dsc->u.block.writeback = writeback; | |
7132 | dsc->u.block.cond = INST_AL; | |
7133 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 7134 | |
34518530 YQ |
7135 | if (load) |
7136 | { | |
7137 | if (dsc->u.block.regmask == 0xffff) | |
7138 | { | |
7139 | /* This branch is impossible to happen. */ | |
7140 | gdb_assert (0); | |
7141 | } | |
7142 | else | |
7143 | { | |
7144 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 7145 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 7146 | unsigned int i; |
34518530 YQ |
7147 | |
7148 | for (i = 0; i < num_in_list; i++) | |
7149 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7150 | ||
7151 | if (writeback) | |
7152 | insn1 &= ~(1 << 5); | |
7153 | ||
7154 | new_regmask = (1 << num_in_list) - 1; | |
7155 | ||
136821d9 SM |
7156 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
7157 | "%.4x, modified list %.4x", | |
7158 | rn, writeback ? "!" : "", | |
7159 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7160 | |
7161 | dsc->modinsn[0] = insn1; | |
7162 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
7163 | dsc->numinsns = 2; | |
7164 | ||
7165 | dsc->cleanup = &cleanup_block_load_pc; | |
7166 | } | |
7167 | } | |
7168 | else | |
7169 | { | |
7170 | dsc->modinsn[0] = insn1; | |
7171 | dsc->modinsn[1] = insn2; | |
7172 | dsc->numinsns = 2; | |
7173 | dsc->cleanup = &cleanup_block_store_pc; | |
7174 | } | |
7175 | return 0; | |
7176 | } | |
7177 | ||
d9311bfa AT |
7178 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
7179 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
7180 | ||
7181 | ULONGEST | |
7182 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
7183 | int byte_order) | |
7184 | { | |
5f2dfcfd AT |
7185 | return read_memory_unsigned_integer (memaddr, len, |
7186 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
7187 | } |
7188 | ||
7189 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
7190 | ||
7191 | CORE_ADDR | |
7192 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
7193 | CORE_ADDR val) | |
7194 | { | |
ac7936df | 7195 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
7196 | } |
7197 | ||
7198 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
7199 | ||
e7cf25a8 | 7200 | static CORE_ADDR |
553cb527 | 7201 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 7202 | { |
d9311bfa AT |
7203 | return 0; |
7204 | } | |
7205 | ||
7206 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
7207 | ||
7208 | int | |
7209 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
7210 | { | |
7211 | return arm_is_thumb (self->regcache); | |
7212 | } | |
7213 | ||
7214 | /* single_step() is called just before we want to resume the inferior, | |
7215 | if we want to single-step it but there is no hardware or kernel | |
7216 | single-step support. We find the target of the coming instructions | |
7217 | and breakpoint them. */ | |
7218 | ||
a0ff9e1a | 7219 | std::vector<CORE_ADDR> |
f5ea389a | 7220 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 7221 | { |
ac7936df | 7222 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 7223 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
7224 | |
7225 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
7226 | &arm_get_next_pcs_ops, | |
7227 | gdbarch_byte_order (gdbarch), | |
7228 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 7229 | 0, |
d9311bfa AT |
7230 | regcache); |
7231 | ||
a0ff9e1a | 7232 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 7233 | |
a0ff9e1a SM |
7234 | for (CORE_ADDR &pc_ref : next_pcs) |
7235 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 7236 | |
93f9a11f | 7237 | return next_pcs; |
d9311bfa AT |
7238 | } |
7239 | ||
34518530 YQ |
7240 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
7241 | for Linux, where some SVC instructions must be treated specially. */ | |
7242 | ||
7243 | static void | |
7244 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7245 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7246 | { |
7247 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
7248 | ||
136821d9 SM |
7249 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
7250 | (unsigned long) resume_addr); | |
34518530 YQ |
7251 | |
7252 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
7253 | } | |
7254 | ||
7255 | ||
85102364 | 7256 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
7257 | |
7258 | static int | |
7259 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7260 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7261 | { |
7262 | /* Preparation: none. | |
7263 | Insn: unmodified svc. | |
7264 | Cleanup: pc <- insn_addr + insn_size. */ | |
7265 | ||
7266 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
7267 | instruction. */ | |
7268 | dsc->wrote_to_pc = 1; | |
7269 | ||
7270 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
7271 | if (dsc->u.svc.copy_svc_os) |
7272 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
7273 | else | |
7274 | { | |
7275 | dsc->cleanup = &cleanup_svc; | |
7276 | return 0; | |
7277 | } | |
34518530 YQ |
7278 | } |
7279 | ||
7280 | static int | |
7281 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 7282 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7283 | { |
7284 | ||
136821d9 SM |
7285 | displaced_debug_printf ("copying svc insn %.8lx", |
7286 | (unsigned long) insn); | |
34518530 YQ |
7287 | |
7288 | dsc->modinsn[0] = insn; | |
7289 | ||
7290 | return install_svc (gdbarch, regs, dsc); | |
7291 | } | |
7292 | ||
7293 | static int | |
7294 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 7295 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7296 | { |
7297 | ||
136821d9 | 7298 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 7299 | |
34518530 YQ |
7300 | dsc->modinsn[0] = insn; |
7301 | ||
7302 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
7303 | } |
7304 | ||
7305 | /* Copy undefined instructions. */ | |
7306 | ||
7307 | static int | |
7ff120b4 | 7308 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7309 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7310 | { |
136821d9 SM |
7311 | displaced_debug_printf ("copying undefined insn %.8lx", |
7312 | (unsigned long) insn); | |
cca44b1b JB |
7313 | |
7314 | dsc->modinsn[0] = insn; | |
7315 | ||
7316 | return 0; | |
7317 | } | |
7318 | ||
34518530 YQ |
7319 | static int |
7320 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 7321 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7322 | { |
7323 | ||
136821d9 SM |
7324 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
7325 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
7326 | |
7327 | dsc->modinsn[0] = insn1; | |
7328 | dsc->modinsn[1] = insn2; | |
7329 | dsc->numinsns = 2; | |
7330 | ||
7331 | return 0; | |
7332 | } | |
7333 | ||
cca44b1b JB |
7334 | /* Copy unpredictable instructions. */ |
7335 | ||
7336 | static int | |
7ff120b4 | 7337 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7338 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7339 | { |
136821d9 SM |
7340 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
7341 | (unsigned long) insn); | |
cca44b1b JB |
7342 | |
7343 | dsc->modinsn[0] = insn; | |
7344 | ||
7345 | return 0; | |
7346 | } | |
7347 | ||
7348 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
7349 | the presentation in the ARM ARM. */ | |
7350 | ||
7351 | static int | |
7ff120b4 YQ |
7352 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
7353 | struct regcache *regs, | |
1152d984 | 7354 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7355 | { |
7356 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
7357 | unsigned int rn = bits (insn, 16, 19); | |
7358 | ||
2f924de6 | 7359 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 7360 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 7361 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 7362 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 7363 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 7364 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 7365 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
7366 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
7367 | dsc); | |
cca44b1b | 7368 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 7369 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7370 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 7371 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
7372 | else if ((op1 & 0x77) == 0x51) |
7373 | { | |
7374 | if (rn != 0xf) | |
7ff120b4 | 7375 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 7376 | else |
7ff120b4 | 7377 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7378 | } |
7379 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 7380 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
7381 | else if (op1 == 0x57) |
7382 | switch (op2) | |
7383 | { | |
7ff120b4 YQ |
7384 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
7385 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
7386 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
7387 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
7388 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
7389 | } |
7390 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 7391 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7392 | else if ((op2 & 0x1) == 0x0) |
7393 | switch (op1 & ~0x80) | |
7394 | { | |
7395 | case 0x61: | |
7ff120b4 | 7396 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7397 | case 0x65: |
7ff120b4 | 7398 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 7399 | case 0x71: case 0x75: |
dda83cd7 | 7400 | /* pld/pldw reg. */ |
7ff120b4 | 7401 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7402 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 7403 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 7404 | default: |
7ff120b4 | 7405 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7406 | } |
7407 | else | |
7ff120b4 | 7408 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
7409 | } |
7410 | ||
7411 | static int | |
7ff120b4 YQ |
7412 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
7413 | struct regcache *regs, | |
1152d984 | 7414 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7415 | { |
7416 | if (bit (insn, 27) == 0) | |
7ff120b4 | 7417 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7418 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
7419 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
7420 | { | |
7421 | case 0x0: case 0x2: | |
7ff120b4 | 7422 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
7423 | |
7424 | case 0x1: case 0x3: | |
7ff120b4 | 7425 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
7426 | |
7427 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 7428 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7429 | |
7430 | case 0x8: | |
7431 | switch ((insn & 0xe00000) >> 21) | |
7432 | { | |
7433 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
7434 | /* stc/stc2. */ | |
7ff120b4 | 7435 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7436 | |
7437 | case 0x2: | |
7ff120b4 | 7438 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
7439 | |
7440 | default: | |
7ff120b4 | 7441 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7442 | } |
7443 | ||
7444 | case 0x9: | |
7445 | { | |
7446 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
7447 | switch ((insn & 0xe00000) >> 21) | |
7448 | { | |
7449 | case 0x1: case 0x3: | |
7450 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
7451 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
7452 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
7453 | |
7454 | case 0x2: | |
7ff120b4 | 7455 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7456 | |
7457 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7458 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
7459 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
7460 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
7461 | |
7462 | default: | |
7ff120b4 | 7463 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7464 | } |
7465 | } | |
7466 | ||
7467 | case 0xa: | |
7ff120b4 | 7468 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
7469 | |
7470 | case 0xb: | |
7471 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 7472 | /* ldc/ldc2 lit. */ |
7ff120b4 | 7473 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7474 | else |
7ff120b4 | 7475 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7476 | |
7477 | case 0xc: | |
7478 | if (bit (insn, 4)) | |
7ff120b4 | 7479 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7480 | else |
7ff120b4 | 7481 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7482 | |
7483 | case 0xd: | |
7484 | if (bit (insn, 4)) | |
7ff120b4 | 7485 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7486 | else |
7ff120b4 | 7487 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7488 | |
7489 | default: | |
7ff120b4 | 7490 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7491 | } |
7492 | } | |
7493 | ||
7494 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
7495 | ||
7496 | static int | |
7ff120b4 YQ |
7497 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
7498 | struct regcache *regs, | |
1152d984 | 7499 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7500 | { |
7501 | unsigned int op2 = bits (insn, 4, 6); | |
7502 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
7503 | |
7504 | switch (op2) | |
7505 | { | |
7506 | case 0x0: | |
7ff120b4 | 7507 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
7508 | |
7509 | case 0x1: | |
7510 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 7511 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7512 | else if (op == 0x3) |
7ff120b4 | 7513 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 7514 | else |
7ff120b4 | 7515 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7516 | |
7517 | case 0x2: | |
7518 | if (op == 0x1) | |
dda83cd7 | 7519 | /* Not really supported. */ |
7ff120b4 | 7520 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 7521 | else |
7ff120b4 | 7522 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7523 | |
7524 | case 0x3: | |
7525 | if (op == 0x1) | |
7ff120b4 | 7526 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 7527 | regs, dsc); /* blx register. */ |
cca44b1b | 7528 | else |
7ff120b4 | 7529 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7530 | |
7531 | case 0x5: | |
7ff120b4 | 7532 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
7533 | |
7534 | case 0x7: | |
7535 | if (op == 0x1) | |
7ff120b4 | 7536 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 7537 | else if (op == 0x3) |
dda83cd7 | 7538 | /* Not really supported. */ |
7ff120b4 | 7539 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 7540 | /* Fall through. */ |
cca44b1b JB |
7541 | |
7542 | default: | |
7ff120b4 | 7543 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7544 | } |
7545 | } | |
7546 | ||
7547 | static int | |
7ff120b4 YQ |
7548 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
7549 | struct regcache *regs, | |
1152d984 | 7550 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7551 | { |
7552 | if (bit (insn, 25)) | |
7553 | switch (bits (insn, 20, 24)) | |
7554 | { | |
7555 | case 0x10: | |
7ff120b4 | 7556 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
7557 | |
7558 | case 0x14: | |
7ff120b4 | 7559 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
7560 | |
7561 | case 0x12: case 0x16: | |
7ff120b4 | 7562 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
7563 | |
7564 | default: | |
7ff120b4 | 7565 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7566 | } |
7567 | else | |
7568 | { | |
7569 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
7570 | ||
7571 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 7572 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7573 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 7574 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7575 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 7576 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 7577 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 7578 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 7579 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 7580 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 7581 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 7582 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 7583 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 7584 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
7585 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
7586 | dsc); | |
cca44b1b JB |
7587 | } |
7588 | ||
7589 | /* Should be unreachable. */ | |
7590 | return 1; | |
7591 | } | |
7592 | ||
7593 | static int | |
7ff120b4 YQ |
7594 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
7595 | struct regcache *regs, | |
1152d984 | 7596 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7597 | { |
7598 | int a = bit (insn, 25), b = bit (insn, 4); | |
7599 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
7600 | |
7601 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
7602 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 7603 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
7604 | else if ((!a && (op1 & 0x17) == 0x02) |
7605 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 7606 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
7607 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
7608 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 7609 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
7610 | else if ((!a && (op1 & 0x17) == 0x03) |
7611 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 7612 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
7613 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
7614 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 7615 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
7616 | else if ((!a && (op1 & 0x17) == 0x06) |
7617 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 7618 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
7619 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
7620 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 7621 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
7622 | else if ((!a && (op1 & 0x17) == 0x07) |
7623 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 7624 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
7625 | |
7626 | /* Should be unreachable. */ | |
7627 | return 1; | |
7628 | } | |
7629 | ||
7630 | static int | |
7ff120b4 | 7631 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7632 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7633 | { |
7634 | switch (bits (insn, 20, 24)) | |
7635 | { | |
7636 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 7637 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
7638 | |
7639 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 7640 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
7641 | |
7642 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
7643 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 7644 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
7645 | "decode/pack/unpack/saturate/reverse", dsc); |
7646 | ||
7647 | case 0x18: | |
7648 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
7649 | { | |
7650 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 7651 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 7652 | else |
7ff120b4 | 7653 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
7654 | } |
7655 | else | |
7ff120b4 | 7656 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7657 | |
7658 | case 0x1a: case 0x1b: | |
7659 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7660 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 7661 | else |
7ff120b4 | 7662 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7663 | |
7664 | case 0x1c: case 0x1d: | |
7665 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
7666 | { | |
7667 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 7668 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 7669 | else |
7ff120b4 | 7670 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
7671 | } |
7672 | else | |
7ff120b4 | 7673 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7674 | |
7675 | case 0x1e: case 0x1f: | |
7676 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7677 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 7678 | else |
7ff120b4 | 7679 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7680 | } |
7681 | ||
7682 | /* Should be unreachable. */ | |
7683 | return 1; | |
7684 | } | |
7685 | ||
7686 | static int | |
615234c1 | 7687 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 7688 | struct regcache *regs, |
1152d984 | 7689 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7690 | { |
7691 | if (bit (insn, 25)) | |
7ff120b4 | 7692 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 7693 | else |
7ff120b4 | 7694 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7695 | } |
7696 | ||
7697 | static int | |
7ff120b4 YQ |
7698 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
7699 | struct regcache *regs, | |
1152d984 | 7700 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7701 | { |
7702 | unsigned int opcode = bits (insn, 20, 24); | |
7703 | ||
7704 | switch (opcode) | |
7705 | { | |
7706 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 7707 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
7708 | |
7709 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
7710 | case 0x12: case 0x16: | |
7ff120b4 | 7711 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
7712 | |
7713 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
7714 | case 0x13: case 0x17: | |
7ff120b4 | 7715 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
7716 | |
7717 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7718 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7719 | /* Note: no writeback for these instructions. Bit 25 will always be | |
7720 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 7721 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7722 | } |
7723 | ||
7724 | /* Should be unreachable. */ | |
7725 | return 1; | |
7726 | } | |
7727 | ||
34518530 YQ |
7728 | /* Decode shifted register instructions. */ |
7729 | ||
7730 | static int | |
7731 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
7732 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7733 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7734 | { |
7735 | /* PC is only allowed to be used in instruction MOV. */ | |
7736 | ||
7737 | unsigned int op = bits (insn1, 5, 8); | |
7738 | unsigned int rn = bits (insn1, 0, 3); | |
7739 | ||
7740 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
7741 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
7742 | else | |
7743 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7744 | "dp (shift reg)", dsc); | |
7745 | } | |
7746 | ||
7747 | ||
7748 | /* Decode extension register load/store. Exactly the same as | |
7749 | arm_decode_ext_reg_ld_st. */ | |
7750 | ||
7751 | static int | |
7752 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
7753 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7754 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7755 | { |
7756 | unsigned int opcode = bits (insn1, 4, 8); | |
7757 | ||
7758 | switch (opcode) | |
7759 | { | |
7760 | case 0x04: case 0x05: | |
7761 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7762 | "vfp/neon vmov", dsc); | |
7763 | ||
7764 | case 0x08: case 0x0c: /* 01x00 */ | |
7765 | case 0x0a: case 0x0e: /* 01x10 */ | |
7766 | case 0x12: case 0x16: /* 10x10 */ | |
7767 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7768 | "vfp/neon vstm/vpush", dsc); | |
7769 | ||
7770 | case 0x09: case 0x0d: /* 01x01 */ | |
7771 | case 0x0b: case 0x0f: /* 01x11 */ | |
7772 | case 0x13: case 0x17: /* 10x11 */ | |
7773 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7774 | "vfp/neon vldm/vpop", dsc); | |
7775 | ||
7776 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7777 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7778 | "vstr", dsc); | |
7779 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7780 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
7781 | } | |
7782 | ||
7783 | /* Should be unreachable. */ | |
7784 | return 1; | |
7785 | } | |
7786 | ||
cca44b1b | 7787 | static int |
12545665 | 7788 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7789 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7790 | { |
7791 | unsigned int op1 = bits (insn, 20, 25); | |
7792 | int op = bit (insn, 4); | |
7793 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
7794 | |
7795 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 7796 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7797 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
7798 | && (coproc & 0xe) != 0xa) | |
7799 | /* stc/stc2. */ | |
7ff120b4 | 7800 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7801 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
7802 | && (coproc & 0xe) != 0xa) | |
7803 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 7804 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7805 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 7806 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 7807 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 7808 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 7809 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7810 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 7811 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7812 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7813 | else if ((op1 & 0x30) == 0x20 && !op) |
7814 | { | |
7815 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 7816 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 7817 | else |
7ff120b4 | 7818 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7819 | } |
7820 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 7821 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 7822 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7823 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7824 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7825 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7826 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 7827 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 7828 | else |
7ff120b4 | 7829 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
7830 | } |
7831 | ||
34518530 YQ |
7832 | static int |
7833 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
7834 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7835 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7836 | { |
7837 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
7838 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
7839 | unsigned int bit_9 = bit (insn1, 9); | |
7840 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
7841 | |
7842 | if (bit_9 == 0) | |
7843 | { | |
7844 | if (bit_5_8 == 2) | |
7845 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7846 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
7847 | dsc); | |
7848 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
7849 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7850 | else | |
7851 | { | |
7852 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
7853 | if ((coproc & 0xe) == 0xa) | |
7854 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
7855 | dsc); | |
7856 | else /* coproc is not 101x. */ | |
7857 | { | |
7858 | if (bit_4 == 0) /* STC/STC2. */ | |
7859 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7860 | "stc/stc2", dsc); | |
405feb71 | 7861 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
7862 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
7863 | regs, dsc); | |
7864 | } | |
7865 | } | |
7866 | } | |
7867 | else | |
7868 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
7869 | ||
7870 | return 0; | |
7871 | } | |
7872 | ||
7873 | static void | |
7874 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7875 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
7876 | { |
7877 | /* ADR Rd, #imm | |
7878 | ||
7879 | Rewrite as: | |
7880 | ||
7881 | Preparation: Rd <- PC | |
7882 | Insn: ADD Rd, #imm | |
7883 | Cleanup: Null. | |
7884 | */ | |
7885 | ||
7886 | /* Rd <- PC */ | |
7887 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7888 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
7889 | } | |
7890 | ||
7891 | static int | |
7892 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7893 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
7894 | int rd, unsigned int imm) |
7895 | { | |
7896 | ||
7897 | /* Encoding T2: ADDS Rd, #imm */ | |
7898 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
7899 | ||
7900 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7901 | ||
7902 | return 0; | |
7903 | } | |
7904 | ||
7905 | static int | |
7906 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
7907 | struct regcache *regs, | |
1152d984 | 7908 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7909 | { |
7910 | unsigned int rd = bits (insn, 8, 10); | |
7911 | unsigned int imm8 = bits (insn, 0, 7); | |
7912 | ||
136821d9 SM |
7913 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
7914 | rd, imm8, insn); | |
34518530 YQ |
7915 | |
7916 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
7917 | } | |
7918 | ||
7919 | static int | |
7920 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
7921 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7922 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7923 | { |
7924 | unsigned int rd = bits (insn2, 8, 11); | |
7925 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
7926 | extract raw immediate encoding rather than computing immediate. When | |
7927 | generating ADD or SUB instruction, we can simply perform OR operation to | |
7928 | set immediate into ADD. */ | |
7929 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
7930 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
7931 | ||
136821d9 SM |
7932 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
7933 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
7934 | |
7935 | if (bit (insn1, 7)) /* Encoding T2 */ | |
7936 | { | |
7937 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
7938 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
7939 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7940 | } | |
7941 | else /* Encoding T3 */ | |
7942 | { | |
7943 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
7944 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
7945 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7946 | } | |
7947 | dsc->numinsns = 2; | |
7948 | ||
7949 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7950 | ||
7951 | return 0; | |
7952 | } | |
7953 | ||
7954 | static int | |
615234c1 | 7955 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7956 | struct regcache *regs, |
1152d984 | 7957 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7958 | { |
7959 | unsigned int rt = bits (insn1, 8, 10); | |
7960 | unsigned int pc; | |
7961 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7962 | |
7963 | /* LDR Rd, #imm8 | |
7964 | ||
7965 | Rwrite as: | |
7966 | ||
7967 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7968 | ||
7969 | Insn: LDR R0, [R2, R3]; | |
7970 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7971 | ||
136821d9 | 7972 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7973 | |
7974 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7975 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7976 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7977 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7978 | /* The assembler calculates the required value of the offset from the | |
7979 | Align(PC,4) value of this instruction to the label. */ | |
7980 | pc = pc & 0xfffffffc; | |
7981 | ||
7982 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7983 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7984 | ||
7985 | dsc->rd = rt; | |
7986 | dsc->u.ldst.xfersize = 4; | |
7987 | dsc->u.ldst.rn = 0; | |
7988 | dsc->u.ldst.immed = 0; | |
7989 | dsc->u.ldst.writeback = 0; | |
7990 | dsc->u.ldst.restore_r4 = 0; | |
7991 | ||
7992 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7993 | ||
7994 | dsc->cleanup = &cleanup_load; | |
7995 | ||
7996 | return 0; | |
7997 | } | |
7998 | ||
405feb71 | 7999 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
8000 | |
8001 | static int | |
8002 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
8003 | struct regcache *regs, | |
1152d984 | 8004 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8005 | { |
8006 | int non_zero = bit (insn1, 11); | |
8007 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
8008 | CORE_ADDR from = dsc->insn_addr; | |
8009 | int rn = bits (insn1, 0, 2); | |
8010 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
8011 | ||
8012 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
8013 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
8014 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
8015 | condition is false, let it be, cleanup_branch will do nothing. */ | |
8016 | if (dsc->u.branch.cond) | |
8017 | { | |
8018 | dsc->u.branch.cond = INST_AL; | |
8019 | dsc->u.branch.dest = from + 4 + imm5; | |
8020 | } | |
8021 | else | |
8022 | dsc->u.branch.dest = from + 2; | |
8023 | ||
8024 | dsc->u.branch.link = 0; | |
8025 | dsc->u.branch.exchange = 0; | |
8026 | ||
136821d9 SM |
8027 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
8028 | non_zero ? "cbnz" : "cbz", | |
8029 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
8030 | |
8031 | dsc->modinsn[0] = THUMB_NOP; | |
8032 | ||
8033 | dsc->cleanup = &cleanup_branch; | |
8034 | return 0; | |
8035 | } | |
8036 | ||
8037 | /* Copy Table Branch Byte/Halfword */ | |
8038 | static int | |
8039 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
8040 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 8041 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8042 | { |
8043 | ULONGEST rn_val, rm_val; | |
8044 | int is_tbh = bit (insn2, 4); | |
8045 | CORE_ADDR halfwords = 0; | |
8046 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8047 | ||
8048 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
8049 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
8050 | ||
8051 | if (is_tbh) | |
8052 | { | |
8053 | gdb_byte buf[2]; | |
8054 | ||
8055 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
8056 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
8057 | } | |
8058 | else | |
8059 | { | |
8060 | gdb_byte buf[1]; | |
8061 | ||
8062 | target_read_memory (rn_val + rm_val, buf, 1); | |
8063 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
8064 | } | |
8065 | ||
136821d9 SM |
8066 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
8067 | is_tbh ? "tbh" : "tbb", | |
8068 | (unsigned int) rn_val, (unsigned int) rm_val, | |
8069 | (unsigned int) halfwords); | |
34518530 YQ |
8070 | |
8071 | dsc->u.branch.cond = INST_AL; | |
8072 | dsc->u.branch.link = 0; | |
8073 | dsc->u.branch.exchange = 0; | |
8074 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
8075 | ||
8076 | dsc->cleanup = &cleanup_branch; | |
8077 | ||
8078 | return 0; | |
8079 | } | |
8080 | ||
8081 | static void | |
8082 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 8083 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8084 | { |
8085 | /* PC <- r7 */ | |
8086 | int val = displaced_read_reg (regs, dsc, 7); | |
8087 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
8088 | ||
8089 | /* r7 <- r8 */ | |
8090 | val = displaced_read_reg (regs, dsc, 8); | |
8091 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
8092 | ||
8093 | /* r8 <- tmp[0] */ | |
8094 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
8095 | ||
8096 | } | |
8097 | ||
8098 | static int | |
615234c1 | 8099 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 8100 | struct regcache *regs, |
1152d984 | 8101 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8102 | { |
8103 | dsc->u.block.regmask = insn1 & 0x00ff; | |
8104 | ||
8105 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
8106 | to : | |
8107 | ||
8108 | (1) register list is full, that is, r0-r7 are used. | |
8109 | Prepare: tmp[0] <- r8 | |
8110 | ||
8111 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
8112 | MOV r8, r7; Move value of r7 to r8; | |
8113 | POP {r7}; Store PC value into r7. | |
8114 | ||
8115 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
8116 | ||
8117 | (2) register list is not full, supposing there are N registers in | |
8118 | register list (except PC, 0 <= N <= 7). | |
8119 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
8120 | ||
8121 | POP {r0, r1, ...., rN}; | |
8122 | ||
8123 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
8124 | from tmp[] properly. | |
8125 | */ | |
136821d9 SM |
8126 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
8127 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
8128 | |
8129 | if (dsc->u.block.regmask == 0xff) | |
8130 | { | |
8131 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
8132 | ||
8133 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
8134 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
8135 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
8136 | ||
8137 | dsc->numinsns = 3; | |
8138 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
8139 | } | |
8140 | else | |
8141 | { | |
5f661e03 | 8142 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
8143 | unsigned int i; |
8144 | unsigned int new_regmask; | |
34518530 YQ |
8145 | |
8146 | for (i = 0; i < num_in_list + 1; i++) | |
8147 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
8148 | ||
8149 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
8150 | ||
136821d9 SM |
8151 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
8152 | "modified list %.4x", | |
8153 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
8154 | |
8155 | dsc->u.block.regmask |= 0x8000; | |
8156 | dsc->u.block.writeback = 0; | |
8157 | dsc->u.block.cond = INST_AL; | |
8158 | ||
8159 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
8160 | ||
8161 | dsc->cleanup = &cleanup_block_load_pc; | |
8162 | } | |
8163 | ||
8164 | return 0; | |
8165 | } | |
8166 | ||
8167 | static void | |
8168 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8169 | struct regcache *regs, | |
1152d984 | 8170 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8171 | { |
8172 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
8173 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
8174 | int err = 0; | |
8175 | ||
8176 | /* 16-bit thumb instructions. */ | |
8177 | switch (op_bit_12_15) | |
8178 | { | |
8179 | /* Shift (imme), add, subtract, move and compare. */ | |
8180 | case 0: case 1: case 2: case 3: | |
8181 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8182 | "shift/add/sub/mov/cmp", | |
8183 | dsc); | |
8184 | break; | |
8185 | case 4: | |
8186 | switch (op_bit_10_11) | |
8187 | { | |
8188 | case 0: /* Data-processing */ | |
8189 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
8190 | "data-processing", | |
8191 | dsc); | |
8192 | break; | |
8193 | case 1: /* Special data instructions and branch and exchange. */ | |
8194 | { | |
8195 | unsigned short op = bits (insn1, 7, 9); | |
8196 | if (op == 6 || op == 7) /* BX or BLX */ | |
8197 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
8198 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
8199 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
8200 | else | |
8201 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
8202 | dsc); | |
8203 | } | |
8204 | break; | |
8205 | default: /* LDR (literal) */ | |
8206 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
8207 | } | |
8208 | break; | |
8209 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
8210 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
8211 | break; | |
8212 | case 10: | |
8213 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
8214 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
8215 | else /* Generate SP-relative address */ | |
8216 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
8217 | break; | |
8218 | case 11: /* Misc 16-bit instructions */ | |
8219 | { | |
8220 | switch (bits (insn1, 8, 11)) | |
8221 | { | |
8222 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
8223 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
8224 | break; | |
8225 | case 12: case 13: /* POP */ | |
8226 | if (bit (insn1, 8)) /* PC is in register list. */ | |
8227 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
8228 | else | |
8229 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
8230 | break; | |
8231 | case 15: /* If-Then, and hints */ | |
8232 | if (bits (insn1, 0, 3)) | |
8233 | /* If-Then makes up to four following instructions conditional. | |
8234 | IT instruction itself is not conditional, so handle it as a | |
8235 | common unmodified instruction. */ | |
8236 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
8237 | dsc); | |
8238 | else | |
8239 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
8240 | break; | |
8241 | default: | |
8242 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
8243 | } | |
8244 | } | |
8245 | break; | |
8246 | case 12: | |
8247 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
8248 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
8249 | else /* Load multiple registers */ | |
8250 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
8251 | break; | |
8252 | case 13: /* Conditional branch and supervisor call */ | |
8253 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
8254 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8255 | else | |
8256 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
8257 | break; | |
8258 | case 14: /* Unconditional branch */ | |
8259 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8260 | break; | |
8261 | default: | |
8262 | err = 1; | |
8263 | } | |
8264 | ||
8265 | if (err) | |
f34652de | 8266 | internal_error (_("thumb_process_displaced_16bit_insn: Instruction decode error")); |
34518530 YQ |
8267 | } |
8268 | ||
8269 | static int | |
8270 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
8271 | uint16_t insn1, uint16_t insn2, | |
8272 | struct regcache *regs, | |
1152d984 | 8273 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8274 | { |
8275 | int rt = bits (insn2, 12, 15); | |
8276 | int rn = bits (insn1, 0, 3); | |
8277 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
8278 | |
8279 | switch (bits (insn1, 5, 6)) | |
8280 | { | |
8281 | case 0: /* Load byte and memory hints */ | |
8282 | if (rt == 0xf) /* PLD/PLI */ | |
8283 | { | |
8284 | if (rn == 0xf) | |
8285 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
8286 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
8287 | else | |
8288 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8289 | "pli/pld", dsc); | |
8290 | } | |
8291 | else | |
8292 | { | |
8293 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
8294 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8295 | 1); | |
8296 | else | |
8297 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8298 | "ldrb{reg, immediate}/ldrbt", | |
8299 | dsc); | |
8300 | } | |
8301 | ||
8302 | break; | |
8303 | case 1: /* Load halfword and memory hints. */ | |
8304 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
8305 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8306 | "pld/unalloc memhint", dsc); | |
8307 | else | |
8308 | { | |
8309 | if (rn == 0xf) | |
8310 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8311 | 2); | |
8312 | else | |
8313 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8314 | "ldrh/ldrht", dsc); | |
8315 | } | |
8316 | break; | |
8317 | case 2: /* Load word */ | |
8318 | { | |
8319 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
8320 | ||
8321 | if (rn == 0xf) | |
8322 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
8323 | else if (op1 == 0x1) /* Encoding T3 */ | |
8324 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
8325 | 0, 1); | |
8326 | else /* op1 == 0x0 */ | |
8327 | { | |
8328 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
8329 | /* LDR (immediate) */ | |
8330 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8331 | dsc, bit (insn2, 8), 1); | |
8332 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
8333 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8334 | "ldrt", dsc); | |
8335 | else | |
8336 | /* LDR (register) */ | |
8337 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8338 | dsc, 0, 0); | |
8339 | } | |
8340 | break; | |
8341 | } | |
8342 | default: | |
8343 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
8344 | break; | |
8345 | } | |
8346 | return 0; | |
8347 | } | |
8348 | ||
8349 | static void | |
8350 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8351 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 8352 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8353 | { |
8354 | int err = 0; | |
8355 | unsigned short op = bit (insn2, 15); | |
8356 | unsigned int op1 = bits (insn1, 11, 12); | |
8357 | ||
8358 | switch (op1) | |
8359 | { | |
8360 | case 1: | |
8361 | { | |
8362 | switch (bits (insn1, 9, 10)) | |
8363 | { | |
8364 | case 0: | |
8365 | if (bit (insn1, 6)) | |
8366 | { | |
405feb71 | 8367 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
8368 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
8369 | && bits (insn2, 5, 7) == 0) | |
8370 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
8371 | dsc); | |
8372 | else | |
8373 | /* PC is not allowed to use in load/store {dual, exclusive} | |
8374 | instructions. */ | |
8375 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8376 | "load/store dual/ex", dsc); | |
8377 | } | |
8378 | else /* load/store multiple */ | |
8379 | { | |
8380 | switch (bits (insn1, 7, 8)) | |
8381 | { | |
8382 | case 0: case 3: /* SRS, RFE */ | |
8383 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8384 | "srs/rfe", dsc); | |
8385 | break; | |
8386 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
8387 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
8388 | break; | |
8389 | } | |
8390 | } | |
8391 | break; | |
8392 | ||
8393 | case 1: | |
8394 | /* Data-processing (shift register). */ | |
8395 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
8396 | dsc); | |
8397 | break; | |
8398 | default: /* Coprocessor instructions. */ | |
8399 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8400 | break; | |
8401 | } | |
8402 | break; | |
8403 | } | |
8404 | case 2: /* op1 = 2 */ | |
8405 | if (op) /* Branch and misc control. */ | |
8406 | { | |
8407 | if (bit (insn2, 14) /* BLX/BL */ | |
8408 | || bit (insn2, 12) /* Unconditional branch */ | |
8409 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
8410 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
8411 | else | |
8412 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8413 | "misc ctrl", dsc); | |
8414 | } | |
8415 | else | |
8416 | { | |
8417 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
8418 | { | |
b926417a | 8419 | int dp_op = bits (insn1, 4, 8); |
34518530 | 8420 | int rn = bits (insn1, 0, 3); |
b926417a | 8421 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
8422 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
8423 | regs, dsc); | |
8424 | else | |
8425 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8426 | "dp/pb", dsc); | |
8427 | } | |
405feb71 | 8428 | else /* Data processing (modified immediate) */ |
34518530 YQ |
8429 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
8430 | "dp/mi", dsc); | |
8431 | } | |
8432 | break; | |
8433 | case 3: /* op1 = 3 */ | |
8434 | switch (bits (insn1, 9, 10)) | |
8435 | { | |
8436 | case 0: | |
8437 | if (bit (insn1, 4)) | |
8438 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
8439 | regs, dsc); | |
8440 | else /* NEON Load/Store and Store single data item */ | |
8441 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8442 | "neon elt/struct load/store", | |
8443 | dsc); | |
8444 | break; | |
8445 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
8446 | switch (bits (insn1, 7, 8)) | |
8447 | { | |
8448 | case 0: case 1: /* Data processing (register) */ | |
8449 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8450 | "dp(reg)", dsc); | |
8451 | break; | |
8452 | case 2: /* Multiply and absolute difference */ | |
8453 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8454 | "mul/mua/diff", dsc); | |
8455 | break; | |
8456 | case 3: /* Long multiply and divide */ | |
8457 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8458 | "lmul/lmua", dsc); | |
8459 | break; | |
8460 | } | |
8461 | break; | |
8462 | default: /* Coprocessor instructions */ | |
8463 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8464 | break; | |
8465 | } | |
8466 | break; | |
8467 | default: | |
8468 | err = 1; | |
8469 | } | |
8470 | ||
8471 | if (err) | |
f34652de | 8472 | internal_error (_("thumb_process_displaced_32bit_insn: Instruction decode error")); |
34518530 YQ |
8473 | |
8474 | } | |
8475 | ||
b434a28f YQ |
8476 | static void |
8477 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 8478 | struct regcache *regs, |
1152d984 | 8479 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 8480 | { |
34518530 YQ |
8481 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8482 | uint16_t insn1 | |
8483 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
8484 | ||
136821d9 SM |
8485 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
8486 | insn1, (unsigned long) from); | |
34518530 YQ |
8487 | |
8488 | dsc->is_thumb = 1; | |
8489 | dsc->insn_size = thumb_insn_size (insn1); | |
8490 | if (thumb_insn_size (insn1) == 4) | |
8491 | { | |
8492 | uint16_t insn2 | |
8493 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
8494 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
8495 | } | |
8496 | else | |
8497 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
8498 | } |
8499 | ||
cca44b1b | 8500 | void |
b434a28f YQ |
8501 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
8502 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 8503 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
8504 | { |
8505 | int err = 0; | |
b434a28f YQ |
8506 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8507 | uint32_t insn; | |
cca44b1b JB |
8508 | |
8509 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
8510 | here and override below if/when necessary. */ | |
8511 | dsc->numinsns = 1; | |
8512 | dsc->insn_addr = from; | |
8513 | dsc->scratch_base = to; | |
8514 | dsc->cleanup = NULL; | |
8515 | dsc->wrote_to_pc = 0; | |
8516 | ||
b434a28f | 8517 | if (!displaced_in_arm_mode (regs)) |
12545665 | 8518 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 8519 | |
4db71c0b YQ |
8520 | dsc->is_thumb = 0; |
8521 | dsc->insn_size = 4; | |
b434a28f | 8522 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
8523 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
8524 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 8525 | |
cca44b1b | 8526 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 8527 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8528 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
8529 | { | |
8530 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 8531 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8532 | break; |
8533 | ||
8534 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 8535 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8536 | break; |
8537 | ||
8538 | case 0x7: | |
7ff120b4 | 8539 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
8540 | break; |
8541 | ||
8542 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 8543 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8544 | break; |
8545 | ||
8546 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 8547 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8548 | break; |
8549 | } | |
8550 | ||
8551 | if (err) | |
f34652de | 8552 | internal_error (_("arm_process_displaced_insn: Instruction decode error")); |
cca44b1b JB |
8553 | } |
8554 | ||
8555 | /* Actually set up the scratch space for a displaced instruction. */ | |
8556 | ||
8557 | void | |
8558 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
8559 | CORE_ADDR to, |
8560 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 8561 | { |
08106042 | 8562 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
4db71c0b | 8563 | unsigned int i, len, offset; |
cca44b1b | 8564 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 8565 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 8566 | const gdb_byte *bkp_insn; |
cca44b1b | 8567 | |
4db71c0b | 8568 | offset = 0; |
cca44b1b JB |
8569 | /* Poke modified instruction(s). */ |
8570 | for (i = 0; i < dsc->numinsns; i++) | |
8571 | { | |
136821d9 SM |
8572 | if (size == 4) |
8573 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
8574 | dsc->modinsn[i], (unsigned long) to + offset); | |
8575 | else if (size == 2) | |
8576 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
8577 | (unsigned short) dsc->modinsn[i], | |
8578 | (unsigned long) to + offset); | |
4db71c0b | 8579 | |
4db71c0b YQ |
8580 | write_memory_unsigned_integer (to + offset, size, |
8581 | byte_order_for_code, | |
cca44b1b | 8582 | dsc->modinsn[i]); |
4db71c0b YQ |
8583 | offset += size; |
8584 | } | |
8585 | ||
8586 | /* Choose the correct breakpoint instruction. */ | |
8587 | if (dsc->is_thumb) | |
8588 | { | |
8589 | bkp_insn = tdep->thumb_breakpoint; | |
8590 | len = tdep->thumb_breakpoint_size; | |
8591 | } | |
8592 | else | |
8593 | { | |
8594 | bkp_insn = tdep->arm_breakpoint; | |
8595 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
8596 | } |
8597 | ||
8598 | /* Put breakpoint afterwards. */ | |
4db71c0b | 8599 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 8600 | |
136821d9 SM |
8601 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
8602 | paddress (gdbarch, to)); | |
cca44b1b JB |
8603 | } |
8604 | ||
cca44b1b JB |
8605 | /* Entry point for cleaning things up after a displaced instruction has been |
8606 | single-stepped. */ | |
8607 | ||
8608 | void | |
8609 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 8610 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
8611 | CORE_ADDR from, CORE_ADDR to, |
8612 | struct regcache *regs) | |
8613 | { | |
1152d984 SM |
8614 | arm_displaced_step_copy_insn_closure *dsc |
8615 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 8616 | |
cca44b1b JB |
8617 | if (dsc->cleanup) |
8618 | dsc->cleanup (gdbarch, regs, dsc); | |
8619 | ||
8620 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
8621 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
8622 | dsc->insn_addr + dsc->insn_size); | |
8623 | ||
cca44b1b JB |
8624 | } |
8625 | ||
8626 | #include "bfd-in2.h" | |
8627 | #include "libcoff.h" | |
8628 | ||
8629 | static int | |
8630 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
8631 | { | |
f0c2e3e0 AB |
8632 | gdb_disassemble_info *di |
8633 | = static_cast<gdb_disassemble_info *> (info->application_data); | |
e47ad6c0 | 8634 | struct gdbarch *gdbarch = di->arch (); |
9779414d DJ |
8635 | |
8636 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
8637 | { |
8638 | static asymbol *asym; | |
8639 | static combined_entry_type ce; | |
8640 | static struct coff_symbol_struct csym; | |
8641 | static struct bfd fake_bfd; | |
8642 | static bfd_target fake_target; | |
8643 | ||
8644 | if (csym.native == NULL) | |
8645 | { | |
8646 | /* Create a fake symbol vector containing a Thumb symbol. | |
8647 | This is solely so that the code in print_insn_little_arm() | |
8648 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
8649 | the presence of a Thumb symbol and switch to decoding | |
8650 | Thumb instructions. */ | |
8651 | ||
8652 | fake_target.flavour = bfd_target_coff_flavour; | |
8653 | fake_bfd.xvec = &fake_target; | |
8654 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
8655 | csym.native = &ce; | |
8656 | csym.symbol.the_bfd = &fake_bfd; | |
8657 | csym.symbol.name = "fake"; | |
8658 | asym = (asymbol *) & csym; | |
8659 | } | |
8660 | ||
8661 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
8662 | info->symbols = &asym; | |
8663 | } | |
8664 | else | |
8665 | info->symbols = NULL; | |
8666 | ||
e60eb288 YQ |
8667 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
8668 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
8669 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
8670 | the assert on the mismatch of info->mach and |
8671 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
8672 | default_print_insn. */ | |
3047c786 TV |
8673 | if (current_program_space->exec_bfd () != NULL |
8674 | && (current_program_space->exec_bfd ()->arch_info | |
8675 | == gdbarch_bfd_arch_info (gdbarch))) | |
e60eb288 YQ |
8676 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
8677 | ||
6394c606 | 8678 | return default_print_insn (memaddr, info); |
cca44b1b JB |
8679 | } |
8680 | ||
8681 | /* The following define instruction sequences that will cause ARM | |
8682 | cpu's to take an undefined instruction trap. These are used to | |
8683 | signal a breakpoint to GDB. | |
8684 | ||
8685 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
8686 | modes. A different instruction is required for each mode. The ARM | |
8687 | cpu's can also be big or little endian. Thus four different | |
8688 | instructions are needed to support all cases. | |
8689 | ||
8690 | Note: ARMv4 defines several new instructions that will take the | |
8691 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
8692 | not in fact add the new instructions. The new undefined | |
8693 | instructions in ARMv4 are all instructions that had no defined | |
8694 | behaviour in earlier chips. There is no guarantee that they will | |
8695 | raise an exception, but may be treated as NOP's. In practice, it | |
8696 | may only safe to rely on instructions matching: | |
8697 | ||
8698 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
8699 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
8700 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
8701 | ||
0963b4bd | 8702 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
8703 | following use a condition predicate of ALWAYS so it is always TRUE. |
8704 | ||
8705 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
8706 | and NetBSD all use a software interrupt rather than an undefined | |
8707 | instruction to force a trap. This can be handled by by the | |
8708 | abi-specific code during establishment of the gdbarch vector. */ | |
8709 | ||
8710 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
8711 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
8712 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
8713 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
8714 | ||
948f8e3d PA |
8715 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
8716 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
8717 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
8718 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 8719 | |
cd6c3b4f YQ |
8720 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
8721 | ||
d19280ad YQ |
8722 | static int |
8723 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b | 8724 | { |
08106042 | 8725 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 8726 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 8727 | |
9779414d | 8728 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
8729 | { |
8730 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
8731 | |
8732 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
8733 | check whether we are replacing a 32-bit instruction. */ | |
8734 | if (tdep->thumb2_breakpoint != NULL) | |
8735 | { | |
8736 | gdb_byte buf[2]; | |
d19280ad | 8737 | |
177321bd DJ |
8738 | if (target_read_memory (*pcptr, buf, 2) == 0) |
8739 | { | |
8740 | unsigned short inst1; | |
d19280ad | 8741 | |
177321bd | 8742 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 8743 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 8744 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
8745 | } |
8746 | } | |
8747 | ||
d19280ad | 8748 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
8749 | } |
8750 | else | |
d19280ad YQ |
8751 | return ARM_BP_KIND_ARM; |
8752 | ||
8753 | } | |
8754 | ||
cd6c3b4f YQ |
8755 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
8756 | ||
d19280ad YQ |
8757 | static const gdb_byte * |
8758 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
8759 | { | |
08106042 | 8760 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
d19280ad YQ |
8761 | |
8762 | switch (kind) | |
cca44b1b | 8763 | { |
d19280ad YQ |
8764 | case ARM_BP_KIND_ARM: |
8765 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 8766 | return tdep->arm_breakpoint; |
d19280ad YQ |
8767 | case ARM_BP_KIND_THUMB: |
8768 | *size = tdep->thumb_breakpoint_size; | |
8769 | return tdep->thumb_breakpoint; | |
8770 | case ARM_BP_KIND_THUMB2: | |
8771 | *size = tdep->thumb2_breakpoint_size; | |
8772 | return tdep->thumb2_breakpoint; | |
8773 | default: | |
8774 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
8775 | } |
8776 | } | |
8777 | ||
833b7ab5 YQ |
8778 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
8779 | ||
8780 | static int | |
8781 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
8782 | struct regcache *regcache, | |
8783 | CORE_ADDR *pcptr) | |
8784 | { | |
8785 | gdb_byte buf[4]; | |
8786 | ||
8787 | /* Check the memory pointed by PC is readable. */ | |
8788 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
8789 | { | |
8790 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
8791 | |
8792 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
8793 | &arm_get_next_pcs_ops, | |
8794 | gdbarch_byte_order (gdbarch), | |
8795 | gdbarch_byte_order_for_code (gdbarch), | |
8796 | 0, | |
8797 | regcache); | |
8798 | ||
a0ff9e1a | 8799 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
8800 | |
8801 | /* If MEMADDR is the next instruction of current pc, do the | |
8802 | software single step computation, and get the thumb mode by | |
8803 | the destination address. */ | |
a0ff9e1a | 8804 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
8805 | { |
8806 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
8807 | { | |
833b7ab5 YQ |
8808 | if (IS_THUMB_ADDR (pc)) |
8809 | { | |
8810 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
8811 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8812 | } | |
8813 | else | |
8814 | return ARM_BP_KIND_ARM; | |
8815 | } | |
8816 | } | |
833b7ab5 YQ |
8817 | } |
8818 | ||
8819 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8820 | } | |
8821 | ||
cca44b1b JB |
8822 | /* Extract from an array REGBUF containing the (raw) register state a |
8823 | function return value of type TYPE, and copy that, in virtual | |
8824 | format, into VALBUF. */ | |
8825 | ||
8826 | static void | |
8827 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
8828 | gdb_byte *valbuf) | |
8829 | { | |
ac7936df | 8830 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b | 8831 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 8832 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
cca44b1b | 8833 | |
78134374 | 8834 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b | 8835 | { |
345bd07c | 8836 | switch (tdep->fp_model) |
cca44b1b JB |
8837 | { |
8838 | case ARM_FLOAT_FPA: | |
8839 | { | |
8840 | /* The value is in register F0 in internal format. We need to | |
8841 | extract the raw value and then convert it to the desired | |
8842 | internal type. */ | |
f0452268 | 8843 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 8844 | |
dca08e1f | 8845 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
8846 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
8847 | valbuf, type); | |
cca44b1b JB |
8848 | } |
8849 | break; | |
8850 | ||
8851 | case ARM_FLOAT_SOFT_FPA: | |
8852 | case ARM_FLOAT_SOFT_VFP: | |
8853 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
8854 | not using the VFP ABI code. */ | |
8855 | case ARM_FLOAT_VFP: | |
dca08e1f | 8856 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
df86565b | 8857 | if (type->length () > 4) |
f0452268 AH |
8858 | regs->cooked_read (ARM_A1_REGNUM + 1, |
8859 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
8860 | break; |
8861 | ||
8862 | default: | |
f34652de | 8863 | internal_error (_("arm_extract_return_value: " |
0963b4bd | 8864 | "Floating point model not supported")); |
cca44b1b JB |
8865 | break; |
8866 | } | |
8867 | } | |
78134374 SM |
8868 | else if (type->code () == TYPE_CODE_INT |
8869 | || type->code () == TYPE_CODE_CHAR | |
8870 | || type->code () == TYPE_CODE_BOOL | |
8871 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8872 | || TYPE_IS_REFERENCE (type) |
a6617193 JB |
8873 | || type->code () == TYPE_CODE_ENUM |
8874 | || is_fixed_point_type (type)) | |
cca44b1b | 8875 | { |
b021a221 MS |
8876 | /* If the type is a plain integer, then the access is |
8877 | straight-forward. Otherwise we have to play around a bit | |
8878 | more. */ | |
df86565b | 8879 | int len = type->length (); |
cca44b1b JB |
8880 | int regno = ARM_A1_REGNUM; |
8881 | ULONGEST tmp; | |
8882 | ||
8883 | while (len > 0) | |
8884 | { | |
8885 | /* By using store_unsigned_integer we avoid having to do | |
8886 | anything special for small big-endian values. */ | |
8887 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
8888 | store_unsigned_integer (valbuf, | |
f0452268 AH |
8889 | (len > ARM_INT_REGISTER_SIZE |
8890 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 8891 | byte_order, tmp); |
f0452268 AH |
8892 | len -= ARM_INT_REGISTER_SIZE; |
8893 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8894 | } |
8895 | } | |
8896 | else | |
8897 | { | |
8898 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8899 | been stored to word-aligned memory and then loaded into |
8900 | registers with 32-bit load instruction(s). */ | |
df86565b | 8901 | int len = type->length (); |
cca44b1b | 8902 | int regno = ARM_A1_REGNUM; |
f0452268 | 8903 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
8904 | |
8905 | while (len > 0) | |
8906 | { | |
dca08e1f | 8907 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 8908 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
8909 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
8910 | len -= ARM_INT_REGISTER_SIZE; | |
8911 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8912 | } |
8913 | } | |
8914 | } | |
8915 | ||
8916 | ||
8917 | /* Will a function return an aggregate type in memory or in a | |
8918 | register? Return 0 if an aggregate type can be returned in a | |
8919 | register, 1 if it must be returned in memory. */ | |
8920 | ||
8921 | static int | |
8922 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
8923 | { | |
cca44b1b JB |
8924 | enum type_code code; |
8925 | ||
f168693b | 8926 | type = check_typedef (type); |
cca44b1b | 8927 | |
b13c8ab2 YQ |
8928 | /* Simple, non-aggregate types (ie not including vectors and |
8929 | complex) are always returned in a register (or registers). */ | |
78134374 | 8930 | code = type->code (); |
b13c8ab2 YQ |
8931 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
8932 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
8933 | return 0; | |
cca44b1b | 8934 | |
bd63c870 | 8935 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
8936 | { |
8937 | /* Vector values should be returned using ARM registers if they | |
8938 | are not over 16 bytes. */ | |
df86565b | 8939 | return (type->length () > 16); |
c4312b19 YQ |
8940 | } |
8941 | ||
08106042 | 8942 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 8943 | if (tdep->arm_abi != ARM_ABI_APCS) |
cca44b1b | 8944 | { |
b13c8ab2 YQ |
8945 | /* The AAPCS says all aggregates not larger than a word are returned |
8946 | in a register. */ | |
df86565b | 8947 | if (type->length () <= ARM_INT_REGISTER_SIZE |
bab22d06 | 8948 | && language_pass_by_reference (type).trivially_copyable) |
b13c8ab2 YQ |
8949 | return 0; |
8950 | ||
cca44b1b JB |
8951 | return 1; |
8952 | } | |
b13c8ab2 YQ |
8953 | else |
8954 | { | |
8955 | int nRc; | |
cca44b1b | 8956 | |
b13c8ab2 YQ |
8957 | /* All aggregate types that won't fit in a register must be returned |
8958 | in memory. */ | |
df86565b | 8959 | if (type->length () > ARM_INT_REGISTER_SIZE |
bab22d06 | 8960 | || !language_pass_by_reference (type).trivially_copyable) |
b13c8ab2 | 8961 | return 1; |
cca44b1b | 8962 | |
b13c8ab2 YQ |
8963 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8964 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8965 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8966 | offset of each addressable subfield must be zero. Note that bit |
8967 | fields are not addressable, and all addressable subfields of | |
8968 | unions always start at offset zero. | |
cca44b1b | 8969 | |
b13c8ab2 YQ |
8970 | This function is based on the behaviour of GCC 2.95.1. |
8971 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8972 | |
b13c8ab2 YQ |
8973 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8974 | parameters correctly for a function returning the following | |
8975 | structure: struct { float f;}; This should be returned in memory, | |
8976 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8977 | know of any way to detect if a function like the above has been | |
8978 | compiled with the correct calling convention. */ | |
8979 | ||
8980 | /* Assume all other aggregate types can be returned in a register. | |
8981 | Run a check for structures, unions and arrays. */ | |
8982 | nRc = 0; | |
67255d04 | 8983 | |
b13c8ab2 YQ |
8984 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8985 | { | |
8986 | int i; | |
8987 | /* Need to check if this struct/union is "integer" like. For | |
8988 | this to be true, its size must be less than or equal to | |
f0452268 | 8989 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8990 | subfield must be zero. Note that bit fields are not |
8991 | addressable, and unions always start at offset zero. If any | |
8992 | of the subfields is a floating point type, the struct/union | |
8993 | cannot be an integer type. */ | |
8994 | ||
8995 | /* For each field in the object, check: | |
8996 | 1) Is it FP? --> yes, nRc = 1; | |
8997 | 2) Is it addressable (bitpos != 0) and | |
8998 | not packed (bitsize == 0)? | |
8999 | --> yes, nRc = 1 | |
9000 | */ | |
9001 | ||
1f704f76 | 9002 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 9003 | { |
b13c8ab2 YQ |
9004 | enum type_code field_type_code; |
9005 | ||
9006 | field_type_code | |
940da03e | 9007 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
9008 | |
9009 | /* Is it a floating point type field? */ | |
9010 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
9011 | { |
9012 | nRc = 1; | |
9013 | break; | |
9014 | } | |
b13c8ab2 YQ |
9015 | |
9016 | /* If bitpos != 0, then we have to care about it. */ | |
b610c045 | 9017 | if (type->field (i).loc_bitpos () != 0) |
b13c8ab2 YQ |
9018 | { |
9019 | /* Bitfields are not addressable. If the field bitsize is | |
9020 | zero, then the field is not packed. Hence it cannot be | |
9021 | a bitfield or any other packed type. */ | |
9022 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
9023 | { | |
9024 | nRc = 1; | |
9025 | break; | |
9026 | } | |
9027 | } | |
67255d04 RE |
9028 | } |
9029 | } | |
67255d04 | 9030 | |
b13c8ab2 YQ |
9031 | return nRc; |
9032 | } | |
67255d04 RE |
9033 | } |
9034 | ||
34e8f22d RE |
9035 | /* Write into appropriate registers a function return value of type |
9036 | TYPE, given in virtual format. */ | |
9037 | ||
9038 | static void | |
b508a996 | 9039 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 9040 | const gdb_byte *valbuf) |
34e8f22d | 9041 | { |
ac7936df | 9042 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 9043 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 9044 | |
78134374 | 9045 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 9046 | { |
f0452268 | 9047 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
08106042 | 9048 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
34e8f22d | 9049 | |
345bd07c | 9050 | switch (tdep->fp_model) |
08216dd7 RE |
9051 | { |
9052 | case ARM_FLOAT_FPA: | |
9053 | ||
3b2ca824 | 9054 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 9055 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
9056 | break; |
9057 | ||
fd50bc42 | 9058 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 9059 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
9060 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
9061 | not using the VFP ABI code. */ | |
9062 | case ARM_FLOAT_VFP: | |
b66f5587 | 9063 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
df86565b | 9064 | if (type->length () > 4) |
f0452268 AH |
9065 | regs->cooked_write (ARM_A1_REGNUM + 1, |
9066 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
9067 | break; |
9068 | ||
9069 | default: | |
f34652de | 9070 | internal_error (_("arm_store_return_value: Floating " |
9b20d036 | 9071 | "point model not supported")); |
08216dd7 RE |
9072 | break; |
9073 | } | |
34e8f22d | 9074 | } |
78134374 SM |
9075 | else if (type->code () == TYPE_CODE_INT |
9076 | || type->code () == TYPE_CODE_CHAR | |
9077 | || type->code () == TYPE_CODE_BOOL | |
9078 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 9079 | || TYPE_IS_REFERENCE (type) |
78134374 | 9080 | || type->code () == TYPE_CODE_ENUM) |
b508a996 | 9081 | { |
df86565b | 9082 | if (type->length () <= 4) |
b508a996 RE |
9083 | { |
9084 | /* Values of one word or less are zero/sign-extended and | |
9085 | returned in r0. */ | |
f0452268 | 9086 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
9087 | LONGEST val = unpack_long (type, valbuf); |
9088 | ||
f0452268 | 9089 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 9090 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
9091 | } |
9092 | else | |
9093 | { | |
9094 | /* Integral values greater than one word are stored in consecutive | |
9095 | registers starting with r0. This will always be a multiple of | |
9096 | the regiser size. */ | |
df86565b | 9097 | int len = type->length (); |
b508a996 RE |
9098 | int regno = ARM_A1_REGNUM; |
9099 | ||
9100 | while (len > 0) | |
9101 | { | |
b66f5587 | 9102 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
9103 | len -= ARM_INT_REGISTER_SIZE; |
9104 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
9105 | } |
9106 | } | |
9107 | } | |
34e8f22d | 9108 | else |
b508a996 RE |
9109 | { |
9110 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
9111 | been stored to word-aligned memory and then loaded into |
9112 | registers with 32-bit load instruction(s). */ | |
df86565b | 9113 | int len = type->length (); |
b508a996 | 9114 | int regno = ARM_A1_REGNUM; |
f0452268 | 9115 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
9116 | |
9117 | while (len > 0) | |
9118 | { | |
9119 | memcpy (tmpbuf, valbuf, | |
f0452268 | 9120 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 9121 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
9122 | len -= ARM_INT_REGISTER_SIZE; |
9123 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
9124 | } |
9125 | } | |
34e8f22d RE |
9126 | } |
9127 | ||
2af48f68 PB |
9128 | |
9129 | /* Handle function return values. */ | |
9130 | ||
9131 | static enum return_value_convention | |
6a3a010b | 9132 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
9133 | struct type *valtype, struct regcache *regcache, |
9134 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 9135 | { |
08106042 | 9136 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
6a3a010b | 9137 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
9138 | enum arm_vfp_cprc_base_type vfp_base_type; |
9139 | int vfp_base_count; | |
9140 | ||
9141 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
9142 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
9143 | { | |
9144 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
9145 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
9146 | int i; | |
9147 | for (i = 0; i < vfp_base_count; i++) | |
9148 | { | |
58d6951d DJ |
9149 | if (reg_char == 'q') |
9150 | { | |
9151 | if (writebuf) | |
9152 | arm_neon_quad_write (gdbarch, regcache, i, | |
9153 | writebuf + i * unit_length); | |
9154 | ||
9155 | if (readbuf) | |
9156 | arm_neon_quad_read (gdbarch, regcache, i, | |
9157 | readbuf + i * unit_length); | |
9158 | } | |
9159 | else | |
9160 | { | |
9161 | char name_buf[4]; | |
9162 | int regnum; | |
9163 | ||
8c042590 | 9164 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
9165 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9166 | strlen (name_buf)); | |
9167 | if (writebuf) | |
b66f5587 | 9168 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 9169 | if (readbuf) |
dca08e1f | 9170 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 9171 | } |
90445bd3 DJ |
9172 | } |
9173 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9174 | } | |
7c00367c | 9175 | |
78134374 SM |
9176 | if (valtype->code () == TYPE_CODE_STRUCT |
9177 | || valtype->code () == TYPE_CODE_UNION | |
9178 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 9179 | { |
bab22d06 LM |
9180 | /* From the AAPCS document: |
9181 | ||
9182 | Result return: | |
9183 | ||
9184 | A Composite Type larger than 4 bytes, or whose size cannot be | |
9185 | determined statically by both caller and callee, is stored in memory | |
9186 | at an address passed as an extra argument when the function was | |
9187 | called (Parameter Passing, rule A.4). The memory to be used for the | |
9188 | result may be modified at any point during the function call. | |
9189 | ||
9190 | Parameter Passing: | |
9191 | ||
9192 | A.4: If the subroutine is a function that returns a result in memory, | |
9193 | then the address for the result is placed in r0 and the NCRN is set | |
9194 | to r1. */ | |
7c00367c MK |
9195 | if (tdep->struct_return == pcc_struct_return |
9196 | || arm_return_in_memory (gdbarch, valtype)) | |
bab22d06 LM |
9197 | { |
9198 | if (readbuf) | |
9199 | { | |
9200 | CORE_ADDR addr; | |
9201 | ||
9202 | regcache->cooked_read (ARM_A1_REGNUM, &addr); | |
df86565b | 9203 | read_memory (addr, readbuf, valtype->length ()); |
bab22d06 LM |
9204 | } |
9205 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
9206 | } | |
2af48f68 | 9207 | } |
78134374 | 9208 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
9209 | { |
9210 | if (arm_return_in_memory (gdbarch, valtype)) | |
9211 | return RETURN_VALUE_STRUCT_CONVENTION; | |
9212 | } | |
7052e42c | 9213 | |
2af48f68 PB |
9214 | if (writebuf) |
9215 | arm_store_return_value (valtype, regcache, writebuf); | |
9216 | ||
9217 | if (readbuf) | |
9218 | arm_extract_return_value (valtype, regcache, readbuf); | |
9219 | ||
9220 | return RETURN_VALUE_REGISTER_CONVENTION; | |
9221 | } | |
9222 | ||
9223 | ||
9df628e0 | 9224 | static int |
bd2b40ac | 9225 | arm_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
9df628e0 | 9226 | { |
e17a4113 | 9227 | struct gdbarch *gdbarch = get_frame_arch (frame); |
08106042 | 9228 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
e17a4113 | 9229 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9df628e0 | 9230 | CORE_ADDR jb_addr; |
f0452268 | 9231 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 9232 | |
60ade65d | 9233 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
9234 | |
9235 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 9236 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
9237 | return 0; |
9238 | ||
f0452268 | 9239 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
9240 | return 1; |
9241 | } | |
40eadf04 SP |
9242 | /* A call to cmse secure entry function "foo" at "a" is modified by |
9243 | GNU ld as "b". | |
9244 | a) bl xxxx <foo> | |
9245 | ||
9246 | <foo> | |
9247 | xxxx: | |
9248 | ||
9249 | b) bl yyyy <__acle_se_foo> | |
9250 | ||
9251 | section .gnu.sgstubs: | |
9252 | <foo> | |
9253 | yyyy: sg // secure gateway | |
9254 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
9255 | ||
9256 | <__acle_se_foo> | |
9257 | xxxx: | |
9258 | ||
9259 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
9260 | trampoline and does not exist in source code. This function returns the | |
9261 | target pc "xxxx". For more details please refer to section 5.4 | |
9262 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
9263 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
9264 | document on www.developer.arm.com. */ | |
9265 | ||
9266 | static CORE_ADDR | |
9267 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
9268 | { | |
9269 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
9270 | char *target_name = (char *) alloca (target_len); | |
9271 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
9272 | ||
9273 | struct bound_minimal_symbol minsym | |
9274 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
9275 | ||
9276 | if (minsym.minsym != nullptr) | |
4aeddc50 | 9277 | return minsym.value_address (); |
40eadf04 SP |
9278 | |
9279 | return 0; | |
9280 | } | |
9281 | ||
9282 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
9283 | ||
9284 | static bool | |
9285 | arm_is_sgstubs_section (struct obj_section *sec) | |
9286 | { | |
9287 | return (sec != nullptr | |
9288 | && sec->the_bfd_section != nullptr | |
9289 | && sec->the_bfd_section->name != nullptr | |
9290 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
9291 | } | |
9df628e0 | 9292 | |
faa95490 DJ |
9293 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
9294 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
9295 | |
9296 | CORE_ADDR | |
bd2b40ac | 9297 | arm_skip_stub (frame_info_ptr frame, CORE_ADDR pc) |
c906108c | 9298 | { |
2c02bd72 | 9299 | const char *name; |
faa95490 | 9300 | int namelen; |
c906108c SS |
9301 | CORE_ADDR start_addr; |
9302 | ||
9303 | /* Find the starting address and name of the function containing the PC. */ | |
9304 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
9305 | { |
9306 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
9307 | check here. */ | |
9308 | start_addr = arm_skip_bx_reg (frame, pc); | |
9309 | if (start_addr != 0) | |
9310 | return start_addr; | |
9311 | ||
9312 | return 0; | |
9313 | } | |
c906108c | 9314 | |
faa95490 DJ |
9315 | /* If PC is in a Thumb call or return stub, return the address of the |
9316 | target PC, which is in a register. The thunk functions are called | |
9317 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
9318 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
9319 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
9320 | if (startswith (name, "_call_via_") |
9321 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 9322 | { |
ed9a39eb | 9323 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 9324 | target PC. */ |
a121b7c1 | 9325 | static const char *table[15] = |
c5aa993b JM |
9326 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
9327 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
9328 | }; | |
c906108c | 9329 | int regno; |
faa95490 | 9330 | int offset = strlen (name) - 2; |
c906108c SS |
9331 | |
9332 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 9333 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 9334 | return get_frame_register_unsigned (frame, regno); |
c906108c | 9335 | } |
ed9a39eb | 9336 | |
faa95490 DJ |
9337 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
9338 | non-interworking calls to foo. We could decode the stubs | |
9339 | to find the target but it's easier to use the symbol table. */ | |
9340 | namelen = strlen (name); | |
9341 | if (name[0] == '_' && name[1] == '_' | |
9342 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 9343 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 9344 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 9345 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
9346 | { |
9347 | char *target_name; | |
9348 | int target_len = namelen - 2; | |
3b7344d5 | 9349 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
9350 | struct objfile *objfile; |
9351 | struct obj_section *sec; | |
9352 | ||
9353 | if (name[namelen - 1] == 'b') | |
9354 | target_len -= strlen ("_from_thumb"); | |
9355 | else | |
9356 | target_len -= strlen ("_from_arm"); | |
9357 | ||
224c3ddb | 9358 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
9359 | memcpy (target_name, name + 2, target_len); |
9360 | target_name[target_len] = '\0'; | |
9361 | ||
9362 | sec = find_pc_section (pc); | |
9363 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
9364 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 9365 | if (minsym.minsym != NULL) |
4aeddc50 | 9366 | return minsym.value_address (); |
faa95490 DJ |
9367 | else |
9368 | return 0; | |
9369 | } | |
9370 | ||
40eadf04 SP |
9371 | struct obj_section *section = find_pc_section (pc); |
9372 | ||
9373 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
9374 | if (arm_is_sgstubs_section (section)) | |
9375 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
9376 | ||
c5aa993b | 9377 | return 0; /* not a stub */ |
c906108c SS |
9378 | } |
9379 | ||
28e97307 DJ |
9380 | static void |
9381 | arm_update_current_architecture (void) | |
fd50bc42 | 9382 | { |
28e97307 | 9383 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 9384 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 9385 | return; |
fd50bc42 | 9386 | |
28e97307 | 9387 | /* Update the architecture. */ |
b447dd03 | 9388 | gdbarch_info info; |
28e97307 | 9389 | if (!gdbarch_update_p (info)) |
f34652de | 9390 | internal_error (_("could not update architecture")); |
fd50bc42 RE |
9391 | } |
9392 | ||
9393 | static void | |
eb4c3f4a | 9394 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
9395 | struct cmd_list_element *c) |
9396 | { | |
570dc176 | 9397 | int fp_model; |
fd50bc42 RE |
9398 | |
9399 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
9400 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
9401 | { | |
aead7601 | 9402 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
9403 | break; |
9404 | } | |
9405 | ||
9406 | if (fp_model == ARM_FLOAT_LAST) | |
f34652de | 9407 | internal_error (_("Invalid fp model accepted: %s."), |
fd50bc42 RE |
9408 | current_fp_model); |
9409 | ||
28e97307 | 9410 | arm_update_current_architecture (); |
fd50bc42 RE |
9411 | } |
9412 | ||
9413 | static void | |
08546159 AC |
9414 | show_fp_model (struct ui_file *file, int from_tty, |
9415 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 9416 | { |
28e97307 | 9417 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 9418 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9419 | { |
9420 | arm_gdbarch_tdep *tdep | |
08106042 | 9421 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9422 | |
9423 | gdb_printf (file, _("\ | |
28e97307 | 9424 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9425 | fp_model_strings[tdep->fp_model]); |
9426 | } | |
28e97307 | 9427 | else |
6cb06a8c | 9428 | gdb_printf (file, _("\ |
28e97307 | 9429 | The current ARM floating point model is \"%s\".\n"), |
6cb06a8c | 9430 | fp_model_strings[arm_fp_model]); |
28e97307 DJ |
9431 | } |
9432 | ||
9433 | static void | |
eb4c3f4a | 9434 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
9435 | struct cmd_list_element *c) |
9436 | { | |
570dc176 | 9437 | int arm_abi; |
28e97307 DJ |
9438 | |
9439 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
9440 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
9441 | { | |
aead7601 | 9442 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
9443 | break; |
9444 | } | |
9445 | ||
9446 | if (arm_abi == ARM_ABI_LAST) | |
f34652de | 9447 | internal_error (_("Invalid ABI accepted: %s."), |
28e97307 DJ |
9448 | arm_abi_string); |
9449 | ||
9450 | arm_update_current_architecture (); | |
9451 | } | |
9452 | ||
9453 | static void | |
9454 | arm_show_abi (struct ui_file *file, int from_tty, | |
9455 | struct cmd_list_element *c, const char *value) | |
9456 | { | |
28e97307 | 9457 | if (arm_abi_global == ARM_ABI_AUTO |
f5656ead | 9458 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9459 | { |
9460 | arm_gdbarch_tdep *tdep | |
08106042 | 9461 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9462 | |
9463 | gdb_printf (file, _("\ | |
28e97307 | 9464 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9465 | arm_abi_strings[tdep->arm_abi]); |
9466 | } | |
28e97307 | 9467 | else |
6cb06a8c TT |
9468 | gdb_printf (file, _("The current ARM ABI is \"%s\".\n"), |
9469 | arm_abi_string); | |
fd50bc42 RE |
9470 | } |
9471 | ||
0428b8f5 DJ |
9472 | static void |
9473 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
9474 | struct cmd_list_element *c, const char *value) | |
9475 | { | |
6cb06a8c TT |
9476 | gdb_printf (file, |
9477 | _("The current execution mode assumed " | |
9478 | "(when symbols are unavailable) is \"%s\".\n"), | |
9479 | arm_fallback_mode_string); | |
0428b8f5 DJ |
9480 | } |
9481 | ||
9482 | static void | |
9483 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
9484 | struct cmd_list_element *c, const char *value) | |
9485 | { | |
6cb06a8c TT |
9486 | gdb_printf (file, |
9487 | _("The current execution mode assumed " | |
9488 | "(even when symbols are available) is \"%s\".\n"), | |
9489 | arm_force_mode_string); | |
0428b8f5 DJ |
9490 | } |
9491 | ||
ef273377 CL |
9492 | static void |
9493 | arm_show_unwind_secure_frames (struct ui_file *file, int from_tty, | |
9494 | struct cmd_list_element *c, const char *value) | |
9495 | { | |
9496 | gdb_printf (file, | |
9497 | _("Usage of non-secure to secure exception stack unwinding is %s.\n"), | |
9498 | arm_unwind_secure_frames ? "on" : "off"); | |
9499 | } | |
9500 | ||
afd7eef0 RE |
9501 | /* If the user changes the register disassembly style used for info |
9502 | register and other commands, we have to also switch the style used | |
9503 | in opcodes for disassembly output. This function is run in the "set | |
9504 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
9505 | |
9506 | static void | |
eb4c3f4a | 9507 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 9508 | struct cmd_list_element *c) |
bc90b915 | 9509 | { |
65b48a81 PB |
9510 | /* Convert the short style name into the long style name (eg, reg-names-*) |
9511 | before calling the generic set_disassembler_options() function. */ | |
9512 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
9513 | set_disassembler_options (&long_name[0]); | |
9514 | } | |
9515 | ||
9516 | static void | |
9517 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
9518 | struct cmd_list_element *c, const char *value) | |
9519 | { | |
9520 | struct gdbarch *gdbarch = get_current_arch (); | |
9521 | char *options = get_disassembler_options (gdbarch); | |
9522 | const char *style = ""; | |
9523 | int len = 0; | |
f995bbe8 | 9524 | const char *opt; |
65b48a81 PB |
9525 | |
9526 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
08dedd66 | 9527 | if (startswith (opt, "reg-names-")) |
65b48a81 PB |
9528 | { |
9529 | style = &opt[strlen ("reg-names-")]; | |
9530 | len = strcspn (style, ","); | |
9531 | } | |
9532 | ||
6cb06a8c | 9533 | gdb_printf (file, "The disassembly style is \"%.*s\".\n", len, style); |
bc90b915 FN |
9534 | } |
9535 | \f | |
966fbf70 | 9536 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 9537 | static const char * |
d93859e2 | 9538 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 9539 | { |
08106042 | 9540 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 9541 | |
ecbf5d4f | 9542 | if (is_s_pseudo (gdbarch, i)) |
58d6951d | 9543 | { |
ecbf5d4f | 9544 | static const char *const s_pseudo_names[] = { |
58d6951d DJ |
9545 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
9546 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
9547 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
9548 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
9549 | }; | |
9550 | ||
ecbf5d4f | 9551 | return s_pseudo_names[i - tdep->s_pseudo_base]; |
58d6951d DJ |
9552 | } |
9553 | ||
ecbf5d4f | 9554 | if (is_q_pseudo (gdbarch, i)) |
58d6951d | 9555 | { |
ecbf5d4f | 9556 | static const char *const q_pseudo_names[] = { |
58d6951d DJ |
9557 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", |
9558 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
9559 | }; | |
9560 | ||
ecbf5d4f | 9561 | return q_pseudo_names[i - tdep->q_pseudo_base]; |
58d6951d DJ |
9562 | } |
9563 | ||
ae66a8f1 SP |
9564 | if (is_mve_pseudo (gdbarch, i)) |
9565 | return "p0"; | |
9566 | ||
a01567f4 LM |
9567 | /* RA_AUTH_CODE is used for unwinding only. Do not assign it a name. */ |
9568 | if (is_pacbti_pseudo (gdbarch, i)) | |
9569 | return ""; | |
9570 | ||
ff6f572f DJ |
9571 | if (i >= ARRAY_SIZE (arm_register_names)) |
9572 | /* These registers are only supported on targets which supply | |
9573 | an XML description. */ | |
9574 | return ""; | |
9575 | ||
ecbf5d4f | 9576 | /* Non-pseudo registers. */ |
966fbf70 RE |
9577 | return arm_register_names[i]; |
9578 | } | |
9579 | ||
082fc60d RE |
9580 | /* Test whether the coff symbol specific value corresponds to a Thumb |
9581 | function. */ | |
9582 | ||
9583 | static int | |
9584 | coff_sym_is_thumb (int val) | |
9585 | { | |
f8bf5763 PM |
9586 | return (val == C_THUMBEXT |
9587 | || val == C_THUMBSTAT | |
9588 | || val == C_THUMBEXTFUNC | |
9589 | || val == C_THUMBSTATFUNC | |
9590 | || val == C_THUMBLABEL); | |
082fc60d RE |
9591 | } |
9592 | ||
9593 | /* arm_coff_make_msymbol_special() | |
9594 | arm_elf_make_msymbol_special() | |
9595 | ||
9596 | These functions test whether the COFF or ELF symbol corresponds to | |
9597 | an address in thumb code, and set a "special" bit in a minimal | |
9598 | symbol to indicate that it does. */ | |
9599 | ||
34e8f22d | 9600 | static void |
082fc60d RE |
9601 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
9602 | { | |
39d911fc TP |
9603 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
9604 | ||
9605 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 9606 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
9607 | MSYMBOL_SET_SPECIAL (msym); |
9608 | } | |
9609 | ||
34e8f22d | 9610 | static void |
082fc60d RE |
9611 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
9612 | { | |
9613 | if (coff_sym_is_thumb (val)) | |
9614 | MSYMBOL_SET_SPECIAL (msym); | |
9615 | } | |
9616 | ||
60c5725c DJ |
9617 | static void |
9618 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
9619 | asymbol *sym) | |
9620 | { | |
9621 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 9622 | struct arm_per_bfd *data; |
60c5725c DJ |
9623 | struct arm_mapping_symbol new_map_sym; |
9624 | ||
9625 | gdb_assert (name[0] == '$'); | |
9626 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
9627 | return; | |
9628 | ||
98badbfd | 9629 | data = arm_bfd_data_key.get (objfile->obfd.get ()); |
60c5725c | 9630 | if (data == NULL) |
98badbfd | 9631 | data = arm_bfd_data_key.emplace (objfile->obfd.get (), |
bd5766ec | 9632 | objfile->obfd->section_count); |
54cc7474 | 9633 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 9634 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
9635 | |
9636 | new_map_sym.value = sym->value; | |
9637 | new_map_sym.type = name[1]; | |
9638 | ||
4838e44c SM |
9639 | /* Insert at the end, the vector will be sorted on first use. */ |
9640 | map.push_back (new_map_sym); | |
60c5725c DJ |
9641 | } |
9642 | ||
756fe439 | 9643 | static void |
61a1198a | 9644 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 9645 | { |
ac7936df | 9646 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 9647 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
9648 | |
9649 | /* If necessary, set the T bit. */ | |
9650 | if (arm_apcs_32) | |
9651 | { | |
9779414d | 9652 | ULONGEST val, t_bit; |
61a1198a | 9653 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
9654 | t_bit = arm_psr_thumb_bit (gdbarch); |
9655 | if (arm_pc_is_thumb (gdbarch, pc)) | |
9656 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
9657 | val | t_bit); | |
756fe439 | 9658 | else |
61a1198a | 9659 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 9660 | val & ~t_bit); |
756fe439 DJ |
9661 | } |
9662 | } | |
123dc839 | 9663 | |
58d6951d DJ |
9664 | /* Read the contents of a NEON quad register, by reading from two |
9665 | double registers. This is used to implement the quad pseudo | |
9666 | registers, and for argument passing in case the quad registers are | |
9667 | missing; vectors are passed in quad registers when using the VFP | |
9668 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
9669 | the quad register, in [0, 15]. */ | |
9670 | ||
05d1431c | 9671 | static enum register_status |
849d0ba8 | 9672 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9673 | int regnum, gdb_byte *buf) |
9674 | { | |
9675 | char name_buf[4]; | |
9676 | gdb_byte reg_buf[8]; | |
9677 | int offset, double_regnum; | |
05d1431c | 9678 | enum register_status status; |
58d6951d | 9679 | |
8c042590 | 9680 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9681 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9682 | strlen (name_buf)); | |
9683 | ||
9684 | /* d0 is always the least significant half of q0. */ | |
9685 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9686 | offset = 8; | |
9687 | else | |
9688 | offset = 0; | |
9689 | ||
03f50fc8 | 9690 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9691 | if (status != REG_VALID) |
9692 | return status; | |
58d6951d DJ |
9693 | memcpy (buf + offset, reg_buf, 8); |
9694 | ||
9695 | offset = 8 - offset; | |
03f50fc8 | 9696 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
9697 | if (status != REG_VALID) |
9698 | return status; | |
58d6951d | 9699 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
9700 | |
9701 | return REG_VALID; | |
58d6951d DJ |
9702 | } |
9703 | ||
ae66a8f1 SP |
9704 | /* Read the contents of the MVE pseudo register REGNUM and store it |
9705 | in BUF. */ | |
9706 | ||
9707 | static enum register_status | |
9708 | arm_mve_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, | |
9709 | int regnum, gdb_byte *buf) | |
9710 | { | |
08106042 | 9711 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9712 | |
9713 | /* P0 is the first 16 bits of VPR. */ | |
9714 | return regcache->raw_read_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9715 | } | |
9716 | ||
05d1431c | 9717 | static enum register_status |
849d0ba8 | 9718 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9719 | int regnum, gdb_byte *buf) |
9720 | { | |
9721 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9722 | char name_buf[4]; | |
9723 | gdb_byte reg_buf[8]; | |
9724 | int offset, double_regnum; | |
08106042 | 9725 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9726 | |
9727 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9728 | |
ecbf5d4f LM |
9729 | if (is_q_pseudo (gdbarch, regnum)) |
9730 | { | |
9731 | /* Quad-precision register. */ | |
9732 | return arm_neon_quad_read (gdbarch, regcache, | |
9733 | regnum - tdep->q_pseudo_base, buf); | |
9734 | } | |
ae66a8f1 SP |
9735 | else if (is_mve_pseudo (gdbarch, regnum)) |
9736 | return arm_mve_pseudo_read (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9737 | else |
9738 | { | |
05d1431c PA |
9739 | enum register_status status; |
9740 | ||
ecbf5d4f | 9741 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9742 | /* Single-precision register. */ |
9743 | gdb_assert (regnum < 32); | |
9744 | ||
9745 | /* s0 is always the least significant half of d0. */ | |
9746 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9747 | offset = (regnum & 1) ? 0 : 4; | |
9748 | else | |
9749 | offset = (regnum & 1) ? 4 : 0; | |
9750 | ||
8c042590 | 9751 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9752 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9753 | strlen (name_buf)); | |
9754 | ||
03f50fc8 | 9755 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9756 | if (status == REG_VALID) |
9757 | memcpy (buf, reg_buf + offset, 4); | |
9758 | return status; | |
58d6951d DJ |
9759 | } |
9760 | } | |
9761 | ||
9762 | /* Store the contents of BUF to a NEON quad register, by writing to | |
9763 | two double registers. This is used to implement the quad pseudo | |
9764 | registers, and for argument passing in case the quad registers are | |
9765 | missing; vectors are passed in quad registers when using the VFP | |
9766 | ABI, even if a NEON unit is not present. REGNUM is the index | |
9767 | of the quad register, in [0, 15]. */ | |
9768 | ||
9769 | static void | |
9770 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9771 | int regnum, const gdb_byte *buf) | |
9772 | { | |
9773 | char name_buf[4]; | |
58d6951d DJ |
9774 | int offset, double_regnum; |
9775 | ||
8c042590 | 9776 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9777 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9778 | strlen (name_buf)); | |
9779 | ||
9780 | /* d0 is always the least significant half of q0. */ | |
9781 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9782 | offset = 8; | |
9783 | else | |
9784 | offset = 0; | |
9785 | ||
10eaee5f | 9786 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 9787 | offset = 8 - offset; |
10eaee5f | 9788 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
9789 | } |
9790 | ||
ae66a8f1 SP |
9791 | /* Store the contents of BUF to the MVE pseudo register REGNUM. */ |
9792 | ||
9793 | static void | |
9794 | arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9795 | int regnum, const gdb_byte *buf) | |
9796 | { | |
08106042 | 9797 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9798 | |
9799 | /* P0 is the first 16 bits of VPR. */ | |
9800 | regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9801 | } | |
9802 | ||
58d6951d DJ |
9803 | static void |
9804 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9805 | int regnum, const gdb_byte *buf) | |
9806 | { | |
9807 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9808 | char name_buf[4]; | |
9809 | gdb_byte reg_buf[8]; | |
9810 | int offset, double_regnum; | |
08106042 | 9811 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9812 | |
9813 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9814 | |
ecbf5d4f LM |
9815 | if (is_q_pseudo (gdbarch, regnum)) |
9816 | { | |
9817 | /* Quad-precision register. */ | |
9818 | arm_neon_quad_write (gdbarch, regcache, | |
9819 | regnum - tdep->q_pseudo_base, buf); | |
9820 | } | |
ae66a8f1 SP |
9821 | else if (is_mve_pseudo (gdbarch, regnum)) |
9822 | arm_mve_pseudo_write (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9823 | else |
9824 | { | |
ecbf5d4f | 9825 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9826 | /* Single-precision register. */ |
9827 | gdb_assert (regnum < 32); | |
9828 | ||
9829 | /* s0 is always the least significant half of d0. */ | |
9830 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9831 | offset = (regnum & 1) ? 0 : 4; | |
9832 | else | |
9833 | offset = (regnum & 1) ? 4 : 0; | |
9834 | ||
8c042590 | 9835 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9836 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9837 | strlen (name_buf)); | |
9838 | ||
0b883586 | 9839 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 9840 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 9841 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
9842 | } |
9843 | } | |
9844 | ||
123dc839 | 9845 | static struct value * |
bd2b40ac | 9846 | value_of_arm_user_reg (frame_info_ptr frame, const void *baton) |
123dc839 | 9847 | { |
9a3c8263 | 9848 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
9849 | return value_of_register (*reg_p, frame); |
9850 | } | |
97e03143 | 9851 | \f |
70f80edf JT |
9852 | static enum gdb_osabi |
9853 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 9854 | { |
2af48f68 | 9855 | unsigned int elfosabi; |
70f80edf | 9856 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 9857 | |
70f80edf | 9858 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 9859 | |
28e97307 DJ |
9860 | if (elfosabi == ELFOSABI_ARM) |
9861 | /* GNU tools use this value. Check note sections in this case, | |
9862 | as well. */ | |
b35c1d1c TT |
9863 | { |
9864 | for (asection *sect : gdb_bfd_sections (abfd)) | |
9865 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
9866 | } | |
97e03143 | 9867 | |
28e97307 | 9868 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 9869 | return osabi; |
97e03143 RE |
9870 | } |
9871 | ||
54483882 YQ |
9872 | static int |
9873 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 9874 | const struct reggroup *group) |
54483882 | 9875 | { |
2c291032 YQ |
9876 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
9877 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
9878 | all_reggroup, of course. */ | |
54483882 | 9879 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
9880 | return (group == float_reggroup |
9881 | || group == save_reggroup | |
9882 | || group == restore_reggroup | |
9883 | || group == all_reggroup); | |
54483882 YQ |
9884 | else |
9885 | return default_register_reggroup_p (gdbarch, regnum, group); | |
9886 | } | |
9887 | ||
25f8c692 JL |
9888 | /* For backward-compatibility we allow two 'g' packet lengths with |
9889 | the remote protocol depending on whether FPA registers are | |
9890 | supplied. M-profile targets do not have FPA registers, but some | |
9891 | stubs already exist in the wild which use a 'g' packet which | |
9892 | supplies them albeit with dummy values. The packet format which | |
9893 | includes FPA registers should be considered deprecated for | |
9894 | M-profile targets. */ | |
9895 | ||
9896 | static void | |
9897 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
9898 | { | |
08106042 | 9899 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9900 | |
9901 | if (tdep->is_m) | |
25f8c692 | 9902 | { |
d105cce5 AH |
9903 | const target_desc *tdesc; |
9904 | ||
25f8c692 JL |
9905 | /* If we know from the executable this is an M-profile target, |
9906 | cater for remote targets whose register set layout is the | |
9907 | same as the FPA layout. */ | |
d105cce5 | 9908 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 9909 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9910 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 9911 | tdesc); |
25f8c692 JL |
9912 | |
9913 | /* The regular M-profile layout. */ | |
d105cce5 | 9914 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 9915 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 9916 | tdesc); |
3184d3f9 JL |
9917 | |
9918 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 9919 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 9920 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9921 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 9922 | tdesc); |
ae66a8f1 SP |
9923 | /* M-profile plus MVE. */ |
9924 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_MVE); | |
9925 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE | |
9926 | + ARM_VFP2_REGS_SIZE | |
9927 | + ARM_INT_REGISTER_SIZE, tdesc); | |
9074667a CL |
9928 | |
9929 | /* M-profile system (stack pointers). */ | |
9930 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_SYSTEM); | |
9931 | register_remote_g_packet_guess (gdbarch, 2 * ARM_INT_REGISTER_SIZE, tdesc); | |
25f8c692 JL |
9932 | } |
9933 | ||
9934 | /* Otherwise we don't have a useful guess. */ | |
9935 | } | |
9936 | ||
7eb89530 YQ |
9937 | /* Implement the code_of_frame_writable gdbarch method. */ |
9938 | ||
9939 | static int | |
bd2b40ac | 9940 | arm_code_of_frame_writable (struct gdbarch *gdbarch, frame_info_ptr frame) |
7eb89530 | 9941 | { |
08106042 | 9942 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9943 | |
9944 | if (tdep->is_m && get_frame_type (frame) == SIGTRAMP_FRAME) | |
7eb89530 YQ |
9945 | { |
9946 | /* M-profile exception frames return to some magic PCs, where | |
9947 | isn't writable at all. */ | |
9948 | return 0; | |
9949 | } | |
9950 | else | |
9951 | return 1; | |
9952 | } | |
9953 | ||
3426ae57 AH |
9954 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
9955 | to be postfixed by a version (eg armv7hl). */ | |
9956 | ||
9957 | static const char * | |
9958 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
9959 | { | |
9960 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
9961 | return "arm(v[^- ]*)?"; | |
9962 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
9963 | } | |
9964 | ||
a01567f4 LM |
9965 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
9966 | ||
9967 | static std::string | |
bd2b40ac | 9968 | arm_get_pc_address_flags (frame_info_ptr frame, CORE_ADDR pc) |
a01567f4 LM |
9969 | { |
9970 | if (get_frame_pc_masked (frame)) | |
9971 | return "PAC"; | |
9972 | ||
9973 | return ""; | |
9974 | } | |
9975 | ||
da3c6d4a MS |
9976 | /* Initialize the current architecture based on INFO. If possible, |
9977 | re-use an architecture from ARCHES, which is a list of | |
9978 | architectures already created during this debugging session. | |
97e03143 | 9979 | |
da3c6d4a MS |
9980 | Called e.g. at program startup, when reading a core file, and when |
9981 | reading a binary file. */ | |
97e03143 | 9982 | |
39bbf761 RE |
9983 | static struct gdbarch * |
9984 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
9985 | { | |
9986 | struct gdbarch *gdbarch; | |
28e97307 DJ |
9987 | struct gdbarch_list *best_arch; |
9988 | enum arm_abi_kind arm_abi = arm_abi_global; | |
9989 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 9990 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
9991 | int i; |
9992 | bool is_m = false; | |
ae7e2f45 | 9993 | bool have_sec_ext = false; |
7559c217 | 9994 | int vfp_register_count = 0; |
ecbf5d4f | 9995 | bool have_s_pseudos = false, have_q_pseudos = false; |
7559c217 CB |
9996 | bool have_wmmx_registers = false; |
9997 | bool have_neon = false; | |
9998 | bool have_fpa_registers = true; | |
9779414d | 9999 | const struct target_desc *tdesc = info.target_desc; |
ae66a8f1 SP |
10000 | bool have_vfp = false; |
10001 | bool have_mve = false; | |
a01567f4 | 10002 | bool have_pacbti = false; |
ae66a8f1 | 10003 | int mve_vpr_regnum = -1; |
ecbf5d4f | 10004 | int register_count = ARM_NUM_REGS; |
9074667a CL |
10005 | bool have_m_profile_msp = false; |
10006 | int m_profile_msp_regnum = -1; | |
10007 | int m_profile_psp_regnum = -1; | |
ae7e2f45 CL |
10008 | int m_profile_msp_ns_regnum = -1; |
10009 | int m_profile_psp_ns_regnum = -1; | |
10010 | int m_profile_msp_s_regnum = -1; | |
10011 | int m_profile_psp_s_regnum = -1; | |
92d48a1e | 10012 | int tls_regnum = 0; |
9779414d DJ |
10013 | |
10014 | /* If we have an object to base this architecture on, try to determine | |
10015 | its ABI. */ | |
10016 | ||
10017 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
10018 | { | |
10019 | int ei_osabi, e_flags; | |
10020 | ||
10021 | switch (bfd_get_flavour (info.abfd)) | |
10022 | { | |
9779414d DJ |
10023 | case bfd_target_coff_flavour: |
10024 | /* Assume it's an old APCS-style ABI. */ | |
10025 | /* XXX WinCE? */ | |
10026 | arm_abi = ARM_ABI_APCS; | |
10027 | break; | |
10028 | ||
10029 | case bfd_target_elf_flavour: | |
10030 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
10031 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
10032 | ||
10033 | if (ei_osabi == ELFOSABI_ARM) | |
10034 | { | |
10035 | /* GNU tools used to use this value, but do not for EABI | |
10036 | objects. There's nowhere to tag an EABI version | |
10037 | anyway, so assume APCS. */ | |
10038 | arm_abi = ARM_ABI_APCS; | |
10039 | } | |
d403db27 | 10040 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
10041 | { |
10042 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
10043 | |
10044 | switch (eabi_ver) | |
10045 | { | |
10046 | case EF_ARM_EABI_UNKNOWN: | |
10047 | /* Assume GNU tools. */ | |
10048 | arm_abi = ARM_ABI_APCS; | |
10049 | break; | |
10050 | ||
10051 | case EF_ARM_EABI_VER4: | |
10052 | case EF_ARM_EABI_VER5: | |
10053 | arm_abi = ARM_ABI_AAPCS; | |
10054 | /* EABI binaries default to VFP float ordering. | |
10055 | They may also contain build attributes that can | |
10056 | be used to identify if the VFP argument-passing | |
10057 | ABI is in use. */ | |
10058 | if (fp_model == ARM_FLOAT_AUTO) | |
10059 | { | |
10060 | #ifdef HAVE_ELF | |
10061 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
10062 | OBJ_ATTR_PROC, | |
10063 | Tag_ABI_VFP_args)) | |
10064 | { | |
b35b0298 | 10065 | case AEABI_VFP_args_base: |
9779414d DJ |
10066 | /* "The user intended FP parameter/result |
10067 | passing to conform to AAPCS, base | |
10068 | variant". */ | |
10069 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10070 | break; | |
b35b0298 | 10071 | case AEABI_VFP_args_vfp: |
9779414d DJ |
10072 | /* "The user intended FP parameter/result |
10073 | passing to conform to AAPCS, VFP | |
10074 | variant". */ | |
10075 | fp_model = ARM_FLOAT_VFP; | |
10076 | break; | |
b35b0298 | 10077 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
10078 | /* "The user intended FP parameter/result |
10079 | passing to conform to tool chain-specific | |
10080 | conventions" - we don't know any such | |
10081 | conventions, so leave it as "auto". */ | |
10082 | break; | |
b35b0298 | 10083 | case AEABI_VFP_args_compatible: |
5c294fee TG |
10084 | /* "Code is compatible with both the base |
10085 | and VFP variants; the user did not permit | |
10086 | non-variadic functions to pass FP | |
10087 | parameters/results" - leave it as | |
10088 | "auto". */ | |
10089 | break; | |
9779414d DJ |
10090 | default: |
10091 | /* Attribute value not mentioned in the | |
5c294fee | 10092 | November 2012 ABI, so leave it as |
9779414d DJ |
10093 | "auto". */ |
10094 | break; | |
10095 | } | |
10096 | #else | |
10097 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10098 | #endif | |
10099 | } | |
10100 | break; | |
10101 | ||
10102 | default: | |
10103 | /* Leave it as "auto". */ | |
10104 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
10105 | break; | |
10106 | } | |
10107 | ||
10108 | #ifdef HAVE_ELF | |
10109 | /* Detect M-profile programs. This only works if the | |
10110 | executable file includes build attributes; GCC does | |
10111 | copy them to the executable, but e.g. RealView does | |
10112 | not. */ | |
17cbafdb SM |
10113 | int attr_arch |
10114 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10115 | Tag_CPU_arch); | |
10116 | int attr_profile | |
10117 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10118 | Tag_CPU_arch_profile); | |
10119 | ||
9779414d DJ |
10120 | /* GCC specifies the profile for v6-M; RealView only |
10121 | specifies the profile for architectures starting with | |
10122 | V7 (as opposed to architectures with a tag | |
10123 | numerically greater than TAG_CPU_ARCH_V7). */ | |
10124 | if (!tdesc_has_registers (tdesc) | |
10125 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
10126 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
131a355f LM |
10127 | || attr_arch == TAG_CPU_ARCH_V7E_M |
10128 | || attr_arch == TAG_CPU_ARCH_V8M_BASE | |
10129 | || attr_arch == TAG_CPU_ARCH_V8M_MAIN | |
ae66a8f1 | 10130 | || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN |
9779414d | 10131 | || attr_profile == 'M')) |
7559c217 | 10132 | is_m = true; |
a01567f4 LM |
10133 | |
10134 | /* Look for attributes that indicate support for ARMv8.1-m | |
10135 | PACBTI. */ | |
10136 | if (!tdesc_has_registers (tdesc) && is_m) | |
10137 | { | |
10138 | int attr_pac_extension | |
10139 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10140 | Tag_PAC_extension); | |
10141 | ||
10142 | int attr_bti_extension | |
10143 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10144 | Tag_BTI_extension); | |
10145 | ||
10146 | int attr_pacret_use | |
10147 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10148 | Tag_PACRET_use); | |
10149 | ||
10150 | int attr_bti_use | |
10151 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
10152 | Tag_BTI_use); | |
10153 | ||
10154 | if (attr_pac_extension != 0 || attr_bti_extension != 0 | |
10155 | || attr_pacret_use != 0 || attr_bti_use != 0) | |
10156 | have_pacbti = true; | |
10157 | } | |
9779414d DJ |
10158 | #endif |
10159 | } | |
10160 | ||
10161 | if (fp_model == ARM_FLOAT_AUTO) | |
10162 | { | |
9779414d DJ |
10163 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
10164 | { | |
10165 | case 0: | |
10166 | /* Leave it as "auto". Strictly speaking this case | |
10167 | means FPA, but almost nobody uses that now, and | |
10168 | many toolchains fail to set the appropriate bits | |
10169 | for the floating-point model they use. */ | |
10170 | break; | |
10171 | case EF_ARM_SOFT_FLOAT: | |
10172 | fp_model = ARM_FLOAT_SOFT_FPA; | |
10173 | break; | |
10174 | case EF_ARM_VFP_FLOAT: | |
10175 | fp_model = ARM_FLOAT_VFP; | |
10176 | break; | |
10177 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
10178 | fp_model = ARM_FLOAT_SOFT_VFP; | |
10179 | break; | |
10180 | } | |
10181 | } | |
10182 | ||
10183 | if (e_flags & EF_ARM_BE8) | |
10184 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
10185 | ||
10186 | break; | |
10187 | ||
10188 | default: | |
10189 | /* Leave it as "auto". */ | |
10190 | break; | |
10191 | } | |
10192 | } | |
123dc839 DJ |
10193 | |
10194 | /* Check any target description for validity. */ | |
9779414d | 10195 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
10196 | { |
10197 | /* For most registers we require GDB's default names; but also allow | |
10198 | the numeric names for sp / lr / pc, as a convenience. */ | |
10199 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
10200 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
10201 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
10202 | ||
10203 | const struct tdesc_feature *feature; | |
58d6951d | 10204 | int valid_p; |
123dc839 | 10205 | |
9779414d | 10206 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10207 | "org.gnu.gdb.arm.core"); |
10208 | if (feature == NULL) | |
9779414d DJ |
10209 | { |
10210 | feature = tdesc_find_feature (tdesc, | |
10211 | "org.gnu.gdb.arm.m-profile"); | |
10212 | if (feature == NULL) | |
10213 | return NULL; | |
10214 | else | |
7559c217 | 10215 | is_m = true; |
9779414d | 10216 | } |
123dc839 DJ |
10217 | |
10218 | tdesc_data = tdesc_data_alloc (); | |
10219 | ||
10220 | valid_p = 1; | |
10221 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 10222 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 10223 | arm_register_names[i]); |
c1e1314d | 10224 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10225 | ARM_SP_REGNUM, |
10226 | arm_sp_names); | |
c1e1314d | 10227 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10228 | ARM_LR_REGNUM, |
10229 | arm_lr_names); | |
c1e1314d | 10230 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
10231 | ARM_PC_REGNUM, |
10232 | arm_pc_names); | |
9779414d | 10233 | if (is_m) |
c1e1314d | 10234 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
10235 | ARM_PS_REGNUM, "xpsr"); |
10236 | else | |
c1e1314d | 10237 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 10238 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
10239 | |
10240 | if (!valid_p) | |
c1e1314d | 10241 | return NULL; |
123dc839 | 10242 | |
9074667a CL |
10243 | if (is_m) |
10244 | { | |
10245 | feature = tdesc_find_feature (tdesc, | |
10246 | "org.gnu.gdb.arm.m-system"); | |
10247 | if (feature != nullptr) | |
10248 | { | |
10249 | /* MSP */ | |
10250 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10251 | register_count, "msp"); | |
10252 | if (!valid_p) | |
10253 | { | |
10254 | warning (_("M-profile m-system feature is missing required register msp.")); | |
10255 | return nullptr; | |
10256 | } | |
10257 | have_m_profile_msp = true; | |
10258 | m_profile_msp_regnum = register_count++; | |
10259 | ||
10260 | /* PSP */ | |
10261 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10262 | register_count, "psp"); | |
10263 | if (!valid_p) | |
10264 | { | |
10265 | warning (_("M-profile m-system feature is missing required register psp.")); | |
10266 | return nullptr; | |
10267 | } | |
10268 | m_profile_psp_regnum = register_count++; | |
10269 | } | |
10270 | } | |
10271 | ||
9779414d | 10272 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10273 | "org.gnu.gdb.arm.fpa"); |
10274 | if (feature != NULL) | |
10275 | { | |
10276 | valid_p = 1; | |
10277 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 10278 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
10279 | arm_register_names[i]); |
10280 | if (!valid_p) | |
c1e1314d | 10281 | return NULL; |
123dc839 | 10282 | } |
ff6f572f | 10283 | else |
7559c217 | 10284 | have_fpa_registers = false; |
ff6f572f | 10285 | |
9779414d | 10286 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
10287 | "org.gnu.gdb.xscale.iwmmxt"); |
10288 | if (feature != NULL) | |
10289 | { | |
10290 | static const char *const iwmmxt_names[] = { | |
10291 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
10292 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
10293 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
10294 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
10295 | }; | |
10296 | ||
10297 | valid_p = 1; | |
10298 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
10299 | valid_p | |
c1e1314d | 10300 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10301 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10302 | ||
10303 | /* Check for the control registers, but do not fail if they | |
10304 | are missing. */ | |
10305 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 10306 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10307 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10308 | ||
10309 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
10310 | valid_p | |
c1e1314d | 10311 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10312 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10313 | ||
10314 | if (!valid_p) | |
c1e1314d | 10315 | return NULL; |
a56cc1ce | 10316 | |
7559c217 | 10317 | have_wmmx_registers = true; |
ff6f572f | 10318 | } |
58d6951d DJ |
10319 | |
10320 | /* If we have a VFP unit, check whether the single precision registers | |
10321 | are present. If not, then we will synthesize them as pseudo | |
10322 | registers. */ | |
9779414d | 10323 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10324 | "org.gnu.gdb.arm.vfp"); |
10325 | if (feature != NULL) | |
10326 | { | |
10327 | static const char *const vfp_double_names[] = { | |
10328 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
10329 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
10330 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
10331 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
10332 | }; | |
10333 | ||
10334 | /* Require the double precision registers. There must be either | |
10335 | 16 or 32. */ | |
10336 | valid_p = 1; | |
10337 | for (i = 0; i < 32; i++) | |
10338 | { | |
c1e1314d | 10339 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
10340 | ARM_D0_REGNUM + i, |
10341 | vfp_double_names[i]); | |
10342 | if (!valid_p) | |
10343 | break; | |
10344 | } | |
2b9e5ea6 UW |
10345 | if (!valid_p && i == 16) |
10346 | valid_p = 1; | |
58d6951d | 10347 | |
2b9e5ea6 | 10348 | /* Also require FPSCR. */ |
c1e1314d | 10349 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
10350 | ARM_FPSCR_REGNUM, "fpscr"); |
10351 | if (!valid_p) | |
c1e1314d | 10352 | return NULL; |
58d6951d | 10353 | |
ae66a8f1 SP |
10354 | have_vfp = true; |
10355 | ||
58d6951d | 10356 | if (tdesc_unnumbered_register (feature, "s0") == 0) |
ecbf5d4f | 10357 | have_s_pseudos = true; |
58d6951d | 10358 | |
330c6ca9 | 10359 | vfp_register_count = i; |
58d6951d DJ |
10360 | |
10361 | /* If we have VFP, also check for NEON. The architecture allows | |
10362 | NEON without VFP (integer vector operations only), but GDB | |
10363 | does not support that. */ | |
9779414d | 10364 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10365 | "org.gnu.gdb.arm.neon"); |
10366 | if (feature != NULL) | |
10367 | { | |
10368 | /* NEON requires 32 double-precision registers. */ | |
10369 | if (i != 32) | |
c1e1314d | 10370 | return NULL; |
58d6951d DJ |
10371 | |
10372 | /* If there are quad registers defined by the stub, use | |
10373 | their type; otherwise (normally) provide them with | |
10374 | the default type. */ | |
10375 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
ecbf5d4f | 10376 | have_q_pseudos = true; |
ae66a8f1 SP |
10377 | } |
10378 | } | |
10379 | ||
92d48a1e JB |
10380 | /* Check for the TLS register feature. */ |
10381 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.arm.tls"); | |
10382 | if (feature != nullptr) | |
10383 | { | |
10384 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10385 | register_count, "tpidruro"); | |
10386 | if (!valid_p) | |
10387 | return nullptr; | |
10388 | ||
10389 | tls_regnum = register_count; | |
10390 | register_count++; | |
10391 | } | |
10392 | ||
ae66a8f1 SP |
10393 | /* Check for MVE after all the checks for GPR's, VFP and Neon. |
10394 | MVE (Helium) is an M-profile extension. */ | |
10395 | if (is_m) | |
10396 | { | |
10397 | /* Do we have the MVE feature? */ | |
10398 | feature = tdesc_find_feature (tdesc,"org.gnu.gdb.arm.m-profile-mve"); | |
10399 | ||
10400 | if (feature != nullptr) | |
10401 | { | |
10402 | /* If we have MVE, we must always have the VPR register. */ | |
10403 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10404 | register_count, "vpr"); | |
10405 | if (!valid_p) | |
10406 | { | |
10407 | warning (_("MVE feature is missing required register vpr.")); | |
10408 | return nullptr; | |
10409 | } | |
58d6951d | 10410 | |
ae66a8f1 SP |
10411 | have_mve = true; |
10412 | mve_vpr_regnum = register_count; | |
10413 | register_count++; | |
10414 | ||
10415 | /* We can't have Q pseudo registers available here, as that | |
10416 | would mean we have NEON features, and that is only available | |
10417 | on A and R profiles. */ | |
10418 | gdb_assert (!have_q_pseudos); | |
10419 | ||
10420 | /* Given we have a M-profile target description, if MVE is | |
10421 | enabled and there are VFP registers, we should have Q | |
10422 | pseudo registers (Q0 ~ Q7). */ | |
10423 | if (have_vfp) | |
10424 | have_q_pseudos = true; | |
58d6951d | 10425 | } |
a01567f4 LM |
10426 | |
10427 | /* Do we have the ARMv8.1-m PACBTI feature? */ | |
10428 | feature = tdesc_find_feature (tdesc, | |
10429 | "org.gnu.gdb.arm.m-profile-pacbti"); | |
10430 | if (feature != nullptr) | |
10431 | { | |
10432 | /* By advertising this feature, the target acknowledges the | |
10433 | presence of the ARMv8.1-m PACBTI extensions. | |
10434 | ||
10435 | We don't care for any particular registers in this group, so | |
10436 | the target is free to include whatever it deems appropriate. | |
10437 | ||
10438 | The expectation is for this feature to include the PAC | |
10439 | keys. */ | |
10440 | have_pacbti = true; | |
10441 | } | |
ae7e2f45 CL |
10442 | |
10443 | /* Do we have the Security extension? */ | |
10444 | feature = tdesc_find_feature (tdesc, | |
10445 | "org.gnu.gdb.arm.secext"); | |
10446 | if (feature != nullptr) | |
10447 | { | |
10448 | /* Secure/Non-secure stack pointers. */ | |
10449 | /* MSP_NS */ | |
10450 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10451 | register_count, "msp_ns"); | |
10452 | if (!valid_p) | |
10453 | { | |
10454 | warning (_("M-profile secext feature is missing required register msp_ns.")); | |
10455 | return nullptr; | |
10456 | } | |
10457 | m_profile_msp_ns_regnum = register_count++; | |
10458 | ||
10459 | /* PSP_NS */ | |
10460 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10461 | register_count, "psp_ns"); | |
10462 | if (!valid_p) | |
10463 | { | |
10464 | warning (_("M-profile secext feature is missing required register psp_ns.")); | |
10465 | return nullptr; | |
10466 | } | |
10467 | m_profile_psp_ns_regnum = register_count++; | |
10468 | ||
10469 | /* MSP_S */ | |
10470 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10471 | register_count, "msp_s"); | |
10472 | if (!valid_p) | |
10473 | { | |
10474 | warning (_("M-profile secext feature is missing required register msp_s.")); | |
10475 | return nullptr; | |
10476 | } | |
10477 | m_profile_msp_s_regnum = register_count++; | |
10478 | ||
10479 | /* PSP_S */ | |
10480 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10481 | register_count, "psp_s"); | |
10482 | if (!valid_p) | |
10483 | { | |
10484 | warning (_("M-profile secext feature is missing required register psp_s.")); | |
10485 | return nullptr; | |
10486 | } | |
10487 | m_profile_psp_s_regnum = register_count++; | |
10488 | ||
10489 | have_sec_ext = true; | |
10490 | } | |
10491 | ||
58d6951d | 10492 | } |
123dc839 | 10493 | } |
39bbf761 | 10494 | |
28e97307 DJ |
10495 | /* If there is already a candidate, use it. */ |
10496 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
10497 | best_arch != NULL; | |
10498 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
10499 | { | |
345bd07c | 10500 | arm_gdbarch_tdep *tdep |
08106042 | 10501 | = gdbarch_tdep<arm_gdbarch_tdep> (best_arch->gdbarch); |
345bd07c SM |
10502 | |
10503 | if (arm_abi != ARM_ABI_AUTO && arm_abi != tdep->arm_abi) | |
28e97307 DJ |
10504 | continue; |
10505 | ||
345bd07c | 10506 | if (fp_model != ARM_FLOAT_AUTO && fp_model != tdep->fp_model) |
28e97307 DJ |
10507 | continue; |
10508 | ||
58d6951d DJ |
10509 | /* There are various other properties in tdep that we do not |
10510 | need to check here: those derived from a target description, | |
10511 | since gdbarches with a different target description are | |
10512 | automatically disqualified. */ | |
10513 | ||
9779414d | 10514 | /* Do check is_m, though, since it might come from the binary. */ |
345bd07c | 10515 | if (is_m != tdep->is_m) |
9779414d DJ |
10516 | continue; |
10517 | ||
a01567f4 LM |
10518 | /* Also check for ARMv8.1-m PACBTI support, since it might come from |
10519 | the binary. */ | |
10520 | if (have_pacbti != tdep->have_pacbti) | |
10521 | continue; | |
10522 | ||
28e97307 DJ |
10523 | /* Found a match. */ |
10524 | break; | |
10525 | } | |
97e03143 | 10526 | |
28e97307 | 10527 | if (best_arch != NULL) |
c1e1314d | 10528 | return best_arch->gdbarch; |
28e97307 | 10529 | |
345bd07c | 10530 | arm_gdbarch_tdep *tdep = new arm_gdbarch_tdep; |
97e03143 RE |
10531 | gdbarch = gdbarch_alloc (&info, tdep); |
10532 | ||
28e97307 DJ |
10533 | /* Record additional information about the architecture we are defining. |
10534 | These are gdbarch discriminators, like the OSABI. */ | |
10535 | tdep->arm_abi = arm_abi; | |
10536 | tdep->fp_model = fp_model; | |
9779414d | 10537 | tdep->is_m = is_m; |
ae7e2f45 | 10538 | tdep->have_sec_ext = have_sec_ext; |
ff6f572f | 10539 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 10540 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
10541 | gdb_assert (vfp_register_count == 0 |
10542 | || vfp_register_count == 16 | |
10543 | || vfp_register_count == 32); | |
10544 | tdep->vfp_register_count = vfp_register_count; | |
ecbf5d4f LM |
10545 | tdep->have_s_pseudos = have_s_pseudos; |
10546 | tdep->have_q_pseudos = have_q_pseudos; | |
58d6951d | 10547 | tdep->have_neon = have_neon; |
92d48a1e | 10548 | tdep->tls_regnum = tls_regnum; |
08216dd7 | 10549 | |
ae66a8f1 SP |
10550 | /* Adjust the MVE feature settings. */ |
10551 | if (have_mve) | |
10552 | { | |
10553 | tdep->have_mve = true; | |
10554 | tdep->mve_vpr_regnum = mve_vpr_regnum; | |
10555 | } | |
10556 | ||
a01567f4 LM |
10557 | /* Adjust the PACBTI feature settings. */ |
10558 | tdep->have_pacbti = have_pacbti; | |
10559 | ||
9074667a CL |
10560 | /* Adjust the M-profile stack pointers settings. */ |
10561 | if (have_m_profile_msp) | |
10562 | { | |
10563 | tdep->m_profile_msp_regnum = m_profile_msp_regnum; | |
10564 | tdep->m_profile_psp_regnum = m_profile_psp_regnum; | |
ae7e2f45 CL |
10565 | tdep->m_profile_msp_ns_regnum = m_profile_msp_ns_regnum; |
10566 | tdep->m_profile_psp_ns_regnum = m_profile_psp_ns_regnum; | |
10567 | tdep->m_profile_msp_s_regnum = m_profile_msp_s_regnum; | |
10568 | tdep->m_profile_psp_s_regnum = m_profile_psp_s_regnum; | |
9074667a CL |
10569 | } |
10570 | ||
25f8c692 JL |
10571 | arm_register_g_packet_guesses (gdbarch); |
10572 | ||
08216dd7 | 10573 | /* Breakpoints. */ |
9d4fde75 | 10574 | switch (info.byte_order_for_code) |
67255d04 RE |
10575 | { |
10576 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
10577 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
10578 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
10579 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
10580 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
10581 | ||
67255d04 RE |
10582 | break; |
10583 | ||
10584 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
10585 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
10586 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
10587 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
10588 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
10589 | ||
67255d04 RE |
10590 | break; |
10591 | ||
10592 | default: | |
f34652de | 10593 | internal_error (_("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
10594 | } |
10595 | ||
d7b486e7 RE |
10596 | /* On ARM targets char defaults to unsigned. */ |
10597 | set_gdbarch_char_signed (gdbarch, 0); | |
10598 | ||
53375380 PA |
10599 | /* wchar_t is unsigned under the AAPCS. */ |
10600 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
10601 | set_gdbarch_wchar_signed (gdbarch, 0); | |
10602 | else | |
10603 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 10604 | |
030197b4 AB |
10605 | /* Compute type alignment. */ |
10606 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
10607 | ||
cca44b1b JB |
10608 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
10609 | of additional scratch space. This setting isn't used for anything beside | |
10610 | displaced stepping at present. */ | |
e935475c | 10611 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 10612 | |
9df628e0 | 10613 | /* This should be low enough for everything. */ |
97e03143 | 10614 | tdep->lowest_pc = 0x20; |
94c30b78 | 10615 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 10616 | |
7c00367c MK |
10617 | /* The default, for both APCS and AAPCS, is to return small |
10618 | structures in registers. */ | |
10619 | tdep->struct_return = reg_struct_return; | |
10620 | ||
2dd604e7 | 10621 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 10622 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 10623 | |
7eb89530 YQ |
10624 | if (is_m) |
10625 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
10626 | ||
756fe439 DJ |
10627 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
10628 | ||
eb5492fa | 10629 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 10630 | |
34e8f22d | 10631 | /* Address manipulation. */ |
34e8f22d RE |
10632 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
10633 | ||
34e8f22d RE |
10634 | /* Advance PC across function entry code. */ |
10635 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
10636 | ||
c9cf6e20 MG |
10637 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
10638 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 10639 | |
190dce09 UW |
10640 | /* Skip trampolines. */ |
10641 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
10642 | ||
34e8f22d RE |
10643 | /* The stack grows downward. */ |
10644 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
10645 | ||
10646 | /* Breakpoint manipulation. */ | |
04180708 YQ |
10647 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
10648 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
10649 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
10650 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
10651 | |
10652 | /* Information about registers, etc. */ | |
34e8f22d RE |
10653 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
10654 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ecbf5d4f | 10655 | set_gdbarch_num_regs (gdbarch, register_count); |
7a5ea0d4 | 10656 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 10657 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 10658 | |
ff6f572f DJ |
10659 | /* This "info float" is FPA-specific. Use the generic version if we |
10660 | do not have FPA. */ | |
345bd07c | 10661 | if (tdep->have_fpa_registers) |
ff6f572f DJ |
10662 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
10663 | ||
26216b98 | 10664 | /* Internal <-> external register number maps. */ |
ff6f572f | 10665 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
10666 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
10667 | ||
34e8f22d RE |
10668 | set_gdbarch_register_name (gdbarch, arm_register_name); |
10669 | ||
10670 | /* Returning results. */ | |
2af48f68 | 10671 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 10672 | |
03d48a7d RE |
10673 | /* Disassembly. */ |
10674 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
10675 | ||
34e8f22d RE |
10676 | /* Minsymbol frobbing. */ |
10677 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
10678 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
10679 | arm_coff_make_msymbol_special); | |
60c5725c | 10680 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 10681 | |
f9d67f43 DJ |
10682 | /* Thumb-2 IT block support. */ |
10683 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
10684 | arm_adjust_breakpoint_address); | |
10685 | ||
0d5de010 DJ |
10686 | /* Virtual tables. */ |
10687 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
10688 | ||
97e03143 | 10689 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 10690 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 10691 | |
b39cc962 DJ |
10692 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
10693 | ||
eb5492fa | 10694 | /* Add some default predicates. */ |
2ae28aa9 YQ |
10695 | if (is_m) |
10696 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
10697 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
10698 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 10699 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 10700 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 10701 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 10702 | |
97e03143 RE |
10703 | /* Now we have tuned the configuration, set a few final things, |
10704 | based on what the OS ABI has told us. */ | |
10705 | ||
b8926edc DJ |
10706 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
10707 | binaries are always marked. */ | |
10708 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
10709 | tdep->arm_abi = ARM_ABI_APCS; | |
10710 | ||
e3039479 UW |
10711 | /* Watchpoints are not steppable. */ |
10712 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
10713 | ||
b8926edc DJ |
10714 | /* We used to default to FPA for generic ARM, but almost nobody |
10715 | uses that now, and we now provide a way for the user to force | |
10716 | the model. So default to the most useful variant. */ | |
10717 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
10718 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
10719 | ||
9df628e0 RE |
10720 | if (tdep->jb_pc >= 0) |
10721 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
10722 | ||
08216dd7 | 10723 | /* Floating point sizes and format. */ |
8da61cc4 | 10724 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 10725 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 10726 | { |
8da61cc4 DJ |
10727 | set_gdbarch_double_format |
10728 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10729 | set_gdbarch_long_double_format | |
10730 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10731 | } | |
10732 | else | |
10733 | { | |
10734 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
10735 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
10736 | } |
10737 | ||
a01567f4 LM |
10738 | /* Hook used to decorate frames with signed return addresses, only available |
10739 | for ARMv8.1-m PACBTI. */ | |
10740 | if (is_m && have_pacbti) | |
10741 | set_gdbarch_get_pc_address_flags (gdbarch, arm_get_pc_address_flags); | |
10742 | ||
dc22c61a LM |
10743 | if (tdesc_data != nullptr) |
10744 | { | |
10745 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
10746 | ||
10747 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
ecbf5d4f | 10748 | register_count = gdbarch_num_regs (gdbarch); |
dc22c61a LM |
10749 | |
10750 | /* Override tdesc_register_type to adjust the types of VFP | |
10751 | registers for NEON. */ | |
10752 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
10753 | } | |
10754 | ||
ecbf5d4f | 10755 | /* Initialize the pseudo register data. */ |
ae66a8f1 | 10756 | int num_pseudos = 0; |
ecbf5d4f | 10757 | if (tdep->have_s_pseudos) |
58d6951d | 10758 | { |
ecbf5d4f LM |
10759 | /* VFP single precision pseudo registers (S0~S31). */ |
10760 | tdep->s_pseudo_base = register_count; | |
10761 | tdep->s_pseudo_count = 32; | |
ae66a8f1 | 10762 | num_pseudos += tdep->s_pseudo_count; |
ecbf5d4f LM |
10763 | |
10764 | if (tdep->have_q_pseudos) | |
10765 | { | |
10766 | /* NEON quad precision pseudo registers (Q0~Q15). */ | |
10767 | tdep->q_pseudo_base = register_count + num_pseudos; | |
ae66a8f1 SP |
10768 | |
10769 | if (have_neon) | |
10770 | tdep->q_pseudo_count = 16; | |
10771 | else if (have_mve) | |
10772 | tdep->q_pseudo_count = ARM_MVE_NUM_Q_REGS; | |
10773 | ||
ecbf5d4f LM |
10774 | num_pseudos += tdep->q_pseudo_count; |
10775 | } | |
ae66a8f1 SP |
10776 | } |
10777 | ||
10778 | /* Do we have any MVE pseudo registers? */ | |
10779 | if (have_mve) | |
10780 | { | |
10781 | tdep->mve_pseudo_base = register_count + num_pseudos; | |
10782 | tdep->mve_pseudo_count = 1; | |
10783 | num_pseudos += tdep->mve_pseudo_count; | |
10784 | } | |
58d6951d | 10785 | |
a01567f4 LM |
10786 | /* Do we have any ARMv8.1-m PACBTI pseudo registers. */ |
10787 | if (have_pacbti) | |
10788 | { | |
10789 | tdep->pacbti_pseudo_base = register_count + num_pseudos; | |
10790 | tdep->pacbti_pseudo_count = 1; | |
10791 | num_pseudos += tdep->pacbti_pseudo_count; | |
10792 | } | |
10793 | ||
ae66a8f1 | 10794 | /* Set some pseudo register hooks, if we have pseudo registers. */ |
a01567f4 | 10795 | if (tdep->have_s_pseudos || have_mve || have_pacbti) |
ae66a8f1 | 10796 | { |
58d6951d DJ |
10797 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); |
10798 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
10799 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
10800 | } | |
10801 | ||
123dc839 | 10802 | /* Add standard register aliases. We add aliases even for those |
85102364 | 10803 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
10804 | and does no harm, since nothing ever lists user registers. */ |
10805 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
10806 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
10807 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
10808 | ||
65b48a81 PB |
10809 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
10810 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
10811 | ||
3426ae57 AH |
10812 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
10813 | ||
39bbf761 RE |
10814 | return gdbarch; |
10815 | } | |
10816 | ||
97e03143 | 10817 | static void |
2af46ca0 | 10818 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 10819 | { |
08106042 | 10820 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
97e03143 RE |
10821 | |
10822 | if (tdep == NULL) | |
10823 | return; | |
10824 | ||
6cb06a8c TT |
10825 | gdb_printf (file, _("arm_dump_tdep: fp_model = %i\n"), |
10826 | (int) tdep->fp_model); | |
10827 | gdb_printf (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
10828 | (int) tdep->have_fpa_registers); | |
10829 | gdb_printf (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
10830 | (int) tdep->have_wmmx_registers); | |
10831 | gdb_printf (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
10832 | (int) tdep->vfp_register_count); | |
10833 | gdb_printf (file, _("arm_dump_tdep: have_s_pseudos = %s\n"), | |
10834 | tdep->have_s_pseudos? "true" : "false"); | |
10835 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_base = %i\n"), | |
10836 | (int) tdep->s_pseudo_base); | |
10837 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_count = %i\n"), | |
10838 | (int) tdep->s_pseudo_count); | |
10839 | gdb_printf (file, _("arm_dump_tdep: have_q_pseudos = %s\n"), | |
10840 | tdep->have_q_pseudos? "true" : "false"); | |
10841 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_base = %i\n"), | |
10842 | (int) tdep->q_pseudo_base); | |
10843 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_count = %i\n"), | |
10844 | (int) tdep->q_pseudo_count); | |
10845 | gdb_printf (file, _("arm_dump_tdep: have_neon = %i\n"), | |
10846 | (int) tdep->have_neon); | |
10847 | gdb_printf (file, _("arm_dump_tdep: have_mve = %s\n"), | |
10848 | tdep->have_mve? "yes" : "no"); | |
10849 | gdb_printf (file, _("arm_dump_tdep: mve_vpr_regnum = %i\n"), | |
10850 | tdep->mve_vpr_regnum); | |
10851 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_base = %i\n"), | |
10852 | tdep->mve_pseudo_base); | |
10853 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_count = %i\n"), | |
10854 | tdep->mve_pseudo_count); | |
9074667a CL |
10855 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_regnum = %i\n"), |
10856 | tdep->m_profile_msp_regnum); | |
10857 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_regnum = %i\n"), | |
10858 | tdep->m_profile_psp_regnum); | |
ae7e2f45 CL |
10859 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"), |
10860 | tdep->m_profile_msp_ns_regnum); | |
10861 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"), | |
10862 | tdep->m_profile_psp_ns_regnum); | |
10863 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_s_regnum = %i\n"), | |
10864 | tdep->m_profile_msp_s_regnum); | |
10865 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_s_regnum = %i\n"), | |
10866 | tdep->m_profile_psp_s_regnum); | |
6cb06a8c TT |
10867 | gdb_printf (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), |
10868 | (unsigned long) tdep->lowest_pc); | |
a01567f4 LM |
10869 | gdb_printf (file, _("arm_dump_tdep: have_pacbti = %s\n"), |
10870 | tdep->have_pacbti? "yes" : "no"); | |
10871 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_base = %i\n"), | |
10872 | tdep->pacbti_pseudo_base); | |
10873 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_count = %i\n"), | |
10874 | tdep->pacbti_pseudo_count); | |
10875 | gdb_printf (file, _("arm_dump_tdep: is_m = %s\n"), | |
10876 | tdep->is_m? "yes" : "no"); | |
97e03143 RE |
10877 | } |
10878 | ||
0d4c07af | 10879 | #if GDB_SELF_TEST |
b121eeb9 YQ |
10880 | namespace selftests |
10881 | { | |
10882 | static void arm_record_test (void); | |
9ecab40c | 10883 | static void arm_analyze_prologue_test (); |
b121eeb9 | 10884 | } |
0d4c07af | 10885 | #endif |
b121eeb9 | 10886 | |
6c265988 | 10887 | void _initialize_arm_tdep (); |
c906108c | 10888 | void |
6c265988 | 10889 | _initialize_arm_tdep () |
c906108c | 10890 | { |
bc90b915 | 10891 | long length; |
65b48a81 | 10892 | int i, j; |
edefbb7c AC |
10893 | char regdesc[1024], *rdptr = regdesc; |
10894 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 10895 | |
42cf1509 | 10896 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 10897 | |
0e9e9abd | 10898 | /* Add ourselves to objfile event chain. */ |
c90e7d63 | 10899 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile, "arm-tdep"); |
0e9e9abd | 10900 | |
70f80edf JT |
10901 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
10902 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
10903 | bfd_target_elf_flavour, | |
10904 | arm_elf_osabi_sniffer); | |
10905 | ||
afd7eef0 | 10906 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
f54bdb6d SM |
10907 | add_setshow_prefix_cmd ("arm", no_class, |
10908 | _("Various ARM-specific commands."), | |
10909 | _("Various ARM-specific commands."), | |
10910 | &setarmcmdlist, &showarmcmdlist, | |
10911 | &setlist, &showlist); | |
c5aa993b | 10912 | |
65b48a81 | 10913 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
10914 | const disasm_options_t *disasm_options |
10915 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
10916 | int num_disassembly_styles = 0; |
10917 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10918 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10919 | num_disassembly_styles++; |
10920 | ||
10921 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 10922 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
10923 | num_disassembly_styles + 1); |
10924 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10925 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10926 | { |
10927 | size_t offset = strlen ("reg-names-"); | |
10928 | const char *style = disasm_options->name[i]; | |
10929 | valid_disassembly_styles[j++] = &style[offset]; | |
dedb7102 TT |
10930 | if (strcmp (&style[offset], "std") == 0) |
10931 | disassembly_style = &style[offset]; | |
65b48a81 PB |
10932 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], |
10933 | disasm_options->description[i]); | |
10934 | rdptr += length; | |
10935 | rest -= length; | |
10936 | } | |
94c30b78 | 10937 | /* Mark the end of valid options. */ |
65b48a81 | 10938 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 10939 | |
edefbb7c | 10940 | /* Create the help text. */ |
d7e74731 PA |
10941 | std::string helptext = string_printf ("%s%s%s", |
10942 | _("The valid values are:\n"), | |
10943 | regdesc, | |
10944 | _("The default is \"std\".")); | |
ed9a39eb | 10945 | |
edefbb7c AC |
10946 | add_setshow_enum_cmd("disassembler", no_class, |
10947 | valid_disassembly_styles, &disassembly_style, | |
10948 | _("Set the disassembly style."), | |
10949 | _("Show the disassembly style."), | |
09b0e4b0 | 10950 | helptext.c_str (), |
2c5b56ce | 10951 | set_disassembly_style_sfunc, |
65b48a81 | 10952 | show_disassembly_style_sfunc, |
7376b4c2 | 10953 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
10954 | |
10955 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
10956 | _("Set usage of ARM 32-bit mode."), | |
10957 | _("Show usage of ARM 32-bit mode."), | |
10958 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 10959 | NULL, |
0963b4bd MS |
10960 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
10961 | mode is %s. */ | |
26304000 | 10962 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 10963 | |
fd50bc42 | 10964 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
10965 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
10966 | _("Set the floating point type."), | |
10967 | _("Show the floating point type."), | |
10968 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
10969 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
10970 | fpa - FPA co-processor (GCC compiled).\n\ | |
10971 | softvfp - Software FP with pure-endian doubles.\n\ | |
10972 | vfp - VFP co-processor."), | |
edefbb7c | 10973 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 10974 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 10975 | |
28e97307 DJ |
10976 | /* Add a command to allow the user to force the ABI. */ |
10977 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
10978 | _("Set the ABI."), | |
10979 | _("Show the ABI."), | |
10980 | NULL, arm_set_abi, arm_show_abi, | |
10981 | &setarmcmdlist, &showarmcmdlist); | |
10982 | ||
0428b8f5 DJ |
10983 | /* Add two commands to allow the user to force the assumed |
10984 | execution mode. */ | |
10985 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
10986 | arm_mode_strings, &arm_fallback_mode_string, | |
10987 | _("Set the mode assumed when symbols are unavailable."), | |
10988 | _("Show the mode assumed when symbols are unavailable."), | |
10989 | NULL, NULL, arm_show_fallback_mode, | |
10990 | &setarmcmdlist, &showarmcmdlist); | |
10991 | add_setshow_enum_cmd ("force-mode", class_support, | |
10992 | arm_mode_strings, &arm_force_mode_string, | |
10993 | _("Set the mode assumed even when symbols are available."), | |
10994 | _("Show the mode assumed even when symbols are available."), | |
10995 | NULL, NULL, arm_show_force_mode, | |
10996 | &setarmcmdlist, &showarmcmdlist); | |
10997 | ||
ef273377 CL |
10998 | /* Add a command to stop triggering security exceptions when |
10999 | unwinding exception stacks. */ | |
11000 | add_setshow_boolean_cmd ("unwind-secure-frames", no_class, &arm_unwind_secure_frames, | |
11001 | _("Set usage of non-secure to secure exception stack unwinding."), | |
11002 | _("Show usage of non-secure to secure exception stack unwinding."), | |
11003 | _("When on, the debugger can trigger memory access traps."), | |
11004 | NULL, arm_show_unwind_secure_frames, | |
11005 | &setarmcmdlist, &showarmcmdlist); | |
11006 | ||
6529d2dd | 11007 | /* Debugging flag. */ |
edefbb7c AC |
11008 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
11009 | _("Set ARM debugging."), | |
11010 | _("Show ARM debugging."), | |
11011 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 11012 | NULL, |
7915a72c | 11013 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 11014 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
11015 | |
11016 | #if GDB_SELF_TEST | |
1526853e | 11017 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 11018 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
11019 | #endif |
11020 | ||
c906108c | 11021 | } |
72508ac0 PO |
11022 | |
11023 | /* ARM-reversible process record data structures. */ | |
11024 | ||
11025 | #define ARM_INSN_SIZE_BYTES 4 | |
11026 | #define THUMB_INSN_SIZE_BYTES 2 | |
11027 | #define THUMB2_INSN_SIZE_BYTES 4 | |
11028 | ||
11029 | ||
71e396f9 LM |
11030 | /* Position of the bit within a 32-bit ARM instruction |
11031 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
11032 | #define INSN_S_L_BIT_NUM 20 |
11033 | ||
11034 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
11035 | do \ |
11036 | { \ | |
11037 | unsigned int reg_len = LENGTH; \ | |
11038 | if (reg_len) \ | |
11039 | { \ | |
11040 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
11041 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
11042 | } \ | |
11043 | } \ | |
11044 | while (0) | |
72508ac0 PO |
11045 | |
11046 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
11047 | do \ |
11048 | { \ | |
11049 | unsigned int mem_len = LENGTH; \ | |
11050 | if (mem_len) \ | |
01add95b SM |
11051 | { \ |
11052 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
11053 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
11054 | sizeof(struct arm_mem_r) * LENGTH); \ | |
11055 | } \ | |
dda83cd7 SM |
11056 | } \ |
11057 | while (0) | |
72508ac0 PO |
11058 | |
11059 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
11060 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 11061 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
11062 | |
11063 | /* ARM memory record structure. */ | |
11064 | struct arm_mem_r | |
11065 | { | |
11066 | uint32_t len; /* Record length. */ | |
bfbbec00 | 11067 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
11068 | }; |
11069 | ||
11070 | /* ARM instruction record contains opcode of current insn | |
11071 | and execution state (before entry to decode_insn()), | |
11072 | contains list of to-be-modified registers and | |
11073 | memory blocks (on return from decode_insn()). */ | |
11074 | ||
4748a9be | 11075 | struct arm_insn_decode_record |
72508ac0 PO |
11076 | { |
11077 | struct gdbarch *gdbarch; | |
11078 | struct regcache *regcache; | |
11079 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
11080 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
11081 | uint32_t cond; /* Condition code. */ | |
11082 | uint32_t opcode; /* Insn opcode. */ | |
11083 | uint32_t decode; /* Insn decode bits. */ | |
11084 | uint32_t mem_rec_count; /* No of mem records. */ | |
11085 | uint32_t reg_rec_count; /* No of reg records. */ | |
11086 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
11087 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
4748a9be | 11088 | }; |
72508ac0 PO |
11089 | |
11090 | ||
11091 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
11092 | ||
11093 | static int | |
11094 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
11095 | { | |
11096 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
11097 | ||
11098 | if (!len) | |
11099 | return 1; | |
11100 | ||
11101 | if (!sbo) | |
11102 | ones = ~ones; | |
11103 | ||
11104 | while (ones) | |
11105 | { | |
11106 | if (!(ones & sbo)) | |
dda83cd7 SM |
11107 | { |
11108 | return 0; | |
11109 | } | |
72508ac0 PO |
11110 | ones = ones >> 1; |
11111 | } | |
11112 | return 1; | |
11113 | } | |
11114 | ||
c6ec2b30 OJ |
11115 | enum arm_record_result |
11116 | { | |
11117 | ARM_RECORD_SUCCESS = 0, | |
11118 | ARM_RECORD_FAILURE = 1 | |
11119 | }; | |
11120 | ||
0d1703b8 | 11121 | enum arm_record_strx_t |
72508ac0 PO |
11122 | { |
11123 | ARM_RECORD_STRH=1, | |
11124 | ARM_RECORD_STRD | |
0d1703b8 | 11125 | }; |
72508ac0 | 11126 | |
0d1703b8 | 11127 | enum record_type_t |
72508ac0 PO |
11128 | { |
11129 | ARM_RECORD=1, | |
11130 | THUMB_RECORD, | |
11131 | THUMB2_RECORD | |
0d1703b8 | 11132 | }; |
72508ac0 PO |
11133 | |
11134 | ||
11135 | static int | |
4748a9be | 11136 | arm_record_strx (arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, |
dda83cd7 | 11137 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
11138 | { |
11139 | ||
11140 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11141 | ULONGEST u_regval[2]= {0}; | |
11142 | ||
11143 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
11144 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
11145 | |
11146 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11147 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
11148 | |
11149 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11150 | { | |
11151 | /* 1) Handle misc store, immediate offset. */ | |
11152 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
11153 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
11154 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11155 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 11156 | &u_regval[0]); |
72508ac0 | 11157 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
11158 | { |
11159 | /* If R15 was used as Rn, hence current PC+8. */ | |
11160 | u_regval[0] = u_regval[0] + 8; | |
11161 | } | |
72508ac0 PO |
11162 | offset_8 = (immed_high << 4) | immed_low; |
11163 | /* Calculate target store address. */ | |
11164 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
11165 | { |
11166 | tgt_mem_addr = u_regval[0] + offset_8; | |
11167 | } | |
72508ac0 | 11168 | else |
dda83cd7 SM |
11169 | { |
11170 | tgt_mem_addr = u_regval[0] - offset_8; | |
11171 | } | |
72508ac0 | 11172 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11173 | { |
11174 | record_buf_mem[0] = 2; | |
11175 | record_buf_mem[1] = tgt_mem_addr; | |
11176 | arm_insn_r->mem_rec_count = 1; | |
11177 | } | |
72508ac0 | 11178 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11179 | { |
11180 | record_buf_mem[0] = 4; | |
11181 | record_buf_mem[1] = tgt_mem_addr; | |
11182 | record_buf_mem[2] = 4; | |
11183 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11184 | arm_insn_r->mem_rec_count = 2; | |
11185 | } | |
72508ac0 PO |
11186 | } |
11187 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
11188 | { | |
11189 | /* 2) Store, register offset. */ | |
11190 | /* Get Rm. */ | |
11191 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11192 | /* Get Rn. */ | |
11193 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11194 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11195 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11196 | if (15 == reg_src2) | |
dda83cd7 SM |
11197 | { |
11198 | /* If R15 was used as Rn, hence current PC+8. */ | |
11199 | u_regval[0] = u_regval[0] + 8; | |
11200 | } | |
72508ac0 PO |
11201 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
11202 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
11203 | { |
11204 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11205 | } | |
72508ac0 | 11206 | else |
dda83cd7 SM |
11207 | { |
11208 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11209 | } | |
72508ac0 | 11210 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11211 | { |
11212 | record_buf_mem[0] = 2; | |
11213 | record_buf_mem[1] = tgt_mem_addr; | |
11214 | arm_insn_r->mem_rec_count = 1; | |
11215 | } | |
72508ac0 | 11216 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11217 | { |
11218 | record_buf_mem[0] = 4; | |
11219 | record_buf_mem[1] = tgt_mem_addr; | |
11220 | record_buf_mem[2] = 4; | |
11221 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11222 | arm_insn_r->mem_rec_count = 2; | |
11223 | } | |
72508ac0 PO |
11224 | } |
11225 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 11226 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
11227 | { |
11228 | /* 3) Store, immediate pre-indexed. */ | |
11229 | /* 5) Store, immediate post-indexed. */ | |
11230 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
11231 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
11232 | offset_8 = (immed_high << 4) | immed_low; | |
11233 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11234 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11235 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11236 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
11237 | { |
11238 | tgt_mem_addr = u_regval[0] + offset_8; | |
11239 | } | |
72508ac0 | 11240 | else |
dda83cd7 SM |
11241 | { |
11242 | tgt_mem_addr = u_regval[0] - offset_8; | |
11243 | } | |
72508ac0 | 11244 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11245 | { |
11246 | record_buf_mem[0] = 2; | |
11247 | record_buf_mem[1] = tgt_mem_addr; | |
11248 | arm_insn_r->mem_rec_count = 1; | |
11249 | } | |
72508ac0 | 11250 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11251 | { |
11252 | record_buf_mem[0] = 4; | |
11253 | record_buf_mem[1] = tgt_mem_addr; | |
11254 | record_buf_mem[2] = 4; | |
11255 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11256 | arm_insn_r->mem_rec_count = 2; | |
11257 | } | |
72508ac0 PO |
11258 | /* Record Rn also as it changes. */ |
11259 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11260 | arm_insn_r->reg_rec_count = 1; | |
11261 | } | |
11262 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 11263 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
11264 | { |
11265 | /* 4) Store, register pre-indexed. */ | |
11266 | /* 6) Store, register post -indexed. */ | |
11267 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11268 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11269 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11270 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11271 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11272 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
11273 | { |
11274 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11275 | } | |
72508ac0 | 11276 | else |
dda83cd7 SM |
11277 | { |
11278 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11279 | } | |
72508ac0 | 11280 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11281 | { |
11282 | record_buf_mem[0] = 2; | |
11283 | record_buf_mem[1] = tgt_mem_addr; | |
11284 | arm_insn_r->mem_rec_count = 1; | |
11285 | } | |
72508ac0 | 11286 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11287 | { |
11288 | record_buf_mem[0] = 4; | |
11289 | record_buf_mem[1] = tgt_mem_addr; | |
11290 | record_buf_mem[2] = 4; | |
11291 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11292 | arm_insn_r->mem_rec_count = 2; | |
11293 | } | |
72508ac0 PO |
11294 | /* Record Rn also as it changes. */ |
11295 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11296 | arm_insn_r->reg_rec_count = 1; | |
11297 | } | |
11298 | return 0; | |
11299 | } | |
11300 | ||
11301 | /* Handling ARM extension space insns. */ | |
11302 | ||
11303 | static int | |
4748a9be | 11304 | arm_record_extension_space (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 11305 | { |
df95a9cf | 11306 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
11307 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
11308 | uint32_t record_buf[8], record_buf_mem[8]; | |
11309 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
11310 | struct regcache *reg_cache = arm_insn_r->regcache; |
11311 | ULONGEST u_regval = 0; | |
11312 | ||
11313 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
11314 | /* Handle unconditional insn extension space. */ | |
11315 | ||
11316 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
11317 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11318 | if (arm_insn_r->cond) | |
11319 | { | |
11320 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 11321 | the caches. */ |
72508ac0 | 11322 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
11323 | { |
11324 | /* BLX(1) */ | |
11325 | record_buf[0] = ARM_PS_REGNUM; | |
11326 | record_buf[1] = ARM_LR_REGNUM; | |
11327 | arm_insn_r->reg_rec_count = 2; | |
11328 | } | |
72508ac0 PO |
11329 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
11330 | } | |
11331 | ||
11332 | ||
11333 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11334 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
11335 | { | |
11336 | ret = -1; | |
11337 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 11338 | versions define it. */ |
72508ac0 PO |
11339 | } |
11340 | ||
11341 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
11342 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11343 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11344 | ||
11345 | /* Handle arithmetic insn extension space. */ | |
11346 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
11347 | && !INSN_RECORDED(arm_insn_r)) | |
11348 | { | |
11349 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 11350 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
01add95b SM |
11351 | { |
11352 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11353 | record_buf[1] = ARM_PS_REGNUM; | |
11354 | arm_insn_r->reg_rec_count = 2; | |
11355 | } | |
b020ff80 | 11356 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
01add95b SM |
11357 | { |
11358 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
11359 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11360 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11361 | record_buf[2] = ARM_PS_REGNUM; | |
11362 | arm_insn_r->reg_rec_count = 3; | |
11363 | } | |
72508ac0 PO |
11364 | } |
11365 | ||
11366 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
11367 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
11368 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
11369 | ||
11370 | /* Handle control insn extension space. */ | |
11371 | ||
11372 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
11373 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
11374 | { | |
11375 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
11376 | { |
11377 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
11378 | { | |
11379 | if ((0 == insn_op1) || (2 == insn_op1)) | |
11380 | { | |
11381 | /* MRS. */ | |
11382 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11383 | arm_insn_r->reg_rec_count = 1; | |
11384 | } | |
11385 | else if (1 == insn_op1) | |
11386 | { | |
11387 | /* CSPR is going to be changed. */ | |
11388 | record_buf[0] = ARM_PS_REGNUM; | |
11389 | arm_insn_r->reg_rec_count = 1; | |
11390 | } | |
11391 | else if (3 == insn_op1) | |
11392 | { | |
11393 | /* SPSR is going to be changed. */ | |
11394 | /* We need to get SPSR value, which is yet to be done. */ | |
11395 | return -1; | |
11396 | } | |
11397 | } | |
11398 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11399 | { | |
11400 | if (1 == insn_op1) | |
11401 | { | |
11402 | /* BX. */ | |
11403 | record_buf[0] = ARM_PS_REGNUM; | |
11404 | arm_insn_r->reg_rec_count = 1; | |
11405 | } | |
11406 | else if (3 == insn_op1) | |
11407 | { | |
11408 | /* CLZ. */ | |
11409 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11410 | arm_insn_r->reg_rec_count = 1; | |
11411 | } | |
11412 | } | |
11413 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11414 | { | |
11415 | /* BLX. */ | |
11416 | record_buf[0] = ARM_PS_REGNUM; | |
11417 | record_buf[1] = ARM_LR_REGNUM; | |
11418 | arm_insn_r->reg_rec_count = 2; | |
11419 | } | |
11420 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11421 | { | |
11422 | /* QADD, QSUB, QDADD, QDSUB */ | |
11423 | record_buf[0] = ARM_PS_REGNUM; | |
11424 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11425 | arm_insn_r->reg_rec_count = 2; | |
11426 | } | |
11427 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11428 | { | |
11429 | /* BKPT. */ | |
11430 | record_buf[0] = ARM_PS_REGNUM; | |
11431 | record_buf[1] = ARM_LR_REGNUM; | |
11432 | arm_insn_r->reg_rec_count = 2; | |
11433 | ||
11434 | /* Save SPSR also;how? */ | |
11435 | return -1; | |
11436 | } | |
11437 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
11438 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
11439 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
11440 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
11441 | ) | |
11442 | { | |
11443 | if (0 == insn_op1 || 1 == insn_op1) | |
11444 | { | |
11445 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
11446 | /* We dont do optimization for SMULW<y> where we | |
11447 | need only Rd. */ | |
11448 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11449 | record_buf[1] = ARM_PS_REGNUM; | |
11450 | arm_insn_r->reg_rec_count = 2; | |
11451 | } | |
11452 | else if (2 == insn_op1) | |
11453 | { | |
11454 | /* SMLAL<x><y>. */ | |
11455 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11456 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11457 | arm_insn_r->reg_rec_count = 2; | |
11458 | } | |
11459 | else if (3 == insn_op1) | |
11460 | { | |
11461 | /* SMUL<x><y>. */ | |
11462 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11463 | arm_insn_r->reg_rec_count = 1; | |
11464 | } | |
11465 | } | |
11466 | } | |
72508ac0 | 11467 | else |
dda83cd7 SM |
11468 | { |
11469 | /* MSR : immediate form. */ | |
11470 | if (1 == insn_op1) | |
11471 | { | |
11472 | /* CSPR is going to be changed. */ | |
11473 | record_buf[0] = ARM_PS_REGNUM; | |
11474 | arm_insn_r->reg_rec_count = 1; | |
11475 | } | |
11476 | else if (3 == insn_op1) | |
11477 | { | |
11478 | /* SPSR is going to be changed. */ | |
11479 | /* we need to get SPSR value, which is yet to be done */ | |
11480 | return -1; | |
11481 | } | |
11482 | } | |
72508ac0 PO |
11483 | } |
11484 | ||
11485 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11486 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
11487 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
11488 | ||
11489 | /* Handle load/store insn extension space. */ | |
11490 | ||
11491 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
11492 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
11493 | && !INSN_RECORDED(arm_insn_r)) | |
11494 | { | |
11495 | /* SWP/SWPB. */ | |
11496 | if (0 == insn_op1) | |
dda83cd7 SM |
11497 | { |
11498 | /* These insn, changes register and memory as well. */ | |
11499 | /* SWP or SWPB insn. */ | |
11500 | /* Get memory address given by Rn. */ | |
11501 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11502 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11503 | /* SWP insn ?, swaps word. */ | |
11504 | if (8 == arm_insn_r->opcode) | |
11505 | { | |
11506 | record_buf_mem[0] = 4; | |
11507 | } | |
11508 | else | |
11509 | { | |
11510 | /* SWPB insn, swaps only byte. */ | |
11511 | record_buf_mem[0] = 1; | |
11512 | } | |
11513 | record_buf_mem[1] = u_regval; | |
11514 | arm_insn_r->mem_rec_count = 1; | |
11515 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11516 | arm_insn_r->reg_rec_count = 1; | |
11517 | } | |
72508ac0 | 11518 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11519 | { |
11520 | /* STRH. */ | |
11521 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11522 | ARM_RECORD_STRH); | |
11523 | } | |
72508ac0 | 11524 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11525 | { |
11526 | /* LDRD. */ | |
11527 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11528 | record_buf[1] = record_buf[0] + 1; | |
11529 | arm_insn_r->reg_rec_count = 2; | |
11530 | } | |
72508ac0 | 11531 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11532 | { |
11533 | /* STRD. */ | |
11534 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11535 | ARM_RECORD_STRD); | |
11536 | } | |
72508ac0 | 11537 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
11538 | { |
11539 | /* LDRH, LDRSB, LDRSH. */ | |
11540 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11541 | arm_insn_r->reg_rec_count = 1; | |
11542 | } | |
72508ac0 PO |
11543 | |
11544 | } | |
11545 | ||
11546 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
11547 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
11548 | && !INSN_RECORDED(arm_insn_r)) | |
11549 | { | |
11550 | ret = -1; | |
11551 | /* Handle coprocessor insn extension space. */ | |
11552 | } | |
11553 | ||
11554 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
11555 | if (-1 == ret) | |
ca92db2d | 11556 | return ret; |
72508ac0 PO |
11557 | |
11558 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11559 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11560 | ||
11561 | return ret; | |
11562 | } | |
11563 | ||
11564 | /* Handling opcode 000 insns. */ | |
11565 | ||
11566 | static int | |
4748a9be | 11567 | arm_record_data_proc_misc_ld_str (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11568 | { |
11569 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11570 | uint32_t record_buf[8], record_buf_mem[8]; | |
11571 | ULONGEST u_regval[2] = {0}; | |
11572 | ||
8d49165d | 11573 | uint32_t reg_src1 = 0; |
72508ac0 PO |
11574 | uint32_t opcode1 = 0; |
11575 | ||
11576 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11577 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11578 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
11579 | ||
2d9e6acb | 11580 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11581 | { |
2d9e6acb YQ |
11582 | /* Data-processing (register) and Data-processing (register-shifted |
11583 | register */ | |
11584 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
11585 | register, which is specified by 13-16 decode. */ | |
11586 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11587 | record_buf[1] = ARM_PS_REGNUM; | |
11588 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 11589 | } |
2d9e6acb | 11590 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11591 | { |
2d9e6acb YQ |
11592 | /* Miscellaneous instructions */ |
11593 | ||
11594 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
11595 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11596 | { | |
11597 | /* Handle BLX, branch and link/exchange. */ | |
11598 | if (9 == arm_insn_r->opcode) | |
11599 | { | |
11600 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
11601 | and R14 stores the return address. */ | |
11602 | record_buf[0] = ARM_PS_REGNUM; | |
11603 | record_buf[1] = ARM_LR_REGNUM; | |
11604 | arm_insn_r->reg_rec_count = 2; | |
11605 | } | |
11606 | } | |
11607 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
11608 | { | |
11609 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
11610 | /* CPSR is changed to be executed in ARM state, disabling normal | |
11611 | interrupts, entering abort mode. */ | |
11612 | /* According to high vector configuration PC is set. */ | |
11613 | /* user hit breakpoint and type reverse, in | |
11614 | that case, we need to go back with previous CPSR and | |
11615 | Program Counter. */ | |
11616 | record_buf[0] = ARM_PS_REGNUM; | |
11617 | record_buf[1] = ARM_LR_REGNUM; | |
11618 | arm_insn_r->reg_rec_count = 2; | |
11619 | ||
11620 | /* Save SPSR also; how? */ | |
11621 | return -1; | |
11622 | } | |
11623 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
11624 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11625 | { | |
11626 | /* Handle BX, branch and link/exchange. */ | |
11627 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
11628 | record_buf[0] = ARM_PS_REGNUM; | |
11629 | arm_insn_r->reg_rec_count = 1; | |
11630 | } | |
11631 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
11632 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
11633 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
11634 | { | |
11635 | /* Count leading zeros: CLZ. */ | |
11636 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11637 | arm_insn_r->reg_rec_count = 1; | |
11638 | } | |
11639 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
11640 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11641 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
11642 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
11643 | { | |
11644 | /* Handle MRS insn. */ | |
11645 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11646 | arm_insn_r->reg_rec_count = 1; | |
11647 | } | |
72508ac0 | 11648 | } |
2d9e6acb | 11649 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 11650 | { |
2d9e6acb YQ |
11651 | /* Multiply and multiply-accumulate */ |
11652 | ||
11653 | /* Handle multiply instructions. */ | |
11654 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
11655 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
f2a883a8 SM |
11656 | { |
11657 | /* Handle MLA and MUL. */ | |
11658 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11659 | record_buf[1] = ARM_PS_REGNUM; | |
11660 | arm_insn_r->reg_rec_count = 2; | |
11661 | } | |
11662 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
11663 | { | |
11664 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
11665 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11666 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11667 | record_buf[2] = ARM_PS_REGNUM; | |
11668 | arm_insn_r->reg_rec_count = 3; | |
11669 | } | |
2d9e6acb YQ |
11670 | } |
11671 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
11672 | { | |
11673 | /* Synchronization primitives */ | |
11674 | ||
72508ac0 PO |
11675 | /* Handling SWP, SWPB. */ |
11676 | /* These insn, changes register and memory as well. */ | |
11677 | /* SWP or SWPB insn. */ | |
11678 | ||
11679 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11680 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11681 | /* SWP insn ?, swaps word. */ | |
11682 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
11683 | { |
11684 | record_buf_mem[0] = 4; | |
11685 | } | |
11686 | else | |
11687 | { | |
11688 | /* SWPB insn, swaps only byte. */ | |
11689 | record_buf_mem[0] = 1; | |
11690 | } | |
72508ac0 PO |
11691 | record_buf_mem[1] = u_regval[0]; |
11692 | arm_insn_r->mem_rec_count = 1; | |
11693 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11694 | arm_insn_r->reg_rec_count = 1; | |
11695 | } | |
2d9e6acb YQ |
11696 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
11697 | || 15 == arm_insn_r->decode) | |
72508ac0 | 11698 | { |
2d9e6acb YQ |
11699 | if ((opcode1 & 0x12) == 2) |
11700 | { | |
11701 | /* Extra load/store (unprivileged) */ | |
11702 | return -1; | |
11703 | } | |
11704 | else | |
11705 | { | |
11706 | /* Extra load/store */ | |
11707 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
11708 | { | |
11709 | case 1: | |
11710 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
11711 | { | |
11712 | /* STRH (register), STRH (immediate) */ | |
11713 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11714 | &record_buf_mem[0], ARM_RECORD_STRH); | |
11715 | } | |
11716 | else if ((opcode1 & 0x05) == 0x1) | |
11717 | { | |
11718 | /* LDRH (register) */ | |
11719 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11720 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 11721 | |
2d9e6acb YQ |
11722 | if (bit (arm_insn_r->arm_insn, 21)) |
11723 | { | |
11724 | /* Write back to Rn. */ | |
11725 | record_buf[arm_insn_r->reg_rec_count++] | |
11726 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11727 | } | |
11728 | } | |
11729 | else if ((opcode1 & 0x05) == 0x5) | |
11730 | { | |
11731 | /* LDRH (immediate), LDRH (literal) */ | |
11732 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11733 | |
2d9e6acb YQ |
11734 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11735 | arm_insn_r->reg_rec_count = 1; | |
11736 | ||
11737 | if (rn != 15) | |
11738 | { | |
11739 | /*LDRH (immediate) */ | |
11740 | if (bit (arm_insn_r->arm_insn, 21)) | |
11741 | { | |
11742 | /* Write back to Rn. */ | |
11743 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11744 | } | |
11745 | } | |
11746 | } | |
11747 | else | |
11748 | return -1; | |
11749 | break; | |
11750 | case 2: | |
11751 | if ((opcode1 & 0x05) == 0x0) | |
11752 | { | |
11753 | /* LDRD (register) */ | |
11754 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11755 | record_buf[1] = record_buf[0] + 1; | |
11756 | arm_insn_r->reg_rec_count = 2; | |
11757 | ||
11758 | if (bit (arm_insn_r->arm_insn, 21)) | |
11759 | { | |
11760 | /* Write back to Rn. */ | |
11761 | record_buf[arm_insn_r->reg_rec_count++] | |
11762 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11763 | } | |
11764 | } | |
11765 | else if ((opcode1 & 0x05) == 0x1) | |
11766 | { | |
11767 | /* LDRSB (register) */ | |
11768 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11769 | arm_insn_r->reg_rec_count = 1; | |
11770 | ||
11771 | if (bit (arm_insn_r->arm_insn, 21)) | |
11772 | { | |
11773 | /* Write back to Rn. */ | |
11774 | record_buf[arm_insn_r->reg_rec_count++] | |
11775 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11776 | } | |
11777 | } | |
11778 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
11779 | { | |
11780 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
11781 | LDRSB (literal) */ | |
11782 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11783 | ||
11784 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11785 | arm_insn_r->reg_rec_count = 1; | |
11786 | ||
11787 | if (rn != 15) | |
11788 | { | |
11789 | /*LDRD (immediate), LDRSB (immediate) */ | |
11790 | if (bit (arm_insn_r->arm_insn, 21)) | |
11791 | { | |
11792 | /* Write back to Rn. */ | |
11793 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11794 | } | |
11795 | } | |
11796 | } | |
11797 | else | |
11798 | return -1; | |
11799 | break; | |
11800 | case 3: | |
11801 | if ((opcode1 & 0x05) == 0x0) | |
11802 | { | |
11803 | /* STRD (register) */ | |
11804 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11805 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11806 | } | |
11807 | else if ((opcode1 & 0x05) == 0x1) | |
11808 | { | |
11809 | /* LDRSH (register) */ | |
11810 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11811 | arm_insn_r->reg_rec_count = 1; | |
11812 | ||
11813 | if (bit (arm_insn_r->arm_insn, 21)) | |
11814 | { | |
11815 | /* Write back to Rn. */ | |
11816 | record_buf[arm_insn_r->reg_rec_count++] | |
11817 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11818 | } | |
11819 | } | |
11820 | else if ((opcode1 & 0x05) == 0x4) | |
11821 | { | |
11822 | /* STRD (immediate) */ | |
11823 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11824 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11825 | } | |
11826 | else if ((opcode1 & 0x05) == 0x5) | |
11827 | { | |
11828 | /* LDRSH (immediate), LDRSH (literal) */ | |
11829 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11830 | arm_insn_r->reg_rec_count = 1; | |
11831 | ||
11832 | if (bit (arm_insn_r->arm_insn, 21)) | |
11833 | { | |
11834 | /* Write back to Rn. */ | |
11835 | record_buf[arm_insn_r->reg_rec_count++] | |
11836 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11837 | } | |
11838 | } | |
11839 | else | |
11840 | return -1; | |
11841 | break; | |
11842 | default: | |
11843 | return -1; | |
11844 | } | |
11845 | } | |
72508ac0 PO |
11846 | } |
11847 | else | |
11848 | { | |
11849 | return -1; | |
11850 | } | |
11851 | ||
11852 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11853 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11854 | return 0; | |
11855 | } | |
11856 | ||
11857 | /* Handling opcode 001 insns. */ | |
11858 | ||
11859 | static int | |
4748a9be | 11860 | arm_record_data_proc_imm (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11861 | { |
11862 | uint32_t record_buf[8], record_buf_mem[8]; | |
11863 | ||
11864 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11865 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11866 | ||
11867 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
11868 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
11869 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
11870 | ) | |
11871 | { | |
11872 | /* Handle MSR insn. */ | |
11873 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
11874 | { |
11875 | /* CSPR is going to be changed. */ | |
11876 | record_buf[0] = ARM_PS_REGNUM; | |
11877 | arm_insn_r->reg_rec_count = 1; | |
11878 | } | |
72508ac0 | 11879 | else |
dda83cd7 SM |
11880 | { |
11881 | /* SPSR is going to be changed. */ | |
11882 | } | |
72508ac0 PO |
11883 | } |
11884 | else if (arm_insn_r->opcode <= 15) | |
11885 | { | |
11886 | /* Normal data processing insns. */ | |
11887 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 11888 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
11889 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11890 | record_buf[1] = ARM_PS_REGNUM; | |
11891 | arm_insn_r->reg_rec_count = 2; | |
11892 | } | |
11893 | else | |
11894 | { | |
11895 | return -1; | |
11896 | } | |
11897 | ||
11898 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11899 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11900 | return 0; | |
11901 | } | |
11902 | ||
c55978a6 | 11903 | static int |
4748a9be | 11904 | arm_record_media (arm_insn_decode_record *arm_insn_r) |
c55978a6 YQ |
11905 | { |
11906 | uint32_t record_buf[8]; | |
11907 | ||
11908 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
11909 | { | |
11910 | case 0: | |
11911 | /* Parallel addition and subtraction, signed */ | |
11912 | case 1: | |
11913 | /* Parallel addition and subtraction, unsigned */ | |
11914 | case 2: | |
11915 | case 3: | |
11916 | /* Packing, unpacking, saturation and reversal */ | |
11917 | { | |
11918 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
11919 | ||
11920 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11921 | } | |
11922 | break; | |
11923 | ||
11924 | case 4: | |
11925 | case 5: | |
11926 | /* Signed multiplies */ | |
11927 | { | |
11928 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
11929 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
11930 | ||
11931 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11932 | if (op1 == 0x0) | |
11933 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11934 | else if (op1 == 0x4) | |
11935 | record_buf[arm_insn_r->reg_rec_count++] | |
11936 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11937 | } | |
11938 | break; | |
11939 | ||
11940 | case 6: | |
11941 | { | |
11942 | if (bit (arm_insn_r->arm_insn, 21) | |
11943 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
11944 | { | |
11945 | /* SBFX */ | |
11946 | record_buf[arm_insn_r->reg_rec_count++] | |
11947 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11948 | } | |
11949 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
11950 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
11951 | { | |
11952 | /* USAD8 and USADA8 */ | |
11953 | record_buf[arm_insn_r->reg_rec_count++] | |
11954 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11955 | } | |
11956 | } | |
11957 | break; | |
11958 | ||
11959 | case 7: | |
11960 | { | |
11961 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
11962 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
11963 | { | |
11964 | /* Permanently UNDEFINED */ | |
11965 | return -1; | |
11966 | } | |
11967 | else | |
11968 | { | |
11969 | /* BFC, BFI and UBFX */ | |
11970 | record_buf[arm_insn_r->reg_rec_count++] | |
11971 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11972 | } | |
11973 | } | |
11974 | break; | |
11975 | ||
11976 | default: | |
11977 | return -1; | |
11978 | } | |
11979 | ||
11980 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11981 | ||
11982 | return 0; | |
11983 | } | |
11984 | ||
71e396f9 | 11985 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
11986 | |
11987 | static int | |
4748a9be | 11988 | arm_record_ld_st_imm_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11989 | { |
11990 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11991 | ||
71e396f9 LM |
11992 | uint32_t reg_base , reg_dest; |
11993 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 11994 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
11995 | unsigned char wback; |
11996 | ULONGEST u_regval; | |
72508ac0 | 11997 | |
71e396f9 LM |
11998 | /* Calculate wback. */ |
11999 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
12000 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 12001 | |
71e396f9 LM |
12002 | arm_insn_r->reg_rec_count = 0; |
12003 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
12004 | |
12005 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12006 | { | |
71e396f9 LM |
12007 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
12008 | and LDRT. */ | |
12009 | ||
72508ac0 | 12010 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
12011 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
12012 | ||
12013 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
12014 | preceeds a LDR instruction having R15 as reg_base, it | |
12015 | emulates a branch and link instruction, and hence we need to save | |
12016 | CPSR and PC as well. */ | |
12017 | if (ARM_PC_REGNUM == reg_dest) | |
12018 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
12019 | ||
12020 | /* If wback is true, also save the base register, which is going to be | |
12021 | written to. */ | |
12022 | if (wback) | |
12023 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
12024 | } |
12025 | else | |
12026 | { | |
71e396f9 LM |
12027 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
12028 | ||
72508ac0 | 12029 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
12030 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
12031 | ||
12032 | /* Handle bit U. */ | |
72508ac0 | 12033 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
12034 | { |
12035 | /* U == 1: Add the offset. */ | |
12036 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
12037 | } | |
72508ac0 | 12038 | else |
71e396f9 LM |
12039 | { |
12040 | /* U == 0: subtract the offset. */ | |
12041 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
12042 | } | |
12043 | ||
12044 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
12045 | bytes. */ | |
12046 | if (bit (arm_insn_r->arm_insn, 22)) | |
12047 | { | |
12048 | /* STRB and STRBT: 1 byte. */ | |
12049 | record_buf_mem[0] = 1; | |
12050 | } | |
12051 | else | |
12052 | { | |
12053 | /* STR and STRT: 4 bytes. */ | |
12054 | record_buf_mem[0] = 4; | |
12055 | } | |
12056 | ||
12057 | /* Handle bit P. */ | |
12058 | if (bit (arm_insn_r->arm_insn, 24)) | |
12059 | record_buf_mem[1] = tgt_mem_addr; | |
12060 | else | |
12061 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 12062 | |
72508ac0 PO |
12063 | arm_insn_r->mem_rec_count = 1; |
12064 | ||
71e396f9 LM |
12065 | /* If wback is true, also save the base register, which is going to be |
12066 | written to. */ | |
12067 | if (wback) | |
12068 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
12069 | } |
12070 | ||
12071 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12072 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12073 | return 0; | |
12074 | } | |
12075 | ||
12076 | /* Handling opcode 011 insns. */ | |
12077 | ||
12078 | static int | |
4748a9be | 12079 | arm_record_ld_st_reg_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12080 | { |
12081 | struct regcache *reg_cache = arm_insn_r->regcache; | |
12082 | ||
12083 | uint32_t shift_imm = 0; | |
12084 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
12085 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
12086 | uint32_t record_buf[8], record_buf_mem[8]; | |
12087 | ||
12088 | LONGEST s_word; | |
12089 | ULONGEST u_regval[2]; | |
12090 | ||
c55978a6 YQ |
12091 | if (bit (arm_insn_r->arm_insn, 4)) |
12092 | return arm_record_media (arm_insn_r); | |
12093 | ||
72508ac0 PO |
12094 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
12095 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
12096 | ||
12097 | /* Handle enhanced store insns and LDRD DSP insn, | |
12098 | order begins according to addressing modes for store insns | |
12099 | STRH insn. */ | |
12100 | ||
12101 | /* LDR or STR? */ | |
12102 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12103 | { | |
12104 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
12105 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
12106 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
12107 | in that case, it emulates branch and link insn, and hence we | |
12108 | need to save CSPR and PC as well. */ | |
72508ac0 | 12109 | if (15 != reg_dest) |
dda83cd7 SM |
12110 | { |
12111 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12112 | arm_insn_r->reg_rec_count = 1; | |
12113 | } | |
72508ac0 | 12114 | else |
dda83cd7 SM |
12115 | { |
12116 | record_buf[0] = reg_dest; | |
12117 | record_buf[1] = ARM_PS_REGNUM; | |
12118 | arm_insn_r->reg_rec_count = 2; | |
12119 | } | |
72508ac0 PO |
12120 | } |
12121 | else | |
12122 | { | |
12123 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
12124 | { |
12125 | /* Store insn, register offset and register pre-indexed, | |
12126 | register post-indexed. */ | |
12127 | /* Get Rm. */ | |
12128 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
12129 | /* Get Rn. */ | |
12130 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12131 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
12132 | , &u_regval[0]); | |
12133 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
12134 | , &u_regval[1]); | |
12135 | if (15 == reg_src2) | |
12136 | { | |
12137 | /* If R15 was used as Rn, hence current PC+8. */ | |
12138 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
12139 | u_regval[0] = u_regval[0] + 8; | |
12140 | } | |
12141 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
12142 | /* U == 1. */ | |
12143 | if (bit (arm_insn_r->arm_insn, 23)) | |
12144 | { | |
12145 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
12146 | } | |
12147 | else | |
12148 | { | |
12149 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
12150 | } | |
12151 | ||
12152 | switch (arm_insn_r->opcode) | |
12153 | { | |
12154 | /* STR. */ | |
12155 | case 8: | |
12156 | case 12: | |
12157 | /* STR. */ | |
12158 | case 9: | |
12159 | case 13: | |
12160 | /* STRT. */ | |
12161 | case 1: | |
12162 | case 5: | |
12163 | /* STR. */ | |
12164 | case 0: | |
12165 | case 4: | |
12166 | record_buf_mem[0] = 4; | |
12167 | break; | |
12168 | ||
12169 | /* STRB. */ | |
12170 | case 10: | |
12171 | case 14: | |
12172 | /* STRB. */ | |
12173 | case 11: | |
12174 | case 15: | |
12175 | /* STRBT. */ | |
12176 | case 3: | |
12177 | case 7: | |
12178 | /* STRB. */ | |
12179 | case 2: | |
12180 | case 6: | |
12181 | record_buf_mem[0] = 1; | |
12182 | break; | |
12183 | ||
12184 | default: | |
12185 | gdb_assert_not_reached ("no decoding pattern found"); | |
12186 | break; | |
12187 | } | |
12188 | record_buf_mem[1] = tgt_mem_addr; | |
12189 | arm_insn_r->mem_rec_count = 1; | |
12190 | ||
12191 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
12192 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
12193 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
12194 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
12195 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
12196 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
12197 | ) | |
12198 | { | |
12199 | /* Rn is going to be changed in pre-indexed mode and | |
12200 | post-indexed mode as well. */ | |
12201 | record_buf[0] = reg_src2; | |
12202 | arm_insn_r->reg_rec_count = 1; | |
12203 | } | |
12204 | } | |
72508ac0 | 12205 | else |
dda83cd7 SM |
12206 | { |
12207 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
12208 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
12209 | /* Get Rm. */ | |
12210 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
12211 | /* Get Rn. */ | |
12212 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12213 | /* Get shift_imm. */ | |
12214 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
12215 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
12216 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
12217 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12218 | /* Offset_12 used as shift. */ | |
12219 | switch (offset_12) | |
12220 | { | |
12221 | case 0: | |
12222 | /* Offset_12 used as index. */ | |
12223 | offset_12 = u_regval[0] << shift_imm; | |
12224 | break; | |
12225 | ||
12226 | case 1: | |
12227 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
12228 | break; | |
12229 | ||
12230 | case 2: | |
12231 | if (!shift_imm) | |
12232 | { | |
12233 | if (bit (u_regval[0], 31)) | |
12234 | { | |
12235 | offset_12 = 0xFFFFFFFF; | |
12236 | } | |
12237 | else | |
12238 | { | |
12239 | offset_12 = 0; | |
12240 | } | |
12241 | } | |
12242 | else | |
12243 | { | |
12244 | /* This is arithmetic shift. */ | |
12245 | offset_12 = s_word >> shift_imm; | |
12246 | } | |
12247 | break; | |
12248 | ||
12249 | case 3: | |
12250 | if (!shift_imm) | |
12251 | { | |
12252 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
12253 | &u_regval[1]); | |
12254 | /* Get C flag value and shift it by 31. */ | |
12255 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
12256 | | (u_regval[0]) >> 1); | |
12257 | } | |
12258 | else | |
12259 | { | |
12260 | offset_12 = (u_regval[0] >> shift_imm) \ | |
12261 | | (u_regval[0] << | |
12262 | (sizeof(uint32_t) - shift_imm)); | |
12263 | } | |
12264 | break; | |
12265 | ||
12266 | default: | |
12267 | gdb_assert_not_reached ("no decoding pattern found"); | |
12268 | break; | |
12269 | } | |
12270 | ||
12271 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12272 | /* bit U set. */ | |
12273 | if (bit (arm_insn_r->arm_insn, 23)) | |
12274 | { | |
12275 | tgt_mem_addr = u_regval[1] + offset_12; | |
12276 | } | |
12277 | else | |
12278 | { | |
12279 | tgt_mem_addr = u_regval[1] - offset_12; | |
12280 | } | |
12281 | ||
12282 | switch (arm_insn_r->opcode) | |
12283 | { | |
12284 | /* STR. */ | |
12285 | case 8: | |
12286 | case 12: | |
12287 | /* STR. */ | |
12288 | case 9: | |
12289 | case 13: | |
12290 | /* STRT. */ | |
12291 | case 1: | |
12292 | case 5: | |
12293 | /* STR. */ | |
12294 | case 0: | |
12295 | case 4: | |
12296 | record_buf_mem[0] = 4; | |
12297 | break; | |
12298 | ||
12299 | /* STRB. */ | |
12300 | case 10: | |
12301 | case 14: | |
12302 | /* STRB. */ | |
12303 | case 11: | |
12304 | case 15: | |
12305 | /* STRBT. */ | |
12306 | case 3: | |
12307 | case 7: | |
12308 | /* STRB. */ | |
12309 | case 2: | |
12310 | case 6: | |
12311 | record_buf_mem[0] = 1; | |
12312 | break; | |
12313 | ||
12314 | default: | |
12315 | gdb_assert_not_reached ("no decoding pattern found"); | |
12316 | break; | |
12317 | } | |
12318 | record_buf_mem[1] = tgt_mem_addr; | |
12319 | arm_insn_r->mem_rec_count = 1; | |
12320 | ||
12321 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
12322 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
12323 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
12324 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
12325 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
12326 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
12327 | ) | |
12328 | { | |
12329 | /* Rn is going to be changed in register scaled pre-indexed | |
12330 | mode,and scaled post indexed mode. */ | |
12331 | record_buf[0] = reg_src2; | |
12332 | arm_insn_r->reg_rec_count = 1; | |
12333 | } | |
12334 | } | |
72508ac0 PO |
12335 | } |
12336 | ||
12337 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12338 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12339 | return 0; | |
12340 | } | |
12341 | ||
71e396f9 | 12342 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
12343 | |
12344 | static int | |
4748a9be | 12345 | arm_record_ld_st_multiple (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12346 | { |
12347 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
12348 | uint32_t register_count = 0, register_bits; |
12349 | uint32_t reg_base, addr_mode; | |
72508ac0 | 12350 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
12351 | uint32_t wback; |
12352 | ULONGEST u_regval; | |
72508ac0 | 12353 | |
71e396f9 LM |
12354 | /* Fetch the list of registers. */ |
12355 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
12356 | arm_insn_r->reg_rec_count = 0; | |
12357 | ||
12358 | /* Fetch the base register that contains the address we are loading data | |
12359 | to. */ | |
12360 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 12361 | |
71e396f9 LM |
12362 | /* Calculate wback. */ |
12363 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
12364 | |
12365 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12366 | { | |
71e396f9 | 12367 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 12368 | |
71e396f9 | 12369 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 12370 | while (register_bits) |
71e396f9 LM |
12371 | { |
12372 | if (register_bits & 0x00000001) | |
12373 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
12374 | register_bits = register_bits >> 1; | |
12375 | register_count++; | |
12376 | } | |
72508ac0 | 12377 | |
71e396f9 LM |
12378 | |
12379 | /* If wback is true, also save the base register, which is going to be | |
12380 | written to. */ | |
12381 | if (wback) | |
12382 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
12383 | ||
12384 | /* Save the CPSR register. */ | |
12385 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
12386 | } |
12387 | else | |
12388 | { | |
71e396f9 | 12389 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 12390 | |
71e396f9 LM |
12391 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
12392 | ||
12393 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
12394 | ||
12395 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 12396 | while (register_bits) |
71e396f9 LM |
12397 | { |
12398 | if (register_bits & 0x00000001) | |
12399 | register_count++; | |
12400 | register_bits = register_bits >> 1; | |
12401 | } | |
72508ac0 PO |
12402 | |
12403 | switch (addr_mode) | |
71e396f9 LM |
12404 | { |
12405 | /* STMDA (STMED): Decrement after. */ | |
12406 | case 0: | |
12407 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12408 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
12409 | break; |
12410 | /* STM (STMIA, STMEA): Increment after. */ | |
12411 | case 1: | |
12412 | record_buf_mem[1] = (uint32_t) u_regval; | |
12413 | break; | |
12414 | /* STMDB (STMFD): Decrement before. */ | |
12415 | case 2: | |
12416 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12417 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12418 | break; |
12419 | /* STMIB (STMFA): Increment before. */ | |
12420 | case 3: | |
f0452268 | 12421 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12422 | break; |
12423 | default: | |
12424 | gdb_assert_not_reached ("no decoding pattern found"); | |
12425 | break; | |
12426 | } | |
72508ac0 | 12427 | |
f0452268 | 12428 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12429 | arm_insn_r->mem_rec_count = 1; |
12430 | ||
12431 | /* If wback is true, also save the base register, which is going to be | |
12432 | written to. */ | |
12433 | if (wback) | |
12434 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
12435 | } |
12436 | ||
12437 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12438 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12439 | return 0; | |
12440 | } | |
12441 | ||
12442 | /* Handling opcode 101 insns. */ | |
12443 | ||
12444 | static int | |
4748a9be | 12445 | arm_record_b_bl (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12446 | { |
12447 | uint32_t record_buf[8]; | |
12448 | ||
12449 | /* Handle B, BL, BLX(1) insns. */ | |
12450 | /* B simply branches so we do nothing here. */ | |
12451 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
12452 | extension space. */ | |
12453 | if (bit (arm_insn_r->arm_insn, 24)) | |
01add95b SM |
12454 | { |
12455 | record_buf[0] = ARM_LR_REGNUM; | |
12456 | arm_insn_r->reg_rec_count = 1; | |
12457 | } | |
72508ac0 PO |
12458 | |
12459 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12460 | ||
12461 | return 0; | |
12462 | } | |
12463 | ||
72508ac0 | 12464 | static int |
4748a9be | 12465 | arm_record_unsupported_insn (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 12466 | { |
6cb06a8c TT |
12467 | gdb_printf (gdb_stderr, |
12468 | _("Process record does not support instruction " | |
12469 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
12470 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
12471 | |
12472 | return -1; | |
12473 | } | |
12474 | ||
5a578da5 OJ |
12475 | /* Record handler for vector data transfer instructions. */ |
12476 | ||
12477 | static int | |
4748a9be | 12478 | arm_record_vdata_transfer_insn (arm_insn_decode_record *arm_insn_r) |
5a578da5 OJ |
12479 | { |
12480 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
12481 | uint32_t record_buf[4]; | |
12482 | ||
5a578da5 OJ |
12483 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
12484 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
12485 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
12486 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
12487 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
12488 | ||
12489 | /* Handle VMOV instruction. */ | |
12490 | if (bit_l && bit_c) | |
12491 | { | |
12492 | record_buf[0] = reg_t; | |
12493 | arm_insn_r->reg_rec_count = 1; | |
12494 | } | |
12495 | else if (bit_l && !bit_c) | |
12496 | { | |
12497 | /* Handle VMOV instruction. */ | |
12498 | if (bits_a == 0x00) | |
dda83cd7 | 12499 | { |
f1771dce | 12500 | record_buf[0] = reg_t; |
dda83cd7 SM |
12501 | arm_insn_r->reg_rec_count = 1; |
12502 | } | |
5a578da5 OJ |
12503 | /* Handle VMRS instruction. */ |
12504 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12505 | { |
12506 | if (reg_t == 15) | |
12507 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 12508 | |
dda83cd7 SM |
12509 | record_buf[0] = reg_t; |
12510 | arm_insn_r->reg_rec_count = 1; | |
12511 | } | |
5a578da5 OJ |
12512 | } |
12513 | else if (!bit_l && !bit_c) | |
12514 | { | |
12515 | /* Handle VMOV instruction. */ | |
12516 | if (bits_a == 0x00) | |
dda83cd7 | 12517 | { |
f1771dce | 12518 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 12519 | |
dda83cd7 SM |
12520 | arm_insn_r->reg_rec_count = 1; |
12521 | } | |
5a578da5 OJ |
12522 | /* Handle VMSR instruction. */ |
12523 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12524 | { |
12525 | record_buf[0] = ARM_FPSCR_REGNUM; | |
12526 | arm_insn_r->reg_rec_count = 1; | |
12527 | } | |
5a578da5 OJ |
12528 | } |
12529 | else if (!bit_l && bit_c) | |
12530 | { | |
12531 | /* Handle VMOV instruction. */ | |
12532 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
12533 | { |
12534 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
12535 | + ARM_D0_REGNUM; | |
12536 | arm_insn_r->reg_rec_count = 1; | |
12537 | } | |
5a578da5 OJ |
12538 | /* Handle VDUP instruction. */ |
12539 | else | |
dda83cd7 SM |
12540 | { |
12541 | if (bit (arm_insn_r->arm_insn, 21)) | |
12542 | { | |
12543 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12544 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12545 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
12546 | arm_insn_r->reg_rec_count = 2; | |
12547 | } | |
12548 | else | |
12549 | { | |
12550 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12551 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12552 | arm_insn_r->reg_rec_count = 1; | |
12553 | } | |
12554 | } | |
12555 | } | |
12556 | ||
12557 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12558 | return 0; | |
12559 | } | |
12560 | ||
f20f80dd OJ |
12561 | /* Record handler for extension register load/store instructions. */ |
12562 | ||
12563 | static int | |
4748a9be | 12564 | arm_record_exreg_ld_st_insn (arm_insn_decode_record *arm_insn_r) |
f20f80dd OJ |
12565 | { |
12566 | uint32_t opcode, single_reg; | |
12567 | uint8_t op_vldm_vstm; | |
12568 | uint32_t record_buf[8], record_buf_mem[128]; | |
12569 | ULONGEST u_regval = 0; | |
12570 | ||
12571 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
12572 | |
12573 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 12574 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
12575 | op_vldm_vstm = opcode & 0x1b; |
12576 | ||
12577 | /* Handle VMOV instructions. */ | |
12578 | if ((opcode & 0x1e) == 0x04) | |
12579 | { | |
9fde51ed | 12580 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
12581 | { |
12582 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12583 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12584 | arm_insn_r->reg_rec_count = 2; | |
12585 | } | |
f20f80dd | 12586 | else |
01e57735 | 12587 | { |
9fde51ed YQ |
12588 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
12589 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 12590 | |
9fde51ed | 12591 | if (single_reg) |
01e57735 | 12592 | { |
9fde51ed YQ |
12593 | /* The first S register number m is REG_M:M (M is bit 5), |
12594 | the corresponding D register number is REG_M:M / 2, which | |
12595 | is REG_M. */ | |
12596 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
12597 | /* The second S register number is REG_M:M + 1, the | |
12598 | corresponding D register number is (REG_M:M + 1) / 2. | |
12599 | IOW, if bit M is 1, the first and second S registers | |
12600 | are mapped to different D registers, otherwise, they are | |
12601 | in the same D register. */ | |
12602 | if (bit_m) | |
12603 | { | |
12604 | record_buf[arm_insn_r->reg_rec_count++] | |
12605 | = ARM_D0_REGNUM + reg_m + 1; | |
12606 | } | |
01e57735 YQ |
12607 | } |
12608 | else | |
12609 | { | |
9fde51ed | 12610 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
12611 | arm_insn_r->reg_rec_count = 1; |
12612 | } | |
12613 | } | |
f20f80dd OJ |
12614 | } |
12615 | /* Handle VSTM and VPUSH instructions. */ | |
12616 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 12617 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
12618 | { |
12619 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
12620 | uint32_t memory_index = 0; | |
12621 | ||
12622 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12623 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12624 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12625 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12626 | memory_count = imm_off8; |
12627 | ||
12628 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12629 | start_address = u_regval; |
f20f80dd | 12630 | else |
01e57735 | 12631 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12632 | |
12633 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
12634 | { |
12635 | record_buf[0] = reg_rn; | |
12636 | arm_insn_r->reg_rec_count = 1; | |
12637 | } | |
f20f80dd OJ |
12638 | |
12639 | while (memory_count > 0) | |
01e57735 | 12640 | { |
9fde51ed | 12641 | if (single_reg) |
01e57735 | 12642 | { |
9fde51ed YQ |
12643 | record_buf_mem[memory_index] = 4; |
12644 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12645 | start_address = start_address + 4; |
12646 | memory_index = memory_index + 2; | |
12647 | } | |
12648 | else | |
12649 | { | |
9fde51ed YQ |
12650 | record_buf_mem[memory_index] = 4; |
12651 | record_buf_mem[memory_index + 1] = start_address; | |
12652 | record_buf_mem[memory_index + 2] = 4; | |
12653 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12654 | start_address = start_address + 8; |
12655 | memory_index = memory_index + 4; | |
12656 | } | |
12657 | memory_count--; | |
12658 | } | |
f20f80dd OJ |
12659 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
12660 | } | |
12661 | /* Handle VLDM instructions. */ | |
12662 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 12663 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
12664 | { |
12665 | uint32_t reg_count, reg_vd; | |
12666 | uint32_t reg_index = 0; | |
9fde51ed | 12667 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
12668 | |
12669 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12670 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
12671 | ||
9fde51ed YQ |
12672 | /* REG_VD is the first D register number. If the instruction |
12673 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
12674 | number is (REG_VD << 1 | bit D), so the corresponding D | |
12675 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
12676 | if (!single_reg) | |
12677 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 12678 | |
9fde51ed | 12679 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 12680 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 12681 | |
9fde51ed YQ |
12682 | /* If the instruction loads memory to D register, REG_COUNT should |
12683 | be divided by 2, according to the ARM Architecture Reference | |
12684 | Manual. If the instruction loads memory to S register, divide by | |
12685 | 2 as well because two S registers are mapped to D register. */ | |
12686 | reg_count = reg_count / 2; | |
12687 | if (single_reg && bit_d) | |
01e57735 | 12688 | { |
9fde51ed YQ |
12689 | /* Increase the register count if S register list starts from |
12690 | an odd number (bit d is one). */ | |
12691 | reg_count++; | |
12692 | } | |
f20f80dd | 12693 | |
9fde51ed YQ |
12694 | while (reg_count > 0) |
12695 | { | |
12696 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
12697 | reg_count--; |
12698 | } | |
f20f80dd OJ |
12699 | arm_insn_r->reg_rec_count = reg_index; |
12700 | } | |
12701 | /* VSTR Vector store register. */ | |
12702 | else if ((opcode & 0x13) == 0x10) | |
12703 | { | |
bec2ab5a | 12704 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
12705 | uint32_t memory_index = 0; |
12706 | ||
12707 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12708 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12709 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12710 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12711 | |
12712 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12713 | start_address = u_regval + imm_off32; |
f20f80dd | 12714 | else |
01e57735 | 12715 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12716 | |
12717 | if (single_reg) | |
01e57735 | 12718 | { |
9fde51ed YQ |
12719 | record_buf_mem[memory_index] = 4; |
12720 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12721 | arm_insn_r->mem_rec_count = 1; |
12722 | } | |
f20f80dd | 12723 | else |
01e57735 | 12724 | { |
9fde51ed YQ |
12725 | record_buf_mem[memory_index] = 4; |
12726 | record_buf_mem[memory_index + 1] = start_address; | |
12727 | record_buf_mem[memory_index + 2] = 4; | |
12728 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12729 | arm_insn_r->mem_rec_count = 2; |
12730 | } | |
f20f80dd OJ |
12731 | } |
12732 | /* VLDR Vector load register. */ | |
12733 | else if ((opcode & 0x13) == 0x11) | |
12734 | { | |
12735 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12736 | ||
12737 | if (!single_reg) | |
01e57735 YQ |
12738 | { |
12739 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
12740 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
12741 | } | |
f20f80dd | 12742 | else |
01e57735 YQ |
12743 | { |
12744 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
12745 | /* Record register D rather than pseudo register S. */ |
12746 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 12747 | } |
f20f80dd OJ |
12748 | arm_insn_r->reg_rec_count = 1; |
12749 | } | |
12750 | ||
12751 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12752 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12753 | return 0; | |
12754 | } | |
12755 | ||
851f26ae OJ |
12756 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
12757 | ||
12758 | static int | |
4748a9be | 12759 | arm_record_vfp_data_proc_insn (arm_insn_decode_record *arm_insn_r) |
851f26ae OJ |
12760 | { |
12761 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
12762 | uint32_t record_buf[4]; | |
12763 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
12764 | enum insn_types curr_insn_type = INSN_INV; | |
12765 | ||
12766 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12767 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
12768 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12769 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
12770 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
12771 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
12772 | /* Mask off the "D" bit. */ |
12773 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
12774 | |
12775 | /* Handle VMLA, VMLS. */ | |
12776 | if (opc1 == 0x00) | |
12777 | { | |
12778 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12779 | { |
12780 | if (bit (arm_insn_r->arm_insn, 6)) | |
12781 | curr_insn_type = INSN_T0; | |
12782 | else | |
12783 | curr_insn_type = INSN_T1; | |
12784 | } | |
851f26ae | 12785 | else |
dda83cd7 SM |
12786 | { |
12787 | if (dp_op_sz) | |
12788 | curr_insn_type = INSN_T1; | |
12789 | else | |
12790 | curr_insn_type = INSN_T2; | |
12791 | } | |
851f26ae OJ |
12792 | } |
12793 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
12794 | else if (opc1 == 0x01) | |
12795 | { | |
12796 | if (dp_op_sz) | |
dda83cd7 | 12797 | curr_insn_type = INSN_T1; |
851f26ae | 12798 | else |
dda83cd7 | 12799 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12800 | } |
12801 | /* Handle VMUL. */ | |
12802 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
12803 | { | |
12804 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12805 | { |
12806 | if (bit (arm_insn_r->arm_insn, 6)) | |
12807 | curr_insn_type = INSN_T0; | |
12808 | else | |
12809 | curr_insn_type = INSN_T1; | |
12810 | } | |
851f26ae | 12811 | else |
dda83cd7 SM |
12812 | { |
12813 | if (dp_op_sz) | |
12814 | curr_insn_type = INSN_T1; | |
12815 | else | |
12816 | curr_insn_type = INSN_T2; | |
12817 | } | |
851f26ae OJ |
12818 | } |
12819 | /* Handle VADD, VSUB. */ | |
12820 | else if (opc1 == 0x03) | |
12821 | { | |
12822 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
12823 | { |
12824 | if (bit (arm_insn_r->arm_insn, 6)) | |
12825 | curr_insn_type = INSN_T0; | |
12826 | else | |
12827 | curr_insn_type = INSN_T1; | |
12828 | } | |
851f26ae | 12829 | else |
dda83cd7 SM |
12830 | { |
12831 | if (dp_op_sz) | |
12832 | curr_insn_type = INSN_T1; | |
12833 | else | |
12834 | curr_insn_type = INSN_T2; | |
12835 | } | |
851f26ae OJ |
12836 | } |
12837 | /* Handle VDIV. */ | |
ce887586 | 12838 | else if (opc1 == 0x08) |
851f26ae OJ |
12839 | { |
12840 | if (dp_op_sz) | |
dda83cd7 | 12841 | curr_insn_type = INSN_T1; |
851f26ae | 12842 | else |
dda83cd7 | 12843 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12844 | } |
12845 | /* Handle all other vfp data processing instructions. */ | |
12846 | else if (opc1 == 0x0b) | |
12847 | { | |
12848 | /* Handle VMOV. */ | |
12849 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
12850 | { |
12851 | if (bit (arm_insn_r->arm_insn, 4)) | |
12852 | { | |
12853 | if (bit (arm_insn_r->arm_insn, 6)) | |
12854 | curr_insn_type = INSN_T0; | |
12855 | else | |
12856 | curr_insn_type = INSN_T1; | |
12857 | } | |
12858 | else | |
12859 | { | |
12860 | if (dp_op_sz) | |
12861 | curr_insn_type = INSN_T1; | |
12862 | else | |
12863 | curr_insn_type = INSN_T2; | |
12864 | } | |
12865 | } | |
851f26ae OJ |
12866 | /* Handle VNEG and VABS. */ |
12867 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
12868 | || (opc2 == 0x00 && opc3 == 0x03)) |
12869 | { | |
12870 | if (!bit (arm_insn_r->arm_insn, 11)) | |
12871 | { | |
12872 | if (bit (arm_insn_r->arm_insn, 6)) | |
12873 | curr_insn_type = INSN_T0; | |
12874 | else | |
12875 | curr_insn_type = INSN_T1; | |
12876 | } | |
12877 | else | |
12878 | { | |
12879 | if (dp_op_sz) | |
12880 | curr_insn_type = INSN_T1; | |
12881 | else | |
12882 | curr_insn_type = INSN_T2; | |
12883 | } | |
12884 | } | |
851f26ae OJ |
12885 | /* Handle VSQRT. */ |
12886 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
12887 | { |
12888 | if (dp_op_sz) | |
12889 | curr_insn_type = INSN_T1; | |
12890 | else | |
12891 | curr_insn_type = INSN_T2; | |
12892 | } | |
851f26ae OJ |
12893 | /* Handle VCVT. */ |
12894 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
12895 | { |
12896 | if (!dp_op_sz) | |
12897 | curr_insn_type = INSN_T1; | |
12898 | else | |
12899 | curr_insn_type = INSN_T2; | |
12900 | } | |
851f26ae | 12901 | else if (opc3 & 0x01) |
dda83cd7 SM |
12902 | { |
12903 | /* Handle VCVT. */ | |
12904 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
12905 | { | |
12906 | if (!bit (arm_insn_r->arm_insn, 18)) | |
12907 | curr_insn_type = INSN_T2; | |
12908 | else | |
12909 | { | |
12910 | if (dp_op_sz) | |
12911 | curr_insn_type = INSN_T1; | |
12912 | else | |
12913 | curr_insn_type = INSN_T2; | |
12914 | } | |
12915 | } | |
12916 | /* Handle VCVT. */ | |
12917 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
12918 | { | |
12919 | if (dp_op_sz) | |
12920 | curr_insn_type = INSN_T1; | |
12921 | else | |
12922 | curr_insn_type = INSN_T2; | |
12923 | } | |
12924 | /* Handle VCVTB, VCVTT. */ | |
12925 | else if ((opc2 & 0x0e) == 0x02) | |
12926 | curr_insn_type = INSN_T2; | |
12927 | /* Handle VCMP, VCMPE. */ | |
12928 | else if ((opc2 & 0x0e) == 0x04) | |
12929 | curr_insn_type = INSN_T3; | |
12930 | } | |
851f26ae OJ |
12931 | } |
12932 | ||
12933 | switch (curr_insn_type) | |
12934 | { | |
12935 | case INSN_T0: | |
dda83cd7 SM |
12936 | reg_vd = reg_vd | (bit_d << 4); |
12937 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12938 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
12939 | arm_insn_r->reg_rec_count = 2; | |
12940 | break; | |
851f26ae OJ |
12941 | |
12942 | case INSN_T1: | |
dda83cd7 SM |
12943 | reg_vd = reg_vd | (bit_d << 4); |
12944 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12945 | arm_insn_r->reg_rec_count = 1; | |
12946 | break; | |
851f26ae OJ |
12947 | |
12948 | case INSN_T2: | |
dda83cd7 SM |
12949 | reg_vd = (reg_vd << 1) | bit_d; |
12950 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12951 | arm_insn_r->reg_rec_count = 1; | |
12952 | break; | |
851f26ae OJ |
12953 | |
12954 | case INSN_T3: | |
dda83cd7 SM |
12955 | record_buf[0] = ARM_FPSCR_REGNUM; |
12956 | arm_insn_r->reg_rec_count = 1; | |
12957 | break; | |
851f26ae OJ |
12958 | |
12959 | default: | |
dda83cd7 SM |
12960 | gdb_assert_not_reached ("no decoding pattern found"); |
12961 | break; | |
851f26ae OJ |
12962 | } |
12963 | ||
12964 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12965 | return 0; | |
12966 | } | |
12967 | ||
60cc5e93 OJ |
12968 | /* Handling opcode 110 insns. */ |
12969 | ||
12970 | static int | |
4748a9be | 12971 | arm_record_asimd_vfp_coproc (arm_insn_decode_record *arm_insn_r) |
60cc5e93 | 12972 | { |
bec2ab5a | 12973 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
12974 | |
12975 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
12976 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
12977 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12978 | ||
12979 | if ((coproc & 0x0e) == 0x0a) | |
12980 | { | |
12981 | /* Handle extension register ld/st instructions. */ | |
12982 | if (!(op1 & 0x20)) | |
dda83cd7 | 12983 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12984 | |
12985 | /* 64-bit transfers between arm core and extension registers. */ | |
12986 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 12987 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12988 | } |
12989 | else | |
12990 | { | |
12991 | /* Handle coprocessor ld/st instructions. */ | |
12992 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
12993 | { |
12994 | /* Store. */ | |
12995 | if (!op1_ebit) | |
12996 | return arm_record_unsupported_insn (arm_insn_r); | |
12997 | else | |
12998 | /* Load. */ | |
12999 | return arm_record_unsupported_insn (arm_insn_r); | |
13000 | } | |
60cc5e93 OJ |
13001 | |
13002 | /* Move to coprocessor from two arm core registers. */ | |
13003 | if (op1 == 0x4) | |
dda83cd7 | 13004 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
13005 | |
13006 | /* Move to two arm core registers from coprocessor. */ | |
13007 | if (op1 == 0x5) | |
dda83cd7 SM |
13008 | { |
13009 | uint32_t reg_t[2]; | |
60cc5e93 | 13010 | |
dda83cd7 SM |
13011 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
13012 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
13013 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 13014 | |
dda83cd7 SM |
13015 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
13016 | return 0; | |
60cc5e93 OJ |
13017 | } |
13018 | } | |
13019 | return arm_record_unsupported_insn (arm_insn_r); | |
13020 | } | |
13021 | ||
72508ac0 PO |
13022 | /* Handling opcode 111 insns. */ |
13023 | ||
13024 | static int | |
4748a9be | 13025 | arm_record_coproc_data_proc (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 13026 | { |
2d9e6acb | 13027 | uint32_t op, op1_ebit, coproc, bits_24_25; |
345bd07c | 13028 | arm_gdbarch_tdep *tdep |
08106042 | 13029 | = gdbarch_tdep<arm_gdbarch_tdep> (arm_insn_r->gdbarch); |
72508ac0 | 13030 | struct regcache *reg_cache = arm_insn_r->regcache; |
72508ac0 PO |
13031 | |
13032 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 13033 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
13034 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
13035 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 13036 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
13037 | |
13038 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 13039 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
13040 | { |
13041 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
13042 | { |
13043 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 13044 | |
dda83cd7 | 13045 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 13046 | |
dda83cd7 SM |
13047 | if (svc_operand) /* OABI. */ |
13048 | svc_number = svc_operand - 0x900000; | |
13049 | else /* EABI. */ | |
13050 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 13051 | |
dda83cd7 SM |
13052 | return tdep->arm_syscall_record (reg_cache, svc_number); |
13053 | } | |
97dfe206 | 13054 | else |
dda83cd7 | 13055 | { |
6cb06a8c | 13056 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
13057 | return -1; |
13058 | } | |
97dfe206 | 13059 | } |
2d9e6acb | 13060 | else if (bits_24_25 == 0x02) |
60cc5e93 | 13061 | { |
2d9e6acb YQ |
13062 | if (op) |
13063 | { | |
13064 | if ((coproc & 0x0e) == 0x0a) | |
13065 | { | |
13066 | /* 8, 16, and 32-bit transfer */ | |
13067 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
13068 | } | |
13069 | else | |
13070 | { | |
13071 | if (op1_ebit) | |
13072 | { | |
13073 | /* MRC, MRC2 */ | |
13074 | uint32_t record_buf[1]; | |
13075 | ||
13076 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
13077 | if (record_buf[0] == 15) | |
13078 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 13079 | |
2d9e6acb YQ |
13080 | arm_insn_r->reg_rec_count = 1; |
13081 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
13082 | record_buf); | |
13083 | return 0; | |
13084 | } | |
13085 | else | |
13086 | { | |
13087 | /* MCR, MCR2 */ | |
13088 | return -1; | |
13089 | } | |
13090 | } | |
13091 | } | |
13092 | else | |
13093 | { | |
13094 | if ((coproc & 0x0e) == 0x0a) | |
13095 | { | |
13096 | /* VFP data-processing instructions. */ | |
13097 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
13098 | } | |
13099 | else | |
13100 | { | |
13101 | /* CDP, CDP2 */ | |
13102 | return -1; | |
13103 | } | |
13104 | } | |
60cc5e93 | 13105 | } |
97dfe206 OJ |
13106 | else |
13107 | { | |
2d9e6acb | 13108 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 13109 | |
2d9e6acb YQ |
13110 | if (op1 == 5) |
13111 | { | |
13112 | if ((coproc & 0x0e) != 0x0a) | |
13113 | { | |
13114 | /* MRRC, MRRC2 */ | |
13115 | return -1; | |
13116 | } | |
13117 | } | |
13118 | else if (op1 == 4 || op1 == 5) | |
13119 | { | |
13120 | if ((coproc & 0x0e) == 0x0a) | |
13121 | { | |
13122 | /* 64-bit transfers between ARM core and extension */ | |
13123 | return -1; | |
13124 | } | |
13125 | else if (op1 == 4) | |
13126 | { | |
13127 | /* MCRR, MCRR2 */ | |
13128 | return -1; | |
13129 | } | |
13130 | } | |
13131 | else if (op1 == 0 || op1 == 1) | |
13132 | { | |
13133 | /* UNDEFINED */ | |
13134 | return -1; | |
13135 | } | |
13136 | else | |
13137 | { | |
13138 | if ((coproc & 0x0e) == 0x0a) | |
13139 | { | |
13140 | /* Extension register load/store */ | |
13141 | } | |
13142 | else | |
13143 | { | |
13144 | /* STC, STC2, LDC, LDC2 */ | |
13145 | } | |
13146 | return -1; | |
13147 | } | |
97dfe206 | 13148 | } |
72508ac0 | 13149 | |
2d9e6acb | 13150 | return -1; |
72508ac0 PO |
13151 | } |
13152 | ||
13153 | /* Handling opcode 000 insns. */ | |
13154 | ||
13155 | static int | |
4748a9be | 13156 | thumb_record_shift_add_sub (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13157 | { |
13158 | uint32_t record_buf[8]; | |
13159 | uint32_t reg_src1 = 0; | |
13160 | ||
13161 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13162 | ||
13163 | record_buf[0] = ARM_PS_REGNUM; | |
13164 | record_buf[1] = reg_src1; | |
13165 | thumb_insn_r->reg_rec_count = 2; | |
13166 | ||
13167 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13168 | ||
13169 | return 0; | |
13170 | } | |
13171 | ||
13172 | ||
13173 | /* Handling opcode 001 insns. */ | |
13174 | ||
13175 | static int | |
4748a9be | 13176 | thumb_record_add_sub_cmp_mov (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13177 | { |
13178 | uint32_t record_buf[8]; | |
13179 | uint32_t reg_src1 = 0; | |
13180 | ||
13181 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13182 | ||
13183 | record_buf[0] = ARM_PS_REGNUM; | |
13184 | record_buf[1] = reg_src1; | |
13185 | thumb_insn_r->reg_rec_count = 2; | |
13186 | ||
13187 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13188 | ||
13189 | return 0; | |
13190 | } | |
13191 | ||
13192 | /* Handling opcode 010 insns. */ | |
13193 | ||
13194 | static int | |
4748a9be | 13195 | thumb_record_ld_st_reg_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13196 | { |
13197 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13198 | uint32_t record_buf[8], record_buf_mem[8]; | |
13199 | ||
13200 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
13201 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
13202 | ||
13203 | ULONGEST u_regval[2] = {0}; | |
13204 | ||
13205 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
13206 | ||
13207 | if (bit (thumb_insn_r->arm_insn, 12)) | |
13208 | { | |
13209 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
13210 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
13211 | ||
b020ff80 | 13212 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
13213 | { |
13214 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
13215 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
13216 | record_buf[0] = reg_src1; | |
13217 | thumb_insn_r->reg_rec_count = 1; | |
13218 | } | |
b020ff80 | 13219 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
13220 | { |
13221 | /* STR(2), STRB(2), STRH(2) . */ | |
13222 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13223 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
13224 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
13225 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
13226 | if (0 == opB) | |
13227 | record_buf_mem[0] = 4; /* STR (2). */ | |
13228 | else if (2 == opB) | |
13229 | record_buf_mem[0] = 1; /* STRB (2). */ | |
13230 | else if (1 == opB) | |
13231 | record_buf_mem[0] = 2; /* STRH (2). */ | |
13232 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
13233 | thumb_insn_r->mem_rec_count = 1; | |
13234 | } | |
72508ac0 PO |
13235 | } |
13236 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
13237 | { | |
13238 | /* Handle load from literal pool. */ | |
13239 | /* LDR(3). */ | |
13240 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13241 | record_buf[0] = reg_src1; | |
13242 | thumb_insn_r->reg_rec_count = 1; | |
13243 | } | |
13244 | else if (opcode1) | |
13245 | { | |
b121eeb9 | 13246 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
13247 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
13248 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13249 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
13250 | { |
13251 | /* Branch with exchange. */ | |
13252 | record_buf[0] = ARM_PS_REGNUM; | |
13253 | thumb_insn_r->reg_rec_count = 1; | |
13254 | } | |
72508ac0 | 13255 | else |
dda83cd7 | 13256 | { |
1f33efec YQ |
13257 | /* Format 8; special data processing insns. */ |
13258 | record_buf[0] = ARM_PS_REGNUM; | |
13259 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
13260 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
13261 | thumb_insn_r->reg_rec_count = 2; |
13262 | } | |
72508ac0 PO |
13263 | } |
13264 | else | |
13265 | { | |
13266 | /* Format 5; data processing insns. */ | |
13267 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13268 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
13269 | { |
13270 | reg_src1 = reg_src1 + 8; | |
13271 | } | |
72508ac0 PO |
13272 | record_buf[0] = ARM_PS_REGNUM; |
13273 | record_buf[1] = reg_src1; | |
13274 | thumb_insn_r->reg_rec_count = 2; | |
13275 | } | |
13276 | ||
13277 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13278 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13279 | record_buf_mem); |
72508ac0 PO |
13280 | |
13281 | return 0; | |
13282 | } | |
13283 | ||
13284 | /* Handling opcode 001 insns. */ | |
13285 | ||
13286 | static int | |
4748a9be | 13287 | thumb_record_ld_st_imm_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13288 | { |
13289 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13290 | uint32_t record_buf[8], record_buf_mem[8]; | |
13291 | ||
13292 | uint32_t reg_src1 = 0; | |
13293 | uint32_t opcode = 0, immed_5 = 0; | |
13294 | ||
13295 | ULONGEST u_regval = 0; | |
13296 | ||
13297 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13298 | ||
13299 | if (opcode) | |
13300 | { | |
13301 | /* LDR(1). */ | |
13302 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13303 | record_buf[0] = reg_src1; | |
13304 | thumb_insn_r->reg_rec_count = 1; | |
13305 | } | |
13306 | else | |
13307 | { | |
13308 | /* STR(1). */ | |
13309 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13310 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13311 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13312 | record_buf_mem[0] = 4; | |
13313 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
13314 | thumb_insn_r->mem_rec_count = 1; | |
13315 | } | |
13316 | ||
13317 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13318 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13319 | record_buf_mem); |
72508ac0 PO |
13320 | |
13321 | return 0; | |
13322 | } | |
13323 | ||
13324 | /* Handling opcode 100 insns. */ | |
13325 | ||
13326 | static int | |
4748a9be | 13327 | thumb_record_ld_st_stack (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13328 | { |
13329 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13330 | uint32_t record_buf[8], record_buf_mem[8]; | |
13331 | ||
13332 | uint32_t reg_src1 = 0; | |
13333 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
13334 | ||
13335 | ULONGEST u_regval = 0; | |
13336 | ||
13337 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13338 | ||
13339 | if (3 == opcode) | |
13340 | { | |
13341 | /* LDR(4). */ | |
13342 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13343 | record_buf[0] = reg_src1; | |
13344 | thumb_insn_r->reg_rec_count = 1; | |
13345 | } | |
13346 | else if (1 == opcode) | |
13347 | { | |
13348 | /* LDRH(1). */ | |
13349 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13350 | record_buf[0] = reg_src1; | |
13351 | thumb_insn_r->reg_rec_count = 1; | |
13352 | } | |
13353 | else if (2 == opcode) | |
13354 | { | |
13355 | /* STR(3). */ | |
13356 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
13357 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13358 | record_buf_mem[0] = 4; | |
13359 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
13360 | thumb_insn_r->mem_rec_count = 1; | |
13361 | } | |
13362 | else if (0 == opcode) | |
13363 | { | |
13364 | /* STRH(1). */ | |
13365 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13366 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13367 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13368 | record_buf_mem[0] = 2; | |
13369 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
13370 | thumb_insn_r->mem_rec_count = 1; | |
13371 | } | |
13372 | ||
13373 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13374 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13375 | record_buf_mem); |
72508ac0 PO |
13376 | |
13377 | return 0; | |
13378 | } | |
13379 | ||
13380 | /* Handling opcode 101 insns. */ | |
13381 | ||
13382 | static int | |
4748a9be | 13383 | thumb_record_misc (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13384 | { |
13385 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13386 | ||
b121eeb9 | 13387 | uint32_t opcode = 0; |
72508ac0 | 13388 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 13389 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13390 | uint32_t record_buf[24], record_buf_mem[48]; |
13391 | uint32_t reg_src1; | |
13392 | ||
13393 | ULONGEST u_regval = 0; | |
13394 | ||
13395 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 13396 | |
b121eeb9 | 13397 | if (opcode == 0 || opcode == 1) |
72508ac0 | 13398 | { |
b121eeb9 YQ |
13399 | /* ADR and ADD (SP plus immediate) */ |
13400 | ||
72508ac0 PO |
13401 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
13402 | record_buf[0] = reg_src1; | |
13403 | thumb_insn_r->reg_rec_count = 1; | |
13404 | } | |
b121eeb9 | 13405 | else |
72508ac0 | 13406 | { |
b121eeb9 YQ |
13407 | /* Miscellaneous 16-bit instructions */ |
13408 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
13409 | ||
13410 | switch (opcode2) | |
13411 | { | |
13412 | case 6: | |
13413 | /* SETEND and CPS */ | |
13414 | break; | |
13415 | case 0: | |
13416 | /* ADD/SUB (SP plus immediate) */ | |
13417 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13418 | record_buf[0] = ARM_SP_REGNUM; | |
13419 | thumb_insn_r->reg_rec_count = 1; | |
13420 | break; | |
13421 | case 1: /* fall through */ | |
13422 | case 3: /* fall through */ | |
13423 | case 9: /* fall through */ | |
13424 | case 11: | |
13425 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
13426 | break; |
13427 | case 2: | |
13428 | /* SXTH, SXTB, UXTH, UXTB */ | |
13429 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
13430 | thumb_insn_r->reg_rec_count = 1; | |
13431 | break; | |
13432 | case 4: /* fall through */ | |
13433 | case 5: | |
13434 | /* PUSH. */ | |
13435 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13436 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13437 | while (register_bits) | |
13438 | { | |
13439 | if (register_bits & 0x00000001) | |
13440 | register_count++; | |
13441 | register_bits = register_bits >> 1; | |
13442 | } | |
13443 | start_address = u_regval - \ | |
13444 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
13445 | thumb_insn_r->mem_rec_count = register_count; | |
13446 | while (register_count) | |
13447 | { | |
13448 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13449 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13450 | start_address = start_address + 4; | |
13451 | register_count--; | |
13452 | } | |
13453 | record_buf[0] = ARM_SP_REGNUM; | |
13454 | thumb_insn_r->reg_rec_count = 1; | |
13455 | break; | |
13456 | case 10: | |
13457 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
13458 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
13459 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
13460 | break; |
13461 | case 12: /* fall through */ | |
13462 | case 13: | |
13463 | /* POP. */ | |
13464 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13465 | while (register_bits) | |
13466 | { | |
13467 | if (register_bits & 0x00000001) | |
13468 | record_buf[index++] = register_count; | |
13469 | register_bits = register_bits >> 1; | |
13470 | register_count++; | |
13471 | } | |
13472 | record_buf[index++] = ARM_PS_REGNUM; | |
13473 | record_buf[index++] = ARM_SP_REGNUM; | |
13474 | thumb_insn_r->reg_rec_count = index; | |
13475 | break; | |
13476 | case 0xe: | |
13477 | /* BKPT insn. */ | |
13478 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
13479 | /* CPSR is changed to be executed in ARM state, disabling normal | |
13480 | interrupts, entering abort mode. */ | |
13481 | /* According to high vector configuration PC is set. */ | |
13482 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
13483 | previous CPSR and Program Counter. */ | |
13484 | record_buf[0] = ARM_PS_REGNUM; | |
13485 | record_buf[1] = ARM_LR_REGNUM; | |
13486 | thumb_insn_r->reg_rec_count = 2; | |
13487 | /* We need to save SPSR value, which is not yet done. */ | |
6cb06a8c TT |
13488 | gdb_printf (gdb_stderr, |
13489 | _("Process record does not support instruction " | |
13490 | "0x%0x at address %s.\n"), | |
13491 | thumb_insn_r->arm_insn, | |
13492 | paddress (thumb_insn_r->gdbarch, | |
13493 | thumb_insn_r->this_addr)); | |
b121eeb9 YQ |
13494 | return -1; |
13495 | ||
13496 | case 0xf: | |
13497 | /* If-Then, and hints */ | |
13498 | break; | |
13499 | default: | |
13500 | return -1; | |
13501 | }; | |
72508ac0 PO |
13502 | } |
13503 | ||
13504 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13505 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13506 | record_buf_mem); |
72508ac0 PO |
13507 | |
13508 | return 0; | |
13509 | } | |
13510 | ||
13511 | /* Handling opcode 110 insns. */ | |
13512 | ||
13513 | static int | |
4748a9be | 13514 | thumb_record_ldm_stm_swi (arm_insn_decode_record *thumb_insn_r) |
72508ac0 | 13515 | { |
345bd07c | 13516 | arm_gdbarch_tdep *tdep |
08106042 | 13517 | = gdbarch_tdep<arm_gdbarch_tdep> (thumb_insn_r->gdbarch); |
72508ac0 PO |
13518 | struct regcache *reg_cache = thumb_insn_r->regcache; |
13519 | ||
13520 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
13521 | uint32_t reg_src1 = 0; | |
13522 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 13523 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13524 | uint32_t record_buf[24], record_buf_mem[48]; |
13525 | ||
13526 | ULONGEST u_regval = 0; | |
13527 | ||
13528 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
13529 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
13530 | ||
13531 | if (1 == opcode2) | |
13532 | { | |
13533 | ||
13534 | /* LDMIA. */ | |
13535 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13536 | /* Get Rn. */ | |
13537 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13538 | while (register_bits) | |
dda83cd7 SM |
13539 | { |
13540 | if (register_bits & 0x00000001) | |
13541 | record_buf[index++] = register_count; | |
13542 | register_bits = register_bits >> 1; | |
13543 | register_count++; | |
13544 | } | |
f969241e OJ |
13545 | record_buf[index++] = reg_src1; |
13546 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
13547 | } |
13548 | else if (0 == opcode2) | |
13549 | { | |
13550 | /* It handles both STMIA. */ | |
13551 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13552 | /* Get Rn. */ | |
13553 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13554 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13555 | while (register_bits) | |
dda83cd7 SM |
13556 | { |
13557 | if (register_bits & 0x00000001) | |
13558 | register_count++; | |
13559 | register_bits = register_bits >> 1; | |
13560 | } | |
72508ac0 PO |
13561 | start_address = u_regval; |
13562 | thumb_insn_r->mem_rec_count = register_count; | |
13563 | while (register_count) | |
dda83cd7 SM |
13564 | { |
13565 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13566 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13567 | start_address = start_address + 4; | |
13568 | register_count--; | |
13569 | } | |
72508ac0 PO |
13570 | } |
13571 | else if (0x1F == opcode1) | |
13572 | { | |
dda83cd7 SM |
13573 | /* Handle arm syscall insn. */ |
13574 | if (tdep->arm_syscall_record != NULL) | |
13575 | { | |
13576 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
13577 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
13578 | } | |
13579 | else | |
13580 | { | |
6cb06a8c | 13581 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
13582 | return -1; |
13583 | } | |
72508ac0 PO |
13584 | } |
13585 | ||
13586 | /* B (1), conditional branch is automatically taken care in process_record, | |
13587 | as PC is saved there. */ | |
13588 | ||
13589 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13590 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13591 | record_buf_mem); |
72508ac0 PO |
13592 | |
13593 | return ret; | |
13594 | } | |
13595 | ||
13596 | /* Handling opcode 111 insns. */ | |
13597 | ||
13598 | static int | |
4748a9be | 13599 | thumb_record_branch (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13600 | { |
13601 | uint32_t record_buf[8]; | |
13602 | uint32_t bits_h = 0; | |
13603 | ||
13604 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
13605 | ||
13606 | if (2 == bits_h || 3 == bits_h) | |
13607 | { | |
13608 | /* BL */ | |
13609 | record_buf[0] = ARM_LR_REGNUM; | |
13610 | thumb_insn_r->reg_rec_count = 1; | |
13611 | } | |
13612 | else if (1 == bits_h) | |
13613 | { | |
13614 | /* BLX(1). */ | |
13615 | record_buf[0] = ARM_PS_REGNUM; | |
13616 | record_buf[1] = ARM_LR_REGNUM; | |
13617 | thumb_insn_r->reg_rec_count = 2; | |
13618 | } | |
13619 | ||
13620 | /* B(2) is automatically taken care in process_record, as PC is | |
13621 | saved there. */ | |
13622 | ||
13623 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13624 | ||
13625 | return 0; | |
13626 | } | |
13627 | ||
c6ec2b30 OJ |
13628 | /* Handler for thumb2 load/store multiple instructions. */ |
13629 | ||
13630 | static int | |
4748a9be | 13631 | thumb2_record_ld_st_multiple (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13632 | { |
13633 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13634 | ||
13635 | uint32_t reg_rn, op; | |
13636 | uint32_t register_bits = 0, register_count = 0; | |
13637 | uint32_t index = 0, start_address = 0; | |
13638 | uint32_t record_buf[24], record_buf_mem[48]; | |
13639 | ||
13640 | ULONGEST u_regval = 0; | |
13641 | ||
13642 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13643 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13644 | ||
13645 | if (0 == op || 3 == op) | |
13646 | { | |
13647 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13648 | { |
13649 | /* Handle RFE instruction. */ | |
13650 | record_buf[0] = ARM_PS_REGNUM; | |
13651 | thumb2_insn_r->reg_rec_count = 1; | |
13652 | } | |
c6ec2b30 | 13653 | else |
dda83cd7 SM |
13654 | { |
13655 | /* Handle SRS instruction after reading banked SP. */ | |
13656 | return arm_record_unsupported_insn (thumb2_insn_r); | |
13657 | } | |
c6ec2b30 OJ |
13658 | } |
13659 | else if (1 == op || 2 == op) | |
13660 | { | |
13661 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13662 | { |
13663 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
13664 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13665 | while (register_bits) | |
13666 | { | |
13667 | if (register_bits & 0x00000001) | |
13668 | record_buf[index++] = register_count; | |
13669 | ||
13670 | register_count++; | |
13671 | register_bits = register_bits >> 1; | |
13672 | } | |
13673 | record_buf[index++] = reg_rn; | |
13674 | record_buf[index++] = ARM_PS_REGNUM; | |
13675 | thumb2_insn_r->reg_rec_count = index; | |
13676 | } | |
c6ec2b30 | 13677 | else |
dda83cd7 SM |
13678 | { |
13679 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
13680 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13681 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13682 | while (register_bits) | |
13683 | { | |
13684 | if (register_bits & 0x00000001) | |
13685 | register_count++; | |
13686 | ||
13687 | register_bits = register_bits >> 1; | |
13688 | } | |
13689 | ||
13690 | if (1 == op) | |
13691 | { | |
13692 | /* Start address calculation for LDMDB/LDMEA. */ | |
13693 | start_address = u_regval; | |
13694 | } | |
13695 | else if (2 == op) | |
13696 | { | |
13697 | /* Start address calculation for LDMDB/LDMEA. */ | |
13698 | start_address = u_regval - register_count * 4; | |
13699 | } | |
13700 | ||
13701 | thumb2_insn_r->mem_rec_count = register_count; | |
13702 | while (register_count) | |
13703 | { | |
13704 | record_buf_mem[register_count * 2 - 1] = start_address; | |
13705 | record_buf_mem[register_count * 2 - 2] = 4; | |
13706 | start_address = start_address + 4; | |
13707 | register_count--; | |
13708 | } | |
13709 | record_buf[0] = reg_rn; | |
13710 | record_buf[1] = ARM_PS_REGNUM; | |
13711 | thumb2_insn_r->reg_rec_count = 2; | |
13712 | } | |
c6ec2b30 OJ |
13713 | } |
13714 | ||
13715 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 13716 | record_buf_mem); |
c6ec2b30 | 13717 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 13718 | record_buf); |
c6ec2b30 OJ |
13719 | return ARM_RECORD_SUCCESS; |
13720 | } | |
13721 | ||
13722 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
13723 | instructions. */ | |
13724 | ||
13725 | static int | |
4748a9be | 13726 | thumb2_record_ld_st_dual_ex_tbb (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13727 | { |
13728 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13729 | ||
13730 | uint32_t reg_rd, reg_rn, offset_imm; | |
13731 | uint32_t reg_dest1, reg_dest2; | |
13732 | uint32_t address, offset_addr; | |
13733 | uint32_t record_buf[8], record_buf_mem[8]; | |
13734 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
13735 | |
13736 | ULONGEST u_regval[2]; | |
13737 | ||
13738 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13739 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
13740 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13741 | ||
13742 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13743 | { | |
13744 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
13745 | { |
13746 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13747 | record_buf[0] = reg_dest1; | |
13748 | record_buf[1] = ARM_PS_REGNUM; | |
13749 | thumb2_insn_r->reg_rec_count = 2; | |
13750 | } | |
c6ec2b30 OJ |
13751 | |
13752 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
13753 | { |
13754 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13755 | record_buf[2] = reg_dest2; | |
13756 | thumb2_insn_r->reg_rec_count = 3; | |
13757 | } | |
c6ec2b30 OJ |
13758 | } |
13759 | else | |
13760 | { | |
13761 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13762 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13763 | ||
13764 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
13765 | { |
13766 | /* Handle STREX. */ | |
13767 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13768 | address = u_regval[0] + (offset_imm * 4); | |
13769 | record_buf_mem[0] = 4; | |
13770 | record_buf_mem[1] = address; | |
13771 | thumb2_insn_r->mem_rec_count = 1; | |
13772 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13773 | record_buf[0] = reg_rd; | |
13774 | thumb2_insn_r->reg_rec_count = 1; | |
13775 | } | |
c6ec2b30 | 13776 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
13777 | { |
13778 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13779 | record_buf[0] = reg_rd; | |
13780 | thumb2_insn_r->reg_rec_count = 1; | |
13781 | address = u_regval[0]; | |
13782 | record_buf_mem[1] = address; | |
13783 | ||
13784 | if (4 == op3) | |
13785 | { | |
13786 | /* Handle STREXB. */ | |
13787 | record_buf_mem[0] = 1; | |
13788 | thumb2_insn_r->mem_rec_count = 1; | |
13789 | } | |
13790 | else if (5 == op3) | |
13791 | { | |
13792 | /* Handle STREXH. */ | |
13793 | record_buf_mem[0] = 2 ; | |
13794 | thumb2_insn_r->mem_rec_count = 1; | |
13795 | } | |
13796 | else if (7 == op3) | |
13797 | { | |
13798 | /* Handle STREXD. */ | |
13799 | address = u_regval[0]; | |
13800 | record_buf_mem[0] = 4; | |
13801 | record_buf_mem[2] = 4; | |
13802 | record_buf_mem[3] = address + 4; | |
13803 | thumb2_insn_r->mem_rec_count = 2; | |
13804 | } | |
13805 | } | |
c6ec2b30 | 13806 | else |
dda83cd7 SM |
13807 | { |
13808 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13809 | ||
13810 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
13811 | { | |
13812 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13813 | offset_addr = u_regval[0] + (offset_imm * 4); | |
13814 | else | |
13815 | offset_addr = u_regval[0] - (offset_imm * 4); | |
13816 | ||
13817 | address = offset_addr; | |
13818 | } | |
13819 | else | |
13820 | address = u_regval[0]; | |
13821 | ||
13822 | record_buf_mem[0] = 4; | |
13823 | record_buf_mem[1] = address; | |
13824 | record_buf_mem[2] = 4; | |
13825 | record_buf_mem[3] = address + 4; | |
13826 | thumb2_insn_r->mem_rec_count = 2; | |
13827 | record_buf[0] = reg_rn; | |
13828 | thumb2_insn_r->reg_rec_count = 1; | |
13829 | } | |
c6ec2b30 OJ |
13830 | } |
13831 | ||
13832 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13833 | record_buf); |
c6ec2b30 | 13834 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13835 | record_buf_mem); |
c6ec2b30 OJ |
13836 | return ARM_RECORD_SUCCESS; |
13837 | } | |
13838 | ||
13839 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
13840 | instructions. */ | |
13841 | ||
13842 | static int | |
4748a9be | 13843 | thumb2_record_data_proc_sreg_mimm (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13844 | { |
13845 | uint32_t reg_rd, op; | |
13846 | uint32_t record_buf[8]; | |
13847 | ||
13848 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
13849 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13850 | ||
13851 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
13852 | { | |
13853 | record_buf[0] = ARM_PS_REGNUM; | |
13854 | thumb2_insn_r->reg_rec_count = 1; | |
13855 | } | |
13856 | else | |
13857 | { | |
13858 | record_buf[0] = reg_rd; | |
13859 | record_buf[1] = ARM_PS_REGNUM; | |
13860 | thumb2_insn_r->reg_rec_count = 2; | |
13861 | } | |
13862 | ||
13863 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13864 | record_buf); |
c6ec2b30 OJ |
13865 | return ARM_RECORD_SUCCESS; |
13866 | } | |
13867 | ||
13868 | /* Generic handler for thumb2 instructions which effect destination and PS | |
13869 | registers. */ | |
13870 | ||
13871 | static int | |
4748a9be | 13872 | thumb2_record_ps_dest_generic (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13873 | { |
13874 | uint32_t reg_rd; | |
13875 | uint32_t record_buf[8]; | |
13876 | ||
13877 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13878 | ||
13879 | record_buf[0] = reg_rd; | |
13880 | record_buf[1] = ARM_PS_REGNUM; | |
13881 | thumb2_insn_r->reg_rec_count = 2; | |
13882 | ||
13883 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13884 | record_buf); |
c6ec2b30 OJ |
13885 | return ARM_RECORD_SUCCESS; |
13886 | } | |
13887 | ||
13888 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
13889 | ||
13890 | static int | |
4748a9be | 13891 | thumb2_record_branch_misc_cntrl (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13892 | { |
13893 | uint32_t op, op1, op2; | |
13894 | uint32_t record_buf[8]; | |
13895 | ||
13896 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13897 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
13898 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13899 | ||
13900 | /* Handle MSR insn. */ | |
13901 | if (!(op1 & 0x2) && 0x38 == op) | |
13902 | { | |
13903 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
13904 | { |
13905 | /* CPSR is going to be changed. */ | |
13906 | record_buf[0] = ARM_PS_REGNUM; | |
13907 | thumb2_insn_r->reg_rec_count = 1; | |
13908 | } | |
c6ec2b30 | 13909 | else |
dda83cd7 SM |
13910 | { |
13911 | arm_record_unsupported_insn(thumb2_insn_r); | |
13912 | return -1; | |
13913 | } | |
c6ec2b30 OJ |
13914 | } |
13915 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
13916 | { | |
13917 | /* BLX. */ | |
13918 | record_buf[0] = ARM_PS_REGNUM; | |
13919 | record_buf[1] = ARM_LR_REGNUM; | |
13920 | thumb2_insn_r->reg_rec_count = 2; | |
13921 | } | |
13922 | ||
13923 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13924 | record_buf); |
c6ec2b30 OJ |
13925 | return ARM_RECORD_SUCCESS; |
13926 | } | |
13927 | ||
13928 | /* Handler for thumb2 store single data item instructions. */ | |
13929 | ||
13930 | static int | |
4748a9be | 13931 | thumb2_record_str_single_data (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13932 | { |
13933 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13934 | ||
13935 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
13936 | uint32_t address, offset_addr; | |
13937 | uint32_t record_buf[8], record_buf_mem[8]; | |
13938 | uint32_t op1, op2; | |
13939 | ||
13940 | ULONGEST u_regval[2]; | |
13941 | ||
13942 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
13943 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
13944 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13945 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13946 | ||
13947 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13948 | { | |
13949 | /* T2 encoding. */ | |
13950 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
13951 | offset_addr = u_regval[0] + offset_imm; | |
13952 | address = offset_addr; | |
13953 | } | |
13954 | else | |
13955 | { | |
13956 | /* T3 encoding. */ | |
13957 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
13958 | { |
13959 | /* Handle STRB (register). */ | |
13960 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13961 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
13962 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
13963 | offset_addr = u_regval[1] << shift_imm; | |
13964 | address = u_regval[0] + offset_addr; | |
13965 | } | |
c6ec2b30 | 13966 | else |
dda83cd7 SM |
13967 | { |
13968 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13969 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
13970 | { | |
13971 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
13972 | offset_addr = u_regval[0] + offset_imm; | |
13973 | else | |
13974 | offset_addr = u_regval[0] - offset_imm; | |
13975 | ||
13976 | address = offset_addr; | |
13977 | } | |
13978 | else | |
13979 | address = u_regval[0]; | |
13980 | } | |
c6ec2b30 OJ |
13981 | } |
13982 | ||
13983 | switch (op1) | |
13984 | { | |
13985 | /* Store byte instructions. */ | |
13986 | case 4: | |
13987 | case 0: | |
dda83cd7 SM |
13988 | record_buf_mem[0] = 1; |
13989 | break; | |
c6ec2b30 OJ |
13990 | /* Store half word instructions. */ |
13991 | case 1: | |
13992 | case 5: | |
dda83cd7 SM |
13993 | record_buf_mem[0] = 2; |
13994 | break; | |
c6ec2b30 OJ |
13995 | /* Store word instructions. */ |
13996 | case 2: | |
13997 | case 6: | |
dda83cd7 SM |
13998 | record_buf_mem[0] = 4; |
13999 | break; | |
c6ec2b30 OJ |
14000 | |
14001 | default: | |
dda83cd7 SM |
14002 | gdb_assert_not_reached ("no decoding pattern found"); |
14003 | break; | |
c6ec2b30 OJ |
14004 | } |
14005 | ||
14006 | record_buf_mem[1] = address; | |
14007 | thumb2_insn_r->mem_rec_count = 1; | |
14008 | record_buf[0] = reg_rn; | |
14009 | thumb2_insn_r->reg_rec_count = 1; | |
14010 | ||
14011 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14012 | record_buf); |
c6ec2b30 | 14013 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 14014 | record_buf_mem); |
c6ec2b30 OJ |
14015 | return ARM_RECORD_SUCCESS; |
14016 | } | |
14017 | ||
14018 | /* Handler for thumb2 load memory hints instructions. */ | |
14019 | ||
14020 | static int | |
4748a9be | 14021 | thumb2_record_ld_mem_hints (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
14022 | { |
14023 | uint32_t record_buf[8]; | |
14024 | uint32_t reg_rt, reg_rn; | |
14025 | ||
14026 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14027 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
14028 | ||
14029 | if (ARM_PC_REGNUM != reg_rt) | |
14030 | { | |
14031 | record_buf[0] = reg_rt; | |
14032 | record_buf[1] = reg_rn; | |
14033 | record_buf[2] = ARM_PS_REGNUM; | |
14034 | thumb2_insn_r->reg_rec_count = 3; | |
14035 | ||
14036 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14037 | record_buf); |
c6ec2b30 OJ |
14038 | return ARM_RECORD_SUCCESS; |
14039 | } | |
14040 | ||
14041 | return ARM_RECORD_FAILURE; | |
14042 | } | |
14043 | ||
14044 | /* Handler for thumb2 load word instructions. */ | |
14045 | ||
14046 | static int | |
4748a9be | 14047 | thumb2_record_ld_word (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 | 14048 | { |
c6ec2b30 OJ |
14049 | uint32_t record_buf[8]; |
14050 | ||
14051 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14052 | record_buf[1] = ARM_PS_REGNUM; | |
14053 | thumb2_insn_r->reg_rec_count = 2; | |
14054 | ||
14055 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14056 | record_buf); |
c6ec2b30 OJ |
14057 | return ARM_RECORD_SUCCESS; |
14058 | } | |
14059 | ||
14060 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
14061 | divide instructions. */ | |
14062 | ||
14063 | static int | |
4748a9be | 14064 | thumb2_record_lmul_lmla_div (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
14065 | { |
14066 | uint32_t opcode1 = 0, opcode2 = 0; | |
14067 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
14068 | |
14069 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
14070 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
14071 | ||
14072 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
14073 | { | |
14074 | /* Handle SMULL, UMULL, SMULAL. */ | |
14075 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
14076 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
14077 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14078 | record_buf[2] = ARM_PS_REGNUM; | |
14079 | thumb2_insn_r->reg_rec_count = 3; | |
14080 | } | |
14081 | else if (1 == opcode1 || 3 == opcode2) | |
14082 | { | |
14083 | /* Handle SDIV and UDIV. */ | |
14084 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
14085 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14086 | record_buf[2] = ARM_PS_REGNUM; | |
14087 | thumb2_insn_r->reg_rec_count = 3; | |
14088 | } | |
14089 | else | |
14090 | return ARM_RECORD_FAILURE; | |
14091 | ||
14092 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14093 | record_buf); |
c6ec2b30 OJ |
14094 | return ARM_RECORD_SUCCESS; |
14095 | } | |
14096 | ||
60cc5e93 OJ |
14097 | /* Record handler for thumb32 coprocessor instructions. */ |
14098 | ||
14099 | static int | |
4748a9be | 14100 | thumb2_record_coproc_insn (arm_insn_decode_record *thumb2_insn_r) |
60cc5e93 OJ |
14101 | { |
14102 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
14103 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
14104 | else | |
14105 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
14106 | } | |
14107 | ||
1e1b6563 OJ |
14108 | /* Record handler for advance SIMD structure load/store instructions. */ |
14109 | ||
14110 | static int | |
4748a9be | 14111 | thumb2_record_asimd_struct_ld_st (arm_insn_decode_record *thumb2_insn_r) |
1e1b6563 OJ |
14112 | { |
14113 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
14114 | uint32_t l_bit, a_bit, b_bits; | |
14115 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 14116 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
14117 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
14118 | uint8_t f_ebytes; | |
14119 | ||
14120 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
14121 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
14122 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
14123 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
14124 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
14125 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
14126 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
14127 | f_elem = 8 / f_ebytes; |
14128 | ||
14129 | if (!l_bit) | |
14130 | { | |
14131 | ULONGEST u_regval = 0; | |
14132 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
14133 | address = u_regval; | |
14134 | ||
14135 | if (!a_bit) | |
dda83cd7 SM |
14136 | { |
14137 | /* Handle VST1. */ | |
14138 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
14139 | { | |
14140 | if (b_bits == 0x07) | |
14141 | bf_regs = 1; | |
14142 | else if (b_bits == 0x0a) | |
14143 | bf_regs = 2; | |
14144 | else if (b_bits == 0x06) | |
14145 | bf_regs = 3; | |
14146 | else if (b_bits == 0x02) | |
14147 | bf_regs = 4; | |
14148 | else | |
14149 | bf_regs = 0; | |
14150 | ||
14151 | for (index_r = 0; index_r < bf_regs; index_r++) | |
14152 | { | |
14153 | for (index_e = 0; index_e < f_elem; index_e++) | |
14154 | { | |
14155 | record_buf_mem[index_m++] = f_ebytes; | |
14156 | record_buf_mem[index_m++] = address; | |
14157 | address = address + f_ebytes; | |
14158 | thumb2_insn_r->mem_rec_count += 1; | |
14159 | } | |
14160 | } | |
14161 | } | |
14162 | /* Handle VST2. */ | |
14163 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
14164 | { | |
14165 | if (b_bits == 0x09 || b_bits == 0x08) | |
14166 | bf_regs = 1; | |
14167 | else if (b_bits == 0x03) | |
14168 | bf_regs = 2; | |
14169 | else | |
14170 | bf_regs = 0; | |
14171 | ||
14172 | for (index_r = 0; index_r < bf_regs; index_r++) | |
14173 | for (index_e = 0; index_e < f_elem; index_e++) | |
14174 | { | |
14175 | for (loop_t = 0; loop_t < 2; loop_t++) | |
14176 | { | |
14177 | record_buf_mem[index_m++] = f_ebytes; | |
14178 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14179 | thumb2_insn_r->mem_rec_count += 1; | |
14180 | } | |
14181 | address = address + (2 * f_ebytes); | |
14182 | } | |
14183 | } | |
14184 | /* Handle VST3. */ | |
14185 | else if ((b_bits & 0x0e) == 0x04) | |
14186 | { | |
14187 | for (index_e = 0; index_e < f_elem; index_e++) | |
14188 | { | |
14189 | for (loop_t = 0; loop_t < 3; loop_t++) | |
14190 | { | |
14191 | record_buf_mem[index_m++] = f_ebytes; | |
14192 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14193 | thumb2_insn_r->mem_rec_count += 1; | |
14194 | } | |
14195 | address = address + (3 * f_ebytes); | |
14196 | } | |
14197 | } | |
14198 | /* Handle VST4. */ | |
14199 | else if (!(b_bits & 0x0e)) | |
14200 | { | |
14201 | for (index_e = 0; index_e < f_elem; index_e++) | |
14202 | { | |
14203 | for (loop_t = 0; loop_t < 4; loop_t++) | |
14204 | { | |
14205 | record_buf_mem[index_m++] = f_ebytes; | |
14206 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
14207 | thumb2_insn_r->mem_rec_count += 1; | |
14208 | } | |
14209 | address = address + (4 * f_ebytes); | |
14210 | } | |
14211 | } | |
14212 | } | |
1e1b6563 | 14213 | else |
dda83cd7 SM |
14214 | { |
14215 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
14216 | ||
14217 | if (bft_size == 0x00) | |
14218 | f_ebytes = 1; | |
14219 | else if (bft_size == 0x01) | |
14220 | f_ebytes = 2; | |
14221 | else if (bft_size == 0x02) | |
14222 | f_ebytes = 4; | |
14223 | else | |
14224 | f_ebytes = 0; | |
14225 | ||
14226 | /* Handle VST1. */ | |
14227 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
14228 | thumb2_insn_r->mem_rec_count = 1; | |
14229 | /* Handle VST2. */ | |
14230 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
14231 | thumb2_insn_r->mem_rec_count = 2; | |
14232 | /* Handle VST3. */ | |
14233 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
14234 | thumb2_insn_r->mem_rec_count = 3; | |
14235 | /* Handle VST4. */ | |
14236 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
14237 | thumb2_insn_r->mem_rec_count = 4; | |
14238 | ||
14239 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
14240 | { | |
14241 | record_buf_mem[index_m] = f_ebytes; | |
14242 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
14243 | } | |
14244 | } | |
1e1b6563 OJ |
14245 | } |
14246 | else | |
14247 | { | |
14248 | if (!a_bit) | |
dda83cd7 SM |
14249 | { |
14250 | /* Handle VLD1. */ | |
14251 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
14252 | thumb2_insn_r->reg_rec_count = 1; | |
14253 | /* Handle VLD2. */ | |
14254 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
14255 | thumb2_insn_r->reg_rec_count = 2; | |
14256 | /* Handle VLD3. */ | |
14257 | else if ((b_bits & 0x0e) == 0x04) | |
14258 | thumb2_insn_r->reg_rec_count = 3; | |
14259 | /* Handle VLD4. */ | |
14260 | else if (!(b_bits & 0x0e)) | |
14261 | thumb2_insn_r->reg_rec_count = 4; | |
14262 | } | |
1e1b6563 | 14263 | else |
dda83cd7 SM |
14264 | { |
14265 | /* Handle VLD1. */ | |
14266 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
14267 | thumb2_insn_r->reg_rec_count = 1; | |
14268 | /* Handle VLD2. */ | |
14269 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
14270 | thumb2_insn_r->reg_rec_count = 2; | |
14271 | /* Handle VLD3. */ | |
14272 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
14273 | thumb2_insn_r->reg_rec_count = 3; | |
14274 | /* Handle VLD4. */ | |
14275 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
14276 | thumb2_insn_r->reg_rec_count = 4; | |
14277 | ||
14278 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
14279 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
14280 | } | |
1e1b6563 OJ |
14281 | } |
14282 | ||
14283 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
14284 | { | |
14285 | record_buf[index_r] = reg_rn; | |
14286 | thumb2_insn_r->reg_rec_count += 1; | |
14287 | } | |
14288 | ||
14289 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14290 | record_buf); |
1e1b6563 | 14291 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 14292 | record_buf_mem); |
1e1b6563 OJ |
14293 | return 0; |
14294 | } | |
14295 | ||
c6ec2b30 OJ |
14296 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
14297 | ||
14298 | static unsigned int | |
4748a9be | 14299 | thumb2_record_decode_insn_handler (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
14300 | { |
14301 | uint32_t op, op1, op2; | |
14302 | ||
14303 | op = bit (thumb2_insn_r->arm_insn, 15); | |
14304 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
14305 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
14306 | ||
14307 | if (op1 == 0x01) | |
14308 | { | |
14309 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
14310 | { |
14311 | /* Load/store multiple instruction. */ | |
14312 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
14313 | } | |
b121eeb9 | 14314 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
14315 | { |
14316 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
14317 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
14318 | } | |
b121eeb9 | 14319 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
14320 | { |
14321 | /* Data-processing (shifted register). */ | |
14322 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14323 | } | |
c6ec2b30 | 14324 | else if (op2 & 0x40) |
dda83cd7 SM |
14325 | { |
14326 | /* Co-processor instructions. */ | |
14327 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14328 | } | |
c6ec2b30 OJ |
14329 | } |
14330 | else if (op1 == 0x02) | |
14331 | { | |
14332 | if (op) | |
dda83cd7 SM |
14333 | { |
14334 | /* Branches and miscellaneous control instructions. */ | |
14335 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
14336 | } | |
c6ec2b30 | 14337 | else if (op2 & 0x20) |
dda83cd7 SM |
14338 | { |
14339 | /* Data-processing (plain binary immediate) instruction. */ | |
14340 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14341 | } | |
c6ec2b30 | 14342 | else |
dda83cd7 SM |
14343 | { |
14344 | /* Data-processing (modified immediate). */ | |
14345 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14346 | } | |
c6ec2b30 OJ |
14347 | } |
14348 | else if (op1 == 0x03) | |
14349 | { | |
14350 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
14351 | { |
14352 | /* Store single data item. */ | |
14353 | return thumb2_record_str_single_data (thumb2_insn_r); | |
14354 | } | |
c6ec2b30 | 14355 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
14356 | { |
14357 | /* Advanced SIMD or structure load/store instructions. */ | |
14358 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
14359 | } | |
c6ec2b30 | 14360 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
14361 | { |
14362 | /* Load byte, memory hints instruction. */ | |
14363 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14364 | } | |
c6ec2b30 | 14365 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
14366 | { |
14367 | /* Load halfword, memory hints instruction. */ | |
14368 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14369 | } | |
c6ec2b30 | 14370 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
14371 | { |
14372 | /* Load word instruction. */ | |
14373 | return thumb2_record_ld_word (thumb2_insn_r); | |
14374 | } | |
c6ec2b30 | 14375 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
14376 | { |
14377 | /* Data-processing (register) instruction. */ | |
14378 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14379 | } | |
c6ec2b30 | 14380 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
14381 | { |
14382 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
14383 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14384 | } | |
c6ec2b30 | 14385 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
14386 | { |
14387 | /* Long multiply, long multiply accumulate, and divide. */ | |
14388 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
14389 | } | |
c6ec2b30 | 14390 | else if (op2 & 0x40) |
dda83cd7 SM |
14391 | { |
14392 | /* Co-processor instructions. */ | |
14393 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14394 | } | |
c6ec2b30 OJ |
14395 | } |
14396 | ||
14397 | return -1; | |
14398 | } | |
72508ac0 | 14399 | |
ffdbe864 | 14400 | namespace { |
0833fb8f | 14401 | /* Abstract instruction reader. */ |
728a7913 | 14402 | |
0833fb8f | 14403 | class abstract_instruction_reader |
728a7913 YQ |
14404 | { |
14405 | public: | |
0833fb8f LM |
14406 | /* Read one instruction of size LEN from address MEMADDR and using |
14407 | BYTE_ORDER endianness. */ | |
728a7913 | 14408 | |
0833fb8f LM |
14409 | virtual ULONGEST read (CORE_ADDR memaddr, const size_t len, |
14410 | enum bfd_endian byte_order) = 0; | |
728a7913 YQ |
14411 | }; |
14412 | ||
14413 | /* Instruction reader from real target. */ | |
14414 | ||
0833fb8f | 14415 | class instruction_reader : public abstract_instruction_reader |
728a7913 YQ |
14416 | { |
14417 | public: | |
0833fb8f LM |
14418 | ULONGEST read (CORE_ADDR memaddr, const size_t len, |
14419 | enum bfd_endian byte_order) override | |
728a7913 | 14420 | { |
0833fb8f | 14421 | return read_code_unsigned_integer (memaddr, len, byte_order); |
728a7913 YQ |
14422 | } |
14423 | }; | |
14424 | ||
ffdbe864 YQ |
14425 | } // namespace |
14426 | ||
4748a9be | 14427 | typedef int (*sti_arm_hdl_fp_t) (arm_insn_decode_record*); |
72508ac0 PO |
14428 | |
14429 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
14430 | dispatch it. */ | |
14431 | ||
14432 | static int | |
0833fb8f | 14433 | decode_insn (abstract_instruction_reader &reader, |
4748a9be | 14434 | arm_insn_decode_record *arm_record, |
728a7913 | 14435 | record_type_t record_type, uint32_t insn_size) |
72508ac0 PO |
14436 | { |
14437 | ||
01e57735 YQ |
14438 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
14439 | instruction. */ | |
0fa9c223 | 14440 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
14441 | { |
14442 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
14443 | arm_record_data_proc_imm, /* 001. */ | |
14444 | arm_record_ld_st_imm_offset, /* 010. */ | |
14445 | arm_record_ld_st_reg_offset, /* 011. */ | |
14446 | arm_record_ld_st_multiple, /* 100. */ | |
14447 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 14448 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
14449 | arm_record_coproc_data_proc /* 111. */ |
14450 | }; | |
14451 | ||
01e57735 YQ |
14452 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
14453 | instruction. */ | |
0fa9c223 | 14454 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
14455 | { \ |
14456 | thumb_record_shift_add_sub, /* 000. */ | |
14457 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
14458 | thumb_record_ld_st_reg_offset, /* 010. */ | |
14459 | thumb_record_ld_st_imm_offset, /* 011. */ | |
14460 | thumb_record_ld_st_stack, /* 100. */ | |
14461 | thumb_record_misc, /* 101. */ | |
14462 | thumb_record_ldm_stm_swi, /* 110. */ | |
14463 | thumb_record_branch /* 111. */ | |
14464 | }; | |
14465 | ||
14466 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
14467 | uint32_t insn_id = 0; | |
0833fb8f LM |
14468 | enum bfd_endian code_endian |
14469 | = gdbarch_byte_order_for_code (arm_record->gdbarch); | |
14470 | arm_record->arm_insn | |
14471 | = reader.read (arm_record->this_addr, insn_size, code_endian); | |
72508ac0 | 14472 | |
0833fb8f | 14473 | if (ARM_RECORD == record_type) |
72508ac0 PO |
14474 | { |
14475 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
14476 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
14477 | |
14478 | if (arm_record->cond == 0xf) | |
14479 | ret = arm_record_extension_space (arm_record); | |
14480 | else | |
01e57735 | 14481 | { |
ca92db2d YQ |
14482 | /* If this insn has fallen into extension space |
14483 | then we need not decode it anymore. */ | |
01e57735 YQ |
14484 | ret = arm_handle_insn[insn_id] (arm_record); |
14485 | } | |
ca92db2d YQ |
14486 | if (ret != ARM_RECORD_SUCCESS) |
14487 | { | |
14488 | arm_record_unsupported_insn (arm_record); | |
14489 | ret = -1; | |
14490 | } | |
72508ac0 PO |
14491 | } |
14492 | else if (THUMB_RECORD == record_type) | |
14493 | { | |
14494 | /* As thumb does not have condition codes, we set negative. */ | |
14495 | arm_record->cond = -1; | |
14496 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
14497 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
14498 | if (ret != ARM_RECORD_SUCCESS) |
14499 | { | |
14500 | arm_record_unsupported_insn (arm_record); | |
14501 | ret = -1; | |
14502 | } | |
72508ac0 PO |
14503 | } |
14504 | else if (THUMB2_RECORD == record_type) | |
14505 | { | |
c6ec2b30 OJ |
14506 | /* As thumb does not have condition codes, we set negative. */ |
14507 | arm_record->cond = -1; | |
14508 | ||
14509 | /* Swap first half of 32bit thumb instruction with second half. */ | |
14510 | arm_record->arm_insn | |
01e57735 | 14511 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 14512 | |
ca92db2d | 14513 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 14514 | |
ca92db2d | 14515 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
14516 | { |
14517 | arm_record_unsupported_insn (arm_record); | |
14518 | ret = -1; | |
14519 | } | |
72508ac0 PO |
14520 | } |
14521 | else | |
14522 | { | |
14523 | /* Throw assertion. */ | |
14524 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
14525 | } | |
14526 | ||
14527 | return ret; | |
14528 | } | |
14529 | ||
b121eeb9 YQ |
14530 | #if GDB_SELF_TEST |
14531 | namespace selftests { | |
14532 | ||
0833fb8f LM |
14533 | /* Instruction reader class for selftests. |
14534 | ||
14535 | For 16-bit Thumb instructions, an array of uint16_t should be used. | |
b121eeb9 | 14536 | |
0833fb8f LM |
14537 | For 32-bit Thumb instructions and regular 32-bit Arm instructions, an array |
14538 | of uint32_t should be used. */ | |
14539 | ||
14540 | template<typename T> | |
14541 | class instruction_reader_selftest : public abstract_instruction_reader | |
b121eeb9 YQ |
14542 | { |
14543 | public: | |
14544 | template<size_t SIZE> | |
0833fb8f LM |
14545 | instruction_reader_selftest (const T (&insns)[SIZE]) |
14546 | : m_insns (insns), m_insns_size (SIZE) | |
b121eeb9 YQ |
14547 | {} |
14548 | ||
0833fb8f LM |
14549 | ULONGEST read (CORE_ADDR memaddr, const size_t length, |
14550 | enum bfd_endian byte_order) override | |
b121eeb9 | 14551 | { |
0833fb8f LM |
14552 | SELF_CHECK (length == sizeof (T)); |
14553 | SELF_CHECK (memaddr % sizeof (T) == 0); | |
14554 | SELF_CHECK ((memaddr / sizeof (T)) < m_insns_size); | |
b121eeb9 | 14555 | |
0833fb8f | 14556 | return m_insns[memaddr / sizeof (T)]; |
b121eeb9 YQ |
14557 | } |
14558 | ||
14559 | private: | |
0833fb8f LM |
14560 | const T *m_insns; |
14561 | const size_t m_insns_size; | |
b121eeb9 YQ |
14562 | }; |
14563 | ||
14564 | static void | |
14565 | arm_record_test (void) | |
14566 | { | |
14567 | struct gdbarch_info info; | |
b121eeb9 YQ |
14568 | info.bfd_arch_info = bfd_scan_arch ("arm"); |
14569 | ||
14570 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14571 | ||
14572 | SELF_CHECK (gdbarch != NULL); | |
14573 | ||
14574 | /* 16-bit Thumb instructions. */ | |
14575 | { | |
4748a9be | 14576 | arm_insn_decode_record arm_record; |
b121eeb9 | 14577 | |
4748a9be | 14578 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14579 | arm_record.gdbarch = gdbarch; |
14580 | ||
0833fb8f LM |
14581 | /* Use the endian-free representation of the instructions here. The test |
14582 | will handle endianness conversions. */ | |
b121eeb9 YQ |
14583 | static const uint16_t insns[] = { |
14584 | /* db b2 uxtb r3, r3 */ | |
14585 | 0xb2db, | |
14586 | /* cd 58 ldr r5, [r1, r3] */ | |
14587 | 0x58cd, | |
14588 | }; | |
14589 | ||
0833fb8f | 14590 | instruction_reader_selftest<uint16_t> reader (insns); |
b121eeb9 YQ |
14591 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
14592 | THUMB_INSN_SIZE_BYTES); | |
14593 | ||
14594 | SELF_CHECK (ret == 0); | |
14595 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14596 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14597 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
14598 | ||
14599 | arm_record.this_addr += 2; | |
14600 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
14601 | THUMB_INSN_SIZE_BYTES); | |
14602 | ||
14603 | SELF_CHECK (ret == 0); | |
14604 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14605 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14606 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
14607 | } | |
14608 | ||
14609 | /* 32-bit Thumb-2 instructions. */ | |
14610 | { | |
4748a9be | 14611 | arm_insn_decode_record arm_record; |
b121eeb9 | 14612 | |
4748a9be | 14613 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14614 | arm_record.gdbarch = gdbarch; |
14615 | ||
0833fb8f LM |
14616 | /* Use the endian-free representation of the instruction here. The test |
14617 | will handle endianness conversions. */ | |
14618 | static const uint32_t insns[] = { | |
14619 | /* mrc 15, 0, r7, cr13, cr0, {3} */ | |
14620 | 0x7f70ee1d, | |
b121eeb9 YQ |
14621 | }; |
14622 | ||
0833fb8f | 14623 | instruction_reader_selftest<uint32_t> reader (insns); |
b121eeb9 YQ |
14624 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
14625 | THUMB2_INSN_SIZE_BYTES); | |
14626 | ||
14627 | SELF_CHECK (ret == 0); | |
14628 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14629 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14630 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
14631 | } | |
0833fb8f LM |
14632 | |
14633 | /* 32-bit instructions. */ | |
14634 | { | |
14635 | arm_insn_decode_record arm_record; | |
14636 | ||
14637 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); | |
14638 | arm_record.gdbarch = gdbarch; | |
14639 | ||
14640 | /* Use the endian-free representation of the instruction here. The test | |
14641 | will handle endianness conversions. */ | |
14642 | static const uint32_t insns[] = { | |
14643 | /* mov r5, r0 */ | |
14644 | 0xe1a05000, | |
14645 | }; | |
14646 | ||
14647 | instruction_reader_selftest<uint32_t> reader (insns); | |
14648 | int ret = decode_insn (reader, &arm_record, ARM_RECORD, | |
14649 | ARM_INSN_SIZE_BYTES); | |
14650 | ||
14651 | SELF_CHECK (ret == 0); | |
14652 | } | |
b121eeb9 | 14653 | } |
9ecab40c SM |
14654 | |
14655 | /* Instruction reader from manually cooked instruction sequences. */ | |
14656 | ||
14657 | class test_arm_instruction_reader : public arm_instruction_reader | |
14658 | { | |
14659 | public: | |
14660 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
14661 | : m_insns (insns) | |
14662 | {} | |
14663 | ||
14664 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
14665 | { | |
14666 | SELF_CHECK (memaddr % 4 == 0); | |
14667 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
14668 | ||
14669 | return m_insns[memaddr / 4]; | |
14670 | } | |
14671 | ||
14672 | private: | |
14673 | const gdb::array_view<const uint32_t> m_insns; | |
14674 | }; | |
14675 | ||
14676 | static void | |
14677 | arm_analyze_prologue_test () | |
14678 | { | |
14679 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
14680 | { | |
14681 | struct gdbarch_info info; | |
9ecab40c SM |
14682 | info.byte_order = endianness; |
14683 | info.byte_order_for_code = endianness; | |
14684 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
14685 | ||
14686 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14687 | ||
14688 | SELF_CHECK (gdbarch != NULL); | |
14689 | ||
14690 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
14691 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
14692 | UBSan. */ | |
14693 | const uint32_t insns[] = { | |
14694 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
14695 | 0xe1a05000, /* mov r5, r0 */ | |
14696 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
14697 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
14698 | }; | |
14699 | ||
14700 | test_arm_instruction_reader mem_reader (insns); | |
14701 | arm_prologue_cache cache; | |
0824193f | 14702 | arm_cache_init (&cache, gdbarch); |
9ecab40c SM |
14703 | |
14704 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
14705 | } | |
14706 | } | |
14707 | ||
b121eeb9 YQ |
14708 | } // namespace selftests |
14709 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
14710 | |
14711 | /* Cleans up local record registers and memory allocations. */ | |
14712 | ||
14713 | static void | |
4748a9be | 14714 | deallocate_reg_mem (arm_insn_decode_record *record) |
72508ac0 PO |
14715 | { |
14716 | xfree (record->arm_regs); | |
14717 | xfree (record->arm_mems); | |
14718 | } | |
14719 | ||
14720 | ||
01e57735 | 14721 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
14722 | memory that will be changed in current instruction to record_arch_list". |
14723 | Return -1 if something is wrong. */ | |
14724 | ||
14725 | int | |
01e57735 YQ |
14726 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
14727 | CORE_ADDR insn_addr) | |
72508ac0 PO |
14728 | { |
14729 | ||
72508ac0 PO |
14730 | uint32_t no_of_rec = 0; |
14731 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
14732 | ULONGEST t_bit = 0, insn_id = 0; | |
14733 | ||
14734 | ULONGEST u_regval = 0; | |
14735 | ||
4748a9be | 14736 | arm_insn_decode_record arm_record; |
72508ac0 | 14737 | |
4748a9be | 14738 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
72508ac0 PO |
14739 | arm_record.regcache = regcache; |
14740 | arm_record.this_addr = insn_addr; | |
14741 | arm_record.gdbarch = gdbarch; | |
14742 | ||
14743 | ||
14744 | if (record_debug > 1) | |
14745 | { | |
6cb06a8c TT |
14746 | gdb_printf (gdb_stdlog, "Process record: arm_process_record " |
14747 | "addr = %s\n", | |
14748 | paddress (gdbarch, arm_record.this_addr)); | |
72508ac0 PO |
14749 | } |
14750 | ||
728a7913 | 14751 | instruction_reader reader; |
0833fb8f LM |
14752 | enum bfd_endian code_endian |
14753 | = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
14754 | arm_record.arm_insn | |
14755 | = reader.read (arm_record.this_addr, 2, code_endian); | |
72508ac0 PO |
14756 | |
14757 | /* Check the insn, whether it is thumb or arm one. */ | |
14758 | ||
14759 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
14760 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
14761 | ||
14762 | ||
14763 | if (!(u_regval & t_bit)) | |
14764 | { | |
14765 | /* We are decoding arm insn. */ | |
728a7913 | 14766 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
14767 | } |
14768 | else | |
14769 | { | |
14770 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
14771 | /* is it thumb2 insn? */ | |
14772 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 14773 | { |
728a7913 | 14774 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
14775 | THUMB2_INSN_SIZE_BYTES); |
14776 | } | |
72508ac0 | 14777 | else |
01e57735 YQ |
14778 | { |
14779 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
14780 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
14781 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 14782 | } |
72508ac0 PO |
14783 | } |
14784 | ||
14785 | if (0 == ret) | |
14786 | { | |
14787 | /* Record registers. */ | |
25ea693b | 14788 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 14789 | if (arm_record.arm_regs) |
01e57735 YQ |
14790 | { |
14791 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
14792 | { | |
14793 | if (record_full_arch_list_add_reg | |
25ea693b | 14794 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
14795 | ret = -1; |
14796 | } | |
14797 | } | |
72508ac0 PO |
14798 | /* Record memories. */ |
14799 | if (arm_record.arm_mems) | |
01e57735 YQ |
14800 | { |
14801 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
14802 | { | |
14803 | if (record_full_arch_list_add_mem | |
14804 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 14805 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
14806 | ret = -1; |
14807 | } | |
14808 | } | |
72508ac0 | 14809 | |
25ea693b | 14810 | if (record_full_arch_list_add_end ()) |
01e57735 | 14811 | ret = -1; |
72508ac0 PO |
14812 | } |
14813 | ||
14814 | ||
14815 | deallocate_reg_mem (&arm_record); | |
14816 | ||
14817 | return ret; | |
14818 | } | |
d105cce5 AH |
14819 | |
14820 | /* See arm-tdep.h. */ | |
14821 | ||
14822 | const target_desc * | |
92d48a1e | 14823 | arm_read_description (arm_fp_type fp_type, bool tls) |
d105cce5 | 14824 | { |
92d48a1e | 14825 | struct target_desc *tdesc = tdesc_arm_list[fp_type][tls]; |
d105cce5 AH |
14826 | |
14827 | if (tdesc == nullptr) | |
14828 | { | |
92d48a1e JB |
14829 | tdesc = arm_create_target_description (fp_type, tls); |
14830 | tdesc_arm_list[fp_type][tls] = tdesc; | |
d105cce5 AH |
14831 | } |
14832 | ||
14833 | return tdesc; | |
14834 | } | |
14835 | ||
14836 | /* See arm-tdep.h. */ | |
14837 | ||
14838 | const target_desc * | |
14839 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
14840 | { | |
14841 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
14842 | ||
14843 | if (tdesc == nullptr) | |
14844 | { | |
14845 | tdesc = arm_create_mprofile_target_description (m_type); | |
14846 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
14847 | } | |
14848 | ||
14849 | return tdesc; | |
14850 | } |