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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
4a94e368 | 3 | Copyright (C) 1988-2022 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
a01567f4 | 41 | #include "dwarf2.h" |
82ca8957 | 42 | #include "dwarf2/frame.h" |
4de283e4 TT |
43 | #include "gdbtypes.h" |
44 | #include "prologue-value.h" | |
45 | #include "remote.h" | |
46 | #include "target-descriptions.h" | |
47 | #include "user-regs.h" | |
48 | #include "observable.h" | |
5f661e03 | 49 | #include "count-one-bits.h" |
4de283e4 | 50 | |
d55e5aa6 | 51 | #include "arch/arm.h" |
4de283e4 | 52 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 53 | #include "arm-tdep.h" |
4de283e4 TT |
54 | #include "gdb/sim-arm.h" |
55 | ||
d55e5aa6 | 56 | #include "elf-bfd.h" |
4de283e4 | 57 | #include "coff/internal.h" |
d55e5aa6 | 58 | #include "elf/arm.h" |
4de283e4 | 59 | |
4de283e4 TT |
60 | #include "record.h" |
61 | #include "record-full.h" | |
62 | #include <algorithm> | |
63 | ||
c2fd7fae AKS |
64 | #include "producer.h" |
65 | ||
b121eeb9 | 66 | #if GDB_SELF_TEST |
268a13a5 | 67 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
68 | #endif |
69 | ||
491144b5 | 70 | static bool arm_debug; |
6529d2dd | 71 | |
7cb6d92a SM |
72 | /* Print an "arm" debug statement. */ |
73 | ||
74 | #define arm_debug_printf(fmt, ...) \ | |
75 | debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__) | |
76 | ||
082fc60d RE |
77 | /* Macros for setting and testing a bit in a minimal symbol that marks |
78 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 79 | is used for this purpose. |
082fc60d RE |
80 | |
81 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 82 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 83 | |
0963b4bd | 84 | #define MSYMBOL_SET_SPECIAL(msym) \ |
e165fcef | 85 | (msym)->set_target_flag_1 (true) |
082fc60d RE |
86 | |
87 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
e165fcef | 88 | (msym)->target_flag_1 () |
082fc60d | 89 | |
60c5725c DJ |
90 | struct arm_mapping_symbol |
91 | { | |
227031b2 | 92 | CORE_ADDR value; |
60c5725c | 93 | char type; |
54cc7474 SM |
94 | |
95 | bool operator< (const arm_mapping_symbol &other) const | |
96 | { return this->value < other.value; } | |
60c5725c | 97 | }; |
54cc7474 SM |
98 | |
99 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 100 | |
bd5766ec | 101 | struct arm_per_bfd |
60c5725c | 102 | { |
bd5766ec | 103 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
104 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
105 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
106 | {} |
107 | ||
bd5766ec | 108 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
109 | |
110 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
111 | ||
112 | The format is an array of vectors of arm_mapping_symbols, there is one | |
113 | vector for each section of the objfile (the array is index by BFD section | |
114 | index). | |
115 | ||
116 | For each section, the vector of arm_mapping_symbol is sorted by | |
117 | symbol value (address). */ | |
118 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
119 | |
120 | /* For each corresponding element of section_maps above, is this vector | |
121 | sorted. */ | |
122 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
123 | }; |
124 | ||
bd5766ec LM |
125 | /* Per-bfd data used for mapping symbols. */ |
126 | static bfd_key<arm_per_bfd> arm_bfd_data_key; | |
1b7f24cd | 127 | |
afd7eef0 RE |
128 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
129 | static struct cmd_list_element *setarmcmdlist = NULL; | |
130 | static struct cmd_list_element *showarmcmdlist = NULL; | |
131 | ||
fd50bc42 RE |
132 | /* The type of floating-point to use. Keep this in sync with enum |
133 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 134 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
135 | { |
136 | "auto", | |
137 | "softfpa", | |
138 | "fpa", | |
139 | "softvfp", | |
28e97307 DJ |
140 | "vfp", |
141 | NULL | |
fd50bc42 RE |
142 | }; |
143 | ||
144 | /* A variable that can be configured by the user. */ | |
145 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
146 | static const char *current_fp_model = "auto"; | |
147 | ||
28e97307 | 148 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 149 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
150 | { |
151 | "auto", | |
152 | "APCS", | |
153 | "AAPCS", | |
154 | NULL | |
155 | }; | |
156 | ||
157 | /* A variable that can be configured by the user. */ | |
158 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
159 | static const char *arm_abi_string = "auto"; | |
160 | ||
0428b8f5 | 161 | /* The execution mode to assume. */ |
40478521 | 162 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
163 | { |
164 | "auto", | |
165 | "arm", | |
68770265 MGD |
166 | "thumb", |
167 | NULL | |
0428b8f5 DJ |
168 | }; |
169 | ||
170 | static const char *arm_fallback_mode_string = "auto"; | |
171 | static const char *arm_force_mode_string = "auto"; | |
172 | ||
f32bf4a4 YQ |
173 | /* The standard register names, and all the valid aliases for them. Note |
174 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
175 | have been added as builtin user registers in | |
176 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
177 | static const struct |
178 | { | |
179 | const char *name; | |
180 | int regnum; | |
181 | } arm_register_aliases[] = { | |
182 | /* Basic register numbers. */ | |
183 | { "r0", 0 }, | |
184 | { "r1", 1 }, | |
185 | { "r2", 2 }, | |
186 | { "r3", 3 }, | |
187 | { "r4", 4 }, | |
188 | { "r5", 5 }, | |
189 | { "r6", 6 }, | |
190 | { "r7", 7 }, | |
191 | { "r8", 8 }, | |
192 | { "r9", 9 }, | |
193 | { "r10", 10 }, | |
194 | { "r11", 11 }, | |
195 | { "r12", 12 }, | |
196 | { "r13", 13 }, | |
197 | { "r14", 14 }, | |
198 | { "r15", 15 }, | |
199 | /* Synonyms (argument and variable registers). */ | |
200 | { "a1", 0 }, | |
201 | { "a2", 1 }, | |
202 | { "a3", 2 }, | |
203 | { "a4", 3 }, | |
204 | { "v1", 4 }, | |
205 | { "v2", 5 }, | |
206 | { "v3", 6 }, | |
207 | { "v4", 7 }, | |
208 | { "v5", 8 }, | |
209 | { "v6", 9 }, | |
210 | { "v7", 10 }, | |
211 | { "v8", 11 }, | |
212 | /* Other platform-specific names for r9. */ | |
213 | { "sb", 9 }, | |
214 | { "tr", 9 }, | |
215 | /* Special names. */ | |
216 | { "ip", 12 }, | |
123dc839 | 217 | { "lr", 14 }, |
123dc839 DJ |
218 | /* Names used by GCC (not listed in the ARM EABI). */ |
219 | { "sl", 10 }, | |
123dc839 DJ |
220 | /* A special name from the older ATPCS. */ |
221 | { "wr", 7 }, | |
222 | }; | |
bc90b915 | 223 | |
123dc839 | 224 | static const char *const arm_register_names[] = |
da59e081 JM |
225 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
226 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
227 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
228 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
229 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
230 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 231 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 232 | |
65b48a81 PB |
233 | /* Holds the current set of options to be passed to the disassembler. */ |
234 | static char *arm_disassembler_options; | |
235 | ||
afd7eef0 RE |
236 | /* Valid register name styles. */ |
237 | static const char **valid_disassembly_styles; | |
ed9a39eb | 238 | |
afd7eef0 RE |
239 | /* Disassembly style to use. Default to "std" register names. */ |
240 | static const char *disassembly_style; | |
96baa820 | 241 | |
d105cce5 | 242 | /* All possible arm target descriptors. */ |
92d48a1e | 243 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID][2]; |
d105cce5 AH |
244 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; |
245 | ||
ed9a39eb | 246 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 247 | style. */ |
eb4c3f4a | 248 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 249 | struct cmd_list_element *); |
65b48a81 PB |
250 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
251 | struct cmd_list_element *, | |
252 | const char *); | |
ed9a39eb | 253 | |
05d1431c | 254 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 255 | readable_regcache *regcache, |
05d1431c | 256 | int regnum, gdb_byte *buf); |
58d6951d DJ |
257 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
258 | struct regcache *regcache, | |
259 | int regnum, const gdb_byte *buf); | |
260 | ||
e7cf25a8 | 261 | static CORE_ADDR |
553cb527 | 262 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
263 | |
264 | ||
d9311bfa AT |
265 | /* get_next_pcs operations. */ |
266 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
267 | arm_get_next_pcs_read_memory_unsigned_integer, | |
268 | arm_get_next_pcs_syscall_next_pc, | |
269 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
270 | arm_get_next_pcs_is_thumb, |
271 | NULL, | |
d9311bfa AT |
272 | }; |
273 | ||
9b8d791a | 274 | struct arm_prologue_cache |
c3b4394c | 275 | { |
eb5492fa DJ |
276 | /* The stack pointer at the time this frame was created; i.e. the |
277 | caller's stack pointer when this function was called. It is used | |
278 | to identify this frame. */ | |
ae7e2f45 CL |
279 | CORE_ADDR sp; |
280 | ||
281 | /* Additional stack pointers used by M-profile with Security extension. */ | |
282 | /* Use msp_s / psp_s to hold the values of msp / psp when there is | |
283 | no Security extension. */ | |
284 | CORE_ADDR msp_s; | |
285 | CORE_ADDR msp_ns; | |
286 | CORE_ADDR psp_s; | |
287 | CORE_ADDR psp_ns; | |
288 | ||
289 | /* Active stack pointer. */ | |
290 | int active_sp_regnum; | |
0d12d61b YR |
291 | int active_msp_regnum; |
292 | int active_psp_regnum; | |
eb5492fa | 293 | |
4be43953 DJ |
294 | /* The frame base for this frame is just prev_sp - frame size. |
295 | FRAMESIZE is the distance from the frame pointer to the | |
296 | initial stack pointer. */ | |
eb5492fa | 297 | |
c3b4394c | 298 | int framesize; |
eb5492fa DJ |
299 | |
300 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 301 | int framereg; |
eb5492fa | 302 | |
a01567f4 LM |
303 | /* True if the return address is signed, false otherwise. */ |
304 | gdb::optional<bool> ra_signed_state; | |
305 | ||
eb5492fa | 306 | /* Saved register offsets. */ |
098caef4 | 307 | trad_frame_saved_reg *saved_regs; |
0824193f CL |
308 | |
309 | arm_prologue_cache() = default; | |
c3b4394c | 310 | }; |
ed9a39eb | 311 | |
8c9ae6df YR |
312 | |
313 | /* Reconstruct T bit in program status register from LR value. */ | |
314 | ||
315 | static inline ULONGEST | |
316 | reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) | |
317 | { | |
318 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
319 | if (IS_THUMB_ADDR (lr)) | |
320 | psr |= t_bit; | |
321 | else | |
322 | psr &= ~t_bit; | |
323 | ||
324 | return psr; | |
325 | } | |
326 | ||
ae7e2f45 CL |
327 | /* Initialize stack pointers, and flag the active one. */ |
328 | ||
329 | static inline void | |
330 | arm_cache_init_sp (int regnum, CORE_ADDR* member, | |
331 | struct arm_prologue_cache *cache, | |
332 | struct frame_info *frame) | |
333 | { | |
334 | CORE_ADDR val = get_frame_register_unsigned (frame, regnum); | |
335 | if (val == cache->sp) | |
336 | cache->active_sp_regnum = regnum; | |
337 | ||
338 | *member = val; | |
339 | } | |
340 | ||
0824193f CL |
341 | /* Initialize CACHE fields for which zero is not adequate (CACHE is |
342 | expected to have been ZALLOC'ed before calling this function). */ | |
343 | ||
344 | static void | |
345 | arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch) | |
346 | { | |
ae7e2f45 CL |
347 | cache->active_sp_regnum = ARM_SP_REGNUM; |
348 | ||
0824193f CL |
349 | cache->saved_regs = trad_frame_alloc_saved_regs (gdbarch); |
350 | } | |
351 | ||
352 | /* Similar to the previous function, but extracts GDBARCH from FRAME. */ | |
353 | ||
354 | static void | |
355 | arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame) | |
356 | { | |
357 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 358 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0824193f CL |
359 | |
360 | arm_cache_init (cache, gdbarch); | |
fe642a5b | 361 | cache->sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
ae7e2f45 CL |
362 | |
363 | if (tdep->have_sec_ext) | |
364 | { | |
0d12d61b YR |
365 | CORE_ADDR msp_val = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); |
366 | CORE_ADDR psp_val = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); | |
367 | ||
ae7e2f45 CL |
368 | arm_cache_init_sp (tdep->m_profile_msp_s_regnum, &cache->msp_s, cache, frame); |
369 | arm_cache_init_sp (tdep->m_profile_psp_s_regnum, &cache->psp_s, cache, frame); | |
370 | arm_cache_init_sp (tdep->m_profile_msp_ns_regnum, &cache->msp_ns, cache, frame); | |
371 | arm_cache_init_sp (tdep->m_profile_psp_ns_regnum, &cache->psp_ns, cache, frame); | |
372 | ||
0d12d61b YR |
373 | if (msp_val == cache->msp_s) |
374 | cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; | |
375 | else if (msp_val == cache->msp_ns) | |
376 | cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; | |
377 | if (psp_val == cache->psp_s) | |
378 | cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; | |
379 | else if (psp_val == cache->psp_ns) | |
380 | cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; | |
381 | ||
ae7e2f45 CL |
382 | /* Use MSP_S as default stack pointer. */ |
383 | if (cache->active_sp_regnum == ARM_SP_REGNUM) | |
384 | cache->active_sp_regnum = tdep->m_profile_msp_s_regnum; | |
385 | } | |
386 | else if (tdep->is_m) | |
387 | { | |
388 | arm_cache_init_sp (tdep->m_profile_msp_regnum, &cache->msp_s, cache, frame); | |
389 | arm_cache_init_sp (tdep->m_profile_psp_regnum, &cache->psp_s, cache, frame); | |
390 | } | |
391 | else | |
392 | arm_cache_init_sp (ARM_SP_REGNUM, &cache->msp_s, cache, frame); | |
393 | } | |
394 | ||
395 | /* Return the requested stack pointer value (in REGNUM), taking into | |
396 | account whether we have a Security extension or an M-profile | |
397 | CPU. */ | |
398 | ||
399 | static CORE_ADDR | |
400 | arm_cache_get_sp_register (struct arm_prologue_cache *cache, | |
401 | arm_gdbarch_tdep *tdep, int regnum) | |
402 | { | |
ae7e2f45 CL |
403 | if (tdep->have_sec_ext) |
404 | { | |
405 | if (regnum == tdep->m_profile_msp_s_regnum) | |
406 | return cache->msp_s; | |
407 | if (regnum == tdep->m_profile_msp_ns_regnum) | |
408 | return cache->msp_ns; | |
409 | if (regnum == tdep->m_profile_psp_s_regnum) | |
410 | return cache->psp_s; | |
411 | if (regnum == tdep->m_profile_psp_ns_regnum) | |
412 | return cache->psp_ns; | |
0d12d61b YR |
413 | if (regnum == tdep->m_profile_msp_regnum) |
414 | return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); | |
415 | if (regnum == tdep->m_profile_psp_regnum) | |
416 | return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); | |
b9b66a3a YR |
417 | if (regnum == ARM_SP_REGNUM) |
418 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 CL |
419 | } |
420 | else if (tdep->is_m) | |
421 | { | |
422 | if (regnum == tdep->m_profile_msp_regnum) | |
423 | return cache->msp_s; | |
424 | if (regnum == tdep->m_profile_psp_regnum) | |
425 | return cache->psp_s; | |
b9b66a3a YR |
426 | if (regnum == ARM_SP_REGNUM) |
427 | return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
ae7e2f45 | 428 | } |
b9b66a3a YR |
429 | else if (regnum == ARM_SP_REGNUM) |
430 | return cache->sp; | |
ae7e2f45 CL |
431 | |
432 | gdb_assert_not_reached ("Invalid SP selection"); | |
433 | } | |
434 | ||
435 | /* Return the previous stack address, depending on which SP register | |
436 | is active. */ | |
437 | ||
438 | static CORE_ADDR | |
439 | arm_cache_get_prev_sp_value (struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep) | |
440 | { | |
441 | CORE_ADDR val = arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); | |
442 | return val; | |
443 | } | |
444 | ||
445 | /* Set the active stack pointer to VAL. */ | |
446 | ||
447 | static void | |
448 | arm_cache_set_active_sp_value (struct arm_prologue_cache *cache, | |
449 | arm_gdbarch_tdep *tdep, CORE_ADDR val) | |
450 | { | |
ae7e2f45 CL |
451 | if (tdep->have_sec_ext) |
452 | { | |
453 | if (cache->active_sp_regnum == tdep->m_profile_msp_s_regnum) | |
454 | cache->msp_s = val; | |
455 | else if (cache->active_sp_regnum == tdep->m_profile_msp_ns_regnum) | |
456 | cache->msp_ns = val; | |
457 | else if (cache->active_sp_regnum == tdep->m_profile_psp_s_regnum) | |
458 | cache->psp_s = val; | |
459 | else if (cache->active_sp_regnum == tdep->m_profile_psp_ns_regnum) | |
460 | cache->psp_ns = val; | |
461 | ||
462 | return; | |
463 | } | |
464 | else if (tdep->is_m) | |
465 | { | |
466 | if (cache->active_sp_regnum == tdep->m_profile_msp_regnum) | |
467 | cache->msp_s = val; | |
468 | else if (cache->active_sp_regnum == tdep->m_profile_psp_regnum) | |
469 | cache->psp_s = val; | |
470 | ||
471 | return; | |
472 | } | |
b9b66a3a YR |
473 | else if (cache->active_sp_regnum == ARM_SP_REGNUM) |
474 | { | |
475 | cache->sp = val; | |
476 | return; | |
477 | } | |
ae7e2f45 CL |
478 | |
479 | gdb_assert_not_reached ("Invalid SP selection"); | |
0824193f CL |
480 | } |
481 | ||
d65edaa0 | 482 | /* Return true if REGNUM is one of the alternative stack pointers. */ |
ef273377 CL |
483 | |
484 | static bool | |
d65edaa0 | 485 | arm_is_alternative_sp_register (arm_gdbarch_tdep *tdep, int regnum) |
ef273377 | 486 | { |
d65edaa0 | 487 | if ((regnum == tdep->m_profile_msp_regnum) |
ef273377 CL |
488 | || (regnum == tdep->m_profile_msp_s_regnum) |
489 | || (regnum == tdep->m_profile_msp_ns_regnum) | |
490 | || (regnum == tdep->m_profile_psp_regnum) | |
491 | || (regnum == tdep->m_profile_psp_s_regnum) | |
492 | || (regnum == tdep->m_profile_psp_ns_regnum)) | |
493 | return true; | |
494 | else | |
495 | return false; | |
496 | } | |
497 | ||
498 | /* Set the active stack pointer to SP_REGNUM. */ | |
499 | ||
500 | static void | |
501 | arm_cache_switch_prev_sp (struct arm_prologue_cache *cache, | |
502 | arm_gdbarch_tdep *tdep, int sp_regnum) | |
503 | { | |
d65edaa0 | 504 | gdb_assert (arm_is_alternative_sp_register (tdep, sp_regnum)); |
ef273377 CL |
505 | |
506 | if (tdep->have_sec_ext) | |
507 | gdb_assert (sp_regnum != tdep->m_profile_msp_regnum | |
508 | && sp_regnum != tdep->m_profile_psp_regnum); | |
509 | ||
510 | cache->active_sp_regnum = sp_regnum; | |
511 | } | |
512 | ||
9ecab40c SM |
513 | namespace { |
514 | ||
515 | /* Abstract class to read ARM instructions from memory. */ | |
516 | ||
517 | class arm_instruction_reader | |
518 | { | |
519 | public: | |
2c5b1849 | 520 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
521 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
522 | }; | |
523 | ||
524 | /* Read instructions from target memory. */ | |
525 | ||
526 | class target_arm_instruction_reader : public arm_instruction_reader | |
527 | { | |
528 | public: | |
529 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
530 | { | |
531 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
532 | } | |
533 | }; | |
534 | ||
535 | } /* namespace */ | |
536 | ||
537 | static CORE_ADDR arm_analyze_prologue | |
538 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
539 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 540 | |
cca44b1b JB |
541 | /* Architecture version for displaced stepping. This effects the behaviour of |
542 | certain instructions, and really should not be hard-wired. */ | |
543 | ||
544 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
545 | ||
c7ae7675 | 546 | /* See arm-tdep.h. */ |
c906108c | 547 | |
491144b5 | 548 | bool arm_apcs_32 = true; |
ef273377 | 549 | bool arm_unwind_secure_frames = true; |
c906108c | 550 | |
9779414d DJ |
551 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
552 | ||
478fd957 | 553 | int |
9779414d DJ |
554 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
555 | { | |
08106042 | 556 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
557 | |
558 | if (tdep->is_m) | |
9779414d DJ |
559 | return XPSR_T; |
560 | else | |
561 | return CPSR_T; | |
562 | } | |
563 | ||
d0e59a68 AT |
564 | /* Determine if the processor is currently executing in Thumb mode. */ |
565 | ||
566 | int | |
567 | arm_is_thumb (struct regcache *regcache) | |
568 | { | |
569 | ULONGEST cpsr; | |
ac7936df | 570 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
571 | |
572 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
573 | ||
574 | return (cpsr & t_bit) != 0; | |
575 | } | |
576 | ||
60270718 AB |
577 | /* Determine if FRAME is executing in Thumb mode. FRAME must be an ARM |
578 | frame. */ | |
b39cc962 | 579 | |
25b41d01 | 580 | int |
b39cc962 DJ |
581 | arm_frame_is_thumb (struct frame_info *frame) |
582 | { | |
60270718 AB |
583 | /* Check the architecture of FRAME. */ |
584 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
585 | gdb_assert (gdbarch_bfd_arch_info (gdbarch)->arch == bfd_arch_arm); | |
b39cc962 DJ |
586 | |
587 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
588 | directly (from a signal frame or dummy frame) or by interpreting | |
589 | the saved LR (from a prologue or DWARF frame). So consult it and | |
590 | trust the unwinders. */ | |
60270718 | 591 | CORE_ADDR cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
b39cc962 | 592 | |
60270718 AB |
593 | /* Find and extract the thumb bit. */ |
594 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); | |
9779414d | 595 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
596 | } |
597 | ||
f9d67f43 DJ |
598 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
599 | return its type. Otherwise, return 0. If START is non-NULL, | |
600 | set *START to the location of the mapping symbol. */ | |
c906108c | 601 | |
f9d67f43 DJ |
602 | static char |
603 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 604 | { |
60c5725c | 605 | struct obj_section *sec; |
0428b8f5 | 606 | |
60c5725c DJ |
607 | /* If there are mapping symbols, consult them. */ |
608 | sec = find_pc_section (memaddr); | |
609 | if (sec != NULL) | |
610 | { | |
bd5766ec | 611 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd); |
60c5725c DJ |
612 | if (data != NULL) |
613 | { | |
4838e44c SM |
614 | unsigned int section_idx = sec->the_bfd_section->index; |
615 | arm_mapping_symbol_vec &map | |
616 | = data->section_maps[section_idx]; | |
617 | ||
618 | /* Sort the vector on first use. */ | |
619 | if (!data->section_maps_sorted[section_idx]) | |
620 | { | |
621 | std::sort (map.begin (), map.end ()); | |
622 | data->section_maps_sorted[section_idx] = true; | |
623 | } | |
624 | ||
0c1bcd23 | 625 | arm_mapping_symbol map_key = { memaddr - sec->addr (), 0 }; |
54cc7474 SM |
626 | arm_mapping_symbol_vec::const_iterator it |
627 | = std::lower_bound (map.begin (), map.end (), map_key); | |
628 | ||
629 | /* std::lower_bound finds the earliest ordered insertion | |
630 | point. If the symbol at this position starts at this exact | |
631 | address, we use that; otherwise, the preceding | |
632 | mapping symbol covers this address. */ | |
633 | if (it < map.end ()) | |
60c5725c | 634 | { |
54cc7474 | 635 | if (it->value == map_key.value) |
60c5725c | 636 | { |
f9d67f43 | 637 | if (start) |
0c1bcd23 | 638 | *start = it->value + sec->addr (); |
54cc7474 | 639 | return it->type; |
60c5725c DJ |
640 | } |
641 | } | |
54cc7474 SM |
642 | |
643 | if (it > map.begin ()) | |
644 | { | |
645 | arm_mapping_symbol_vec::const_iterator prev_it | |
646 | = it - 1; | |
647 | ||
648 | if (start) | |
0c1bcd23 | 649 | *start = prev_it->value + sec->addr (); |
54cc7474 SM |
650 | return prev_it->type; |
651 | } | |
60c5725c DJ |
652 | } |
653 | } | |
654 | ||
f9d67f43 DJ |
655 | return 0; |
656 | } | |
657 | ||
658 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
659 | function. This function should be called for addresses unrelated to | |
660 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
661 | ||
e3039479 | 662 | int |
9779414d | 663 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 664 | { |
7cbd4a93 | 665 | struct bound_minimal_symbol sym; |
f9d67f43 | 666 | char type; |
187b041e | 667 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
08106042 | 668 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
187b041e SM |
669 | |
670 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
671 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
672 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
673 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
674 | |
675 | /* If checking the mode of displaced instruction in copy area, the mode | |
676 | should be determined by instruction on the original address. */ | |
677 | if (dsc) | |
678 | { | |
136821d9 SM |
679 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
680 | (unsigned long) dsc->insn_addr, | |
681 | (unsigned long) memaddr); | |
a42244db YQ |
682 | memaddr = dsc->insn_addr; |
683 | } | |
f9d67f43 DJ |
684 | |
685 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
686 | if (IS_THUMB_ADDR (memaddr)) | |
687 | return 1; | |
688 | ||
689 | /* If the user wants to override the symbol table, let him. */ | |
690 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
691 | return 0; | |
692 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
693 | return 1; | |
694 | ||
9779414d | 695 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
345bd07c | 696 | if (tdep->is_m) |
9779414d DJ |
697 | return 1; |
698 | ||
f9d67f43 DJ |
699 | /* If there are mapping symbols, consult them. */ |
700 | type = arm_find_mapping_symbol (memaddr, NULL); | |
701 | if (type) | |
702 | return type == 't'; | |
703 | ||
ed9a39eb | 704 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 705 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
706 | if (sym.minsym) |
707 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
708 | |
709 | /* If the user wants to override the fallback mode, let them. */ | |
710 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
711 | return 0; | |
712 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
713 | return 1; | |
714 | ||
715 | /* If we couldn't find any symbol, but we're talking to a running | |
716 | target, then trust the current value of $cpsr. This lets | |
717 | "display/i $pc" always show the correct mode (though if there is | |
718 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 719 | displayed in the mode it will be executed). */ |
9dccd06e | 720 | if (target_has_registers ()) |
18819fa6 | 721 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
722 | |
723 | /* Otherwise we're out of luck; we assume ARM. */ | |
724 | return 0; | |
c906108c SS |
725 | } |
726 | ||
ca90e760 | 727 | /* Determine if the address specified equals any of these magic return |
55ea94da | 728 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
ca90e760 FH |
729 | architectures. |
730 | ||
731 | From ARMv6-M Reference Manual B1.5.8 | |
732 | Table B1-5 Exception return behavior | |
733 | ||
734 | EXC_RETURN Return To Return Stack | |
735 | 0xFFFFFFF1 Handler mode Main | |
736 | 0xFFFFFFF9 Thread mode Main | |
737 | 0xFFFFFFFD Thread mode Process | |
738 | ||
739 | From ARMv7-M Reference Manual B1.5.8 | |
740 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
741 | ||
742 | EXC_RETURN Return To Return Stack | |
743 | 0xFFFFFFF1 Handler mode Main | |
744 | 0xFFFFFFF9 Thread mode Main | |
745 | 0xFFFFFFFD Thread mode Process | |
746 | ||
747 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
748 | FP | |
749 | ||
750 | EXC_RETURN Return To Return Stack Frame Type | |
751 | 0xFFFFFFE1 Handler mode Main Extended | |
752 | 0xFFFFFFE9 Thread mode Main Extended | |
753 | 0xFFFFFFED Thread mode Process Extended | |
754 | 0xFFFFFFF1 Handler mode Main Basic | |
755 | 0xFFFFFFF9 Thread mode Main Basic | |
756 | 0xFFFFFFFD Thread mode Process Basic | |
757 | ||
758 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
759 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
760 | ||
761 | In the ARMv8-M Architecture Technical Reference also adds | |
762 | for implementations without the Security Extension: | |
763 | ||
764 | EXC_RETURN Condition | |
765 | 0xFFFFFFB0 Return to Handler mode. | |
766 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
767 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
768 | |
769 | static int | |
ef273377 CL |
770 | arm_m_addr_is_magic (struct gdbarch *gdbarch, CORE_ADDR addr) |
771 | { | |
08106042 | 772 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ef273377 CL |
773 | if (tdep->have_sec_ext) |
774 | { | |
775 | switch ((addr & 0xff000000)) | |
776 | { | |
777 | case 0xff000000: /* EXC_RETURN pattern. */ | |
778 | case 0xfe000000: /* FNC_RETURN pattern. */ | |
779 | return 1; | |
780 | default: | |
781 | return 0; | |
782 | } | |
783 | } | |
784 | else | |
785 | { | |
786 | switch (addr) | |
787 | { | |
788 | /* Values from ARMv8-M Architecture Technical Reference. */ | |
789 | case 0xffffffb0: | |
790 | case 0xffffffb8: | |
791 | case 0xffffffbc: | |
792 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of | |
793 | the exception return behavior. */ | |
794 | case 0xffffffe1: | |
795 | case 0xffffffe9: | |
796 | case 0xffffffed: | |
797 | case 0xfffffff1: | |
798 | case 0xfffffff9: | |
799 | case 0xfffffffd: | |
800 | /* Address is magic. */ | |
801 | return 1; | |
ca90e760 | 802 | |
ef273377 CL |
803 | default: |
804 | /* Address is not magic. */ | |
805 | return 0; | |
806 | } | |
ca90e760 FH |
807 | } |
808 | } | |
809 | ||
181c1381 | 810 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 811 | static CORE_ADDR |
24568a2c | 812 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 813 | { |
08106042 | 814 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 815 | |
2ae28aa9 YQ |
816 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
817 | (the magic exception return address). */ | |
ef273377 | 818 | if (tdep->is_m && arm_m_addr_is_magic (gdbarch, val)) |
2ae28aa9 YQ |
819 | return val; |
820 | ||
a3a2ee65 | 821 | if (arm_apcs_32) |
dd6be234 | 822 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 823 | else |
a3a2ee65 | 824 | return (val & 0x03fffffc); |
c906108c SS |
825 | } |
826 | ||
0d39a070 | 827 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
828 | can be safely ignored during prologue skipping. IS_THUMB is true |
829 | if the function is known to be a Thumb function due to the way it | |
830 | is being called. */ | |
0d39a070 | 831 | static int |
e0634ccf | 832 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 833 | { |
e0634ccf | 834 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 835 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
836 | |
837 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 838 | if (msym.minsym != NULL |
4aeddc50 | 839 | && msym.value_address () == pc |
c9d95fa3 | 840 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 841 | { |
c9d95fa3 | 842 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 843 | |
e0634ccf UW |
844 | /* The GNU linker's Thumb call stub to foo is named |
845 | __foo_from_thumb. */ | |
846 | if (strstr (name, "_from_thumb") != NULL) | |
847 | name += 2; | |
0d39a070 | 848 | |
e0634ccf UW |
849 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
850 | arguments to their argument types in non-prototyped | |
851 | functions. */ | |
61012eef | 852 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 853 | return 1; |
61012eef | 854 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 855 | return 1; |
0d39a070 | 856 | |
e0634ccf | 857 | /* Internal functions related to thread-local storage. */ |
61012eef | 858 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 859 | return 1; |
61012eef | 860 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
861 | return 1; |
862 | } | |
863 | else | |
864 | { | |
865 | /* If we run against a stripped glibc, we may be unable to identify | |
866 | special functions by name. Check for one important case, | |
867 | __aeabi_read_tp, by comparing the *code* against the default | |
868 | implementation (this is hand-written ARM assembler in glibc). */ | |
869 | ||
870 | if (!is_thumb | |
198cd59d | 871 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 872 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 873 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
874 | == 0xe240f01f) /* sub pc, r0, #31 */ |
875 | return 1; | |
876 | } | |
ec3d575a | 877 | |
0d39a070 DJ |
878 | return 0; |
879 | } | |
880 | ||
621c6d5b YQ |
881 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
882 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
883 | instruction. */ | |
884 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
885 | ((bits ((insn1), 0, 3) << 12) \ | |
886 | | (bits ((insn1), 10, 10) << 11) \ | |
887 | | (bits ((insn2), 12, 14) << 8) \ | |
888 | | bits ((insn2), 0, 7)) | |
889 | ||
890 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
891 | the 32-bit instruction. */ | |
892 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
893 | ((bits ((insn), 16, 19) << 12) \ | |
894 | | bits ((insn), 0, 11)) | |
895 | ||
ec3d575a UW |
896 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
897 | ||
898 | static unsigned int | |
899 | thumb_expand_immediate (unsigned int imm) | |
900 | { | |
901 | unsigned int count = imm >> 7; | |
902 | ||
903 | if (count < 8) | |
904 | switch (count / 2) | |
905 | { | |
906 | case 0: | |
907 | return imm & 0xff; | |
908 | case 1: | |
909 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
910 | case 2: | |
911 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
912 | case 3: | |
913 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
914 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
915 | } | |
916 | ||
917 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
918 | } | |
919 | ||
540314bd YQ |
920 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
921 | epilogue, 0 otherwise. */ | |
922 | ||
923 | static int | |
924 | thumb_instruction_restores_sp (unsigned short insn) | |
925 | { | |
926 | return (insn == 0x46bd /* mov sp, r7 */ | |
927 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
928 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
929 | } | |
930 | ||
29d73ae4 DJ |
931 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
932 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
933 | clobber the stack frame unexpectedly, or an unknown instruction. |
934 | Return the last address which is definitely safe to skip for an | |
935 | initial breakpoint. */ | |
c906108c SS |
936 | |
937 | static CORE_ADDR | |
29d73ae4 DJ |
938 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
939 | CORE_ADDR start, CORE_ADDR limit, | |
940 | struct arm_prologue_cache *cache) | |
c906108c | 941 | { |
08106042 | 942 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 | 943 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 944 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
945 | int i; |
946 | pv_t regs[16]; | |
29d73ae4 | 947 | CORE_ADDR offset; |
ec3d575a | 948 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 949 | |
29d73ae4 DJ |
950 | for (i = 0; i < 16; i++) |
951 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 952 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 953 | |
29d73ae4 | 954 | while (start < limit) |
c906108c | 955 | { |
29d73ae4 | 956 | unsigned short insn; |
a01567f4 | 957 | gdb::optional<bool> ra_signed_state; |
29d73ae4 | 958 | |
198cd59d | 959 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 960 | |
94c30b78 | 961 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 962 | { |
29d73ae4 DJ |
963 | int regno; |
964 | int mask; | |
4be43953 | 965 | |
f7b7ed97 | 966 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 967 | break; |
29d73ae4 DJ |
968 | |
969 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
970 | whether to save LR (R14). */ | |
971 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
972 | ||
973 | /* Calculate offsets of saved R0-R7 and LR. */ | |
974 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
975 | if (mask & (1 << regno)) | |
976 | { | |
29d73ae4 DJ |
977 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
978 | -4); | |
f7b7ed97 | 979 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 980 | } |
da59e081 | 981 | } |
1db01f22 | 982 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 983 | { |
29d73ae4 | 984 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
985 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
986 | -offset); | |
da59e081 | 987 | } |
808f7ab1 YQ |
988 | else if (thumb_instruction_restores_sp (insn)) |
989 | { | |
990 | /* Don't scan past the epilogue. */ | |
991 | break; | |
992 | } | |
0d39a070 DJ |
993 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
994 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
995 | (insn & 0xff) << 2); | |
996 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
997 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
998 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
999 | bits (insn, 6, 8)); | |
1000 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
1001 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1002 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
1003 | bits (insn, 0, 7)); | |
1004 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
1005 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
1006 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
1007 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
1008 | regs[bits (insn, 6, 8)]); | |
1009 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
1010 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
1011 | { | |
1012 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
1013 | int rm = bits (insn, 3, 6); | |
1014 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
1015 | } | |
29d73ae4 | 1016 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 1017 | { |
29d73ae4 DJ |
1018 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
1019 | int src_reg = (insn & 0x78) >> 3; | |
1020 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 1021 | } |
29d73ae4 | 1022 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 1023 | { |
29d73ae4 DJ |
1024 | /* Handle stores to the stack. Normally pushes are used, |
1025 | but with GCC -mtpcs-frame, there may be other stores | |
1026 | in the prologue to create the frame. */ | |
1027 | int regno = (insn >> 8) & 0x7; | |
1028 | pv_t addr; | |
1029 | ||
1030 | offset = (insn & 0xff) << 2; | |
1031 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
1032 | ||
f7b7ed97 | 1033 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
1034 | break; |
1035 | ||
f7b7ed97 | 1036 | stack.store (addr, 4, regs[regno]); |
da59e081 | 1037 | } |
0d39a070 DJ |
1038 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
1039 | { | |
1040 | int rd = bits (insn, 0, 2); | |
1041 | int rn = bits (insn, 3, 5); | |
1042 | pv_t addr; | |
1043 | ||
1044 | offset = bits (insn, 6, 10) << 2; | |
1045 | addr = pv_add_constant (regs[rn], offset); | |
1046 | ||
f7b7ed97 | 1047 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
1048 | break; |
1049 | ||
f7b7ed97 | 1050 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
1051 | } |
1052 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
1053 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
1054 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
1055 | /* Ignore stores of argument registers to the stack. */ | |
1056 | ; | |
1057 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
1058 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
1059 | /* Ignore block loads from the stack, potentially copying | |
1060 | parameters from memory. */ | |
1061 | ; | |
1062 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
1063 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
1064 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
1065 | /* Similarly ignore single loads from the stack. */ | |
1066 | ; | |
1067 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
1068 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
1069 | /* Skip register copies, i.e. saves to another register | |
1070 | instead of the stack. */ | |
1071 | ; | |
1072 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
1073 | /* Recognize constant loads; even with small stacks these are necessary | |
1074 | on Thumb. */ | |
1075 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
1076 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
1077 | { | |
1078 | /* Constant pool loads, for the same reason. */ | |
1079 | unsigned int constant; | |
1080 | CORE_ADDR loc; | |
1081 | ||
1082 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
1083 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1084 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
1085 | } | |
db24da6d | 1086 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 1087 | { |
0d39a070 DJ |
1088 | unsigned short inst2; |
1089 | ||
198cd59d YQ |
1090 | inst2 = read_code_unsigned_integer (start + 2, 2, |
1091 | byte_order_for_code); | |
a01567f4 | 1092 | uint32_t whole_insn = (insn << 16) | inst2; |
0d39a070 DJ |
1093 | |
1094 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
1095 | { | |
1096 | /* BL, BLX. Allow some special function calls when | |
1097 | skipping the prologue; GCC generates these before | |
1098 | storing arguments to the stack. */ | |
1099 | CORE_ADDR nextpc; | |
1100 | int j1, j2, imm1, imm2; | |
1101 | ||
1102 | imm1 = sbits (insn, 0, 10); | |
1103 | imm2 = bits (inst2, 0, 10); | |
1104 | j1 = bit (inst2, 13); | |
1105 | j2 = bit (inst2, 11); | |
1106 | ||
1107 | offset = ((imm1 << 12) + (imm2 << 1)); | |
1108 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
1109 | ||
1110 | nextpc = start + 4 + offset; | |
1111 | /* For BLX make sure to clear the low bits. */ | |
1112 | if (bit (inst2, 12) == 0) | |
1113 | nextpc = nextpc & 0xfffffffc; | |
1114 | ||
e0634ccf UW |
1115 | if (!skip_prologue_function (gdbarch, nextpc, |
1116 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
1117 | break; |
1118 | } | |
ec3d575a | 1119 | |
0963b4bd MS |
1120 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
1121 | { registers } */ | |
ec3d575a UW |
1122 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1123 | { | |
1124 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1125 | int regno; | |
1126 | ||
f7b7ed97 | 1127 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1128 | break; |
1129 | ||
1130 | /* Calculate offsets of saved registers. */ | |
1131 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
1132 | if (inst2 & (1 << regno)) | |
1133 | { | |
1134 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 1135 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1136 | } |
1137 | ||
1138 | if (insn & 0x0020) | |
1139 | regs[bits (insn, 0, 3)] = addr; | |
1140 | } | |
1141 | ||
fcaa1071 CL |
1142 | /* vstmdb Rn{!}, { D-registers } (aka vpush). */ |
1143 | else if ((insn & 0xff20) == 0xed20 | |
1144 | && (inst2 & 0x0f00) == 0x0b00 | |
1145 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1146 | { | |
1147 | /* Address SP points to. */ | |
1148 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1149 | ||
1150 | /* Number of registers saved. */ | |
1151 | unsigned int number = bits (inst2, 0, 7) >> 1; | |
1152 | ||
1153 | /* First register to save. */ | |
1154 | int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4); | |
1155 | ||
1156 | if (stack.store_would_trash (addr)) | |
1157 | break; | |
1158 | ||
1159 | /* Calculate offsets of saved registers. */ | |
1160 | for (; number > 0; number--) | |
1161 | { | |
1162 | addr = pv_add_constant (addr, -8); | |
1163 | stack.store (addr, 8, pv_register (ARM_D0_REGNUM | |
1164 | + vd + number, 0)); | |
1165 | } | |
1166 | ||
1167 | /* Writeback SP to account for the saved registers. */ | |
1168 | regs[bits (insn, 0, 3)] = addr; | |
1169 | } | |
1170 | ||
0963b4bd MS |
1171 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
1172 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
1173 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
1174 | { | |
1175 | int regno1 = bits (inst2, 12, 15); | |
1176 | int regno2 = bits (inst2, 8, 11); | |
1177 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1178 | ||
1179 | offset = inst2 & 0xff; | |
1180 | if (insn & 0x0080) | |
1181 | addr = pv_add_constant (addr, offset); | |
1182 | else | |
1183 | addr = pv_add_constant (addr, -offset); | |
1184 | ||
f7b7ed97 | 1185 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1186 | break; |
1187 | ||
f7b7ed97 TT |
1188 | stack.store (addr, 4, regs[regno1]); |
1189 | stack.store (pv_add_constant (addr, 4), | |
1190 | 4, regs[regno2]); | |
ec3d575a UW |
1191 | |
1192 | if (insn & 0x0020) | |
1193 | regs[bits (insn, 0, 3)] = addr; | |
1194 | } | |
1195 | ||
1196 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
1197 | && (inst2 & 0x0c00) == 0x0c00 | |
1198 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1199 | { | |
1200 | int regno = bits (inst2, 12, 15); | |
1201 | pv_t addr = regs[bits (insn, 0, 3)]; | |
1202 | ||
1203 | offset = inst2 & 0xff; | |
1204 | if (inst2 & 0x0200) | |
1205 | addr = pv_add_constant (addr, offset); | |
1206 | else | |
1207 | addr = pv_add_constant (addr, -offset); | |
1208 | ||
f7b7ed97 | 1209 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1210 | break; |
1211 | ||
f7b7ed97 | 1212 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1213 | |
1214 | if (inst2 & 0x0100) | |
1215 | regs[bits (insn, 0, 3)] = addr; | |
1216 | } | |
1217 | ||
1218 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
1219 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1220 | { | |
1221 | int regno = bits (inst2, 12, 15); | |
1222 | pv_t addr; | |
1223 | ||
1224 | offset = inst2 & 0xfff; | |
1225 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
1226 | ||
f7b7ed97 | 1227 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
1228 | break; |
1229 | ||
f7b7ed97 | 1230 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
1231 | } |
1232 | ||
1233 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 1234 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1235 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1236 | ; |
ec3d575a UW |
1237 | |
1238 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
1239 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1240 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1241 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1242 | ; |
ec3d575a | 1243 | |
0963b4bd MS |
1244 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
1245 | { registers } */ | |
ec3d575a UW |
1246 | && (inst2 & 0x8000) == 0x0000 |
1247 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1248 | /* Ignore block loads from the stack, potentially copying | |
1249 | parameters from memory. */ | |
0d39a070 | 1250 | ; |
ec3d575a | 1251 | |
f8c6d152 | 1252 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 1253 | [Rn, #+/-imm] */ |
0d39a070 | 1254 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1255 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 1256 | ; |
ec3d575a UW |
1257 | |
1258 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
1259 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1260 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1261 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1262 | ; |
ec3d575a UW |
1263 | |
1264 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 1265 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1266 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1267 | ; |
ec3d575a UW |
1268 | |
1269 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
1270 | && (inst2 & 0x8000) == 0x0000) | |
1271 | { | |
1272 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1273 | | (bits (inst2, 12, 14) << 8) | |
1274 | | bits (inst2, 0, 7)); | |
1275 | ||
1276 | regs[bits (inst2, 8, 11)] | |
1277 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1278 | thumb_expand_immediate (imm)); | |
1279 | } | |
1280 | ||
1281 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1282 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1283 | { |
ec3d575a UW |
1284 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1285 | | (bits (inst2, 12, 14) << 8) | |
1286 | | bits (inst2, 0, 7)); | |
1287 | ||
1288 | regs[bits (inst2, 8, 11)] | |
1289 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1290 | } | |
1291 | ||
1292 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1293 | && (inst2 & 0x8000) == 0x0000) | |
1294 | { | |
1295 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1296 | | (bits (inst2, 12, 14) << 8) | |
1297 | | bits (inst2, 0, 7)); | |
1298 | ||
1299 | regs[bits (inst2, 8, 11)] | |
1300 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1301 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1302 | } | |
1303 | ||
1304 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1305 | && (inst2 & 0x8000) == 0x0000) | |
1306 | { | |
1307 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1308 | | (bits (inst2, 12, 14) << 8) | |
1309 | | bits (inst2, 0, 7)); | |
1310 | ||
1311 | regs[bits (inst2, 8, 11)] | |
1312 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1313 | } | |
1314 | ||
1315 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1316 | { | |
1317 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1318 | | (bits (inst2, 12, 14) << 8) | |
1319 | | bits (inst2, 0, 7)); | |
1320 | ||
1321 | regs[bits (inst2, 8, 11)] | |
1322 | = pv_constant (thumb_expand_immediate (imm)); | |
1323 | } | |
1324 | ||
1325 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1326 | { | |
621c6d5b YQ |
1327 | unsigned int imm |
1328 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1329 | |
1330 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1331 | } | |
1332 | ||
1333 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1334 | && (inst2 & 0xf0f0) == 0) | |
1335 | { | |
1336 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1337 | int src_reg = inst2 & 0xf; | |
1338 | regs[dst_reg] = regs[src_reg]; | |
1339 | } | |
1340 | ||
1341 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1342 | { | |
1343 | /* Constant pool loads. */ | |
1344 | unsigned int constant; | |
1345 | CORE_ADDR loc; | |
1346 | ||
cac395ea | 1347 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1348 | if (insn & 0x0080) |
1349 | loc = start + 4 + offset; | |
1350 | else | |
1351 | loc = start + 4 - offset; | |
1352 | ||
1353 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1354 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1355 | } | |
1356 | ||
1357 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1358 | { | |
1359 | /* Constant pool loads. */ | |
1360 | unsigned int constant; | |
1361 | CORE_ADDR loc; | |
1362 | ||
cac395ea | 1363 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1364 | if (insn & 0x0080) |
1365 | loc = start + 4 + offset; | |
1366 | else | |
1367 | loc = start + 4 - offset; | |
1368 | ||
1369 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1370 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1371 | ||
1372 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1373 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1374 | } | |
a01567f4 LM |
1375 | /* Start of ARMv8.1-m PACBTI extension instructions. */ |
1376 | else if (IS_PAC (whole_insn)) | |
1377 | { | |
1378 | /* LR and SP are input registers. PAC is in R12. LR is | |
1379 | signed from this point onwards. NOP space. */ | |
1380 | ra_signed_state = true; | |
1381 | } | |
1382 | else if (IS_PACBTI (whole_insn)) | |
1383 | { | |
1384 | /* LR and SP are input registers. PAC is in R12 and PC is a | |
1385 | valid BTI landing pad. LR is signed from this point onwards. | |
1386 | NOP space. */ | |
1387 | ra_signed_state = true; | |
1388 | } | |
1389 | else if (IS_BTI (whole_insn)) | |
1390 | { | |
1391 | /* Valid BTI landing pad. NOP space. */ | |
1392 | } | |
1393 | else if (IS_PACG (whole_insn)) | |
1394 | { | |
1395 | /* Sign Rn using Rm and store the PAC in Rd. Rd is signed from | |
1396 | this point onwards. */ | |
1397 | ra_signed_state = true; | |
1398 | } | |
1399 | else if (IS_AUT (whole_insn) || IS_AUTG (whole_insn)) | |
1400 | { | |
1401 | /* These instructions appear close to the epilogue, when signed | |
1402 | pointers are getting authenticated. */ | |
1403 | ra_signed_state = false; | |
1404 | } | |
1405 | /* End of ARMv8.1-m PACBTI extension instructions */ | |
ec3d575a UW |
1406 | else if (thumb2_instruction_changes_pc (insn, inst2)) |
1407 | { | |
1408 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1409 | break; |
1410 | } | |
ec3d575a UW |
1411 | else |
1412 | { | |
1413 | /* The optimizer might shove anything into the prologue, | |
1414 | so we just skip what we don't recognize. */ | |
1415 | unrecognized_pc = start; | |
1416 | } | |
0d39a070 | 1417 | |
a01567f4 LM |
1418 | /* Make sure we are dealing with a target that supports ARMv8.1-m |
1419 | PACBTI. */ | |
1420 | if (cache != nullptr && tdep->have_pacbti | |
1421 | && ra_signed_state.has_value ()) | |
1422 | { | |
1423 | arm_debug_printf ("Found pacbti instruction at %s", | |
1424 | paddress (gdbarch, start)); | |
1425 | arm_debug_printf ("RA is %s", | |
1426 | *ra_signed_state? "signed" : "not signed"); | |
1427 | cache->ra_signed_state = ra_signed_state; | |
1428 | } | |
1429 | ||
0d39a070 DJ |
1430 | start += 2; |
1431 | } | |
ec3d575a | 1432 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1433 | { |
ec3d575a | 1434 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1435 | break; |
3d74b771 | 1436 | } |
ec3d575a UW |
1437 | else |
1438 | { | |
1439 | /* The optimizer might shove anything into the prologue, | |
1440 | so we just skip what we don't recognize. */ | |
1441 | unrecognized_pc = start; | |
1442 | } | |
29d73ae4 DJ |
1443 | |
1444 | start += 2; | |
c906108c SS |
1445 | } |
1446 | ||
7cb6d92a SM |
1447 | arm_debug_printf ("Prologue scan stopped at %s", |
1448 | paddress (gdbarch, start)); | |
0d39a070 | 1449 | |
ec3d575a UW |
1450 | if (unrecognized_pc == 0) |
1451 | unrecognized_pc = start; | |
1452 | ||
29d73ae4 | 1453 | if (cache == NULL) |
f7b7ed97 | 1454 | return unrecognized_pc; |
29d73ae4 | 1455 | |
29d73ae4 DJ |
1456 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1457 | { | |
1458 | /* Frame pointer is fp. Frame size is constant. */ | |
1459 | cache->framereg = ARM_FP_REGNUM; | |
1460 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1461 | } | |
1462 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1463 | { | |
1464 | /* Frame pointer is r7. Frame size is constant. */ | |
1465 | cache->framereg = THUMB_FP_REGNUM; | |
1466 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1467 | } | |
72a2e3dc | 1468 | else |
29d73ae4 DJ |
1469 | { |
1470 | /* Try the stack pointer... this is a bit desperate. */ | |
1471 | cache->framereg = ARM_SP_REGNUM; | |
1472 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1473 | } | |
29d73ae4 | 1474 | |
de76473c | 1475 | for (i = 0; i < gdbarch_num_regs (gdbarch); i++) |
f7b7ed97 | 1476 | if (stack.find_reg (gdbarch, i, &offset)) |
10245fe8 YR |
1477 | { |
1478 | cache->saved_regs[i].set_addr (offset); | |
1479 | if (i == ARM_SP_REGNUM) | |
1480 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
1481 | } | |
29d73ae4 | 1482 | |
ec3d575a | 1483 | return unrecognized_pc; |
c906108c SS |
1484 | } |
1485 | ||
621c6d5b YQ |
1486 | |
1487 | /* Try to analyze the instructions starting from PC, which load symbol | |
1488 | __stack_chk_guard. Return the address of instruction after loading this | |
1489 | symbol, set the dest register number to *BASEREG, and set the size of | |
1490 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1491 | not recognized. */ | |
1492 | ||
1493 | static CORE_ADDR | |
1494 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1495 | unsigned int *destreg, int *offset) | |
1496 | { | |
1497 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1498 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1499 | unsigned int low, high, address; | |
1500 | ||
1501 | address = 0; | |
1502 | if (is_thumb) | |
1503 | { | |
1504 | unsigned short insn1 | |
198cd59d | 1505 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1506 | |
1507 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1508 | { | |
1509 | *destreg = bits (insn1, 8, 10); | |
1510 | *offset = 2; | |
6ae274b7 YQ |
1511 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1512 | address = read_memory_unsigned_integer (address, 4, | |
1513 | byte_order_for_code); | |
621c6d5b YQ |
1514 | } |
1515 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1516 | { | |
1517 | unsigned short insn2 | |
198cd59d | 1518 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1519 | |
1520 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1521 | ||
1522 | insn1 | |
198cd59d | 1523 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1524 | insn2 |
198cd59d | 1525 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1526 | |
1527 | /* movt Rd, #const */ | |
1528 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1529 | { | |
1530 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1531 | *destreg = bits (insn2, 8, 11); | |
1532 | *offset = 8; | |
1533 | address = (high << 16 | low); | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | else | |
1538 | { | |
2e9e421f | 1539 | unsigned int insn |
198cd59d | 1540 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1541 | |
6ae274b7 | 1542 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1543 | { |
6ae274b7 YQ |
1544 | address = bits (insn, 0, 11) + pc + 8; |
1545 | address = read_memory_unsigned_integer (address, 4, | |
1546 | byte_order_for_code); | |
1547 | ||
2e9e421f UW |
1548 | *destreg = bits (insn, 12, 15); |
1549 | *offset = 4; | |
1550 | } | |
1551 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1552 | { | |
1553 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1554 | ||
1555 | insn | |
198cd59d | 1556 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1557 | |
1558 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1559 | { | |
1560 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1561 | *destreg = bits (insn, 12, 15); | |
1562 | *offset = 8; | |
1563 | address = (high << 16 | low); | |
1564 | } | |
1565 | } | |
621c6d5b YQ |
1566 | } |
1567 | ||
1568 | return address; | |
1569 | } | |
1570 | ||
1571 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1572 | points to the first instruction of this sequence, return the address of |
1573 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1574 | |
1575 | On arm, this sequence of instructions is composed of mainly three steps, | |
1576 | Step 1: load symbol __stack_chk_guard, | |
1577 | Step 2: load from address of __stack_chk_guard, | |
1578 | Step 3: store it to somewhere else. | |
1579 | ||
1580 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1581 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1582 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1583 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1584 | they are, | |
1585 | ||
1586 | movw Rn, #:lower16:__stack_chk_guard | |
1587 | movt Rn, #:upper16:__stack_chk_guard | |
1588 | ||
1589 | On ARMv5t, it is, | |
1590 | ||
1591 | ldr Rn, .Label | |
1592 | .... | |
1593 | .Lable: | |
1594 | .word __stack_chk_guard | |
1595 | ||
1596 | Since ldr/str is a very popular instruction, we can't use them as | |
1597 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1598 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1599 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1600 | ||
1601 | static CORE_ADDR | |
1602 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1603 | { | |
1604 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1605 | unsigned int basereg; |
7cbd4a93 | 1606 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1607 | int offset; |
1608 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1609 | CORE_ADDR addr; | |
1610 | ||
1611 | /* Try to parse the instructions in Step 1. */ | |
1612 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1613 | &basereg, &offset); | |
1614 | if (!addr) | |
1615 | return pc; | |
1616 | ||
1617 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1618 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1619 | Otherwise, this sequence cannot be for stack protector. */ | |
1620 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1621 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1622 | return pc; |
1623 | ||
1624 | if (is_thumb) | |
1625 | { | |
1626 | unsigned int destreg; | |
1627 | unsigned short insn | |
198cd59d | 1628 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1629 | |
1630 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1631 | if ((insn & 0xf800) != 0x6800) | |
1632 | return pc; | |
1633 | if (bits (insn, 3, 5) != basereg) | |
1634 | return pc; | |
1635 | destreg = bits (insn, 0, 2); | |
1636 | ||
198cd59d YQ |
1637 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1638 | byte_order_for_code); | |
621c6d5b YQ |
1639 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1640 | if ((insn & 0xf800) != 0x6000) | |
1641 | return pc; | |
1642 | if (destreg != bits (insn, 0, 2)) | |
1643 | return pc; | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | unsigned int destreg; | |
1648 | unsigned int insn | |
198cd59d | 1649 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1650 | |
1651 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1652 | if ((insn & 0x0e500000) != 0x04100000) | |
1653 | return pc; | |
1654 | if (bits (insn, 16, 19) != basereg) | |
1655 | return pc; | |
1656 | destreg = bits (insn, 12, 15); | |
1657 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1658 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1659 | 4, byte_order_for_code); |
1660 | if ((insn & 0x0e500000) != 0x04000000) | |
1661 | return pc; | |
1662 | if (bits (insn, 12, 15) != destreg) | |
1663 | return pc; | |
1664 | } | |
1665 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1666 | on arm. */ | |
1667 | if (is_thumb) | |
1668 | return pc + offset + 4; | |
1669 | else | |
1670 | return pc + offset + 8; | |
1671 | } | |
1672 | ||
da3c6d4a MS |
1673 | /* Advance the PC across any function entry prologue instructions to |
1674 | reach some "real" code. | |
34e8f22d RE |
1675 | |
1676 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1677 | prologue: |
c906108c | 1678 | |
c5aa993b JM |
1679 | mov ip, sp |
1680 | [stmfd sp!, {a1,a2,a3,a4}] | |
1681 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1682 | [stfe f7, [sp, #-12]!] |
1683 | [stfe f6, [sp, #-12]!] | |
1684 | [stfe f5, [sp, #-12]!] | |
1685 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1686 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1687 | |
34e8f22d | 1688 | static CORE_ADDR |
6093d2eb | 1689 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1690 | { |
a89fea3c | 1691 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1692 | |
a89fea3c JL |
1693 | /* See if we can determine the end of the prologue via the symbol table. |
1694 | If so, then return either PC, or the PC after the prologue, whichever | |
1695 | is greater. */ | |
1696 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1697 | { |
d80b854b UW |
1698 | CORE_ADDR post_prologue_pc |
1699 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1700 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1701 | |
621c6d5b YQ |
1702 | if (post_prologue_pc) |
1703 | post_prologue_pc | |
1704 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1705 | ||
1706 | ||
0d39a070 DJ |
1707 | /* GCC always emits a line note before the prologue and another |
1708 | one after, even if the two are at the same address or on the | |
1709 | same line. Take advantage of this so that we do not need to | |
1710 | know every instruction that might appear in the prologue. We | |
1711 | will have producer information for most binaries; if it is | |
1712 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1713 | if (post_prologue_pc | |
43f3e411 | 1714 | && (cust == NULL |
ab5f850e SM |
1715 | || cust->producer () == NULL |
1716 | || startswith (cust->producer (), "GNU ") | |
1717 | || producer_is_llvm (cust->producer ()))) | |
0d39a070 DJ |
1718 | return post_prologue_pc; |
1719 | ||
a89fea3c | 1720 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1721 | { |
1722 | CORE_ADDR analyzed_limit; | |
1723 | ||
1724 | /* For non-GCC compilers, make sure the entire line is an | |
1725 | acceptable prologue; GDB will round this function's | |
1726 | return value up to the end of the following line so we | |
1727 | can not skip just part of a line (and we do not want to). | |
1728 | ||
1729 | RealView does not treat the prologue specially, but does | |
1730 | associate prologue code with the opening brace; so this | |
1731 | lets us skip the first line if we think it is the opening | |
1732 | brace. */ | |
9779414d | 1733 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1734 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1735 | post_prologue_pc, NULL); | |
1736 | else | |
9ecab40c SM |
1737 | analyzed_limit |
1738 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1739 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1740 | |
1741 | if (analyzed_limit != post_prologue_pc) | |
1742 | return func_addr; | |
1743 | ||
1744 | return post_prologue_pc; | |
1745 | } | |
c906108c SS |
1746 | } |
1747 | ||
a89fea3c JL |
1748 | /* Can't determine prologue from the symbol table, need to examine |
1749 | instructions. */ | |
c906108c | 1750 | |
a89fea3c JL |
1751 | /* Find an upper limit on the function prologue using the debug |
1752 | information. If the debug information could not be used to provide | |
1753 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1754 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1755 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1756 | if (limit_pc == 0) |
1757 | limit_pc = pc + 64; /* Magic. */ | |
1758 | ||
c906108c | 1759 | |
29d73ae4 | 1760 | /* Check if this is Thumb code. */ |
9779414d | 1761 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1762 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1763 | else |
9ecab40c SM |
1764 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1765 | target_arm_instruction_reader ()); | |
c906108c | 1766 | } |
94c30b78 | 1767 | |
c5aa993b | 1768 | /* *INDENT-OFF* */ |
c906108c SS |
1769 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1770 | This function decodes a Thumb function prologue to determine: | |
1771 | 1) the size of the stack frame | |
1772 | 2) which registers are saved on it | |
1773 | 3) the offsets of saved regs | |
1774 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1775 | |
da59e081 JM |
1776 | A typical Thumb function prologue would create this stack frame |
1777 | (offsets relative to FP) | |
c906108c SS |
1778 | old SP -> 24 stack parameters |
1779 | 20 LR | |
1780 | 16 R7 | |
1781 | R7 -> 0 local variables (16 bytes) | |
1782 | SP -> -12 additional stack space (12 bytes) | |
1783 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1784 | 12 bytes. The frame register is R7. |
da59e081 | 1785 | |
da3c6d4a MS |
1786 | The comments for thumb_skip_prolog() describe the algorithm we use |
1787 | to detect the end of the prolog. */ | |
c5aa993b JM |
1788 | /* *INDENT-ON* */ |
1789 | ||
c906108c | 1790 | static void |
be8626e0 | 1791 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1792 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1793 | { |
1794 | CORE_ADDR prologue_start; | |
1795 | CORE_ADDR prologue_end; | |
c906108c | 1796 | |
b39cc962 DJ |
1797 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1798 | &prologue_end)) | |
c906108c | 1799 | { |
ec3d575a UW |
1800 | /* See comment in arm_scan_prologue for an explanation of |
1801 | this heuristics. */ | |
1802 | if (prologue_end > prologue_start + 64) | |
1803 | { | |
1804 | prologue_end = prologue_start + 64; | |
1805 | } | |
c906108c SS |
1806 | } |
1807 | else | |
f7060f85 DJ |
1808 | /* We're in the boondocks: we have no idea where the start of the |
1809 | function is. */ | |
1810 | return; | |
c906108c | 1811 | |
325fac50 | 1812 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1813 | |
be8626e0 | 1814 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1815 | } |
1816 | ||
f303bc3e YQ |
1817 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1818 | otherwise. */ | |
1819 | ||
1820 | static int | |
1821 | arm_instruction_restores_sp (unsigned int insn) | |
1822 | { | |
1823 | if (bits (insn, 28, 31) != INST_NV) | |
1824 | { | |
1825 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1826 | /* ADD SP (register or immediate). */ | |
1827 | || (insn & 0x0df0f000) == 0x0040d000 | |
1828 | /* SUB SP (register or immediate). */ | |
1829 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1830 | /* MOV SP. */ | |
1831 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1832 | /* POP (LDMIA). */ | |
1833 | || (insn & 0x0fff0000) == 0x049d0000) | |
1834 | /* POP of a single register. */ | |
1835 | return 1; | |
1836 | } | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
9ecab40c SM |
1841 | /* Implement immediate value decoding, as described in section A5.2.4 |
1842 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1843 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1844 | ||
1845 | static uint32_t | |
1846 | arm_expand_immediate (uint32_t imm) | |
1847 | { | |
1848 | /* Immediate values are 12 bits long. */ | |
1849 | gdb_assert ((imm & 0xfffff000) == 0); | |
1850 | ||
1851 | uint32_t unrotated_value = imm & 0xff; | |
1852 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1853 | ||
1854 | if (rotate_amount == 0) | |
1855 | return unrotated_value; | |
1856 | ||
1857 | return ((unrotated_value >> rotate_amount) | |
1858 | | (unrotated_value << (32 - rotate_amount))); | |
1859 | } | |
1860 | ||
0d39a070 DJ |
1861 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1862 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1863 | fill it in. Return the first address not recognized as a prologue | |
1864 | instruction. | |
eb5492fa | 1865 | |
0d39a070 DJ |
1866 | We recognize all the instructions typically found in ARM prologues, |
1867 | plus harmless instructions which can be skipped (either for analysis | |
1868 | purposes, or a more restrictive set that can be skipped when finding | |
1869 | the end of the prologue). */ | |
1870 | ||
1871 | static CORE_ADDR | |
1872 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1873 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1874 | struct arm_prologue_cache *cache, |
1875 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1876 | { |
0d39a070 DJ |
1877 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1878 | int regno; | |
1879 | CORE_ADDR offset, current_pc; | |
1880 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 | 1881 | CORE_ADDR unrecognized_pc = 0; |
08106042 | 1882 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
1883 | |
1884 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1885 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1886 | |
96baa820 JM |
1887 | Be careful, however, and if it doesn't look like a prologue, |
1888 | don't try to scan it. If, for instance, a frameless function | |
1889 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1890 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1891 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1892 | traceback. */ |
d4473757 | 1893 | |
4be43953 DJ |
1894 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1895 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1896 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1897 | |
94c30b78 MS |
1898 | for (current_pc = prologue_start; |
1899 | current_pc < prologue_end; | |
f43845b3 | 1900 | current_pc += 4) |
96baa820 | 1901 | { |
9ecab40c | 1902 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1903 | |
94c30b78 | 1904 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1905 | { |
4be43953 | 1906 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1907 | continue; |
1908 | } | |
0d39a070 DJ |
1909 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1910 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1911 | { |
9ecab40c | 1912 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1913 | int rd = bits (insn, 12, 15); |
0d39a070 | 1914 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1915 | continue; |
1916 | } | |
0d39a070 DJ |
1917 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1918 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1919 | { |
9ecab40c | 1920 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1921 | int rd = bits (insn, 12, 15); |
0d39a070 | 1922 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1923 | continue; |
1924 | } | |
0963b4bd MS |
1925 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1926 | [sp, #-4]! */ | |
f43845b3 | 1927 | { |
f7b7ed97 | 1928 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1929 | break; |
1930 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
1931 | stack.store (regs[ARM_SP_REGNUM], 4, |
1932 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1933 | continue; |
1934 | } | |
1935 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1936 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1937 | or | |
1938 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1939 | { |
d4473757 | 1940 | int mask = insn & 0xffff; |
ed9a39eb | 1941 | |
f7b7ed97 | 1942 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1943 | break; |
1944 | ||
94c30b78 | 1945 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1946 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1947 | if (mask & (1 << regno)) |
1948 | { | |
0963b4bd MS |
1949 | regs[ARM_SP_REGNUM] |
1950 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 1951 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1952 | } |
1953 | } | |
0d39a070 DJ |
1954 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1955 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1956 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1957 | { |
1958 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1959 | continue; | |
1960 | } | |
0d39a070 DJ |
1961 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1962 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1963 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1964 | { |
1965 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1966 | continue; | |
1967 | } | |
0963b4bd MS |
1968 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1969 | { registers } */ | |
0d39a070 DJ |
1970 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1971 | { | |
1972 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1973 | continue; | |
1974 | } | |
d4473757 KB |
1975 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1976 | { | |
9ecab40c | 1977 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 1978 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1979 | } |
1980 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1981 | { | |
9ecab40c | 1982 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 1983 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1984 | } |
0963b4bd MS |
1985 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1986 | [sp, -#c]! */ | |
345bd07c | 1987 | && tdep->have_fpa_registers) |
d4473757 | 1988 | { |
f7b7ed97 | 1989 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1990 | break; |
1991 | ||
1992 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1993 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 1994 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1995 | } |
0963b4bd MS |
1996 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1997 | [sp!] */ | |
345bd07c | 1998 | && tdep->have_fpa_registers) |
d4473757 KB |
1999 | { |
2000 | int n_saved_fp_regs; | |
2001 | unsigned int fp_start_reg, fp_bound_reg; | |
2002 | ||
f7b7ed97 | 2003 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
2004 | break; |
2005 | ||
94c30b78 | 2006 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 2007 | { |
d4473757 KB |
2008 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2009 | n_saved_fp_regs = 3; | |
2010 | else | |
2011 | n_saved_fp_regs = 1; | |
96baa820 | 2012 | } |
d4473757 | 2013 | else |
96baa820 | 2014 | { |
d4473757 KB |
2015 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
2016 | n_saved_fp_regs = 2; | |
2017 | else | |
2018 | n_saved_fp_regs = 4; | |
96baa820 | 2019 | } |
d4473757 | 2020 | |
34e8f22d | 2021 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
2022 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
2023 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 2024 | { |
4be43953 | 2025 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
2026 | stack.store (regs[ARM_SP_REGNUM], 12, |
2027 | regs[fp_start_reg++]); | |
96baa820 | 2028 | } |
c906108c | 2029 | } |
0d39a070 DJ |
2030 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
2031 | { | |
2032 | /* Allow some special function calls when skipping the | |
2033 | prologue; GCC generates these before storing arguments to | |
2034 | the stack. */ | |
2035 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
2036 | ||
e0634ccf | 2037 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
2038 | continue; |
2039 | else | |
2040 | break; | |
2041 | } | |
d4473757 | 2042 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 2043 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
2044 | else if (arm_instruction_changes_pc (insn)) |
2045 | /* Don't scan past anything that might change control flow. */ | |
2046 | break; | |
f303bc3e YQ |
2047 | else if (arm_instruction_restores_sp (insn)) |
2048 | { | |
2049 | /* Don't scan past the epilogue. */ | |
2050 | break; | |
2051 | } | |
d19f7eee UW |
2052 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
2053 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2054 | /* Ignore block loads from the stack, potentially copying | |
2055 | parameters from memory. */ | |
2056 | continue; | |
2057 | else if ((insn & 0xfc500000) == 0xe4100000 | |
2058 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
2059 | /* Similarly ignore single loads from the stack. */ | |
2060 | continue; | |
0d39a070 DJ |
2061 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
2062 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
2063 | register instead of the stack. */ | |
d4473757 | 2064 | continue; |
0d39a070 DJ |
2065 | else |
2066 | { | |
21daaaaf YQ |
2067 | /* The optimizer might shove anything into the prologue, if |
2068 | we build up cache (cache != NULL) from scanning prologue, | |
2069 | we just skip what we don't recognize and scan further to | |
2070 | make cache as complete as possible. However, if we skip | |
2071 | prologue, we'll stop immediately on unrecognized | |
2072 | instruction. */ | |
0d39a070 | 2073 | unrecognized_pc = current_pc; |
21daaaaf YQ |
2074 | if (cache != NULL) |
2075 | continue; | |
2076 | else | |
2077 | break; | |
0d39a070 | 2078 | } |
c906108c SS |
2079 | } |
2080 | ||
0d39a070 DJ |
2081 | if (unrecognized_pc == 0) |
2082 | unrecognized_pc = current_pc; | |
2083 | ||
0d39a070 DJ |
2084 | if (cache) |
2085 | { | |
4072f920 YQ |
2086 | int framereg, framesize; |
2087 | ||
2088 | /* The frame size is just the distance from the frame register | |
2089 | to the original stack pointer. */ | |
2090 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
2091 | { | |
2092 | /* Frame pointer is fp. */ | |
2093 | framereg = ARM_FP_REGNUM; | |
2094 | framesize = -regs[ARM_FP_REGNUM].k; | |
2095 | } | |
2096 | else | |
2097 | { | |
2098 | /* Try the stack pointer... this is a bit desperate. */ | |
2099 | framereg = ARM_SP_REGNUM; | |
2100 | framesize = -regs[ARM_SP_REGNUM].k; | |
2101 | } | |
2102 | ||
0d39a070 DJ |
2103 | cache->framereg = framereg; |
2104 | cache->framesize = framesize; | |
2105 | ||
2106 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 2107 | if (stack.find_reg (gdbarch, regno, &offset)) |
10245fe8 YR |
2108 | { |
2109 | cache->saved_regs[regno].set_addr (offset); | |
2110 | if (regno == ARM_SP_REGNUM) | |
2111 | arm_cache_set_active_sp_value(cache, tdep, offset); | |
2112 | } | |
0d39a070 DJ |
2113 | } |
2114 | ||
7cb6d92a SM |
2115 | arm_debug_printf ("Prologue scan stopped at %s", |
2116 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 2117 | |
0d39a070 DJ |
2118 | return unrecognized_pc; |
2119 | } | |
2120 | ||
2121 | static void | |
2122 | arm_scan_prologue (struct frame_info *this_frame, | |
2123 | struct arm_prologue_cache *cache) | |
2124 | { | |
2125 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2126 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 2127 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
2128 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
2129 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
08106042 | 2130 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
0d39a070 DJ |
2131 | |
2132 | /* Assume there is no frame until proven otherwise. */ | |
2133 | cache->framereg = ARM_SP_REGNUM; | |
2134 | cache->framesize = 0; | |
2135 | ||
2136 | /* Check for Thumb prologue. */ | |
2137 | if (arm_frame_is_thumb (this_frame)) | |
2138 | { | |
2139 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
2140 | return; | |
2141 | } | |
2142 | ||
2143 | /* Find the function prologue. If we can't find the function in | |
2144 | the symbol table, peek in the stack frame to find the PC. */ | |
2145 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
2146 | &prologue_end)) | |
2147 | { | |
2148 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 2149 | for unoptimized code) is to do the following: |
0d39a070 DJ |
2150 | |
2151 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
2152 | ||
2153 | if (sal.line == 0) | |
2154 | prologue_end = prev_pc; | |
2155 | else if (sal.end < prologue_end) | |
2156 | prologue_end = sal.end; | |
2157 | ||
2158 | This mechanism is very accurate so long as the optimizer | |
2159 | doesn't move any instructions from the function body into the | |
2160 | prologue. If this happens, sal.end will be the last | |
2161 | instruction in the first hunk of prologue code just before | |
2162 | the first instruction that the scheduler has moved from | |
2163 | the body to the prologue. | |
2164 | ||
2165 | In order to make sure that we scan all of the prologue | |
2166 | instructions, we use a slightly less accurate mechanism which | |
2167 | may scan more than necessary. To help compensate for this | |
2168 | lack of accuracy, the prologue scanning loop below contains | |
2169 | several clauses which'll cause the loop to terminate early if | |
2170 | an implausible prologue instruction is encountered. | |
2171 | ||
2172 | The expression | |
2173 | ||
2174 | prologue_start + 64 | |
2175 | ||
2176 | is a suitable endpoint since it accounts for the largest | |
2177 | possible prologue plus up to five instructions inserted by | |
2178 | the scheduler. */ | |
2179 | ||
2180 | if (prologue_end > prologue_start + 64) | |
2181 | { | |
2182 | prologue_end = prologue_start + 64; /* See above. */ | |
2183 | } | |
2184 | } | |
2185 | else | |
2186 | { | |
2187 | /* We have no symbol information. Our only option is to assume this | |
2188 | function has a standard stack frame and the normal frame register. | |
2189 | Then, we can find the value of our frame pointer on entrance to | |
2190 | the callee (or at the present moment if this is the innermost frame). | |
2191 | The value stored there should be the address of the stmfd + 8. */ | |
2192 | CORE_ADDR frame_loc; | |
7913a64c | 2193 | ULONGEST return_value; |
0d39a070 | 2194 | |
9e237747 | 2195 | /* AAPCS does not use a frame register, so we can abort here. */ |
345bd07c | 2196 | if (tdep->arm_abi == ARM_ABI_AAPCS) |
dda83cd7 | 2197 | return; |
9e237747 | 2198 | |
0d39a070 | 2199 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
2200 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
2201 | &return_value)) | |
dda83cd7 | 2202 | return; |
0d39a070 | 2203 | else |
dda83cd7 SM |
2204 | { |
2205 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 2206 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
2207 | prologue_end = prologue_start + 64; /* See above. */ |
2208 | } | |
0d39a070 DJ |
2209 | } |
2210 | ||
2211 | if (prev_pc < prologue_end) | |
2212 | prologue_end = prev_pc; | |
2213 | ||
9ecab40c SM |
2214 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
2215 | target_arm_instruction_reader ()); | |
c906108c SS |
2216 | } |
2217 | ||
eb5492fa | 2218 | static struct arm_prologue_cache * |
a262aec2 | 2219 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 2220 | { |
eb5492fa DJ |
2221 | int reg; |
2222 | struct arm_prologue_cache *cache; | |
1ef3351b | 2223 | CORE_ADDR unwound_fp, prev_sp; |
c5aa993b | 2224 | |
35d5d4ee | 2225 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 2226 | arm_cache_init (cache, this_frame); |
c906108c | 2227 | |
a262aec2 | 2228 | arm_scan_prologue (this_frame, cache); |
848cfffb | 2229 | |
a262aec2 | 2230 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
2231 | if (unwound_fp == 0) |
2232 | return cache; | |
c906108c | 2233 | |
ae7e2f45 | 2234 | arm_gdbarch_tdep *tdep = |
08106042 | 2235 | gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2236 | |
1ef3351b YR |
2237 | prev_sp = unwound_fp + cache->framesize; |
2238 | arm_cache_set_active_sp_value (cache, tdep, prev_sp); | |
c906108c | 2239 | |
eb5492fa DJ |
2240 | /* Calculate actual addresses of saved registers using offsets |
2241 | determined by arm_scan_prologue. */ | |
a262aec2 | 2242 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
a9a87d35 | 2243 | if (cache->saved_regs[reg].is_addr ()) |
1ef3351b YR |
2244 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () + |
2245 | prev_sp); | |
eb5492fa DJ |
2246 | |
2247 | return cache; | |
c906108c SS |
2248 | } |
2249 | ||
c1ee9414 LM |
2250 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
2251 | ||
2252 | static enum unwind_stop_reason | |
2253 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
2254 | void **this_cache) | |
2255 | { | |
2256 | struct arm_prologue_cache *cache; | |
2257 | CORE_ADDR pc; | |
2258 | ||
2259 | if (*this_cache == NULL) | |
2260 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 2261 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
2262 | |
2263 | /* This is meant to halt the backtrace at "_start". */ | |
2264 | pc = get_frame_pc (this_frame); | |
345bd07c | 2265 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 2266 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (arch); |
345bd07c | 2267 | if (pc <= tdep->lowest_pc) |
c1ee9414 LM |
2268 | return UNWIND_OUTERMOST; |
2269 | ||
2270 | /* If we've hit a wall, stop. */ | |
ae7e2f45 | 2271 | if (arm_cache_get_prev_sp_value (cache, tdep) == 0) |
c1ee9414 LM |
2272 | return UNWIND_OUTERMOST; |
2273 | ||
2274 | return UNWIND_NO_REASON; | |
2275 | } | |
2276 | ||
eb5492fa DJ |
2277 | /* Our frame ID for a normal frame is the current function's starting PC |
2278 | and the caller's SP when we were called. */ | |
c906108c | 2279 | |
148754e5 | 2280 | static void |
a262aec2 | 2281 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
2282 | void **this_cache, |
2283 | struct frame_id *this_id) | |
c906108c | 2284 | { |
eb5492fa DJ |
2285 | struct arm_prologue_cache *cache; |
2286 | struct frame_id id; | |
2c404490 | 2287 | CORE_ADDR pc, func; |
f079148d | 2288 | |
eb5492fa | 2289 | if (*this_cache == NULL) |
a262aec2 | 2290 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2291 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 2292 | |
ae7e2f45 | 2293 | arm_gdbarch_tdep *tdep |
08106042 | 2294 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2295 | |
0e9e9abd UW |
2296 | /* Use function start address as part of the frame ID. If we cannot |
2297 | identify the start address (due to missing symbol information), | |
2298 | fall back to just using the current PC. */ | |
c1ee9414 | 2299 | pc = get_frame_pc (this_frame); |
2c404490 | 2300 | func = get_frame_func (this_frame); |
0e9e9abd UW |
2301 | if (!func) |
2302 | func = pc; | |
2303 | ||
ae7e2f45 | 2304 | id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), func); |
eb5492fa | 2305 | *this_id = id; |
c906108c SS |
2306 | } |
2307 | ||
a262aec2 DJ |
2308 | static struct value * |
2309 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 2310 | void **this_cache, |
a262aec2 | 2311 | int prev_regnum) |
24de872b | 2312 | { |
24568a2c | 2313 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b | 2314 | struct arm_prologue_cache *cache; |
ef273377 | 2315 | CORE_ADDR sp_value; |
24de872b | 2316 | |
eb5492fa | 2317 | if (*this_cache == NULL) |
a262aec2 | 2318 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2319 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 2320 | |
08106042 | 2321 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
2322 | |
2323 | /* If this frame has signed the return address, mark it as so. */ | |
2324 | if (tdep->have_pacbti && cache->ra_signed_state.has_value () | |
2325 | && *cache->ra_signed_state) | |
2326 | set_frame_previous_pc_masked (this_frame); | |
2327 | ||
eb5492fa | 2328 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
2329 | instead. The prologue may save PC, but it will point into this |
2330 | frame's prologue, not the next frame's resume location. Also | |
2331 | strip the saved T bit. A valid LR may have the low bit set, but | |
2332 | a valid PC never does. */ | |
eb5492fa | 2333 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
2334 | { |
2335 | CORE_ADDR lr; | |
2336 | ||
2337 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2338 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 2339 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 2340 | } |
24de872b | 2341 | |
eb5492fa | 2342 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 2343 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2344 | The value was already reconstructed into PREV_SP. */ |
2345 | if (prev_regnum == ARM_SP_REGNUM) | |
ae7e2f45 CL |
2346 | return frame_unwind_got_constant (this_frame, prev_regnum, |
2347 | arm_cache_get_prev_sp_value (cache, tdep)); | |
eb5492fa | 2348 | |
ef273377 CL |
2349 | /* The value might be one of the alternative SP, if so, use the |
2350 | value already constructed. */ | |
d65edaa0 | 2351 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
2352 | { |
2353 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
2354 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
2355 | } | |
2356 | ||
b39cc962 DJ |
2357 | /* The CPSR may have been changed by the call instruction and by the |
2358 | called function. The only bit we can reconstruct is the T bit, | |
2359 | by checking the low bit of LR as of the call. This is a reliable | |
2360 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2361 | Thumb code, which could get away with a clear low bit as long as | |
2362 | the called function did not use bx. Guess that all other | |
2363 | bits are unchanged; the condition flags are presumably lost, | |
2364 | but the processor status is likely valid. */ | |
2365 | if (prev_regnum == ARM_PS_REGNUM) | |
2366 | { | |
8c9ae6df YR |
2367 | ULONGEST cpsr = get_frame_register_unsigned (this_frame, prev_regnum); |
2368 | CORE_ADDR lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
b39cc962 | 2369 | |
8c9ae6df | 2370 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
b39cc962 DJ |
2371 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2372 | } | |
2373 | ||
a262aec2 DJ |
2374 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2375 | prev_regnum); | |
eb5492fa DJ |
2376 | } |
2377 | ||
6bd434d6 | 2378 | static frame_unwind arm_prologue_unwind = { |
a154d838 | 2379 | "arm prologue", |
eb5492fa | 2380 | NORMAL_FRAME, |
c1ee9414 | 2381 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2382 | arm_prologue_this_id, |
a262aec2 DJ |
2383 | arm_prologue_prev_register, |
2384 | NULL, | |
2385 | default_frame_sniffer | |
eb5492fa DJ |
2386 | }; |
2387 | ||
0e9e9abd UW |
2388 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2389 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2390 | personality routines; the cache will contain only the frame unwinding | |
2391 | instructions associated with the entry (not the descriptors). */ | |
2392 | ||
0e9e9abd UW |
2393 | struct arm_exidx_entry |
2394 | { | |
227031b2 | 2395 | CORE_ADDR addr; |
0e9e9abd | 2396 | gdb_byte *entry; |
7a5d944b TT |
2397 | |
2398 | bool operator< (const arm_exidx_entry &other) const | |
2399 | { | |
2400 | return addr < other.addr; | |
2401 | } | |
0e9e9abd | 2402 | }; |
0e9e9abd UW |
2403 | |
2404 | struct arm_exidx_data | |
2405 | { | |
7a5d944b | 2406 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2407 | }; |
2408 | ||
a2726d4f LM |
2409 | /* Per-BFD key to store exception handling information. */ |
2410 | static const struct bfd_key<arm_exidx_data> arm_exidx_data_key; | |
0e9e9abd UW |
2411 | |
2412 | static struct obj_section * | |
2413 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2414 | { | |
2415 | struct obj_section *osect; | |
2416 | ||
2417 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2418 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2419 | { |
2420 | bfd_vma start, size; | |
fd361982 AM |
2421 | start = bfd_section_vma (osect->the_bfd_section); |
2422 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2423 | |
2424 | if (start <= vma && vma < start + size) | |
2425 | return osect; | |
2426 | } | |
2427 | ||
2428 | return NULL; | |
2429 | } | |
2430 | ||
2431 | /* Parse contents of exception table and exception index sections | |
2432 | of OBJFILE, and fill in the exception table entry cache. | |
2433 | ||
2434 | For each entry that refers to a standard ARM-defined personality | |
2435 | routine, extract the frame unwinding instructions (from either | |
2436 | the index or the table section). The unwinding instructions | |
2437 | are normalized by: | |
2438 | - extracting them from the rest of the table data | |
2439 | - converting to host endianness | |
2440 | - appending the implicit 0xb0 ("Finish") code | |
2441 | ||
2442 | The extracted and normalized instructions are stored for later | |
2443 | retrieval by the arm_find_exidx_entry routine. */ | |
2444 | ||
2445 | static void | |
2446 | arm_exidx_new_objfile (struct objfile *objfile) | |
2447 | { | |
0e9e9abd UW |
2448 | struct arm_exidx_data *data; |
2449 | asection *exidx, *extab; | |
2450 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2451 | LONGEST i; |
2452 | ||
2453 | /* If we've already touched this file, do nothing. */ | |
a2726d4f | 2454 | if (!objfile || arm_exidx_data_key.get (objfile->obfd) != NULL) |
0e9e9abd UW |
2455 | return; |
2456 | ||
2457 | /* Read contents of exception table and index. */ | |
a5eda10c | 2458 | exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); |
984c7238 | 2459 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2460 | if (exidx) |
2461 | { | |
fd361982 AM |
2462 | exidx_vma = bfd_section_vma (exidx); |
2463 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd UW |
2464 | |
2465 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
984c7238 TT |
2466 | exidx_data.data (), 0, |
2467 | exidx_data.size ())) | |
2468 | return; | |
0e9e9abd UW |
2469 | } |
2470 | ||
2471 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
984c7238 | 2472 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2473 | if (extab) |
2474 | { | |
fd361982 AM |
2475 | extab_vma = bfd_section_vma (extab); |
2476 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd UW |
2477 | |
2478 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
984c7238 TT |
2479 | extab_data.data (), 0, |
2480 | extab_data.size ())) | |
2481 | return; | |
0e9e9abd UW |
2482 | } |
2483 | ||
2484 | /* Allocate exception table data structure. */ | |
a2726d4f | 2485 | data = arm_exidx_data_key.emplace (objfile->obfd); |
7a5d944b | 2486 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2487 | |
2488 | /* Fill in exception table. */ | |
984c7238 | 2489 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2490 | { |
2491 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2492 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2493 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2494 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2495 | bfd_vma addr = 0, word = 0; |
2496 | int n_bytes = 0, n_words = 0; | |
2497 | struct obj_section *sec; | |
2498 | gdb_byte *entry = NULL; | |
2499 | ||
2500 | /* Extract address of start of function. */ | |
2501 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2502 | idx += exidx_vma + i * 8; | |
2503 | ||
2504 | /* Find section containing function and compute section offset. */ | |
2505 | sec = arm_obj_section_from_vma (objfile, idx); | |
2506 | if (sec == NULL) | |
2507 | continue; | |
fd361982 | 2508 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2509 | |
2510 | /* Determine address of exception table entry. */ | |
2511 | if (val == 1) | |
2512 | { | |
2513 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2514 | } | |
2515 | else if ((val & 0xff000000) == 0x80000000) | |
2516 | { | |
2517 | /* Exception table entry embedded in .ARM.exidx | |
2518 | -- must be short form. */ | |
2519 | word = val; | |
2520 | n_bytes = 3; | |
2521 | } | |
2522 | else if (!(val & 0x80000000)) | |
2523 | { | |
2524 | /* Exception table entry in .ARM.extab. */ | |
2525 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2526 | addr += exidx_vma + i * 8 + 4; | |
2527 | ||
984c7238 | 2528 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2529 | { |
2530 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2531 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2532 | addr += 4; |
2533 | ||
2534 | if ((word & 0xff000000) == 0x80000000) | |
2535 | { | |
2536 | /* Short form. */ | |
2537 | n_bytes = 3; | |
2538 | } | |
2539 | else if ((word & 0xff000000) == 0x81000000 | |
2540 | || (word & 0xff000000) == 0x82000000) | |
2541 | { | |
2542 | /* Long form. */ | |
2543 | n_bytes = 2; | |
2544 | n_words = ((word >> 16) & 0xff); | |
2545 | } | |
2546 | else if (!(word & 0x80000000)) | |
2547 | { | |
2548 | bfd_vma pers; | |
2549 | struct obj_section *pers_sec; | |
2550 | int gnu_personality = 0; | |
2551 | ||
2552 | /* Custom personality routine. */ | |
2553 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2554 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2555 | ||
2556 | /* Check whether we've got one of the variants of the | |
2557 | GNU personality routines. */ | |
2558 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2559 | if (pers_sec) | |
2560 | { | |
2561 | static const char *personality[] = | |
2562 | { | |
2563 | "__gcc_personality_v0", | |
2564 | "__gxx_personality_v0", | |
2565 | "__gcj_personality_v0", | |
2566 | "__gnu_objc_personality_v0", | |
2567 | NULL | |
2568 | }; | |
2569 | ||
0c1bcd23 | 2570 | CORE_ADDR pc = pers + pers_sec->offset (); |
0e9e9abd UW |
2571 | int k; |
2572 | ||
2573 | for (k = 0; personality[k]; k++) | |
2574 | if (lookup_minimal_symbol_by_pc_name | |
2575 | (pc, personality[k], objfile)) | |
2576 | { | |
2577 | gnu_personality = 1; | |
2578 | break; | |
2579 | } | |
2580 | } | |
2581 | ||
2582 | /* If so, the next word contains a word count in the high | |
2583 | byte, followed by the same unwind instructions as the | |
2584 | pre-defined forms. */ | |
2585 | if (gnu_personality | |
984c7238 | 2586 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2587 | { |
2588 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2589 | (extab_data.data () |
2590 | + addr - extab_vma)); | |
0e9e9abd UW |
2591 | addr += 4; |
2592 | n_bytes = 3; | |
2593 | n_words = ((word >> 24) & 0xff); | |
2594 | } | |
2595 | } | |
2596 | } | |
2597 | } | |
2598 | ||
2599 | /* Sanity check address. */ | |
2600 | if (n_words) | |
984c7238 TT |
2601 | if (addr < extab_vma |
2602 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2603 | n_words = n_bytes = 0; |
2604 | ||
2605 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2606 | significant bytes are valid), followed by N_WORDS words in the | |
2607 | extab section starting at ADDR. */ | |
2608 | if (n_bytes || n_words) | |
2609 | { | |
224c3ddb SM |
2610 | gdb_byte *p = entry |
2611 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2612 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2613 | |
2614 | while (n_bytes--) | |
2615 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2616 | ||
2617 | while (n_words--) | |
2618 | { | |
2619 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2620 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2621 | addr += 4; |
2622 | ||
2623 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2624 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2625 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2626 | *p++ = (gdb_byte) (word & 0xff); | |
2627 | } | |
2628 | ||
2629 | /* Implied "Finish" to terminate the list. */ | |
2630 | *p++ = 0xb0; | |
2631 | } | |
2632 | ||
2633 | /* Push entry onto vector. They are guaranteed to always | |
2634 | appear in order of increasing addresses. */ | |
2635 | new_exidx_entry.addr = idx; | |
2636 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2637 | data->section_maps[sec->the_bfd_section->index].push_back |
2638 | (new_exidx_entry); | |
0e9e9abd | 2639 | } |
0e9e9abd UW |
2640 | } |
2641 | ||
2642 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2643 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2644 | set *START to the start of the region covered by this entry. */ | |
2645 | ||
2646 | static gdb_byte * | |
2647 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2648 | { | |
2649 | struct obj_section *sec; | |
2650 | ||
2651 | sec = find_pc_section (memaddr); | |
2652 | if (sec != NULL) | |
2653 | { | |
2654 | struct arm_exidx_data *data; | |
0c1bcd23 | 2655 | struct arm_exidx_entry map_key = { memaddr - sec->addr (), 0 }; |
0e9e9abd | 2656 | |
a2726d4f | 2657 | data = arm_exidx_data_key.get (sec->objfile->obfd); |
0e9e9abd UW |
2658 | if (data != NULL) |
2659 | { | |
7a5d944b TT |
2660 | std::vector<arm_exidx_entry> &map |
2661 | = data->section_maps[sec->the_bfd_section->index]; | |
2662 | if (!map.empty ()) | |
0e9e9abd | 2663 | { |
7a5d944b | 2664 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2665 | |
7a5d944b | 2666 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2667 | point. If the following symbol starts at this exact |
2668 | address, we use that; otherwise, the preceding | |
2669 | exception table entry covers this address. */ | |
7a5d944b | 2670 | if (idx < map.end ()) |
0e9e9abd | 2671 | { |
7a5d944b | 2672 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2673 | { |
2674 | if (start) | |
0c1bcd23 | 2675 | *start = idx->addr + sec->addr (); |
7a5d944b | 2676 | return idx->entry; |
0e9e9abd UW |
2677 | } |
2678 | } | |
2679 | ||
7a5d944b | 2680 | if (idx > map.begin ()) |
0e9e9abd | 2681 | { |
7a5d944b | 2682 | idx = idx - 1; |
0e9e9abd | 2683 | if (start) |
0c1bcd23 | 2684 | *start = idx->addr + sec->addr (); |
7a5d944b | 2685 | return idx->entry; |
0e9e9abd UW |
2686 | } |
2687 | } | |
2688 | } | |
2689 | } | |
2690 | ||
2691 | return NULL; | |
2692 | } | |
2693 | ||
2694 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2695 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2696 | return a prologue cache structure describing how to unwind this frame. | |
2697 | ||
2698 | Return NULL if the unwinding instruction list contains a "spare", | |
2699 | "reserved" or "refuse to unwind" instruction as defined in section | |
2700 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2701 | for the ARM Architecture" document. */ | |
2702 | ||
2703 | static struct arm_prologue_cache * | |
2704 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2705 | { | |
2706 | CORE_ADDR vsp = 0; | |
2707 | int vsp_valid = 0; | |
2708 | ||
2709 | struct arm_prologue_cache *cache; | |
2710 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 2711 | arm_cache_init (cache, this_frame); |
0e9e9abd UW |
2712 | |
2713 | for (;;) | |
2714 | { | |
2715 | gdb_byte insn; | |
2716 | ||
2717 | /* Whenever we reload SP, we actually have to retrieve its | |
2718 | actual value in the current frame. */ | |
2719 | if (!vsp_valid) | |
2720 | { | |
a9a87d35 | 2721 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
0e9e9abd | 2722 | { |
098caef4 | 2723 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2724 | vsp = get_frame_register_unsigned (this_frame, reg); |
2725 | } | |
2726 | else | |
2727 | { | |
098caef4 | 2728 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr (); |
0e9e9abd UW |
2729 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); |
2730 | } | |
2731 | ||
2732 | vsp_valid = 1; | |
2733 | } | |
2734 | ||
2735 | /* Decode next unwind instruction. */ | |
2736 | insn = *entry++; | |
2737 | ||
2738 | if ((insn & 0xc0) == 0) | |
2739 | { | |
2740 | int offset = insn & 0x3f; | |
2741 | vsp += (offset << 2) + 4; | |
2742 | } | |
2743 | else if ((insn & 0xc0) == 0x40) | |
2744 | { | |
2745 | int offset = insn & 0x3f; | |
2746 | vsp -= (offset << 2) + 4; | |
2747 | } | |
2748 | else if ((insn & 0xf0) == 0x80) | |
2749 | { | |
2750 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2751 | int i; | |
2752 | ||
2753 | /* The special case of an all-zero mask identifies | |
2754 | "Refuse to unwind". We return NULL to fall back | |
2755 | to the prologue analyzer. */ | |
2756 | if (mask == 0) | |
2757 | return NULL; | |
2758 | ||
2759 | /* Pop registers r4..r15 under mask. */ | |
2760 | for (i = 0; i < 12; i++) | |
2761 | if (mask & (1 << i)) | |
2762 | { | |
098caef4 | 2763 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2764 | vsp += 4; |
2765 | } | |
2766 | ||
2767 | /* Special-case popping SP -- we need to reload vsp. */ | |
2768 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2769 | vsp_valid = 0; | |
2770 | } | |
2771 | else if ((insn & 0xf0) == 0x90) | |
2772 | { | |
2773 | int reg = insn & 0xf; | |
2774 | ||
2775 | /* Reserved cases. */ | |
2776 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2777 | return NULL; | |
2778 | ||
2779 | /* Set SP from another register and mark VSP for reload. */ | |
2780 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2781 | vsp_valid = 0; | |
2782 | } | |
2783 | else if ((insn & 0xf0) == 0xa0) | |
2784 | { | |
2785 | int count = insn & 0x7; | |
2786 | int pop_lr = (insn & 0x8) != 0; | |
2787 | int i; | |
2788 | ||
2789 | /* Pop r4..r[4+count]. */ | |
2790 | for (i = 0; i <= count; i++) | |
2791 | { | |
098caef4 | 2792 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2793 | vsp += 4; |
2794 | } | |
2795 | ||
2796 | /* If indicated by flag, pop LR as well. */ | |
2797 | if (pop_lr) | |
2798 | { | |
098caef4 | 2799 | cache->saved_regs[ARM_LR_REGNUM].set_addr (vsp); |
0e9e9abd UW |
2800 | vsp += 4; |
2801 | } | |
2802 | } | |
2803 | else if (insn == 0xb0) | |
2804 | { | |
2805 | /* We could only have updated PC by popping into it; if so, it | |
2806 | will show up as address. Otherwise, copy LR into PC. */ | |
a9a87d35 | 2807 | if (!cache->saved_regs[ARM_PC_REGNUM].is_addr ()) |
0e9e9abd UW |
2808 | cache->saved_regs[ARM_PC_REGNUM] |
2809 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2810 | ||
2811 | /* We're done. */ | |
2812 | break; | |
2813 | } | |
2814 | else if (insn == 0xb1) | |
2815 | { | |
2816 | int mask = *entry++; | |
2817 | int i; | |
2818 | ||
2819 | /* All-zero mask and mask >= 16 is "spare". */ | |
2820 | if (mask == 0 || mask >= 16) | |
2821 | return NULL; | |
2822 | ||
2823 | /* Pop r0..r3 under mask. */ | |
2824 | for (i = 0; i < 4; i++) | |
2825 | if (mask & (1 << i)) | |
2826 | { | |
098caef4 | 2827 | cache->saved_regs[i].set_addr (vsp); |
0e9e9abd UW |
2828 | vsp += 4; |
2829 | } | |
2830 | } | |
2831 | else if (insn == 0xb2) | |
2832 | { | |
2833 | ULONGEST offset = 0; | |
2834 | unsigned shift = 0; | |
2835 | ||
2836 | do | |
2837 | { | |
2838 | offset |= (*entry & 0x7f) << shift; | |
2839 | shift += 7; | |
2840 | } | |
2841 | while (*entry++ & 0x80); | |
2842 | ||
2843 | vsp += 0x204 + (offset << 2); | |
2844 | } | |
2845 | else if (insn == 0xb3) | |
2846 | { | |
2847 | int start = *entry >> 4; | |
2848 | int count = (*entry++) & 0xf; | |
2849 | int i; | |
2850 | ||
2851 | /* Only registers D0..D15 are valid here. */ | |
2852 | if (start + count >= 16) | |
2853 | return NULL; | |
2854 | ||
2855 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2856 | for (i = 0; i <= count; i++) | |
2857 | { | |
098caef4 | 2858 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2859 | vsp += 8; |
2860 | } | |
2861 | ||
2862 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2863 | vsp += 4; | |
2864 | } | |
2865 | else if ((insn & 0xf8) == 0xb8) | |
2866 | { | |
2867 | int count = insn & 0x7; | |
2868 | int i; | |
2869 | ||
2870 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2871 | for (i = 0; i <= count; i++) | |
2872 | { | |
098caef4 | 2873 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2874 | vsp += 8; |
2875 | } | |
2876 | ||
2877 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2878 | vsp += 4; | |
2879 | } | |
2880 | else if (insn == 0xc6) | |
2881 | { | |
2882 | int start = *entry >> 4; | |
2883 | int count = (*entry++) & 0xf; | |
2884 | int i; | |
2885 | ||
2886 | /* Only registers WR0..WR15 are valid. */ | |
2887 | if (start + count >= 16) | |
2888 | return NULL; | |
2889 | ||
2890 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2891 | for (i = 0; i <= count; i++) | |
2892 | { | |
098caef4 | 2893 | cache->saved_regs[ARM_WR0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2894 | vsp += 8; |
2895 | } | |
2896 | } | |
2897 | else if (insn == 0xc7) | |
2898 | { | |
2899 | int mask = *entry++; | |
2900 | int i; | |
2901 | ||
2902 | /* All-zero mask and mask >= 16 is "spare". */ | |
2903 | if (mask == 0 || mask >= 16) | |
2904 | return NULL; | |
2905 | ||
2906 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2907 | for (i = 0; i < 4; i++) | |
2908 | if (mask & (1 << i)) | |
2909 | { | |
098caef4 | 2910 | cache->saved_regs[ARM_WCGR0_REGNUM + i].set_addr (vsp); |
0e9e9abd UW |
2911 | vsp += 4; |
2912 | } | |
2913 | } | |
2914 | else if ((insn & 0xf8) == 0xc0) | |
2915 | { | |
2916 | int count = insn & 0x7; | |
2917 | int i; | |
2918 | ||
2919 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2920 | for (i = 0; i <= count; i++) | |
2921 | { | |
098caef4 | 2922 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].set_addr (vsp); |
0e9e9abd UW |
2923 | vsp += 8; |
2924 | } | |
2925 | } | |
2926 | else if (insn == 0xc8) | |
2927 | { | |
2928 | int start = *entry >> 4; | |
2929 | int count = (*entry++) & 0xf; | |
2930 | int i; | |
2931 | ||
2932 | /* Only registers D0..D31 are valid. */ | |
2933 | if (start + count >= 16) | |
2934 | return NULL; | |
2935 | ||
2936 | /* Pop VFP double-precision registers | |
2937 | D[16+start]..D[16+start+count]. */ | |
2938 | for (i = 0; i <= count; i++) | |
2939 | { | |
098caef4 | 2940 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].set_addr (vsp); |
0e9e9abd UW |
2941 | vsp += 8; |
2942 | } | |
2943 | } | |
2944 | else if (insn == 0xc9) | |
2945 | { | |
2946 | int start = *entry >> 4; | |
2947 | int count = (*entry++) & 0xf; | |
2948 | int i; | |
2949 | ||
2950 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2951 | for (i = 0; i <= count; i++) | |
2952 | { | |
098caef4 | 2953 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2954 | vsp += 8; |
2955 | } | |
2956 | } | |
2957 | else if ((insn & 0xf8) == 0xd0) | |
2958 | { | |
2959 | int count = insn & 0x7; | |
2960 | int i; | |
2961 | ||
2962 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2963 | for (i = 0; i <= count; i++) | |
2964 | { | |
098caef4 | 2965 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2966 | vsp += 8; |
2967 | } | |
2968 | } | |
2969 | else | |
2970 | { | |
2971 | /* Everything else is "spare". */ | |
2972 | return NULL; | |
2973 | } | |
2974 | } | |
2975 | ||
2976 | /* If we restore SP from a register, assume this was the frame register. | |
2977 | Otherwise just fall back to SP as frame register. */ | |
a9a87d35 | 2978 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
098caef4 | 2979 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2980 | else |
2981 | cache->framereg = ARM_SP_REGNUM; | |
2982 | ||
2983 | /* Determine offset to previous frame. */ | |
2984 | cache->framesize | |
2985 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2986 | ||
2987 | /* We already got the previous SP. */ | |
ae7e2f45 | 2988 | arm_gdbarch_tdep *tdep |
08106042 | 2989 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 2990 | arm_cache_set_active_sp_value (cache, tdep, vsp); |
0e9e9abd UW |
2991 | |
2992 | return cache; | |
2993 | } | |
2994 | ||
2995 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2996 | already computes a filled-in prologue cache, which is then used | |
2997 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2998 | routines also used for prologue-parsing based unwinding. */ | |
2999 | ||
3000 | static int | |
3001 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
3002 | struct frame_info *this_frame, | |
3003 | void **this_prologue_cache) | |
3004 | { | |
3005 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3006 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3007 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
3008 | struct arm_prologue_cache *cache; | |
3009 | gdb_byte *entry; | |
3010 | ||
3011 | /* See if we have an ARM exception table entry covering this address. */ | |
3012 | addr_in_block = get_frame_address_in_block (this_frame); | |
3013 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
3014 | if (!entry) | |
3015 | return 0; | |
3016 | ||
3017 | /* The ARM exception table does not describe unwind information | |
3018 | for arbitrary PC values, but is guaranteed to be correct only | |
3019 | at call sites. We have to decide here whether we want to use | |
3020 | ARM exception table information for this frame, or fall back | |
3021 | to using prologue parsing. (Note that if we have DWARF CFI, | |
3022 | this sniffer isn't even called -- CFI is always preferred.) | |
3023 | ||
3024 | Before we make this decision, however, we check whether we | |
3025 | actually have *symbol* information for the current frame. | |
3026 | If not, prologue parsing would not work anyway, so we might | |
3027 | as well use the exception table and hope for the best. */ | |
3028 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
3029 | { | |
3030 | int exc_valid = 0; | |
3031 | ||
3032 | /* If the next frame is "normal", we are at a call site in this | |
3033 | frame, so exception information is guaranteed to be valid. */ | |
3034 | if (get_next_frame (this_frame) | |
3035 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
3036 | exc_valid = 1; | |
3037 | ||
3038 | /* We also assume exception information is valid if we're currently | |
3039 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
3040 | ensure this, so that e.g. pthread cancellation works. */ |
3041 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 3042 | { |
7913a64c | 3043 | ULONGEST insn; |
416dc9c6 | 3044 | |
7913a64c YQ |
3045 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
3046 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
3047 | && (insn & 0xff00) == 0xdf00 /* svc */) |
3048 | exc_valid = 1; | |
0e9e9abd | 3049 | } |
d9311bfa AT |
3050 | else |
3051 | { | |
7913a64c | 3052 | ULONGEST insn; |
416dc9c6 | 3053 | |
7913a64c YQ |
3054 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
3055 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
3056 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
3057 | exc_valid = 1; | |
3058 | } | |
3059 | ||
0e9e9abd UW |
3060 | /* Bail out if we don't know that exception information is valid. */ |
3061 | if (!exc_valid) | |
3062 | return 0; | |
3063 | ||
3064 | /* The ARM exception index does not mark the *end* of the region | |
3065 | covered by the entry, and some functions will not have any entry. | |
3066 | To correctly recognize the end of the covered region, the linker | |
3067 | should have inserted dummy records with a CANTUNWIND marker. | |
3068 | ||
3069 | Unfortunately, current versions of GNU ld do not reliably do | |
3070 | this, and thus we may have found an incorrect entry above. | |
3071 | As a (temporary) sanity check, we only use the entry if it | |
3072 | lies *within* the bounds of the function. Note that this check | |
3073 | might reject perfectly valid entries that just happen to cover | |
3074 | multiple functions; therefore this check ought to be removed | |
3075 | once the linker is fixed. */ | |
3076 | if (func_start > exidx_region) | |
3077 | return 0; | |
3078 | } | |
3079 | ||
3080 | /* Decode the list of unwinding instructions into a prologue cache. | |
3081 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
3082 | cache = arm_exidx_fill_cache (this_frame, entry); | |
3083 | if (!cache) | |
3084 | return 0; | |
3085 | ||
3086 | *this_prologue_cache = cache; | |
3087 | return 1; | |
3088 | } | |
3089 | ||
3090 | struct frame_unwind arm_exidx_unwind = { | |
a154d838 | 3091 | "arm exidx", |
0e9e9abd | 3092 | NORMAL_FRAME, |
8fbca658 | 3093 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
3094 | arm_prologue_this_id, |
3095 | arm_prologue_prev_register, | |
3096 | NULL, | |
3097 | arm_exidx_unwind_sniffer | |
3098 | }; | |
3099 | ||
779aa56f YQ |
3100 | static struct arm_prologue_cache * |
3101 | arm_make_epilogue_frame_cache (struct frame_info *this_frame) | |
3102 | { | |
3103 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
3104 | int reg; |
3105 | ||
3106 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3107 | arm_cache_init (cache, this_frame); |
779aa56f YQ |
3108 | |
3109 | /* Still rely on the offset calculated from prologue. */ | |
3110 | arm_scan_prologue (this_frame, cache); | |
3111 | ||
3112 | /* Since we are in epilogue, the SP has been restored. */ | |
ae7e2f45 | 3113 | arm_gdbarch_tdep *tdep |
08106042 | 3114 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3115 | arm_cache_set_active_sp_value (cache, tdep, |
3116 | get_frame_register_unsigned (this_frame, | |
3117 | ARM_SP_REGNUM)); | |
779aa56f YQ |
3118 | |
3119 | /* Calculate actual addresses of saved registers using offsets | |
3120 | determined by arm_scan_prologue. */ | |
3121 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 3122 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 | 3123 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
ae7e2f45 | 3124 | + arm_cache_get_prev_sp_value (cache, tdep)); |
779aa56f YQ |
3125 | |
3126 | return cache; | |
3127 | } | |
3128 | ||
3129 | /* Implementation of function hook 'this_id' in | |
3130 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3131 | ||
3132 | static void | |
3133 | arm_epilogue_frame_this_id (struct frame_info *this_frame, | |
3134 | void **this_cache, | |
3135 | struct frame_id *this_id) | |
3136 | { | |
3137 | struct arm_prologue_cache *cache; | |
3138 | CORE_ADDR pc, func; | |
3139 | ||
3140 | if (*this_cache == NULL) | |
3141 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
3142 | cache = (struct arm_prologue_cache *) *this_cache; | |
3143 | ||
3144 | /* Use function start address as part of the frame ID. If we cannot | |
3145 | identify the start address (due to missing symbol information), | |
3146 | fall back to just using the current PC. */ | |
3147 | pc = get_frame_pc (this_frame); | |
3148 | func = get_frame_func (this_frame); | |
fb3f3d25 | 3149 | if (func == 0) |
779aa56f YQ |
3150 | func = pc; |
3151 | ||
ae7e2f45 | 3152 | arm_gdbarch_tdep *tdep |
08106042 | 3153 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3154 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), pc); |
779aa56f YQ |
3155 | } |
3156 | ||
3157 | /* Implementation of function hook 'prev_register' in | |
3158 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3159 | ||
3160 | static struct value * | |
3161 | arm_epilogue_frame_prev_register (struct frame_info *this_frame, | |
3162 | void **this_cache, int regnum) | |
3163 | { | |
779aa56f YQ |
3164 | if (*this_cache == NULL) |
3165 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
3166 | |
3167 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
3168 | } | |
3169 | ||
3170 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
3171 | CORE_ADDR pc); | |
3172 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
3173 | CORE_ADDR pc); | |
3174 | ||
3175 | /* Implementation of function hook 'sniffer' in | |
3176 | 'struct frame_uwnind' for epilogue unwinder. */ | |
3177 | ||
3178 | static int | |
3179 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
3180 | struct frame_info *this_frame, | |
3181 | void **this_prologue_cache) | |
3182 | { | |
3183 | if (frame_relative_level (this_frame) == 0) | |
3184 | { | |
3185 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3186 | CORE_ADDR pc = get_frame_pc (this_frame); | |
3187 | ||
3188 | if (arm_frame_is_thumb (this_frame)) | |
3189 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3190 | else | |
3191 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3192 | } | |
3193 | else | |
3194 | return 0; | |
3195 | } | |
3196 | ||
3197 | /* Frame unwinder from epilogue. */ | |
3198 | ||
3199 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
3200 | { | |
a154d838 | 3201 | "arm epilogue", |
779aa56f YQ |
3202 | NORMAL_FRAME, |
3203 | default_frame_unwind_stop_reason, | |
3204 | arm_epilogue_frame_this_id, | |
3205 | arm_epilogue_frame_prev_register, | |
3206 | NULL, | |
3207 | arm_epilogue_frame_sniffer, | |
3208 | }; | |
3209 | ||
80d8d390 YQ |
3210 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
3211 | trampoline, return the target PC. Otherwise return 0. | |
3212 | ||
3213 | void call0a (char c, short s, int i, long l) {} | |
3214 | ||
3215 | int main (void) | |
3216 | { | |
3217 | (*pointer_to_call0a) (c, s, i, l); | |
3218 | } | |
3219 | ||
3220 | Instead of calling a stub library function _call_via_xx (xx is | |
3221 | the register name), GCC may inline the trampoline in the object | |
3222 | file as below (register r2 has the address of call0a). | |
3223 | ||
3224 | .global main | |
3225 | .type main, %function | |
3226 | ... | |
3227 | bl .L1 | |
3228 | ... | |
3229 | .size main, .-main | |
3230 | ||
3231 | .L1: | |
3232 | bx r2 | |
3233 | ||
3234 | The trampoline 'bx r2' doesn't belong to main. */ | |
3235 | ||
3236 | static CORE_ADDR | |
3237 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
3238 | { | |
3239 | /* The heuristics of recognizing such trampoline is that FRAME is | |
3240 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
3241 | if (arm_frame_is_thumb (frame)) | |
3242 | { | |
3243 | gdb_byte buf[2]; | |
3244 | ||
3245 | if (target_read_memory (pc, buf, 2) == 0) | |
3246 | { | |
3247 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
3248 | enum bfd_endian byte_order_for_code | |
3249 | = gdbarch_byte_order_for_code (gdbarch); | |
3250 | uint16_t insn | |
3251 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3252 | ||
3253 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3254 | { | |
3255 | CORE_ADDR dest | |
3256 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
3257 | ||
3258 | /* Clear the LSB so that gdb core sets step-resume | |
3259 | breakpoint at the right address. */ | |
3260 | return UNMAKE_THUMB_ADDR (dest); | |
3261 | } | |
3262 | } | |
3263 | } | |
3264 | ||
3265 | return 0; | |
3266 | } | |
3267 | ||
909cf6ea | 3268 | static struct arm_prologue_cache * |
a262aec2 | 3269 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 3270 | { |
909cf6ea | 3271 | struct arm_prologue_cache *cache; |
909cf6ea | 3272 | |
35d5d4ee | 3273 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
0824193f | 3274 | arm_cache_init (cache, this_frame); |
909cf6ea | 3275 | |
ae7e2f45 | 3276 | arm_gdbarch_tdep *tdep |
08106042 | 3277 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3278 | arm_cache_set_active_sp_value (cache, tdep, |
3279 | get_frame_register_unsigned (this_frame, | |
3280 | ARM_SP_REGNUM)); | |
909cf6ea DJ |
3281 | |
3282 | return cache; | |
3283 | } | |
3284 | ||
3285 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3286 | ||
3287 | static void | |
a262aec2 | 3288 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
3289 | void **this_cache, |
3290 | struct frame_id *this_id) | |
3291 | { | |
3292 | struct arm_prologue_cache *cache; | |
3293 | ||
3294 | if (*this_cache == NULL) | |
a262aec2 | 3295 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 3296 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 3297 | |
ae7e2f45 | 3298 | arm_gdbarch_tdep *tdep |
08106042 | 3299 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 CL |
3300 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
3301 | get_frame_pc (this_frame)); | |
909cf6ea DJ |
3302 | } |
3303 | ||
a262aec2 DJ |
3304 | static int |
3305 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
3306 | struct frame_info *this_frame, | |
3307 | void **this_prologue_cache) | |
909cf6ea | 3308 | { |
93d42b30 | 3309 | CORE_ADDR addr_in_block; |
948f8e3d | 3310 | gdb_byte dummy[4]; |
18d18ac8 YQ |
3311 | CORE_ADDR pc, start_addr; |
3312 | const char *name; | |
909cf6ea | 3313 | |
a262aec2 | 3314 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 3315 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 3316 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
3317 | /* We also use the stub winder if the target memory is unreadable |
3318 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
3319 | || target_read_memory (pc, dummy, 4) != 0) |
3320 | return 1; | |
3321 | ||
3322 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
3323 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 3324 | return 1; |
909cf6ea | 3325 | |
a262aec2 | 3326 | return 0; |
909cf6ea DJ |
3327 | } |
3328 | ||
a262aec2 | 3329 | struct frame_unwind arm_stub_unwind = { |
a154d838 | 3330 | "arm stub", |
a262aec2 | 3331 | NORMAL_FRAME, |
8fbca658 | 3332 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
3333 | arm_stub_this_id, |
3334 | arm_prologue_prev_register, | |
3335 | NULL, | |
3336 | arm_stub_unwind_sniffer | |
3337 | }; | |
3338 | ||
2ae28aa9 YQ |
3339 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
3340 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
3341 | returned. */ | |
3342 | ||
3343 | static struct arm_prologue_cache * | |
3344 | arm_m_exception_cache (struct frame_info *this_frame) | |
3345 | { | |
3346 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
08106042 | 3347 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ef273377 | 3348 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2ae28aa9 | 3349 | struct arm_prologue_cache *cache; |
55ea94da | 3350 | CORE_ADDR lr; |
ef273377 | 3351 | CORE_ADDR sp; |
2ae28aa9 | 3352 | CORE_ADDR unwound_sp; |
ef273377 | 3353 | uint32_t sp_r0_offset = 0; |
2ae28aa9 | 3354 | LONGEST xpsr; |
55ea94da | 3355 | uint32_t exc_return; |
ef273377 | 3356 | bool fnc_return; |
55ea94da | 3357 | uint32_t extended_frame_used; |
ef273377 CL |
3358 | bool secure_stack_used = false; |
3359 | bool default_callee_register_stacking = false; | |
3360 | bool exception_domain_is_secure = false; | |
2ae28aa9 YQ |
3361 | |
3362 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
0824193f | 3363 | arm_cache_init (cache, this_frame); |
2ae28aa9 | 3364 | |
55ea94da FH |
3365 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
3366 | describes which bits in LR that define which stack was used prior | |
3367 | to the exception and if FPU is used (causing extended stack frame). */ | |
3368 | ||
3369 | lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); | |
ef273377 CL |
3370 | sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
3371 | ||
148ca9dd YR |
3372 | /* ARMv7-M Architecture Reference "A2.3.1 Arm core registers" |
3373 | states that LR is set to 0xffffffff on reset. ARMv8-M Architecture | |
3374 | Reference "B3.3 Registers" states that LR is set to 0xffffffff on warm | |
3375 | reset if Main Extension is implemented, otherwise the value is unknown. */ | |
3376 | if (lr == 0xffffffff) | |
3377 | { | |
3378 | /* Terminate any further stack unwinding by referring to self. */ | |
3379 | arm_cache_set_active_sp_value (cache, tdep, sp); | |
3380 | return cache; | |
3381 | } | |
3382 | ||
8c9ae6df | 3383 | fnc_return = (((lr >> 24) & 0xff) == 0xfe); |
ef273377 CL |
3384 | if (tdep->have_sec_ext && fnc_return) |
3385 | { | |
8c9ae6df YR |
3386 | if (!arm_unwind_secure_frames) |
3387 | { | |
3388 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
ef273377 | 3389 | |
8c9ae6df YR |
3390 | /* Terminate any further stack unwinding by referring to self. */ |
3391 | arm_cache_set_active_sp_value (cache, tdep, sp); | |
3392 | return cache; | |
3393 | } | |
3394 | ||
3395 | xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); | |
3396 | if ((xpsr & 0xff) != 0) | |
3397 | /* Handler mode: This is the mode that exceptions are handled in. */ | |
3398 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); | |
ef273377 | 3399 | else |
8c9ae6df YR |
3400 | /* Thread mode: This is the normal mode that programs run in. */ |
3401 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); | |
ef273377 | 3402 | |
8c9ae6df | 3403 | unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); |
55ea94da | 3404 | |
8c9ae6df YR |
3405 | /* Stack layout for a function call from Secure to Non-Secure state |
3406 | (ARMv8-M section B3.16): | |
55ea94da | 3407 | |
8c9ae6df YR |
3408 | SP Offset |
3409 | ||
3410 | +-------------------+ | |
3411 | 0x08 | | | |
3412 | +-------------------+ <-- Original SP | |
3413 | 0x04 | Partial xPSR | | |
3414 | +-------------------+ | |
3415 | 0x00 | Return Address | | |
3416 | +===================+ <-- New SP */ | |
3417 | ||
3418 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 0x00); | |
3419 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 0x00); | |
3420 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 0x04); | |
3421 | ||
3422 | arm_cache_set_active_sp_value (cache, tdep, unwound_sp + 0x08); | |
ef273377 CL |
3423 | |
3424 | return cache; | |
3425 | } | |
3426 | ||
3427 | /* Check EXC_RETURN indicator bits (24-31). */ | |
3428 | exc_return = (((lr >> 24) & 0xff) == 0xff); | |
3429 | if (exc_return) | |
55ea94da | 3430 | { |
ef273377 CL |
3431 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ |
3432 | bool process_stack_used = ((lr & (1 << 2)) != 0); | |
3433 | ||
3434 | if (tdep->have_sec_ext) | |
3435 | { | |
3436 | secure_stack_used = ((lr & (1 << 6)) != 0); | |
3437 | default_callee_register_stacking = ((lr & (1 << 5)) != 0); | |
3438 | exception_domain_is_secure = ((lr & (1 << 0)) == 0); | |
3439 | ||
3440 | /* Unwinding from non-secure to secure can trip security | |
3441 | measures. In order to avoid the debugger being | |
3442 | intrusive, rely on the user to configure the requested | |
3443 | mode. */ | |
3444 | if (secure_stack_used && !exception_domain_is_secure | |
3445 | && !arm_unwind_secure_frames) | |
3446 | { | |
3447 | warning (_("Non-secure to secure stack unwinding disabled.")); | |
3448 | ||
3449 | /* Terminate any further stack unwinding by referring to self. */ | |
3450 | arm_cache_set_active_sp_value (cache, tdep, sp); | |
3451 | return cache; | |
3452 | } | |
3453 | ||
3454 | if (process_stack_used) | |
3455 | { | |
3456 | if (secure_stack_used) | |
3457 | /* Secure thread (process) stack used, use PSP_S as SP. */ | |
3458 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); | |
3459 | else | |
3460 | /* Non-secure thread (process) stack used, use PSP_NS as SP. */ | |
3461 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_ns_regnum); | |
3462 | } | |
3463 | else | |
3464 | { | |
3465 | if (secure_stack_used) | |
3466 | /* Secure main stack used, use MSP_S as SP. */ | |
3467 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); | |
3468 | else | |
3469 | /* Non-secure main stack used, use MSP_NS as SP. */ | |
3470 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_ns_regnum); | |
3471 | } | |
3472 | } | |
3473 | else | |
3474 | { | |
3475 | if (process_stack_used) | |
3476 | /* Thread (process) stack used, use PSP as SP. */ | |
3477 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_regnum); | |
3478 | else | |
3479 | /* Main stack used, use MSP as SP. */ | |
3480 | arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_regnum); | |
3481 | } | |
55ea94da | 3482 | } |
ef273377 CL |
3483 | |
3484 | /* Fetch the SP to use for this frame. */ | |
3485 | unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); | |
3486 | ||
2d9cf99d YR |
3487 | /* Exception entry context stacking are described in ARMv8-M (section B3.19) |
3488 | and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference Manuals. | |
3489 | ||
3490 | The following figure shows the structure of the stack frame when Security | |
3491 | and Floating-point extensions are present. | |
3492 | ||
3493 | SP Offsets | |
3494 | Without With | |
3495 | Callee Regs Callee Regs | |
3496 | (Secure -> Non-Secure) | |
3497 | +-------------------+ | |
3498 | 0xA8 | | 0xD0 | |
3499 | +===================+ --+ <-- Original SP | |
3500 | 0xA4 | S31 | 0xCC | | |
3501 | +-------------------+ | | |
3502 | ... | Additional FP context | |
3503 | +-------------------+ | | |
3504 | 0x68 | S16 | 0x90 | | |
3505 | +===================+ --+ | |
3506 | 0x64 | Reserved | 0x8C | | |
3507 | +-------------------+ | | |
3508 | 0x60 | FPSCR | 0x88 | | |
3509 | +-------------------+ | | |
3510 | 0x5C | S15 | 0x84 | FP context | |
3511 | +-------------------+ | | |
3512 | ... | | |
3513 | +-------------------+ | | |
3514 | 0x20 | S0 | 0x48 | | |
3515 | +===================+ --+ | |
3516 | 0x1C | xPSR | 0x44 | | |
3517 | +-------------------+ | | |
3518 | 0x18 | Return address | 0x40 | | |
3519 | +-------------------+ | | |
3520 | 0x14 | LR(R14) | 0x3C | | |
3521 | +-------------------+ | | |
3522 | 0x10 | R12 | 0x38 | State context | |
3523 | +-------------------+ | | |
3524 | 0x0C | R3 | 0x34 | | |
3525 | +-------------------+ | | |
3526 | ... | | |
3527 | +-------------------+ | | |
3528 | 0x00 | R0 | 0x28 | | |
3529 | +===================+ --+ | |
3530 | | R11 | 0x24 | | |
3531 | +-------------------+ | | |
3532 | ... | | |
3533 | +-------------------+ | Additional state context | |
3534 | | R4 | 0x08 | when transitioning from | |
3535 | +-------------------+ | Secure to Non-Secure | |
3536 | | Reserved | 0x04 | | |
3537 | +-------------------+ | | |
3538 | | Magic signature | 0x00 | | |
3539 | +===================+ --+ <-- New SP */ | |
3540 | ||
ef273377 CL |
3541 | /* With the Security extension, the hardware saves R4..R11 too. */ |
3542 | if (exc_return && tdep->have_sec_ext && secure_stack_used | |
3543 | && (!default_callee_register_stacking || exception_domain_is_secure)) | |
3544 | { | |
3545 | /* Read R4..R11 from the integer callee registers. */ | |
3546 | cache->saved_regs[4].set_addr (unwound_sp + 0x08); | |
3547 | cache->saved_regs[5].set_addr (unwound_sp + 0x0C); | |
3548 | cache->saved_regs[6].set_addr (unwound_sp + 0x10); | |
3549 | cache->saved_regs[7].set_addr (unwound_sp + 0x14); | |
3550 | cache->saved_regs[8].set_addr (unwound_sp + 0x18); | |
3551 | cache->saved_regs[9].set_addr (unwound_sp + 0x1C); | |
3552 | cache->saved_regs[10].set_addr (unwound_sp + 0x20); | |
3553 | cache->saved_regs[11].set_addr (unwound_sp + 0x24); | |
3554 | sp_r0_offset = 0x28; | |
55ea94da | 3555 | } |
2ae28aa9 YQ |
3556 | |
3557 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3558 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3559 | "B1.5.6 Exception entry behavior" in | |
3560 | "ARMv7-M Architecture Reference Manual". */ | |
ef273377 | 3561 | cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); |
1d2eeb66 YR |
3562 | cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); |
3563 | cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); | |
3564 | cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); | |
3565 | cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x10); | |
3566 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x14); | |
3567 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x18); | |
3568 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x1C); | |
2ae28aa9 | 3569 | |
55ea94da FH |
3570 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) |
3571 | type used. */ | |
3572 | extended_frame_used = ((lr & (1 << 4)) == 0); | |
3573 | if (exc_return && extended_frame_used) | |
3574 | { | |
3575 | int i; | |
3576 | int fpu_regs_stack_offset; | |
69b46464 YR |
3577 | ULONGEST fpccr; |
3578 | ||
3579 | /* Read FPCCR register. */ | |
3580 | gdb_assert (safe_read_memory_unsigned_integer (FPCCR, | |
3581 | ARM_INT_REGISTER_SIZE, | |
3582 | byte_order, &fpccr)); | |
3583 | bool fpccr_ts = bit (fpccr,26); | |
55ea94da FH |
3584 | |
3585 | /* This code does not take into account the lazy stacking, see "Lazy | |
dda83cd7 SM |
3586 | context save of FP state", in B1.5.7, also ARM AN298, supported |
3587 | by Cortex-M4F architecture. | |
3588 | To fully handle this the FPCCR register (Floating-point Context | |
3589 | Control Register) needs to be read out and the bits ASPEN and LSPEN | |
3590 | could be checked to setup correct lazy stacked FP registers. | |
3591 | This register is located at address 0xE000EF34. */ | |
55ea94da FH |
3592 | |
3593 | /* Extended stack frame type used. */ | |
ef273377 | 3594 | fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x20; |
39fc7ff6 | 3595 | for (i = 0; i < 8; i++) |
dda83cd7 | 3596 | { |
098caef4 | 3597 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); |
39fc7ff6 | 3598 | fpu_regs_stack_offset += 8; |
dda83cd7 | 3599 | } |
ef273377 CL |
3600 | cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); |
3601 | fpu_regs_stack_offset += 4; | |
55ea94da | 3602 | |
69b46464 | 3603 | if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts) |
ef273377 CL |
3604 | { |
3605 | /* Handle floating-point callee saved registers. */ | |
2d9cf99d | 3606 | fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; |
39fc7ff6 | 3607 | for (i = 8; i < 16; i++) |
ef273377 CL |
3608 | { |
3609 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); | |
39fc7ff6 | 3610 | fpu_regs_stack_offset += 8; |
ef273377 CL |
3611 | } |
3612 | ||
2d9cf99d YR |
3613 | arm_cache_set_active_sp_value (cache, tdep, |
3614 | unwound_sp + sp_r0_offset + 0xA8); | |
ef273377 CL |
3615 | } |
3616 | else | |
3617 | { | |
3618 | /* Offset 0x64 is reserved. */ | |
2d9cf99d YR |
3619 | arm_cache_set_active_sp_value (cache, tdep, |
3620 | unwound_sp + sp_r0_offset + 0x68); | |
ef273377 | 3621 | } |
55ea94da FH |
3622 | } |
3623 | else | |
3624 | { | |
3625 | /* Standard stack frame type used. */ | |
2d9cf99d YR |
3626 | arm_cache_set_active_sp_value (cache, tdep, |
3627 | unwound_sp + sp_r0_offset + 0x20); | |
55ea94da FH |
3628 | } |
3629 | ||
2ae28aa9 YQ |
3630 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3631 | aligner between the top of the 32-byte stack frame and the | |
3632 | previous context's stack pointer. */ | |
1d2eeb66 YR |
3633 | if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 0x1C, 4, |
3634 | byte_order, &xpsr) | |
2ae28aa9 | 3635 | && (xpsr & (1 << 9)) != 0) |
ae7e2f45 CL |
3636 | arm_cache_set_active_sp_value (cache, tdep, |
3637 | arm_cache_get_prev_sp_value (cache, tdep) + 4); | |
2ae28aa9 YQ |
3638 | |
3639 | return cache; | |
3640 | } | |
3641 | ||
3642 | /* Implementation of function hook 'this_id' in | |
3643 | 'struct frame_uwnind'. */ | |
3644 | ||
3645 | static void | |
3646 | arm_m_exception_this_id (struct frame_info *this_frame, | |
3647 | void **this_cache, | |
3648 | struct frame_id *this_id) | |
3649 | { | |
3650 | struct arm_prologue_cache *cache; | |
3651 | ||
3652 | if (*this_cache == NULL) | |
3653 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3654 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3655 | |
3656 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
ae7e2f45 | 3657 | arm_gdbarch_tdep *tdep |
08106042 | 3658 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3659 | *this_id = frame_id_build (arm_cache_get_prev_sp_value (cache, tdep), |
2ae28aa9 YQ |
3660 | get_frame_pc (this_frame)); |
3661 | } | |
3662 | ||
3663 | /* Implementation of function hook 'prev_register' in | |
3664 | 'struct frame_uwnind'. */ | |
3665 | ||
3666 | static struct value * | |
3667 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
3668 | void **this_cache, | |
3669 | int prev_regnum) | |
3670 | { | |
2ae28aa9 | 3671 | struct arm_prologue_cache *cache; |
ef273377 | 3672 | CORE_ADDR sp_value; |
2ae28aa9 YQ |
3673 | |
3674 | if (*this_cache == NULL) | |
3675 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3676 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3677 | |
3678 | /* The value was already reconstructed into PREV_SP. */ | |
ae7e2f45 | 3679 | arm_gdbarch_tdep *tdep |
08106042 | 3680 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
2ae28aa9 YQ |
3681 | if (prev_regnum == ARM_SP_REGNUM) |
3682 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
ae7e2f45 | 3683 | arm_cache_get_prev_sp_value (cache, tdep)); |
2ae28aa9 | 3684 | |
8c9ae6df YR |
3685 | /* If we are asked to unwind the PC, strip the saved T bit. */ |
3686 | if (prev_regnum == ARM_PC_REGNUM) | |
3687 | { | |
3688 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3689 | cache->saved_regs, | |
3690 | prev_regnum); | |
3691 | CORE_ADDR pc = value_as_address (value); | |
3692 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3693 | UNMAKE_THUMB_ADDR (pc)); | |
3694 | } | |
3695 | ||
ef273377 CL |
3696 | /* The value might be one of the alternative SP, if so, use the |
3697 | value already constructed. */ | |
d65edaa0 | 3698 | if (arm_is_alternative_sp_register (tdep, prev_regnum)) |
ef273377 CL |
3699 | { |
3700 | sp_value = arm_cache_get_sp_register (cache, tdep, prev_regnum); | |
3701 | return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); | |
3702 | } | |
3703 | ||
8c9ae6df YR |
3704 | /* If we are asked to unwind the xPSR, set T bit if PC is in thumb mode. |
3705 | LR register is unreliable as it contains FNC_RETURN or EXC_RETURN | |
3706 | pattern. */ | |
3707 | if (prev_regnum == ARM_PS_REGNUM) | |
3708 | { | |
3709 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3710 | struct value *value = trad_frame_get_prev_register (this_frame, | |
3711 | cache->saved_regs, | |
3712 | ARM_PC_REGNUM); | |
3713 | CORE_ADDR pc = value_as_address (value); | |
3714 | value = trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3715 | ARM_PS_REGNUM); | |
3716 | ULONGEST xpsr = value_as_long (value); | |
3717 | ||
3718 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
3719 | xpsr = reconstruct_t_bit (gdbarch, pc, xpsr); | |
3720 | return frame_unwind_got_constant (this_frame, ARM_PS_REGNUM, xpsr); | |
3721 | } | |
3722 | ||
2ae28aa9 YQ |
3723 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
3724 | prev_regnum); | |
3725 | } | |
3726 | ||
3727 | /* Implementation of function hook 'sniffer' in | |
3728 | 'struct frame_uwnind'. */ | |
3729 | ||
3730 | static int | |
3731 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
3732 | struct frame_info *this_frame, | |
3733 | void **this_prologue_cache) | |
3734 | { | |
ef273377 | 3735 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2ae28aa9 YQ |
3736 | CORE_ADDR this_pc = get_frame_pc (this_frame); |
3737 | ||
3738 | /* No need to check is_m; this sniffer is only registered for | |
3739 | M-profile architectures. */ | |
3740 | ||
ca90e760 | 3741 | /* Check if exception frame returns to a magic PC value. */ |
ef273377 | 3742 | return arm_m_addr_is_magic (gdbarch, this_pc); |
2ae28aa9 YQ |
3743 | } |
3744 | ||
3745 | /* Frame unwinder for M-profile exceptions. */ | |
3746 | ||
3747 | struct frame_unwind arm_m_exception_unwind = | |
3748 | { | |
a154d838 | 3749 | "arm m exception", |
2ae28aa9 YQ |
3750 | SIGTRAMP_FRAME, |
3751 | default_frame_unwind_stop_reason, | |
3752 | arm_m_exception_this_id, | |
3753 | arm_m_exception_prev_register, | |
3754 | NULL, | |
3755 | arm_m_exception_unwind_sniffer | |
3756 | }; | |
3757 | ||
24de872b | 3758 | static CORE_ADDR |
a262aec2 | 3759 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
3760 | { |
3761 | struct arm_prologue_cache *cache; | |
3762 | ||
eb5492fa | 3763 | if (*this_cache == NULL) |
a262aec2 | 3764 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3765 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3766 | |
ae7e2f45 | 3767 | arm_gdbarch_tdep *tdep |
08106042 | 3768 | = gdbarch_tdep<arm_gdbarch_tdep> (get_frame_arch (this_frame)); |
ae7e2f45 | 3769 | return arm_cache_get_prev_sp_value (cache, tdep) - cache->framesize; |
24de872b DJ |
3770 | } |
3771 | ||
eb5492fa DJ |
3772 | struct frame_base arm_normal_base = { |
3773 | &arm_prologue_unwind, | |
3774 | arm_normal_frame_base, | |
3775 | arm_normal_frame_base, | |
3776 | arm_normal_frame_base | |
3777 | }; | |
3778 | ||
b39cc962 DJ |
3779 | static struct value * |
3780 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
3781 | int regnum) | |
3782 | { | |
24568a2c | 3783 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
08106042 | 3784 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
8c9ae6df YR |
3785 | CORE_ADDR lr; |
3786 | ULONGEST cpsr; | |
b39cc962 DJ |
3787 | |
3788 | switch (regnum) | |
3789 | { | |
3790 | case ARM_PC_REGNUM: | |
3791 | /* The PC is normally copied from the return column, which | |
3792 | describes saves of LR. However, that version may have an | |
3793 | extra bit set to indicate Thumb state. The bit is not | |
3794 | part of the PC. */ | |
a01567f4 LM |
3795 | |
3796 | /* Record in the frame whether the return address was signed. */ | |
3797 | if (tdep->have_pacbti) | |
3798 | { | |
3799 | CORE_ADDR ra_auth_code | |
3800 | = frame_unwind_register_unsigned (this_frame, | |
3801 | tdep->pacbti_pseudo_base); | |
3802 | ||
3803 | if (ra_auth_code != 0) | |
3804 | set_frame_previous_pc_masked (this_frame); | |
3805 | } | |
3806 | ||
b39cc962 DJ |
3807 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3808 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3809 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
3810 | |
3811 | case ARM_PS_REGNUM: | |
3812 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 3813 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 | 3814 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
8c9ae6df | 3815 | cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); |
ca38c58e | 3816 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3817 | |
3818 | default: | |
3819 | internal_error (__FILE__, __LINE__, | |
3820 | _("Unexpected register %d"), regnum); | |
3821 | } | |
3822 | } | |
3823 | ||
c9cf6e20 | 3824 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3825 | |
3826 | static int | |
c9cf6e20 | 3827 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3828 | { |
3829 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3830 | unsigned int insn, insn2; | |
3831 | int found_return = 0, found_stack_adjust = 0; | |
3832 | CORE_ADDR func_start, func_end; | |
3833 | CORE_ADDR scan_pc; | |
3834 | gdb_byte buf[4]; | |
3835 | ||
3836 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3837 | return 0; | |
3838 | ||
3839 | /* The epilogue is a sequence of instructions along the following lines: | |
3840 | ||
3841 | - add stack frame size to SP or FP | |
3842 | - [if frame pointer used] restore SP from FP | |
3843 | - restore registers from SP [may include PC] | |
3844 | - a return-type instruction [if PC wasn't already restored] | |
3845 | ||
3846 | In a first pass, we scan forward from the current PC and verify the | |
3847 | instructions we find as compatible with this sequence, ending in a | |
3848 | return instruction. | |
3849 | ||
3850 | However, this is not sufficient to distinguish indirect function calls | |
3851 | within a function from indirect tail calls in the epilogue in some cases. | |
3852 | Therefore, if we didn't already find any SP-changing instruction during | |
3853 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3854 | are in the epilogue. */ | |
3855 | ||
3856 | scan_pc = pc; | |
3857 | while (scan_pc < func_end && !found_return) | |
3858 | { | |
3859 | if (target_read_memory (scan_pc, buf, 2)) | |
3860 | break; | |
3861 | ||
3862 | scan_pc += 2; | |
3863 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3864 | ||
3865 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3866 | found_return = 1; | |
3867 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3868 | found_return = 1; | |
540314bd | 3869 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3870 | { |
b7576e5c | 3871 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3872 | found_return = 1; |
3873 | } | |
db24da6d | 3874 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3875 | { |
3876 | if (target_read_memory (scan_pc, buf, 2)) | |
3877 | break; | |
3878 | ||
3879 | scan_pc += 2; | |
3880 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3881 | ||
3882 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3883 | { | |
4024ca99 UW |
3884 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3885 | found_return = 1; | |
3886 | } | |
3887 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3888 | && (insn2 & 0x0fff) == 0x0b04) | |
3889 | { | |
4024ca99 UW |
3890 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3891 | found_return = 1; | |
3892 | } | |
3893 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3894 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3895 | ; |
4024ca99 UW |
3896 | else |
3897 | break; | |
3898 | } | |
3899 | else | |
3900 | break; | |
3901 | } | |
3902 | ||
3903 | if (!found_return) | |
3904 | return 0; | |
3905 | ||
3906 | /* Since any instruction in the epilogue sequence, with the possible | |
3907 | exception of return itself, updates the stack pointer, we need to | |
3908 | scan backwards for at most one instruction. Try either a 16-bit or | |
3909 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3910 | too much about false positives. */ |
4024ca99 | 3911 | |
6b65d1b6 YQ |
3912 | if (pc - 4 < func_start) |
3913 | return 0; | |
3914 | if (target_read_memory (pc - 4, buf, 4)) | |
3915 | return 0; | |
4024ca99 | 3916 | |
6b65d1b6 YQ |
3917 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3918 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3919 | ||
3920 | if (thumb_instruction_restores_sp (insn2)) | |
3921 | found_stack_adjust = 1; | |
3922 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3923 | found_stack_adjust = 1; | |
3924 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3925 | && (insn2 & 0x0fff) == 0x0b04) | |
3926 | found_stack_adjust = 1; | |
3927 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3928 | && (insn2 & 0x0e00) == 0x0a00) | |
3929 | found_stack_adjust = 1; | |
4024ca99 UW |
3930 | |
3931 | return found_stack_adjust; | |
3932 | } | |
3933 | ||
4024ca99 | 3934 | static int |
c58b006a | 3935 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3936 | { |
3937 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3938 | unsigned int insn; | |
f303bc3e | 3939 | int found_return; |
4024ca99 UW |
3940 | CORE_ADDR func_start, func_end; |
3941 | ||
4024ca99 UW |
3942 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
3943 | return 0; | |
3944 | ||
3945 | /* We are in the epilogue if the previous instruction was a stack | |
3946 | adjustment and the next instruction is a possible return (bx, mov | |
3947 | pc, or pop). We could have to scan backwards to find the stack | |
3948 | adjustment, or forwards to find the return, but this is a decent | |
3949 | approximation. First scan forwards. */ | |
3950 | ||
3951 | found_return = 0; | |
3952 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3953 | if (bits (insn, 28, 31) != INST_NV) | |
3954 | { | |
3955 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3956 | /* BX. */ | |
3957 | found_return = 1; | |
3958 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3959 | /* MOV PC. */ | |
3960 | found_return = 1; | |
3961 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3962 | && (insn & 0x0000c000) != 0) | |
3963 | /* POP (LDMIA), including PC or LR. */ | |
3964 | found_return = 1; | |
3965 | } | |
3966 | ||
3967 | if (!found_return) | |
3968 | return 0; | |
3969 | ||
3970 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3971 | false positives from mode changes. */ | |
3972 | ||
3973 | if (pc < func_start + 4) | |
3974 | return 0; | |
3975 | ||
3976 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3977 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3978 | return 1; |
3979 | ||
3980 | return 0; | |
3981 | } | |
3982 | ||
c58b006a YQ |
3983 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3984 | ||
3985 | static int | |
3986 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3987 | { | |
3988 | if (arm_pc_is_thumb (gdbarch, pc)) | |
3989 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3990 | else | |
3991 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3992 | } | |
4024ca99 | 3993 | |
2dd604e7 RE |
3994 | /* When arguments must be pushed onto the stack, they go on in reverse |
3995 | order. The code below implements a FILO (stack) to do this. */ | |
3996 | ||
0fecb1a7 | 3997 | struct arm_stack_item |
2dd604e7 RE |
3998 | { |
3999 | int len; | |
0fecb1a7 | 4000 | struct arm_stack_item *prev; |
7c543f7b | 4001 | gdb_byte *data; |
2dd604e7 RE |
4002 | }; |
4003 | ||
0fecb1a7 TT |
4004 | static struct arm_stack_item * |
4005 | push_stack_item (struct arm_stack_item *prev, const gdb_byte *contents, | |
4006 | int len) | |
2dd604e7 | 4007 | { |
0fecb1a7 TT |
4008 | struct arm_stack_item *si; |
4009 | si = XNEW (struct arm_stack_item); | |
7c543f7b | 4010 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
4011 | si->len = len; |
4012 | si->prev = prev; | |
4013 | memcpy (si->data, contents, len); | |
4014 | return si; | |
4015 | } | |
4016 | ||
0fecb1a7 TT |
4017 | static struct arm_stack_item * |
4018 | pop_stack_item (struct arm_stack_item *si) | |
2dd604e7 | 4019 | { |
0fecb1a7 | 4020 | struct arm_stack_item *dead = si; |
2dd604e7 RE |
4021 | si = si->prev; |
4022 | xfree (dead->data); | |
4023 | xfree (dead); | |
4024 | return si; | |
4025 | } | |
4026 | ||
030197b4 AB |
4027 | /* Implement the gdbarch type alignment method, overrides the generic |
4028 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 4029 | |
030197b4 AB |
4030 | static ULONGEST |
4031 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 4032 | { |
2af48f68 | 4033 | t = check_typedef (t); |
bd63c870 | 4034 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 4035 | { |
030197b4 AB |
4036 | /* Use the natural alignment for vector types (the same for |
4037 | scalar type), but the maximum alignment is 64-bit. */ | |
4038 | if (TYPE_LENGTH (t) > 8) | |
4039 | return 8; | |
c4312b19 | 4040 | else |
030197b4 | 4041 | return TYPE_LENGTH (t); |
2af48f68 | 4042 | } |
030197b4 AB |
4043 | |
4044 | /* Allow the common code to calculate the alignment. */ | |
4045 | return 0; | |
2af48f68 PB |
4046 | } |
4047 | ||
90445bd3 DJ |
4048 | /* Possible base types for a candidate for passing and returning in |
4049 | VFP registers. */ | |
4050 | ||
4051 | enum arm_vfp_cprc_base_type | |
4052 | { | |
4053 | VFP_CPRC_UNKNOWN, | |
4054 | VFP_CPRC_SINGLE, | |
4055 | VFP_CPRC_DOUBLE, | |
4056 | VFP_CPRC_VEC64, | |
4057 | VFP_CPRC_VEC128 | |
4058 | }; | |
4059 | ||
4060 | /* The length of one element of base type B. */ | |
4061 | ||
4062 | static unsigned | |
4063 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
4064 | { | |
4065 | switch (b) | |
4066 | { | |
4067 | case VFP_CPRC_SINGLE: | |
4068 | return 4; | |
4069 | case VFP_CPRC_DOUBLE: | |
4070 | return 8; | |
4071 | case VFP_CPRC_VEC64: | |
4072 | return 8; | |
4073 | case VFP_CPRC_VEC128: | |
4074 | return 16; | |
4075 | default: | |
4076 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
4077 | (int) b); | |
4078 | } | |
4079 | } | |
4080 | ||
4081 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
4082 | for passing base type B. */ | |
4083 | ||
4084 | static int | |
4085 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
4086 | { | |
4087 | switch (b) | |
4088 | { | |
4089 | case VFP_CPRC_SINGLE: | |
4090 | return 's'; | |
4091 | case VFP_CPRC_DOUBLE: | |
4092 | return 'd'; | |
4093 | case VFP_CPRC_VEC64: | |
4094 | return 'd'; | |
4095 | case VFP_CPRC_VEC128: | |
4096 | return 'q'; | |
4097 | default: | |
4098 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
4099 | (int) b); | |
4100 | } | |
4101 | } | |
4102 | ||
4103 | /* Determine whether T may be part of a candidate for passing and | |
4104 | returning in VFP registers, ignoring the limit on the total number | |
4105 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
4106 | classification of the first valid component found; if it is not | |
4107 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
4108 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
4109 | for passing and returning in VFP registers, a type differently | |
4110 | classified from *BASE_TYPE, or two types differently classified | |
4111 | from each other, return -1, otherwise return the total number of | |
4112 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
4113 | array). Vector types are not currently supported, matching the |
4114 | generic AAPCS support. */ | |
90445bd3 DJ |
4115 | |
4116 | static int | |
4117 | arm_vfp_cprc_sub_candidate (struct type *t, | |
4118 | enum arm_vfp_cprc_base_type *base_type) | |
4119 | { | |
4120 | t = check_typedef (t); | |
78134374 | 4121 | switch (t->code ()) |
90445bd3 DJ |
4122 | { |
4123 | case TYPE_CODE_FLT: | |
4124 | switch (TYPE_LENGTH (t)) | |
4125 | { | |
4126 | case 4: | |
4127 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4128 | *base_type = VFP_CPRC_SINGLE; | |
4129 | else if (*base_type != VFP_CPRC_SINGLE) | |
4130 | return -1; | |
4131 | return 1; | |
4132 | ||
4133 | case 8: | |
4134 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4135 | *base_type = VFP_CPRC_DOUBLE; | |
4136 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4137 | return -1; | |
4138 | return 1; | |
4139 | ||
4140 | default: | |
4141 | return -1; | |
4142 | } | |
4143 | break; | |
4144 | ||
817e0957 YQ |
4145 | case TYPE_CODE_COMPLEX: |
4146 | /* Arguments of complex T where T is one of the types float or | |
4147 | double get treated as if they are implemented as: | |
4148 | ||
4149 | struct complexT | |
4150 | { | |
4151 | T real; | |
4152 | T imag; | |
5f52445b YQ |
4153 | }; |
4154 | ||
4155 | */ | |
817e0957 YQ |
4156 | switch (TYPE_LENGTH (t)) |
4157 | { | |
4158 | case 8: | |
4159 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4160 | *base_type = VFP_CPRC_SINGLE; | |
4161 | else if (*base_type != VFP_CPRC_SINGLE) | |
4162 | return -1; | |
4163 | return 2; | |
4164 | ||
4165 | case 16: | |
4166 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4167 | *base_type = VFP_CPRC_DOUBLE; | |
4168 | else if (*base_type != VFP_CPRC_DOUBLE) | |
4169 | return -1; | |
4170 | return 2; | |
4171 | ||
4172 | default: | |
4173 | return -1; | |
4174 | } | |
4175 | break; | |
4176 | ||
90445bd3 DJ |
4177 | case TYPE_CODE_ARRAY: |
4178 | { | |
bd63c870 | 4179 | if (t->is_vector ()) |
90445bd3 | 4180 | { |
c4312b19 YQ |
4181 | /* A 64-bit or 128-bit containerized vector type are VFP |
4182 | CPRCs. */ | |
4183 | switch (TYPE_LENGTH (t)) | |
4184 | { | |
4185 | case 8: | |
4186 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4187 | *base_type = VFP_CPRC_VEC64; | |
4188 | return 1; | |
4189 | case 16: | |
4190 | if (*base_type == VFP_CPRC_UNKNOWN) | |
4191 | *base_type = VFP_CPRC_VEC128; | |
4192 | return 1; | |
4193 | default: | |
4194 | return -1; | |
4195 | } | |
4196 | } | |
4197 | else | |
4198 | { | |
4199 | int count; | |
4200 | unsigned unitlen; | |
4201 | ||
4202 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), | |
4203 | base_type); | |
4204 | if (count == -1) | |
4205 | return -1; | |
4206 | if (TYPE_LENGTH (t) == 0) | |
4207 | { | |
4208 | gdb_assert (count == 0); | |
4209 | return 0; | |
4210 | } | |
4211 | else if (count == 0) | |
4212 | return -1; | |
4213 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
4214 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
4215 | return TYPE_LENGTH (t) / unitlen; | |
90445bd3 | 4216 | } |
90445bd3 DJ |
4217 | } |
4218 | break; | |
4219 | ||
4220 | case TYPE_CODE_STRUCT: | |
4221 | { | |
4222 | int count = 0; | |
4223 | unsigned unitlen; | |
4224 | int i; | |
1f704f76 | 4225 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4226 | { |
1040b979 YQ |
4227 | int sub_count = 0; |
4228 | ||
ceacbf6e | 4229 | if (!field_is_static (&t->field (i))) |
940da03e | 4230 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 4231 | base_type); |
90445bd3 DJ |
4232 | if (sub_count == -1) |
4233 | return -1; | |
4234 | count += sub_count; | |
4235 | } | |
4236 | if (TYPE_LENGTH (t) == 0) | |
4237 | { | |
4238 | gdb_assert (count == 0); | |
4239 | return 0; | |
4240 | } | |
4241 | else if (count == 0) | |
4242 | return -1; | |
4243 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
4244 | if (TYPE_LENGTH (t) != unitlen * count) | |
4245 | return -1; | |
4246 | return count; | |
4247 | } | |
4248 | ||
4249 | case TYPE_CODE_UNION: | |
4250 | { | |
4251 | int count = 0; | |
4252 | unsigned unitlen; | |
4253 | int i; | |
1f704f76 | 4254 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 4255 | { |
940da03e | 4256 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
4257 | base_type); |
4258 | if (sub_count == -1) | |
4259 | return -1; | |
4260 | count = (count > sub_count ? count : sub_count); | |
4261 | } | |
4262 | if (TYPE_LENGTH (t) == 0) | |
4263 | { | |
4264 | gdb_assert (count == 0); | |
4265 | return 0; | |
4266 | } | |
4267 | else if (count == 0) | |
4268 | return -1; | |
4269 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
4270 | if (TYPE_LENGTH (t) != unitlen * count) | |
4271 | return -1; | |
4272 | return count; | |
4273 | } | |
4274 | ||
4275 | default: | |
4276 | break; | |
4277 | } | |
4278 | ||
4279 | return -1; | |
4280 | } | |
4281 | ||
4282 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
4283 | if passed to or returned from a non-variadic function with the VFP | |
4284 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
4285 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
4286 | elements of that base type before returning. */ | |
4287 | ||
4288 | static int | |
4289 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
4290 | int *count) | |
4291 | { | |
4292 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
4293 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
4294 | if (c <= 0 || c > 4) | |
4295 | return 0; | |
4296 | *base_type = b; | |
4297 | *count = c; | |
4298 | return 1; | |
4299 | } | |
4300 | ||
4301 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
4302 | returning values from a function of type FUNC_TYPE, 0 | |
4303 | otherwise. */ | |
4304 | ||
4305 | static int | |
4306 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
4307 | { | |
08106042 | 4308 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 4309 | |
90445bd3 DJ |
4310 | /* Variadic functions always use the base ABI. Assume that functions |
4311 | without debug info are not variadic. */ | |
a409645d | 4312 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 | 4313 | return 0; |
345bd07c | 4314 | |
90445bd3 DJ |
4315 | /* The VFP ABI is only supported as a variant of AAPCS. */ |
4316 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
4317 | return 0; | |
345bd07c SM |
4318 | |
4319 | return tdep->fp_model == ARM_FLOAT_VFP; | |
90445bd3 DJ |
4320 | } |
4321 | ||
4322 | /* We currently only support passing parameters in integer registers, which | |
4323 | conforms with GCC's default model, and VFP argument passing following | |
4324 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
4325 | we should probably support some of them based on the selected ABI. */ |
4326 | ||
4327 | static CORE_ADDR | |
7d9b040b | 4328 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 4329 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
4330 | struct value **args, CORE_ADDR sp, |
4331 | function_call_return_method return_method, | |
6a65450a | 4332 | CORE_ADDR struct_addr) |
2dd604e7 | 4333 | { |
e17a4113 | 4334 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
4335 | int argnum; |
4336 | int argreg; | |
4337 | int nstack; | |
0fecb1a7 | 4338 | struct arm_stack_item *si = NULL; |
90445bd3 DJ |
4339 | int use_vfp_abi; |
4340 | struct type *ftype; | |
4341 | unsigned vfp_regs_free = (1 << 16) - 1; | |
08106042 | 4342 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
90445bd3 DJ |
4343 | |
4344 | /* Determine the type of this function and whether the VFP ABI | |
4345 | applies. */ | |
4346 | ftype = check_typedef (value_type (function)); | |
78134374 | 4347 | if (ftype->code () == TYPE_CODE_PTR) |
90445bd3 DJ |
4348 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
4349 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 4350 | |
6a65450a AC |
4351 | /* Set the return address. For the ARM, the return breakpoint is |
4352 | always at BP_ADDR. */ | |
9779414d | 4353 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 4354 | bp_addr |= 1; |
6a65450a | 4355 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
4356 | |
4357 | /* Walk through the list of args and determine how large a temporary | |
4358 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 4359 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
4360 | nstack = 0; |
4361 | ||
4362 | argreg = ARM_A1_REGNUM; | |
4363 | nstack = 0; | |
4364 | ||
2dd604e7 RE |
4365 | /* The struct_return pointer occupies the first parameter |
4366 | passing register. */ | |
cf84fa6b | 4367 | if (return_method == return_method_struct) |
2dd604e7 | 4368 | { |
7cb6d92a SM |
4369 | arm_debug_printf ("struct return in %s = %s", |
4370 | gdbarch_register_name (gdbarch, argreg), | |
4371 | paddress (gdbarch, struct_addr)); | |
4372 | ||
2dd604e7 RE |
4373 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
4374 | argreg++; | |
4375 | } | |
4376 | ||
4377 | for (argnum = 0; argnum < nargs; argnum++) | |
4378 | { | |
4379 | int len; | |
4380 | struct type *arg_type; | |
4381 | struct type *target_type; | |
4382 | enum type_code typecode; | |
8c6363cf | 4383 | const bfd_byte *val; |
2af48f68 | 4384 | int align; |
90445bd3 DJ |
4385 | enum arm_vfp_cprc_base_type vfp_base_type; |
4386 | int vfp_base_count; | |
4387 | int may_use_core_reg = 1; | |
2dd604e7 | 4388 | |
df407dfe | 4389 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
4390 | len = TYPE_LENGTH (arg_type); |
4391 | target_type = TYPE_TARGET_TYPE (arg_type); | |
78134374 | 4392 | typecode = arg_type->code (); |
50888e42 | 4393 | val = value_contents (args[argnum]).data (); |
2dd604e7 | 4394 | |
030197b4 | 4395 | align = type_align (arg_type); |
2af48f68 | 4396 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
4397 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
4398 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 | 4399 | /* Different ABIs have different maximum alignments. */ |
345bd07c | 4400 | if (tdep->arm_abi == ARM_ABI_APCS) |
2af48f68 PB |
4401 | { |
4402 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 4403 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
4404 | } |
4405 | else | |
4406 | { | |
4407 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
4408 | if (align > ARM_INT_REGISTER_SIZE * 2) |
4409 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
4410 | } |
4411 | ||
90445bd3 DJ |
4412 | if (use_vfp_abi |
4413 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
4414 | &vfp_base_count)) | |
4415 | { | |
4416 | int regno; | |
4417 | int unit_length; | |
4418 | int shift; | |
4419 | unsigned mask; | |
4420 | ||
4421 | /* Because this is a CPRC it cannot go in a core register or | |
4422 | cause a core register to be skipped for alignment. | |
4423 | Either it goes in VFP registers and the rest of this loop | |
4424 | iteration is skipped for this argument, or it goes on the | |
4425 | stack (and the stack alignment code is correct for this | |
4426 | case). */ | |
4427 | may_use_core_reg = 0; | |
4428 | ||
4429 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
4430 | shift = unit_length / 4; | |
4431 | mask = (1 << (shift * vfp_base_count)) - 1; | |
4432 | for (regno = 0; regno < 16; regno += shift) | |
4433 | if (((vfp_regs_free >> regno) & mask) == mask) | |
4434 | break; | |
4435 | ||
4436 | if (regno < 16) | |
4437 | { | |
4438 | int reg_char; | |
4439 | int reg_scaled; | |
4440 | int i; | |
4441 | ||
4442 | vfp_regs_free &= ~(mask << regno); | |
4443 | reg_scaled = regno / shift; | |
4444 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
4445 | for (i = 0; i < vfp_base_count; i++) | |
4446 | { | |
4447 | char name_buf[4]; | |
4448 | int regnum; | |
58d6951d DJ |
4449 | if (reg_char == 'q') |
4450 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 4451 | val + i * unit_length); |
58d6951d DJ |
4452 | else |
4453 | { | |
8c042590 PM |
4454 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
4455 | reg_char, reg_scaled + i); | |
58d6951d DJ |
4456 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
4457 | strlen (name_buf)); | |
b66f5587 | 4458 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 4459 | } |
90445bd3 DJ |
4460 | } |
4461 | continue; | |
4462 | } | |
4463 | else | |
4464 | { | |
4465 | /* This CPRC could not go in VFP registers, so all VFP | |
4466 | registers are now marked as used. */ | |
4467 | vfp_regs_free = 0; | |
4468 | } | |
4469 | } | |
4470 | ||
85102364 | 4471 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
4472 | if (nstack & (align - 1)) |
4473 | { | |
f0452268 AH |
4474 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
4475 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
4476 | } |
4477 | ||
4478 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
4479 | if (may_use_core_reg |
4480 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 4481 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
4482 | && argreg & 1) |
4483 | argreg++; | |
4484 | ||
2dd604e7 RE |
4485 | /* If the argument is a pointer to a function, and it is a |
4486 | Thumb function, create a LOCAL copy of the value and set | |
4487 | the THUMB bit in it. */ | |
4488 | if (TYPE_CODE_PTR == typecode | |
4489 | && target_type != NULL | |
78134374 | 4490 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 4491 | { |
e17a4113 | 4492 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 4493 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 4494 | { |
224c3ddb | 4495 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 4496 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 4497 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 4498 | val = copy; |
2dd604e7 RE |
4499 | } |
4500 | } | |
4501 | ||
4502 | /* Copy the argument to general registers or the stack in | |
4503 | register-sized pieces. Large arguments are split between | |
4504 | registers and stack. */ | |
4505 | while (len > 0) | |
4506 | { | |
f0452268 AH |
4507 | int partial_len = len < ARM_INT_REGISTER_SIZE |
4508 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
4509 | CORE_ADDR regval |
4510 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 4511 | |
90445bd3 | 4512 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
4513 | { |
4514 | /* The argument is being passed in a general purpose | |
4515 | register. */ | |
e17a4113 | 4516 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 4517 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
7cb6d92a SM |
4518 | |
4519 | arm_debug_printf ("arg %d in %s = 0x%s", argnum, | |
4520 | gdbarch_register_name (gdbarch, argreg), | |
4521 | phex (regval, ARM_INT_REGISTER_SIZE)); | |
4522 | ||
2dd604e7 RE |
4523 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
4524 | argreg++; | |
4525 | } | |
4526 | else | |
4527 | { | |
f0452268 | 4528 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
4529 | |
4530 | memset (buf, 0, sizeof (buf)); | |
4531 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
4532 | ||
2dd604e7 | 4533 | /* Push the arguments onto the stack. */ |
7cb6d92a | 4534 | arm_debug_printf ("arg %d @ sp + %d", argnum, nstack); |
f0452268 AH |
4535 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
4536 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
4537 | } |
4538 | ||
4539 | len -= partial_len; | |
4540 | val += partial_len; | |
4541 | } | |
4542 | } | |
4543 | /* If we have an odd number of words to push, then decrement the stack | |
4544 | by one word now, so first stack argument will be dword aligned. */ | |
4545 | if (nstack & 4) | |
4546 | sp -= 4; | |
4547 | ||
4548 | while (si) | |
4549 | { | |
4550 | sp -= si->len; | |
4551 | write_memory (sp, si->data, si->len); | |
4552 | si = pop_stack_item (si); | |
4553 | } | |
4554 | ||
4555 | /* Finally, update teh SP register. */ | |
4556 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
4557 | ||
4558 | return sp; | |
4559 | } | |
4560 | ||
f53f0d0b PB |
4561 | |
4562 | /* Always align the frame to an 8-byte boundary. This is required on | |
4563 | some platforms and harmless on the rest. */ | |
4564 | ||
4565 | static CORE_ADDR | |
4566 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
4567 | { | |
4568 | /* Align the stack to eight bytes. */ | |
4569 | return sp & ~ (CORE_ADDR) 7; | |
4570 | } | |
4571 | ||
c906108c | 4572 | static void |
12b27276 | 4573 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 4574 | { |
c5aa993b | 4575 | if (flags & (1 << 0)) |
0426ad51 | 4576 | gdb_puts ("IVO ", file); |
c5aa993b | 4577 | if (flags & (1 << 1)) |
0426ad51 | 4578 | gdb_puts ("DVZ ", file); |
c5aa993b | 4579 | if (flags & (1 << 2)) |
0426ad51 | 4580 | gdb_puts ("OFL ", file); |
c5aa993b | 4581 | if (flags & (1 << 3)) |
0426ad51 | 4582 | gdb_puts ("UFL ", file); |
c5aa993b | 4583 | if (flags & (1 << 4)) |
0426ad51 | 4584 | gdb_puts ("INX ", file); |
a11ac3b3 | 4585 | gdb_putc ('\n', file); |
c906108c SS |
4586 | } |
4587 | ||
5e74b15c RE |
4588 | /* Print interesting information about the floating point processor |
4589 | (if present) or emulator. */ | |
34e8f22d | 4590 | static void |
d855c300 | 4591 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 4592 | struct frame_info *frame, const char *args) |
c906108c | 4593 | { |
9c9acae0 | 4594 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4595 | int type; |
4596 | ||
4597 | type = (status >> 24) & 127; | |
edefbb7c | 4598 | if (status & (1 << 31)) |
6cb06a8c | 4599 | gdb_printf (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4600 | else |
6cb06a8c | 4601 | gdb_printf (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4602 | /* i18n: [floating point unit] mask */ |
0426ad51 | 4603 | gdb_puts (_("mask: "), file); |
12b27276 | 4604 | print_fpu_flags (file, status >> 16); |
edefbb7c | 4605 | /* i18n: [floating point unit] flags */ |
0426ad51 | 4606 | gdb_puts (_("flags: "), file); |
12b27276 | 4607 | print_fpu_flags (file, status); |
c906108c SS |
4608 | } |
4609 | ||
27067745 UW |
4610 | /* Construct the ARM extended floating point type. */ |
4611 | static struct type * | |
4612 | arm_ext_type (struct gdbarch *gdbarch) | |
4613 | { | |
08106042 | 4614 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
27067745 UW |
4615 | |
4616 | if (!tdep->arm_ext_type) | |
4617 | tdep->arm_ext_type | |
e9bb382b | 4618 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4619 | floatformats_arm_ext); |
4620 | ||
4621 | return tdep->arm_ext_type; | |
4622 | } | |
4623 | ||
58d6951d DJ |
4624 | static struct type * |
4625 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4626 | { | |
08106042 | 4627 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4628 | |
4629 | if (tdep->neon_double_type == NULL) | |
4630 | { | |
4631 | struct type *t, *elem; | |
4632 | ||
4633 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4634 | TYPE_CODE_UNION); | |
4635 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4636 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4637 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4638 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4639 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4640 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4641 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4642 | append_composite_type_field (t, "u64", elem); | |
4643 | elem = builtin_type (gdbarch)->builtin_float; | |
4644 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4645 | elem = builtin_type (gdbarch)->builtin_double; | |
4646 | append_composite_type_field (t, "f64", elem); | |
4647 | ||
2062087b | 4648 | t->set_is_vector (true); |
d0e39ea2 | 4649 | t->set_name ("neon_d"); |
58d6951d DJ |
4650 | tdep->neon_double_type = t; |
4651 | } | |
4652 | ||
4653 | return tdep->neon_double_type; | |
4654 | } | |
4655 | ||
4656 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4657 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4658 | bits of d0 - regardless of what unit size is being held in d0. So | |
4659 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4660 | first float is 4. This code works as-is for little-endian | |
4661 | targets. */ | |
4662 | ||
4663 | static struct type * | |
4664 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4665 | { | |
08106042 | 4666 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
4667 | |
4668 | if (tdep->neon_quad_type == NULL) | |
4669 | { | |
4670 | struct type *t, *elem; | |
4671 | ||
4672 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4673 | TYPE_CODE_UNION); | |
4674 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4675 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4676 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4677 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4678 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4679 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4680 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4681 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4682 | elem = builtin_type (gdbarch)->builtin_float; | |
4683 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4684 | elem = builtin_type (gdbarch)->builtin_double; | |
4685 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4686 | ||
2062087b | 4687 | t->set_is_vector (true); |
d0e39ea2 | 4688 | t->set_name ("neon_q"); |
58d6951d DJ |
4689 | tdep->neon_quad_type = t; |
4690 | } | |
4691 | ||
4692 | return tdep->neon_quad_type; | |
4693 | } | |
4694 | ||
ecbf5d4f LM |
4695 | /* Return true if REGNUM is a Q pseudo register. Return false |
4696 | otherwise. | |
4697 | ||
4698 | REGNUM is the raw register number and not a pseudo-relative register | |
4699 | number. */ | |
4700 | ||
4701 | static bool | |
4702 | is_q_pseudo (struct gdbarch *gdbarch, int regnum) | |
4703 | { | |
08106042 | 4704 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f | 4705 | |
ae66a8f1 SP |
4706 | /* Q pseudo registers are available for both NEON (Q0~Q15) and |
4707 | MVE (Q0~Q7) features. */ | |
ecbf5d4f LM |
4708 | if (tdep->have_q_pseudos |
4709 | && regnum >= tdep->q_pseudo_base | |
4710 | && regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count)) | |
4711 | return true; | |
4712 | ||
4713 | return false; | |
4714 | } | |
4715 | ||
4716 | /* Return true if REGNUM is a VFP S pseudo register. Return false | |
4717 | otherwise. | |
4718 | ||
4719 | REGNUM is the raw register number and not a pseudo-relative register | |
4720 | number. */ | |
4721 | ||
4722 | static bool | |
4723 | is_s_pseudo (struct gdbarch *gdbarch, int regnum) | |
4724 | { | |
08106042 | 4725 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ecbf5d4f LM |
4726 | |
4727 | if (tdep->have_s_pseudos | |
4728 | && regnum >= tdep->s_pseudo_base | |
4729 | && regnum < (tdep->s_pseudo_base + tdep->s_pseudo_count)) | |
4730 | return true; | |
4731 | ||
4732 | return false; | |
4733 | } | |
4734 | ||
ae66a8f1 SP |
4735 | /* Return true if REGNUM is a MVE pseudo register (P0). Return false |
4736 | otherwise. | |
4737 | ||
4738 | REGNUM is the raw register number and not a pseudo-relative register | |
4739 | number. */ | |
4740 | ||
4741 | static bool | |
4742 | is_mve_pseudo (struct gdbarch *gdbarch, int regnum) | |
4743 | { | |
08106042 | 4744 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
4745 | |
4746 | if (tdep->have_mve | |
4747 | && regnum >= tdep->mve_pseudo_base | |
4748 | && regnum < tdep->mve_pseudo_base + tdep->mve_pseudo_count) | |
4749 | return true; | |
4750 | ||
4751 | return false; | |
4752 | } | |
4753 | ||
a01567f4 LM |
4754 | /* Return true if REGNUM is a PACBTI pseudo register (ra_auth_code). Return |
4755 | false otherwise. | |
4756 | ||
4757 | REGNUM is the raw register number and not a pseudo-relative register | |
4758 | number. */ | |
4759 | ||
4760 | static bool | |
4761 | is_pacbti_pseudo (struct gdbarch *gdbarch, int regnum) | |
4762 | { | |
08106042 | 4763 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
4764 | |
4765 | if (tdep->have_pacbti | |
4766 | && regnum >= tdep->pacbti_pseudo_base | |
4767 | && regnum < tdep->pacbti_pseudo_base + tdep->pacbti_pseudo_count) | |
4768 | return true; | |
4769 | ||
4770 | return false; | |
4771 | } | |
4772 | ||
34e8f22d RE |
4773 | /* Return the GDB type object for the "standard" data type of data in |
4774 | register N. */ | |
4775 | ||
4776 | static struct type * | |
7a5ea0d4 | 4777 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4778 | { |
08106042 | 4779 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 4780 | |
ecbf5d4f | 4781 | if (is_s_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4782 | return builtin_type (gdbarch)->builtin_float; |
4783 | ||
ecbf5d4f | 4784 | if (is_q_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4785 | return arm_neon_quad_type (gdbarch); |
4786 | ||
ae66a8f1 SP |
4787 | if (is_mve_pseudo (gdbarch, regnum)) |
4788 | return builtin_type (gdbarch)->builtin_int16; | |
4789 | ||
a01567f4 LM |
4790 | if (is_pacbti_pseudo (gdbarch, regnum)) |
4791 | return builtin_type (gdbarch)->builtin_uint32; | |
4792 | ||
58d6951d DJ |
4793 | /* If the target description has register information, we are only |
4794 | in this function so that we can override the types of | |
4795 | double-precision registers for NEON. */ | |
4796 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4797 | { | |
4798 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4799 | ||
4800 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 4801 | && t->code () == TYPE_CODE_FLT |
ecbf5d4f | 4802 | && tdep->have_neon) |
58d6951d DJ |
4803 | return arm_neon_double_type (gdbarch); |
4804 | else | |
4805 | return t; | |
4806 | } | |
4807 | ||
34e8f22d | 4808 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d | 4809 | { |
ecbf5d4f | 4810 | if (!tdep->have_fpa_registers) |
58d6951d DJ |
4811 | return builtin_type (gdbarch)->builtin_void; |
4812 | ||
4813 | return arm_ext_type (gdbarch); | |
4814 | } | |
e4c16157 | 4815 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4816 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4817 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4818 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4819 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4820 | /* These registers are only supported on targets which supply | |
4821 | an XML description. */ | |
df4df182 | 4822 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4823 | else |
df4df182 | 4824 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4825 | } |
4826 | ||
ff6f572f DJ |
4827 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4828 | number. */ | |
4829 | ||
4830 | static int | |
d3f73121 | 4831 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4832 | { |
4833 | /* Core integer regs. */ | |
4834 | if (reg >= 0 && reg <= 15) | |
4835 | return reg; | |
4836 | ||
4837 | /* Legacy FPA encoding. These were once used in a way which | |
4838 | overlapped with VFP register numbering, so their use is | |
4839 | discouraged, but GDB doesn't support the ARM toolchain | |
4840 | which used them for VFP. */ | |
4841 | if (reg >= 16 && reg <= 23) | |
4842 | return ARM_F0_REGNUM + reg - 16; | |
4843 | ||
4844 | /* New assignments for the FPA registers. */ | |
4845 | if (reg >= 96 && reg <= 103) | |
4846 | return ARM_F0_REGNUM + reg - 96; | |
4847 | ||
4848 | /* WMMX register assignments. */ | |
4849 | if (reg >= 104 && reg <= 111) | |
4850 | return ARM_WCGR0_REGNUM + reg - 104; | |
4851 | ||
4852 | if (reg >= 112 && reg <= 127) | |
4853 | return ARM_WR0_REGNUM + reg - 112; | |
4854 | ||
a01567f4 LM |
4855 | /* PACBTI register containing the Pointer Authentication Code. */ |
4856 | if (reg == ARM_DWARF_RA_AUTH_CODE) | |
4857 | { | |
08106042 | 4858 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
a01567f4 LM |
4859 | |
4860 | if (tdep->have_pacbti) | |
4861 | return tdep->pacbti_pseudo_base; | |
4862 | ||
4863 | return -1; | |
4864 | } | |
4865 | ||
ff6f572f DJ |
4866 | if (reg >= 192 && reg <= 199) |
4867 | return ARM_WC0_REGNUM + reg - 192; | |
4868 | ||
58d6951d DJ |
4869 | /* VFP v2 registers. A double precision value is actually |
4870 | in d1 rather than s2, but the ABI only defines numbering | |
4871 | for the single precision registers. This will "just work" | |
4872 | in GDB for little endian targets (we'll read eight bytes, | |
4873 | starting in s0 and then progressing to s1), but will be | |
4874 | reversed on big endian targets with VFP. This won't | |
4875 | be a problem for the new Neon quad registers; you're supposed | |
4876 | to use DW_OP_piece for those. */ | |
4877 | if (reg >= 64 && reg <= 95) | |
4878 | { | |
4879 | char name_buf[4]; | |
4880 | ||
8c042590 | 4881 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4882 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4883 | strlen (name_buf)); | |
4884 | } | |
4885 | ||
4886 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4887 | registers, except that it now describes d0 instead of s0. */ | |
4888 | if (reg >= 256 && reg <= 287) | |
4889 | { | |
4890 | char name_buf[4]; | |
4891 | ||
8c042590 | 4892 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4893 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4894 | strlen (name_buf)); | |
4895 | } | |
4896 | ||
ff6f572f DJ |
4897 | return -1; |
4898 | } | |
4899 | ||
26216b98 AC |
4900 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4901 | static int | |
e7faf938 | 4902 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4903 | { |
4904 | int reg = regnum; | |
e7faf938 | 4905 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4906 | |
ff6f572f DJ |
4907 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4908 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4909 | ||
4910 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4911 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4912 | ||
4913 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4914 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4915 | ||
26216b98 AC |
4916 | if (reg < NUM_GREGS) |
4917 | return SIM_ARM_R0_REGNUM + reg; | |
4918 | reg -= NUM_GREGS; | |
4919 | ||
4920 | if (reg < NUM_FREGS) | |
4921 | return SIM_ARM_FP0_REGNUM + reg; | |
4922 | reg -= NUM_FREGS; | |
4923 | ||
4924 | if (reg < NUM_SREGS) | |
4925 | return SIM_ARM_FPS_REGNUM + reg; | |
4926 | reg -= NUM_SREGS; | |
4927 | ||
edefbb7c | 4928 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4929 | } |
34e8f22d | 4930 | |
a01567f4 LM |
4931 | static const unsigned char op_lit0 = DW_OP_lit0; |
4932 | ||
4933 | static void | |
4934 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
4935 | struct dwarf2_frame_state_reg *reg, | |
4936 | struct frame_info *this_frame) | |
4937 | { | |
4938 | if (is_pacbti_pseudo (gdbarch, regnum)) | |
4939 | { | |
4940 | /* Initialize RA_AUTH_CODE to zero. */ | |
4941 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
4942 | reg->loc.exp.start = &op_lit0; | |
4943 | reg->loc.exp.len = 1; | |
4944 | return; | |
4945 | } | |
4946 | ||
4947 | switch (regnum) | |
4948 | { | |
4949 | case ARM_PC_REGNUM: | |
4950 | case ARM_PS_REGNUM: | |
4951 | reg->how = DWARF2_FRAME_REG_FN; | |
4952 | reg->loc.fn = arm_dwarf2_prev_register; | |
4953 | break; | |
4954 | case ARM_SP_REGNUM: | |
4955 | reg->how = DWARF2_FRAME_REG_CFA; | |
4956 | break; | |
4957 | } | |
4958 | } | |
4959 | ||
d9311bfa AT |
4960 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
4961 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
4962 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 4963 | |
d9311bfa AT |
4964 | static gdb_byte * |
4965 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
4966 | int old_len, int new_len) | |
4967 | { | |
4968 | gdb_byte *new_buf; | |
4969 | int bytes_to_read = new_len - old_len; | |
c906108c | 4970 | |
d9311bfa AT |
4971 | new_buf = (gdb_byte *) xmalloc (new_len); |
4972 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
4973 | xfree (buf); | |
198cd59d | 4974 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
4975 | { |
4976 | xfree (new_buf); | |
4977 | return NULL; | |
c906108c | 4978 | } |
d9311bfa | 4979 | return new_buf; |
c906108c SS |
4980 | } |
4981 | ||
d9311bfa AT |
4982 | /* An IT block is at most the 2-byte IT instruction followed by |
4983 | four 4-byte instructions. The furthest back we must search to | |
4984 | find an IT block that affects the current instruction is thus | |
4985 | 2 + 3 * 4 == 14 bytes. */ | |
4986 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 4987 | |
d9311bfa AT |
4988 | /* Use a quick scan if there are more than this many bytes of |
4989 | code. */ | |
4990 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 4991 | |
d9311bfa AT |
4992 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
4993 | A breakpoint in an IT block may not be hit, depending on the | |
4994 | condition flags. */ | |
ad527d2e | 4995 | static CORE_ADDR |
d9311bfa | 4996 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 4997 | { |
d9311bfa AT |
4998 | gdb_byte *buf; |
4999 | char map_type; | |
5000 | CORE_ADDR boundary, func_start; | |
5001 | int buf_len; | |
5002 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
5003 | int i, any, last_it, last_it_count; | |
08106042 | 5004 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 5005 | |
d9311bfa | 5006 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
345bd07c | 5007 | if (tdep->thumb2_breakpoint == NULL) |
d9311bfa | 5008 | return bpaddr; |
177321bd | 5009 | |
d9311bfa AT |
5010 | /* ARM mode does not have this problem. */ |
5011 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
5012 | return bpaddr; | |
177321bd | 5013 | |
d9311bfa AT |
5014 | /* We are setting a breakpoint in Thumb code that could potentially |
5015 | contain an IT block. The first step is to find how much Thumb | |
5016 | code there is; we do not need to read outside of known Thumb | |
5017 | sequences. */ | |
5018 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
5019 | if (map_type == 0) | |
5020 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
5021 | return bpaddr; | |
9dca5578 | 5022 | |
d9311bfa | 5023 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 5024 | |
d9311bfa AT |
5025 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
5026 | && func_start > boundary) | |
5027 | boundary = func_start; | |
9dca5578 | 5028 | |
d9311bfa AT |
5029 | /* Search for a candidate IT instruction. We have to do some fancy |
5030 | footwork to distinguish a real IT instruction from the second | |
5031 | half of a 32-bit instruction, but there is no need for that if | |
5032 | there's no candidate. */ | |
325fac50 | 5033 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
5034 | if (buf_len == 0) |
5035 | /* No room for an IT instruction. */ | |
5036 | return bpaddr; | |
c906108c | 5037 | |
d9311bfa | 5038 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 5039 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
5040 | return bpaddr; |
5041 | any = 0; | |
5042 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 5043 | { |
d9311bfa AT |
5044 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
5045 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 5046 | { |
d9311bfa AT |
5047 | any = 1; |
5048 | break; | |
25b41d01 | 5049 | } |
c906108c | 5050 | } |
d9311bfa AT |
5051 | |
5052 | if (any == 0) | |
c906108c | 5053 | { |
d9311bfa AT |
5054 | xfree (buf); |
5055 | return bpaddr; | |
f9d67f43 DJ |
5056 | } |
5057 | ||
5058 | /* OK, the code bytes before this instruction contain at least one | |
5059 | halfword which resembles an IT instruction. We know that it's | |
5060 | Thumb code, but there are still two possibilities. Either the | |
5061 | halfword really is an IT instruction, or it is the second half of | |
5062 | a 32-bit Thumb instruction. The only way we can tell is to | |
5063 | scan forwards from a known instruction boundary. */ | |
5064 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
5065 | { | |
5066 | int definite; | |
5067 | ||
5068 | /* There's a lot of code before this instruction. Start with an | |
5069 | optimistic search; it's easy to recognize halfwords that can | |
5070 | not be the start of a 32-bit instruction, and use that to | |
5071 | lock on to the instruction boundaries. */ | |
5072 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
5073 | if (buf == NULL) | |
5074 | return bpaddr; | |
5075 | buf_len = IT_SCAN_THRESHOLD; | |
5076 | ||
5077 | definite = 0; | |
5078 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
5079 | { | |
5080 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5081 | if (thumb_insn_size (inst1) == 2) | |
5082 | { | |
5083 | definite = 1; | |
5084 | break; | |
5085 | } | |
5086 | } | |
5087 | ||
5088 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
5089 | are sure that we know the instruction boundaries, and it is far | |
5090 | enough from BPADDR that we could not miss an IT instruction | |
5091 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
5092 | known boundary. */ | |
5093 | if (! definite) | |
5094 | { | |
0963b4bd MS |
5095 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
5096 | bpaddr - boundary); | |
f9d67f43 DJ |
5097 | if (buf == NULL) |
5098 | return bpaddr; | |
5099 | buf_len = bpaddr - boundary; | |
5100 | i = 0; | |
5101 | } | |
5102 | } | |
5103 | else | |
5104 | { | |
5105 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
5106 | if (buf == NULL) | |
5107 | return bpaddr; | |
5108 | buf_len = bpaddr - boundary; | |
5109 | i = 0; | |
5110 | } | |
5111 | ||
5112 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
5113 | last_it = -1; | |
5114 | last_it_count = 0; | |
5115 | while (i < buf_len) | |
5116 | { | |
5117 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
5118 | last_it_count--; | |
5119 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
5120 | { | |
5121 | last_it = i; | |
5122 | if (inst1 & 0x0001) | |
5123 | last_it_count = 4; | |
5124 | else if (inst1 & 0x0002) | |
5125 | last_it_count = 3; | |
5126 | else if (inst1 & 0x0004) | |
5127 | last_it_count = 2; | |
5128 | else | |
5129 | last_it_count = 1; | |
5130 | } | |
5131 | i += thumb_insn_size (inst1); | |
5132 | } | |
5133 | ||
5134 | xfree (buf); | |
5135 | ||
5136 | if (last_it == -1) | |
5137 | /* There wasn't really an IT instruction after all. */ | |
5138 | return bpaddr; | |
5139 | ||
5140 | if (last_it_count < 1) | |
5141 | /* It was too far away. */ | |
5142 | return bpaddr; | |
5143 | ||
5144 | /* This really is a trouble spot. Move the breakpoint to the IT | |
5145 | instruction. */ | |
5146 | return bpaddr - buf_len + last_it; | |
5147 | } | |
5148 | ||
cca44b1b | 5149 | /* ARM displaced stepping support. |
c906108c | 5150 | |
cca44b1b | 5151 | Generally ARM displaced stepping works as follows: |
c906108c | 5152 | |
cca44b1b | 5153 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
5154 | arm_process_displaced_insn. Depending on the type of instruction, it is |
5155 | then copied to a scratch location, possibly in a modified form. The | |
5156 | copy_* set of functions performs such modification, as necessary. A | |
5157 | breakpoint is placed after the modified instruction in the scratch space | |
5158 | to return control to GDB. Note in particular that instructions which | |
5159 | modify the PC will no longer do so after modification. | |
c5aa993b | 5160 | |
cca44b1b JB |
5161 | 2. The instruction is single-stepped, by setting the PC to the scratch |
5162 | location address, and resuming. Control returns to GDB when the | |
5163 | breakpoint is hit. | |
c5aa993b | 5164 | |
cca44b1b JB |
5165 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
5166 | function used for the current instruction. This function's job is to | |
5167 | put the CPU/memory state back to what it would have been if the | |
5168 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 5169 | |
cca44b1b JB |
5170 | /* NOP instruction (mov r0, r0). */ |
5171 | #define ARM_NOP 0xe1a00000 | |
34518530 | 5172 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
5173 | |
5174 | /* Helper for register reads for displaced stepping. In particular, this | |
5175 | returns the PC as it would be seen by the instruction at its original | |
5176 | location. */ | |
5177 | ||
5178 | ULONGEST | |
1152d984 | 5179 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5180 | int regno) |
cca44b1b JB |
5181 | { |
5182 | ULONGEST ret; | |
36073a92 | 5183 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 5184 | |
bf9f652a | 5185 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 5186 | { |
4db71c0b YQ |
5187 | /* Compute pipeline offset: |
5188 | - When executing an ARM instruction, PC reads as the address of the | |
5189 | current instruction plus 8. | |
5190 | - When executing a Thumb instruction, PC reads as the address of the | |
5191 | current instruction plus 4. */ | |
5192 | ||
36073a92 | 5193 | if (!dsc->is_thumb) |
4db71c0b YQ |
5194 | from += 8; |
5195 | else | |
5196 | from += 4; | |
5197 | ||
136821d9 SM |
5198 | displaced_debug_printf ("read pc value %.8lx", |
5199 | (unsigned long) from); | |
4db71c0b | 5200 | return (ULONGEST) from; |
cca44b1b | 5201 | } |
c906108c | 5202 | else |
cca44b1b JB |
5203 | { |
5204 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
5205 | |
5206 | displaced_debug_printf ("read r%d value %.8lx", | |
5207 | regno, (unsigned long) ret); | |
5208 | ||
cca44b1b JB |
5209 | return ret; |
5210 | } | |
c906108c SS |
5211 | } |
5212 | ||
cca44b1b JB |
5213 | static int |
5214 | displaced_in_arm_mode (struct regcache *regs) | |
5215 | { | |
5216 | ULONGEST ps; | |
ac7936df | 5217 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 5218 | |
cca44b1b | 5219 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 5220 | |
9779414d | 5221 | return (ps & t_bit) == 0; |
cca44b1b | 5222 | } |
66e810cd | 5223 | |
cca44b1b | 5224 | /* Write to the PC as from a branch instruction. */ |
c906108c | 5225 | |
cca44b1b | 5226 | static void |
1152d984 | 5227 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5228 | ULONGEST val) |
c906108c | 5229 | { |
36073a92 | 5230 | if (!dsc->is_thumb) |
cca44b1b JB |
5231 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
5232 | architecture versions < 6. */ | |
0963b4bd MS |
5233 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5234 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 5235 | else |
0963b4bd MS |
5236 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
5237 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 5238 | } |
66e810cd | 5239 | |
cca44b1b JB |
5240 | /* Write to the PC as from a branch-exchange instruction. */ |
5241 | ||
5242 | static void | |
5243 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
5244 | { | |
5245 | ULONGEST ps; | |
ac7936df | 5246 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
5247 | |
5248 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
5249 | ||
5250 | if ((val & 1) == 1) | |
c906108c | 5251 | { |
9779414d | 5252 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
5253 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
5254 | } | |
5255 | else if ((val & 2) == 0) | |
5256 | { | |
9779414d | 5257 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5258 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
5259 | } |
5260 | else | |
5261 | { | |
cca44b1b JB |
5262 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
5263 | mode, align dest to 4 bytes). */ | |
5264 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 5265 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 5266 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
5267 | } |
5268 | } | |
ed9a39eb | 5269 | |
cca44b1b | 5270 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 5271 | |
34e8f22d | 5272 | static void |
1152d984 | 5273 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5274 | ULONGEST val) |
ed9a39eb | 5275 | { |
cca44b1b JB |
5276 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
5277 | bx_write_pc (regs, val); | |
5278 | else | |
36073a92 | 5279 | branch_write_pc (regs, dsc, val); |
cca44b1b | 5280 | } |
be8626e0 | 5281 | |
cca44b1b JB |
5282 | /* Write to the PC as if from an ALU instruction. */ |
5283 | ||
5284 | static void | |
1152d984 | 5285 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 5286 | ULONGEST val) |
cca44b1b | 5287 | { |
36073a92 | 5288 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
5289 | bx_write_pc (regs, val); |
5290 | else | |
36073a92 | 5291 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
5292 | } |
5293 | ||
5294 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
5295 | has a varying effects depending on the instruction which does the write: | |
5296 | this is controlled by the WRITE_PC argument. */ | |
5297 | ||
5298 | void | |
1152d984 | 5299 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
5300 | int regno, ULONGEST val, enum pc_write_style write_pc) |
5301 | { | |
bf9f652a | 5302 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 5303 | { |
136821d9 SM |
5304 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
5305 | ||
cca44b1b | 5306 | switch (write_pc) |
08216dd7 | 5307 | { |
cca44b1b | 5308 | case BRANCH_WRITE_PC: |
36073a92 | 5309 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
5310 | break; |
5311 | ||
cca44b1b JB |
5312 | case BX_WRITE_PC: |
5313 | bx_write_pc (regs, val); | |
24b21115 | 5314 | break; |
cca44b1b JB |
5315 | |
5316 | case LOAD_WRITE_PC: | |
36073a92 | 5317 | load_write_pc (regs, dsc, val); |
24b21115 | 5318 | break; |
cca44b1b JB |
5319 | |
5320 | case ALU_WRITE_PC: | |
36073a92 | 5321 | alu_write_pc (regs, dsc, val); |
24b21115 | 5322 | break; |
cca44b1b JB |
5323 | |
5324 | case CANNOT_WRITE_PC: | |
5325 | warning (_("Instruction wrote to PC in an unexpected way when " | |
5326 | "single-stepping")); | |
08216dd7 RE |
5327 | break; |
5328 | ||
5329 | default: | |
97b9747c JB |
5330 | internal_error (__FILE__, __LINE__, |
5331 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 5332 | } |
b508a996 | 5333 | |
cca44b1b | 5334 | dsc->wrote_to_pc = 1; |
b508a996 | 5335 | } |
ed9a39eb | 5336 | else |
b508a996 | 5337 | { |
136821d9 SM |
5338 | displaced_debug_printf ("writing r%d value %.8lx", |
5339 | regno, (unsigned long) val); | |
cca44b1b | 5340 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 5341 | } |
34e8f22d RE |
5342 | } |
5343 | ||
cca44b1b JB |
5344 | /* This function is used to concisely determine if an instruction INSN |
5345 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
5346 | corresponding fields of BITMASK set to 0b1111. The function |
5347 | returns return 1 if any of these fields in INSN reference the PC | |
5348 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
5349 | |
5350 | static int | |
cca44b1b | 5351 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 5352 | { |
cca44b1b | 5353 | uint32_t lowbit = 1; |
67255d04 | 5354 | |
cca44b1b JB |
5355 | while (bitmask != 0) |
5356 | { | |
5357 | uint32_t mask; | |
44e1a9eb | 5358 | |
cca44b1b JB |
5359 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
5360 | ; | |
67255d04 | 5361 | |
cca44b1b JB |
5362 | if (!lowbit) |
5363 | break; | |
67255d04 | 5364 | |
cca44b1b | 5365 | mask = lowbit * 0xf; |
67255d04 | 5366 | |
cca44b1b JB |
5367 | if ((insn & mask) == mask) |
5368 | return 1; | |
5369 | ||
5370 | bitmask &= ~mask; | |
67255d04 RE |
5371 | } |
5372 | ||
cca44b1b JB |
5373 | return 0; |
5374 | } | |
2af48f68 | 5375 | |
cca44b1b JB |
5376 | /* The simplest copy function. Many instructions have the same effect no |
5377 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 5378 | |
cca44b1b | 5379 | static int |
1152d984 SM |
5380 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
5381 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 5382 | { |
136821d9 SM |
5383 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
5384 | (unsigned long) insn, iname); | |
67255d04 | 5385 | |
cca44b1b | 5386 | dsc->modinsn[0] = insn; |
67255d04 | 5387 | |
cca44b1b JB |
5388 | return 0; |
5389 | } | |
5390 | ||
34518530 YQ |
5391 | static int |
5392 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
5393 | uint16_t insn2, const char *iname, | |
1152d984 | 5394 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5395 | { |
136821d9 SM |
5396 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
5397 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
5398 | |
5399 | dsc->modinsn[0] = insn1; | |
5400 | dsc->modinsn[1] = insn2; | |
5401 | dsc->numinsns = 2; | |
5402 | ||
5403 | return 0; | |
5404 | } | |
5405 | ||
5406 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
5407 | modification. */ | |
5408 | static int | |
615234c1 | 5409 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 5410 | const char *iname, |
1152d984 | 5411 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5412 | { |
136821d9 SM |
5413 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
5414 | insn, iname); | |
34518530 YQ |
5415 | |
5416 | dsc->modinsn[0] = insn; | |
5417 | ||
5418 | return 0; | |
5419 | } | |
5420 | ||
cca44b1b JB |
5421 | /* Preload instructions with immediate offset. */ |
5422 | ||
5423 | static void | |
1152d984 SM |
5424 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
5425 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
5426 | { |
5427 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5428 | if (!dsc->u.preload.immed) | |
5429 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5430 | } | |
5431 | ||
7ff120b4 YQ |
5432 | static void |
5433 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5434 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 5435 | { |
cca44b1b | 5436 | ULONGEST rn_val; |
cca44b1b JB |
5437 | /* Preload instructions: |
5438 | ||
5439 | {pli/pld} [rn, #+/-imm] | |
5440 | -> | |
5441 | {pli/pld} [r0, #+/-imm]. */ | |
5442 | ||
36073a92 YQ |
5443 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5444 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5445 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
5446 | dsc->u.preload.immed = 1; |
5447 | ||
cca44b1b | 5448 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
5449 | } |
5450 | ||
cca44b1b | 5451 | static int |
7ff120b4 | 5452 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5453 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5454 | { |
5455 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 5456 | |
7ff120b4 YQ |
5457 | if (!insn_references_pc (insn, 0x000f0000ul)) |
5458 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 5459 | |
136821d9 | 5460 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 5461 | |
7ff120b4 YQ |
5462 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5463 | ||
5464 | install_preload (gdbarch, regs, dsc, rn); | |
5465 | ||
5466 | return 0; | |
5467 | } | |
5468 | ||
34518530 YQ |
5469 | static int |
5470 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 5471 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5472 | { |
5473 | unsigned int rn = bits (insn1, 0, 3); | |
5474 | unsigned int u_bit = bit (insn1, 7); | |
5475 | int imm12 = bits (insn2, 0, 11); | |
5476 | ULONGEST pc_val; | |
5477 | ||
5478 | if (rn != ARM_PC_REGNUM) | |
5479 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
5480 | ||
5481 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
5482 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
5483 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
5484 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
5485 | imm12); | |
34518530 YQ |
5486 | |
5487 | if (!u_bit) | |
5488 | imm12 = -1 * imm12; | |
5489 | ||
5490 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
5491 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
5492 | ||
5493 | {pli/pld} [r0, r1] | |
5494 | ||
5495 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
5496 | ||
5497 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5498 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5499 | ||
5500 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5501 | ||
5502 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
5503 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
5504 | dsc->u.preload.immed = 0; | |
5505 | ||
5506 | /* {pli/pld} [r0, r1] */ | |
5507 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5508 | dsc->modinsn[1] = 0xf001; | |
5509 | dsc->numinsns = 2; | |
5510 | ||
5511 | dsc->cleanup = &cleanup_preload; | |
5512 | return 0; | |
5513 | } | |
5514 | ||
7ff120b4 YQ |
5515 | /* Preload instructions with register offset. */ |
5516 | ||
5517 | static void | |
5518 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5519 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
5520 | unsigned int rm) |
5521 | { | |
5522 | ULONGEST rn_val, rm_val; | |
5523 | ||
cca44b1b JB |
5524 | /* Preload register-offset instructions: |
5525 | ||
5526 | {pli/pld} [rn, rm {, shift}] | |
5527 | -> | |
5528 | {pli/pld} [r0, r1 {, shift}]. */ | |
5529 | ||
36073a92 YQ |
5530 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5531 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5532 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5533 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5534 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5535 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
5536 | dsc->u.preload.immed = 0; |
5537 | ||
cca44b1b | 5538 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
5539 | } |
5540 | ||
5541 | static int | |
5542 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5543 | struct regcache *regs, | |
1152d984 | 5544 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5545 | { |
5546 | unsigned int rn = bits (insn, 16, 19); | |
5547 | unsigned int rm = bits (insn, 0, 3); | |
5548 | ||
5549 | ||
5550 | if (!insn_references_pc (insn, 0x000f000ful)) | |
5551 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
5552 | ||
136821d9 SM |
5553 | displaced_debug_printf ("copying preload insn %.8lx", |
5554 | (unsigned long) insn); | |
7ff120b4 YQ |
5555 | |
5556 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 5557 | |
7ff120b4 | 5558 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
5559 | return 0; |
5560 | } | |
5561 | ||
5562 | /* Copy/cleanup coprocessor load and store instructions. */ | |
5563 | ||
5564 | static void | |
6e39997a | 5565 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 5566 | struct regcache *regs, |
1152d984 | 5567 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5568 | { |
36073a92 | 5569 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5570 | |
5571 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5572 | ||
5573 | if (dsc->u.ldst.writeback) | |
5574 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
5575 | } | |
5576 | ||
7ff120b4 YQ |
5577 | static void |
5578 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5579 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5580 | int writeback, unsigned int rn) |
cca44b1b | 5581 | { |
cca44b1b | 5582 | ULONGEST rn_val; |
cca44b1b | 5583 | |
cca44b1b JB |
5584 | /* Coprocessor load/store instructions: |
5585 | ||
5586 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
5587 | -> | |
5588 | {stc/stc2} [r0, #+/-imm]. | |
5589 | ||
5590 | ldc/ldc2 are handled identically. */ | |
5591 | ||
36073a92 YQ |
5592 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5593 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
5594 | /* PC should be 4-byte aligned. */ |
5595 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
5596 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5597 | ||
7ff120b4 | 5598 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5599 | dsc->u.ldst.rn = rn; |
5600 | ||
7ff120b4 YQ |
5601 | dsc->cleanup = &cleanup_copro_load_store; |
5602 | } | |
5603 | ||
5604 | static int | |
5605 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
5606 | struct regcache *regs, | |
1152d984 | 5607 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5608 | { |
5609 | unsigned int rn = bits (insn, 16, 19); | |
5610 | ||
5611 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
5612 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
5613 | ||
136821d9 SM |
5614 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
5615 | (unsigned long) insn); | |
7ff120b4 | 5616 | |
cca44b1b JB |
5617 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5618 | ||
7ff120b4 | 5619 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
5620 | |
5621 | return 0; | |
5622 | } | |
5623 | ||
34518530 YQ |
5624 | static int |
5625 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
5626 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5627 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5628 | { |
5629 | unsigned int rn = bits (insn1, 0, 3); | |
5630 | ||
5631 | if (rn != ARM_PC_REGNUM) | |
5632 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
5633 | "copro load/store", dsc); | |
5634 | ||
136821d9 SM |
5635 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
5636 | insn1, insn2); | |
34518530 YQ |
5637 | |
5638 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5639 | dsc->modinsn[1] = insn2; | |
5640 | dsc->numinsns = 2; | |
5641 | ||
5642 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
5643 | doesn't support writeback, so pass 0. */ | |
5644 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
5645 | ||
5646 | return 0; | |
5647 | } | |
5648 | ||
cca44b1b JB |
5649 | /* Clean up branch instructions (actually perform the branch, by setting |
5650 | PC). */ | |
5651 | ||
5652 | static void | |
6e39997a | 5653 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5654 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5655 | { |
36073a92 | 5656 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5657 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
5658 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
5659 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
5660 | ||
5661 | if (!branch_taken) | |
5662 | return; | |
5663 | ||
5664 | if (dsc->u.branch.link) | |
5665 | { | |
8c8dba6d | 5666 | /* The value of LR should be the next insn of current one. In order |
85102364 | 5667 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
5668 | is Thumb, the bit 0 of LR value should be set to 1. */ |
5669 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
5670 | ||
5671 | if (dsc->is_thumb) | |
5672 | next_insn_addr |= 0x1; | |
5673 | ||
5674 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
5675 | CANNOT_WRITE_PC); | |
cca44b1b JB |
5676 | } |
5677 | ||
bf9f652a | 5678 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
5679 | } |
5680 | ||
5681 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
5682 | ||
7ff120b4 YQ |
5683 | static void |
5684 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5685 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5686 | unsigned int cond, int exchange, int link, long offset) |
5687 | { | |
5688 | /* Implement "BL<cond> <label>" as: | |
5689 | ||
5690 | Preparation: cond <- instruction condition | |
5691 | Insn: mov r0, r0 (nop) | |
5692 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
5693 | ||
5694 | B<cond> similar, but don't set r14 in cleanup. */ | |
5695 | ||
5696 | dsc->u.branch.cond = cond; | |
5697 | dsc->u.branch.link = link; | |
5698 | dsc->u.branch.exchange = exchange; | |
5699 | ||
2b16b2e3 YQ |
5700 | dsc->u.branch.dest = dsc->insn_addr; |
5701 | if (link && exchange) | |
5702 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5703 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5704 | ||
7ff120b4 | 5705 | if (dsc->is_thumb) |
2b16b2e3 | 5706 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5707 | else |
2b16b2e3 | 5708 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5709 | |
5710 | dsc->cleanup = &cleanup_branch; | |
5711 | } | |
cca44b1b | 5712 | static int |
7ff120b4 | 5713 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5714 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5715 | { |
5716 | unsigned int cond = bits (insn, 28, 31); | |
5717 | int exchange = (cond == 0xf); | |
5718 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5719 | long offset; |
5720 | ||
136821d9 SM |
5721 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5722 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5723 | (unsigned long) insn); | |
cca44b1b JB |
5724 | if (exchange) |
5725 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5726 | then arrange the switch into Thumb mode. */ | |
5727 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5728 | else | |
5729 | offset = bits (insn, 0, 23) << 2; | |
5730 | ||
5731 | if (bit (offset, 25)) | |
5732 | offset = offset | ~0x3ffffff; | |
5733 | ||
cca44b1b JB |
5734 | dsc->modinsn[0] = ARM_NOP; |
5735 | ||
7ff120b4 | 5736 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5737 | return 0; |
5738 | } | |
5739 | ||
34518530 YQ |
5740 | static int |
5741 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5742 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5743 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5744 | { |
5745 | int link = bit (insn2, 14); | |
5746 | int exchange = link && !bit (insn2, 12); | |
5747 | int cond = INST_AL; | |
5748 | long offset = 0; | |
5749 | int j1 = bit (insn2, 13); | |
5750 | int j2 = bit (insn2, 11); | |
5751 | int s = sbits (insn1, 10, 10); | |
5752 | int i1 = !(j1 ^ bit (insn1, 10)); | |
5753 | int i2 = !(j2 ^ bit (insn1, 10)); | |
5754 | ||
5755 | if (!link && !exchange) /* B */ | |
5756 | { | |
5757 | offset = (bits (insn2, 0, 10) << 1); | |
5758 | if (bit (insn2, 12)) /* Encoding T4 */ | |
5759 | { | |
5760 | offset |= (bits (insn1, 0, 9) << 12) | |
5761 | | (i2 << 22) | |
5762 | | (i1 << 23) | |
5763 | | (s << 24); | |
5764 | cond = INST_AL; | |
5765 | } | |
5766 | else /* Encoding T3 */ | |
5767 | { | |
5768 | offset |= (bits (insn1, 0, 5) << 12) | |
5769 | | (j1 << 18) | |
5770 | | (j2 << 19) | |
5771 | | (s << 20); | |
5772 | cond = bits (insn1, 6, 9); | |
5773 | } | |
5774 | } | |
5775 | else | |
5776 | { | |
5777 | offset = (bits (insn1, 0, 9) << 12); | |
5778 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
5779 | offset |= exchange ? | |
5780 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
5781 | } | |
5782 | ||
136821d9 SM |
5783 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
5784 | link ? (exchange) ? "blx" : "bl" : "b", | |
5785 | insn1, insn2, offset); | |
34518530 YQ |
5786 | |
5787 | dsc->modinsn[0] = THUMB_NOP; | |
5788 | ||
5789 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
5790 | return 0; | |
5791 | } | |
5792 | ||
5793 | /* Copy B Thumb instructions. */ | |
5794 | static int | |
615234c1 | 5795 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 5796 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5797 | { |
5798 | unsigned int cond = 0; | |
5799 | int offset = 0; | |
5800 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
5801 | CORE_ADDR from = dsc->insn_addr; | |
5802 | ||
5803 | if (bit_12_15 == 0xd) | |
5804 | { | |
5805 | /* offset = SignExtend (imm8:0, 32) */ | |
5806 | offset = sbits ((insn << 1), 0, 8); | |
5807 | cond = bits (insn, 8, 11); | |
5808 | } | |
5809 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
5810 | { | |
5811 | offset = sbits ((insn << 1), 0, 11); | |
5812 | cond = INST_AL; | |
5813 | } | |
5814 | ||
136821d9 SM |
5815 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
5816 | insn, offset); | |
34518530 YQ |
5817 | |
5818 | dsc->u.branch.cond = cond; | |
5819 | dsc->u.branch.link = 0; | |
5820 | dsc->u.branch.exchange = 0; | |
5821 | dsc->u.branch.dest = from + 4 + offset; | |
5822 | ||
5823 | dsc->modinsn[0] = THUMB_NOP; | |
5824 | ||
5825 | dsc->cleanup = &cleanup_branch; | |
5826 | ||
5827 | return 0; | |
5828 | } | |
5829 | ||
cca44b1b JB |
5830 | /* Copy BX/BLX with register-specified destinations. */ |
5831 | ||
7ff120b4 YQ |
5832 | static void |
5833 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5834 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 5835 | unsigned int cond, unsigned int rm) |
cca44b1b | 5836 | { |
cca44b1b JB |
5837 | /* Implement {BX,BLX}<cond> <reg>" as: |
5838 | ||
5839 | Preparation: cond <- instruction condition | |
5840 | Insn: mov r0, r0 (nop) | |
5841 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5842 | ||
5843 | Don't set r14 in cleanup for BX. */ | |
5844 | ||
36073a92 | 5845 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5846 | |
5847 | dsc->u.branch.cond = cond; | |
5848 | dsc->u.branch.link = link; | |
cca44b1b | 5849 | |
7ff120b4 | 5850 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
5851 | |
5852 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 5853 | } |
cca44b1b | 5854 | |
7ff120b4 YQ |
5855 | static int |
5856 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 5857 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5858 | { |
5859 | unsigned int cond = bits (insn, 28, 31); | |
5860 | /* BX: x12xxx1x | |
5861 | BLX: x12xxx3x. */ | |
5862 | int link = bit (insn, 5); | |
5863 | unsigned int rm = bits (insn, 0, 3); | |
5864 | ||
136821d9 | 5865 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
5866 | |
5867 | dsc->modinsn[0] = ARM_NOP; | |
5868 | ||
5869 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
5870 | return 0; |
5871 | } | |
5872 | ||
34518530 YQ |
5873 | static int |
5874 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5875 | struct regcache *regs, | |
1152d984 | 5876 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5877 | { |
5878 | int link = bit (insn, 7); | |
5879 | unsigned int rm = bits (insn, 3, 6); | |
5880 | ||
136821d9 | 5881 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
5882 | |
5883 | dsc->modinsn[0] = THUMB_NOP; | |
5884 | ||
5885 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
5886 | ||
5887 | return 0; | |
5888 | } | |
5889 | ||
5890 | ||
0963b4bd | 5891 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
5892 | |
5893 | static void | |
6e39997a | 5894 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 5895 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5896 | { |
36073a92 | 5897 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5898 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
5899 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5900 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5901 | } | |
5902 | ||
5903 | static int | |
7ff120b4 | 5904 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5905 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5906 | { |
5907 | unsigned int rn = bits (insn, 16, 19); | |
5908 | unsigned int rd = bits (insn, 12, 15); | |
5909 | unsigned int op = bits (insn, 21, 24); | |
5910 | int is_mov = (op == 0xd); | |
5911 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
5912 | |
5913 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 5914 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 5915 | |
136821d9 SM |
5916 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
5917 | is_mov ? "move" : "ALU", | |
5918 | (unsigned long) insn); | |
cca44b1b JB |
5919 | |
5920 | /* Instruction is of form: | |
5921 | ||
5922 | <op><cond> rd, [rn,] #imm | |
5923 | ||
5924 | Rewrite as: | |
5925 | ||
5926 | Preparation: tmp1, tmp2 <- r0, r1; | |
5927 | r0, r1 <- rd, rn | |
5928 | Insn: <op><cond> r0, r1, #imm | |
5929 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5930 | */ | |
5931 | ||
36073a92 YQ |
5932 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5933 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5934 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5935 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
5936 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5937 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5938 | dsc->rd = rd; | |
5939 | ||
5940 | if (is_mov) | |
5941 | dsc->modinsn[0] = insn & 0xfff00fff; | |
5942 | else | |
5943 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
5944 | ||
5945 | dsc->cleanup = &cleanup_alu_imm; | |
5946 | ||
5947 | return 0; | |
5948 | } | |
5949 | ||
34518530 YQ |
5950 | static int |
5951 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5952 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5953 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5954 | { |
5955 | unsigned int op = bits (insn1, 5, 8); | |
5956 | unsigned int rn, rm, rd; | |
5957 | ULONGEST rd_val, rn_val; | |
5958 | ||
5959 | rn = bits (insn1, 0, 3); /* Rn */ | |
5960 | rm = bits (insn2, 0, 3); /* Rm */ | |
5961 | rd = bits (insn2, 8, 11); /* Rd */ | |
5962 | ||
5963 | /* This routine is only called for instruction MOV. */ | |
5964 | gdb_assert (op == 0x2 && rn == 0xf); | |
5965 | ||
5966 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
5967 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
5968 | ||
136821d9 | 5969 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
5970 | |
5971 | /* Instruction is of form: | |
5972 | ||
5973 | <op><cond> rd, [rn,] #imm | |
5974 | ||
5975 | Rewrite as: | |
5976 | ||
5977 | Preparation: tmp1, tmp2 <- r0, r1; | |
5978 | r0, r1 <- rd, rn | |
5979 | Insn: <op><cond> r0, r1, #imm | |
5980 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5981 | */ | |
5982 | ||
5983 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5984 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5985 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5986 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5987 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
5988 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5989 | dsc->rd = rd; | |
5990 | ||
5991 | dsc->modinsn[0] = insn1; | |
5992 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
5993 | dsc->numinsns = 2; | |
5994 | ||
5995 | dsc->cleanup = &cleanup_alu_imm; | |
5996 | ||
5997 | return 0; | |
5998 | } | |
5999 | ||
cca44b1b JB |
6000 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
6001 | ||
6002 | static void | |
6e39997a | 6003 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 6004 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6005 | { |
6006 | ULONGEST rd_val; | |
6007 | int i; | |
6008 | ||
36073a92 | 6009 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6010 | |
6011 | for (i = 0; i < 3; i++) | |
6012 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6013 | ||
6014 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6015 | } | |
6016 | ||
7ff120b4 YQ |
6017 | static void |
6018 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6019 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 6020 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 6021 | { |
cca44b1b | 6022 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 6023 | |
cca44b1b JB |
6024 | /* Instruction is of form: |
6025 | ||
6026 | <op><cond> rd, [rn,] rm [, <shift>] | |
6027 | ||
6028 | Rewrite as: | |
6029 | ||
6030 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
6031 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 6032 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
6033 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
6034 | */ | |
6035 | ||
36073a92 YQ |
6036 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6037 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6038 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6039 | rd_val = displaced_read_reg (regs, dsc, rd); | |
6040 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6041 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
6042 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6043 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6044 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6045 | dsc->rd = rd; | |
6046 | ||
7ff120b4 YQ |
6047 | dsc->cleanup = &cleanup_alu_reg; |
6048 | } | |
6049 | ||
6050 | static int | |
6051 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 6052 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6053 | { |
6054 | unsigned int op = bits (insn, 21, 24); | |
6055 | int is_mov = (op == 0xd); | |
6056 | ||
6057 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6058 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
6059 | ||
136821d9 SM |
6060 | displaced_debug_printf ("copying reg %s insn %.8lx", |
6061 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 6062 | |
cca44b1b JB |
6063 | if (is_mov) |
6064 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
6065 | else | |
6066 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
6067 | ||
7ff120b4 YQ |
6068 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
6069 | bits (insn, 0, 3)); | |
cca44b1b JB |
6070 | return 0; |
6071 | } | |
6072 | ||
34518530 YQ |
6073 | static int |
6074 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
6075 | struct regcache *regs, | |
1152d984 | 6076 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 6077 | { |
ef713951 | 6078 | unsigned rm, rd; |
34518530 | 6079 | |
ef713951 YQ |
6080 | rm = bits (insn, 3, 6); |
6081 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 6082 | |
ef713951 | 6083 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
6084 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
6085 | ||
136821d9 | 6086 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 6087 | |
ef713951 | 6088 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 6089 | |
ef713951 | 6090 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
6091 | |
6092 | return 0; | |
6093 | } | |
6094 | ||
cca44b1b JB |
6095 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
6096 | ||
6097 | static void | |
6e39997a | 6098 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 6099 | struct regcache *regs, |
1152d984 | 6100 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6101 | { |
36073a92 | 6102 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
6103 | int i; |
6104 | ||
6105 | for (i = 0; i < 4; i++) | |
6106 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
6107 | ||
6108 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
6109 | } | |
6110 | ||
7ff120b4 YQ |
6111 | static void |
6112 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6113 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
6114 | unsigned int rd, unsigned int rn, unsigned int rm, |
6115 | unsigned rs) | |
cca44b1b | 6116 | { |
7ff120b4 | 6117 | int i; |
cca44b1b | 6118 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 6119 | |
cca44b1b JB |
6120 | /* Instruction is of form: |
6121 | ||
6122 | <op><cond> rd, [rn,] rm, <shift> rs | |
6123 | ||
6124 | Rewrite as: | |
6125 | ||
6126 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
6127 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
6128 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
6129 | Cleanup: tmp5 <- r0 | |
6130 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
6131 | rd <- tmp5 | |
6132 | */ | |
6133 | ||
6134 | for (i = 0; i < 4; i++) | |
36073a92 | 6135 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 6136 | |
36073a92 YQ |
6137 | rd_val = displaced_read_reg (regs, dsc, rd); |
6138 | rn_val = displaced_read_reg (regs, dsc, rn); | |
6139 | rm_val = displaced_read_reg (regs, dsc, rm); | |
6140 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
6141 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
6142 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
6143 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
6144 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
6145 | dsc->rd = rd; | |
7ff120b4 YQ |
6146 | dsc->cleanup = &cleanup_alu_shifted_reg; |
6147 | } | |
6148 | ||
6149 | static int | |
6150 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
6151 | struct regcache *regs, | |
1152d984 | 6152 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
6153 | { |
6154 | unsigned int op = bits (insn, 21, 24); | |
6155 | int is_mov = (op == 0xd); | |
6156 | unsigned int rd, rn, rm, rs; | |
6157 | ||
6158 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
6159 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
6160 | ||
136821d9 SM |
6161 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
6162 | is_mov ? "move" : "ALU", | |
6163 | (unsigned long) insn); | |
7ff120b4 YQ |
6164 | |
6165 | rn = bits (insn, 16, 19); | |
6166 | rm = bits (insn, 0, 3); | |
6167 | rs = bits (insn, 8, 11); | |
6168 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
6169 | |
6170 | if (is_mov) | |
6171 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
6172 | else | |
6173 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
6174 | ||
7ff120b4 | 6175 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
6176 | |
6177 | return 0; | |
6178 | } | |
6179 | ||
6180 | /* Clean up load instructions. */ | |
6181 | ||
6182 | static void | |
6e39997a | 6183 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6184 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6185 | { |
6186 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 6187 | |
36073a92 | 6188 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 6189 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
6190 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
6191 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
6192 | |
6193 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6194 | if (dsc->u.ldst.xfersize > 4) | |
6195 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6196 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6197 | if (!dsc->u.ldst.immed) | |
6198 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6199 | ||
6200 | /* Handle register writeback. */ | |
6201 | if (dsc->u.ldst.writeback) | |
6202 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6203 | /* Put result in right place. */ | |
6204 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
6205 | if (dsc->u.ldst.xfersize == 8) | |
6206 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
6207 | } | |
6208 | ||
6209 | /* Clean up store instructions. */ | |
6210 | ||
6211 | static void | |
6e39997a | 6212 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6213 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6214 | { |
36073a92 | 6215 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
6216 | |
6217 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
6218 | if (dsc->u.ldst.xfersize > 4) | |
6219 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
6220 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
6221 | if (!dsc->u.ldst.immed) | |
6222 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
6223 | if (!dsc->u.ldst.restore_r4) | |
6224 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
6225 | ||
6226 | /* Writeback. */ | |
6227 | if (dsc->u.ldst.writeback) | |
6228 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
6229 | } | |
6230 | ||
6231 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
6232 | transfers, which have a different encoding to byte/word transfers. */ | |
6233 | ||
6234 | static int | |
550dc4e2 | 6235 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 6236 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6237 | { |
6238 | unsigned int op1 = bits (insn, 20, 24); | |
6239 | unsigned int op2 = bits (insn, 5, 6); | |
6240 | unsigned int rt = bits (insn, 12, 15); | |
6241 | unsigned int rn = bits (insn, 16, 19); | |
6242 | unsigned int rm = bits (insn, 0, 3); | |
6243 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
6244 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
6245 | int immed = (op1 & 0x4) != 0; | |
6246 | int opcode; | |
6247 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
6248 | |
6249 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 6250 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 6251 | |
136821d9 SM |
6252 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
6253 | unprivileged ? "unprivileged " : "", | |
6254 | (unsigned long) insn); | |
cca44b1b JB |
6255 | |
6256 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
6257 | ||
6258 | if (opcode < 0) | |
6259 | internal_error (__FILE__, __LINE__, | |
6260 | _("copy_extra_ld_st: instruction decode error")); | |
6261 | ||
36073a92 YQ |
6262 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6263 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
6264 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6265 | if (!immed) |
36073a92 | 6266 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6267 | |
36073a92 | 6268 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 6269 | if (bytesize[opcode] == 8) |
36073a92 YQ |
6270 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
6271 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6272 | if (!immed) |
36073a92 | 6273 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6274 | |
6275 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6276 | if (bytesize[opcode] == 8) | |
6277 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
6278 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6279 | if (!immed) | |
6280 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
6281 | ||
6282 | dsc->rd = rt; | |
6283 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
6284 | dsc->u.ldst.rn = rn; | |
6285 | dsc->u.ldst.immed = immed; | |
6286 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
6287 | dsc->u.ldst.restore_r4 = 0; | |
6288 | ||
6289 | if (immed) | |
6290 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
6291 | -> | |
6292 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
6293 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6294 | else | |
6295 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
6296 | -> | |
6297 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
6298 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6299 | ||
6300 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
6301 | ||
6302 | return 0; | |
6303 | } | |
6304 | ||
0f6f04ba | 6305 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 6306 | |
7ff120b4 | 6307 | static void |
0f6f04ba | 6308 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 6309 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
6310 | int immed, int writeback, int size, int usermode, |
6311 | int rt, int rm, int rn) | |
cca44b1b | 6312 | { |
cca44b1b | 6313 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 6314 | |
36073a92 YQ |
6315 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
6316 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 6317 | if (!immed) |
36073a92 | 6318 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 6319 | if (!load) |
36073a92 | 6320 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 6321 | |
36073a92 YQ |
6322 | rt_val = displaced_read_reg (regs, dsc, rt); |
6323 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6324 | if (!immed) |
36073a92 | 6325 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
6326 | |
6327 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
6328 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
6329 | if (!immed) | |
6330 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 6331 | dsc->rd = rt; |
0f6f04ba | 6332 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
6333 | dsc->u.ldst.rn = rn; |
6334 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 6335 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
6336 | |
6337 | /* To write PC we can do: | |
6338 | ||
494e194e YQ |
6339 | Before this sequence of instructions: |
6340 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 6341 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
6342 | |
6343 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
6344 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
6345 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
6346 | = addr(Insn1) + offset - addr(Insn3) - 8 |
6347 | = offset - 16 | |
494e194e YQ |
6348 | Insn4: add r4, r4, #8 r4 = offset - 8 |
6349 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 6350 | = from + offset |
494e194e | 6351 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
6352 | |
6353 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
6354 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
6355 | of this can be found in Section "Saving from r15" in | |
6356 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 6357 | |
7ff120b4 YQ |
6358 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
6359 | } | |
6360 | ||
34518530 YQ |
6361 | |
6362 | static int | |
6363 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
6364 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6365 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
6366 | { |
6367 | unsigned int u_bit = bit (insn1, 7); | |
6368 | unsigned int rt = bits (insn2, 12, 15); | |
6369 | int imm12 = bits (insn2, 0, 11); | |
6370 | ULONGEST pc_val; | |
6371 | ||
136821d9 SM |
6372 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
6373 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
6374 | imm12); | |
34518530 YQ |
6375 | |
6376 | if (!u_bit) | |
6377 | imm12 = -1 * imm12; | |
6378 | ||
6379 | /* Rewrite instruction LDR Rt imm12 into: | |
6380 | ||
6381 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
6382 | ||
6383 | LDR R0, R2, R3, | |
6384 | ||
6385 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
6386 | ||
6387 | ||
6388 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
6389 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
6390 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
6391 | ||
6392 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
6393 | ||
6394 | pc_val = pc_val & 0xfffffffc; | |
6395 | ||
6396 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
6397 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
6398 | ||
6399 | dsc->rd = rt; | |
6400 | ||
6401 | dsc->u.ldst.xfersize = size; | |
6402 | dsc->u.ldst.immed = 0; | |
6403 | dsc->u.ldst.writeback = 0; | |
6404 | dsc->u.ldst.restore_r4 = 0; | |
6405 | ||
6406 | /* LDR R0, R2, R3 */ | |
6407 | dsc->modinsn[0] = 0xf852; | |
6408 | dsc->modinsn[1] = 0x3; | |
6409 | dsc->numinsns = 2; | |
6410 | ||
6411 | dsc->cleanup = &cleanup_load; | |
6412 | ||
6413 | return 0; | |
6414 | } | |
6415 | ||
6416 | static int | |
6417 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
6418 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 6419 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
6420 | int writeback, int immed) |
6421 | { | |
6422 | unsigned int rt = bits (insn2, 12, 15); | |
6423 | unsigned int rn = bits (insn1, 0, 3); | |
6424 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
6425 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
6426 | be PC, so we don't have to check it. */ | |
6427 | ||
6428 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
6429 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
6430 | dsc); | |
6431 | ||
136821d9 SM |
6432 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
6433 | rt, rn, insn1, insn2); | |
34518530 YQ |
6434 | |
6435 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
6436 | 0, rt, rm, rn); | |
6437 | ||
6438 | dsc->u.ldst.restore_r4 = 0; | |
6439 | ||
6440 | if (immed) | |
6441 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
6442 | -> | |
6443 | ldr[b]<cond> r0, [r2, #imm]. */ | |
6444 | { | |
6445 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6446 | dsc->modinsn[1] = insn2 & 0x0fff; | |
6447 | } | |
6448 | else | |
6449 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
6450 | -> | |
6451 | ldr[b]<cond> r0, [r2, r3]. */ | |
6452 | { | |
6453 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
6454 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
6455 | } | |
6456 | ||
6457 | dsc->numinsns = 2; | |
6458 | ||
6459 | return 0; | |
6460 | } | |
6461 | ||
6462 | ||
7ff120b4 YQ |
6463 | static int |
6464 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
6465 | struct regcache *regs, | |
1152d984 | 6466 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 6467 | int load, int size, int usermode) |
7ff120b4 YQ |
6468 | { |
6469 | int immed = !bit (insn, 25); | |
6470 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
6471 | unsigned int rt = bits (insn, 12, 15); | |
6472 | unsigned int rn = bits (insn, 16, 19); | |
6473 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
6474 | ||
6475 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6476 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
6477 | ||
136821d9 SM |
6478 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
6479 | load ? (size == 1 ? "ldrb" : "ldr") | |
6480 | : (size == 1 ? "strb" : "str"), | |
6481 | usermode ? "t" : "", | |
6482 | rt, rn, | |
6483 | (unsigned long) insn); | |
7ff120b4 | 6484 | |
0f6f04ba YQ |
6485 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
6486 | usermode, rt, rm, rn); | |
7ff120b4 | 6487 | |
bf9f652a | 6488 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
6489 | { |
6490 | dsc->u.ldst.restore_r4 = 0; | |
6491 | ||
6492 | if (immed) | |
6493 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
6494 | -> | |
6495 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
6496 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6497 | else | |
6498 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
6499 | -> | |
6500 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
6501 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6502 | } | |
6503 | else | |
6504 | { | |
6505 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
6506 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
6507 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
6508 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
6509 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
6510 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
6511 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
6512 | ||
6513 | /* As above. */ | |
6514 | if (immed) | |
6515 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
6516 | else | |
6517 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
6518 | ||
cca44b1b JB |
6519 | dsc->numinsns = 6; |
6520 | } | |
6521 | ||
6522 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
6523 | ||
6524 | return 0; | |
6525 | } | |
6526 | ||
6527 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
6528 | unfortunate corner case: it's impossible to implement correctly by modifying | |
6529 | the instruction. The issue is as follows: we have an instruction, | |
6530 | ||
6531 | ldm rN, {r0-r15} | |
6532 | ||
6533 | which we must rewrite to avoid loading PC. A possible solution would be to | |
6534 | do the load in two halves, something like (with suitable cleanup | |
6535 | afterwards): | |
6536 | ||
6537 | mov r8, rN | |
6538 | ldm[id][ab] r8!, {r0-r7} | |
6539 | str r7, <temp> | |
6540 | ldm[id][ab] r8, {r7-r14} | |
6541 | <bkpt> | |
6542 | ||
6543 | but at present there's no suitable place for <temp>, since the scratch space | |
6544 | is overwritten before the cleanup routine is called. For now, we simply | |
6545 | emulate the instruction. */ | |
6546 | ||
6547 | static void | |
6548 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6549 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6550 | { |
cca44b1b JB |
6551 | int inc = dsc->u.block.increment; |
6552 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
6553 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
6554 | uint32_t regmask = dsc->u.block.regmask; | |
6555 | int regno = inc ? 0 : 15; | |
6556 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
6557 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
6558 | && (regmask & 0x8000) != 0; | |
36073a92 | 6559 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6560 | int do_transfer = condition_true (dsc->u.block.cond, status); |
6561 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6562 | ||
6563 | if (!do_transfer) | |
6564 | return; | |
6565 | ||
6566 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
6567 | sensible we can do here. Complain loudly. */ | |
6568 | if (exception_return) | |
6569 | error (_("Cannot single-step exception return")); | |
6570 | ||
6571 | /* We don't handle any stores here for now. */ | |
6572 | gdb_assert (dsc->u.block.load != 0); | |
6573 | ||
136821d9 SM |
6574 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
6575 | dsc->u.block.load ? "ldm" : "stm", | |
6576 | dsc->u.block.increment ? "inc" : "dec", | |
6577 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
6578 | |
6579 | while (regmask) | |
6580 | { | |
6581 | uint32_t memword; | |
6582 | ||
6583 | if (inc) | |
bf9f652a | 6584 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
6585 | regno++; |
6586 | else | |
6587 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
6588 | regno--; | |
6589 | ||
6590 | xfer_addr += bump_before; | |
6591 | ||
6592 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
6593 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
6594 | ||
6595 | xfer_addr += bump_after; | |
6596 | ||
6597 | regmask &= ~(1 << regno); | |
6598 | } | |
6599 | ||
6600 | if (dsc->u.block.writeback) | |
6601 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
6602 | CANNOT_WRITE_PC); | |
6603 | } | |
6604 | ||
6605 | /* Clean up an STM which included the PC in the register list. */ | |
6606 | ||
6607 | static void | |
6608 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6609 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6610 | { |
36073a92 | 6611 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 6612 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
6613 | CORE_ADDR pc_stored_at, transferred_regs |
6614 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
6615 | CORE_ADDR stm_insn_addr; |
6616 | uint32_t pc_val; | |
6617 | long offset; | |
6618 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6619 | ||
6620 | /* If condition code fails, there's nothing else to do. */ | |
6621 | if (!store_executed) | |
6622 | return; | |
6623 | ||
6624 | if (dsc->u.block.increment) | |
6625 | { | |
6626 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
6627 | ||
6628 | if (dsc->u.block.before) | |
6629 | pc_stored_at += 4; | |
6630 | } | |
6631 | else | |
6632 | { | |
6633 | pc_stored_at = dsc->u.block.xfer_addr; | |
6634 | ||
6635 | if (dsc->u.block.before) | |
6636 | pc_stored_at -= 4; | |
6637 | } | |
6638 | ||
6639 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
6640 | stm_insn_addr = dsc->scratch_base; | |
6641 | offset = pc_val - stm_insn_addr; | |
6642 | ||
136821d9 SM |
6643 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
6644 | offset); | |
cca44b1b JB |
6645 | |
6646 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
6647 | instruction. */ | |
6648 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
6649 | dsc->insn_addr + offset); | |
6650 | } | |
6651 | ||
6652 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
6653 | the registers in the transferred list into a contiguous range r0...rX (to | |
6654 | avoid loading PC directly and losing control of the debugged program), so we | |
6655 | must undo that here. */ | |
6656 | ||
6657 | static void | |
6e39997a | 6658 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 6659 | struct regcache *regs, |
1152d984 | 6660 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6661 | { |
36073a92 | 6662 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 6663 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 6664 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 6665 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
6666 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
6667 | ||
6668 | /* The method employed here will fail if the register list is fully populated | |
6669 | (we need to avoid loading PC directly). */ | |
6670 | gdb_assert (num_to_shuffle < 16); | |
6671 | ||
6672 | if (!load_executed) | |
6673 | return; | |
6674 | ||
6675 | clobbered = (1 << num_to_shuffle) - 1; | |
6676 | ||
6677 | while (num_to_shuffle > 0) | |
6678 | { | |
6679 | if ((mask & (1 << write_reg)) != 0) | |
6680 | { | |
6681 | unsigned int read_reg = num_to_shuffle - 1; | |
6682 | ||
6683 | if (read_reg != write_reg) | |
6684 | { | |
36073a92 | 6685 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 6686 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
6687 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
6688 | read_reg, write_reg); | |
cca44b1b | 6689 | } |
136821d9 SM |
6690 | else |
6691 | displaced_debug_printf ("LDM: register r%d already in the right " | |
6692 | "place", write_reg); | |
cca44b1b JB |
6693 | |
6694 | clobbered &= ~(1 << write_reg); | |
6695 | ||
6696 | num_to_shuffle--; | |
6697 | } | |
6698 | ||
6699 | write_reg--; | |
6700 | } | |
6701 | ||
6702 | /* Restore any registers we scribbled over. */ | |
6703 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6704 | { | |
6705 | if ((clobbered & (1 << write_reg)) != 0) | |
6706 | { | |
6707 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6708 | CANNOT_WRITE_PC); | |
136821d9 SM |
6709 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6710 | write_reg); | |
cca44b1b JB |
6711 | clobbered &= ~(1 << write_reg); |
6712 | } | |
6713 | } | |
6714 | ||
6715 | /* Perform register writeback manually. */ | |
6716 | if (dsc->u.block.writeback) | |
6717 | { | |
6718 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6719 | ||
6720 | if (dsc->u.block.increment) | |
6721 | new_rn_val += regs_loaded * 4; | |
6722 | else | |
6723 | new_rn_val -= regs_loaded * 4; | |
6724 | ||
6725 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6726 | CANNOT_WRITE_PC); | |
6727 | } | |
6728 | } | |
6729 | ||
6730 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6731 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6732 | ||
6733 | static int | |
7ff120b4 YQ |
6734 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6735 | struct regcache *regs, | |
1152d984 | 6736 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6737 | { |
6738 | int load = bit (insn, 20); | |
6739 | int user = bit (insn, 22); | |
6740 | int increment = bit (insn, 23); | |
6741 | int before = bit (insn, 24); | |
6742 | int writeback = bit (insn, 21); | |
6743 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6744 | |
0963b4bd MS |
6745 | /* Block transfers which don't mention PC can be run directly |
6746 | out-of-line. */ | |
bf9f652a | 6747 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 6748 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 6749 | |
bf9f652a | 6750 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 6751 | { |
0963b4bd MS |
6752 | warning (_("displaced: Unpredictable LDM or STM with " |
6753 | "base register r15")); | |
7ff120b4 | 6754 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
6755 | } |
6756 | ||
136821d9 SM |
6757 | displaced_debug_printf ("copying block transfer insn %.8lx", |
6758 | (unsigned long) insn); | |
cca44b1b | 6759 | |
36073a92 | 6760 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
6761 | dsc->u.block.rn = rn; |
6762 | ||
6763 | dsc->u.block.load = load; | |
6764 | dsc->u.block.user = user; | |
6765 | dsc->u.block.increment = increment; | |
6766 | dsc->u.block.before = before; | |
6767 | dsc->u.block.writeback = writeback; | |
6768 | dsc->u.block.cond = bits (insn, 28, 31); | |
6769 | ||
6770 | dsc->u.block.regmask = insn & 0xffff; | |
6771 | ||
6772 | if (load) | |
6773 | { | |
6774 | if ((insn & 0xffff) == 0xffff) | |
6775 | { | |
6776 | /* LDM with a fully-populated register list. This case is | |
6777 | particularly tricky. Implement for now by fully emulating the | |
6778 | instruction (which might not behave perfectly in all cases, but | |
6779 | these instructions should be rare enough for that not to matter | |
6780 | too much). */ | |
6781 | dsc->modinsn[0] = ARM_NOP; | |
6782 | ||
6783 | dsc->cleanup = &cleanup_block_load_all; | |
6784 | } | |
6785 | else | |
6786 | { | |
6787 | /* LDM of a list of registers which includes PC. Implement by | |
6788 | rewriting the list of registers to be transferred into a | |
6789 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
6790 | registers into the correct places in the cleanup routine. */ | |
6791 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 6792 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6793 | unsigned int i; |
cca44b1b JB |
6794 | |
6795 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 6796 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
6797 | |
6798 | /* Writeback makes things complicated. We need to avoid clobbering | |
6799 | the base register with one of the registers in our modified | |
6800 | register list, but just using a different register can't work in | |
6801 | all cases, e.g.: | |
6802 | ||
6803 | ldm r14!, {r0-r13,pc} | |
6804 | ||
6805 | which would need to be rewritten as: | |
6806 | ||
6807 | ldm rN!, {r0-r14} | |
6808 | ||
6809 | but that can't work, because there's no free register for N. | |
6810 | ||
6811 | Solve this by turning off the writeback bit, and emulating | |
6812 | writeback manually in the cleanup routine. */ | |
6813 | ||
6814 | if (writeback) | |
6815 | insn &= ~(1 << 21); | |
6816 | ||
6817 | new_regmask = (1 << num_in_list) - 1; | |
6818 | ||
136821d9 SM |
6819 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6820 | "%.4x, modified list %.4x", | |
6821 | rn, writeback ? "!" : "", | |
6822 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
6823 | |
6824 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6825 | ||
6826 | dsc->cleanup = &cleanup_block_load_pc; | |
6827 | } | |
6828 | } | |
6829 | else | |
6830 | { | |
6831 | /* STM of a list of registers which includes PC. Run the instruction | |
6832 | as-is, but out of line: this will store the wrong value for the PC, | |
6833 | so we must manually fix up the memory in the cleanup routine. | |
6834 | Doing things this way has the advantage that we can auto-detect | |
6835 | the offset of the PC write (which is architecture-dependent) in | |
6836 | the cleanup routine. */ | |
6837 | dsc->modinsn[0] = insn; | |
6838 | ||
6839 | dsc->cleanup = &cleanup_block_store_pc; | |
6840 | } | |
6841 | ||
6842 | return 0; | |
6843 | } | |
6844 | ||
34518530 YQ |
6845 | static int |
6846 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6847 | struct regcache *regs, | |
1152d984 | 6848 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6849 | { |
34518530 YQ |
6850 | int rn = bits (insn1, 0, 3); |
6851 | int load = bit (insn1, 4); | |
6852 | int writeback = bit (insn1, 5); | |
cca44b1b | 6853 | |
34518530 YQ |
6854 | /* Block transfers which don't mention PC can be run directly |
6855 | out-of-line. */ | |
6856 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
6857 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 6858 | |
34518530 YQ |
6859 | if (rn == ARM_PC_REGNUM) |
6860 | { | |
6861 | warning (_("displaced: Unpredictable LDM or STM with " | |
6862 | "base register r15")); | |
6863 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6864 | "unpredictable ldm/stm", dsc); | |
6865 | } | |
cca44b1b | 6866 | |
136821d9 SM |
6867 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
6868 | insn1, insn2); | |
cca44b1b | 6869 | |
34518530 YQ |
6870 | /* Clear bit 13, since it should be always zero. */ |
6871 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
6872 | dsc->u.block.rn = rn; | |
cca44b1b | 6873 | |
34518530 YQ |
6874 | dsc->u.block.load = load; |
6875 | dsc->u.block.user = 0; | |
6876 | dsc->u.block.increment = bit (insn1, 7); | |
6877 | dsc->u.block.before = bit (insn1, 8); | |
6878 | dsc->u.block.writeback = writeback; | |
6879 | dsc->u.block.cond = INST_AL; | |
6880 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6881 | |
34518530 YQ |
6882 | if (load) |
6883 | { | |
6884 | if (dsc->u.block.regmask == 0xffff) | |
6885 | { | |
6886 | /* This branch is impossible to happen. */ | |
6887 | gdb_assert (0); | |
6888 | } | |
6889 | else | |
6890 | { | |
6891 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 6892 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6893 | unsigned int i; |
34518530 YQ |
6894 | |
6895 | for (i = 0; i < num_in_list; i++) | |
6896 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
6897 | ||
6898 | if (writeback) | |
6899 | insn1 &= ~(1 << 5); | |
6900 | ||
6901 | new_regmask = (1 << num_in_list) - 1; | |
6902 | ||
136821d9 SM |
6903 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6904 | "%.4x, modified list %.4x", | |
6905 | rn, writeback ? "!" : "", | |
6906 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
6907 | |
6908 | dsc->modinsn[0] = insn1; | |
6909 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
6910 | dsc->numinsns = 2; | |
6911 | ||
6912 | dsc->cleanup = &cleanup_block_load_pc; | |
6913 | } | |
6914 | } | |
6915 | else | |
6916 | { | |
6917 | dsc->modinsn[0] = insn1; | |
6918 | dsc->modinsn[1] = insn2; | |
6919 | dsc->numinsns = 2; | |
6920 | dsc->cleanup = &cleanup_block_store_pc; | |
6921 | } | |
6922 | return 0; | |
6923 | } | |
6924 | ||
d9311bfa AT |
6925 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
6926 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
6927 | ||
6928 | ULONGEST | |
6929 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
6930 | int byte_order) | |
6931 | { | |
5f2dfcfd AT |
6932 | return read_memory_unsigned_integer (memaddr, len, |
6933 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
6934 | } |
6935 | ||
6936 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
6937 | ||
6938 | CORE_ADDR | |
6939 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
6940 | CORE_ADDR val) | |
6941 | { | |
ac7936df | 6942 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
6943 | } |
6944 | ||
6945 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
6946 | ||
e7cf25a8 | 6947 | static CORE_ADDR |
553cb527 | 6948 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 6949 | { |
d9311bfa AT |
6950 | return 0; |
6951 | } | |
6952 | ||
6953 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
6954 | ||
6955 | int | |
6956 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
6957 | { | |
6958 | return arm_is_thumb (self->regcache); | |
6959 | } | |
6960 | ||
6961 | /* single_step() is called just before we want to resume the inferior, | |
6962 | if we want to single-step it but there is no hardware or kernel | |
6963 | single-step support. We find the target of the coming instructions | |
6964 | and breakpoint them. */ | |
6965 | ||
a0ff9e1a | 6966 | std::vector<CORE_ADDR> |
f5ea389a | 6967 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 6968 | { |
ac7936df | 6969 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 6970 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
6971 | |
6972 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
6973 | &arm_get_next_pcs_ops, | |
6974 | gdbarch_byte_order (gdbarch), | |
6975 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 6976 | 0, |
d9311bfa AT |
6977 | regcache); |
6978 | ||
a0ff9e1a | 6979 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 6980 | |
a0ff9e1a SM |
6981 | for (CORE_ADDR &pc_ref : next_pcs) |
6982 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 6983 | |
93f9a11f | 6984 | return next_pcs; |
d9311bfa AT |
6985 | } |
6986 | ||
34518530 YQ |
6987 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
6988 | for Linux, where some SVC instructions must be treated specially. */ | |
6989 | ||
6990 | static void | |
6991 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6992 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6993 | { |
6994 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
6995 | ||
136821d9 SM |
6996 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
6997 | (unsigned long) resume_addr); | |
34518530 YQ |
6998 | |
6999 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
7000 | } | |
7001 | ||
7002 | ||
85102364 | 7003 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
7004 | |
7005 | static int | |
7006 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7007 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7008 | { |
7009 | /* Preparation: none. | |
7010 | Insn: unmodified svc. | |
7011 | Cleanup: pc <- insn_addr + insn_size. */ | |
7012 | ||
7013 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
7014 | instruction. */ | |
7015 | dsc->wrote_to_pc = 1; | |
7016 | ||
7017 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
7018 | if (dsc->u.svc.copy_svc_os) |
7019 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
7020 | else | |
7021 | { | |
7022 | dsc->cleanup = &cleanup_svc; | |
7023 | return 0; | |
7024 | } | |
34518530 YQ |
7025 | } |
7026 | ||
7027 | static int | |
7028 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 7029 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7030 | { |
7031 | ||
136821d9 SM |
7032 | displaced_debug_printf ("copying svc insn %.8lx", |
7033 | (unsigned long) insn); | |
34518530 YQ |
7034 | |
7035 | dsc->modinsn[0] = insn; | |
7036 | ||
7037 | return install_svc (gdbarch, regs, dsc); | |
7038 | } | |
7039 | ||
7040 | static int | |
7041 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 7042 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7043 | { |
7044 | ||
136821d9 | 7045 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 7046 | |
34518530 YQ |
7047 | dsc->modinsn[0] = insn; |
7048 | ||
7049 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
7050 | } |
7051 | ||
7052 | /* Copy undefined instructions. */ | |
7053 | ||
7054 | static int | |
7ff120b4 | 7055 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7056 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7057 | { |
136821d9 SM |
7058 | displaced_debug_printf ("copying undefined insn %.8lx", |
7059 | (unsigned long) insn); | |
cca44b1b JB |
7060 | |
7061 | dsc->modinsn[0] = insn; | |
7062 | ||
7063 | return 0; | |
7064 | } | |
7065 | ||
34518530 YQ |
7066 | static int |
7067 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 7068 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7069 | { |
7070 | ||
136821d9 SM |
7071 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
7072 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
7073 | |
7074 | dsc->modinsn[0] = insn1; | |
7075 | dsc->modinsn[1] = insn2; | |
7076 | dsc->numinsns = 2; | |
7077 | ||
7078 | return 0; | |
7079 | } | |
7080 | ||
cca44b1b JB |
7081 | /* Copy unpredictable instructions. */ |
7082 | ||
7083 | static int | |
7ff120b4 | 7084 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7085 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 7086 | { |
136821d9 SM |
7087 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
7088 | (unsigned long) insn); | |
cca44b1b JB |
7089 | |
7090 | dsc->modinsn[0] = insn; | |
7091 | ||
7092 | return 0; | |
7093 | } | |
7094 | ||
7095 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
7096 | the presentation in the ARM ARM. */ | |
7097 | ||
7098 | static int | |
7ff120b4 YQ |
7099 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
7100 | struct regcache *regs, | |
1152d984 | 7101 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7102 | { |
7103 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
7104 | unsigned int rn = bits (insn, 16, 19); | |
7105 | ||
2f924de6 | 7106 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 7107 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 7108 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 7109 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 7110 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 7111 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 7112 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
7113 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
7114 | dsc); | |
cca44b1b | 7115 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 7116 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7117 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 7118 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
7119 | else if ((op1 & 0x77) == 0x51) |
7120 | { | |
7121 | if (rn != 0xf) | |
7ff120b4 | 7122 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 7123 | else |
7ff120b4 | 7124 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7125 | } |
7126 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 7127 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
7128 | else if (op1 == 0x57) |
7129 | switch (op2) | |
7130 | { | |
7ff120b4 YQ |
7131 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
7132 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
7133 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
7134 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
7135 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
7136 | } |
7137 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 7138 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
7139 | else if ((op2 & 0x1) == 0x0) |
7140 | switch (op1 & ~0x80) | |
7141 | { | |
7142 | case 0x61: | |
7ff120b4 | 7143 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 7144 | case 0x65: |
7ff120b4 | 7145 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 7146 | case 0x71: case 0x75: |
dda83cd7 | 7147 | /* pld/pldw reg. */ |
7ff120b4 | 7148 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7149 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 7150 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 7151 | default: |
7ff120b4 | 7152 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7153 | } |
7154 | else | |
7ff120b4 | 7155 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
7156 | } |
7157 | ||
7158 | static int | |
7ff120b4 YQ |
7159 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
7160 | struct regcache *regs, | |
1152d984 | 7161 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7162 | { |
7163 | if (bit (insn, 27) == 0) | |
7ff120b4 | 7164 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7165 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
7166 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
7167 | { | |
7168 | case 0x0: case 0x2: | |
7ff120b4 | 7169 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
7170 | |
7171 | case 0x1: case 0x3: | |
7ff120b4 | 7172 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
7173 | |
7174 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 7175 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7176 | |
7177 | case 0x8: | |
7178 | switch ((insn & 0xe00000) >> 21) | |
7179 | { | |
7180 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
7181 | /* stc/stc2. */ | |
7ff120b4 | 7182 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7183 | |
7184 | case 0x2: | |
7ff120b4 | 7185 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
7186 | |
7187 | default: | |
7ff120b4 | 7188 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7189 | } |
7190 | ||
7191 | case 0x9: | |
7192 | { | |
7193 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
7194 | switch ((insn & 0xe00000) >> 21) | |
7195 | { | |
7196 | case 0x1: case 0x3: | |
7197 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
7198 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
7199 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
7200 | |
7201 | case 0x2: | |
7ff120b4 | 7202 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7203 | |
7204 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7205 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
7206 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
7207 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
7208 | |
7209 | default: | |
7ff120b4 | 7210 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7211 | } |
7212 | } | |
7213 | ||
7214 | case 0xa: | |
7ff120b4 | 7215 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
7216 | |
7217 | case 0xb: | |
7218 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 7219 | /* ldc/ldc2 lit. */ |
7ff120b4 | 7220 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7221 | else |
7ff120b4 | 7222 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7223 | |
7224 | case 0xc: | |
7225 | if (bit (insn, 4)) | |
7ff120b4 | 7226 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7227 | else |
7ff120b4 | 7228 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7229 | |
7230 | case 0xd: | |
7231 | if (bit (insn, 4)) | |
7ff120b4 | 7232 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7233 | else |
7ff120b4 | 7234 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7235 | |
7236 | default: | |
7ff120b4 | 7237 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7238 | } |
7239 | } | |
7240 | ||
7241 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
7242 | ||
7243 | static int | |
7ff120b4 YQ |
7244 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
7245 | struct regcache *regs, | |
1152d984 | 7246 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7247 | { |
7248 | unsigned int op2 = bits (insn, 4, 6); | |
7249 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
7250 | |
7251 | switch (op2) | |
7252 | { | |
7253 | case 0x0: | |
7ff120b4 | 7254 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
7255 | |
7256 | case 0x1: | |
7257 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 7258 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7259 | else if (op == 0x3) |
7ff120b4 | 7260 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 7261 | else |
7ff120b4 | 7262 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7263 | |
7264 | case 0x2: | |
7265 | if (op == 0x1) | |
dda83cd7 | 7266 | /* Not really supported. */ |
7ff120b4 | 7267 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 7268 | else |
7ff120b4 | 7269 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7270 | |
7271 | case 0x3: | |
7272 | if (op == 0x1) | |
7ff120b4 | 7273 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 7274 | regs, dsc); /* blx register. */ |
cca44b1b | 7275 | else |
7ff120b4 | 7276 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7277 | |
7278 | case 0x5: | |
7ff120b4 | 7279 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
7280 | |
7281 | case 0x7: | |
7282 | if (op == 0x1) | |
7ff120b4 | 7283 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 7284 | else if (op == 0x3) |
dda83cd7 | 7285 | /* Not really supported. */ |
7ff120b4 | 7286 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 7287 | /* Fall through. */ |
cca44b1b JB |
7288 | |
7289 | default: | |
7ff120b4 | 7290 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7291 | } |
7292 | } | |
7293 | ||
7294 | static int | |
7ff120b4 YQ |
7295 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
7296 | struct regcache *regs, | |
1152d984 | 7297 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7298 | { |
7299 | if (bit (insn, 25)) | |
7300 | switch (bits (insn, 20, 24)) | |
7301 | { | |
7302 | case 0x10: | |
7ff120b4 | 7303 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
7304 | |
7305 | case 0x14: | |
7ff120b4 | 7306 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
7307 | |
7308 | case 0x12: case 0x16: | |
7ff120b4 | 7309 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
7310 | |
7311 | default: | |
7ff120b4 | 7312 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7313 | } |
7314 | else | |
7315 | { | |
7316 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
7317 | ||
7318 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 7319 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7320 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 7321 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 7322 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 7323 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 7324 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 7325 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 7326 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 7327 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 7328 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 7329 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 7330 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 7331 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
7332 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
7333 | dsc); | |
cca44b1b JB |
7334 | } |
7335 | ||
7336 | /* Should be unreachable. */ | |
7337 | return 1; | |
7338 | } | |
7339 | ||
7340 | static int | |
7ff120b4 YQ |
7341 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
7342 | struct regcache *regs, | |
1152d984 | 7343 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7344 | { |
7345 | int a = bit (insn, 25), b = bit (insn, 4); | |
7346 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
7347 | |
7348 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
7349 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 7350 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
7351 | else if ((!a && (op1 & 0x17) == 0x02) |
7352 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 7353 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
7354 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
7355 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 7356 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
7357 | else if ((!a && (op1 & 0x17) == 0x03) |
7358 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 7359 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
7360 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
7361 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 7362 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
7363 | else if ((!a && (op1 & 0x17) == 0x06) |
7364 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 7365 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
7366 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
7367 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 7368 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
7369 | else if ((!a && (op1 & 0x17) == 0x07) |
7370 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 7371 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
7372 | |
7373 | /* Should be unreachable. */ | |
7374 | return 1; | |
7375 | } | |
7376 | ||
7377 | static int | |
7ff120b4 | 7378 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7379 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7380 | { |
7381 | switch (bits (insn, 20, 24)) | |
7382 | { | |
7383 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 7384 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
7385 | |
7386 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 7387 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
7388 | |
7389 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
7390 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 7391 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
7392 | "decode/pack/unpack/saturate/reverse", dsc); |
7393 | ||
7394 | case 0x18: | |
7395 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
7396 | { | |
7397 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 7398 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 7399 | else |
7ff120b4 | 7400 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
7401 | } |
7402 | else | |
7ff120b4 | 7403 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7404 | |
7405 | case 0x1a: case 0x1b: | |
7406 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7407 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 7408 | else |
7ff120b4 | 7409 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7410 | |
7411 | case 0x1c: case 0x1d: | |
7412 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
7413 | { | |
7414 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 7415 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 7416 | else |
7ff120b4 | 7417 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
7418 | } |
7419 | else | |
7ff120b4 | 7420 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7421 | |
7422 | case 0x1e: case 0x1f: | |
7423 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 7424 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 7425 | else |
7ff120b4 | 7426 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
7427 | } |
7428 | ||
7429 | /* Should be unreachable. */ | |
7430 | return 1; | |
7431 | } | |
7432 | ||
7433 | static int | |
615234c1 | 7434 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 7435 | struct regcache *regs, |
1152d984 | 7436 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7437 | { |
7438 | if (bit (insn, 25)) | |
7ff120b4 | 7439 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 7440 | else |
7ff120b4 | 7441 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7442 | } |
7443 | ||
7444 | static int | |
7ff120b4 YQ |
7445 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
7446 | struct regcache *regs, | |
1152d984 | 7447 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7448 | { |
7449 | unsigned int opcode = bits (insn, 20, 24); | |
7450 | ||
7451 | switch (opcode) | |
7452 | { | |
7453 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 7454 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
7455 | |
7456 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
7457 | case 0x12: case 0x16: | |
7ff120b4 | 7458 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
7459 | |
7460 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
7461 | case 0x13: case 0x17: | |
7ff120b4 | 7462 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
7463 | |
7464 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7465 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7466 | /* Note: no writeback for these instructions. Bit 25 will always be | |
7467 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 7468 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7469 | } |
7470 | ||
7471 | /* Should be unreachable. */ | |
7472 | return 1; | |
7473 | } | |
7474 | ||
34518530 YQ |
7475 | /* Decode shifted register instructions. */ |
7476 | ||
7477 | static int | |
7478 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
7479 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7480 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7481 | { |
7482 | /* PC is only allowed to be used in instruction MOV. */ | |
7483 | ||
7484 | unsigned int op = bits (insn1, 5, 8); | |
7485 | unsigned int rn = bits (insn1, 0, 3); | |
7486 | ||
7487 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
7488 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
7489 | else | |
7490 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7491 | "dp (shift reg)", dsc); | |
7492 | } | |
7493 | ||
7494 | ||
7495 | /* Decode extension register load/store. Exactly the same as | |
7496 | arm_decode_ext_reg_ld_st. */ | |
7497 | ||
7498 | static int | |
7499 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
7500 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7501 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7502 | { |
7503 | unsigned int opcode = bits (insn1, 4, 8); | |
7504 | ||
7505 | switch (opcode) | |
7506 | { | |
7507 | case 0x04: case 0x05: | |
7508 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7509 | "vfp/neon vmov", dsc); | |
7510 | ||
7511 | case 0x08: case 0x0c: /* 01x00 */ | |
7512 | case 0x0a: case 0x0e: /* 01x10 */ | |
7513 | case 0x12: case 0x16: /* 10x10 */ | |
7514 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7515 | "vfp/neon vstm/vpush", dsc); | |
7516 | ||
7517 | case 0x09: case 0x0d: /* 01x01 */ | |
7518 | case 0x0b: case 0x0f: /* 01x11 */ | |
7519 | case 0x13: case 0x17: /* 10x11 */ | |
7520 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7521 | "vfp/neon vldm/vpop", dsc); | |
7522 | ||
7523 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7524 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7525 | "vstr", dsc); | |
7526 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7527 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
7528 | } | |
7529 | ||
7530 | /* Should be unreachable. */ | |
7531 | return 1; | |
7532 | } | |
7533 | ||
cca44b1b | 7534 | static int |
12545665 | 7535 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7536 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7537 | { |
7538 | unsigned int op1 = bits (insn, 20, 25); | |
7539 | int op = bit (insn, 4); | |
7540 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
7541 | |
7542 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 7543 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7544 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
7545 | && (coproc & 0xe) != 0xa) | |
7546 | /* stc/stc2. */ | |
7ff120b4 | 7547 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7548 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
7549 | && (coproc & 0xe) != 0xa) | |
7550 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 7551 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7552 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 7553 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 7554 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 7555 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 7556 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7557 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 7558 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7559 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7560 | else if ((op1 & 0x30) == 0x20 && !op) |
7561 | { | |
7562 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 7563 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 7564 | else |
7ff120b4 | 7565 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7566 | } |
7567 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 7568 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 7569 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7570 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7571 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7572 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7573 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 7574 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 7575 | else |
7ff120b4 | 7576 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
7577 | } |
7578 | ||
34518530 YQ |
7579 | static int |
7580 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
7581 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7582 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7583 | { |
7584 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
7585 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
7586 | unsigned int bit_9 = bit (insn1, 9); | |
7587 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
7588 | |
7589 | if (bit_9 == 0) | |
7590 | { | |
7591 | if (bit_5_8 == 2) | |
7592 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7593 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
7594 | dsc); | |
7595 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
7596 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7597 | else | |
7598 | { | |
7599 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
7600 | if ((coproc & 0xe) == 0xa) | |
7601 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
7602 | dsc); | |
7603 | else /* coproc is not 101x. */ | |
7604 | { | |
7605 | if (bit_4 == 0) /* STC/STC2. */ | |
7606 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7607 | "stc/stc2", dsc); | |
405feb71 | 7608 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
7609 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
7610 | regs, dsc); | |
7611 | } | |
7612 | } | |
7613 | } | |
7614 | else | |
7615 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
7616 | ||
7617 | return 0; | |
7618 | } | |
7619 | ||
7620 | static void | |
7621 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7622 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
7623 | { |
7624 | /* ADR Rd, #imm | |
7625 | ||
7626 | Rewrite as: | |
7627 | ||
7628 | Preparation: Rd <- PC | |
7629 | Insn: ADD Rd, #imm | |
7630 | Cleanup: Null. | |
7631 | */ | |
7632 | ||
7633 | /* Rd <- PC */ | |
7634 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7635 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
7636 | } | |
7637 | ||
7638 | static int | |
7639 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7640 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
7641 | int rd, unsigned int imm) |
7642 | { | |
7643 | ||
7644 | /* Encoding T2: ADDS Rd, #imm */ | |
7645 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
7646 | ||
7647 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7648 | ||
7649 | return 0; | |
7650 | } | |
7651 | ||
7652 | static int | |
7653 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
7654 | struct regcache *regs, | |
1152d984 | 7655 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7656 | { |
7657 | unsigned int rd = bits (insn, 8, 10); | |
7658 | unsigned int imm8 = bits (insn, 0, 7); | |
7659 | ||
136821d9 SM |
7660 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
7661 | rd, imm8, insn); | |
34518530 YQ |
7662 | |
7663 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
7664 | } | |
7665 | ||
7666 | static int | |
7667 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
7668 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7669 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7670 | { |
7671 | unsigned int rd = bits (insn2, 8, 11); | |
7672 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
7673 | extract raw immediate encoding rather than computing immediate. When | |
7674 | generating ADD or SUB instruction, we can simply perform OR operation to | |
7675 | set immediate into ADD. */ | |
7676 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
7677 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
7678 | ||
136821d9 SM |
7679 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
7680 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
7681 | |
7682 | if (bit (insn1, 7)) /* Encoding T2 */ | |
7683 | { | |
7684 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
7685 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
7686 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7687 | } | |
7688 | else /* Encoding T3 */ | |
7689 | { | |
7690 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
7691 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
7692 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7693 | } | |
7694 | dsc->numinsns = 2; | |
7695 | ||
7696 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7697 | ||
7698 | return 0; | |
7699 | } | |
7700 | ||
7701 | static int | |
615234c1 | 7702 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7703 | struct regcache *regs, |
1152d984 | 7704 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7705 | { |
7706 | unsigned int rt = bits (insn1, 8, 10); | |
7707 | unsigned int pc; | |
7708 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7709 | |
7710 | /* LDR Rd, #imm8 | |
7711 | ||
7712 | Rwrite as: | |
7713 | ||
7714 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7715 | ||
7716 | Insn: LDR R0, [R2, R3]; | |
7717 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7718 | ||
136821d9 | 7719 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7720 | |
7721 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7722 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7723 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7724 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7725 | /* The assembler calculates the required value of the offset from the | |
7726 | Align(PC,4) value of this instruction to the label. */ | |
7727 | pc = pc & 0xfffffffc; | |
7728 | ||
7729 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7730 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7731 | ||
7732 | dsc->rd = rt; | |
7733 | dsc->u.ldst.xfersize = 4; | |
7734 | dsc->u.ldst.rn = 0; | |
7735 | dsc->u.ldst.immed = 0; | |
7736 | dsc->u.ldst.writeback = 0; | |
7737 | dsc->u.ldst.restore_r4 = 0; | |
7738 | ||
7739 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7740 | ||
7741 | dsc->cleanup = &cleanup_load; | |
7742 | ||
7743 | return 0; | |
7744 | } | |
7745 | ||
405feb71 | 7746 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
7747 | |
7748 | static int | |
7749 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
7750 | struct regcache *regs, | |
1152d984 | 7751 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7752 | { |
7753 | int non_zero = bit (insn1, 11); | |
7754 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
7755 | CORE_ADDR from = dsc->insn_addr; | |
7756 | int rn = bits (insn1, 0, 2); | |
7757 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
7758 | ||
7759 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
7760 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
7761 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
7762 | condition is false, let it be, cleanup_branch will do nothing. */ | |
7763 | if (dsc->u.branch.cond) | |
7764 | { | |
7765 | dsc->u.branch.cond = INST_AL; | |
7766 | dsc->u.branch.dest = from + 4 + imm5; | |
7767 | } | |
7768 | else | |
7769 | dsc->u.branch.dest = from + 2; | |
7770 | ||
7771 | dsc->u.branch.link = 0; | |
7772 | dsc->u.branch.exchange = 0; | |
7773 | ||
136821d9 SM |
7774 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
7775 | non_zero ? "cbnz" : "cbz", | |
7776 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
7777 | |
7778 | dsc->modinsn[0] = THUMB_NOP; | |
7779 | ||
7780 | dsc->cleanup = &cleanup_branch; | |
7781 | return 0; | |
7782 | } | |
7783 | ||
7784 | /* Copy Table Branch Byte/Halfword */ | |
7785 | static int | |
7786 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7787 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7788 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7789 | { |
7790 | ULONGEST rn_val, rm_val; | |
7791 | int is_tbh = bit (insn2, 4); | |
7792 | CORE_ADDR halfwords = 0; | |
7793 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7794 | ||
7795 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7796 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7797 | ||
7798 | if (is_tbh) | |
7799 | { | |
7800 | gdb_byte buf[2]; | |
7801 | ||
7802 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7803 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7804 | } | |
7805 | else | |
7806 | { | |
7807 | gdb_byte buf[1]; | |
7808 | ||
7809 | target_read_memory (rn_val + rm_val, buf, 1); | |
7810 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7811 | } | |
7812 | ||
136821d9 SM |
7813 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
7814 | is_tbh ? "tbh" : "tbb", | |
7815 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7816 | (unsigned int) halfwords); | |
34518530 YQ |
7817 | |
7818 | dsc->u.branch.cond = INST_AL; | |
7819 | dsc->u.branch.link = 0; | |
7820 | dsc->u.branch.exchange = 0; | |
7821 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7822 | ||
7823 | dsc->cleanup = &cleanup_branch; | |
7824 | ||
7825 | return 0; | |
7826 | } | |
7827 | ||
7828 | static void | |
7829 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7830 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7831 | { |
7832 | /* PC <- r7 */ | |
7833 | int val = displaced_read_reg (regs, dsc, 7); | |
7834 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7835 | ||
7836 | /* r7 <- r8 */ | |
7837 | val = displaced_read_reg (regs, dsc, 8); | |
7838 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7839 | ||
7840 | /* r8 <- tmp[0] */ | |
7841 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7842 | ||
7843 | } | |
7844 | ||
7845 | static int | |
615234c1 | 7846 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7847 | struct regcache *regs, |
1152d984 | 7848 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7849 | { |
7850 | dsc->u.block.regmask = insn1 & 0x00ff; | |
7851 | ||
7852 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
7853 | to : | |
7854 | ||
7855 | (1) register list is full, that is, r0-r7 are used. | |
7856 | Prepare: tmp[0] <- r8 | |
7857 | ||
7858 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
7859 | MOV r8, r7; Move value of r7 to r8; | |
7860 | POP {r7}; Store PC value into r7. | |
7861 | ||
7862 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
7863 | ||
7864 | (2) register list is not full, supposing there are N registers in | |
7865 | register list (except PC, 0 <= N <= 7). | |
7866 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
7867 | ||
7868 | POP {r0, r1, ...., rN}; | |
7869 | ||
7870 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
7871 | from tmp[] properly. | |
7872 | */ | |
136821d9 SM |
7873 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
7874 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
7875 | |
7876 | if (dsc->u.block.regmask == 0xff) | |
7877 | { | |
7878 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
7879 | ||
7880 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
7881 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
7882 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
7883 | ||
7884 | dsc->numinsns = 3; | |
7885 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
7886 | } | |
7887 | else | |
7888 | { | |
5f661e03 | 7889 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
7890 | unsigned int i; |
7891 | unsigned int new_regmask; | |
34518530 YQ |
7892 | |
7893 | for (i = 0; i < num_in_list + 1; i++) | |
7894 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7895 | ||
7896 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
7897 | ||
136821d9 SM |
7898 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
7899 | "modified list %.4x", | |
7900 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7901 | |
7902 | dsc->u.block.regmask |= 0x8000; | |
7903 | dsc->u.block.writeback = 0; | |
7904 | dsc->u.block.cond = INST_AL; | |
7905 | ||
7906 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
7907 | ||
7908 | dsc->cleanup = &cleanup_block_load_pc; | |
7909 | } | |
7910 | ||
7911 | return 0; | |
7912 | } | |
7913 | ||
7914 | static void | |
7915 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7916 | struct regcache *regs, | |
1152d984 | 7917 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7918 | { |
7919 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
7920 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
7921 | int err = 0; | |
7922 | ||
7923 | /* 16-bit thumb instructions. */ | |
7924 | switch (op_bit_12_15) | |
7925 | { | |
7926 | /* Shift (imme), add, subtract, move and compare. */ | |
7927 | case 0: case 1: case 2: case 3: | |
7928 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7929 | "shift/add/sub/mov/cmp", | |
7930 | dsc); | |
7931 | break; | |
7932 | case 4: | |
7933 | switch (op_bit_10_11) | |
7934 | { | |
7935 | case 0: /* Data-processing */ | |
7936 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7937 | "data-processing", | |
7938 | dsc); | |
7939 | break; | |
7940 | case 1: /* Special data instructions and branch and exchange. */ | |
7941 | { | |
7942 | unsigned short op = bits (insn1, 7, 9); | |
7943 | if (op == 6 || op == 7) /* BX or BLX */ | |
7944 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
7945 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
7946 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
7947 | else | |
7948 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
7949 | dsc); | |
7950 | } | |
7951 | break; | |
7952 | default: /* LDR (literal) */ | |
7953 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
7954 | } | |
7955 | break; | |
7956 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
7957 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
7958 | break; | |
7959 | case 10: | |
7960 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
7961 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
7962 | else /* Generate SP-relative address */ | |
7963 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
7964 | break; | |
7965 | case 11: /* Misc 16-bit instructions */ | |
7966 | { | |
7967 | switch (bits (insn1, 8, 11)) | |
7968 | { | |
7969 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
7970 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
7971 | break; | |
7972 | case 12: case 13: /* POP */ | |
7973 | if (bit (insn1, 8)) /* PC is in register list. */ | |
7974 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
7975 | else | |
7976 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
7977 | break; | |
7978 | case 15: /* If-Then, and hints */ | |
7979 | if (bits (insn1, 0, 3)) | |
7980 | /* If-Then makes up to four following instructions conditional. | |
7981 | IT instruction itself is not conditional, so handle it as a | |
7982 | common unmodified instruction. */ | |
7983 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
7984 | dsc); | |
7985 | else | |
7986 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
7987 | break; | |
7988 | default: | |
7989 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
7990 | } | |
7991 | } | |
7992 | break; | |
7993 | case 12: | |
7994 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
7995 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
7996 | else /* Load multiple registers */ | |
7997 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
7998 | break; | |
7999 | case 13: /* Conditional branch and supervisor call */ | |
8000 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
8001 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8002 | else | |
8003 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
8004 | break; | |
8005 | case 14: /* Unconditional branch */ | |
8006 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
8007 | break; | |
8008 | default: | |
8009 | err = 1; | |
8010 | } | |
8011 | ||
8012 | if (err) | |
8013 | internal_error (__FILE__, __LINE__, | |
8014 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
8015 | } | |
8016 | ||
8017 | static int | |
8018 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
8019 | uint16_t insn1, uint16_t insn2, | |
8020 | struct regcache *regs, | |
1152d984 | 8021 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8022 | { |
8023 | int rt = bits (insn2, 12, 15); | |
8024 | int rn = bits (insn1, 0, 3); | |
8025 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
8026 | |
8027 | switch (bits (insn1, 5, 6)) | |
8028 | { | |
8029 | case 0: /* Load byte and memory hints */ | |
8030 | if (rt == 0xf) /* PLD/PLI */ | |
8031 | { | |
8032 | if (rn == 0xf) | |
8033 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
8034 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
8035 | else | |
8036 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8037 | "pli/pld", dsc); | |
8038 | } | |
8039 | else | |
8040 | { | |
8041 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
8042 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8043 | 1); | |
8044 | else | |
8045 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8046 | "ldrb{reg, immediate}/ldrbt", | |
8047 | dsc); | |
8048 | } | |
8049 | ||
8050 | break; | |
8051 | case 1: /* Load halfword and memory hints. */ | |
8052 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
8053 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8054 | "pld/unalloc memhint", dsc); | |
8055 | else | |
8056 | { | |
8057 | if (rn == 0xf) | |
8058 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
8059 | 2); | |
8060 | else | |
8061 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8062 | "ldrh/ldrht", dsc); | |
8063 | } | |
8064 | break; | |
8065 | case 2: /* Load word */ | |
8066 | { | |
8067 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
8068 | ||
8069 | if (rn == 0xf) | |
8070 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
8071 | else if (op1 == 0x1) /* Encoding T3 */ | |
8072 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
8073 | 0, 1); | |
8074 | else /* op1 == 0x0 */ | |
8075 | { | |
8076 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
8077 | /* LDR (immediate) */ | |
8078 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8079 | dsc, bit (insn2, 8), 1); | |
8080 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
8081 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8082 | "ldrt", dsc); | |
8083 | else | |
8084 | /* LDR (register) */ | |
8085 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
8086 | dsc, 0, 0); | |
8087 | } | |
8088 | break; | |
8089 | } | |
8090 | default: | |
8091 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
8092 | break; | |
8093 | } | |
8094 | return 0; | |
8095 | } | |
8096 | ||
8097 | static void | |
8098 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
8099 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 8100 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
8101 | { |
8102 | int err = 0; | |
8103 | unsigned short op = bit (insn2, 15); | |
8104 | unsigned int op1 = bits (insn1, 11, 12); | |
8105 | ||
8106 | switch (op1) | |
8107 | { | |
8108 | case 1: | |
8109 | { | |
8110 | switch (bits (insn1, 9, 10)) | |
8111 | { | |
8112 | case 0: | |
8113 | if (bit (insn1, 6)) | |
8114 | { | |
405feb71 | 8115 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
8116 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
8117 | && bits (insn2, 5, 7) == 0) | |
8118 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
8119 | dsc); | |
8120 | else | |
8121 | /* PC is not allowed to use in load/store {dual, exclusive} | |
8122 | instructions. */ | |
8123 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8124 | "load/store dual/ex", dsc); | |
8125 | } | |
8126 | else /* load/store multiple */ | |
8127 | { | |
8128 | switch (bits (insn1, 7, 8)) | |
8129 | { | |
8130 | case 0: case 3: /* SRS, RFE */ | |
8131 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8132 | "srs/rfe", dsc); | |
8133 | break; | |
8134 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
8135 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
8136 | break; | |
8137 | } | |
8138 | } | |
8139 | break; | |
8140 | ||
8141 | case 1: | |
8142 | /* Data-processing (shift register). */ | |
8143 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
8144 | dsc); | |
8145 | break; | |
8146 | default: /* Coprocessor instructions. */ | |
8147 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8148 | break; | |
8149 | } | |
8150 | break; | |
8151 | } | |
8152 | case 2: /* op1 = 2 */ | |
8153 | if (op) /* Branch and misc control. */ | |
8154 | { | |
8155 | if (bit (insn2, 14) /* BLX/BL */ | |
8156 | || bit (insn2, 12) /* Unconditional branch */ | |
8157 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
8158 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
8159 | else | |
8160 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8161 | "misc ctrl", dsc); | |
8162 | } | |
8163 | else | |
8164 | { | |
8165 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
8166 | { | |
b926417a | 8167 | int dp_op = bits (insn1, 4, 8); |
34518530 | 8168 | int rn = bits (insn1, 0, 3); |
b926417a | 8169 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
8170 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
8171 | regs, dsc); | |
8172 | else | |
8173 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8174 | "dp/pb", dsc); | |
8175 | } | |
405feb71 | 8176 | else /* Data processing (modified immediate) */ |
34518530 YQ |
8177 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
8178 | "dp/mi", dsc); | |
8179 | } | |
8180 | break; | |
8181 | case 3: /* op1 = 3 */ | |
8182 | switch (bits (insn1, 9, 10)) | |
8183 | { | |
8184 | case 0: | |
8185 | if (bit (insn1, 4)) | |
8186 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
8187 | regs, dsc); | |
8188 | else /* NEON Load/Store and Store single data item */ | |
8189 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8190 | "neon elt/struct load/store", | |
8191 | dsc); | |
8192 | break; | |
8193 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
8194 | switch (bits (insn1, 7, 8)) | |
8195 | { | |
8196 | case 0: case 1: /* Data processing (register) */ | |
8197 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8198 | "dp(reg)", dsc); | |
8199 | break; | |
8200 | case 2: /* Multiply and absolute difference */ | |
8201 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8202 | "mul/mua/diff", dsc); | |
8203 | break; | |
8204 | case 3: /* Long multiply and divide */ | |
8205 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
8206 | "lmul/lmua", dsc); | |
8207 | break; | |
8208 | } | |
8209 | break; | |
8210 | default: /* Coprocessor instructions */ | |
8211 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
8212 | break; | |
8213 | } | |
8214 | break; | |
8215 | default: | |
8216 | err = 1; | |
8217 | } | |
8218 | ||
8219 | if (err) | |
8220 | internal_error (__FILE__, __LINE__, | |
8221 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
8222 | ||
8223 | } | |
8224 | ||
b434a28f YQ |
8225 | static void |
8226 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 8227 | struct regcache *regs, |
1152d984 | 8228 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 8229 | { |
34518530 YQ |
8230 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8231 | uint16_t insn1 | |
8232 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
8233 | ||
136821d9 SM |
8234 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
8235 | insn1, (unsigned long) from); | |
34518530 YQ |
8236 | |
8237 | dsc->is_thumb = 1; | |
8238 | dsc->insn_size = thumb_insn_size (insn1); | |
8239 | if (thumb_insn_size (insn1) == 4) | |
8240 | { | |
8241 | uint16_t insn2 | |
8242 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
8243 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
8244 | } | |
8245 | else | |
8246 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
8247 | } |
8248 | ||
cca44b1b | 8249 | void |
b434a28f YQ |
8250 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
8251 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 8252 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
8253 | { |
8254 | int err = 0; | |
b434a28f YQ |
8255 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
8256 | uint32_t insn; | |
cca44b1b JB |
8257 | |
8258 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
8259 | here and override below if/when necessary. */ | |
8260 | dsc->numinsns = 1; | |
8261 | dsc->insn_addr = from; | |
8262 | dsc->scratch_base = to; | |
8263 | dsc->cleanup = NULL; | |
8264 | dsc->wrote_to_pc = 0; | |
8265 | ||
b434a28f | 8266 | if (!displaced_in_arm_mode (regs)) |
12545665 | 8267 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 8268 | |
4db71c0b YQ |
8269 | dsc->is_thumb = 0; |
8270 | dsc->insn_size = 4; | |
b434a28f | 8271 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
8272 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
8273 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 8274 | |
cca44b1b | 8275 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 8276 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8277 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
8278 | { | |
8279 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 8280 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8281 | break; |
8282 | ||
8283 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 8284 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8285 | break; |
8286 | ||
8287 | case 0x7: | |
7ff120b4 | 8288 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
8289 | break; |
8290 | ||
8291 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 8292 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8293 | break; |
8294 | ||
8295 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 8296 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
8297 | break; |
8298 | } | |
8299 | ||
8300 | if (err) | |
8301 | internal_error (__FILE__, __LINE__, | |
8302 | _("arm_process_displaced_insn: Instruction decode error")); | |
8303 | } | |
8304 | ||
8305 | /* Actually set up the scratch space for a displaced instruction. */ | |
8306 | ||
8307 | void | |
8308 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
8309 | CORE_ADDR to, |
8310 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 8311 | { |
08106042 | 8312 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
4db71c0b | 8313 | unsigned int i, len, offset; |
cca44b1b | 8314 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 8315 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 8316 | const gdb_byte *bkp_insn; |
cca44b1b | 8317 | |
4db71c0b | 8318 | offset = 0; |
cca44b1b JB |
8319 | /* Poke modified instruction(s). */ |
8320 | for (i = 0; i < dsc->numinsns; i++) | |
8321 | { | |
136821d9 SM |
8322 | if (size == 4) |
8323 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
8324 | dsc->modinsn[i], (unsigned long) to + offset); | |
8325 | else if (size == 2) | |
8326 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
8327 | (unsigned short) dsc->modinsn[i], | |
8328 | (unsigned long) to + offset); | |
4db71c0b | 8329 | |
4db71c0b YQ |
8330 | write_memory_unsigned_integer (to + offset, size, |
8331 | byte_order_for_code, | |
cca44b1b | 8332 | dsc->modinsn[i]); |
4db71c0b YQ |
8333 | offset += size; |
8334 | } | |
8335 | ||
8336 | /* Choose the correct breakpoint instruction. */ | |
8337 | if (dsc->is_thumb) | |
8338 | { | |
8339 | bkp_insn = tdep->thumb_breakpoint; | |
8340 | len = tdep->thumb_breakpoint_size; | |
8341 | } | |
8342 | else | |
8343 | { | |
8344 | bkp_insn = tdep->arm_breakpoint; | |
8345 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
8346 | } |
8347 | ||
8348 | /* Put breakpoint afterwards. */ | |
4db71c0b | 8349 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 8350 | |
136821d9 SM |
8351 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
8352 | paddress (gdbarch, to)); | |
cca44b1b JB |
8353 | } |
8354 | ||
cca44b1b JB |
8355 | /* Entry point for cleaning things up after a displaced instruction has been |
8356 | single-stepped. */ | |
8357 | ||
8358 | void | |
8359 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 8360 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
8361 | CORE_ADDR from, CORE_ADDR to, |
8362 | struct regcache *regs) | |
8363 | { | |
1152d984 SM |
8364 | arm_displaced_step_copy_insn_closure *dsc |
8365 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 8366 | |
cca44b1b JB |
8367 | if (dsc->cleanup) |
8368 | dsc->cleanup (gdbarch, regs, dsc); | |
8369 | ||
8370 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
8371 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
8372 | dsc->insn_addr + dsc->insn_size); | |
8373 | ||
cca44b1b JB |
8374 | } |
8375 | ||
8376 | #include "bfd-in2.h" | |
8377 | #include "libcoff.h" | |
8378 | ||
8379 | static int | |
8380 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
8381 | { | |
f0c2e3e0 AB |
8382 | gdb_disassemble_info *di |
8383 | = static_cast<gdb_disassemble_info *> (info->application_data); | |
e47ad6c0 | 8384 | struct gdbarch *gdbarch = di->arch (); |
9779414d DJ |
8385 | |
8386 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
8387 | { |
8388 | static asymbol *asym; | |
8389 | static combined_entry_type ce; | |
8390 | static struct coff_symbol_struct csym; | |
8391 | static struct bfd fake_bfd; | |
8392 | static bfd_target fake_target; | |
8393 | ||
8394 | if (csym.native == NULL) | |
8395 | { | |
8396 | /* Create a fake symbol vector containing a Thumb symbol. | |
8397 | This is solely so that the code in print_insn_little_arm() | |
8398 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
8399 | the presence of a Thumb symbol and switch to decoding | |
8400 | Thumb instructions. */ | |
8401 | ||
8402 | fake_target.flavour = bfd_target_coff_flavour; | |
8403 | fake_bfd.xvec = &fake_target; | |
8404 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
8405 | csym.native = &ce; | |
8406 | csym.symbol.the_bfd = &fake_bfd; | |
8407 | csym.symbol.name = "fake"; | |
8408 | asym = (asymbol *) & csym; | |
8409 | } | |
8410 | ||
8411 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
8412 | info->symbols = &asym; | |
8413 | } | |
8414 | else | |
8415 | info->symbols = NULL; | |
8416 | ||
e60eb288 YQ |
8417 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
8418 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
8419 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
8420 | the assert on the mismatch of info->mach and |
8421 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
8422 | default_print_insn. */ | |
3047c786 TV |
8423 | if (current_program_space->exec_bfd () != NULL |
8424 | && (current_program_space->exec_bfd ()->arch_info | |
8425 | == gdbarch_bfd_arch_info (gdbarch))) | |
e60eb288 YQ |
8426 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
8427 | ||
6394c606 | 8428 | return default_print_insn (memaddr, info); |
cca44b1b JB |
8429 | } |
8430 | ||
8431 | /* The following define instruction sequences that will cause ARM | |
8432 | cpu's to take an undefined instruction trap. These are used to | |
8433 | signal a breakpoint to GDB. | |
8434 | ||
8435 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
8436 | modes. A different instruction is required for each mode. The ARM | |
8437 | cpu's can also be big or little endian. Thus four different | |
8438 | instructions are needed to support all cases. | |
8439 | ||
8440 | Note: ARMv4 defines several new instructions that will take the | |
8441 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
8442 | not in fact add the new instructions. The new undefined | |
8443 | instructions in ARMv4 are all instructions that had no defined | |
8444 | behaviour in earlier chips. There is no guarantee that they will | |
8445 | raise an exception, but may be treated as NOP's. In practice, it | |
8446 | may only safe to rely on instructions matching: | |
8447 | ||
8448 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
8449 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
8450 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
8451 | ||
0963b4bd | 8452 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
8453 | following use a condition predicate of ALWAYS so it is always TRUE. |
8454 | ||
8455 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
8456 | and NetBSD all use a software interrupt rather than an undefined | |
8457 | instruction to force a trap. This can be handled by by the | |
8458 | abi-specific code during establishment of the gdbarch vector. */ | |
8459 | ||
8460 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
8461 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
8462 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
8463 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
8464 | ||
948f8e3d PA |
8465 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
8466 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
8467 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
8468 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 8469 | |
cd6c3b4f YQ |
8470 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
8471 | ||
d19280ad YQ |
8472 | static int |
8473 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b | 8474 | { |
08106042 | 8475 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
177321bd | 8476 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 8477 | |
9779414d | 8478 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
8479 | { |
8480 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
8481 | |
8482 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
8483 | check whether we are replacing a 32-bit instruction. */ | |
8484 | if (tdep->thumb2_breakpoint != NULL) | |
8485 | { | |
8486 | gdb_byte buf[2]; | |
d19280ad | 8487 | |
177321bd DJ |
8488 | if (target_read_memory (*pcptr, buf, 2) == 0) |
8489 | { | |
8490 | unsigned short inst1; | |
d19280ad | 8491 | |
177321bd | 8492 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 8493 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 8494 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
8495 | } |
8496 | } | |
8497 | ||
d19280ad | 8498 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
8499 | } |
8500 | else | |
d19280ad YQ |
8501 | return ARM_BP_KIND_ARM; |
8502 | ||
8503 | } | |
8504 | ||
cd6c3b4f YQ |
8505 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
8506 | ||
d19280ad YQ |
8507 | static const gdb_byte * |
8508 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
8509 | { | |
08106042 | 8510 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
d19280ad YQ |
8511 | |
8512 | switch (kind) | |
cca44b1b | 8513 | { |
d19280ad YQ |
8514 | case ARM_BP_KIND_ARM: |
8515 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 8516 | return tdep->arm_breakpoint; |
d19280ad YQ |
8517 | case ARM_BP_KIND_THUMB: |
8518 | *size = tdep->thumb_breakpoint_size; | |
8519 | return tdep->thumb_breakpoint; | |
8520 | case ARM_BP_KIND_THUMB2: | |
8521 | *size = tdep->thumb2_breakpoint_size; | |
8522 | return tdep->thumb2_breakpoint; | |
8523 | default: | |
8524 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
8525 | } |
8526 | } | |
8527 | ||
833b7ab5 YQ |
8528 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
8529 | ||
8530 | static int | |
8531 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
8532 | struct regcache *regcache, | |
8533 | CORE_ADDR *pcptr) | |
8534 | { | |
8535 | gdb_byte buf[4]; | |
8536 | ||
8537 | /* Check the memory pointed by PC is readable. */ | |
8538 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
8539 | { | |
8540 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
8541 | |
8542 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
8543 | &arm_get_next_pcs_ops, | |
8544 | gdbarch_byte_order (gdbarch), | |
8545 | gdbarch_byte_order_for_code (gdbarch), | |
8546 | 0, | |
8547 | regcache); | |
8548 | ||
a0ff9e1a | 8549 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
8550 | |
8551 | /* If MEMADDR is the next instruction of current pc, do the | |
8552 | software single step computation, and get the thumb mode by | |
8553 | the destination address. */ | |
a0ff9e1a | 8554 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
8555 | { |
8556 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
8557 | { | |
833b7ab5 YQ |
8558 | if (IS_THUMB_ADDR (pc)) |
8559 | { | |
8560 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
8561 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8562 | } | |
8563 | else | |
8564 | return ARM_BP_KIND_ARM; | |
8565 | } | |
8566 | } | |
833b7ab5 YQ |
8567 | } |
8568 | ||
8569 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8570 | } | |
8571 | ||
cca44b1b JB |
8572 | /* Extract from an array REGBUF containing the (raw) register state a |
8573 | function return value of type TYPE, and copy that, in virtual | |
8574 | format, into VALBUF. */ | |
8575 | ||
8576 | static void | |
8577 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
8578 | gdb_byte *valbuf) | |
8579 | { | |
ac7936df | 8580 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b | 8581 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 8582 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
cca44b1b | 8583 | |
78134374 | 8584 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b | 8585 | { |
345bd07c | 8586 | switch (tdep->fp_model) |
cca44b1b JB |
8587 | { |
8588 | case ARM_FLOAT_FPA: | |
8589 | { | |
8590 | /* The value is in register F0 in internal format. We need to | |
8591 | extract the raw value and then convert it to the desired | |
8592 | internal type. */ | |
f0452268 | 8593 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 8594 | |
dca08e1f | 8595 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
8596 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
8597 | valbuf, type); | |
cca44b1b JB |
8598 | } |
8599 | break; | |
8600 | ||
8601 | case ARM_FLOAT_SOFT_FPA: | |
8602 | case ARM_FLOAT_SOFT_VFP: | |
8603 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
8604 | not using the VFP ABI code. */ | |
8605 | case ARM_FLOAT_VFP: | |
dca08e1f | 8606 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
cca44b1b | 8607 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8608 | regs->cooked_read (ARM_A1_REGNUM + 1, |
8609 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
8610 | break; |
8611 | ||
8612 | default: | |
0963b4bd MS |
8613 | internal_error (__FILE__, __LINE__, |
8614 | _("arm_extract_return_value: " | |
8615 | "Floating point model not supported")); | |
cca44b1b JB |
8616 | break; |
8617 | } | |
8618 | } | |
78134374 SM |
8619 | else if (type->code () == TYPE_CODE_INT |
8620 | || type->code () == TYPE_CODE_CHAR | |
8621 | || type->code () == TYPE_CODE_BOOL | |
8622 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8623 | || TYPE_IS_REFERENCE (type) |
a6617193 JB |
8624 | || type->code () == TYPE_CODE_ENUM |
8625 | || is_fixed_point_type (type)) | |
cca44b1b | 8626 | { |
b021a221 MS |
8627 | /* If the type is a plain integer, then the access is |
8628 | straight-forward. Otherwise we have to play around a bit | |
8629 | more. */ | |
cca44b1b JB |
8630 | int len = TYPE_LENGTH (type); |
8631 | int regno = ARM_A1_REGNUM; | |
8632 | ULONGEST tmp; | |
8633 | ||
8634 | while (len > 0) | |
8635 | { | |
8636 | /* By using store_unsigned_integer we avoid having to do | |
8637 | anything special for small big-endian values. */ | |
8638 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
8639 | store_unsigned_integer (valbuf, | |
f0452268 AH |
8640 | (len > ARM_INT_REGISTER_SIZE |
8641 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 8642 | byte_order, tmp); |
f0452268 AH |
8643 | len -= ARM_INT_REGISTER_SIZE; |
8644 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8645 | } |
8646 | } | |
8647 | else | |
8648 | { | |
8649 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8650 | been stored to word-aligned memory and then loaded into |
8651 | registers with 32-bit load instruction(s). */ | |
cca44b1b JB |
8652 | int len = TYPE_LENGTH (type); |
8653 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8654 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
8655 | |
8656 | while (len > 0) | |
8657 | { | |
dca08e1f | 8658 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 8659 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
8660 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
8661 | len -= ARM_INT_REGISTER_SIZE; | |
8662 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8663 | } |
8664 | } | |
8665 | } | |
8666 | ||
8667 | ||
8668 | /* Will a function return an aggregate type in memory or in a | |
8669 | register? Return 0 if an aggregate type can be returned in a | |
8670 | register, 1 if it must be returned in memory. */ | |
8671 | ||
8672 | static int | |
8673 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
8674 | { | |
cca44b1b JB |
8675 | enum type_code code; |
8676 | ||
f168693b | 8677 | type = check_typedef (type); |
cca44b1b | 8678 | |
b13c8ab2 YQ |
8679 | /* Simple, non-aggregate types (ie not including vectors and |
8680 | complex) are always returned in a register (or registers). */ | |
78134374 | 8681 | code = type->code (); |
b13c8ab2 YQ |
8682 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
8683 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
8684 | return 0; | |
cca44b1b | 8685 | |
bd63c870 | 8686 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
8687 | { |
8688 | /* Vector values should be returned using ARM registers if they | |
8689 | are not over 16 bytes. */ | |
8690 | return (TYPE_LENGTH (type) > 16); | |
8691 | } | |
8692 | ||
08106042 | 8693 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c | 8694 | if (tdep->arm_abi != ARM_ABI_APCS) |
cca44b1b | 8695 | { |
b13c8ab2 YQ |
8696 | /* The AAPCS says all aggregates not larger than a word are returned |
8697 | in a register. */ | |
bab22d06 LM |
8698 | if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE |
8699 | && language_pass_by_reference (type).trivially_copyable) | |
b13c8ab2 YQ |
8700 | return 0; |
8701 | ||
cca44b1b JB |
8702 | return 1; |
8703 | } | |
b13c8ab2 YQ |
8704 | else |
8705 | { | |
8706 | int nRc; | |
cca44b1b | 8707 | |
b13c8ab2 YQ |
8708 | /* All aggregate types that won't fit in a register must be returned |
8709 | in memory. */ | |
bab22d06 LM |
8710 | if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE |
8711 | || !language_pass_by_reference (type).trivially_copyable) | |
b13c8ab2 | 8712 | return 1; |
cca44b1b | 8713 | |
b13c8ab2 YQ |
8714 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8715 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8716 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8717 | offset of each addressable subfield must be zero. Note that bit |
8718 | fields are not addressable, and all addressable subfields of | |
8719 | unions always start at offset zero. | |
cca44b1b | 8720 | |
b13c8ab2 YQ |
8721 | This function is based on the behaviour of GCC 2.95.1. |
8722 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8723 | |
b13c8ab2 YQ |
8724 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8725 | parameters correctly for a function returning the following | |
8726 | structure: struct { float f;}; This should be returned in memory, | |
8727 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8728 | know of any way to detect if a function like the above has been | |
8729 | compiled with the correct calling convention. */ | |
8730 | ||
8731 | /* Assume all other aggregate types can be returned in a register. | |
8732 | Run a check for structures, unions and arrays. */ | |
8733 | nRc = 0; | |
67255d04 | 8734 | |
b13c8ab2 YQ |
8735 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8736 | { | |
8737 | int i; | |
8738 | /* Need to check if this struct/union is "integer" like. For | |
8739 | this to be true, its size must be less than or equal to | |
f0452268 | 8740 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8741 | subfield must be zero. Note that bit fields are not |
8742 | addressable, and unions always start at offset zero. If any | |
8743 | of the subfields is a floating point type, the struct/union | |
8744 | cannot be an integer type. */ | |
8745 | ||
8746 | /* For each field in the object, check: | |
8747 | 1) Is it FP? --> yes, nRc = 1; | |
8748 | 2) Is it addressable (bitpos != 0) and | |
8749 | not packed (bitsize == 0)? | |
8750 | --> yes, nRc = 1 | |
8751 | */ | |
8752 | ||
1f704f76 | 8753 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 8754 | { |
b13c8ab2 YQ |
8755 | enum type_code field_type_code; |
8756 | ||
8757 | field_type_code | |
940da03e | 8758 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
8759 | |
8760 | /* Is it a floating point type field? */ | |
8761 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
8762 | { |
8763 | nRc = 1; | |
8764 | break; | |
8765 | } | |
b13c8ab2 YQ |
8766 | |
8767 | /* If bitpos != 0, then we have to care about it. */ | |
b610c045 | 8768 | if (type->field (i).loc_bitpos () != 0) |
b13c8ab2 YQ |
8769 | { |
8770 | /* Bitfields are not addressable. If the field bitsize is | |
8771 | zero, then the field is not packed. Hence it cannot be | |
8772 | a bitfield or any other packed type. */ | |
8773 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
8774 | { | |
8775 | nRc = 1; | |
8776 | break; | |
8777 | } | |
8778 | } | |
67255d04 RE |
8779 | } |
8780 | } | |
67255d04 | 8781 | |
b13c8ab2 YQ |
8782 | return nRc; |
8783 | } | |
67255d04 RE |
8784 | } |
8785 | ||
34e8f22d RE |
8786 | /* Write into appropriate registers a function return value of type |
8787 | TYPE, given in virtual format. */ | |
8788 | ||
8789 | static void | |
b508a996 | 8790 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 8791 | const gdb_byte *valbuf) |
34e8f22d | 8792 | { |
ac7936df | 8793 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 8794 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 8795 | |
78134374 | 8796 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 8797 | { |
f0452268 | 8798 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
08106042 | 8799 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
34e8f22d | 8800 | |
345bd07c | 8801 | switch (tdep->fp_model) |
08216dd7 RE |
8802 | { |
8803 | case ARM_FLOAT_FPA: | |
8804 | ||
3b2ca824 | 8805 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 8806 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
8807 | break; |
8808 | ||
fd50bc42 | 8809 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8810 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8811 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8812 | not using the VFP ABI code. */ | |
8813 | case ARM_FLOAT_VFP: | |
b66f5587 | 8814 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
b508a996 | 8815 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8816 | regs->cooked_write (ARM_A1_REGNUM + 1, |
8817 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
8818 | break; |
8819 | ||
8820 | default: | |
9b20d036 MS |
8821 | internal_error (__FILE__, __LINE__, |
8822 | _("arm_store_return_value: Floating " | |
8823 | "point model not supported")); | |
08216dd7 RE |
8824 | break; |
8825 | } | |
34e8f22d | 8826 | } |
78134374 SM |
8827 | else if (type->code () == TYPE_CODE_INT |
8828 | || type->code () == TYPE_CODE_CHAR | |
8829 | || type->code () == TYPE_CODE_BOOL | |
8830 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8831 | || TYPE_IS_REFERENCE (type) |
78134374 | 8832 | || type->code () == TYPE_CODE_ENUM) |
b508a996 RE |
8833 | { |
8834 | if (TYPE_LENGTH (type) <= 4) | |
8835 | { | |
8836 | /* Values of one word or less are zero/sign-extended and | |
8837 | returned in r0. */ | |
f0452268 | 8838 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8839 | LONGEST val = unpack_long (type, valbuf); |
8840 | ||
f0452268 | 8841 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 8842 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
8843 | } |
8844 | else | |
8845 | { | |
8846 | /* Integral values greater than one word are stored in consecutive | |
8847 | registers starting with r0. This will always be a multiple of | |
8848 | the regiser size. */ | |
8849 | int len = TYPE_LENGTH (type); | |
8850 | int regno = ARM_A1_REGNUM; | |
8851 | ||
8852 | while (len > 0) | |
8853 | { | |
b66f5587 | 8854 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
8855 | len -= ARM_INT_REGISTER_SIZE; |
8856 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8857 | } |
8858 | } | |
8859 | } | |
34e8f22d | 8860 | else |
b508a996 RE |
8861 | { |
8862 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8863 | been stored to word-aligned memory and then loaded into |
8864 | registers with 32-bit load instruction(s). */ | |
b508a996 RE |
8865 | int len = TYPE_LENGTH (type); |
8866 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8867 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8868 | |
8869 | while (len > 0) | |
8870 | { | |
8871 | memcpy (tmpbuf, valbuf, | |
f0452268 | 8872 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 8873 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
8874 | len -= ARM_INT_REGISTER_SIZE; |
8875 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8876 | } |
8877 | } | |
34e8f22d RE |
8878 | } |
8879 | ||
2af48f68 PB |
8880 | |
8881 | /* Handle function return values. */ | |
8882 | ||
8883 | static enum return_value_convention | |
6a3a010b | 8884 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
8885 | struct type *valtype, struct regcache *regcache, |
8886 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 8887 | { |
08106042 | 8888 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
6a3a010b | 8889 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
8890 | enum arm_vfp_cprc_base_type vfp_base_type; |
8891 | int vfp_base_count; | |
8892 | ||
8893 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
8894 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
8895 | { | |
8896 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
8897 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
8898 | int i; | |
8899 | for (i = 0; i < vfp_base_count; i++) | |
8900 | { | |
58d6951d DJ |
8901 | if (reg_char == 'q') |
8902 | { | |
8903 | if (writebuf) | |
8904 | arm_neon_quad_write (gdbarch, regcache, i, | |
8905 | writebuf + i * unit_length); | |
8906 | ||
8907 | if (readbuf) | |
8908 | arm_neon_quad_read (gdbarch, regcache, i, | |
8909 | readbuf + i * unit_length); | |
8910 | } | |
8911 | else | |
8912 | { | |
8913 | char name_buf[4]; | |
8914 | int regnum; | |
8915 | ||
8c042590 | 8916 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
8917 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8918 | strlen (name_buf)); | |
8919 | if (writebuf) | |
b66f5587 | 8920 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 8921 | if (readbuf) |
dca08e1f | 8922 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 8923 | } |
90445bd3 DJ |
8924 | } |
8925 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8926 | } | |
7c00367c | 8927 | |
78134374 SM |
8928 | if (valtype->code () == TYPE_CODE_STRUCT |
8929 | || valtype->code () == TYPE_CODE_UNION | |
8930 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 8931 | { |
bab22d06 LM |
8932 | /* From the AAPCS document: |
8933 | ||
8934 | Result return: | |
8935 | ||
8936 | A Composite Type larger than 4 bytes, or whose size cannot be | |
8937 | determined statically by both caller and callee, is stored in memory | |
8938 | at an address passed as an extra argument when the function was | |
8939 | called (Parameter Passing, rule A.4). The memory to be used for the | |
8940 | result may be modified at any point during the function call. | |
8941 | ||
8942 | Parameter Passing: | |
8943 | ||
8944 | A.4: If the subroutine is a function that returns a result in memory, | |
8945 | then the address for the result is placed in r0 and the NCRN is set | |
8946 | to r1. */ | |
7c00367c MK |
8947 | if (tdep->struct_return == pcc_struct_return |
8948 | || arm_return_in_memory (gdbarch, valtype)) | |
bab22d06 LM |
8949 | { |
8950 | if (readbuf) | |
8951 | { | |
8952 | CORE_ADDR addr; | |
8953 | ||
8954 | regcache->cooked_read (ARM_A1_REGNUM, &addr); | |
8955 | read_memory (addr, readbuf, TYPE_LENGTH (valtype)); | |
8956 | } | |
8957 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
8958 | } | |
2af48f68 | 8959 | } |
78134374 | 8960 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
8961 | { |
8962 | if (arm_return_in_memory (gdbarch, valtype)) | |
8963 | return RETURN_VALUE_STRUCT_CONVENTION; | |
8964 | } | |
7052e42c | 8965 | |
2af48f68 PB |
8966 | if (writebuf) |
8967 | arm_store_return_value (valtype, regcache, writebuf); | |
8968 | ||
8969 | if (readbuf) | |
8970 | arm_extract_return_value (valtype, regcache, readbuf); | |
8971 | ||
8972 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8973 | } | |
8974 | ||
8975 | ||
9df628e0 | 8976 | static int |
60ade65d | 8977 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 8978 | { |
e17a4113 | 8979 | struct gdbarch *gdbarch = get_frame_arch (frame); |
08106042 | 8980 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
e17a4113 | 8981 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9df628e0 | 8982 | CORE_ADDR jb_addr; |
f0452268 | 8983 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 8984 | |
60ade65d | 8985 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
8986 | |
8987 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 8988 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
8989 | return 0; |
8990 | ||
f0452268 | 8991 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
8992 | return 1; |
8993 | } | |
40eadf04 SP |
8994 | /* A call to cmse secure entry function "foo" at "a" is modified by |
8995 | GNU ld as "b". | |
8996 | a) bl xxxx <foo> | |
8997 | ||
8998 | <foo> | |
8999 | xxxx: | |
9000 | ||
9001 | b) bl yyyy <__acle_se_foo> | |
9002 | ||
9003 | section .gnu.sgstubs: | |
9004 | <foo> | |
9005 | yyyy: sg // secure gateway | |
9006 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
9007 | ||
9008 | <__acle_se_foo> | |
9009 | xxxx: | |
9010 | ||
9011 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
9012 | trampoline and does not exist in source code. This function returns the | |
9013 | target pc "xxxx". For more details please refer to section 5.4 | |
9014 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
9015 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
9016 | document on www.developer.arm.com. */ | |
9017 | ||
9018 | static CORE_ADDR | |
9019 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
9020 | { | |
9021 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
9022 | char *target_name = (char *) alloca (target_len); | |
9023 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
9024 | ||
9025 | struct bound_minimal_symbol minsym | |
9026 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
9027 | ||
9028 | if (minsym.minsym != nullptr) | |
4aeddc50 | 9029 | return minsym.value_address (); |
40eadf04 SP |
9030 | |
9031 | return 0; | |
9032 | } | |
9033 | ||
9034 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
9035 | ||
9036 | static bool | |
9037 | arm_is_sgstubs_section (struct obj_section *sec) | |
9038 | { | |
9039 | return (sec != nullptr | |
9040 | && sec->the_bfd_section != nullptr | |
9041 | && sec->the_bfd_section->name != nullptr | |
9042 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
9043 | } | |
9df628e0 | 9044 | |
faa95490 DJ |
9045 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
9046 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
9047 | |
9048 | CORE_ADDR | |
52f729a7 | 9049 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 9050 | { |
2c02bd72 | 9051 | const char *name; |
faa95490 | 9052 | int namelen; |
c906108c SS |
9053 | CORE_ADDR start_addr; |
9054 | ||
9055 | /* Find the starting address and name of the function containing the PC. */ | |
9056 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
9057 | { |
9058 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
9059 | check here. */ | |
9060 | start_addr = arm_skip_bx_reg (frame, pc); | |
9061 | if (start_addr != 0) | |
9062 | return start_addr; | |
9063 | ||
9064 | return 0; | |
9065 | } | |
c906108c | 9066 | |
faa95490 DJ |
9067 | /* If PC is in a Thumb call or return stub, return the address of the |
9068 | target PC, which is in a register. The thunk functions are called | |
9069 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
9070 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
9071 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
9072 | if (startswith (name, "_call_via_") |
9073 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 9074 | { |
ed9a39eb | 9075 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 9076 | target PC. */ |
a121b7c1 | 9077 | static const char *table[15] = |
c5aa993b JM |
9078 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
9079 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
9080 | }; | |
c906108c | 9081 | int regno; |
faa95490 | 9082 | int offset = strlen (name) - 2; |
c906108c SS |
9083 | |
9084 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 9085 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 9086 | return get_frame_register_unsigned (frame, regno); |
c906108c | 9087 | } |
ed9a39eb | 9088 | |
faa95490 DJ |
9089 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
9090 | non-interworking calls to foo. We could decode the stubs | |
9091 | to find the target but it's easier to use the symbol table. */ | |
9092 | namelen = strlen (name); | |
9093 | if (name[0] == '_' && name[1] == '_' | |
9094 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 9095 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 9096 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 9097 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
9098 | { |
9099 | char *target_name; | |
9100 | int target_len = namelen - 2; | |
3b7344d5 | 9101 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
9102 | struct objfile *objfile; |
9103 | struct obj_section *sec; | |
9104 | ||
9105 | if (name[namelen - 1] == 'b') | |
9106 | target_len -= strlen ("_from_thumb"); | |
9107 | else | |
9108 | target_len -= strlen ("_from_arm"); | |
9109 | ||
224c3ddb | 9110 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
9111 | memcpy (target_name, name + 2, target_len); |
9112 | target_name[target_len] = '\0'; | |
9113 | ||
9114 | sec = find_pc_section (pc); | |
9115 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
9116 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 9117 | if (minsym.minsym != NULL) |
4aeddc50 | 9118 | return minsym.value_address (); |
faa95490 DJ |
9119 | else |
9120 | return 0; | |
9121 | } | |
9122 | ||
40eadf04 SP |
9123 | struct obj_section *section = find_pc_section (pc); |
9124 | ||
9125 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
9126 | if (arm_is_sgstubs_section (section)) | |
9127 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
9128 | ||
c5aa993b | 9129 | return 0; /* not a stub */ |
c906108c SS |
9130 | } |
9131 | ||
28e97307 DJ |
9132 | static void |
9133 | arm_update_current_architecture (void) | |
fd50bc42 | 9134 | { |
28e97307 | 9135 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 9136 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 9137 | return; |
fd50bc42 | 9138 | |
28e97307 | 9139 | /* Update the architecture. */ |
b447dd03 | 9140 | gdbarch_info info; |
28e97307 | 9141 | if (!gdbarch_update_p (info)) |
9b20d036 | 9142 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
9143 | } |
9144 | ||
9145 | static void | |
eb4c3f4a | 9146 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
9147 | struct cmd_list_element *c) |
9148 | { | |
570dc176 | 9149 | int fp_model; |
fd50bc42 RE |
9150 | |
9151 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
9152 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
9153 | { | |
aead7601 | 9154 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
9155 | break; |
9156 | } | |
9157 | ||
9158 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 9159 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
9160 | current_fp_model); |
9161 | ||
28e97307 | 9162 | arm_update_current_architecture (); |
fd50bc42 RE |
9163 | } |
9164 | ||
9165 | static void | |
08546159 AC |
9166 | show_fp_model (struct ui_file *file, int from_tty, |
9167 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 9168 | { |
28e97307 | 9169 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 9170 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9171 | { |
9172 | arm_gdbarch_tdep *tdep | |
08106042 | 9173 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9174 | |
9175 | gdb_printf (file, _("\ | |
28e97307 | 9176 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9177 | fp_model_strings[tdep->fp_model]); |
9178 | } | |
28e97307 | 9179 | else |
6cb06a8c | 9180 | gdb_printf (file, _("\ |
28e97307 | 9181 | The current ARM floating point model is \"%s\".\n"), |
6cb06a8c | 9182 | fp_model_strings[arm_fp_model]); |
28e97307 DJ |
9183 | } |
9184 | ||
9185 | static void | |
eb4c3f4a | 9186 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
9187 | struct cmd_list_element *c) |
9188 | { | |
570dc176 | 9189 | int arm_abi; |
28e97307 DJ |
9190 | |
9191 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
9192 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
9193 | { | |
aead7601 | 9194 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
9195 | break; |
9196 | } | |
9197 | ||
9198 | if (arm_abi == ARM_ABI_LAST) | |
9199 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
9200 | arm_abi_string); | |
9201 | ||
9202 | arm_update_current_architecture (); | |
9203 | } | |
9204 | ||
9205 | static void | |
9206 | arm_show_abi (struct ui_file *file, int from_tty, | |
9207 | struct cmd_list_element *c, const char *value) | |
9208 | { | |
28e97307 | 9209 | if (arm_abi_global == ARM_ABI_AUTO |
f5656ead | 9210 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6dff2a6f AB |
9211 | { |
9212 | arm_gdbarch_tdep *tdep | |
08106042 | 9213 | = gdbarch_tdep<arm_gdbarch_tdep> (target_gdbarch ()); |
6dff2a6f AB |
9214 | |
9215 | gdb_printf (file, _("\ | |
28e97307 | 9216 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
6dff2a6f AB |
9217 | arm_abi_strings[tdep->arm_abi]); |
9218 | } | |
28e97307 | 9219 | else |
6cb06a8c TT |
9220 | gdb_printf (file, _("The current ARM ABI is \"%s\".\n"), |
9221 | arm_abi_string); | |
fd50bc42 RE |
9222 | } |
9223 | ||
0428b8f5 DJ |
9224 | static void |
9225 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
9226 | struct cmd_list_element *c, const char *value) | |
9227 | { | |
6cb06a8c TT |
9228 | gdb_printf (file, |
9229 | _("The current execution mode assumed " | |
9230 | "(when symbols are unavailable) is \"%s\".\n"), | |
9231 | arm_fallback_mode_string); | |
0428b8f5 DJ |
9232 | } |
9233 | ||
9234 | static void | |
9235 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
9236 | struct cmd_list_element *c, const char *value) | |
9237 | { | |
6cb06a8c TT |
9238 | gdb_printf (file, |
9239 | _("The current execution mode assumed " | |
9240 | "(even when symbols are available) is \"%s\".\n"), | |
9241 | arm_force_mode_string); | |
0428b8f5 DJ |
9242 | } |
9243 | ||
ef273377 CL |
9244 | static void |
9245 | arm_show_unwind_secure_frames (struct ui_file *file, int from_tty, | |
9246 | struct cmd_list_element *c, const char *value) | |
9247 | { | |
9248 | gdb_printf (file, | |
9249 | _("Usage of non-secure to secure exception stack unwinding is %s.\n"), | |
9250 | arm_unwind_secure_frames ? "on" : "off"); | |
9251 | } | |
9252 | ||
afd7eef0 RE |
9253 | /* If the user changes the register disassembly style used for info |
9254 | register and other commands, we have to also switch the style used | |
9255 | in opcodes for disassembly output. This function is run in the "set | |
9256 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
9257 | |
9258 | static void | |
eb4c3f4a | 9259 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 9260 | struct cmd_list_element *c) |
bc90b915 | 9261 | { |
65b48a81 PB |
9262 | /* Convert the short style name into the long style name (eg, reg-names-*) |
9263 | before calling the generic set_disassembler_options() function. */ | |
9264 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
9265 | set_disassembler_options (&long_name[0]); | |
9266 | } | |
9267 | ||
9268 | static void | |
9269 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
9270 | struct cmd_list_element *c, const char *value) | |
9271 | { | |
9272 | struct gdbarch *gdbarch = get_current_arch (); | |
9273 | char *options = get_disassembler_options (gdbarch); | |
9274 | const char *style = ""; | |
9275 | int len = 0; | |
f995bbe8 | 9276 | const char *opt; |
65b48a81 PB |
9277 | |
9278 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
08dedd66 | 9279 | if (startswith (opt, "reg-names-")) |
65b48a81 PB |
9280 | { |
9281 | style = &opt[strlen ("reg-names-")]; | |
9282 | len = strcspn (style, ","); | |
9283 | } | |
9284 | ||
6cb06a8c | 9285 | gdb_printf (file, "The disassembly style is \"%.*s\".\n", len, style); |
bc90b915 FN |
9286 | } |
9287 | \f | |
966fbf70 | 9288 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 9289 | static const char * |
d93859e2 | 9290 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 9291 | { |
08106042 | 9292 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d | 9293 | |
ecbf5d4f | 9294 | if (is_s_pseudo (gdbarch, i)) |
58d6951d | 9295 | { |
ecbf5d4f | 9296 | static const char *const s_pseudo_names[] = { |
58d6951d DJ |
9297 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
9298 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
9299 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
9300 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
9301 | }; | |
9302 | ||
ecbf5d4f | 9303 | return s_pseudo_names[i - tdep->s_pseudo_base]; |
58d6951d DJ |
9304 | } |
9305 | ||
ecbf5d4f | 9306 | if (is_q_pseudo (gdbarch, i)) |
58d6951d | 9307 | { |
ecbf5d4f | 9308 | static const char *const q_pseudo_names[] = { |
58d6951d DJ |
9309 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", |
9310 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
9311 | }; | |
9312 | ||
ecbf5d4f | 9313 | return q_pseudo_names[i - tdep->q_pseudo_base]; |
58d6951d DJ |
9314 | } |
9315 | ||
ae66a8f1 SP |
9316 | if (is_mve_pseudo (gdbarch, i)) |
9317 | return "p0"; | |
9318 | ||
a01567f4 LM |
9319 | /* RA_AUTH_CODE is used for unwinding only. Do not assign it a name. */ |
9320 | if (is_pacbti_pseudo (gdbarch, i)) | |
9321 | return ""; | |
9322 | ||
ff6f572f DJ |
9323 | if (i >= ARRAY_SIZE (arm_register_names)) |
9324 | /* These registers are only supported on targets which supply | |
9325 | an XML description. */ | |
9326 | return ""; | |
9327 | ||
ecbf5d4f | 9328 | /* Non-pseudo registers. */ |
966fbf70 RE |
9329 | return arm_register_names[i]; |
9330 | } | |
9331 | ||
082fc60d RE |
9332 | /* Test whether the coff symbol specific value corresponds to a Thumb |
9333 | function. */ | |
9334 | ||
9335 | static int | |
9336 | coff_sym_is_thumb (int val) | |
9337 | { | |
f8bf5763 PM |
9338 | return (val == C_THUMBEXT |
9339 | || val == C_THUMBSTAT | |
9340 | || val == C_THUMBEXTFUNC | |
9341 | || val == C_THUMBSTATFUNC | |
9342 | || val == C_THUMBLABEL); | |
082fc60d RE |
9343 | } |
9344 | ||
9345 | /* arm_coff_make_msymbol_special() | |
9346 | arm_elf_make_msymbol_special() | |
9347 | ||
9348 | These functions test whether the COFF or ELF symbol corresponds to | |
9349 | an address in thumb code, and set a "special" bit in a minimal | |
9350 | symbol to indicate that it does. */ | |
9351 | ||
34e8f22d | 9352 | static void |
082fc60d RE |
9353 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
9354 | { | |
39d911fc TP |
9355 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
9356 | ||
9357 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 9358 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
9359 | MSYMBOL_SET_SPECIAL (msym); |
9360 | } | |
9361 | ||
34e8f22d | 9362 | static void |
082fc60d RE |
9363 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
9364 | { | |
9365 | if (coff_sym_is_thumb (val)) | |
9366 | MSYMBOL_SET_SPECIAL (msym); | |
9367 | } | |
9368 | ||
60c5725c DJ |
9369 | static void |
9370 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
9371 | asymbol *sym) | |
9372 | { | |
9373 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 9374 | struct arm_per_bfd *data; |
60c5725c DJ |
9375 | struct arm_mapping_symbol new_map_sym; |
9376 | ||
9377 | gdb_assert (name[0] == '$'); | |
9378 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
9379 | return; | |
9380 | ||
bd5766ec | 9381 | data = arm_bfd_data_key.get (objfile->obfd); |
60c5725c | 9382 | if (data == NULL) |
bd5766ec LM |
9383 | data = arm_bfd_data_key.emplace (objfile->obfd, |
9384 | objfile->obfd->section_count); | |
54cc7474 | 9385 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 9386 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
9387 | |
9388 | new_map_sym.value = sym->value; | |
9389 | new_map_sym.type = name[1]; | |
9390 | ||
4838e44c SM |
9391 | /* Insert at the end, the vector will be sorted on first use. */ |
9392 | map.push_back (new_map_sym); | |
60c5725c DJ |
9393 | } |
9394 | ||
756fe439 | 9395 | static void |
61a1198a | 9396 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 9397 | { |
ac7936df | 9398 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 9399 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
9400 | |
9401 | /* If necessary, set the T bit. */ | |
9402 | if (arm_apcs_32) | |
9403 | { | |
9779414d | 9404 | ULONGEST val, t_bit; |
61a1198a | 9405 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
9406 | t_bit = arm_psr_thumb_bit (gdbarch); |
9407 | if (arm_pc_is_thumb (gdbarch, pc)) | |
9408 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
9409 | val | t_bit); | |
756fe439 | 9410 | else |
61a1198a | 9411 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 9412 | val & ~t_bit); |
756fe439 DJ |
9413 | } |
9414 | } | |
123dc839 | 9415 | |
58d6951d DJ |
9416 | /* Read the contents of a NEON quad register, by reading from two |
9417 | double registers. This is used to implement the quad pseudo | |
9418 | registers, and for argument passing in case the quad registers are | |
9419 | missing; vectors are passed in quad registers when using the VFP | |
9420 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
9421 | the quad register, in [0, 15]. */ | |
9422 | ||
05d1431c | 9423 | static enum register_status |
849d0ba8 | 9424 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9425 | int regnum, gdb_byte *buf) |
9426 | { | |
9427 | char name_buf[4]; | |
9428 | gdb_byte reg_buf[8]; | |
9429 | int offset, double_regnum; | |
05d1431c | 9430 | enum register_status status; |
58d6951d | 9431 | |
8c042590 | 9432 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9433 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9434 | strlen (name_buf)); | |
9435 | ||
9436 | /* d0 is always the least significant half of q0. */ | |
9437 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9438 | offset = 8; | |
9439 | else | |
9440 | offset = 0; | |
9441 | ||
03f50fc8 | 9442 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9443 | if (status != REG_VALID) |
9444 | return status; | |
58d6951d DJ |
9445 | memcpy (buf + offset, reg_buf, 8); |
9446 | ||
9447 | offset = 8 - offset; | |
03f50fc8 | 9448 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
9449 | if (status != REG_VALID) |
9450 | return status; | |
58d6951d | 9451 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
9452 | |
9453 | return REG_VALID; | |
58d6951d DJ |
9454 | } |
9455 | ||
ae66a8f1 SP |
9456 | /* Read the contents of the MVE pseudo register REGNUM and store it |
9457 | in BUF. */ | |
9458 | ||
9459 | static enum register_status | |
9460 | arm_mve_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, | |
9461 | int regnum, gdb_byte *buf) | |
9462 | { | |
08106042 | 9463 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9464 | |
9465 | /* P0 is the first 16 bits of VPR. */ | |
9466 | return regcache->raw_read_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9467 | } | |
9468 | ||
05d1431c | 9469 | static enum register_status |
849d0ba8 | 9470 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
9471 | int regnum, gdb_byte *buf) |
9472 | { | |
9473 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9474 | char name_buf[4]; | |
9475 | gdb_byte reg_buf[8]; | |
9476 | int offset, double_regnum; | |
08106042 | 9477 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9478 | |
9479 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9480 | |
ecbf5d4f LM |
9481 | if (is_q_pseudo (gdbarch, regnum)) |
9482 | { | |
9483 | /* Quad-precision register. */ | |
9484 | return arm_neon_quad_read (gdbarch, regcache, | |
9485 | regnum - tdep->q_pseudo_base, buf); | |
9486 | } | |
ae66a8f1 SP |
9487 | else if (is_mve_pseudo (gdbarch, regnum)) |
9488 | return arm_mve_pseudo_read (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9489 | else |
9490 | { | |
05d1431c PA |
9491 | enum register_status status; |
9492 | ||
ecbf5d4f | 9493 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9494 | /* Single-precision register. */ |
9495 | gdb_assert (regnum < 32); | |
9496 | ||
9497 | /* s0 is always the least significant half of d0. */ | |
9498 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9499 | offset = (regnum & 1) ? 0 : 4; | |
9500 | else | |
9501 | offset = (regnum & 1) ? 4 : 0; | |
9502 | ||
8c042590 | 9503 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9504 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9505 | strlen (name_buf)); | |
9506 | ||
03f50fc8 | 9507 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9508 | if (status == REG_VALID) |
9509 | memcpy (buf, reg_buf + offset, 4); | |
9510 | return status; | |
58d6951d DJ |
9511 | } |
9512 | } | |
9513 | ||
9514 | /* Store the contents of BUF to a NEON quad register, by writing to | |
9515 | two double registers. This is used to implement the quad pseudo | |
9516 | registers, and for argument passing in case the quad registers are | |
9517 | missing; vectors are passed in quad registers when using the VFP | |
9518 | ABI, even if a NEON unit is not present. REGNUM is the index | |
9519 | of the quad register, in [0, 15]. */ | |
9520 | ||
9521 | static void | |
9522 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9523 | int regnum, const gdb_byte *buf) | |
9524 | { | |
9525 | char name_buf[4]; | |
58d6951d DJ |
9526 | int offset, double_regnum; |
9527 | ||
8c042590 | 9528 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9529 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9530 | strlen (name_buf)); | |
9531 | ||
9532 | /* d0 is always the least significant half of q0. */ | |
9533 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9534 | offset = 8; | |
9535 | else | |
9536 | offset = 0; | |
9537 | ||
10eaee5f | 9538 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 9539 | offset = 8 - offset; |
10eaee5f | 9540 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
9541 | } |
9542 | ||
ae66a8f1 SP |
9543 | /* Store the contents of BUF to the MVE pseudo register REGNUM. */ |
9544 | ||
9545 | static void | |
9546 | arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9547 | int regnum, const gdb_byte *buf) | |
9548 | { | |
08106042 | 9549 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
ae66a8f1 SP |
9550 | |
9551 | /* P0 is the first 16 bits of VPR. */ | |
9552 | regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9553 | } | |
9554 | ||
58d6951d DJ |
9555 | static void |
9556 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9557 | int regnum, const gdb_byte *buf) | |
9558 | { | |
9559 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9560 | char name_buf[4]; | |
9561 | gdb_byte reg_buf[8]; | |
9562 | int offset, double_regnum; | |
08106042 | 9563 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
58d6951d DJ |
9564 | |
9565 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9566 | |
ecbf5d4f LM |
9567 | if (is_q_pseudo (gdbarch, regnum)) |
9568 | { | |
9569 | /* Quad-precision register. */ | |
9570 | arm_neon_quad_write (gdbarch, regcache, | |
9571 | regnum - tdep->q_pseudo_base, buf); | |
9572 | } | |
ae66a8f1 SP |
9573 | else if (is_mve_pseudo (gdbarch, regnum)) |
9574 | arm_mve_pseudo_write (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9575 | else |
9576 | { | |
ecbf5d4f | 9577 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9578 | /* Single-precision register. */ |
9579 | gdb_assert (regnum < 32); | |
9580 | ||
9581 | /* s0 is always the least significant half of d0. */ | |
9582 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9583 | offset = (regnum & 1) ? 0 : 4; | |
9584 | else | |
9585 | offset = (regnum & 1) ? 4 : 0; | |
9586 | ||
8c042590 | 9587 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9588 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9589 | strlen (name_buf)); | |
9590 | ||
0b883586 | 9591 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 9592 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 9593 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
9594 | } |
9595 | } | |
9596 | ||
123dc839 DJ |
9597 | static struct value * |
9598 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
9599 | { | |
9a3c8263 | 9600 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
9601 | return value_of_register (*reg_p, frame); |
9602 | } | |
97e03143 | 9603 | \f |
70f80edf JT |
9604 | static enum gdb_osabi |
9605 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 9606 | { |
2af48f68 | 9607 | unsigned int elfosabi; |
70f80edf | 9608 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 9609 | |
70f80edf | 9610 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 9611 | |
28e97307 DJ |
9612 | if (elfosabi == ELFOSABI_ARM) |
9613 | /* GNU tools use this value. Check note sections in this case, | |
9614 | as well. */ | |
b35c1d1c TT |
9615 | { |
9616 | for (asection *sect : gdb_bfd_sections (abfd)) | |
9617 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
9618 | } | |
97e03143 | 9619 | |
28e97307 | 9620 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 9621 | return osabi; |
97e03143 RE |
9622 | } |
9623 | ||
54483882 YQ |
9624 | static int |
9625 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 9626 | const struct reggroup *group) |
54483882 | 9627 | { |
2c291032 YQ |
9628 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
9629 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
9630 | all_reggroup, of course. */ | |
54483882 | 9631 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
9632 | return (group == float_reggroup |
9633 | || group == save_reggroup | |
9634 | || group == restore_reggroup | |
9635 | || group == all_reggroup); | |
54483882 YQ |
9636 | else |
9637 | return default_register_reggroup_p (gdbarch, regnum, group); | |
9638 | } | |
9639 | ||
25f8c692 JL |
9640 | /* For backward-compatibility we allow two 'g' packet lengths with |
9641 | the remote protocol depending on whether FPA registers are | |
9642 | supplied. M-profile targets do not have FPA registers, but some | |
9643 | stubs already exist in the wild which use a 'g' packet which | |
9644 | supplies them albeit with dummy values. The packet format which | |
9645 | includes FPA registers should be considered deprecated for | |
9646 | M-profile targets. */ | |
9647 | ||
9648 | static void | |
9649 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
9650 | { | |
08106042 | 9651 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9652 | |
9653 | if (tdep->is_m) | |
25f8c692 | 9654 | { |
d105cce5 AH |
9655 | const target_desc *tdesc; |
9656 | ||
25f8c692 JL |
9657 | /* If we know from the executable this is an M-profile target, |
9658 | cater for remote targets whose register set layout is the | |
9659 | same as the FPA layout. */ | |
d105cce5 | 9660 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 9661 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9662 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 9663 | tdesc); |
25f8c692 JL |
9664 | |
9665 | /* The regular M-profile layout. */ | |
d105cce5 | 9666 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 9667 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 9668 | tdesc); |
3184d3f9 JL |
9669 | |
9670 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 9671 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 9672 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9673 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 9674 | tdesc); |
ae66a8f1 SP |
9675 | /* M-profile plus MVE. */ |
9676 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_MVE); | |
9677 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE | |
9678 | + ARM_VFP2_REGS_SIZE | |
9679 | + ARM_INT_REGISTER_SIZE, tdesc); | |
9074667a CL |
9680 | |
9681 | /* M-profile system (stack pointers). */ | |
9682 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_SYSTEM); | |
9683 | register_remote_g_packet_guess (gdbarch, 2 * ARM_INT_REGISTER_SIZE, tdesc); | |
25f8c692 JL |
9684 | } |
9685 | ||
9686 | /* Otherwise we don't have a useful guess. */ | |
9687 | } | |
9688 | ||
7eb89530 YQ |
9689 | /* Implement the code_of_frame_writable gdbarch method. */ |
9690 | ||
9691 | static int | |
9692 | arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame) | |
9693 | { | |
08106042 | 9694 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
345bd07c SM |
9695 | |
9696 | if (tdep->is_m && get_frame_type (frame) == SIGTRAMP_FRAME) | |
7eb89530 YQ |
9697 | { |
9698 | /* M-profile exception frames return to some magic PCs, where | |
9699 | isn't writable at all. */ | |
9700 | return 0; | |
9701 | } | |
9702 | else | |
9703 | return 1; | |
9704 | } | |
9705 | ||
3426ae57 AH |
9706 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
9707 | to be postfixed by a version (eg armv7hl). */ | |
9708 | ||
9709 | static const char * | |
9710 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
9711 | { | |
9712 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
9713 | return "arm(v[^- ]*)?"; | |
9714 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
9715 | } | |
9716 | ||
a01567f4 LM |
9717 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
9718 | ||
9719 | static std::string | |
9720 | arm_get_pc_address_flags (frame_info *frame, CORE_ADDR pc) | |
9721 | { | |
9722 | if (get_frame_pc_masked (frame)) | |
9723 | return "PAC"; | |
9724 | ||
9725 | return ""; | |
9726 | } | |
9727 | ||
da3c6d4a MS |
9728 | /* Initialize the current architecture based on INFO. If possible, |
9729 | re-use an architecture from ARCHES, which is a list of | |
9730 | architectures already created during this debugging session. | |
97e03143 | 9731 | |
da3c6d4a MS |
9732 | Called e.g. at program startup, when reading a core file, and when |
9733 | reading a binary file. */ | |
97e03143 | 9734 | |
39bbf761 RE |
9735 | static struct gdbarch * |
9736 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
9737 | { | |
9738 | struct gdbarch *gdbarch; | |
28e97307 DJ |
9739 | struct gdbarch_list *best_arch; |
9740 | enum arm_abi_kind arm_abi = arm_abi_global; | |
9741 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 9742 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
9743 | int i; |
9744 | bool is_m = false; | |
ae7e2f45 | 9745 | bool have_sec_ext = false; |
7559c217 | 9746 | int vfp_register_count = 0; |
ecbf5d4f | 9747 | bool have_s_pseudos = false, have_q_pseudos = false; |
7559c217 CB |
9748 | bool have_wmmx_registers = false; |
9749 | bool have_neon = false; | |
9750 | bool have_fpa_registers = true; | |
9779414d | 9751 | const struct target_desc *tdesc = info.target_desc; |
ae66a8f1 SP |
9752 | bool have_vfp = false; |
9753 | bool have_mve = false; | |
a01567f4 | 9754 | bool have_pacbti = false; |
ae66a8f1 | 9755 | int mve_vpr_regnum = -1; |
ecbf5d4f | 9756 | int register_count = ARM_NUM_REGS; |
9074667a CL |
9757 | bool have_m_profile_msp = false; |
9758 | int m_profile_msp_regnum = -1; | |
9759 | int m_profile_psp_regnum = -1; | |
ae7e2f45 CL |
9760 | int m_profile_msp_ns_regnum = -1; |
9761 | int m_profile_psp_ns_regnum = -1; | |
9762 | int m_profile_msp_s_regnum = -1; | |
9763 | int m_profile_psp_s_regnum = -1; | |
92d48a1e | 9764 | int tls_regnum = 0; |
9779414d DJ |
9765 | |
9766 | /* If we have an object to base this architecture on, try to determine | |
9767 | its ABI. */ | |
9768 | ||
9769 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
9770 | { | |
9771 | int ei_osabi, e_flags; | |
9772 | ||
9773 | switch (bfd_get_flavour (info.abfd)) | |
9774 | { | |
9779414d DJ |
9775 | case bfd_target_coff_flavour: |
9776 | /* Assume it's an old APCS-style ABI. */ | |
9777 | /* XXX WinCE? */ | |
9778 | arm_abi = ARM_ABI_APCS; | |
9779 | break; | |
9780 | ||
9781 | case bfd_target_elf_flavour: | |
9782 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
9783 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
9784 | ||
9785 | if (ei_osabi == ELFOSABI_ARM) | |
9786 | { | |
9787 | /* GNU tools used to use this value, but do not for EABI | |
9788 | objects. There's nowhere to tag an EABI version | |
9789 | anyway, so assume APCS. */ | |
9790 | arm_abi = ARM_ABI_APCS; | |
9791 | } | |
d403db27 | 9792 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
9793 | { |
9794 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
9795 | |
9796 | switch (eabi_ver) | |
9797 | { | |
9798 | case EF_ARM_EABI_UNKNOWN: | |
9799 | /* Assume GNU tools. */ | |
9800 | arm_abi = ARM_ABI_APCS; | |
9801 | break; | |
9802 | ||
9803 | case EF_ARM_EABI_VER4: | |
9804 | case EF_ARM_EABI_VER5: | |
9805 | arm_abi = ARM_ABI_AAPCS; | |
9806 | /* EABI binaries default to VFP float ordering. | |
9807 | They may also contain build attributes that can | |
9808 | be used to identify if the VFP argument-passing | |
9809 | ABI is in use. */ | |
9810 | if (fp_model == ARM_FLOAT_AUTO) | |
9811 | { | |
9812 | #ifdef HAVE_ELF | |
9813 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
9814 | OBJ_ATTR_PROC, | |
9815 | Tag_ABI_VFP_args)) | |
9816 | { | |
b35b0298 | 9817 | case AEABI_VFP_args_base: |
9779414d DJ |
9818 | /* "The user intended FP parameter/result |
9819 | passing to conform to AAPCS, base | |
9820 | variant". */ | |
9821 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9822 | break; | |
b35b0298 | 9823 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9824 | /* "The user intended FP parameter/result |
9825 | passing to conform to AAPCS, VFP | |
9826 | variant". */ | |
9827 | fp_model = ARM_FLOAT_VFP; | |
9828 | break; | |
b35b0298 | 9829 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9830 | /* "The user intended FP parameter/result |
9831 | passing to conform to tool chain-specific | |
9832 | conventions" - we don't know any such | |
9833 | conventions, so leave it as "auto". */ | |
9834 | break; | |
b35b0298 | 9835 | case AEABI_VFP_args_compatible: |
5c294fee TG |
9836 | /* "Code is compatible with both the base |
9837 | and VFP variants; the user did not permit | |
9838 | non-variadic functions to pass FP | |
9839 | parameters/results" - leave it as | |
9840 | "auto". */ | |
9841 | break; | |
9779414d DJ |
9842 | default: |
9843 | /* Attribute value not mentioned in the | |
5c294fee | 9844 | November 2012 ABI, so leave it as |
9779414d DJ |
9845 | "auto". */ |
9846 | break; | |
9847 | } | |
9848 | #else | |
9849 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9850 | #endif | |
9851 | } | |
9852 | break; | |
9853 | ||
9854 | default: | |
9855 | /* Leave it as "auto". */ | |
9856 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
9857 | break; | |
9858 | } | |
9859 | ||
9860 | #ifdef HAVE_ELF | |
9861 | /* Detect M-profile programs. This only works if the | |
9862 | executable file includes build attributes; GCC does | |
9863 | copy them to the executable, but e.g. RealView does | |
9864 | not. */ | |
17cbafdb SM |
9865 | int attr_arch |
9866 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9867 | Tag_CPU_arch); | |
9868 | int attr_profile | |
9869 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9870 | Tag_CPU_arch_profile); | |
9871 | ||
9779414d DJ |
9872 | /* GCC specifies the profile for v6-M; RealView only |
9873 | specifies the profile for architectures starting with | |
9874 | V7 (as opposed to architectures with a tag | |
9875 | numerically greater than TAG_CPU_ARCH_V7). */ | |
9876 | if (!tdesc_has_registers (tdesc) | |
9877 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
9878 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
131a355f LM |
9879 | || attr_arch == TAG_CPU_ARCH_V7E_M |
9880 | || attr_arch == TAG_CPU_ARCH_V8M_BASE | |
9881 | || attr_arch == TAG_CPU_ARCH_V8M_MAIN | |
ae66a8f1 | 9882 | || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN |
9779414d | 9883 | || attr_profile == 'M')) |
7559c217 | 9884 | is_m = true; |
a01567f4 LM |
9885 | |
9886 | /* Look for attributes that indicate support for ARMv8.1-m | |
9887 | PACBTI. */ | |
9888 | if (!tdesc_has_registers (tdesc) && is_m) | |
9889 | { | |
9890 | int attr_pac_extension | |
9891 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9892 | Tag_PAC_extension); | |
9893 | ||
9894 | int attr_bti_extension | |
9895 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9896 | Tag_BTI_extension); | |
9897 | ||
9898 | int attr_pacret_use | |
9899 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9900 | Tag_PACRET_use); | |
9901 | ||
9902 | int attr_bti_use | |
9903 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9904 | Tag_BTI_use); | |
9905 | ||
9906 | if (attr_pac_extension != 0 || attr_bti_extension != 0 | |
9907 | || attr_pacret_use != 0 || attr_bti_use != 0) | |
9908 | have_pacbti = true; | |
9909 | } | |
9779414d DJ |
9910 | #endif |
9911 | } | |
9912 | ||
9913 | if (fp_model == ARM_FLOAT_AUTO) | |
9914 | { | |
9779414d DJ |
9915 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
9916 | { | |
9917 | case 0: | |
9918 | /* Leave it as "auto". Strictly speaking this case | |
9919 | means FPA, but almost nobody uses that now, and | |
9920 | many toolchains fail to set the appropriate bits | |
9921 | for the floating-point model they use. */ | |
9922 | break; | |
9923 | case EF_ARM_SOFT_FLOAT: | |
9924 | fp_model = ARM_FLOAT_SOFT_FPA; | |
9925 | break; | |
9926 | case EF_ARM_VFP_FLOAT: | |
9927 | fp_model = ARM_FLOAT_VFP; | |
9928 | break; | |
9929 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
9930 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9931 | break; | |
9932 | } | |
9933 | } | |
9934 | ||
9935 | if (e_flags & EF_ARM_BE8) | |
9936 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
9937 | ||
9938 | break; | |
9939 | ||
9940 | default: | |
9941 | /* Leave it as "auto". */ | |
9942 | break; | |
9943 | } | |
9944 | } | |
123dc839 DJ |
9945 | |
9946 | /* Check any target description for validity. */ | |
9779414d | 9947 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
9948 | { |
9949 | /* For most registers we require GDB's default names; but also allow | |
9950 | the numeric names for sp / lr / pc, as a convenience. */ | |
9951 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
9952 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
9953 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
9954 | ||
9955 | const struct tdesc_feature *feature; | |
58d6951d | 9956 | int valid_p; |
123dc839 | 9957 | |
9779414d | 9958 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9959 | "org.gnu.gdb.arm.core"); |
9960 | if (feature == NULL) | |
9779414d DJ |
9961 | { |
9962 | feature = tdesc_find_feature (tdesc, | |
9963 | "org.gnu.gdb.arm.m-profile"); | |
9964 | if (feature == NULL) | |
9965 | return NULL; | |
9966 | else | |
7559c217 | 9967 | is_m = true; |
9779414d | 9968 | } |
123dc839 DJ |
9969 | |
9970 | tdesc_data = tdesc_data_alloc (); | |
9971 | ||
9972 | valid_p = 1; | |
9973 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 9974 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 9975 | arm_register_names[i]); |
c1e1314d | 9976 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9977 | ARM_SP_REGNUM, |
9978 | arm_sp_names); | |
c1e1314d | 9979 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9980 | ARM_LR_REGNUM, |
9981 | arm_lr_names); | |
c1e1314d | 9982 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9983 | ARM_PC_REGNUM, |
9984 | arm_pc_names); | |
9779414d | 9985 | if (is_m) |
c1e1314d | 9986 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
9987 | ARM_PS_REGNUM, "xpsr"); |
9988 | else | |
c1e1314d | 9989 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 9990 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
9991 | |
9992 | if (!valid_p) | |
c1e1314d | 9993 | return NULL; |
123dc839 | 9994 | |
9074667a CL |
9995 | if (is_m) |
9996 | { | |
9997 | feature = tdesc_find_feature (tdesc, | |
9998 | "org.gnu.gdb.arm.m-system"); | |
9999 | if (feature != nullptr) | |
10000 | { | |
10001 | /* MSP */ | |
10002 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10003 | register_count, "msp"); | |
10004 | if (!valid_p) | |
10005 | { | |
10006 | warning (_("M-profile m-system feature is missing required register msp.")); | |
10007 | return nullptr; | |
10008 | } | |
10009 | have_m_profile_msp = true; | |
10010 | m_profile_msp_regnum = register_count++; | |
10011 | ||
10012 | /* PSP */ | |
10013 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10014 | register_count, "psp"); | |
10015 | if (!valid_p) | |
10016 | { | |
10017 | warning (_("M-profile m-system feature is missing required register psp.")); | |
10018 | return nullptr; | |
10019 | } | |
10020 | m_profile_psp_regnum = register_count++; | |
10021 | } | |
10022 | } | |
10023 | ||
9779414d | 10024 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
10025 | "org.gnu.gdb.arm.fpa"); |
10026 | if (feature != NULL) | |
10027 | { | |
10028 | valid_p = 1; | |
10029 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 10030 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
10031 | arm_register_names[i]); |
10032 | if (!valid_p) | |
c1e1314d | 10033 | return NULL; |
123dc839 | 10034 | } |
ff6f572f | 10035 | else |
7559c217 | 10036 | have_fpa_registers = false; |
ff6f572f | 10037 | |
9779414d | 10038 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
10039 | "org.gnu.gdb.xscale.iwmmxt"); |
10040 | if (feature != NULL) | |
10041 | { | |
10042 | static const char *const iwmmxt_names[] = { | |
10043 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
10044 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
10045 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
10046 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
10047 | }; | |
10048 | ||
10049 | valid_p = 1; | |
10050 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
10051 | valid_p | |
c1e1314d | 10052 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10053 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10054 | ||
10055 | /* Check for the control registers, but do not fail if they | |
10056 | are missing. */ | |
10057 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 10058 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10059 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10060 | ||
10061 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
10062 | valid_p | |
c1e1314d | 10063 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
10064 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
10065 | ||
10066 | if (!valid_p) | |
c1e1314d | 10067 | return NULL; |
a56cc1ce | 10068 | |
7559c217 | 10069 | have_wmmx_registers = true; |
ff6f572f | 10070 | } |
58d6951d DJ |
10071 | |
10072 | /* If we have a VFP unit, check whether the single precision registers | |
10073 | are present. If not, then we will synthesize them as pseudo | |
10074 | registers. */ | |
9779414d | 10075 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10076 | "org.gnu.gdb.arm.vfp"); |
10077 | if (feature != NULL) | |
10078 | { | |
10079 | static const char *const vfp_double_names[] = { | |
10080 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
10081 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
10082 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
10083 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
10084 | }; | |
10085 | ||
10086 | /* Require the double precision registers. There must be either | |
10087 | 16 or 32. */ | |
10088 | valid_p = 1; | |
10089 | for (i = 0; i < 32; i++) | |
10090 | { | |
c1e1314d | 10091 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
10092 | ARM_D0_REGNUM + i, |
10093 | vfp_double_names[i]); | |
10094 | if (!valid_p) | |
10095 | break; | |
10096 | } | |
2b9e5ea6 UW |
10097 | if (!valid_p && i == 16) |
10098 | valid_p = 1; | |
58d6951d | 10099 | |
2b9e5ea6 | 10100 | /* Also require FPSCR. */ |
c1e1314d | 10101 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
10102 | ARM_FPSCR_REGNUM, "fpscr"); |
10103 | if (!valid_p) | |
c1e1314d | 10104 | return NULL; |
58d6951d | 10105 | |
ae66a8f1 SP |
10106 | have_vfp = true; |
10107 | ||
58d6951d | 10108 | if (tdesc_unnumbered_register (feature, "s0") == 0) |
ecbf5d4f | 10109 | have_s_pseudos = true; |
58d6951d | 10110 | |
330c6ca9 | 10111 | vfp_register_count = i; |
58d6951d DJ |
10112 | |
10113 | /* If we have VFP, also check for NEON. The architecture allows | |
10114 | NEON without VFP (integer vector operations only), but GDB | |
10115 | does not support that. */ | |
9779414d | 10116 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
10117 | "org.gnu.gdb.arm.neon"); |
10118 | if (feature != NULL) | |
10119 | { | |
10120 | /* NEON requires 32 double-precision registers. */ | |
10121 | if (i != 32) | |
c1e1314d | 10122 | return NULL; |
58d6951d DJ |
10123 | |
10124 | /* If there are quad registers defined by the stub, use | |
10125 | their type; otherwise (normally) provide them with | |
10126 | the default type. */ | |
10127 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
ecbf5d4f | 10128 | have_q_pseudos = true; |
ae66a8f1 SP |
10129 | } |
10130 | } | |
10131 | ||
92d48a1e JB |
10132 | /* Check for the TLS register feature. */ |
10133 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.arm.tls"); | |
10134 | if (feature != nullptr) | |
10135 | { | |
10136 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10137 | register_count, "tpidruro"); | |
10138 | if (!valid_p) | |
10139 | return nullptr; | |
10140 | ||
10141 | tls_regnum = register_count; | |
10142 | register_count++; | |
10143 | } | |
10144 | ||
ae66a8f1 SP |
10145 | /* Check for MVE after all the checks for GPR's, VFP and Neon. |
10146 | MVE (Helium) is an M-profile extension. */ | |
10147 | if (is_m) | |
10148 | { | |
10149 | /* Do we have the MVE feature? */ | |
10150 | feature = tdesc_find_feature (tdesc,"org.gnu.gdb.arm.m-profile-mve"); | |
10151 | ||
10152 | if (feature != nullptr) | |
10153 | { | |
10154 | /* If we have MVE, we must always have the VPR register. */ | |
10155 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10156 | register_count, "vpr"); | |
10157 | if (!valid_p) | |
10158 | { | |
10159 | warning (_("MVE feature is missing required register vpr.")); | |
10160 | return nullptr; | |
10161 | } | |
58d6951d | 10162 | |
ae66a8f1 SP |
10163 | have_mve = true; |
10164 | mve_vpr_regnum = register_count; | |
10165 | register_count++; | |
10166 | ||
10167 | /* We can't have Q pseudo registers available here, as that | |
10168 | would mean we have NEON features, and that is only available | |
10169 | on A and R profiles. */ | |
10170 | gdb_assert (!have_q_pseudos); | |
10171 | ||
10172 | /* Given we have a M-profile target description, if MVE is | |
10173 | enabled and there are VFP registers, we should have Q | |
10174 | pseudo registers (Q0 ~ Q7). */ | |
10175 | if (have_vfp) | |
10176 | have_q_pseudos = true; | |
58d6951d | 10177 | } |
a01567f4 LM |
10178 | |
10179 | /* Do we have the ARMv8.1-m PACBTI feature? */ | |
10180 | feature = tdesc_find_feature (tdesc, | |
10181 | "org.gnu.gdb.arm.m-profile-pacbti"); | |
10182 | if (feature != nullptr) | |
10183 | { | |
10184 | /* By advertising this feature, the target acknowledges the | |
10185 | presence of the ARMv8.1-m PACBTI extensions. | |
10186 | ||
10187 | We don't care for any particular registers in this group, so | |
10188 | the target is free to include whatever it deems appropriate. | |
10189 | ||
10190 | The expectation is for this feature to include the PAC | |
10191 | keys. */ | |
10192 | have_pacbti = true; | |
10193 | } | |
ae7e2f45 CL |
10194 | |
10195 | /* Do we have the Security extension? */ | |
10196 | feature = tdesc_find_feature (tdesc, | |
10197 | "org.gnu.gdb.arm.secext"); | |
10198 | if (feature != nullptr) | |
10199 | { | |
10200 | /* Secure/Non-secure stack pointers. */ | |
10201 | /* MSP_NS */ | |
10202 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10203 | register_count, "msp_ns"); | |
10204 | if (!valid_p) | |
10205 | { | |
10206 | warning (_("M-profile secext feature is missing required register msp_ns.")); | |
10207 | return nullptr; | |
10208 | } | |
10209 | m_profile_msp_ns_regnum = register_count++; | |
10210 | ||
10211 | /* PSP_NS */ | |
10212 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10213 | register_count, "psp_ns"); | |
10214 | if (!valid_p) | |
10215 | { | |
10216 | warning (_("M-profile secext feature is missing required register psp_ns.")); | |
10217 | return nullptr; | |
10218 | } | |
10219 | m_profile_psp_ns_regnum = register_count++; | |
10220 | ||
10221 | /* MSP_S */ | |
10222 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10223 | register_count, "msp_s"); | |
10224 | if (!valid_p) | |
10225 | { | |
10226 | warning (_("M-profile secext feature is missing required register msp_s.")); | |
10227 | return nullptr; | |
10228 | } | |
10229 | m_profile_msp_s_regnum = register_count++; | |
10230 | ||
10231 | /* PSP_S */ | |
10232 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
10233 | register_count, "psp_s"); | |
10234 | if (!valid_p) | |
10235 | { | |
10236 | warning (_("M-profile secext feature is missing required register psp_s.")); | |
10237 | return nullptr; | |
10238 | } | |
10239 | m_profile_psp_s_regnum = register_count++; | |
10240 | ||
10241 | have_sec_ext = true; | |
10242 | } | |
10243 | ||
58d6951d | 10244 | } |
123dc839 | 10245 | } |
39bbf761 | 10246 | |
28e97307 DJ |
10247 | /* If there is already a candidate, use it. */ |
10248 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
10249 | best_arch != NULL; | |
10250 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
10251 | { | |
345bd07c | 10252 | arm_gdbarch_tdep *tdep |
08106042 | 10253 | = gdbarch_tdep<arm_gdbarch_tdep> (best_arch->gdbarch); |
345bd07c SM |
10254 | |
10255 | if (arm_abi != ARM_ABI_AUTO && arm_abi != tdep->arm_abi) | |
28e97307 DJ |
10256 | continue; |
10257 | ||
345bd07c | 10258 | if (fp_model != ARM_FLOAT_AUTO && fp_model != tdep->fp_model) |
28e97307 DJ |
10259 | continue; |
10260 | ||
58d6951d DJ |
10261 | /* There are various other properties in tdep that we do not |
10262 | need to check here: those derived from a target description, | |
10263 | since gdbarches with a different target description are | |
10264 | automatically disqualified. */ | |
10265 | ||
9779414d | 10266 | /* Do check is_m, though, since it might come from the binary. */ |
345bd07c | 10267 | if (is_m != tdep->is_m) |
9779414d DJ |
10268 | continue; |
10269 | ||
a01567f4 LM |
10270 | /* Also check for ARMv8.1-m PACBTI support, since it might come from |
10271 | the binary. */ | |
10272 | if (have_pacbti != tdep->have_pacbti) | |
10273 | continue; | |
10274 | ||
28e97307 DJ |
10275 | /* Found a match. */ |
10276 | break; | |
10277 | } | |
97e03143 | 10278 | |
28e97307 | 10279 | if (best_arch != NULL) |
c1e1314d | 10280 | return best_arch->gdbarch; |
28e97307 | 10281 | |
345bd07c | 10282 | arm_gdbarch_tdep *tdep = new arm_gdbarch_tdep; |
97e03143 RE |
10283 | gdbarch = gdbarch_alloc (&info, tdep); |
10284 | ||
28e97307 DJ |
10285 | /* Record additional information about the architecture we are defining. |
10286 | These are gdbarch discriminators, like the OSABI. */ | |
10287 | tdep->arm_abi = arm_abi; | |
10288 | tdep->fp_model = fp_model; | |
9779414d | 10289 | tdep->is_m = is_m; |
ae7e2f45 | 10290 | tdep->have_sec_ext = have_sec_ext; |
ff6f572f | 10291 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 10292 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
10293 | gdb_assert (vfp_register_count == 0 |
10294 | || vfp_register_count == 16 | |
10295 | || vfp_register_count == 32); | |
10296 | tdep->vfp_register_count = vfp_register_count; | |
ecbf5d4f LM |
10297 | tdep->have_s_pseudos = have_s_pseudos; |
10298 | tdep->have_q_pseudos = have_q_pseudos; | |
58d6951d | 10299 | tdep->have_neon = have_neon; |
92d48a1e | 10300 | tdep->tls_regnum = tls_regnum; |
08216dd7 | 10301 | |
ae66a8f1 SP |
10302 | /* Adjust the MVE feature settings. */ |
10303 | if (have_mve) | |
10304 | { | |
10305 | tdep->have_mve = true; | |
10306 | tdep->mve_vpr_regnum = mve_vpr_regnum; | |
10307 | } | |
10308 | ||
a01567f4 LM |
10309 | /* Adjust the PACBTI feature settings. */ |
10310 | tdep->have_pacbti = have_pacbti; | |
10311 | ||
9074667a CL |
10312 | /* Adjust the M-profile stack pointers settings. */ |
10313 | if (have_m_profile_msp) | |
10314 | { | |
10315 | tdep->m_profile_msp_regnum = m_profile_msp_regnum; | |
10316 | tdep->m_profile_psp_regnum = m_profile_psp_regnum; | |
ae7e2f45 CL |
10317 | tdep->m_profile_msp_ns_regnum = m_profile_msp_ns_regnum; |
10318 | tdep->m_profile_psp_ns_regnum = m_profile_psp_ns_regnum; | |
10319 | tdep->m_profile_msp_s_regnum = m_profile_msp_s_regnum; | |
10320 | tdep->m_profile_psp_s_regnum = m_profile_psp_s_regnum; | |
9074667a CL |
10321 | } |
10322 | ||
25f8c692 JL |
10323 | arm_register_g_packet_guesses (gdbarch); |
10324 | ||
08216dd7 | 10325 | /* Breakpoints. */ |
9d4fde75 | 10326 | switch (info.byte_order_for_code) |
67255d04 RE |
10327 | { |
10328 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
10329 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
10330 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
10331 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
10332 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
10333 | ||
67255d04 RE |
10334 | break; |
10335 | ||
10336 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
10337 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
10338 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
10339 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
10340 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
10341 | ||
67255d04 RE |
10342 | break; |
10343 | ||
10344 | default: | |
10345 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 10346 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
10347 | } |
10348 | ||
d7b486e7 RE |
10349 | /* On ARM targets char defaults to unsigned. */ |
10350 | set_gdbarch_char_signed (gdbarch, 0); | |
10351 | ||
53375380 PA |
10352 | /* wchar_t is unsigned under the AAPCS. */ |
10353 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
10354 | set_gdbarch_wchar_signed (gdbarch, 0); | |
10355 | else | |
10356 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 10357 | |
030197b4 AB |
10358 | /* Compute type alignment. */ |
10359 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
10360 | ||
cca44b1b JB |
10361 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
10362 | of additional scratch space. This setting isn't used for anything beside | |
10363 | displaced stepping at present. */ | |
e935475c | 10364 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 10365 | |
9df628e0 | 10366 | /* This should be low enough for everything. */ |
97e03143 | 10367 | tdep->lowest_pc = 0x20; |
94c30b78 | 10368 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 10369 | |
7c00367c MK |
10370 | /* The default, for both APCS and AAPCS, is to return small |
10371 | structures in registers. */ | |
10372 | tdep->struct_return = reg_struct_return; | |
10373 | ||
2dd604e7 | 10374 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 10375 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 10376 | |
7eb89530 YQ |
10377 | if (is_m) |
10378 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
10379 | ||
756fe439 DJ |
10380 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
10381 | ||
eb5492fa | 10382 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 10383 | |
34e8f22d | 10384 | /* Address manipulation. */ |
34e8f22d RE |
10385 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
10386 | ||
34e8f22d RE |
10387 | /* Advance PC across function entry code. */ |
10388 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
10389 | ||
c9cf6e20 MG |
10390 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
10391 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 10392 | |
190dce09 UW |
10393 | /* Skip trampolines. */ |
10394 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
10395 | ||
34e8f22d RE |
10396 | /* The stack grows downward. */ |
10397 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
10398 | ||
10399 | /* Breakpoint manipulation. */ | |
04180708 YQ |
10400 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
10401 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
10402 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
10403 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
10404 | |
10405 | /* Information about registers, etc. */ | |
34e8f22d RE |
10406 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
10407 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ecbf5d4f | 10408 | set_gdbarch_num_regs (gdbarch, register_count); |
7a5ea0d4 | 10409 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 10410 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 10411 | |
ff6f572f DJ |
10412 | /* This "info float" is FPA-specific. Use the generic version if we |
10413 | do not have FPA. */ | |
345bd07c | 10414 | if (tdep->have_fpa_registers) |
ff6f572f DJ |
10415 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
10416 | ||
26216b98 | 10417 | /* Internal <-> external register number maps. */ |
ff6f572f | 10418 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
10419 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
10420 | ||
34e8f22d RE |
10421 | set_gdbarch_register_name (gdbarch, arm_register_name); |
10422 | ||
10423 | /* Returning results. */ | |
2af48f68 | 10424 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 10425 | |
03d48a7d RE |
10426 | /* Disassembly. */ |
10427 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
10428 | ||
34e8f22d RE |
10429 | /* Minsymbol frobbing. */ |
10430 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
10431 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
10432 | arm_coff_make_msymbol_special); | |
60c5725c | 10433 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 10434 | |
f9d67f43 DJ |
10435 | /* Thumb-2 IT block support. */ |
10436 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
10437 | arm_adjust_breakpoint_address); | |
10438 | ||
0d5de010 DJ |
10439 | /* Virtual tables. */ |
10440 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
10441 | ||
97e03143 | 10442 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 10443 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 10444 | |
b39cc962 DJ |
10445 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
10446 | ||
eb5492fa | 10447 | /* Add some default predicates. */ |
2ae28aa9 YQ |
10448 | if (is_m) |
10449 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
10450 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
10451 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 10452 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 10453 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 10454 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 10455 | |
97e03143 RE |
10456 | /* Now we have tuned the configuration, set a few final things, |
10457 | based on what the OS ABI has told us. */ | |
10458 | ||
b8926edc DJ |
10459 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
10460 | binaries are always marked. */ | |
10461 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
10462 | tdep->arm_abi = ARM_ABI_APCS; | |
10463 | ||
e3039479 UW |
10464 | /* Watchpoints are not steppable. */ |
10465 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
10466 | ||
b8926edc DJ |
10467 | /* We used to default to FPA for generic ARM, but almost nobody |
10468 | uses that now, and we now provide a way for the user to force | |
10469 | the model. So default to the most useful variant. */ | |
10470 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
10471 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
10472 | ||
9df628e0 RE |
10473 | if (tdep->jb_pc >= 0) |
10474 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
10475 | ||
08216dd7 | 10476 | /* Floating point sizes and format. */ |
8da61cc4 | 10477 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 10478 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 10479 | { |
8da61cc4 DJ |
10480 | set_gdbarch_double_format |
10481 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10482 | set_gdbarch_long_double_format | |
10483 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
10484 | } | |
10485 | else | |
10486 | { | |
10487 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
10488 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
10489 | } |
10490 | ||
a01567f4 LM |
10491 | /* Hook used to decorate frames with signed return addresses, only available |
10492 | for ARMv8.1-m PACBTI. */ | |
10493 | if (is_m && have_pacbti) | |
10494 | set_gdbarch_get_pc_address_flags (gdbarch, arm_get_pc_address_flags); | |
10495 | ||
dc22c61a LM |
10496 | if (tdesc_data != nullptr) |
10497 | { | |
10498 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
10499 | ||
10500 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
ecbf5d4f | 10501 | register_count = gdbarch_num_regs (gdbarch); |
dc22c61a LM |
10502 | |
10503 | /* Override tdesc_register_type to adjust the types of VFP | |
10504 | registers for NEON. */ | |
10505 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
10506 | } | |
10507 | ||
ecbf5d4f | 10508 | /* Initialize the pseudo register data. */ |
ae66a8f1 | 10509 | int num_pseudos = 0; |
ecbf5d4f | 10510 | if (tdep->have_s_pseudos) |
58d6951d | 10511 | { |
ecbf5d4f LM |
10512 | /* VFP single precision pseudo registers (S0~S31). */ |
10513 | tdep->s_pseudo_base = register_count; | |
10514 | tdep->s_pseudo_count = 32; | |
ae66a8f1 | 10515 | num_pseudos += tdep->s_pseudo_count; |
ecbf5d4f LM |
10516 | |
10517 | if (tdep->have_q_pseudos) | |
10518 | { | |
10519 | /* NEON quad precision pseudo registers (Q0~Q15). */ | |
10520 | tdep->q_pseudo_base = register_count + num_pseudos; | |
ae66a8f1 SP |
10521 | |
10522 | if (have_neon) | |
10523 | tdep->q_pseudo_count = 16; | |
10524 | else if (have_mve) | |
10525 | tdep->q_pseudo_count = ARM_MVE_NUM_Q_REGS; | |
10526 | ||
ecbf5d4f LM |
10527 | num_pseudos += tdep->q_pseudo_count; |
10528 | } | |
ae66a8f1 SP |
10529 | } |
10530 | ||
10531 | /* Do we have any MVE pseudo registers? */ | |
10532 | if (have_mve) | |
10533 | { | |
10534 | tdep->mve_pseudo_base = register_count + num_pseudos; | |
10535 | tdep->mve_pseudo_count = 1; | |
10536 | num_pseudos += tdep->mve_pseudo_count; | |
10537 | } | |
58d6951d | 10538 | |
a01567f4 LM |
10539 | /* Do we have any ARMv8.1-m PACBTI pseudo registers. */ |
10540 | if (have_pacbti) | |
10541 | { | |
10542 | tdep->pacbti_pseudo_base = register_count + num_pseudos; | |
10543 | tdep->pacbti_pseudo_count = 1; | |
10544 | num_pseudos += tdep->pacbti_pseudo_count; | |
10545 | } | |
10546 | ||
ae66a8f1 | 10547 | /* Set some pseudo register hooks, if we have pseudo registers. */ |
a01567f4 | 10548 | if (tdep->have_s_pseudos || have_mve || have_pacbti) |
ae66a8f1 | 10549 | { |
58d6951d DJ |
10550 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); |
10551 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
10552 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
10553 | } | |
10554 | ||
123dc839 | 10555 | /* Add standard register aliases. We add aliases even for those |
85102364 | 10556 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
10557 | and does no harm, since nothing ever lists user registers. */ |
10558 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
10559 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
10560 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
10561 | ||
65b48a81 PB |
10562 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
10563 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
10564 | ||
3426ae57 AH |
10565 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
10566 | ||
39bbf761 RE |
10567 | return gdbarch; |
10568 | } | |
10569 | ||
97e03143 | 10570 | static void |
2af46ca0 | 10571 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 10572 | { |
08106042 | 10573 | arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch); |
97e03143 RE |
10574 | |
10575 | if (tdep == NULL) | |
10576 | return; | |
10577 | ||
6cb06a8c TT |
10578 | gdb_printf (file, _("arm_dump_tdep: fp_model = %i\n"), |
10579 | (int) tdep->fp_model); | |
10580 | gdb_printf (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
10581 | (int) tdep->have_fpa_registers); | |
10582 | gdb_printf (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
10583 | (int) tdep->have_wmmx_registers); | |
10584 | gdb_printf (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
10585 | (int) tdep->vfp_register_count); | |
10586 | gdb_printf (file, _("arm_dump_tdep: have_s_pseudos = %s\n"), | |
10587 | tdep->have_s_pseudos? "true" : "false"); | |
10588 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_base = %i\n"), | |
10589 | (int) tdep->s_pseudo_base); | |
10590 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_count = %i\n"), | |
10591 | (int) tdep->s_pseudo_count); | |
10592 | gdb_printf (file, _("arm_dump_tdep: have_q_pseudos = %s\n"), | |
10593 | tdep->have_q_pseudos? "true" : "false"); | |
10594 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_base = %i\n"), | |
10595 | (int) tdep->q_pseudo_base); | |
10596 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_count = %i\n"), | |
10597 | (int) tdep->q_pseudo_count); | |
10598 | gdb_printf (file, _("arm_dump_tdep: have_neon = %i\n"), | |
10599 | (int) tdep->have_neon); | |
10600 | gdb_printf (file, _("arm_dump_tdep: have_mve = %s\n"), | |
10601 | tdep->have_mve? "yes" : "no"); | |
10602 | gdb_printf (file, _("arm_dump_tdep: mve_vpr_regnum = %i\n"), | |
10603 | tdep->mve_vpr_regnum); | |
10604 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_base = %i\n"), | |
10605 | tdep->mve_pseudo_base); | |
10606 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_count = %i\n"), | |
10607 | tdep->mve_pseudo_count); | |
9074667a CL |
10608 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_regnum = %i\n"), |
10609 | tdep->m_profile_msp_regnum); | |
10610 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_regnum = %i\n"), | |
10611 | tdep->m_profile_psp_regnum); | |
ae7e2f45 CL |
10612 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"), |
10613 | tdep->m_profile_msp_ns_regnum); | |
10614 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"), | |
10615 | tdep->m_profile_psp_ns_regnum); | |
10616 | gdb_printf (file, _("arm_dump_tdep: m_profile_msp_s_regnum = %i\n"), | |
10617 | tdep->m_profile_msp_s_regnum); | |
10618 | gdb_printf (file, _("arm_dump_tdep: m_profile_psp_s_regnum = %i\n"), | |
10619 | tdep->m_profile_psp_s_regnum); | |
6cb06a8c TT |
10620 | gdb_printf (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), |
10621 | (unsigned long) tdep->lowest_pc); | |
a01567f4 LM |
10622 | gdb_printf (file, _("arm_dump_tdep: have_pacbti = %s\n"), |
10623 | tdep->have_pacbti? "yes" : "no"); | |
10624 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_base = %i\n"), | |
10625 | tdep->pacbti_pseudo_base); | |
10626 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_count = %i\n"), | |
10627 | tdep->pacbti_pseudo_count); | |
10628 | gdb_printf (file, _("arm_dump_tdep: is_m = %s\n"), | |
10629 | tdep->is_m? "yes" : "no"); | |
97e03143 RE |
10630 | } |
10631 | ||
0d4c07af | 10632 | #if GDB_SELF_TEST |
b121eeb9 YQ |
10633 | namespace selftests |
10634 | { | |
10635 | static void arm_record_test (void); | |
9ecab40c | 10636 | static void arm_analyze_prologue_test (); |
b121eeb9 | 10637 | } |
0d4c07af | 10638 | #endif |
b121eeb9 | 10639 | |
6c265988 | 10640 | void _initialize_arm_tdep (); |
c906108c | 10641 | void |
6c265988 | 10642 | _initialize_arm_tdep () |
c906108c | 10643 | { |
bc90b915 | 10644 | long length; |
65b48a81 | 10645 | int i, j; |
edefbb7c AC |
10646 | char regdesc[1024], *rdptr = regdesc; |
10647 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 10648 | |
42cf1509 | 10649 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 10650 | |
0e9e9abd | 10651 | /* Add ourselves to objfile event chain. */ |
c90e7d63 | 10652 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile, "arm-tdep"); |
0e9e9abd | 10653 | |
70f80edf JT |
10654 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
10655 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
10656 | bfd_target_elf_flavour, | |
10657 | arm_elf_osabi_sniffer); | |
10658 | ||
afd7eef0 | 10659 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
f54bdb6d SM |
10660 | add_setshow_prefix_cmd ("arm", no_class, |
10661 | _("Various ARM-specific commands."), | |
10662 | _("Various ARM-specific commands."), | |
10663 | &setarmcmdlist, &showarmcmdlist, | |
10664 | &setlist, &showlist); | |
c5aa993b | 10665 | |
65b48a81 | 10666 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
10667 | const disasm_options_t *disasm_options |
10668 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
10669 | int num_disassembly_styles = 0; |
10670 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10671 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10672 | num_disassembly_styles++; |
10673 | ||
10674 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 10675 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
10676 | num_disassembly_styles + 1); |
10677 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10678 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10679 | { |
10680 | size_t offset = strlen ("reg-names-"); | |
10681 | const char *style = disasm_options->name[i]; | |
10682 | valid_disassembly_styles[j++] = &style[offset]; | |
dedb7102 TT |
10683 | if (strcmp (&style[offset], "std") == 0) |
10684 | disassembly_style = &style[offset]; | |
65b48a81 PB |
10685 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], |
10686 | disasm_options->description[i]); | |
10687 | rdptr += length; | |
10688 | rest -= length; | |
10689 | } | |
94c30b78 | 10690 | /* Mark the end of valid options. */ |
65b48a81 | 10691 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 10692 | |
edefbb7c | 10693 | /* Create the help text. */ |
d7e74731 PA |
10694 | std::string helptext = string_printf ("%s%s%s", |
10695 | _("The valid values are:\n"), | |
10696 | regdesc, | |
10697 | _("The default is \"std\".")); | |
ed9a39eb | 10698 | |
edefbb7c AC |
10699 | add_setshow_enum_cmd("disassembler", no_class, |
10700 | valid_disassembly_styles, &disassembly_style, | |
10701 | _("Set the disassembly style."), | |
10702 | _("Show the disassembly style."), | |
09b0e4b0 | 10703 | helptext.c_str (), |
2c5b56ce | 10704 | set_disassembly_style_sfunc, |
65b48a81 | 10705 | show_disassembly_style_sfunc, |
7376b4c2 | 10706 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
10707 | |
10708 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
10709 | _("Set usage of ARM 32-bit mode."), | |
10710 | _("Show usage of ARM 32-bit mode."), | |
10711 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 10712 | NULL, |
0963b4bd MS |
10713 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
10714 | mode is %s. */ | |
26304000 | 10715 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 10716 | |
fd50bc42 | 10717 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
10718 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
10719 | _("Set the floating point type."), | |
10720 | _("Show the floating point type."), | |
10721 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
10722 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
10723 | fpa - FPA co-processor (GCC compiled).\n\ | |
10724 | softvfp - Software FP with pure-endian doubles.\n\ | |
10725 | vfp - VFP co-processor."), | |
edefbb7c | 10726 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 10727 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 10728 | |
28e97307 DJ |
10729 | /* Add a command to allow the user to force the ABI. */ |
10730 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
10731 | _("Set the ABI."), | |
10732 | _("Show the ABI."), | |
10733 | NULL, arm_set_abi, arm_show_abi, | |
10734 | &setarmcmdlist, &showarmcmdlist); | |
10735 | ||
0428b8f5 DJ |
10736 | /* Add two commands to allow the user to force the assumed |
10737 | execution mode. */ | |
10738 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
10739 | arm_mode_strings, &arm_fallback_mode_string, | |
10740 | _("Set the mode assumed when symbols are unavailable."), | |
10741 | _("Show the mode assumed when symbols are unavailable."), | |
10742 | NULL, NULL, arm_show_fallback_mode, | |
10743 | &setarmcmdlist, &showarmcmdlist); | |
10744 | add_setshow_enum_cmd ("force-mode", class_support, | |
10745 | arm_mode_strings, &arm_force_mode_string, | |
10746 | _("Set the mode assumed even when symbols are available."), | |
10747 | _("Show the mode assumed even when symbols are available."), | |
10748 | NULL, NULL, arm_show_force_mode, | |
10749 | &setarmcmdlist, &showarmcmdlist); | |
10750 | ||
ef273377 CL |
10751 | /* Add a command to stop triggering security exceptions when |
10752 | unwinding exception stacks. */ | |
10753 | add_setshow_boolean_cmd ("unwind-secure-frames", no_class, &arm_unwind_secure_frames, | |
10754 | _("Set usage of non-secure to secure exception stack unwinding."), | |
10755 | _("Show usage of non-secure to secure exception stack unwinding."), | |
10756 | _("When on, the debugger can trigger memory access traps."), | |
10757 | NULL, arm_show_unwind_secure_frames, | |
10758 | &setarmcmdlist, &showarmcmdlist); | |
10759 | ||
6529d2dd | 10760 | /* Debugging flag. */ |
edefbb7c AC |
10761 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
10762 | _("Set ARM debugging."), | |
10763 | _("Show ARM debugging."), | |
10764 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 10765 | NULL, |
7915a72c | 10766 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 10767 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
10768 | |
10769 | #if GDB_SELF_TEST | |
1526853e | 10770 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 10771 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
10772 | #endif |
10773 | ||
c906108c | 10774 | } |
72508ac0 PO |
10775 | |
10776 | /* ARM-reversible process record data structures. */ | |
10777 | ||
10778 | #define ARM_INSN_SIZE_BYTES 4 | |
10779 | #define THUMB_INSN_SIZE_BYTES 2 | |
10780 | #define THUMB2_INSN_SIZE_BYTES 4 | |
10781 | ||
10782 | ||
71e396f9 LM |
10783 | /* Position of the bit within a 32-bit ARM instruction |
10784 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
10785 | #define INSN_S_L_BIT_NUM 20 |
10786 | ||
10787 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10788 | do \ |
10789 | { \ | |
10790 | unsigned int reg_len = LENGTH; \ | |
10791 | if (reg_len) \ | |
10792 | { \ | |
10793 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
10794 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
10795 | } \ | |
10796 | } \ | |
10797 | while (0) | |
72508ac0 PO |
10798 | |
10799 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10800 | do \ |
10801 | { \ | |
10802 | unsigned int mem_len = LENGTH; \ | |
10803 | if (mem_len) \ | |
01add95b SM |
10804 | { \ |
10805 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
10806 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
10807 | sizeof(struct arm_mem_r) * LENGTH); \ | |
10808 | } \ | |
dda83cd7 SM |
10809 | } \ |
10810 | while (0) | |
72508ac0 PO |
10811 | |
10812 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
10813 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 10814 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
10815 | |
10816 | /* ARM memory record structure. */ | |
10817 | struct arm_mem_r | |
10818 | { | |
10819 | uint32_t len; /* Record length. */ | |
bfbbec00 | 10820 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
10821 | }; |
10822 | ||
10823 | /* ARM instruction record contains opcode of current insn | |
10824 | and execution state (before entry to decode_insn()), | |
10825 | contains list of to-be-modified registers and | |
10826 | memory blocks (on return from decode_insn()). */ | |
10827 | ||
4748a9be | 10828 | struct arm_insn_decode_record |
72508ac0 PO |
10829 | { |
10830 | struct gdbarch *gdbarch; | |
10831 | struct regcache *regcache; | |
10832 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
10833 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
10834 | uint32_t cond; /* Condition code. */ | |
10835 | uint32_t opcode; /* Insn opcode. */ | |
10836 | uint32_t decode; /* Insn decode bits. */ | |
10837 | uint32_t mem_rec_count; /* No of mem records. */ | |
10838 | uint32_t reg_rec_count; /* No of reg records. */ | |
10839 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
10840 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
4748a9be | 10841 | }; |
72508ac0 PO |
10842 | |
10843 | ||
10844 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
10845 | ||
10846 | static int | |
10847 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
10848 | { | |
10849 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
10850 | ||
10851 | if (!len) | |
10852 | return 1; | |
10853 | ||
10854 | if (!sbo) | |
10855 | ones = ~ones; | |
10856 | ||
10857 | while (ones) | |
10858 | { | |
10859 | if (!(ones & sbo)) | |
dda83cd7 SM |
10860 | { |
10861 | return 0; | |
10862 | } | |
72508ac0 PO |
10863 | ones = ones >> 1; |
10864 | } | |
10865 | return 1; | |
10866 | } | |
10867 | ||
c6ec2b30 OJ |
10868 | enum arm_record_result |
10869 | { | |
10870 | ARM_RECORD_SUCCESS = 0, | |
10871 | ARM_RECORD_FAILURE = 1 | |
10872 | }; | |
10873 | ||
0d1703b8 | 10874 | enum arm_record_strx_t |
72508ac0 PO |
10875 | { |
10876 | ARM_RECORD_STRH=1, | |
10877 | ARM_RECORD_STRD | |
0d1703b8 | 10878 | }; |
72508ac0 | 10879 | |
0d1703b8 | 10880 | enum record_type_t |
72508ac0 PO |
10881 | { |
10882 | ARM_RECORD=1, | |
10883 | THUMB_RECORD, | |
10884 | THUMB2_RECORD | |
0d1703b8 | 10885 | }; |
72508ac0 PO |
10886 | |
10887 | ||
10888 | static int | |
4748a9be | 10889 | arm_record_strx (arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, |
dda83cd7 | 10890 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
10891 | { |
10892 | ||
10893 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10894 | ULONGEST u_regval[2]= {0}; | |
10895 | ||
10896 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
10897 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
10898 | |
10899 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10900 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
10901 | |
10902 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10903 | { | |
10904 | /* 1) Handle misc store, immediate offset. */ | |
10905 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10906 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10907 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10908 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 10909 | &u_regval[0]); |
72508ac0 | 10910 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
10911 | { |
10912 | /* If R15 was used as Rn, hence current PC+8. */ | |
10913 | u_regval[0] = u_regval[0] + 8; | |
10914 | } | |
72508ac0 PO |
10915 | offset_8 = (immed_high << 4) | immed_low; |
10916 | /* Calculate target store address. */ | |
10917 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
10918 | { |
10919 | tgt_mem_addr = u_regval[0] + offset_8; | |
10920 | } | |
72508ac0 | 10921 | else |
dda83cd7 SM |
10922 | { |
10923 | tgt_mem_addr = u_regval[0] - offset_8; | |
10924 | } | |
72508ac0 | 10925 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10926 | { |
10927 | record_buf_mem[0] = 2; | |
10928 | record_buf_mem[1] = tgt_mem_addr; | |
10929 | arm_insn_r->mem_rec_count = 1; | |
10930 | } | |
72508ac0 | 10931 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10932 | { |
10933 | record_buf_mem[0] = 4; | |
10934 | record_buf_mem[1] = tgt_mem_addr; | |
10935 | record_buf_mem[2] = 4; | |
10936 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10937 | arm_insn_r->mem_rec_count = 2; | |
10938 | } | |
72508ac0 PO |
10939 | } |
10940 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
10941 | { | |
10942 | /* 2) Store, register offset. */ | |
10943 | /* Get Rm. */ | |
10944 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10945 | /* Get Rn. */ | |
10946 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10947 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10948 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10949 | if (15 == reg_src2) | |
dda83cd7 SM |
10950 | { |
10951 | /* If R15 was used as Rn, hence current PC+8. */ | |
10952 | u_regval[0] = u_regval[0] + 8; | |
10953 | } | |
72508ac0 PO |
10954 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
10955 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
10956 | { |
10957 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10958 | } | |
72508ac0 | 10959 | else |
dda83cd7 SM |
10960 | { |
10961 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10962 | } | |
72508ac0 | 10963 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10964 | { |
10965 | record_buf_mem[0] = 2; | |
10966 | record_buf_mem[1] = tgt_mem_addr; | |
10967 | arm_insn_r->mem_rec_count = 1; | |
10968 | } | |
72508ac0 | 10969 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10970 | { |
10971 | record_buf_mem[0] = 4; | |
10972 | record_buf_mem[1] = tgt_mem_addr; | |
10973 | record_buf_mem[2] = 4; | |
10974 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10975 | arm_insn_r->mem_rec_count = 2; | |
10976 | } | |
72508ac0 PO |
10977 | } |
10978 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 10979 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
10980 | { |
10981 | /* 3) Store, immediate pre-indexed. */ | |
10982 | /* 5) Store, immediate post-indexed. */ | |
10983 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10984 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10985 | offset_8 = (immed_high << 4) | immed_low; | |
10986 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10987 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10988 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10989 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
10990 | { |
10991 | tgt_mem_addr = u_regval[0] + offset_8; | |
10992 | } | |
72508ac0 | 10993 | else |
dda83cd7 SM |
10994 | { |
10995 | tgt_mem_addr = u_regval[0] - offset_8; | |
10996 | } | |
72508ac0 | 10997 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10998 | { |
10999 | record_buf_mem[0] = 2; | |
11000 | record_buf_mem[1] = tgt_mem_addr; | |
11001 | arm_insn_r->mem_rec_count = 1; | |
11002 | } | |
72508ac0 | 11003 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11004 | { |
11005 | record_buf_mem[0] = 4; | |
11006 | record_buf_mem[1] = tgt_mem_addr; | |
11007 | record_buf_mem[2] = 4; | |
11008 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11009 | arm_insn_r->mem_rec_count = 2; | |
11010 | } | |
72508ac0 PO |
11011 | /* Record Rn also as it changes. */ |
11012 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11013 | arm_insn_r->reg_rec_count = 1; | |
11014 | } | |
11015 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 11016 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
11017 | { |
11018 | /* 4) Store, register pre-indexed. */ | |
11019 | /* 6) Store, register post -indexed. */ | |
11020 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11021 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11022 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11023 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11024 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11025 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
11026 | { |
11027 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11028 | } | |
72508ac0 | 11029 | else |
dda83cd7 SM |
11030 | { |
11031 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11032 | } | |
72508ac0 | 11033 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
11034 | { |
11035 | record_buf_mem[0] = 2; | |
11036 | record_buf_mem[1] = tgt_mem_addr; | |
11037 | arm_insn_r->mem_rec_count = 1; | |
11038 | } | |
72508ac0 | 11039 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
11040 | { |
11041 | record_buf_mem[0] = 4; | |
11042 | record_buf_mem[1] = tgt_mem_addr; | |
11043 | record_buf_mem[2] = 4; | |
11044 | record_buf_mem[3] = tgt_mem_addr + 4; | |
11045 | arm_insn_r->mem_rec_count = 2; | |
11046 | } | |
72508ac0 PO |
11047 | /* Record Rn also as it changes. */ |
11048 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
11049 | arm_insn_r->reg_rec_count = 1; | |
11050 | } | |
11051 | return 0; | |
11052 | } | |
11053 | ||
11054 | /* Handling ARM extension space insns. */ | |
11055 | ||
11056 | static int | |
4748a9be | 11057 | arm_record_extension_space (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 11058 | { |
df95a9cf | 11059 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
11060 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
11061 | uint32_t record_buf[8], record_buf_mem[8]; | |
11062 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
11063 | struct regcache *reg_cache = arm_insn_r->regcache; |
11064 | ULONGEST u_regval = 0; | |
11065 | ||
11066 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
11067 | /* Handle unconditional insn extension space. */ | |
11068 | ||
11069 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
11070 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11071 | if (arm_insn_r->cond) | |
11072 | { | |
11073 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 11074 | the caches. */ |
72508ac0 | 11075 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
11076 | { |
11077 | /* BLX(1) */ | |
11078 | record_buf[0] = ARM_PS_REGNUM; | |
11079 | record_buf[1] = ARM_LR_REGNUM; | |
11080 | arm_insn_r->reg_rec_count = 2; | |
11081 | } | |
72508ac0 PO |
11082 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
11083 | } | |
11084 | ||
11085 | ||
11086 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11087 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
11088 | { | |
11089 | ret = -1; | |
11090 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 11091 | versions define it. */ |
72508ac0 PO |
11092 | } |
11093 | ||
11094 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
11095 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
11096 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11097 | ||
11098 | /* Handle arithmetic insn extension space. */ | |
11099 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
11100 | && !INSN_RECORDED(arm_insn_r)) | |
11101 | { | |
11102 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 11103 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
01add95b SM |
11104 | { |
11105 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11106 | record_buf[1] = ARM_PS_REGNUM; | |
11107 | arm_insn_r->reg_rec_count = 2; | |
11108 | } | |
b020ff80 | 11109 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
01add95b SM |
11110 | { |
11111 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
11112 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11113 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11114 | record_buf[2] = ARM_PS_REGNUM; | |
11115 | arm_insn_r->reg_rec_count = 3; | |
11116 | } | |
72508ac0 PO |
11117 | } |
11118 | ||
11119 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
11120 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
11121 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
11122 | ||
11123 | /* Handle control insn extension space. */ | |
11124 | ||
11125 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
11126 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
11127 | { | |
11128 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
11129 | { |
11130 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
11131 | { | |
11132 | if ((0 == insn_op1) || (2 == insn_op1)) | |
11133 | { | |
11134 | /* MRS. */ | |
11135 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11136 | arm_insn_r->reg_rec_count = 1; | |
11137 | } | |
11138 | else if (1 == insn_op1) | |
11139 | { | |
11140 | /* CSPR is going to be changed. */ | |
11141 | record_buf[0] = ARM_PS_REGNUM; | |
11142 | arm_insn_r->reg_rec_count = 1; | |
11143 | } | |
11144 | else if (3 == insn_op1) | |
11145 | { | |
11146 | /* SPSR is going to be changed. */ | |
11147 | /* We need to get SPSR value, which is yet to be done. */ | |
11148 | return -1; | |
11149 | } | |
11150 | } | |
11151 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11152 | { | |
11153 | if (1 == insn_op1) | |
11154 | { | |
11155 | /* BX. */ | |
11156 | record_buf[0] = ARM_PS_REGNUM; | |
11157 | arm_insn_r->reg_rec_count = 1; | |
11158 | } | |
11159 | else if (3 == insn_op1) | |
11160 | { | |
11161 | /* CLZ. */ | |
11162 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11163 | arm_insn_r->reg_rec_count = 1; | |
11164 | } | |
11165 | } | |
11166 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11167 | { | |
11168 | /* BLX. */ | |
11169 | record_buf[0] = ARM_PS_REGNUM; | |
11170 | record_buf[1] = ARM_LR_REGNUM; | |
11171 | arm_insn_r->reg_rec_count = 2; | |
11172 | } | |
11173 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11174 | { | |
11175 | /* QADD, QSUB, QDADD, QDSUB */ | |
11176 | record_buf[0] = ARM_PS_REGNUM; | |
11177 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11178 | arm_insn_r->reg_rec_count = 2; | |
11179 | } | |
11180 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
11181 | { | |
11182 | /* BKPT. */ | |
11183 | record_buf[0] = ARM_PS_REGNUM; | |
11184 | record_buf[1] = ARM_LR_REGNUM; | |
11185 | arm_insn_r->reg_rec_count = 2; | |
11186 | ||
11187 | /* Save SPSR also;how? */ | |
11188 | return -1; | |
11189 | } | |
11190 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
11191 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
11192 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
11193 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
11194 | ) | |
11195 | { | |
11196 | if (0 == insn_op1 || 1 == insn_op1) | |
11197 | { | |
11198 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
11199 | /* We dont do optimization for SMULW<y> where we | |
11200 | need only Rd. */ | |
11201 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11202 | record_buf[1] = ARM_PS_REGNUM; | |
11203 | arm_insn_r->reg_rec_count = 2; | |
11204 | } | |
11205 | else if (2 == insn_op1) | |
11206 | { | |
11207 | /* SMLAL<x><y>. */ | |
11208 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11209 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11210 | arm_insn_r->reg_rec_count = 2; | |
11211 | } | |
11212 | else if (3 == insn_op1) | |
11213 | { | |
11214 | /* SMUL<x><y>. */ | |
11215 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11216 | arm_insn_r->reg_rec_count = 1; | |
11217 | } | |
11218 | } | |
11219 | } | |
72508ac0 | 11220 | else |
dda83cd7 SM |
11221 | { |
11222 | /* MSR : immediate form. */ | |
11223 | if (1 == insn_op1) | |
11224 | { | |
11225 | /* CSPR is going to be changed. */ | |
11226 | record_buf[0] = ARM_PS_REGNUM; | |
11227 | arm_insn_r->reg_rec_count = 1; | |
11228 | } | |
11229 | else if (3 == insn_op1) | |
11230 | { | |
11231 | /* SPSR is going to be changed. */ | |
11232 | /* we need to get SPSR value, which is yet to be done */ | |
11233 | return -1; | |
11234 | } | |
11235 | } | |
72508ac0 PO |
11236 | } |
11237 | ||
11238 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
11239 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
11240 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
11241 | ||
11242 | /* Handle load/store insn extension space. */ | |
11243 | ||
11244 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
11245 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
11246 | && !INSN_RECORDED(arm_insn_r)) | |
11247 | { | |
11248 | /* SWP/SWPB. */ | |
11249 | if (0 == insn_op1) | |
dda83cd7 SM |
11250 | { |
11251 | /* These insn, changes register and memory as well. */ | |
11252 | /* SWP or SWPB insn. */ | |
11253 | /* Get memory address given by Rn. */ | |
11254 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11255 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
11256 | /* SWP insn ?, swaps word. */ | |
11257 | if (8 == arm_insn_r->opcode) | |
11258 | { | |
11259 | record_buf_mem[0] = 4; | |
11260 | } | |
11261 | else | |
11262 | { | |
11263 | /* SWPB insn, swaps only byte. */ | |
11264 | record_buf_mem[0] = 1; | |
11265 | } | |
11266 | record_buf_mem[1] = u_regval; | |
11267 | arm_insn_r->mem_rec_count = 1; | |
11268 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11269 | arm_insn_r->reg_rec_count = 1; | |
11270 | } | |
72508ac0 | 11271 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11272 | { |
11273 | /* STRH. */ | |
11274 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11275 | ARM_RECORD_STRH); | |
11276 | } | |
72508ac0 | 11277 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11278 | { |
11279 | /* LDRD. */ | |
11280 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11281 | record_buf[1] = record_buf[0] + 1; | |
11282 | arm_insn_r->reg_rec_count = 2; | |
11283 | } | |
72508ac0 | 11284 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
11285 | { |
11286 | /* STRD. */ | |
11287 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
11288 | ARM_RECORD_STRD); | |
11289 | } | |
72508ac0 | 11290 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
11291 | { |
11292 | /* LDRH, LDRSB, LDRSH. */ | |
11293 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11294 | arm_insn_r->reg_rec_count = 1; | |
11295 | } | |
72508ac0 PO |
11296 | |
11297 | } | |
11298 | ||
11299 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
11300 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
11301 | && !INSN_RECORDED(arm_insn_r)) | |
11302 | { | |
11303 | ret = -1; | |
11304 | /* Handle coprocessor insn extension space. */ | |
11305 | } | |
11306 | ||
11307 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
11308 | if (-1 == ret) | |
ca92db2d | 11309 | return ret; |
72508ac0 PO |
11310 | |
11311 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11312 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11313 | ||
11314 | return ret; | |
11315 | } | |
11316 | ||
11317 | /* Handling opcode 000 insns. */ | |
11318 | ||
11319 | static int | |
4748a9be | 11320 | arm_record_data_proc_misc_ld_str (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11321 | { |
11322 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11323 | uint32_t record_buf[8], record_buf_mem[8]; | |
11324 | ULONGEST u_regval[2] = {0}; | |
11325 | ||
8d49165d | 11326 | uint32_t reg_src1 = 0; |
72508ac0 PO |
11327 | uint32_t opcode1 = 0; |
11328 | ||
11329 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11330 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11331 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
11332 | ||
2d9e6acb | 11333 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11334 | { |
2d9e6acb YQ |
11335 | /* Data-processing (register) and Data-processing (register-shifted |
11336 | register */ | |
11337 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
11338 | register, which is specified by 13-16 decode. */ | |
11339 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11340 | record_buf[1] = ARM_PS_REGNUM; | |
11341 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 11342 | } |
2d9e6acb | 11343 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 11344 | { |
2d9e6acb YQ |
11345 | /* Miscellaneous instructions */ |
11346 | ||
11347 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
11348 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11349 | { | |
11350 | /* Handle BLX, branch and link/exchange. */ | |
11351 | if (9 == arm_insn_r->opcode) | |
11352 | { | |
11353 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
11354 | and R14 stores the return address. */ | |
11355 | record_buf[0] = ARM_PS_REGNUM; | |
11356 | record_buf[1] = ARM_LR_REGNUM; | |
11357 | arm_insn_r->reg_rec_count = 2; | |
11358 | } | |
11359 | } | |
11360 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
11361 | { | |
11362 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
11363 | /* CPSR is changed to be executed in ARM state, disabling normal | |
11364 | interrupts, entering abort mode. */ | |
11365 | /* According to high vector configuration PC is set. */ | |
11366 | /* user hit breakpoint and type reverse, in | |
11367 | that case, we need to go back with previous CPSR and | |
11368 | Program Counter. */ | |
11369 | record_buf[0] = ARM_PS_REGNUM; | |
11370 | record_buf[1] = ARM_LR_REGNUM; | |
11371 | arm_insn_r->reg_rec_count = 2; | |
11372 | ||
11373 | /* Save SPSR also; how? */ | |
11374 | return -1; | |
11375 | } | |
11376 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
11377 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
11378 | { | |
11379 | /* Handle BX, branch and link/exchange. */ | |
11380 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
11381 | record_buf[0] = ARM_PS_REGNUM; | |
11382 | arm_insn_r->reg_rec_count = 1; | |
11383 | } | |
11384 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
11385 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
11386 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
11387 | { | |
11388 | /* Count leading zeros: CLZ. */ | |
11389 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11390 | arm_insn_r->reg_rec_count = 1; | |
11391 | } | |
11392 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
11393 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
11394 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
11395 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
11396 | { | |
11397 | /* Handle MRS insn. */ | |
11398 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11399 | arm_insn_r->reg_rec_count = 1; | |
11400 | } | |
72508ac0 | 11401 | } |
2d9e6acb | 11402 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 11403 | { |
2d9e6acb YQ |
11404 | /* Multiply and multiply-accumulate */ |
11405 | ||
11406 | /* Handle multiply instructions. */ | |
11407 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
11408 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
f2a883a8 SM |
11409 | { |
11410 | /* Handle MLA and MUL. */ | |
11411 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11412 | record_buf[1] = ARM_PS_REGNUM; | |
11413 | arm_insn_r->reg_rec_count = 2; | |
11414 | } | |
11415 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
11416 | { | |
11417 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
11418 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
11419 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
11420 | record_buf[2] = ARM_PS_REGNUM; | |
11421 | arm_insn_r->reg_rec_count = 3; | |
11422 | } | |
2d9e6acb YQ |
11423 | } |
11424 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
11425 | { | |
11426 | /* Synchronization primitives */ | |
11427 | ||
72508ac0 PO |
11428 | /* Handling SWP, SWPB. */ |
11429 | /* These insn, changes register and memory as well. */ | |
11430 | /* SWP or SWPB insn. */ | |
11431 | ||
11432 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
11433 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11434 | /* SWP insn ?, swaps word. */ | |
11435 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
11436 | { |
11437 | record_buf_mem[0] = 4; | |
11438 | } | |
11439 | else | |
11440 | { | |
11441 | /* SWPB insn, swaps only byte. */ | |
11442 | record_buf_mem[0] = 1; | |
11443 | } | |
72508ac0 PO |
11444 | record_buf_mem[1] = u_regval[0]; |
11445 | arm_insn_r->mem_rec_count = 1; | |
11446 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11447 | arm_insn_r->reg_rec_count = 1; | |
11448 | } | |
2d9e6acb YQ |
11449 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
11450 | || 15 == arm_insn_r->decode) | |
72508ac0 | 11451 | { |
2d9e6acb YQ |
11452 | if ((opcode1 & 0x12) == 2) |
11453 | { | |
11454 | /* Extra load/store (unprivileged) */ | |
11455 | return -1; | |
11456 | } | |
11457 | else | |
11458 | { | |
11459 | /* Extra load/store */ | |
11460 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
11461 | { | |
11462 | case 1: | |
11463 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
11464 | { | |
11465 | /* STRH (register), STRH (immediate) */ | |
11466 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11467 | &record_buf_mem[0], ARM_RECORD_STRH); | |
11468 | } | |
11469 | else if ((opcode1 & 0x05) == 0x1) | |
11470 | { | |
11471 | /* LDRH (register) */ | |
11472 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11473 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 11474 | |
2d9e6acb YQ |
11475 | if (bit (arm_insn_r->arm_insn, 21)) |
11476 | { | |
11477 | /* Write back to Rn. */ | |
11478 | record_buf[arm_insn_r->reg_rec_count++] | |
11479 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11480 | } | |
11481 | } | |
11482 | else if ((opcode1 & 0x05) == 0x5) | |
11483 | { | |
11484 | /* LDRH (immediate), LDRH (literal) */ | |
11485 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11486 | |
2d9e6acb YQ |
11487 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11488 | arm_insn_r->reg_rec_count = 1; | |
11489 | ||
11490 | if (rn != 15) | |
11491 | { | |
11492 | /*LDRH (immediate) */ | |
11493 | if (bit (arm_insn_r->arm_insn, 21)) | |
11494 | { | |
11495 | /* Write back to Rn. */ | |
11496 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11497 | } | |
11498 | } | |
11499 | } | |
11500 | else | |
11501 | return -1; | |
11502 | break; | |
11503 | case 2: | |
11504 | if ((opcode1 & 0x05) == 0x0) | |
11505 | { | |
11506 | /* LDRD (register) */ | |
11507 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11508 | record_buf[1] = record_buf[0] + 1; | |
11509 | arm_insn_r->reg_rec_count = 2; | |
11510 | ||
11511 | if (bit (arm_insn_r->arm_insn, 21)) | |
11512 | { | |
11513 | /* Write back to Rn. */ | |
11514 | record_buf[arm_insn_r->reg_rec_count++] | |
11515 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11516 | } | |
11517 | } | |
11518 | else if ((opcode1 & 0x05) == 0x1) | |
11519 | { | |
11520 | /* LDRSB (register) */ | |
11521 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11522 | arm_insn_r->reg_rec_count = 1; | |
11523 | ||
11524 | if (bit (arm_insn_r->arm_insn, 21)) | |
11525 | { | |
11526 | /* Write back to Rn. */ | |
11527 | record_buf[arm_insn_r->reg_rec_count++] | |
11528 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11529 | } | |
11530 | } | |
11531 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
11532 | { | |
11533 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
11534 | LDRSB (literal) */ | |
11535 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11536 | ||
11537 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11538 | arm_insn_r->reg_rec_count = 1; | |
11539 | ||
11540 | if (rn != 15) | |
11541 | { | |
11542 | /*LDRD (immediate), LDRSB (immediate) */ | |
11543 | if (bit (arm_insn_r->arm_insn, 21)) | |
11544 | { | |
11545 | /* Write back to Rn. */ | |
11546 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
11547 | } | |
11548 | } | |
11549 | } | |
11550 | else | |
11551 | return -1; | |
11552 | break; | |
11553 | case 3: | |
11554 | if ((opcode1 & 0x05) == 0x0) | |
11555 | { | |
11556 | /* STRD (register) */ | |
11557 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11558 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11559 | } | |
11560 | else if ((opcode1 & 0x05) == 0x1) | |
11561 | { | |
11562 | /* LDRSH (register) */ | |
11563 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11564 | arm_insn_r->reg_rec_count = 1; | |
11565 | ||
11566 | if (bit (arm_insn_r->arm_insn, 21)) | |
11567 | { | |
11568 | /* Write back to Rn. */ | |
11569 | record_buf[arm_insn_r->reg_rec_count++] | |
11570 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11571 | } | |
11572 | } | |
11573 | else if ((opcode1 & 0x05) == 0x4) | |
11574 | { | |
11575 | /* STRD (immediate) */ | |
11576 | arm_record_strx (arm_insn_r, &record_buf[0], | |
11577 | &record_buf_mem[0], ARM_RECORD_STRD); | |
11578 | } | |
11579 | else if ((opcode1 & 0x05) == 0x5) | |
11580 | { | |
11581 | /* LDRSH (immediate), LDRSH (literal) */ | |
11582 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11583 | arm_insn_r->reg_rec_count = 1; | |
11584 | ||
11585 | if (bit (arm_insn_r->arm_insn, 21)) | |
11586 | { | |
11587 | /* Write back to Rn. */ | |
11588 | record_buf[arm_insn_r->reg_rec_count++] | |
11589 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11590 | } | |
11591 | } | |
11592 | else | |
11593 | return -1; | |
11594 | break; | |
11595 | default: | |
11596 | return -1; | |
11597 | } | |
11598 | } | |
72508ac0 PO |
11599 | } |
11600 | else | |
11601 | { | |
11602 | return -1; | |
11603 | } | |
11604 | ||
11605 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11606 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11607 | return 0; | |
11608 | } | |
11609 | ||
11610 | /* Handling opcode 001 insns. */ | |
11611 | ||
11612 | static int | |
4748a9be | 11613 | arm_record_data_proc_imm (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11614 | { |
11615 | uint32_t record_buf[8], record_buf_mem[8]; | |
11616 | ||
11617 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
11618 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11619 | ||
11620 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
11621 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
11622 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
11623 | ) | |
11624 | { | |
11625 | /* Handle MSR insn. */ | |
11626 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
11627 | { |
11628 | /* CSPR is going to be changed. */ | |
11629 | record_buf[0] = ARM_PS_REGNUM; | |
11630 | arm_insn_r->reg_rec_count = 1; | |
11631 | } | |
72508ac0 | 11632 | else |
dda83cd7 SM |
11633 | { |
11634 | /* SPSR is going to be changed. */ | |
11635 | } | |
72508ac0 PO |
11636 | } |
11637 | else if (arm_insn_r->opcode <= 15) | |
11638 | { | |
11639 | /* Normal data processing insns. */ | |
11640 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 11641 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
11642 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11643 | record_buf[1] = ARM_PS_REGNUM; | |
11644 | arm_insn_r->reg_rec_count = 2; | |
11645 | } | |
11646 | else | |
11647 | { | |
11648 | return -1; | |
11649 | } | |
11650 | ||
11651 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11652 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11653 | return 0; | |
11654 | } | |
11655 | ||
c55978a6 | 11656 | static int |
4748a9be | 11657 | arm_record_media (arm_insn_decode_record *arm_insn_r) |
c55978a6 YQ |
11658 | { |
11659 | uint32_t record_buf[8]; | |
11660 | ||
11661 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
11662 | { | |
11663 | case 0: | |
11664 | /* Parallel addition and subtraction, signed */ | |
11665 | case 1: | |
11666 | /* Parallel addition and subtraction, unsigned */ | |
11667 | case 2: | |
11668 | case 3: | |
11669 | /* Packing, unpacking, saturation and reversal */ | |
11670 | { | |
11671 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
11672 | ||
11673 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11674 | } | |
11675 | break; | |
11676 | ||
11677 | case 4: | |
11678 | case 5: | |
11679 | /* Signed multiplies */ | |
11680 | { | |
11681 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
11682 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
11683 | ||
11684 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11685 | if (op1 == 0x0) | |
11686 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11687 | else if (op1 == 0x4) | |
11688 | record_buf[arm_insn_r->reg_rec_count++] | |
11689 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11690 | } | |
11691 | break; | |
11692 | ||
11693 | case 6: | |
11694 | { | |
11695 | if (bit (arm_insn_r->arm_insn, 21) | |
11696 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
11697 | { | |
11698 | /* SBFX */ | |
11699 | record_buf[arm_insn_r->reg_rec_count++] | |
11700 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11701 | } | |
11702 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
11703 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
11704 | { | |
11705 | /* USAD8 and USADA8 */ | |
11706 | record_buf[arm_insn_r->reg_rec_count++] | |
11707 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11708 | } | |
11709 | } | |
11710 | break; | |
11711 | ||
11712 | case 7: | |
11713 | { | |
11714 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
11715 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
11716 | { | |
11717 | /* Permanently UNDEFINED */ | |
11718 | return -1; | |
11719 | } | |
11720 | else | |
11721 | { | |
11722 | /* BFC, BFI and UBFX */ | |
11723 | record_buf[arm_insn_r->reg_rec_count++] | |
11724 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11725 | } | |
11726 | } | |
11727 | break; | |
11728 | ||
11729 | default: | |
11730 | return -1; | |
11731 | } | |
11732 | ||
11733 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11734 | ||
11735 | return 0; | |
11736 | } | |
11737 | ||
71e396f9 | 11738 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
11739 | |
11740 | static int | |
4748a9be | 11741 | arm_record_ld_st_imm_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11742 | { |
11743 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11744 | ||
71e396f9 LM |
11745 | uint32_t reg_base , reg_dest; |
11746 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 11747 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
11748 | unsigned char wback; |
11749 | ULONGEST u_regval; | |
72508ac0 | 11750 | |
71e396f9 LM |
11751 | /* Calculate wback. */ |
11752 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
11753 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 11754 | |
71e396f9 LM |
11755 | arm_insn_r->reg_rec_count = 0; |
11756 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
11757 | |
11758 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11759 | { | |
71e396f9 LM |
11760 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
11761 | and LDRT. */ | |
11762 | ||
72508ac0 | 11763 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
11764 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
11765 | ||
11766 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
11767 | preceeds a LDR instruction having R15 as reg_base, it | |
11768 | emulates a branch and link instruction, and hence we need to save | |
11769 | CPSR and PC as well. */ | |
11770 | if (ARM_PC_REGNUM == reg_dest) | |
11771 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11772 | ||
11773 | /* If wback is true, also save the base register, which is going to be | |
11774 | written to. */ | |
11775 | if (wback) | |
11776 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11777 | } |
11778 | else | |
11779 | { | |
71e396f9 LM |
11780 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
11781 | ||
72508ac0 | 11782 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
11783 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
11784 | ||
11785 | /* Handle bit U. */ | |
72508ac0 | 11786 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
11787 | { |
11788 | /* U == 1: Add the offset. */ | |
11789 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
11790 | } | |
72508ac0 | 11791 | else |
71e396f9 LM |
11792 | { |
11793 | /* U == 0: subtract the offset. */ | |
11794 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
11795 | } | |
11796 | ||
11797 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
11798 | bytes. */ | |
11799 | if (bit (arm_insn_r->arm_insn, 22)) | |
11800 | { | |
11801 | /* STRB and STRBT: 1 byte. */ | |
11802 | record_buf_mem[0] = 1; | |
11803 | } | |
11804 | else | |
11805 | { | |
11806 | /* STR and STRT: 4 bytes. */ | |
11807 | record_buf_mem[0] = 4; | |
11808 | } | |
11809 | ||
11810 | /* Handle bit P. */ | |
11811 | if (bit (arm_insn_r->arm_insn, 24)) | |
11812 | record_buf_mem[1] = tgt_mem_addr; | |
11813 | else | |
11814 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 11815 | |
72508ac0 PO |
11816 | arm_insn_r->mem_rec_count = 1; |
11817 | ||
71e396f9 LM |
11818 | /* If wback is true, also save the base register, which is going to be |
11819 | written to. */ | |
11820 | if (wback) | |
11821 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11822 | } |
11823 | ||
11824 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11825 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11826 | return 0; | |
11827 | } | |
11828 | ||
11829 | /* Handling opcode 011 insns. */ | |
11830 | ||
11831 | static int | |
4748a9be | 11832 | arm_record_ld_st_reg_offset (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
11833 | { |
11834 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11835 | ||
11836 | uint32_t shift_imm = 0; | |
11837 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
11838 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
11839 | uint32_t record_buf[8], record_buf_mem[8]; | |
11840 | ||
11841 | LONGEST s_word; | |
11842 | ULONGEST u_regval[2]; | |
11843 | ||
c55978a6 YQ |
11844 | if (bit (arm_insn_r->arm_insn, 4)) |
11845 | return arm_record_media (arm_insn_r); | |
11846 | ||
72508ac0 PO |
11847 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
11848 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11849 | ||
11850 | /* Handle enhanced store insns and LDRD DSP insn, | |
11851 | order begins according to addressing modes for store insns | |
11852 | STRH insn. */ | |
11853 | ||
11854 | /* LDR or STR? */ | |
11855 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11856 | { | |
11857 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
11858 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
11859 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
11860 | in that case, it emulates branch and link insn, and hence we | |
11861 | need to save CSPR and PC as well. */ | |
72508ac0 | 11862 | if (15 != reg_dest) |
dda83cd7 SM |
11863 | { |
11864 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11865 | arm_insn_r->reg_rec_count = 1; | |
11866 | } | |
72508ac0 | 11867 | else |
dda83cd7 SM |
11868 | { |
11869 | record_buf[0] = reg_dest; | |
11870 | record_buf[1] = ARM_PS_REGNUM; | |
11871 | arm_insn_r->reg_rec_count = 2; | |
11872 | } | |
72508ac0 PO |
11873 | } |
11874 | else | |
11875 | { | |
11876 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
11877 | { |
11878 | /* Store insn, register offset and register pre-indexed, | |
11879 | register post-indexed. */ | |
11880 | /* Get Rm. */ | |
11881 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11882 | /* Get Rn. */ | |
11883 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11884 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
11885 | , &u_regval[0]); | |
11886 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
11887 | , &u_regval[1]); | |
11888 | if (15 == reg_src2) | |
11889 | { | |
11890 | /* If R15 was used as Rn, hence current PC+8. */ | |
11891 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
11892 | u_regval[0] = u_regval[0] + 8; | |
11893 | } | |
11894 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11895 | /* U == 1. */ | |
11896 | if (bit (arm_insn_r->arm_insn, 23)) | |
11897 | { | |
11898 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11899 | } | |
11900 | else | |
11901 | { | |
11902 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11903 | } | |
11904 | ||
11905 | switch (arm_insn_r->opcode) | |
11906 | { | |
11907 | /* STR. */ | |
11908 | case 8: | |
11909 | case 12: | |
11910 | /* STR. */ | |
11911 | case 9: | |
11912 | case 13: | |
11913 | /* STRT. */ | |
11914 | case 1: | |
11915 | case 5: | |
11916 | /* STR. */ | |
11917 | case 0: | |
11918 | case 4: | |
11919 | record_buf_mem[0] = 4; | |
11920 | break; | |
11921 | ||
11922 | /* STRB. */ | |
11923 | case 10: | |
11924 | case 14: | |
11925 | /* STRB. */ | |
11926 | case 11: | |
11927 | case 15: | |
11928 | /* STRBT. */ | |
11929 | case 3: | |
11930 | case 7: | |
11931 | /* STRB. */ | |
11932 | case 2: | |
11933 | case 6: | |
11934 | record_buf_mem[0] = 1; | |
11935 | break; | |
11936 | ||
11937 | default: | |
11938 | gdb_assert_not_reached ("no decoding pattern found"); | |
11939 | break; | |
11940 | } | |
11941 | record_buf_mem[1] = tgt_mem_addr; | |
11942 | arm_insn_r->mem_rec_count = 1; | |
11943 | ||
11944 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
11945 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
11946 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
11947 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
11948 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
11949 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
11950 | ) | |
11951 | { | |
11952 | /* Rn is going to be changed in pre-indexed mode and | |
11953 | post-indexed mode as well. */ | |
11954 | record_buf[0] = reg_src2; | |
11955 | arm_insn_r->reg_rec_count = 1; | |
11956 | } | |
11957 | } | |
72508ac0 | 11958 | else |
dda83cd7 SM |
11959 | { |
11960 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
11961 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
11962 | /* Get Rm. */ | |
11963 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11964 | /* Get Rn. */ | |
11965 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11966 | /* Get shift_imm. */ | |
11967 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
11968 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11969 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
11970 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11971 | /* Offset_12 used as shift. */ | |
11972 | switch (offset_12) | |
11973 | { | |
11974 | case 0: | |
11975 | /* Offset_12 used as index. */ | |
11976 | offset_12 = u_regval[0] << shift_imm; | |
11977 | break; | |
11978 | ||
11979 | case 1: | |
11980 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
11981 | break; | |
11982 | ||
11983 | case 2: | |
11984 | if (!shift_imm) | |
11985 | { | |
11986 | if (bit (u_regval[0], 31)) | |
11987 | { | |
11988 | offset_12 = 0xFFFFFFFF; | |
11989 | } | |
11990 | else | |
11991 | { | |
11992 | offset_12 = 0; | |
11993 | } | |
11994 | } | |
11995 | else | |
11996 | { | |
11997 | /* This is arithmetic shift. */ | |
11998 | offset_12 = s_word >> shift_imm; | |
11999 | } | |
12000 | break; | |
12001 | ||
12002 | case 3: | |
12003 | if (!shift_imm) | |
12004 | { | |
12005 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
12006 | &u_regval[1]); | |
12007 | /* Get C flag value and shift it by 31. */ | |
12008 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
12009 | | (u_regval[0]) >> 1); | |
12010 | } | |
12011 | else | |
12012 | { | |
12013 | offset_12 = (u_regval[0] >> shift_imm) \ | |
12014 | | (u_regval[0] << | |
12015 | (sizeof(uint32_t) - shift_imm)); | |
12016 | } | |
12017 | break; | |
12018 | ||
12019 | default: | |
12020 | gdb_assert_not_reached ("no decoding pattern found"); | |
12021 | break; | |
12022 | } | |
12023 | ||
12024 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12025 | /* bit U set. */ | |
12026 | if (bit (arm_insn_r->arm_insn, 23)) | |
12027 | { | |
12028 | tgt_mem_addr = u_regval[1] + offset_12; | |
12029 | } | |
12030 | else | |
12031 | { | |
12032 | tgt_mem_addr = u_regval[1] - offset_12; | |
12033 | } | |
12034 | ||
12035 | switch (arm_insn_r->opcode) | |
12036 | { | |
12037 | /* STR. */ | |
12038 | case 8: | |
12039 | case 12: | |
12040 | /* STR. */ | |
12041 | case 9: | |
12042 | case 13: | |
12043 | /* STRT. */ | |
12044 | case 1: | |
12045 | case 5: | |
12046 | /* STR. */ | |
12047 | case 0: | |
12048 | case 4: | |
12049 | record_buf_mem[0] = 4; | |
12050 | break; | |
12051 | ||
12052 | /* STRB. */ | |
12053 | case 10: | |
12054 | case 14: | |
12055 | /* STRB. */ | |
12056 | case 11: | |
12057 | case 15: | |
12058 | /* STRBT. */ | |
12059 | case 3: | |
12060 | case 7: | |
12061 | /* STRB. */ | |
12062 | case 2: | |
12063 | case 6: | |
12064 | record_buf_mem[0] = 1; | |
12065 | break; | |
12066 | ||
12067 | default: | |
12068 | gdb_assert_not_reached ("no decoding pattern found"); | |
12069 | break; | |
12070 | } | |
12071 | record_buf_mem[1] = tgt_mem_addr; | |
12072 | arm_insn_r->mem_rec_count = 1; | |
12073 | ||
12074 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
12075 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
12076 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
12077 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
12078 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
12079 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
12080 | ) | |
12081 | { | |
12082 | /* Rn is going to be changed in register scaled pre-indexed | |
12083 | mode,and scaled post indexed mode. */ | |
12084 | record_buf[0] = reg_src2; | |
12085 | arm_insn_r->reg_rec_count = 1; | |
12086 | } | |
12087 | } | |
72508ac0 PO |
12088 | } |
12089 | ||
12090 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12091 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12092 | return 0; | |
12093 | } | |
12094 | ||
71e396f9 | 12095 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
12096 | |
12097 | static int | |
4748a9be | 12098 | arm_record_ld_st_multiple (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12099 | { |
12100 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
12101 | uint32_t register_count = 0, register_bits; |
12102 | uint32_t reg_base, addr_mode; | |
72508ac0 | 12103 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
12104 | uint32_t wback; |
12105 | ULONGEST u_regval; | |
72508ac0 | 12106 | |
71e396f9 LM |
12107 | /* Fetch the list of registers. */ |
12108 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
12109 | arm_insn_r->reg_rec_count = 0; | |
12110 | ||
12111 | /* Fetch the base register that contains the address we are loading data | |
12112 | to. */ | |
12113 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 12114 | |
71e396f9 LM |
12115 | /* Calculate wback. */ |
12116 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
12117 | |
12118 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12119 | { | |
71e396f9 | 12120 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 12121 | |
71e396f9 | 12122 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 12123 | while (register_bits) |
71e396f9 LM |
12124 | { |
12125 | if (register_bits & 0x00000001) | |
12126 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
12127 | register_bits = register_bits >> 1; | |
12128 | register_count++; | |
12129 | } | |
72508ac0 | 12130 | |
71e396f9 LM |
12131 | |
12132 | /* If wback is true, also save the base register, which is going to be | |
12133 | written to. */ | |
12134 | if (wback) | |
12135 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
12136 | ||
12137 | /* Save the CPSR register. */ | |
12138 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
12139 | } |
12140 | else | |
12141 | { | |
71e396f9 | 12142 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 12143 | |
71e396f9 LM |
12144 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
12145 | ||
12146 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
12147 | ||
12148 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 12149 | while (register_bits) |
71e396f9 LM |
12150 | { |
12151 | if (register_bits & 0x00000001) | |
12152 | register_count++; | |
12153 | register_bits = register_bits >> 1; | |
12154 | } | |
72508ac0 PO |
12155 | |
12156 | switch (addr_mode) | |
71e396f9 LM |
12157 | { |
12158 | /* STMDA (STMED): Decrement after. */ | |
12159 | case 0: | |
12160 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12161 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
12162 | break; |
12163 | /* STM (STMIA, STMEA): Increment after. */ | |
12164 | case 1: | |
12165 | record_buf_mem[1] = (uint32_t) u_regval; | |
12166 | break; | |
12167 | /* STMDB (STMFD): Decrement before. */ | |
12168 | case 2: | |
12169 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 12170 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12171 | break; |
12172 | /* STMIB (STMFA): Increment before. */ | |
12173 | case 3: | |
f0452268 | 12174 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12175 | break; |
12176 | default: | |
12177 | gdb_assert_not_reached ("no decoding pattern found"); | |
12178 | break; | |
12179 | } | |
72508ac0 | 12180 | |
f0452268 | 12181 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
12182 | arm_insn_r->mem_rec_count = 1; |
12183 | ||
12184 | /* If wback is true, also save the base register, which is going to be | |
12185 | written to. */ | |
12186 | if (wback) | |
12187 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
12188 | } |
12189 | ||
12190 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12191 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12192 | return 0; | |
12193 | } | |
12194 | ||
12195 | /* Handling opcode 101 insns. */ | |
12196 | ||
12197 | static int | |
4748a9be | 12198 | arm_record_b_bl (arm_insn_decode_record *arm_insn_r) |
72508ac0 PO |
12199 | { |
12200 | uint32_t record_buf[8]; | |
12201 | ||
12202 | /* Handle B, BL, BLX(1) insns. */ | |
12203 | /* B simply branches so we do nothing here. */ | |
12204 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
12205 | extension space. */ | |
12206 | if (bit (arm_insn_r->arm_insn, 24)) | |
01add95b SM |
12207 | { |
12208 | record_buf[0] = ARM_LR_REGNUM; | |
12209 | arm_insn_r->reg_rec_count = 1; | |
12210 | } | |
72508ac0 PO |
12211 | |
12212 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12213 | ||
12214 | return 0; | |
12215 | } | |
12216 | ||
72508ac0 | 12217 | static int |
4748a9be | 12218 | arm_record_unsupported_insn (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 12219 | { |
6cb06a8c TT |
12220 | gdb_printf (gdb_stderr, |
12221 | _("Process record does not support instruction " | |
12222 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
12223 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
12224 | |
12225 | return -1; | |
12226 | } | |
12227 | ||
5a578da5 OJ |
12228 | /* Record handler for vector data transfer instructions. */ |
12229 | ||
12230 | static int | |
4748a9be | 12231 | arm_record_vdata_transfer_insn (arm_insn_decode_record *arm_insn_r) |
5a578da5 OJ |
12232 | { |
12233 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
12234 | uint32_t record_buf[4]; | |
12235 | ||
5a578da5 OJ |
12236 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
12237 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
12238 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
12239 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
12240 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
12241 | ||
12242 | /* Handle VMOV instruction. */ | |
12243 | if (bit_l && bit_c) | |
12244 | { | |
12245 | record_buf[0] = reg_t; | |
12246 | arm_insn_r->reg_rec_count = 1; | |
12247 | } | |
12248 | else if (bit_l && !bit_c) | |
12249 | { | |
12250 | /* Handle VMOV instruction. */ | |
12251 | if (bits_a == 0x00) | |
dda83cd7 | 12252 | { |
f1771dce | 12253 | record_buf[0] = reg_t; |
dda83cd7 SM |
12254 | arm_insn_r->reg_rec_count = 1; |
12255 | } | |
5a578da5 OJ |
12256 | /* Handle VMRS instruction. */ |
12257 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12258 | { |
12259 | if (reg_t == 15) | |
12260 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 12261 | |
dda83cd7 SM |
12262 | record_buf[0] = reg_t; |
12263 | arm_insn_r->reg_rec_count = 1; | |
12264 | } | |
5a578da5 OJ |
12265 | } |
12266 | else if (!bit_l && !bit_c) | |
12267 | { | |
12268 | /* Handle VMOV instruction. */ | |
12269 | if (bits_a == 0x00) | |
dda83cd7 | 12270 | { |
f1771dce | 12271 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 12272 | |
dda83cd7 SM |
12273 | arm_insn_r->reg_rec_count = 1; |
12274 | } | |
5a578da5 OJ |
12275 | /* Handle VMSR instruction. */ |
12276 | else if (bits_a == 0x07) | |
dda83cd7 SM |
12277 | { |
12278 | record_buf[0] = ARM_FPSCR_REGNUM; | |
12279 | arm_insn_r->reg_rec_count = 1; | |
12280 | } | |
5a578da5 OJ |
12281 | } |
12282 | else if (!bit_l && bit_c) | |
12283 | { | |
12284 | /* Handle VMOV instruction. */ | |
12285 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
12286 | { |
12287 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
12288 | + ARM_D0_REGNUM; | |
12289 | arm_insn_r->reg_rec_count = 1; | |
12290 | } | |
5a578da5 OJ |
12291 | /* Handle VDUP instruction. */ |
12292 | else | |
dda83cd7 SM |
12293 | { |
12294 | if (bit (arm_insn_r->arm_insn, 21)) | |
12295 | { | |
12296 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12297 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12298 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
12299 | arm_insn_r->reg_rec_count = 2; | |
12300 | } | |
12301 | else | |
12302 | { | |
12303 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
12304 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
12305 | arm_insn_r->reg_rec_count = 1; | |
12306 | } | |
12307 | } | |
12308 | } | |
12309 | ||
12310 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12311 | return 0; | |
12312 | } | |
12313 | ||
f20f80dd OJ |
12314 | /* Record handler for extension register load/store instructions. */ |
12315 | ||
12316 | static int | |
4748a9be | 12317 | arm_record_exreg_ld_st_insn (arm_insn_decode_record *arm_insn_r) |
f20f80dd OJ |
12318 | { |
12319 | uint32_t opcode, single_reg; | |
12320 | uint8_t op_vldm_vstm; | |
12321 | uint32_t record_buf[8], record_buf_mem[128]; | |
12322 | ULONGEST u_regval = 0; | |
12323 | ||
12324 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
12325 | |
12326 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 12327 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
12328 | op_vldm_vstm = opcode & 0x1b; |
12329 | ||
12330 | /* Handle VMOV instructions. */ | |
12331 | if ((opcode & 0x1e) == 0x04) | |
12332 | { | |
9fde51ed | 12333 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
12334 | { |
12335 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12336 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12337 | arm_insn_r->reg_rec_count = 2; | |
12338 | } | |
f20f80dd | 12339 | else |
01e57735 | 12340 | { |
9fde51ed YQ |
12341 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
12342 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 12343 | |
9fde51ed | 12344 | if (single_reg) |
01e57735 | 12345 | { |
9fde51ed YQ |
12346 | /* The first S register number m is REG_M:M (M is bit 5), |
12347 | the corresponding D register number is REG_M:M / 2, which | |
12348 | is REG_M. */ | |
12349 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
12350 | /* The second S register number is REG_M:M + 1, the | |
12351 | corresponding D register number is (REG_M:M + 1) / 2. | |
12352 | IOW, if bit M is 1, the first and second S registers | |
12353 | are mapped to different D registers, otherwise, they are | |
12354 | in the same D register. */ | |
12355 | if (bit_m) | |
12356 | { | |
12357 | record_buf[arm_insn_r->reg_rec_count++] | |
12358 | = ARM_D0_REGNUM + reg_m + 1; | |
12359 | } | |
01e57735 YQ |
12360 | } |
12361 | else | |
12362 | { | |
9fde51ed | 12363 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
12364 | arm_insn_r->reg_rec_count = 1; |
12365 | } | |
12366 | } | |
f20f80dd OJ |
12367 | } |
12368 | /* Handle VSTM and VPUSH instructions. */ | |
12369 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 12370 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
12371 | { |
12372 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
12373 | uint32_t memory_index = 0; | |
12374 | ||
12375 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12376 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12377 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12378 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12379 | memory_count = imm_off8; |
12380 | ||
12381 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12382 | start_address = u_regval; |
f20f80dd | 12383 | else |
01e57735 | 12384 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12385 | |
12386 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
12387 | { |
12388 | record_buf[0] = reg_rn; | |
12389 | arm_insn_r->reg_rec_count = 1; | |
12390 | } | |
f20f80dd OJ |
12391 | |
12392 | while (memory_count > 0) | |
01e57735 | 12393 | { |
9fde51ed | 12394 | if (single_reg) |
01e57735 | 12395 | { |
9fde51ed YQ |
12396 | record_buf_mem[memory_index] = 4; |
12397 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12398 | start_address = start_address + 4; |
12399 | memory_index = memory_index + 2; | |
12400 | } | |
12401 | else | |
12402 | { | |
9fde51ed YQ |
12403 | record_buf_mem[memory_index] = 4; |
12404 | record_buf_mem[memory_index + 1] = start_address; | |
12405 | record_buf_mem[memory_index + 2] = 4; | |
12406 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12407 | start_address = start_address + 8; |
12408 | memory_index = memory_index + 4; | |
12409 | } | |
12410 | memory_count--; | |
12411 | } | |
f20f80dd OJ |
12412 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
12413 | } | |
12414 | /* Handle VLDM instructions. */ | |
12415 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 12416 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
12417 | { |
12418 | uint32_t reg_count, reg_vd; | |
12419 | uint32_t reg_index = 0; | |
9fde51ed | 12420 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
12421 | |
12422 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12423 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
12424 | ||
9fde51ed YQ |
12425 | /* REG_VD is the first D register number. If the instruction |
12426 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
12427 | number is (REG_VD << 1 | bit D), so the corresponding D | |
12428 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
12429 | if (!single_reg) | |
12430 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 12431 | |
9fde51ed | 12432 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 12433 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 12434 | |
9fde51ed YQ |
12435 | /* If the instruction loads memory to D register, REG_COUNT should |
12436 | be divided by 2, according to the ARM Architecture Reference | |
12437 | Manual. If the instruction loads memory to S register, divide by | |
12438 | 2 as well because two S registers are mapped to D register. */ | |
12439 | reg_count = reg_count / 2; | |
12440 | if (single_reg && bit_d) | |
01e57735 | 12441 | { |
9fde51ed YQ |
12442 | /* Increase the register count if S register list starts from |
12443 | an odd number (bit d is one). */ | |
12444 | reg_count++; | |
12445 | } | |
f20f80dd | 12446 | |
9fde51ed YQ |
12447 | while (reg_count > 0) |
12448 | { | |
12449 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
12450 | reg_count--; |
12451 | } | |
f20f80dd OJ |
12452 | arm_insn_r->reg_rec_count = reg_index; |
12453 | } | |
12454 | /* VSTR Vector store register. */ | |
12455 | else if ((opcode & 0x13) == 0x10) | |
12456 | { | |
bec2ab5a | 12457 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
12458 | uint32_t memory_index = 0; |
12459 | ||
12460 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
12461 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12462 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 12463 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
12464 | |
12465 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 12466 | start_address = u_regval + imm_off32; |
f20f80dd | 12467 | else |
01e57735 | 12468 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
12469 | |
12470 | if (single_reg) | |
01e57735 | 12471 | { |
9fde51ed YQ |
12472 | record_buf_mem[memory_index] = 4; |
12473 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
12474 | arm_insn_r->mem_rec_count = 1; |
12475 | } | |
f20f80dd | 12476 | else |
01e57735 | 12477 | { |
9fde51ed YQ |
12478 | record_buf_mem[memory_index] = 4; |
12479 | record_buf_mem[memory_index + 1] = start_address; | |
12480 | record_buf_mem[memory_index + 2] = 4; | |
12481 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
12482 | arm_insn_r->mem_rec_count = 2; |
12483 | } | |
f20f80dd OJ |
12484 | } |
12485 | /* VLDR Vector load register. */ | |
12486 | else if ((opcode & 0x13) == 0x11) | |
12487 | { | |
12488 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12489 | ||
12490 | if (!single_reg) | |
01e57735 YQ |
12491 | { |
12492 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
12493 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
12494 | } | |
f20f80dd | 12495 | else |
01e57735 YQ |
12496 | { |
12497 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
12498 | /* Record register D rather than pseudo register S. */ |
12499 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 12500 | } |
f20f80dd OJ |
12501 | arm_insn_r->reg_rec_count = 1; |
12502 | } | |
12503 | ||
12504 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12505 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
12506 | return 0; | |
12507 | } | |
12508 | ||
851f26ae OJ |
12509 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
12510 | ||
12511 | static int | |
4748a9be | 12512 | arm_record_vfp_data_proc_insn (arm_insn_decode_record *arm_insn_r) |
851f26ae OJ |
12513 | { |
12514 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
12515 | uint32_t record_buf[4]; | |
12516 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
12517 | enum insn_types curr_insn_type = INSN_INV; | |
12518 | ||
12519 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
12520 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
12521 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
12522 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
12523 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
12524 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
12525 | /* Mask off the "D" bit. */ |
12526 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
12527 | |
12528 | /* Handle VMLA, VMLS. */ | |
12529 | if (opc1 == 0x00) | |
12530 | { | |
12531 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12532 | { |
12533 | if (bit (arm_insn_r->arm_insn, 6)) | |
12534 | curr_insn_type = INSN_T0; | |
12535 | else | |
12536 | curr_insn_type = INSN_T1; | |
12537 | } | |
851f26ae | 12538 | else |
dda83cd7 SM |
12539 | { |
12540 | if (dp_op_sz) | |
12541 | curr_insn_type = INSN_T1; | |
12542 | else | |
12543 | curr_insn_type = INSN_T2; | |
12544 | } | |
851f26ae OJ |
12545 | } |
12546 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
12547 | else if (opc1 == 0x01) | |
12548 | { | |
12549 | if (dp_op_sz) | |
dda83cd7 | 12550 | curr_insn_type = INSN_T1; |
851f26ae | 12551 | else |
dda83cd7 | 12552 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12553 | } |
12554 | /* Handle VMUL. */ | |
12555 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
12556 | { | |
12557 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
12558 | { |
12559 | if (bit (arm_insn_r->arm_insn, 6)) | |
12560 | curr_insn_type = INSN_T0; | |
12561 | else | |
12562 | curr_insn_type = INSN_T1; | |
12563 | } | |
851f26ae | 12564 | else |
dda83cd7 SM |
12565 | { |
12566 | if (dp_op_sz) | |
12567 | curr_insn_type = INSN_T1; | |
12568 | else | |
12569 | curr_insn_type = INSN_T2; | |
12570 | } | |
851f26ae OJ |
12571 | } |
12572 | /* Handle VADD, VSUB. */ | |
12573 | else if (opc1 == 0x03) | |
12574 | { | |
12575 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
12576 | { |
12577 | if (bit (arm_insn_r->arm_insn, 6)) | |
12578 | curr_insn_type = INSN_T0; | |
12579 | else | |
12580 | curr_insn_type = INSN_T1; | |
12581 | } | |
851f26ae | 12582 | else |
dda83cd7 SM |
12583 | { |
12584 | if (dp_op_sz) | |
12585 | curr_insn_type = INSN_T1; | |
12586 | else | |
12587 | curr_insn_type = INSN_T2; | |
12588 | } | |
851f26ae OJ |
12589 | } |
12590 | /* Handle VDIV. */ | |
ce887586 | 12591 | else if (opc1 == 0x08) |
851f26ae OJ |
12592 | { |
12593 | if (dp_op_sz) | |
dda83cd7 | 12594 | curr_insn_type = INSN_T1; |
851f26ae | 12595 | else |
dda83cd7 | 12596 | curr_insn_type = INSN_T2; |
851f26ae OJ |
12597 | } |
12598 | /* Handle all other vfp data processing instructions. */ | |
12599 | else if (opc1 == 0x0b) | |
12600 | { | |
12601 | /* Handle VMOV. */ | |
12602 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
12603 | { |
12604 | if (bit (arm_insn_r->arm_insn, 4)) | |
12605 | { | |
12606 | if (bit (arm_insn_r->arm_insn, 6)) | |
12607 | curr_insn_type = INSN_T0; | |
12608 | else | |
12609 | curr_insn_type = INSN_T1; | |
12610 | } | |
12611 | else | |
12612 | { | |
12613 | if (dp_op_sz) | |
12614 | curr_insn_type = INSN_T1; | |
12615 | else | |
12616 | curr_insn_type = INSN_T2; | |
12617 | } | |
12618 | } | |
851f26ae OJ |
12619 | /* Handle VNEG and VABS. */ |
12620 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
12621 | || (opc2 == 0x00 && opc3 == 0x03)) |
12622 | { | |
12623 | if (!bit (arm_insn_r->arm_insn, 11)) | |
12624 | { | |
12625 | if (bit (arm_insn_r->arm_insn, 6)) | |
12626 | curr_insn_type = INSN_T0; | |
12627 | else | |
12628 | curr_insn_type = INSN_T1; | |
12629 | } | |
12630 | else | |
12631 | { | |
12632 | if (dp_op_sz) | |
12633 | curr_insn_type = INSN_T1; | |
12634 | else | |
12635 | curr_insn_type = INSN_T2; | |
12636 | } | |
12637 | } | |
851f26ae OJ |
12638 | /* Handle VSQRT. */ |
12639 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
12640 | { |
12641 | if (dp_op_sz) | |
12642 | curr_insn_type = INSN_T1; | |
12643 | else | |
12644 | curr_insn_type = INSN_T2; | |
12645 | } | |
851f26ae OJ |
12646 | /* Handle VCVT. */ |
12647 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
12648 | { |
12649 | if (!dp_op_sz) | |
12650 | curr_insn_type = INSN_T1; | |
12651 | else | |
12652 | curr_insn_type = INSN_T2; | |
12653 | } | |
851f26ae | 12654 | else if (opc3 & 0x01) |
dda83cd7 SM |
12655 | { |
12656 | /* Handle VCVT. */ | |
12657 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
12658 | { | |
12659 | if (!bit (arm_insn_r->arm_insn, 18)) | |
12660 | curr_insn_type = INSN_T2; | |
12661 | else | |
12662 | { | |
12663 | if (dp_op_sz) | |
12664 | curr_insn_type = INSN_T1; | |
12665 | else | |
12666 | curr_insn_type = INSN_T2; | |
12667 | } | |
12668 | } | |
12669 | /* Handle VCVT. */ | |
12670 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
12671 | { | |
12672 | if (dp_op_sz) | |
12673 | curr_insn_type = INSN_T1; | |
12674 | else | |
12675 | curr_insn_type = INSN_T2; | |
12676 | } | |
12677 | /* Handle VCVTB, VCVTT. */ | |
12678 | else if ((opc2 & 0x0e) == 0x02) | |
12679 | curr_insn_type = INSN_T2; | |
12680 | /* Handle VCMP, VCMPE. */ | |
12681 | else if ((opc2 & 0x0e) == 0x04) | |
12682 | curr_insn_type = INSN_T3; | |
12683 | } | |
851f26ae OJ |
12684 | } |
12685 | ||
12686 | switch (curr_insn_type) | |
12687 | { | |
12688 | case INSN_T0: | |
dda83cd7 SM |
12689 | reg_vd = reg_vd | (bit_d << 4); |
12690 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12691 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
12692 | arm_insn_r->reg_rec_count = 2; | |
12693 | break; | |
851f26ae OJ |
12694 | |
12695 | case INSN_T1: | |
dda83cd7 SM |
12696 | reg_vd = reg_vd | (bit_d << 4); |
12697 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12698 | arm_insn_r->reg_rec_count = 1; | |
12699 | break; | |
851f26ae OJ |
12700 | |
12701 | case INSN_T2: | |
dda83cd7 SM |
12702 | reg_vd = (reg_vd << 1) | bit_d; |
12703 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12704 | arm_insn_r->reg_rec_count = 1; | |
12705 | break; | |
851f26ae OJ |
12706 | |
12707 | case INSN_T3: | |
dda83cd7 SM |
12708 | record_buf[0] = ARM_FPSCR_REGNUM; |
12709 | arm_insn_r->reg_rec_count = 1; | |
12710 | break; | |
851f26ae OJ |
12711 | |
12712 | default: | |
dda83cd7 SM |
12713 | gdb_assert_not_reached ("no decoding pattern found"); |
12714 | break; | |
851f26ae OJ |
12715 | } |
12716 | ||
12717 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12718 | return 0; | |
12719 | } | |
12720 | ||
60cc5e93 OJ |
12721 | /* Handling opcode 110 insns. */ |
12722 | ||
12723 | static int | |
4748a9be | 12724 | arm_record_asimd_vfp_coproc (arm_insn_decode_record *arm_insn_r) |
60cc5e93 | 12725 | { |
bec2ab5a | 12726 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
12727 | |
12728 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
12729 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
12730 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12731 | ||
12732 | if ((coproc & 0x0e) == 0x0a) | |
12733 | { | |
12734 | /* Handle extension register ld/st instructions. */ | |
12735 | if (!(op1 & 0x20)) | |
dda83cd7 | 12736 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12737 | |
12738 | /* 64-bit transfers between arm core and extension registers. */ | |
12739 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 12740 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12741 | } |
12742 | else | |
12743 | { | |
12744 | /* Handle coprocessor ld/st instructions. */ | |
12745 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
12746 | { |
12747 | /* Store. */ | |
12748 | if (!op1_ebit) | |
12749 | return arm_record_unsupported_insn (arm_insn_r); | |
12750 | else | |
12751 | /* Load. */ | |
12752 | return arm_record_unsupported_insn (arm_insn_r); | |
12753 | } | |
60cc5e93 OJ |
12754 | |
12755 | /* Move to coprocessor from two arm core registers. */ | |
12756 | if (op1 == 0x4) | |
dda83cd7 | 12757 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
12758 | |
12759 | /* Move to two arm core registers from coprocessor. */ | |
12760 | if (op1 == 0x5) | |
dda83cd7 SM |
12761 | { |
12762 | uint32_t reg_t[2]; | |
60cc5e93 | 12763 | |
dda83cd7 SM |
12764 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
12765 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12766 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 12767 | |
dda83cd7 SM |
12768 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
12769 | return 0; | |
60cc5e93 OJ |
12770 | } |
12771 | } | |
12772 | return arm_record_unsupported_insn (arm_insn_r); | |
12773 | } | |
12774 | ||
72508ac0 PO |
12775 | /* Handling opcode 111 insns. */ |
12776 | ||
12777 | static int | |
4748a9be | 12778 | arm_record_coproc_data_proc (arm_insn_decode_record *arm_insn_r) |
72508ac0 | 12779 | { |
2d9e6acb | 12780 | uint32_t op, op1_ebit, coproc, bits_24_25; |
345bd07c | 12781 | arm_gdbarch_tdep *tdep |
08106042 | 12782 | = gdbarch_tdep<arm_gdbarch_tdep> (arm_insn_r->gdbarch); |
72508ac0 | 12783 | struct regcache *reg_cache = arm_insn_r->regcache; |
72508ac0 PO |
12784 | |
12785 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 12786 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
12787 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
12788 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 12789 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
12790 | |
12791 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 12792 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
12793 | { |
12794 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
12795 | { |
12796 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 12797 | |
dda83cd7 | 12798 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 12799 | |
dda83cd7 SM |
12800 | if (svc_operand) /* OABI. */ |
12801 | svc_number = svc_operand - 0x900000; | |
12802 | else /* EABI. */ | |
12803 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 12804 | |
dda83cd7 SM |
12805 | return tdep->arm_syscall_record (reg_cache, svc_number); |
12806 | } | |
97dfe206 | 12807 | else |
dda83cd7 | 12808 | { |
6cb06a8c | 12809 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
12810 | return -1; |
12811 | } | |
97dfe206 | 12812 | } |
2d9e6acb | 12813 | else if (bits_24_25 == 0x02) |
60cc5e93 | 12814 | { |
2d9e6acb YQ |
12815 | if (op) |
12816 | { | |
12817 | if ((coproc & 0x0e) == 0x0a) | |
12818 | { | |
12819 | /* 8, 16, and 32-bit transfer */ | |
12820 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
12821 | } | |
12822 | else | |
12823 | { | |
12824 | if (op1_ebit) | |
12825 | { | |
12826 | /* MRC, MRC2 */ | |
12827 | uint32_t record_buf[1]; | |
12828 | ||
12829 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12830 | if (record_buf[0] == 15) | |
12831 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 12832 | |
2d9e6acb YQ |
12833 | arm_insn_r->reg_rec_count = 1; |
12834 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
12835 | record_buf); | |
12836 | return 0; | |
12837 | } | |
12838 | else | |
12839 | { | |
12840 | /* MCR, MCR2 */ | |
12841 | return -1; | |
12842 | } | |
12843 | } | |
12844 | } | |
12845 | else | |
12846 | { | |
12847 | if ((coproc & 0x0e) == 0x0a) | |
12848 | { | |
12849 | /* VFP data-processing instructions. */ | |
12850 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
12851 | } | |
12852 | else | |
12853 | { | |
12854 | /* CDP, CDP2 */ | |
12855 | return -1; | |
12856 | } | |
12857 | } | |
60cc5e93 | 12858 | } |
97dfe206 OJ |
12859 | else |
12860 | { | |
2d9e6acb | 12861 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 12862 | |
2d9e6acb YQ |
12863 | if (op1 == 5) |
12864 | { | |
12865 | if ((coproc & 0x0e) != 0x0a) | |
12866 | { | |
12867 | /* MRRC, MRRC2 */ | |
12868 | return -1; | |
12869 | } | |
12870 | } | |
12871 | else if (op1 == 4 || op1 == 5) | |
12872 | { | |
12873 | if ((coproc & 0x0e) == 0x0a) | |
12874 | { | |
12875 | /* 64-bit transfers between ARM core and extension */ | |
12876 | return -1; | |
12877 | } | |
12878 | else if (op1 == 4) | |
12879 | { | |
12880 | /* MCRR, MCRR2 */ | |
12881 | return -1; | |
12882 | } | |
12883 | } | |
12884 | else if (op1 == 0 || op1 == 1) | |
12885 | { | |
12886 | /* UNDEFINED */ | |
12887 | return -1; | |
12888 | } | |
12889 | else | |
12890 | { | |
12891 | if ((coproc & 0x0e) == 0x0a) | |
12892 | { | |
12893 | /* Extension register load/store */ | |
12894 | } | |
12895 | else | |
12896 | { | |
12897 | /* STC, STC2, LDC, LDC2 */ | |
12898 | } | |
12899 | return -1; | |
12900 | } | |
97dfe206 | 12901 | } |
72508ac0 | 12902 | |
2d9e6acb | 12903 | return -1; |
72508ac0 PO |
12904 | } |
12905 | ||
12906 | /* Handling opcode 000 insns. */ | |
12907 | ||
12908 | static int | |
4748a9be | 12909 | thumb_record_shift_add_sub (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
12910 | { |
12911 | uint32_t record_buf[8]; | |
12912 | uint32_t reg_src1 = 0; | |
12913 | ||
12914 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12915 | ||
12916 | record_buf[0] = ARM_PS_REGNUM; | |
12917 | record_buf[1] = reg_src1; | |
12918 | thumb_insn_r->reg_rec_count = 2; | |
12919 | ||
12920 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12921 | ||
12922 | return 0; | |
12923 | } | |
12924 | ||
12925 | ||
12926 | /* Handling opcode 001 insns. */ | |
12927 | ||
12928 | static int | |
4748a9be | 12929 | thumb_record_add_sub_cmp_mov (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
12930 | { |
12931 | uint32_t record_buf[8]; | |
12932 | uint32_t reg_src1 = 0; | |
12933 | ||
12934 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12935 | ||
12936 | record_buf[0] = ARM_PS_REGNUM; | |
12937 | record_buf[1] = reg_src1; | |
12938 | thumb_insn_r->reg_rec_count = 2; | |
12939 | ||
12940 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12941 | ||
12942 | return 0; | |
12943 | } | |
12944 | ||
12945 | /* Handling opcode 010 insns. */ | |
12946 | ||
12947 | static int | |
4748a9be | 12948 | thumb_record_ld_st_reg_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
12949 | { |
12950 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12951 | uint32_t record_buf[8], record_buf_mem[8]; | |
12952 | ||
12953 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
12954 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
12955 | ||
12956 | ULONGEST u_regval[2] = {0}; | |
12957 | ||
12958 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
12959 | ||
12960 | if (bit (thumb_insn_r->arm_insn, 12)) | |
12961 | { | |
12962 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
12963 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
12964 | ||
b020ff80 | 12965 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
12966 | { |
12967 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
12968 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
12969 | record_buf[0] = reg_src1; | |
12970 | thumb_insn_r->reg_rec_count = 1; | |
12971 | } | |
b020ff80 | 12972 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
12973 | { |
12974 | /* STR(2), STRB(2), STRH(2) . */ | |
12975 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12976 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
12977 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
12978 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12979 | if (0 == opB) | |
12980 | record_buf_mem[0] = 4; /* STR (2). */ | |
12981 | else if (2 == opB) | |
12982 | record_buf_mem[0] = 1; /* STRB (2). */ | |
12983 | else if (1 == opB) | |
12984 | record_buf_mem[0] = 2; /* STRH (2). */ | |
12985 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
12986 | thumb_insn_r->mem_rec_count = 1; | |
12987 | } | |
72508ac0 PO |
12988 | } |
12989 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
12990 | { | |
12991 | /* Handle load from literal pool. */ | |
12992 | /* LDR(3). */ | |
12993 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12994 | record_buf[0] = reg_src1; | |
12995 | thumb_insn_r->reg_rec_count = 1; | |
12996 | } | |
12997 | else if (opcode1) | |
12998 | { | |
b121eeb9 | 12999 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
13000 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
13001 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13002 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
13003 | { |
13004 | /* Branch with exchange. */ | |
13005 | record_buf[0] = ARM_PS_REGNUM; | |
13006 | thumb_insn_r->reg_rec_count = 1; | |
13007 | } | |
72508ac0 | 13008 | else |
dda83cd7 | 13009 | { |
1f33efec YQ |
13010 | /* Format 8; special data processing insns. */ |
13011 | record_buf[0] = ARM_PS_REGNUM; | |
13012 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
13013 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
13014 | thumb_insn_r->reg_rec_count = 2; |
13015 | } | |
72508ac0 PO |
13016 | } |
13017 | else | |
13018 | { | |
13019 | /* Format 5; data processing insns. */ | |
13020 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13021 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
13022 | { |
13023 | reg_src1 = reg_src1 + 8; | |
13024 | } | |
72508ac0 PO |
13025 | record_buf[0] = ARM_PS_REGNUM; |
13026 | record_buf[1] = reg_src1; | |
13027 | thumb_insn_r->reg_rec_count = 2; | |
13028 | } | |
13029 | ||
13030 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13031 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13032 | record_buf_mem); |
72508ac0 PO |
13033 | |
13034 | return 0; | |
13035 | } | |
13036 | ||
13037 | /* Handling opcode 001 insns. */ | |
13038 | ||
13039 | static int | |
4748a9be | 13040 | thumb_record_ld_st_imm_offset (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13041 | { |
13042 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13043 | uint32_t record_buf[8], record_buf_mem[8]; | |
13044 | ||
13045 | uint32_t reg_src1 = 0; | |
13046 | uint32_t opcode = 0, immed_5 = 0; | |
13047 | ||
13048 | ULONGEST u_regval = 0; | |
13049 | ||
13050 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13051 | ||
13052 | if (opcode) | |
13053 | { | |
13054 | /* LDR(1). */ | |
13055 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13056 | record_buf[0] = reg_src1; | |
13057 | thumb_insn_r->reg_rec_count = 1; | |
13058 | } | |
13059 | else | |
13060 | { | |
13061 | /* STR(1). */ | |
13062 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13063 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13064 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13065 | record_buf_mem[0] = 4; | |
13066 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
13067 | thumb_insn_r->mem_rec_count = 1; | |
13068 | } | |
13069 | ||
13070 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13071 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13072 | record_buf_mem); |
72508ac0 PO |
13073 | |
13074 | return 0; | |
13075 | } | |
13076 | ||
13077 | /* Handling opcode 100 insns. */ | |
13078 | ||
13079 | static int | |
4748a9be | 13080 | thumb_record_ld_st_stack (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13081 | { |
13082 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13083 | uint32_t record_buf[8], record_buf_mem[8]; | |
13084 | ||
13085 | uint32_t reg_src1 = 0; | |
13086 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
13087 | ||
13088 | ULONGEST u_regval = 0; | |
13089 | ||
13090 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
13091 | ||
13092 | if (3 == opcode) | |
13093 | { | |
13094 | /* LDR(4). */ | |
13095 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13096 | record_buf[0] = reg_src1; | |
13097 | thumb_insn_r->reg_rec_count = 1; | |
13098 | } | |
13099 | else if (1 == opcode) | |
13100 | { | |
13101 | /* LDRH(1). */ | |
13102 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
13103 | record_buf[0] = reg_src1; | |
13104 | thumb_insn_r->reg_rec_count = 1; | |
13105 | } | |
13106 | else if (2 == opcode) | |
13107 | { | |
13108 | /* STR(3). */ | |
13109 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
13110 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13111 | record_buf_mem[0] = 4; | |
13112 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
13113 | thumb_insn_r->mem_rec_count = 1; | |
13114 | } | |
13115 | else if (0 == opcode) | |
13116 | { | |
13117 | /* STRH(1). */ | |
13118 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
13119 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
13120 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13121 | record_buf_mem[0] = 2; | |
13122 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
13123 | thumb_insn_r->mem_rec_count = 1; | |
13124 | } | |
13125 | ||
13126 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13127 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13128 | record_buf_mem); |
72508ac0 PO |
13129 | |
13130 | return 0; | |
13131 | } | |
13132 | ||
13133 | /* Handling opcode 101 insns. */ | |
13134 | ||
13135 | static int | |
4748a9be | 13136 | thumb_record_misc (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13137 | { |
13138 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
13139 | ||
b121eeb9 | 13140 | uint32_t opcode = 0; |
72508ac0 | 13141 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 13142 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13143 | uint32_t record_buf[24], record_buf_mem[48]; |
13144 | uint32_t reg_src1; | |
13145 | ||
13146 | ULONGEST u_regval = 0; | |
13147 | ||
13148 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 13149 | |
b121eeb9 | 13150 | if (opcode == 0 || opcode == 1) |
72508ac0 | 13151 | { |
b121eeb9 YQ |
13152 | /* ADR and ADD (SP plus immediate) */ |
13153 | ||
72508ac0 PO |
13154 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
13155 | record_buf[0] = reg_src1; | |
13156 | thumb_insn_r->reg_rec_count = 1; | |
13157 | } | |
b121eeb9 | 13158 | else |
72508ac0 | 13159 | { |
b121eeb9 YQ |
13160 | /* Miscellaneous 16-bit instructions */ |
13161 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
13162 | ||
13163 | switch (opcode2) | |
13164 | { | |
13165 | case 6: | |
13166 | /* SETEND and CPS */ | |
13167 | break; | |
13168 | case 0: | |
13169 | /* ADD/SUB (SP plus immediate) */ | |
13170 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13171 | record_buf[0] = ARM_SP_REGNUM; | |
13172 | thumb_insn_r->reg_rec_count = 1; | |
13173 | break; | |
13174 | case 1: /* fall through */ | |
13175 | case 3: /* fall through */ | |
13176 | case 9: /* fall through */ | |
13177 | case 11: | |
13178 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
13179 | break; |
13180 | case 2: | |
13181 | /* SXTH, SXTB, UXTH, UXTB */ | |
13182 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
13183 | thumb_insn_r->reg_rec_count = 1; | |
13184 | break; | |
13185 | case 4: /* fall through */ | |
13186 | case 5: | |
13187 | /* PUSH. */ | |
13188 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13189 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
13190 | while (register_bits) | |
13191 | { | |
13192 | if (register_bits & 0x00000001) | |
13193 | register_count++; | |
13194 | register_bits = register_bits >> 1; | |
13195 | } | |
13196 | start_address = u_regval - \ | |
13197 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
13198 | thumb_insn_r->mem_rec_count = register_count; | |
13199 | while (register_count) | |
13200 | { | |
13201 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13202 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13203 | start_address = start_address + 4; | |
13204 | register_count--; | |
13205 | } | |
13206 | record_buf[0] = ARM_SP_REGNUM; | |
13207 | thumb_insn_r->reg_rec_count = 1; | |
13208 | break; | |
13209 | case 10: | |
13210 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
13211 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
13212 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
13213 | break; |
13214 | case 12: /* fall through */ | |
13215 | case 13: | |
13216 | /* POP. */ | |
13217 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13218 | while (register_bits) | |
13219 | { | |
13220 | if (register_bits & 0x00000001) | |
13221 | record_buf[index++] = register_count; | |
13222 | register_bits = register_bits >> 1; | |
13223 | register_count++; | |
13224 | } | |
13225 | record_buf[index++] = ARM_PS_REGNUM; | |
13226 | record_buf[index++] = ARM_SP_REGNUM; | |
13227 | thumb_insn_r->reg_rec_count = index; | |
13228 | break; | |
13229 | case 0xe: | |
13230 | /* BKPT insn. */ | |
13231 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
13232 | /* CPSR is changed to be executed in ARM state, disabling normal | |
13233 | interrupts, entering abort mode. */ | |
13234 | /* According to high vector configuration PC is set. */ | |
13235 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
13236 | previous CPSR and Program Counter. */ | |
13237 | record_buf[0] = ARM_PS_REGNUM; | |
13238 | record_buf[1] = ARM_LR_REGNUM; | |
13239 | thumb_insn_r->reg_rec_count = 2; | |
13240 | /* We need to save SPSR value, which is not yet done. */ | |
6cb06a8c TT |
13241 | gdb_printf (gdb_stderr, |
13242 | _("Process record does not support instruction " | |
13243 | "0x%0x at address %s.\n"), | |
13244 | thumb_insn_r->arm_insn, | |
13245 | paddress (thumb_insn_r->gdbarch, | |
13246 | thumb_insn_r->this_addr)); | |
b121eeb9 YQ |
13247 | return -1; |
13248 | ||
13249 | case 0xf: | |
13250 | /* If-Then, and hints */ | |
13251 | break; | |
13252 | default: | |
13253 | return -1; | |
13254 | }; | |
72508ac0 PO |
13255 | } |
13256 | ||
13257 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13258 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13259 | record_buf_mem); |
72508ac0 PO |
13260 | |
13261 | return 0; | |
13262 | } | |
13263 | ||
13264 | /* Handling opcode 110 insns. */ | |
13265 | ||
13266 | static int | |
4748a9be | 13267 | thumb_record_ldm_stm_swi (arm_insn_decode_record *thumb_insn_r) |
72508ac0 | 13268 | { |
345bd07c | 13269 | arm_gdbarch_tdep *tdep |
08106042 | 13270 | = gdbarch_tdep<arm_gdbarch_tdep> (thumb_insn_r->gdbarch); |
72508ac0 PO |
13271 | struct regcache *reg_cache = thumb_insn_r->regcache; |
13272 | ||
13273 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
13274 | uint32_t reg_src1 = 0; | |
13275 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 13276 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
13277 | uint32_t record_buf[24], record_buf_mem[48]; |
13278 | ||
13279 | ULONGEST u_regval = 0; | |
13280 | ||
13281 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
13282 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
13283 | ||
13284 | if (1 == opcode2) | |
13285 | { | |
13286 | ||
13287 | /* LDMIA. */ | |
13288 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13289 | /* Get Rn. */ | |
13290 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13291 | while (register_bits) | |
dda83cd7 SM |
13292 | { |
13293 | if (register_bits & 0x00000001) | |
13294 | record_buf[index++] = register_count; | |
13295 | register_bits = register_bits >> 1; | |
13296 | register_count++; | |
13297 | } | |
f969241e OJ |
13298 | record_buf[index++] = reg_src1; |
13299 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
13300 | } |
13301 | else if (0 == opcode2) | |
13302 | { | |
13303 | /* It handles both STMIA. */ | |
13304 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
13305 | /* Get Rn. */ | |
13306 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
13307 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
13308 | while (register_bits) | |
dda83cd7 SM |
13309 | { |
13310 | if (register_bits & 0x00000001) | |
13311 | register_count++; | |
13312 | register_bits = register_bits >> 1; | |
13313 | } | |
72508ac0 PO |
13314 | start_address = u_regval; |
13315 | thumb_insn_r->mem_rec_count = register_count; | |
13316 | while (register_count) | |
dda83cd7 SM |
13317 | { |
13318 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
13319 | record_buf_mem[(register_count * 2) - 2] = 4; | |
13320 | start_address = start_address + 4; | |
13321 | register_count--; | |
13322 | } | |
72508ac0 PO |
13323 | } |
13324 | else if (0x1F == opcode1) | |
13325 | { | |
dda83cd7 SM |
13326 | /* Handle arm syscall insn. */ |
13327 | if (tdep->arm_syscall_record != NULL) | |
13328 | { | |
13329 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
13330 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
13331 | } | |
13332 | else | |
13333 | { | |
6cb06a8c | 13334 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
13335 | return -1; |
13336 | } | |
72508ac0 PO |
13337 | } |
13338 | ||
13339 | /* B (1), conditional branch is automatically taken care in process_record, | |
13340 | as PC is saved there. */ | |
13341 | ||
13342 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13343 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 13344 | record_buf_mem); |
72508ac0 PO |
13345 | |
13346 | return ret; | |
13347 | } | |
13348 | ||
13349 | /* Handling opcode 111 insns. */ | |
13350 | ||
13351 | static int | |
4748a9be | 13352 | thumb_record_branch (arm_insn_decode_record *thumb_insn_r) |
72508ac0 PO |
13353 | { |
13354 | uint32_t record_buf[8]; | |
13355 | uint32_t bits_h = 0; | |
13356 | ||
13357 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
13358 | ||
13359 | if (2 == bits_h || 3 == bits_h) | |
13360 | { | |
13361 | /* BL */ | |
13362 | record_buf[0] = ARM_LR_REGNUM; | |
13363 | thumb_insn_r->reg_rec_count = 1; | |
13364 | } | |
13365 | else if (1 == bits_h) | |
13366 | { | |
13367 | /* BLX(1). */ | |
13368 | record_buf[0] = ARM_PS_REGNUM; | |
13369 | record_buf[1] = ARM_LR_REGNUM; | |
13370 | thumb_insn_r->reg_rec_count = 2; | |
13371 | } | |
13372 | ||
13373 | /* B(2) is automatically taken care in process_record, as PC is | |
13374 | saved there. */ | |
13375 | ||
13376 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
13377 | ||
13378 | return 0; | |
13379 | } | |
13380 | ||
c6ec2b30 OJ |
13381 | /* Handler for thumb2 load/store multiple instructions. */ |
13382 | ||
13383 | static int | |
4748a9be | 13384 | thumb2_record_ld_st_multiple (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13385 | { |
13386 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13387 | ||
13388 | uint32_t reg_rn, op; | |
13389 | uint32_t register_bits = 0, register_count = 0; | |
13390 | uint32_t index = 0, start_address = 0; | |
13391 | uint32_t record_buf[24], record_buf_mem[48]; | |
13392 | ||
13393 | ULONGEST u_regval = 0; | |
13394 | ||
13395 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13396 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13397 | ||
13398 | if (0 == op || 3 == op) | |
13399 | { | |
13400 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13401 | { |
13402 | /* Handle RFE instruction. */ | |
13403 | record_buf[0] = ARM_PS_REGNUM; | |
13404 | thumb2_insn_r->reg_rec_count = 1; | |
13405 | } | |
c6ec2b30 | 13406 | else |
dda83cd7 SM |
13407 | { |
13408 | /* Handle SRS instruction after reading banked SP. */ | |
13409 | return arm_record_unsupported_insn (thumb2_insn_r); | |
13410 | } | |
c6ec2b30 OJ |
13411 | } |
13412 | else if (1 == op || 2 == op) | |
13413 | { | |
13414 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
13415 | { |
13416 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
13417 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13418 | while (register_bits) | |
13419 | { | |
13420 | if (register_bits & 0x00000001) | |
13421 | record_buf[index++] = register_count; | |
13422 | ||
13423 | register_count++; | |
13424 | register_bits = register_bits >> 1; | |
13425 | } | |
13426 | record_buf[index++] = reg_rn; | |
13427 | record_buf[index++] = ARM_PS_REGNUM; | |
13428 | thumb2_insn_r->reg_rec_count = index; | |
13429 | } | |
c6ec2b30 | 13430 | else |
dda83cd7 SM |
13431 | { |
13432 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
13433 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
13434 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13435 | while (register_bits) | |
13436 | { | |
13437 | if (register_bits & 0x00000001) | |
13438 | register_count++; | |
13439 | ||
13440 | register_bits = register_bits >> 1; | |
13441 | } | |
13442 | ||
13443 | if (1 == op) | |
13444 | { | |
13445 | /* Start address calculation for LDMDB/LDMEA. */ | |
13446 | start_address = u_regval; | |
13447 | } | |
13448 | else if (2 == op) | |
13449 | { | |
13450 | /* Start address calculation for LDMDB/LDMEA. */ | |
13451 | start_address = u_regval - register_count * 4; | |
13452 | } | |
13453 | ||
13454 | thumb2_insn_r->mem_rec_count = register_count; | |
13455 | while (register_count) | |
13456 | { | |
13457 | record_buf_mem[register_count * 2 - 1] = start_address; | |
13458 | record_buf_mem[register_count * 2 - 2] = 4; | |
13459 | start_address = start_address + 4; | |
13460 | register_count--; | |
13461 | } | |
13462 | record_buf[0] = reg_rn; | |
13463 | record_buf[1] = ARM_PS_REGNUM; | |
13464 | thumb2_insn_r->reg_rec_count = 2; | |
13465 | } | |
c6ec2b30 OJ |
13466 | } |
13467 | ||
13468 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 13469 | record_buf_mem); |
c6ec2b30 | 13470 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 13471 | record_buf); |
c6ec2b30 OJ |
13472 | return ARM_RECORD_SUCCESS; |
13473 | } | |
13474 | ||
13475 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
13476 | instructions. */ | |
13477 | ||
13478 | static int | |
4748a9be | 13479 | thumb2_record_ld_st_dual_ex_tbb (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13480 | { |
13481 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13482 | ||
13483 | uint32_t reg_rd, reg_rn, offset_imm; | |
13484 | uint32_t reg_dest1, reg_dest2; | |
13485 | uint32_t address, offset_addr; | |
13486 | uint32_t record_buf[8], record_buf_mem[8]; | |
13487 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
13488 | |
13489 | ULONGEST u_regval[2]; | |
13490 | ||
13491 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
13492 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
13493 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13494 | ||
13495 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
13496 | { | |
13497 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
13498 | { |
13499 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13500 | record_buf[0] = reg_dest1; | |
13501 | record_buf[1] = ARM_PS_REGNUM; | |
13502 | thumb2_insn_r->reg_rec_count = 2; | |
13503 | } | |
c6ec2b30 OJ |
13504 | |
13505 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
13506 | { |
13507 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13508 | record_buf[2] = reg_dest2; | |
13509 | thumb2_insn_r->reg_rec_count = 3; | |
13510 | } | |
c6ec2b30 OJ |
13511 | } |
13512 | else | |
13513 | { | |
13514 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13515 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13516 | ||
13517 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
13518 | { |
13519 | /* Handle STREX. */ | |
13520 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13521 | address = u_regval[0] + (offset_imm * 4); | |
13522 | record_buf_mem[0] = 4; | |
13523 | record_buf_mem[1] = address; | |
13524 | thumb2_insn_r->mem_rec_count = 1; | |
13525 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13526 | record_buf[0] = reg_rd; | |
13527 | thumb2_insn_r->reg_rec_count = 1; | |
13528 | } | |
c6ec2b30 | 13529 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
13530 | { |
13531 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13532 | record_buf[0] = reg_rd; | |
13533 | thumb2_insn_r->reg_rec_count = 1; | |
13534 | address = u_regval[0]; | |
13535 | record_buf_mem[1] = address; | |
13536 | ||
13537 | if (4 == op3) | |
13538 | { | |
13539 | /* Handle STREXB. */ | |
13540 | record_buf_mem[0] = 1; | |
13541 | thumb2_insn_r->mem_rec_count = 1; | |
13542 | } | |
13543 | else if (5 == op3) | |
13544 | { | |
13545 | /* Handle STREXH. */ | |
13546 | record_buf_mem[0] = 2 ; | |
13547 | thumb2_insn_r->mem_rec_count = 1; | |
13548 | } | |
13549 | else if (7 == op3) | |
13550 | { | |
13551 | /* Handle STREXD. */ | |
13552 | address = u_regval[0]; | |
13553 | record_buf_mem[0] = 4; | |
13554 | record_buf_mem[2] = 4; | |
13555 | record_buf_mem[3] = address + 4; | |
13556 | thumb2_insn_r->mem_rec_count = 2; | |
13557 | } | |
13558 | } | |
c6ec2b30 | 13559 | else |
dda83cd7 SM |
13560 | { |
13561 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13562 | ||
13563 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
13564 | { | |
13565 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13566 | offset_addr = u_regval[0] + (offset_imm * 4); | |
13567 | else | |
13568 | offset_addr = u_regval[0] - (offset_imm * 4); | |
13569 | ||
13570 | address = offset_addr; | |
13571 | } | |
13572 | else | |
13573 | address = u_regval[0]; | |
13574 | ||
13575 | record_buf_mem[0] = 4; | |
13576 | record_buf_mem[1] = address; | |
13577 | record_buf_mem[2] = 4; | |
13578 | record_buf_mem[3] = address + 4; | |
13579 | thumb2_insn_r->mem_rec_count = 2; | |
13580 | record_buf[0] = reg_rn; | |
13581 | thumb2_insn_r->reg_rec_count = 1; | |
13582 | } | |
c6ec2b30 OJ |
13583 | } |
13584 | ||
13585 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13586 | record_buf); |
c6ec2b30 | 13587 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13588 | record_buf_mem); |
c6ec2b30 OJ |
13589 | return ARM_RECORD_SUCCESS; |
13590 | } | |
13591 | ||
13592 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
13593 | instructions. */ | |
13594 | ||
13595 | static int | |
4748a9be | 13596 | thumb2_record_data_proc_sreg_mimm (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13597 | { |
13598 | uint32_t reg_rd, op; | |
13599 | uint32_t record_buf[8]; | |
13600 | ||
13601 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
13602 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13603 | ||
13604 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
13605 | { | |
13606 | record_buf[0] = ARM_PS_REGNUM; | |
13607 | thumb2_insn_r->reg_rec_count = 1; | |
13608 | } | |
13609 | else | |
13610 | { | |
13611 | record_buf[0] = reg_rd; | |
13612 | record_buf[1] = ARM_PS_REGNUM; | |
13613 | thumb2_insn_r->reg_rec_count = 2; | |
13614 | } | |
13615 | ||
13616 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13617 | record_buf); |
c6ec2b30 OJ |
13618 | return ARM_RECORD_SUCCESS; |
13619 | } | |
13620 | ||
13621 | /* Generic handler for thumb2 instructions which effect destination and PS | |
13622 | registers. */ | |
13623 | ||
13624 | static int | |
4748a9be | 13625 | thumb2_record_ps_dest_generic (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13626 | { |
13627 | uint32_t reg_rd; | |
13628 | uint32_t record_buf[8]; | |
13629 | ||
13630 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13631 | ||
13632 | record_buf[0] = reg_rd; | |
13633 | record_buf[1] = ARM_PS_REGNUM; | |
13634 | thumb2_insn_r->reg_rec_count = 2; | |
13635 | ||
13636 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13637 | record_buf); |
c6ec2b30 OJ |
13638 | return ARM_RECORD_SUCCESS; |
13639 | } | |
13640 | ||
13641 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
13642 | ||
13643 | static int | |
4748a9be | 13644 | thumb2_record_branch_misc_cntrl (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13645 | { |
13646 | uint32_t op, op1, op2; | |
13647 | uint32_t record_buf[8]; | |
13648 | ||
13649 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13650 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
13651 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13652 | ||
13653 | /* Handle MSR insn. */ | |
13654 | if (!(op1 & 0x2) && 0x38 == op) | |
13655 | { | |
13656 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
13657 | { |
13658 | /* CPSR is going to be changed. */ | |
13659 | record_buf[0] = ARM_PS_REGNUM; | |
13660 | thumb2_insn_r->reg_rec_count = 1; | |
13661 | } | |
c6ec2b30 | 13662 | else |
dda83cd7 SM |
13663 | { |
13664 | arm_record_unsupported_insn(thumb2_insn_r); | |
13665 | return -1; | |
13666 | } | |
c6ec2b30 OJ |
13667 | } |
13668 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
13669 | { | |
13670 | /* BLX. */ | |
13671 | record_buf[0] = ARM_PS_REGNUM; | |
13672 | record_buf[1] = ARM_LR_REGNUM; | |
13673 | thumb2_insn_r->reg_rec_count = 2; | |
13674 | } | |
13675 | ||
13676 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13677 | record_buf); |
c6ec2b30 OJ |
13678 | return ARM_RECORD_SUCCESS; |
13679 | } | |
13680 | ||
13681 | /* Handler for thumb2 store single data item instructions. */ | |
13682 | ||
13683 | static int | |
4748a9be | 13684 | thumb2_record_str_single_data (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13685 | { |
13686 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13687 | ||
13688 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
13689 | uint32_t address, offset_addr; | |
13690 | uint32_t record_buf[8], record_buf_mem[8]; | |
13691 | uint32_t op1, op2; | |
13692 | ||
13693 | ULONGEST u_regval[2]; | |
13694 | ||
13695 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
13696 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
13697 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13698 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13699 | ||
13700 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13701 | { | |
13702 | /* T2 encoding. */ | |
13703 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
13704 | offset_addr = u_regval[0] + offset_imm; | |
13705 | address = offset_addr; | |
13706 | } | |
13707 | else | |
13708 | { | |
13709 | /* T3 encoding. */ | |
13710 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
13711 | { |
13712 | /* Handle STRB (register). */ | |
13713 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13714 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
13715 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
13716 | offset_addr = u_regval[1] << shift_imm; | |
13717 | address = u_regval[0] + offset_addr; | |
13718 | } | |
c6ec2b30 | 13719 | else |
dda83cd7 SM |
13720 | { |
13721 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13722 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
13723 | { | |
13724 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
13725 | offset_addr = u_regval[0] + offset_imm; | |
13726 | else | |
13727 | offset_addr = u_regval[0] - offset_imm; | |
13728 | ||
13729 | address = offset_addr; | |
13730 | } | |
13731 | else | |
13732 | address = u_regval[0]; | |
13733 | } | |
c6ec2b30 OJ |
13734 | } |
13735 | ||
13736 | switch (op1) | |
13737 | { | |
13738 | /* Store byte instructions. */ | |
13739 | case 4: | |
13740 | case 0: | |
dda83cd7 SM |
13741 | record_buf_mem[0] = 1; |
13742 | break; | |
c6ec2b30 OJ |
13743 | /* Store half word instructions. */ |
13744 | case 1: | |
13745 | case 5: | |
dda83cd7 SM |
13746 | record_buf_mem[0] = 2; |
13747 | break; | |
c6ec2b30 OJ |
13748 | /* Store word instructions. */ |
13749 | case 2: | |
13750 | case 6: | |
dda83cd7 SM |
13751 | record_buf_mem[0] = 4; |
13752 | break; | |
c6ec2b30 OJ |
13753 | |
13754 | default: | |
dda83cd7 SM |
13755 | gdb_assert_not_reached ("no decoding pattern found"); |
13756 | break; | |
c6ec2b30 OJ |
13757 | } |
13758 | ||
13759 | record_buf_mem[1] = address; | |
13760 | thumb2_insn_r->mem_rec_count = 1; | |
13761 | record_buf[0] = reg_rn; | |
13762 | thumb2_insn_r->reg_rec_count = 1; | |
13763 | ||
13764 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13765 | record_buf); |
c6ec2b30 | 13766 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13767 | record_buf_mem); |
c6ec2b30 OJ |
13768 | return ARM_RECORD_SUCCESS; |
13769 | } | |
13770 | ||
13771 | /* Handler for thumb2 load memory hints instructions. */ | |
13772 | ||
13773 | static int | |
4748a9be | 13774 | thumb2_record_ld_mem_hints (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13775 | { |
13776 | uint32_t record_buf[8]; | |
13777 | uint32_t reg_rt, reg_rn; | |
13778 | ||
13779 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13780 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13781 | ||
13782 | if (ARM_PC_REGNUM != reg_rt) | |
13783 | { | |
13784 | record_buf[0] = reg_rt; | |
13785 | record_buf[1] = reg_rn; | |
13786 | record_buf[2] = ARM_PS_REGNUM; | |
13787 | thumb2_insn_r->reg_rec_count = 3; | |
13788 | ||
13789 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13790 | record_buf); |
c6ec2b30 OJ |
13791 | return ARM_RECORD_SUCCESS; |
13792 | } | |
13793 | ||
13794 | return ARM_RECORD_FAILURE; | |
13795 | } | |
13796 | ||
13797 | /* Handler for thumb2 load word instructions. */ | |
13798 | ||
13799 | static int | |
4748a9be | 13800 | thumb2_record_ld_word (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 | 13801 | { |
c6ec2b30 OJ |
13802 | uint32_t record_buf[8]; |
13803 | ||
13804 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13805 | record_buf[1] = ARM_PS_REGNUM; | |
13806 | thumb2_insn_r->reg_rec_count = 2; | |
13807 | ||
13808 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13809 | record_buf); |
c6ec2b30 OJ |
13810 | return ARM_RECORD_SUCCESS; |
13811 | } | |
13812 | ||
13813 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
13814 | divide instructions. */ | |
13815 | ||
13816 | static int | |
4748a9be | 13817 | thumb2_record_lmul_lmla_div (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
13818 | { |
13819 | uint32_t opcode1 = 0, opcode2 = 0; | |
13820 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
13821 | |
13822 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
13823 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13824 | ||
13825 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
13826 | { | |
13827 | /* Handle SMULL, UMULL, SMULAL. */ | |
13828 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
13829 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13830 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13831 | record_buf[2] = ARM_PS_REGNUM; | |
13832 | thumb2_insn_r->reg_rec_count = 3; | |
13833 | } | |
13834 | else if (1 == opcode1 || 3 == opcode2) | |
13835 | { | |
13836 | /* Handle SDIV and UDIV. */ | |
13837 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13838 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13839 | record_buf[2] = ARM_PS_REGNUM; | |
13840 | thumb2_insn_r->reg_rec_count = 3; | |
13841 | } | |
13842 | else | |
13843 | return ARM_RECORD_FAILURE; | |
13844 | ||
13845 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13846 | record_buf); |
c6ec2b30 OJ |
13847 | return ARM_RECORD_SUCCESS; |
13848 | } | |
13849 | ||
60cc5e93 OJ |
13850 | /* Record handler for thumb32 coprocessor instructions. */ |
13851 | ||
13852 | static int | |
4748a9be | 13853 | thumb2_record_coproc_insn (arm_insn_decode_record *thumb2_insn_r) |
60cc5e93 OJ |
13854 | { |
13855 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
13856 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
13857 | else | |
13858 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
13859 | } | |
13860 | ||
1e1b6563 OJ |
13861 | /* Record handler for advance SIMD structure load/store instructions. */ |
13862 | ||
13863 | static int | |
4748a9be | 13864 | thumb2_record_asimd_struct_ld_st (arm_insn_decode_record *thumb2_insn_r) |
1e1b6563 OJ |
13865 | { |
13866 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13867 | uint32_t l_bit, a_bit, b_bits; | |
13868 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 13869 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
13870 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
13871 | uint8_t f_ebytes; | |
13872 | ||
13873 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
13874 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
13875 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13876 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13877 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13878 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
13879 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
13880 | f_elem = 8 / f_ebytes; |
13881 | ||
13882 | if (!l_bit) | |
13883 | { | |
13884 | ULONGEST u_regval = 0; | |
13885 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13886 | address = u_regval; | |
13887 | ||
13888 | if (!a_bit) | |
dda83cd7 SM |
13889 | { |
13890 | /* Handle VST1. */ | |
13891 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
13892 | { | |
13893 | if (b_bits == 0x07) | |
13894 | bf_regs = 1; | |
13895 | else if (b_bits == 0x0a) | |
13896 | bf_regs = 2; | |
13897 | else if (b_bits == 0x06) | |
13898 | bf_regs = 3; | |
13899 | else if (b_bits == 0x02) | |
13900 | bf_regs = 4; | |
13901 | else | |
13902 | bf_regs = 0; | |
13903 | ||
13904 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13905 | { | |
13906 | for (index_e = 0; index_e < f_elem; index_e++) | |
13907 | { | |
13908 | record_buf_mem[index_m++] = f_ebytes; | |
13909 | record_buf_mem[index_m++] = address; | |
13910 | address = address + f_ebytes; | |
13911 | thumb2_insn_r->mem_rec_count += 1; | |
13912 | } | |
13913 | } | |
13914 | } | |
13915 | /* Handle VST2. */ | |
13916 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
13917 | { | |
13918 | if (b_bits == 0x09 || b_bits == 0x08) | |
13919 | bf_regs = 1; | |
13920 | else if (b_bits == 0x03) | |
13921 | bf_regs = 2; | |
13922 | else | |
13923 | bf_regs = 0; | |
13924 | ||
13925 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13926 | for (index_e = 0; index_e < f_elem; index_e++) | |
13927 | { | |
13928 | for (loop_t = 0; loop_t < 2; loop_t++) | |
13929 | { | |
13930 | record_buf_mem[index_m++] = f_ebytes; | |
13931 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13932 | thumb2_insn_r->mem_rec_count += 1; | |
13933 | } | |
13934 | address = address + (2 * f_ebytes); | |
13935 | } | |
13936 | } | |
13937 | /* Handle VST3. */ | |
13938 | else if ((b_bits & 0x0e) == 0x04) | |
13939 | { | |
13940 | for (index_e = 0; index_e < f_elem; index_e++) | |
13941 | { | |
13942 | for (loop_t = 0; loop_t < 3; loop_t++) | |
13943 | { | |
13944 | record_buf_mem[index_m++] = f_ebytes; | |
13945 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13946 | thumb2_insn_r->mem_rec_count += 1; | |
13947 | } | |
13948 | address = address + (3 * f_ebytes); | |
13949 | } | |
13950 | } | |
13951 | /* Handle VST4. */ | |
13952 | else if (!(b_bits & 0x0e)) | |
13953 | { | |
13954 | for (index_e = 0; index_e < f_elem; index_e++) | |
13955 | { | |
13956 | for (loop_t = 0; loop_t < 4; loop_t++) | |
13957 | { | |
13958 | record_buf_mem[index_m++] = f_ebytes; | |
13959 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13960 | thumb2_insn_r->mem_rec_count += 1; | |
13961 | } | |
13962 | address = address + (4 * f_ebytes); | |
13963 | } | |
13964 | } | |
13965 | } | |
1e1b6563 | 13966 | else |
dda83cd7 SM |
13967 | { |
13968 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
13969 | ||
13970 | if (bft_size == 0x00) | |
13971 | f_ebytes = 1; | |
13972 | else if (bft_size == 0x01) | |
13973 | f_ebytes = 2; | |
13974 | else if (bft_size == 0x02) | |
13975 | f_ebytes = 4; | |
13976 | else | |
13977 | f_ebytes = 0; | |
13978 | ||
13979 | /* Handle VST1. */ | |
13980 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
13981 | thumb2_insn_r->mem_rec_count = 1; | |
13982 | /* Handle VST2. */ | |
13983 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
13984 | thumb2_insn_r->mem_rec_count = 2; | |
13985 | /* Handle VST3. */ | |
13986 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
13987 | thumb2_insn_r->mem_rec_count = 3; | |
13988 | /* Handle VST4. */ | |
13989 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
13990 | thumb2_insn_r->mem_rec_count = 4; | |
13991 | ||
13992 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
13993 | { | |
13994 | record_buf_mem[index_m] = f_ebytes; | |
13995 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
13996 | } | |
13997 | } | |
1e1b6563 OJ |
13998 | } |
13999 | else | |
14000 | { | |
14001 | if (!a_bit) | |
dda83cd7 SM |
14002 | { |
14003 | /* Handle VLD1. */ | |
14004 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
14005 | thumb2_insn_r->reg_rec_count = 1; | |
14006 | /* Handle VLD2. */ | |
14007 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
14008 | thumb2_insn_r->reg_rec_count = 2; | |
14009 | /* Handle VLD3. */ | |
14010 | else if ((b_bits & 0x0e) == 0x04) | |
14011 | thumb2_insn_r->reg_rec_count = 3; | |
14012 | /* Handle VLD4. */ | |
14013 | else if (!(b_bits & 0x0e)) | |
14014 | thumb2_insn_r->reg_rec_count = 4; | |
14015 | } | |
1e1b6563 | 14016 | else |
dda83cd7 SM |
14017 | { |
14018 | /* Handle VLD1. */ | |
14019 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
14020 | thumb2_insn_r->reg_rec_count = 1; | |
14021 | /* Handle VLD2. */ | |
14022 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
14023 | thumb2_insn_r->reg_rec_count = 2; | |
14024 | /* Handle VLD3. */ | |
14025 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
14026 | thumb2_insn_r->reg_rec_count = 3; | |
14027 | /* Handle VLD4. */ | |
14028 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
14029 | thumb2_insn_r->reg_rec_count = 4; | |
14030 | ||
14031 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
14032 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
14033 | } | |
1e1b6563 OJ |
14034 | } |
14035 | ||
14036 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
14037 | { | |
14038 | record_buf[index_r] = reg_rn; | |
14039 | thumb2_insn_r->reg_rec_count += 1; | |
14040 | } | |
14041 | ||
14042 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 14043 | record_buf); |
1e1b6563 | 14044 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 14045 | record_buf_mem); |
1e1b6563 OJ |
14046 | return 0; |
14047 | } | |
14048 | ||
c6ec2b30 OJ |
14049 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
14050 | ||
14051 | static unsigned int | |
4748a9be | 14052 | thumb2_record_decode_insn_handler (arm_insn_decode_record *thumb2_insn_r) |
c6ec2b30 OJ |
14053 | { |
14054 | uint32_t op, op1, op2; | |
14055 | ||
14056 | op = bit (thumb2_insn_r->arm_insn, 15); | |
14057 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
14058 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
14059 | ||
14060 | if (op1 == 0x01) | |
14061 | { | |
14062 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
14063 | { |
14064 | /* Load/store multiple instruction. */ | |
14065 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
14066 | } | |
b121eeb9 | 14067 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
14068 | { |
14069 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
14070 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
14071 | } | |
b121eeb9 | 14072 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
14073 | { |
14074 | /* Data-processing (shifted register). */ | |
14075 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14076 | } | |
c6ec2b30 | 14077 | else if (op2 & 0x40) |
dda83cd7 SM |
14078 | { |
14079 | /* Co-processor instructions. */ | |
14080 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14081 | } | |
c6ec2b30 OJ |
14082 | } |
14083 | else if (op1 == 0x02) | |
14084 | { | |
14085 | if (op) | |
dda83cd7 SM |
14086 | { |
14087 | /* Branches and miscellaneous control instructions. */ | |
14088 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
14089 | } | |
c6ec2b30 | 14090 | else if (op2 & 0x20) |
dda83cd7 SM |
14091 | { |
14092 | /* Data-processing (plain binary immediate) instruction. */ | |
14093 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14094 | } | |
c6ec2b30 | 14095 | else |
dda83cd7 SM |
14096 | { |
14097 | /* Data-processing (modified immediate). */ | |
14098 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
14099 | } | |
c6ec2b30 OJ |
14100 | } |
14101 | else if (op1 == 0x03) | |
14102 | { | |
14103 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
14104 | { |
14105 | /* Store single data item. */ | |
14106 | return thumb2_record_str_single_data (thumb2_insn_r); | |
14107 | } | |
c6ec2b30 | 14108 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
14109 | { |
14110 | /* Advanced SIMD or structure load/store instructions. */ | |
14111 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
14112 | } | |
c6ec2b30 | 14113 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
14114 | { |
14115 | /* Load byte, memory hints instruction. */ | |
14116 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14117 | } | |
c6ec2b30 | 14118 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
14119 | { |
14120 | /* Load halfword, memory hints instruction. */ | |
14121 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
14122 | } | |
c6ec2b30 | 14123 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
14124 | { |
14125 | /* Load word instruction. */ | |
14126 | return thumb2_record_ld_word (thumb2_insn_r); | |
14127 | } | |
c6ec2b30 | 14128 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
14129 | { |
14130 | /* Data-processing (register) instruction. */ | |
14131 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14132 | } | |
c6ec2b30 | 14133 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
14134 | { |
14135 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
14136 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
14137 | } | |
c6ec2b30 | 14138 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
14139 | { |
14140 | /* Long multiply, long multiply accumulate, and divide. */ | |
14141 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
14142 | } | |
c6ec2b30 | 14143 | else if (op2 & 0x40) |
dda83cd7 SM |
14144 | { |
14145 | /* Co-processor instructions. */ | |
14146 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
14147 | } | |
c6ec2b30 OJ |
14148 | } |
14149 | ||
14150 | return -1; | |
14151 | } | |
72508ac0 | 14152 | |
ffdbe864 | 14153 | namespace { |
728a7913 YQ |
14154 | /* Abstract memory reader. */ |
14155 | ||
14156 | class abstract_memory_reader | |
14157 | { | |
14158 | public: | |
14159 | /* Read LEN bytes of target memory at address MEMADDR, placing the | |
14160 | results in GDB's memory at BUF. Return true on success. */ | |
14161 | ||
14162 | virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0; | |
14163 | }; | |
14164 | ||
14165 | /* Instruction reader from real target. */ | |
14166 | ||
14167 | class instruction_reader : public abstract_memory_reader | |
14168 | { | |
14169 | public: | |
632e107b | 14170 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
728a7913 YQ |
14171 | { |
14172 | if (target_read_memory (memaddr, buf, len)) | |
14173 | return false; | |
14174 | else | |
14175 | return true; | |
14176 | } | |
14177 | }; | |
14178 | ||
ffdbe864 YQ |
14179 | } // namespace |
14180 | ||
72508ac0 | 14181 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success |
85102364 | 14182 | and positive val on failure. */ |
72508ac0 PO |
14183 | |
14184 | static int | |
728a7913 | 14185 | extract_arm_insn (abstract_memory_reader& reader, |
4748a9be | 14186 | arm_insn_decode_record *insn_record, uint32_t insn_size) |
72508ac0 PO |
14187 | { |
14188 | gdb_byte buf[insn_size]; | |
14189 | ||
14190 | memset (&buf[0], 0, insn_size); | |
14191 | ||
728a7913 | 14192 | if (!reader.read (insn_record->this_addr, buf, insn_size)) |
72508ac0 PO |
14193 | return 1; |
14194 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
dda83cd7 | 14195 | insn_size, |
2959fed9 | 14196 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
14197 | return 0; |
14198 | } | |
14199 | ||
4748a9be | 14200 | typedef int (*sti_arm_hdl_fp_t) (arm_insn_decode_record*); |
72508ac0 PO |
14201 | |
14202 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
14203 | dispatch it. */ | |
14204 | ||
14205 | static int | |
4748a9be TT |
14206 | decode_insn (abstract_memory_reader &reader, |
14207 | arm_insn_decode_record *arm_record, | |
728a7913 | 14208 | record_type_t record_type, uint32_t insn_size) |
72508ac0 PO |
14209 | { |
14210 | ||
01e57735 YQ |
14211 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
14212 | instruction. */ | |
0fa9c223 | 14213 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
14214 | { |
14215 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
14216 | arm_record_data_proc_imm, /* 001. */ | |
14217 | arm_record_ld_st_imm_offset, /* 010. */ | |
14218 | arm_record_ld_st_reg_offset, /* 011. */ | |
14219 | arm_record_ld_st_multiple, /* 100. */ | |
14220 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 14221 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
14222 | arm_record_coproc_data_proc /* 111. */ |
14223 | }; | |
14224 | ||
01e57735 YQ |
14225 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
14226 | instruction. */ | |
0fa9c223 | 14227 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
14228 | { \ |
14229 | thumb_record_shift_add_sub, /* 000. */ | |
14230 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
14231 | thumb_record_ld_st_reg_offset, /* 010. */ | |
14232 | thumb_record_ld_st_imm_offset, /* 011. */ | |
14233 | thumb_record_ld_st_stack, /* 100. */ | |
14234 | thumb_record_misc, /* 101. */ | |
14235 | thumb_record_ldm_stm_swi, /* 110. */ | |
14236 | thumb_record_branch /* 111. */ | |
14237 | }; | |
14238 | ||
14239 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
14240 | uint32_t insn_id = 0; | |
14241 | ||
728a7913 | 14242 | if (extract_arm_insn (reader, arm_record, insn_size)) |
72508ac0 PO |
14243 | { |
14244 | if (record_debug) | |
01e57735 | 14245 | { |
6cb06a8c TT |
14246 | gdb_printf (gdb_stdlog, |
14247 | _("Process record: error reading memory at " | |
14248 | "addr %s len = %d.\n"), | |
14249 | paddress (arm_record->gdbarch, | |
14250 | arm_record->this_addr), insn_size); | |
01e57735 | 14251 | } |
72508ac0 PO |
14252 | return -1; |
14253 | } | |
14254 | else if (ARM_RECORD == record_type) | |
14255 | { | |
14256 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
14257 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
14258 | |
14259 | if (arm_record->cond == 0xf) | |
14260 | ret = arm_record_extension_space (arm_record); | |
14261 | else | |
01e57735 | 14262 | { |
ca92db2d YQ |
14263 | /* If this insn has fallen into extension space |
14264 | then we need not decode it anymore. */ | |
01e57735 YQ |
14265 | ret = arm_handle_insn[insn_id] (arm_record); |
14266 | } | |
ca92db2d YQ |
14267 | if (ret != ARM_RECORD_SUCCESS) |
14268 | { | |
14269 | arm_record_unsupported_insn (arm_record); | |
14270 | ret = -1; | |
14271 | } | |
72508ac0 PO |
14272 | } |
14273 | else if (THUMB_RECORD == record_type) | |
14274 | { | |
14275 | /* As thumb does not have condition codes, we set negative. */ | |
14276 | arm_record->cond = -1; | |
14277 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
14278 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
14279 | if (ret != ARM_RECORD_SUCCESS) |
14280 | { | |
14281 | arm_record_unsupported_insn (arm_record); | |
14282 | ret = -1; | |
14283 | } | |
72508ac0 PO |
14284 | } |
14285 | else if (THUMB2_RECORD == record_type) | |
14286 | { | |
c6ec2b30 OJ |
14287 | /* As thumb does not have condition codes, we set negative. */ |
14288 | arm_record->cond = -1; | |
14289 | ||
14290 | /* Swap first half of 32bit thumb instruction with second half. */ | |
14291 | arm_record->arm_insn | |
01e57735 | 14292 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 14293 | |
ca92db2d | 14294 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 14295 | |
ca92db2d | 14296 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
14297 | { |
14298 | arm_record_unsupported_insn (arm_record); | |
14299 | ret = -1; | |
14300 | } | |
72508ac0 PO |
14301 | } |
14302 | else | |
14303 | { | |
14304 | /* Throw assertion. */ | |
14305 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
14306 | } | |
14307 | ||
14308 | return ret; | |
14309 | } | |
14310 | ||
b121eeb9 YQ |
14311 | #if GDB_SELF_TEST |
14312 | namespace selftests { | |
14313 | ||
14314 | /* Provide both 16-bit and 32-bit thumb instructions. */ | |
14315 | ||
14316 | class instruction_reader_thumb : public abstract_memory_reader | |
14317 | { | |
14318 | public: | |
14319 | template<size_t SIZE> | |
14320 | instruction_reader_thumb (enum bfd_endian endian, | |
14321 | const uint16_t (&insns)[SIZE]) | |
14322 | : m_endian (endian), m_insns (insns), m_insns_size (SIZE) | |
14323 | {} | |
14324 | ||
632e107b | 14325 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
b121eeb9 YQ |
14326 | { |
14327 | SELF_CHECK (len == 4 || len == 2); | |
14328 | SELF_CHECK (memaddr % 2 == 0); | |
14329 | SELF_CHECK ((memaddr / 2) < m_insns_size); | |
14330 | ||
14331 | store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]); | |
14332 | if (len == 4) | |
14333 | { | |
14334 | store_unsigned_integer (&buf[2], 2, m_endian, | |
14335 | m_insns[memaddr / 2 + 1]); | |
14336 | } | |
14337 | return true; | |
14338 | } | |
14339 | ||
14340 | private: | |
14341 | enum bfd_endian m_endian; | |
14342 | const uint16_t *m_insns; | |
14343 | size_t m_insns_size; | |
14344 | }; | |
14345 | ||
14346 | static void | |
14347 | arm_record_test (void) | |
14348 | { | |
14349 | struct gdbarch_info info; | |
b121eeb9 YQ |
14350 | info.bfd_arch_info = bfd_scan_arch ("arm"); |
14351 | ||
14352 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14353 | ||
14354 | SELF_CHECK (gdbarch != NULL); | |
14355 | ||
14356 | /* 16-bit Thumb instructions. */ | |
14357 | { | |
4748a9be | 14358 | arm_insn_decode_record arm_record; |
b121eeb9 | 14359 | |
4748a9be | 14360 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14361 | arm_record.gdbarch = gdbarch; |
14362 | ||
14363 | static const uint16_t insns[] = { | |
14364 | /* db b2 uxtb r3, r3 */ | |
14365 | 0xb2db, | |
14366 | /* cd 58 ldr r5, [r1, r3] */ | |
14367 | 0x58cd, | |
14368 | }; | |
14369 | ||
14370 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
14371 | instruction_reader_thumb reader (endian, insns); | |
14372 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
14373 | THUMB_INSN_SIZE_BYTES); | |
14374 | ||
14375 | SELF_CHECK (ret == 0); | |
14376 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14377 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14378 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
14379 | ||
14380 | arm_record.this_addr += 2; | |
14381 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
14382 | THUMB_INSN_SIZE_BYTES); | |
14383 | ||
14384 | SELF_CHECK (ret == 0); | |
14385 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14386 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14387 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
14388 | } | |
14389 | ||
14390 | /* 32-bit Thumb-2 instructions. */ | |
14391 | { | |
4748a9be | 14392 | arm_insn_decode_record arm_record; |
b121eeb9 | 14393 | |
4748a9be | 14394 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
b121eeb9 YQ |
14395 | arm_record.gdbarch = gdbarch; |
14396 | ||
14397 | static const uint16_t insns[] = { | |
14398 | /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ | |
14399 | 0xee1d, 0x7f70, | |
14400 | }; | |
14401 | ||
14402 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
14403 | instruction_reader_thumb reader (endian, insns); | |
14404 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, | |
14405 | THUMB2_INSN_SIZE_BYTES); | |
14406 | ||
14407 | SELF_CHECK (ret == 0); | |
14408 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
14409 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
14410 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
14411 | } | |
14412 | } | |
9ecab40c SM |
14413 | |
14414 | /* Instruction reader from manually cooked instruction sequences. */ | |
14415 | ||
14416 | class test_arm_instruction_reader : public arm_instruction_reader | |
14417 | { | |
14418 | public: | |
14419 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
14420 | : m_insns (insns) | |
14421 | {} | |
14422 | ||
14423 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
14424 | { | |
14425 | SELF_CHECK (memaddr % 4 == 0); | |
14426 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
14427 | ||
14428 | return m_insns[memaddr / 4]; | |
14429 | } | |
14430 | ||
14431 | private: | |
14432 | const gdb::array_view<const uint32_t> m_insns; | |
14433 | }; | |
14434 | ||
14435 | static void | |
14436 | arm_analyze_prologue_test () | |
14437 | { | |
14438 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
14439 | { | |
14440 | struct gdbarch_info info; | |
9ecab40c SM |
14441 | info.byte_order = endianness; |
14442 | info.byte_order_for_code = endianness; | |
14443 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
14444 | ||
14445 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
14446 | ||
14447 | SELF_CHECK (gdbarch != NULL); | |
14448 | ||
14449 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
14450 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
14451 | UBSan. */ | |
14452 | const uint32_t insns[] = { | |
14453 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
14454 | 0xe1a05000, /* mov r5, r0 */ | |
14455 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
14456 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
14457 | }; | |
14458 | ||
14459 | test_arm_instruction_reader mem_reader (insns); | |
14460 | arm_prologue_cache cache; | |
0824193f | 14461 | arm_cache_init (&cache, gdbarch); |
9ecab40c SM |
14462 | |
14463 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
14464 | } | |
14465 | } | |
14466 | ||
b121eeb9 YQ |
14467 | } // namespace selftests |
14468 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
14469 | |
14470 | /* Cleans up local record registers and memory allocations. */ | |
14471 | ||
14472 | static void | |
4748a9be | 14473 | deallocate_reg_mem (arm_insn_decode_record *record) |
72508ac0 PO |
14474 | { |
14475 | xfree (record->arm_regs); | |
14476 | xfree (record->arm_mems); | |
14477 | } | |
14478 | ||
14479 | ||
01e57735 | 14480 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
14481 | memory that will be changed in current instruction to record_arch_list". |
14482 | Return -1 if something is wrong. */ | |
14483 | ||
14484 | int | |
01e57735 YQ |
14485 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
14486 | CORE_ADDR insn_addr) | |
72508ac0 PO |
14487 | { |
14488 | ||
72508ac0 PO |
14489 | uint32_t no_of_rec = 0; |
14490 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
14491 | ULONGEST t_bit = 0, insn_id = 0; | |
14492 | ||
14493 | ULONGEST u_regval = 0; | |
14494 | ||
4748a9be | 14495 | arm_insn_decode_record arm_record; |
72508ac0 | 14496 | |
4748a9be | 14497 | memset (&arm_record, 0, sizeof (arm_insn_decode_record)); |
72508ac0 PO |
14498 | arm_record.regcache = regcache; |
14499 | arm_record.this_addr = insn_addr; | |
14500 | arm_record.gdbarch = gdbarch; | |
14501 | ||
14502 | ||
14503 | if (record_debug > 1) | |
14504 | { | |
6cb06a8c TT |
14505 | gdb_printf (gdb_stdlog, "Process record: arm_process_record " |
14506 | "addr = %s\n", | |
14507 | paddress (gdbarch, arm_record.this_addr)); | |
72508ac0 PO |
14508 | } |
14509 | ||
728a7913 YQ |
14510 | instruction_reader reader; |
14511 | if (extract_arm_insn (reader, &arm_record, 2)) | |
72508ac0 PO |
14512 | { |
14513 | if (record_debug) | |
01e57735 | 14514 | { |
6cb06a8c TT |
14515 | gdb_printf (gdb_stdlog, |
14516 | _("Process record: error reading memory at " | |
14517 | "addr %s len = %d.\n"), | |
14518 | paddress (arm_record.gdbarch, | |
14519 | arm_record.this_addr), 2); | |
01e57735 | 14520 | } |
72508ac0 PO |
14521 | return -1; |
14522 | } | |
14523 | ||
14524 | /* Check the insn, whether it is thumb or arm one. */ | |
14525 | ||
14526 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
14527 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
14528 | ||
14529 | ||
14530 | if (!(u_regval & t_bit)) | |
14531 | { | |
14532 | /* We are decoding arm insn. */ | |
728a7913 | 14533 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
14534 | } |
14535 | else | |
14536 | { | |
14537 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
14538 | /* is it thumb2 insn? */ | |
14539 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 14540 | { |
728a7913 | 14541 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
14542 | THUMB2_INSN_SIZE_BYTES); |
14543 | } | |
72508ac0 | 14544 | else |
01e57735 YQ |
14545 | { |
14546 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
14547 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
14548 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 14549 | } |
72508ac0 PO |
14550 | } |
14551 | ||
14552 | if (0 == ret) | |
14553 | { | |
14554 | /* Record registers. */ | |
25ea693b | 14555 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 14556 | if (arm_record.arm_regs) |
01e57735 YQ |
14557 | { |
14558 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
14559 | { | |
14560 | if (record_full_arch_list_add_reg | |
25ea693b | 14561 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
14562 | ret = -1; |
14563 | } | |
14564 | } | |
72508ac0 PO |
14565 | /* Record memories. */ |
14566 | if (arm_record.arm_mems) | |
01e57735 YQ |
14567 | { |
14568 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
14569 | { | |
14570 | if (record_full_arch_list_add_mem | |
14571 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 14572 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
14573 | ret = -1; |
14574 | } | |
14575 | } | |
72508ac0 | 14576 | |
25ea693b | 14577 | if (record_full_arch_list_add_end ()) |
01e57735 | 14578 | ret = -1; |
72508ac0 PO |
14579 | } |
14580 | ||
14581 | ||
14582 | deallocate_reg_mem (&arm_record); | |
14583 | ||
14584 | return ret; | |
14585 | } | |
d105cce5 AH |
14586 | |
14587 | /* See arm-tdep.h. */ | |
14588 | ||
14589 | const target_desc * | |
92d48a1e | 14590 | arm_read_description (arm_fp_type fp_type, bool tls) |
d105cce5 | 14591 | { |
92d48a1e | 14592 | struct target_desc *tdesc = tdesc_arm_list[fp_type][tls]; |
d105cce5 AH |
14593 | |
14594 | if (tdesc == nullptr) | |
14595 | { | |
92d48a1e JB |
14596 | tdesc = arm_create_target_description (fp_type, tls); |
14597 | tdesc_arm_list[fp_type][tls] = tdesc; | |
d105cce5 AH |
14598 | } |
14599 | ||
14600 | return tdesc; | |
14601 | } | |
14602 | ||
14603 | /* See arm-tdep.h. */ | |
14604 | ||
14605 | const target_desc * | |
14606 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
14607 | { | |
14608 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
14609 | ||
14610 | if (tdesc == nullptr) | |
14611 | { | |
14612 | tdesc = arm_create_mprofile_target_description (m_type); | |
14613 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
14614 | } | |
14615 | ||
14616 | return tdesc; | |
14617 | } |