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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
4a94e368 | 3 | Copyright (C) 1988-2022 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
0baeab03 PA |
20 | #include "defs.h" |
21 | ||
4de283e4 | 22 | #include <ctype.h> /* XXX for isupper (). */ |
34e8f22d | 23 | |
4de283e4 TT |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "infrun.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "dis-asm.h" /* For register styles. */ | |
30 | #include "disasm.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "target-float.h" | |
34 | #include "value.h" | |
d55e5aa6 | 35 | #include "arch-utils.h" |
4de283e4 TT |
36 | #include "osabi.h" |
37 | #include "frame-unwind.h" | |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
40 | #include "objfiles.h" | |
a01567f4 | 41 | #include "dwarf2.h" |
82ca8957 | 42 | #include "dwarf2/frame.h" |
4de283e4 TT |
43 | #include "gdbtypes.h" |
44 | #include "prologue-value.h" | |
45 | #include "remote.h" | |
46 | #include "target-descriptions.h" | |
47 | #include "user-regs.h" | |
48 | #include "observable.h" | |
5f661e03 | 49 | #include "count-one-bits.h" |
4de283e4 | 50 | |
d55e5aa6 | 51 | #include "arch/arm.h" |
4de283e4 | 52 | #include "arch/arm-get-next-pcs.h" |
34e8f22d | 53 | #include "arm-tdep.h" |
4de283e4 TT |
54 | #include "gdb/sim-arm.h" |
55 | ||
d55e5aa6 | 56 | #include "elf-bfd.h" |
4de283e4 | 57 | #include "coff/internal.h" |
d55e5aa6 | 58 | #include "elf/arm.h" |
4de283e4 | 59 | |
4de283e4 TT |
60 | #include "record.h" |
61 | #include "record-full.h" | |
62 | #include <algorithm> | |
63 | ||
c2fd7fae AKS |
64 | #include "producer.h" |
65 | ||
b121eeb9 | 66 | #if GDB_SELF_TEST |
268a13a5 | 67 | #include "gdbsupport/selftest.h" |
b121eeb9 YQ |
68 | #endif |
69 | ||
491144b5 | 70 | static bool arm_debug; |
6529d2dd | 71 | |
7cb6d92a SM |
72 | /* Print an "arm" debug statement. */ |
73 | ||
74 | #define arm_debug_printf(fmt, ...) \ | |
75 | debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__) | |
76 | ||
082fc60d RE |
77 | /* Macros for setting and testing a bit in a minimal symbol that marks |
78 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 79 | is used for this purpose. |
082fc60d RE |
80 | |
81 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 82 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d | 83 | |
0963b4bd | 84 | #define MSYMBOL_SET_SPECIAL(msym) \ |
e165fcef | 85 | (msym)->set_target_flag_1 (true) |
082fc60d RE |
86 | |
87 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
e165fcef | 88 | (msym)->target_flag_1 () |
082fc60d | 89 | |
60c5725c DJ |
90 | struct arm_mapping_symbol |
91 | { | |
227031b2 | 92 | CORE_ADDR value; |
60c5725c | 93 | char type; |
54cc7474 SM |
94 | |
95 | bool operator< (const arm_mapping_symbol &other) const | |
96 | { return this->value < other.value; } | |
60c5725c | 97 | }; |
54cc7474 SM |
98 | |
99 | typedef std::vector<arm_mapping_symbol> arm_mapping_symbol_vec; | |
60c5725c | 100 | |
bd5766ec | 101 | struct arm_per_bfd |
60c5725c | 102 | { |
bd5766ec | 103 | explicit arm_per_bfd (size_t num_sections) |
4838e44c SM |
104 | : section_maps (new arm_mapping_symbol_vec[num_sections]), |
105 | section_maps_sorted (new bool[num_sections] ()) | |
54cc7474 SM |
106 | {} |
107 | ||
bd5766ec | 108 | DISABLE_COPY_AND_ASSIGN (arm_per_bfd); |
54cc7474 SM |
109 | |
110 | /* Information about mapping symbols ($a, $d, $t) in the objfile. | |
111 | ||
112 | The format is an array of vectors of arm_mapping_symbols, there is one | |
113 | vector for each section of the objfile (the array is index by BFD section | |
114 | index). | |
115 | ||
116 | For each section, the vector of arm_mapping_symbol is sorted by | |
117 | symbol value (address). */ | |
118 | std::unique_ptr<arm_mapping_symbol_vec[]> section_maps; | |
4838e44c SM |
119 | |
120 | /* For each corresponding element of section_maps above, is this vector | |
121 | sorted. */ | |
122 | std::unique_ptr<bool[]> section_maps_sorted; | |
60c5725c DJ |
123 | }; |
124 | ||
bd5766ec LM |
125 | /* Per-bfd data used for mapping symbols. */ |
126 | static bfd_key<arm_per_bfd> arm_bfd_data_key; | |
1b7f24cd | 127 | |
afd7eef0 RE |
128 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
129 | static struct cmd_list_element *setarmcmdlist = NULL; | |
130 | static struct cmd_list_element *showarmcmdlist = NULL; | |
131 | ||
fd50bc42 RE |
132 | /* The type of floating-point to use. Keep this in sync with enum |
133 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
40478521 | 134 | static const char *const fp_model_strings[] = |
fd50bc42 RE |
135 | { |
136 | "auto", | |
137 | "softfpa", | |
138 | "fpa", | |
139 | "softvfp", | |
28e97307 DJ |
140 | "vfp", |
141 | NULL | |
fd50bc42 RE |
142 | }; |
143 | ||
144 | /* A variable that can be configured by the user. */ | |
145 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
146 | static const char *current_fp_model = "auto"; | |
147 | ||
28e97307 | 148 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
40478521 | 149 | static const char *const arm_abi_strings[] = |
28e97307 DJ |
150 | { |
151 | "auto", | |
152 | "APCS", | |
153 | "AAPCS", | |
154 | NULL | |
155 | }; | |
156 | ||
157 | /* A variable that can be configured by the user. */ | |
158 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
159 | static const char *arm_abi_string = "auto"; | |
160 | ||
0428b8f5 | 161 | /* The execution mode to assume. */ |
40478521 | 162 | static const char *const arm_mode_strings[] = |
0428b8f5 DJ |
163 | { |
164 | "auto", | |
165 | "arm", | |
68770265 MGD |
166 | "thumb", |
167 | NULL | |
0428b8f5 DJ |
168 | }; |
169 | ||
170 | static const char *arm_fallback_mode_string = "auto"; | |
171 | static const char *arm_force_mode_string = "auto"; | |
172 | ||
f32bf4a4 YQ |
173 | /* The standard register names, and all the valid aliases for them. Note |
174 | that `fp', `sp' and `pc' are not added in this alias list, because they | |
175 | have been added as builtin user registers in | |
176 | std-regs.c:_initialize_frame_reg. */ | |
123dc839 DJ |
177 | static const struct |
178 | { | |
179 | const char *name; | |
180 | int regnum; | |
181 | } arm_register_aliases[] = { | |
182 | /* Basic register numbers. */ | |
183 | { "r0", 0 }, | |
184 | { "r1", 1 }, | |
185 | { "r2", 2 }, | |
186 | { "r3", 3 }, | |
187 | { "r4", 4 }, | |
188 | { "r5", 5 }, | |
189 | { "r6", 6 }, | |
190 | { "r7", 7 }, | |
191 | { "r8", 8 }, | |
192 | { "r9", 9 }, | |
193 | { "r10", 10 }, | |
194 | { "r11", 11 }, | |
195 | { "r12", 12 }, | |
196 | { "r13", 13 }, | |
197 | { "r14", 14 }, | |
198 | { "r15", 15 }, | |
199 | /* Synonyms (argument and variable registers). */ | |
200 | { "a1", 0 }, | |
201 | { "a2", 1 }, | |
202 | { "a3", 2 }, | |
203 | { "a4", 3 }, | |
204 | { "v1", 4 }, | |
205 | { "v2", 5 }, | |
206 | { "v3", 6 }, | |
207 | { "v4", 7 }, | |
208 | { "v5", 8 }, | |
209 | { "v6", 9 }, | |
210 | { "v7", 10 }, | |
211 | { "v8", 11 }, | |
212 | /* Other platform-specific names for r9. */ | |
213 | { "sb", 9 }, | |
214 | { "tr", 9 }, | |
215 | /* Special names. */ | |
216 | { "ip", 12 }, | |
123dc839 | 217 | { "lr", 14 }, |
123dc839 DJ |
218 | /* Names used by GCC (not listed in the ARM EABI). */ |
219 | { "sl", 10 }, | |
123dc839 DJ |
220 | /* A special name from the older ATPCS. */ |
221 | { "wr", 7 }, | |
222 | }; | |
bc90b915 | 223 | |
123dc839 | 224 | static const char *const arm_register_names[] = |
da59e081 JM |
225 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
226 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
227 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
228 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
229 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
230 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 231 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 232 | |
65b48a81 PB |
233 | /* Holds the current set of options to be passed to the disassembler. */ |
234 | static char *arm_disassembler_options; | |
235 | ||
afd7eef0 RE |
236 | /* Valid register name styles. */ |
237 | static const char **valid_disassembly_styles; | |
ed9a39eb | 238 | |
afd7eef0 RE |
239 | /* Disassembly style to use. Default to "std" register names. */ |
240 | static const char *disassembly_style; | |
96baa820 | 241 | |
d105cce5 AH |
242 | /* All possible arm target descriptors. */ |
243 | static struct target_desc *tdesc_arm_list[ARM_FP_TYPE_INVALID]; | |
244 | static struct target_desc *tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]; | |
245 | ||
ed9a39eb | 246 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 | 247 | style. */ |
eb4c3f4a | 248 | static void set_disassembly_style_sfunc (const char *, int, |
ed9a39eb | 249 | struct cmd_list_element *); |
65b48a81 PB |
250 | static void show_disassembly_style_sfunc (struct ui_file *, int, |
251 | struct cmd_list_element *, | |
252 | const char *); | |
ed9a39eb | 253 | |
05d1431c | 254 | static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch, |
849d0ba8 | 255 | readable_regcache *regcache, |
05d1431c | 256 | int regnum, gdb_byte *buf); |
58d6951d DJ |
257 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
258 | struct regcache *regcache, | |
259 | int regnum, const gdb_byte *buf); | |
260 | ||
e7cf25a8 | 261 | static CORE_ADDR |
553cb527 | 262 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
e7cf25a8 YQ |
263 | |
264 | ||
d9311bfa AT |
265 | /* get_next_pcs operations. */ |
266 | static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { | |
267 | arm_get_next_pcs_read_memory_unsigned_integer, | |
268 | arm_get_next_pcs_syscall_next_pc, | |
269 | arm_get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
270 | arm_get_next_pcs_is_thumb, |
271 | NULL, | |
d9311bfa AT |
272 | }; |
273 | ||
9b8d791a | 274 | struct arm_prologue_cache |
c3b4394c | 275 | { |
eb5492fa DJ |
276 | /* The stack pointer at the time this frame was created; i.e. the |
277 | caller's stack pointer when this function was called. It is used | |
278 | to identify this frame. */ | |
279 | CORE_ADDR prev_sp; | |
280 | ||
4be43953 DJ |
281 | /* The frame base for this frame is just prev_sp - frame size. |
282 | FRAMESIZE is the distance from the frame pointer to the | |
283 | initial stack pointer. */ | |
eb5492fa | 284 | |
c3b4394c | 285 | int framesize; |
eb5492fa DJ |
286 | |
287 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 288 | int framereg; |
eb5492fa | 289 | |
a01567f4 LM |
290 | /* True if the return address is signed, false otherwise. */ |
291 | gdb::optional<bool> ra_signed_state; | |
292 | ||
eb5492fa | 293 | /* Saved register offsets. */ |
098caef4 | 294 | trad_frame_saved_reg *saved_regs; |
c3b4394c | 295 | }; |
ed9a39eb | 296 | |
9ecab40c SM |
297 | namespace { |
298 | ||
299 | /* Abstract class to read ARM instructions from memory. */ | |
300 | ||
301 | class arm_instruction_reader | |
302 | { | |
303 | public: | |
2c5b1849 | 304 | /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */ |
9ecab40c SM |
305 | virtual uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const = 0; |
306 | }; | |
307 | ||
308 | /* Read instructions from target memory. */ | |
309 | ||
310 | class target_arm_instruction_reader : public arm_instruction_reader | |
311 | { | |
312 | public: | |
313 | uint32_t read (CORE_ADDR memaddr, bfd_endian byte_order) const override | |
314 | { | |
315 | return read_code_unsigned_integer (memaddr, 4, byte_order); | |
316 | } | |
317 | }; | |
318 | ||
319 | } /* namespace */ | |
320 | ||
321 | static CORE_ADDR arm_analyze_prologue | |
322 | (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
323 | struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); | |
0d39a070 | 324 | |
cca44b1b JB |
325 | /* Architecture version for displaced stepping. This effects the behaviour of |
326 | certain instructions, and really should not be hard-wired. */ | |
327 | ||
328 | #define DISPLACED_STEPPING_ARCH_VERSION 5 | |
329 | ||
c7ae7675 | 330 | /* See arm-tdep.h. */ |
c906108c | 331 | |
491144b5 | 332 | bool arm_apcs_32 = true; |
c906108c | 333 | |
9779414d DJ |
334 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
335 | ||
478fd957 | 336 | int |
9779414d DJ |
337 | arm_psr_thumb_bit (struct gdbarch *gdbarch) |
338 | { | |
345bd07c SM |
339 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
340 | ||
341 | if (tdep->is_m) | |
9779414d DJ |
342 | return XPSR_T; |
343 | else | |
344 | return CPSR_T; | |
345 | } | |
346 | ||
d0e59a68 AT |
347 | /* Determine if the processor is currently executing in Thumb mode. */ |
348 | ||
349 | int | |
350 | arm_is_thumb (struct regcache *regcache) | |
351 | { | |
352 | ULONGEST cpsr; | |
ac7936df | 353 | ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ()); |
d0e59a68 AT |
354 | |
355 | cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); | |
356 | ||
357 | return (cpsr & t_bit) != 0; | |
358 | } | |
359 | ||
b39cc962 DJ |
360 | /* Determine if FRAME is executing in Thumb mode. */ |
361 | ||
25b41d01 | 362 | int |
b39cc962 DJ |
363 | arm_frame_is_thumb (struct frame_info *frame) |
364 | { | |
365 | CORE_ADDR cpsr; | |
9779414d | 366 | ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); |
b39cc962 DJ |
367 | |
368 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
369 | directly (from a signal frame or dummy frame) or by interpreting | |
370 | the saved LR (from a prologue or DWARF frame). So consult it and | |
371 | trust the unwinders. */ | |
372 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
373 | ||
9779414d | 374 | return (cpsr & t_bit) != 0; |
b39cc962 DJ |
375 | } |
376 | ||
f9d67f43 DJ |
377 | /* Search for the mapping symbol covering MEMADDR. If one is found, |
378 | return its type. Otherwise, return 0. If START is non-NULL, | |
379 | set *START to the location of the mapping symbol. */ | |
c906108c | 380 | |
f9d67f43 DJ |
381 | static char |
382 | arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) | |
c906108c | 383 | { |
60c5725c | 384 | struct obj_section *sec; |
0428b8f5 | 385 | |
60c5725c DJ |
386 | /* If there are mapping symbols, consult them. */ |
387 | sec = find_pc_section (memaddr); | |
388 | if (sec != NULL) | |
389 | { | |
bd5766ec | 390 | arm_per_bfd *data = arm_bfd_data_key.get (sec->objfile->obfd); |
60c5725c DJ |
391 | if (data != NULL) |
392 | { | |
4838e44c SM |
393 | unsigned int section_idx = sec->the_bfd_section->index; |
394 | arm_mapping_symbol_vec &map | |
395 | = data->section_maps[section_idx]; | |
396 | ||
397 | /* Sort the vector on first use. */ | |
398 | if (!data->section_maps_sorted[section_idx]) | |
399 | { | |
400 | std::sort (map.begin (), map.end ()); | |
401 | data->section_maps_sorted[section_idx] = true; | |
402 | } | |
403 | ||
0c1bcd23 | 404 | arm_mapping_symbol map_key = { memaddr - sec->addr (), 0 }; |
54cc7474 SM |
405 | arm_mapping_symbol_vec::const_iterator it |
406 | = std::lower_bound (map.begin (), map.end (), map_key); | |
407 | ||
408 | /* std::lower_bound finds the earliest ordered insertion | |
409 | point. If the symbol at this position starts at this exact | |
410 | address, we use that; otherwise, the preceding | |
411 | mapping symbol covers this address. */ | |
412 | if (it < map.end ()) | |
60c5725c | 413 | { |
54cc7474 | 414 | if (it->value == map_key.value) |
60c5725c | 415 | { |
f9d67f43 | 416 | if (start) |
0c1bcd23 | 417 | *start = it->value + sec->addr (); |
54cc7474 | 418 | return it->type; |
60c5725c DJ |
419 | } |
420 | } | |
54cc7474 SM |
421 | |
422 | if (it > map.begin ()) | |
423 | { | |
424 | arm_mapping_symbol_vec::const_iterator prev_it | |
425 | = it - 1; | |
426 | ||
427 | if (start) | |
0c1bcd23 | 428 | *start = prev_it->value + sec->addr (); |
54cc7474 SM |
429 | return prev_it->type; |
430 | } | |
60c5725c DJ |
431 | } |
432 | } | |
433 | ||
f9d67f43 DJ |
434 | return 0; |
435 | } | |
436 | ||
437 | /* Determine if the program counter specified in MEMADDR is in a Thumb | |
438 | function. This function should be called for addresses unrelated to | |
439 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
440 | ||
e3039479 | 441 | int |
9779414d | 442 | arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
f9d67f43 | 443 | { |
7cbd4a93 | 444 | struct bound_minimal_symbol sym; |
f9d67f43 | 445 | char type; |
187b041e | 446 | arm_displaced_step_copy_insn_closure *dsc = nullptr; |
345bd07c | 447 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
187b041e SM |
448 | |
449 | if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch)) | |
450 | dsc = ((arm_displaced_step_copy_insn_closure * ) | |
451 | gdbarch_displaced_step_copy_insn_closure_by_addr | |
452 | (gdbarch, current_inferior (), memaddr)); | |
a42244db YQ |
453 | |
454 | /* If checking the mode of displaced instruction in copy area, the mode | |
455 | should be determined by instruction on the original address. */ | |
456 | if (dsc) | |
457 | { | |
136821d9 SM |
458 | displaced_debug_printf ("check mode of %.8lx instead of %.8lx", |
459 | (unsigned long) dsc->insn_addr, | |
460 | (unsigned long) memaddr); | |
a42244db YQ |
461 | memaddr = dsc->insn_addr; |
462 | } | |
f9d67f43 DJ |
463 | |
464 | /* If bit 0 of the address is set, assume this is a Thumb address. */ | |
465 | if (IS_THUMB_ADDR (memaddr)) | |
466 | return 1; | |
467 | ||
468 | /* If the user wants to override the symbol table, let him. */ | |
469 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
470 | return 0; | |
471 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
472 | return 1; | |
473 | ||
9779414d | 474 | /* ARM v6-M and v7-M are always in Thumb mode. */ |
345bd07c | 475 | if (tdep->is_m) |
9779414d DJ |
476 | return 1; |
477 | ||
f9d67f43 DJ |
478 | /* If there are mapping symbols, consult them. */ |
479 | type = arm_find_mapping_symbol (memaddr, NULL); | |
480 | if (type) | |
481 | return type == 't'; | |
482 | ||
ed9a39eb | 483 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c | 484 | sym = lookup_minimal_symbol_by_pc (memaddr); |
7cbd4a93 TT |
485 | if (sym.minsym) |
486 | return (MSYMBOL_IS_SPECIAL (sym.minsym)); | |
0428b8f5 DJ |
487 | |
488 | /* If the user wants to override the fallback mode, let them. */ | |
489 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
490 | return 0; | |
491 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
492 | return 1; | |
493 | ||
494 | /* If we couldn't find any symbol, but we're talking to a running | |
495 | target, then trust the current value of $cpsr. This lets | |
496 | "display/i $pc" always show the correct mode (though if there is | |
497 | a symbol table we will not reach here, so it still may not be | |
18819fa6 | 498 | displayed in the mode it will be executed). */ |
9dccd06e | 499 | if (target_has_registers ()) |
18819fa6 | 500 | return arm_frame_is_thumb (get_current_frame ()); |
0428b8f5 DJ |
501 | |
502 | /* Otherwise we're out of luck; we assume ARM. */ | |
503 | return 0; | |
c906108c SS |
504 | } |
505 | ||
ca90e760 | 506 | /* Determine if the address specified equals any of these magic return |
55ea94da | 507 | values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M |
ca90e760 FH |
508 | architectures. |
509 | ||
510 | From ARMv6-M Reference Manual B1.5.8 | |
511 | Table B1-5 Exception return behavior | |
512 | ||
513 | EXC_RETURN Return To Return Stack | |
514 | 0xFFFFFFF1 Handler mode Main | |
515 | 0xFFFFFFF9 Thread mode Main | |
516 | 0xFFFFFFFD Thread mode Process | |
517 | ||
518 | From ARMv7-M Reference Manual B1.5.8 | |
519 | Table B1-8 EXC_RETURN definition of exception return behavior, no FP | |
520 | ||
521 | EXC_RETURN Return To Return Stack | |
522 | 0xFFFFFFF1 Handler mode Main | |
523 | 0xFFFFFFF9 Thread mode Main | |
524 | 0xFFFFFFFD Thread mode Process | |
525 | ||
526 | Table B1-9 EXC_RETURN definition of exception return behavior, with | |
527 | FP | |
528 | ||
529 | EXC_RETURN Return To Return Stack Frame Type | |
530 | 0xFFFFFFE1 Handler mode Main Extended | |
531 | 0xFFFFFFE9 Thread mode Main Extended | |
532 | 0xFFFFFFED Thread mode Process Extended | |
533 | 0xFFFFFFF1 Handler mode Main Basic | |
534 | 0xFFFFFFF9 Thread mode Main Basic | |
535 | 0xFFFFFFFD Thread mode Process Basic | |
536 | ||
537 | For more details see "B1.5.8 Exception return behavior" | |
55ea94da FH |
538 | in both ARMv6-M and ARMv7-M Architecture Reference Manuals. |
539 | ||
540 | In the ARMv8-M Architecture Technical Reference also adds | |
541 | for implementations without the Security Extension: | |
542 | ||
543 | EXC_RETURN Condition | |
544 | 0xFFFFFFB0 Return to Handler mode. | |
545 | 0xFFFFFFB8 Return to Thread mode using the main stack. | |
546 | 0xFFFFFFBC Return to Thread mode using the process stack. */ | |
ca90e760 FH |
547 | |
548 | static int | |
549 | arm_m_addr_is_magic (CORE_ADDR addr) | |
550 | { | |
551 | switch (addr) | |
552 | { | |
55ea94da FH |
553 | /* Values from ARMv8-M Architecture Technical Reference. */ |
554 | case 0xffffffb0: | |
555 | case 0xffffffb8: | |
556 | case 0xffffffbc: | |
ca90e760 FH |
557 | /* Values from Tables in B1.5.8 the EXC_RETURN definitions of |
558 | the exception return behavior. */ | |
559 | case 0xffffffe1: | |
560 | case 0xffffffe9: | |
561 | case 0xffffffed: | |
562 | case 0xfffffff1: | |
563 | case 0xfffffff9: | |
564 | case 0xfffffffd: | |
565 | /* Address is magic. */ | |
566 | return 1; | |
567 | ||
568 | default: | |
569 | /* Address is not magic. */ | |
570 | return 0; | |
571 | } | |
572 | } | |
573 | ||
181c1381 | 574 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 575 | static CORE_ADDR |
24568a2c | 576 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
c906108c | 577 | { |
345bd07c SM |
578 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
579 | ||
2ae28aa9 YQ |
580 | /* On M-profile devices, do not strip the low bit from EXC_RETURN |
581 | (the magic exception return address). */ | |
345bd07c | 582 | if (tdep->is_m && arm_m_addr_is_magic (val)) |
2ae28aa9 YQ |
583 | return val; |
584 | ||
a3a2ee65 | 585 | if (arm_apcs_32) |
dd6be234 | 586 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 587 | else |
a3a2ee65 | 588 | return (val & 0x03fffffc); |
c906108c SS |
589 | } |
590 | ||
0d39a070 | 591 | /* Return 1 if PC is the start of a compiler helper function which |
e0634ccf UW |
592 | can be safely ignored during prologue skipping. IS_THUMB is true |
593 | if the function is known to be a Thumb function due to the way it | |
594 | is being called. */ | |
0d39a070 | 595 | static int |
e0634ccf | 596 | skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) |
0d39a070 | 597 | { |
e0634ccf | 598 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7cbd4a93 | 599 | struct bound_minimal_symbol msym; |
0d39a070 DJ |
600 | |
601 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 602 | if (msym.minsym != NULL |
4aeddc50 | 603 | && msym.value_address () == pc |
c9d95fa3 | 604 | && msym.minsym->linkage_name () != NULL) |
e0634ccf | 605 | { |
c9d95fa3 | 606 | const char *name = msym.minsym->linkage_name (); |
0d39a070 | 607 | |
e0634ccf UW |
608 | /* The GNU linker's Thumb call stub to foo is named |
609 | __foo_from_thumb. */ | |
610 | if (strstr (name, "_from_thumb") != NULL) | |
611 | name += 2; | |
0d39a070 | 612 | |
e0634ccf UW |
613 | /* On soft-float targets, __truncdfsf2 is called to convert promoted |
614 | arguments to their argument types in non-prototyped | |
615 | functions. */ | |
61012eef | 616 | if (startswith (name, "__truncdfsf2")) |
e0634ccf | 617 | return 1; |
61012eef | 618 | if (startswith (name, "__aeabi_d2f")) |
e0634ccf | 619 | return 1; |
0d39a070 | 620 | |
e0634ccf | 621 | /* Internal functions related to thread-local storage. */ |
61012eef | 622 | if (startswith (name, "__tls_get_addr")) |
e0634ccf | 623 | return 1; |
61012eef | 624 | if (startswith (name, "__aeabi_read_tp")) |
e0634ccf UW |
625 | return 1; |
626 | } | |
627 | else | |
628 | { | |
629 | /* If we run against a stripped glibc, we may be unable to identify | |
630 | special functions by name. Check for one important case, | |
631 | __aeabi_read_tp, by comparing the *code* against the default | |
632 | implementation (this is hand-written ARM assembler in glibc). */ | |
633 | ||
634 | if (!is_thumb | |
198cd59d | 635 | && read_code_unsigned_integer (pc, 4, byte_order_for_code) |
e0634ccf | 636 | == 0xe3e00a0f /* mov r0, #0xffff0fff */ |
198cd59d | 637 | && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) |
e0634ccf UW |
638 | == 0xe240f01f) /* sub pc, r0, #31 */ |
639 | return 1; | |
640 | } | |
ec3d575a | 641 | |
0d39a070 DJ |
642 | return 0; |
643 | } | |
644 | ||
621c6d5b YQ |
645 | /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is |
646 | the first 16-bit of instruction, and INSN2 is the second 16-bit of | |
647 | instruction. */ | |
648 | #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \ | |
649 | ((bits ((insn1), 0, 3) << 12) \ | |
650 | | (bits ((insn1), 10, 10) << 11) \ | |
651 | | (bits ((insn2), 12, 14) << 8) \ | |
652 | | bits ((insn2), 0, 7)) | |
653 | ||
654 | /* Extract the immediate from instruction movw/movt of encoding A. INSN is | |
655 | the 32-bit instruction. */ | |
656 | #define EXTRACT_MOVW_MOVT_IMM_A(insn) \ | |
657 | ((bits ((insn), 16, 19) << 12) \ | |
658 | | bits ((insn), 0, 11)) | |
659 | ||
ec3d575a UW |
660 | /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */ |
661 | ||
662 | static unsigned int | |
663 | thumb_expand_immediate (unsigned int imm) | |
664 | { | |
665 | unsigned int count = imm >> 7; | |
666 | ||
667 | if (count < 8) | |
668 | switch (count / 2) | |
669 | { | |
670 | case 0: | |
671 | return imm & 0xff; | |
672 | case 1: | |
673 | return (imm & 0xff) | ((imm & 0xff) << 16); | |
674 | case 2: | |
675 | return ((imm & 0xff) << 8) | ((imm & 0xff) << 24); | |
676 | case 3: | |
677 | return (imm & 0xff) | ((imm & 0xff) << 8) | |
678 | | ((imm & 0xff) << 16) | ((imm & 0xff) << 24); | |
679 | } | |
680 | ||
681 | return (0x80 | (imm & 0x7f)) << (32 - count); | |
682 | } | |
683 | ||
540314bd YQ |
684 | /* Return 1 if the 16-bit Thumb instruction INSN restores SP in |
685 | epilogue, 0 otherwise. */ | |
686 | ||
687 | static int | |
688 | thumb_instruction_restores_sp (unsigned short insn) | |
689 | { | |
690 | return (insn == 0x46bd /* mov sp, r7 */ | |
691 | || (insn & 0xff80) == 0xb000 /* add sp, imm */ | |
692 | || (insn & 0xfe00) == 0xbc00); /* pop <registers> */ | |
693 | } | |
694 | ||
29d73ae4 DJ |
695 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
696 | and frame pointer. Scan until we encounter a store that could | |
0d39a070 DJ |
697 | clobber the stack frame unexpectedly, or an unknown instruction. |
698 | Return the last address which is definitely safe to skip for an | |
699 | initial breakpoint. */ | |
c906108c SS |
700 | |
701 | static CORE_ADDR | |
29d73ae4 DJ |
702 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
703 | CORE_ADDR start, CORE_ADDR limit, | |
704 | struct arm_prologue_cache *cache) | |
c906108c | 705 | { |
0d39a070 | 706 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e17a4113 | 707 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
29d73ae4 DJ |
708 | int i; |
709 | pv_t regs[16]; | |
29d73ae4 | 710 | CORE_ADDR offset; |
ec3d575a | 711 | CORE_ADDR unrecognized_pc = 0; |
da3c6d4a | 712 | |
29d73ae4 DJ |
713 | for (i = 0; i < 16; i++) |
714 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 715 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
29d73ae4 | 716 | |
29d73ae4 | 717 | while (start < limit) |
c906108c | 718 | { |
29d73ae4 | 719 | unsigned short insn; |
a01567f4 | 720 | gdb::optional<bool> ra_signed_state; |
29d73ae4 | 721 | |
198cd59d | 722 | insn = read_code_unsigned_integer (start, 2, byte_order_for_code); |
9d4fde75 | 723 | |
94c30b78 | 724 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 725 | { |
29d73ae4 DJ |
726 | int regno; |
727 | int mask; | |
4be43953 | 728 | |
f7b7ed97 | 729 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 | 730 | break; |
29d73ae4 DJ |
731 | |
732 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
733 | whether to save LR (R14). */ | |
734 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
735 | ||
736 | /* Calculate offsets of saved R0-R7 and LR. */ | |
737 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
738 | if (mask & (1 << regno)) | |
739 | { | |
29d73ae4 DJ |
740 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
741 | -4); | |
f7b7ed97 | 742 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
29d73ae4 | 743 | } |
da59e081 | 744 | } |
1db01f22 | 745 | else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ |
da59e081 | 746 | { |
29d73ae4 | 747 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
1db01f22 YQ |
748 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
749 | -offset); | |
da59e081 | 750 | } |
808f7ab1 YQ |
751 | else if (thumb_instruction_restores_sp (insn)) |
752 | { | |
753 | /* Don't scan past the epilogue. */ | |
754 | break; | |
755 | } | |
0d39a070 DJ |
756 | else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ |
757 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], | |
758 | (insn & 0xff) << 2); | |
759 | else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ | |
760 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
761 | regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], | |
762 | bits (insn, 6, 8)); | |
763 | else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ | |
764 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
765 | regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], | |
766 | bits (insn, 0, 7)); | |
767 | else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ | |
768 | && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) | |
769 | && pv_is_constant (regs[bits (insn, 3, 5)])) | |
770 | regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], | |
771 | regs[bits (insn, 6, 8)]); | |
772 | else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ | |
773 | && pv_is_constant (regs[bits (insn, 3, 6)])) | |
774 | { | |
775 | int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); | |
776 | int rm = bits (insn, 3, 6); | |
777 | regs[rd] = pv_add (regs[rd], regs[rm]); | |
778 | } | |
29d73ae4 | 779 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
da59e081 | 780 | { |
29d73ae4 DJ |
781 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
782 | int src_reg = (insn & 0x78) >> 3; | |
783 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 784 | } |
29d73ae4 | 785 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 786 | { |
29d73ae4 DJ |
787 | /* Handle stores to the stack. Normally pushes are used, |
788 | but with GCC -mtpcs-frame, there may be other stores | |
789 | in the prologue to create the frame. */ | |
790 | int regno = (insn >> 8) & 0x7; | |
791 | pv_t addr; | |
792 | ||
793 | offset = (insn & 0xff) << 2; | |
794 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
795 | ||
f7b7ed97 | 796 | if (stack.store_would_trash (addr)) |
29d73ae4 DJ |
797 | break; |
798 | ||
f7b7ed97 | 799 | stack.store (addr, 4, regs[regno]); |
da59e081 | 800 | } |
0d39a070 DJ |
801 | else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ |
802 | { | |
803 | int rd = bits (insn, 0, 2); | |
804 | int rn = bits (insn, 3, 5); | |
805 | pv_t addr; | |
806 | ||
807 | offset = bits (insn, 6, 10) << 2; | |
808 | addr = pv_add_constant (regs[rn], offset); | |
809 | ||
f7b7ed97 | 810 | if (stack.store_would_trash (addr)) |
0d39a070 DJ |
811 | break; |
812 | ||
f7b7ed97 | 813 | stack.store (addr, 4, regs[rd]); |
0d39a070 DJ |
814 | } |
815 | else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ | |
816 | || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ | |
817 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) | |
818 | /* Ignore stores of argument registers to the stack. */ | |
819 | ; | |
820 | else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ | |
821 | && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) | |
822 | /* Ignore block loads from the stack, potentially copying | |
823 | parameters from memory. */ | |
824 | ; | |
825 | else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ | |
826 | || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ | |
827 | && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) | |
828 | /* Similarly ignore single loads from the stack. */ | |
829 | ; | |
830 | else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ | |
831 | || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ | |
832 | /* Skip register copies, i.e. saves to another register | |
833 | instead of the stack. */ | |
834 | ; | |
835 | else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ | |
836 | /* Recognize constant loads; even with small stacks these are necessary | |
837 | on Thumb. */ | |
838 | regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); | |
839 | else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ | |
840 | { | |
841 | /* Constant pool loads, for the same reason. */ | |
842 | unsigned int constant; | |
843 | CORE_ADDR loc; | |
844 | ||
845 | loc = start + 4 + bits (insn, 0, 7) * 4; | |
846 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
847 | regs[bits (insn, 8, 10)] = pv_constant (constant); | |
848 | } | |
db24da6d | 849 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instructions. */ |
0d39a070 | 850 | { |
0d39a070 DJ |
851 | unsigned short inst2; |
852 | ||
198cd59d YQ |
853 | inst2 = read_code_unsigned_integer (start + 2, 2, |
854 | byte_order_for_code); | |
a01567f4 | 855 | uint32_t whole_insn = (insn << 16) | inst2; |
0d39a070 DJ |
856 | |
857 | if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) | |
858 | { | |
859 | /* BL, BLX. Allow some special function calls when | |
860 | skipping the prologue; GCC generates these before | |
861 | storing arguments to the stack. */ | |
862 | CORE_ADDR nextpc; | |
863 | int j1, j2, imm1, imm2; | |
864 | ||
865 | imm1 = sbits (insn, 0, 10); | |
866 | imm2 = bits (inst2, 0, 10); | |
867 | j1 = bit (inst2, 13); | |
868 | j2 = bit (inst2, 11); | |
869 | ||
870 | offset = ((imm1 << 12) + (imm2 << 1)); | |
871 | offset ^= ((!j2) << 22) | ((!j1) << 23); | |
872 | ||
873 | nextpc = start + 4 + offset; | |
874 | /* For BLX make sure to clear the low bits. */ | |
875 | if (bit (inst2, 12) == 0) | |
876 | nextpc = nextpc & 0xfffffffc; | |
877 | ||
e0634ccf UW |
878 | if (!skip_prologue_function (gdbarch, nextpc, |
879 | bit (inst2, 12) != 0)) | |
0d39a070 DJ |
880 | break; |
881 | } | |
ec3d575a | 882 | |
0963b4bd MS |
883 | else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, |
884 | { registers } */ | |
ec3d575a UW |
885 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
886 | { | |
887 | pv_t addr = regs[bits (insn, 0, 3)]; | |
888 | int regno; | |
889 | ||
f7b7ed97 | 890 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
891 | break; |
892 | ||
893 | /* Calculate offsets of saved registers. */ | |
894 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
895 | if (inst2 & (1 << regno)) | |
896 | { | |
897 | addr = pv_add_constant (addr, -4); | |
f7b7ed97 | 898 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
899 | } |
900 | ||
901 | if (insn & 0x0020) | |
902 | regs[bits (insn, 0, 3)] = addr; | |
903 | } | |
904 | ||
fcaa1071 CL |
905 | /* vstmdb Rn{!}, { D-registers } (aka vpush). */ |
906 | else if ((insn & 0xff20) == 0xed20 | |
907 | && (inst2 & 0x0f00) == 0x0b00 | |
908 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
909 | { | |
910 | /* Address SP points to. */ | |
911 | pv_t addr = regs[bits (insn, 0, 3)]; | |
912 | ||
913 | /* Number of registers saved. */ | |
914 | unsigned int number = bits (inst2, 0, 7) >> 1; | |
915 | ||
916 | /* First register to save. */ | |
917 | int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4); | |
918 | ||
919 | if (stack.store_would_trash (addr)) | |
920 | break; | |
921 | ||
922 | /* Calculate offsets of saved registers. */ | |
923 | for (; number > 0; number--) | |
924 | { | |
925 | addr = pv_add_constant (addr, -8); | |
926 | stack.store (addr, 8, pv_register (ARM_D0_REGNUM | |
927 | + vd + number, 0)); | |
928 | } | |
929 | ||
930 | /* Writeback SP to account for the saved registers. */ | |
931 | regs[bits (insn, 0, 3)] = addr; | |
932 | } | |
933 | ||
0963b4bd MS |
934 | else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, |
935 | [Rn, #+/-imm]{!} */ | |
ec3d575a UW |
936 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
937 | { | |
938 | int regno1 = bits (inst2, 12, 15); | |
939 | int regno2 = bits (inst2, 8, 11); | |
940 | pv_t addr = regs[bits (insn, 0, 3)]; | |
941 | ||
942 | offset = inst2 & 0xff; | |
943 | if (insn & 0x0080) | |
944 | addr = pv_add_constant (addr, offset); | |
945 | else | |
946 | addr = pv_add_constant (addr, -offset); | |
947 | ||
f7b7ed97 | 948 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
949 | break; |
950 | ||
f7b7ed97 TT |
951 | stack.store (addr, 4, regs[regno1]); |
952 | stack.store (pv_add_constant (addr, 4), | |
953 | 4, regs[regno2]); | |
ec3d575a UW |
954 | |
955 | if (insn & 0x0020) | |
956 | regs[bits (insn, 0, 3)] = addr; | |
957 | } | |
958 | ||
959 | else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */ | |
960 | && (inst2 & 0x0c00) == 0x0c00 | |
961 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
962 | { | |
963 | int regno = bits (inst2, 12, 15); | |
964 | pv_t addr = regs[bits (insn, 0, 3)]; | |
965 | ||
966 | offset = inst2 & 0xff; | |
967 | if (inst2 & 0x0200) | |
968 | addr = pv_add_constant (addr, offset); | |
969 | else | |
970 | addr = pv_add_constant (addr, -offset); | |
971 | ||
f7b7ed97 | 972 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
973 | break; |
974 | ||
f7b7ed97 | 975 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
976 | |
977 | if (inst2 & 0x0100) | |
978 | regs[bits (insn, 0, 3)] = addr; | |
979 | } | |
980 | ||
981 | else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */ | |
982 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
983 | { | |
984 | int regno = bits (inst2, 12, 15); | |
985 | pv_t addr; | |
986 | ||
987 | offset = inst2 & 0xfff; | |
988 | addr = pv_add_constant (regs[bits (insn, 0, 3)], offset); | |
989 | ||
f7b7ed97 | 990 | if (stack.store_would_trash (addr)) |
ec3d575a UW |
991 | break; |
992 | ||
f7b7ed97 | 993 | stack.store (addr, 4, regs[regno]); |
ec3d575a UW |
994 | } |
995 | ||
996 | else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */ | |
0d39a070 | 997 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 998 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 999 | ; |
ec3d575a UW |
1000 | |
1001 | else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */ | |
1002 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1003 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1004 | /* Ignore stores of argument registers to the stack. */ |
0d39a070 | 1005 | ; |
ec3d575a | 1006 | |
0963b4bd MS |
1007 | else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], |
1008 | { registers } */ | |
ec3d575a UW |
1009 | && (inst2 & 0x8000) == 0x0000 |
1010 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) | |
1011 | /* Ignore block loads from the stack, potentially copying | |
1012 | parameters from memory. */ | |
0d39a070 | 1013 | ; |
ec3d575a | 1014 | |
f8c6d152 | 1015 | else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, |
0963b4bd | 1016 | [Rn, #+/-imm] */ |
0d39a070 | 1017 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1018 | /* Similarly ignore dual loads from the stack. */ |
0d39a070 | 1019 | ; |
ec3d575a UW |
1020 | |
1021 | else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */ | |
1022 | && (inst2 & 0x0d00) == 0x0c00 | |
0d39a070 | 1023 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1024 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1025 | ; |
ec3d575a UW |
1026 | |
1027 | else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */ | |
0d39a070 | 1028 | && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |
ec3d575a | 1029 | /* Similarly ignore single loads from the stack. */ |
0d39a070 | 1030 | ; |
ec3d575a UW |
1031 | |
1032 | else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ | |
1033 | && (inst2 & 0x8000) == 0x0000) | |
1034 | { | |
1035 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1036 | | (bits (inst2, 12, 14) << 8) | |
1037 | | bits (inst2, 0, 7)); | |
1038 | ||
1039 | regs[bits (inst2, 8, 11)] | |
1040 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1041 | thumb_expand_immediate (imm)); | |
1042 | } | |
1043 | ||
1044 | else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */ | |
1045 | && (inst2 & 0x8000) == 0x0000) | |
0d39a070 | 1046 | { |
ec3d575a UW |
1047 | unsigned int imm = ((bits (insn, 10, 10) << 11) |
1048 | | (bits (inst2, 12, 14) << 8) | |
1049 | | bits (inst2, 0, 7)); | |
1050 | ||
1051 | regs[bits (inst2, 8, 11)] | |
1052 | = pv_add_constant (regs[bits (insn, 0, 3)], imm); | |
1053 | } | |
1054 | ||
1055 | else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */ | |
1056 | && (inst2 & 0x8000) == 0x0000) | |
1057 | { | |
1058 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1059 | | (bits (inst2, 12, 14) << 8) | |
1060 | | bits (inst2, 0, 7)); | |
1061 | ||
1062 | regs[bits (inst2, 8, 11)] | |
1063 | = pv_add_constant (regs[bits (insn, 0, 3)], | |
1064 | - (CORE_ADDR) thumb_expand_immediate (imm)); | |
1065 | } | |
1066 | ||
1067 | else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */ | |
1068 | && (inst2 & 0x8000) == 0x0000) | |
1069 | { | |
1070 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1071 | | (bits (inst2, 12, 14) << 8) | |
1072 | | bits (inst2, 0, 7)); | |
1073 | ||
1074 | regs[bits (inst2, 8, 11)] | |
1075 | = pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm); | |
1076 | } | |
1077 | ||
1078 | else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */ | |
1079 | { | |
1080 | unsigned int imm = ((bits (insn, 10, 10) << 11) | |
1081 | | (bits (inst2, 12, 14) << 8) | |
1082 | | bits (inst2, 0, 7)); | |
1083 | ||
1084 | regs[bits (inst2, 8, 11)] | |
1085 | = pv_constant (thumb_expand_immediate (imm)); | |
1086 | } | |
1087 | ||
1088 | else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1089 | { | |
621c6d5b YQ |
1090 | unsigned int imm |
1091 | = EXTRACT_MOVW_MOVT_IMM_T (insn, inst2); | |
ec3d575a UW |
1092 | |
1093 | regs[bits (inst2, 8, 11)] = pv_constant (imm); | |
1094 | } | |
1095 | ||
1096 | else if (insn == 0xea5f /* mov.w Rd,Rm */ | |
1097 | && (inst2 & 0xf0f0) == 0) | |
1098 | { | |
1099 | int dst_reg = (inst2 & 0x0f00) >> 8; | |
1100 | int src_reg = inst2 & 0xf; | |
1101 | regs[dst_reg] = regs[src_reg]; | |
1102 | } | |
1103 | ||
1104 | else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */ | |
1105 | { | |
1106 | /* Constant pool loads. */ | |
1107 | unsigned int constant; | |
1108 | CORE_ADDR loc; | |
1109 | ||
cac395ea | 1110 | offset = bits (inst2, 0, 11); |
ec3d575a UW |
1111 | if (insn & 0x0080) |
1112 | loc = start + 4 + offset; | |
1113 | else | |
1114 | loc = start + 4 - offset; | |
1115 | ||
1116 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1117 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1118 | } | |
1119 | ||
1120 | else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */ | |
1121 | { | |
1122 | /* Constant pool loads. */ | |
1123 | unsigned int constant; | |
1124 | CORE_ADDR loc; | |
1125 | ||
cac395ea | 1126 | offset = bits (inst2, 0, 7) << 2; |
ec3d575a UW |
1127 | if (insn & 0x0080) |
1128 | loc = start + 4 + offset; | |
1129 | else | |
1130 | loc = start + 4 - offset; | |
1131 | ||
1132 | constant = read_memory_unsigned_integer (loc, 4, byte_order); | |
1133 | regs[bits (inst2, 12, 15)] = pv_constant (constant); | |
1134 | ||
1135 | constant = read_memory_unsigned_integer (loc + 4, 4, byte_order); | |
1136 | regs[bits (inst2, 8, 11)] = pv_constant (constant); | |
1137 | } | |
a01567f4 LM |
1138 | /* Start of ARMv8.1-m PACBTI extension instructions. */ |
1139 | else if (IS_PAC (whole_insn)) | |
1140 | { | |
1141 | /* LR and SP are input registers. PAC is in R12. LR is | |
1142 | signed from this point onwards. NOP space. */ | |
1143 | ra_signed_state = true; | |
1144 | } | |
1145 | else if (IS_PACBTI (whole_insn)) | |
1146 | { | |
1147 | /* LR and SP are input registers. PAC is in R12 and PC is a | |
1148 | valid BTI landing pad. LR is signed from this point onwards. | |
1149 | NOP space. */ | |
1150 | ra_signed_state = true; | |
1151 | } | |
1152 | else if (IS_BTI (whole_insn)) | |
1153 | { | |
1154 | /* Valid BTI landing pad. NOP space. */ | |
1155 | } | |
1156 | else if (IS_PACG (whole_insn)) | |
1157 | { | |
1158 | /* Sign Rn using Rm and store the PAC in Rd. Rd is signed from | |
1159 | this point onwards. */ | |
1160 | ra_signed_state = true; | |
1161 | } | |
1162 | else if (IS_AUT (whole_insn) || IS_AUTG (whole_insn)) | |
1163 | { | |
1164 | /* These instructions appear close to the epilogue, when signed | |
1165 | pointers are getting authenticated. */ | |
1166 | ra_signed_state = false; | |
1167 | } | |
1168 | /* End of ARMv8.1-m PACBTI extension instructions */ | |
ec3d575a UW |
1169 | else if (thumb2_instruction_changes_pc (insn, inst2)) |
1170 | { | |
1171 | /* Don't scan past anything that might change control flow. */ | |
0d39a070 DJ |
1172 | break; |
1173 | } | |
ec3d575a UW |
1174 | else |
1175 | { | |
1176 | /* The optimizer might shove anything into the prologue, | |
1177 | so we just skip what we don't recognize. */ | |
1178 | unrecognized_pc = start; | |
1179 | } | |
0d39a070 | 1180 | |
a01567f4 LM |
1181 | arm_gdbarch_tdep *tdep |
1182 | = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); | |
1183 | ||
1184 | /* Make sure we are dealing with a target that supports ARMv8.1-m | |
1185 | PACBTI. */ | |
1186 | if (cache != nullptr && tdep->have_pacbti | |
1187 | && ra_signed_state.has_value ()) | |
1188 | { | |
1189 | arm_debug_printf ("Found pacbti instruction at %s", | |
1190 | paddress (gdbarch, start)); | |
1191 | arm_debug_printf ("RA is %s", | |
1192 | *ra_signed_state? "signed" : "not signed"); | |
1193 | cache->ra_signed_state = ra_signed_state; | |
1194 | } | |
1195 | ||
0d39a070 DJ |
1196 | start += 2; |
1197 | } | |
ec3d575a | 1198 | else if (thumb_instruction_changes_pc (insn)) |
3d74b771 | 1199 | { |
ec3d575a | 1200 | /* Don't scan past anything that might change control flow. */ |
da3c6d4a | 1201 | break; |
3d74b771 | 1202 | } |
ec3d575a UW |
1203 | else |
1204 | { | |
1205 | /* The optimizer might shove anything into the prologue, | |
1206 | so we just skip what we don't recognize. */ | |
1207 | unrecognized_pc = start; | |
1208 | } | |
29d73ae4 DJ |
1209 | |
1210 | start += 2; | |
c906108c SS |
1211 | } |
1212 | ||
7cb6d92a SM |
1213 | arm_debug_printf ("Prologue scan stopped at %s", |
1214 | paddress (gdbarch, start)); | |
0d39a070 | 1215 | |
ec3d575a UW |
1216 | if (unrecognized_pc == 0) |
1217 | unrecognized_pc = start; | |
1218 | ||
29d73ae4 | 1219 | if (cache == NULL) |
f7b7ed97 | 1220 | return unrecognized_pc; |
29d73ae4 | 1221 | |
29d73ae4 DJ |
1222 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
1223 | { | |
1224 | /* Frame pointer is fp. Frame size is constant. */ | |
1225 | cache->framereg = ARM_FP_REGNUM; | |
1226 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
1227 | } | |
1228 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
1229 | { | |
1230 | /* Frame pointer is r7. Frame size is constant. */ | |
1231 | cache->framereg = THUMB_FP_REGNUM; | |
1232 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
1233 | } | |
72a2e3dc | 1234 | else |
29d73ae4 DJ |
1235 | { |
1236 | /* Try the stack pointer... this is a bit desperate. */ | |
1237 | cache->framereg = ARM_SP_REGNUM; | |
1238 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
1239 | } | |
29d73ae4 DJ |
1240 | |
1241 | for (i = 0; i < 16; i++) | |
f7b7ed97 | 1242 | if (stack.find_reg (gdbarch, i, &offset)) |
098caef4 | 1243 | cache->saved_regs[i].set_addr (offset); |
29d73ae4 | 1244 | |
ec3d575a | 1245 | return unrecognized_pc; |
c906108c SS |
1246 | } |
1247 | ||
621c6d5b YQ |
1248 | |
1249 | /* Try to analyze the instructions starting from PC, which load symbol | |
1250 | __stack_chk_guard. Return the address of instruction after loading this | |
1251 | symbol, set the dest register number to *BASEREG, and set the size of | |
1252 | instructions for loading symbol in OFFSET. Return 0 if instructions are | |
1253 | not recognized. */ | |
1254 | ||
1255 | static CORE_ADDR | |
1256 | arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, | |
1257 | unsigned int *destreg, int *offset) | |
1258 | { | |
1259 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
1260 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1261 | unsigned int low, high, address; | |
1262 | ||
1263 | address = 0; | |
1264 | if (is_thumb) | |
1265 | { | |
1266 | unsigned short insn1 | |
198cd59d | 1267 | = read_code_unsigned_integer (pc, 2, byte_order_for_code); |
621c6d5b YQ |
1268 | |
1269 | if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ | |
1270 | { | |
1271 | *destreg = bits (insn1, 8, 10); | |
1272 | *offset = 2; | |
6ae274b7 YQ |
1273 | address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); |
1274 | address = read_memory_unsigned_integer (address, 4, | |
1275 | byte_order_for_code); | |
621c6d5b YQ |
1276 | } |
1277 | else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ | |
1278 | { | |
1279 | unsigned short insn2 | |
198cd59d | 1280 | = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); |
621c6d5b YQ |
1281 | |
1282 | low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1283 | ||
1284 | insn1 | |
198cd59d | 1285 | = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); |
621c6d5b | 1286 | insn2 |
198cd59d | 1287 | = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); |
621c6d5b YQ |
1288 | |
1289 | /* movt Rd, #const */ | |
1290 | if ((insn1 & 0xfbc0) == 0xf2c0) | |
1291 | { | |
1292 | high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); | |
1293 | *destreg = bits (insn2, 8, 11); | |
1294 | *offset = 8; | |
1295 | address = (high << 16 | low); | |
1296 | } | |
1297 | } | |
1298 | } | |
1299 | else | |
1300 | { | |
2e9e421f | 1301 | unsigned int insn |
198cd59d | 1302 | = read_code_unsigned_integer (pc, 4, byte_order_for_code); |
2e9e421f | 1303 | |
6ae274b7 | 1304 | if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ |
2e9e421f | 1305 | { |
6ae274b7 YQ |
1306 | address = bits (insn, 0, 11) + pc + 8; |
1307 | address = read_memory_unsigned_integer (address, 4, | |
1308 | byte_order_for_code); | |
1309 | ||
2e9e421f UW |
1310 | *destreg = bits (insn, 12, 15); |
1311 | *offset = 4; | |
1312 | } | |
1313 | else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */ | |
1314 | { | |
1315 | low = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1316 | ||
1317 | insn | |
198cd59d | 1318 | = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); |
2e9e421f UW |
1319 | |
1320 | if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ | |
1321 | { | |
1322 | high = EXTRACT_MOVW_MOVT_IMM_A (insn); | |
1323 | *destreg = bits (insn, 12, 15); | |
1324 | *offset = 8; | |
1325 | address = (high << 16 | low); | |
1326 | } | |
1327 | } | |
621c6d5b YQ |
1328 | } |
1329 | ||
1330 | return address; | |
1331 | } | |
1332 | ||
1333 | /* Try to skip a sequence of instructions used for stack protector. If PC | |
0963b4bd MS |
1334 | points to the first instruction of this sequence, return the address of |
1335 | first instruction after this sequence, otherwise, return original PC. | |
621c6d5b YQ |
1336 | |
1337 | On arm, this sequence of instructions is composed of mainly three steps, | |
1338 | Step 1: load symbol __stack_chk_guard, | |
1339 | Step 2: load from address of __stack_chk_guard, | |
1340 | Step 3: store it to somewhere else. | |
1341 | ||
1342 | Usually, instructions on step 2 and step 3 are the same on various ARM | |
1343 | architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and | |
1344 | on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However, | |
1345 | instructions in step 1 vary from different ARM architectures. On ARMv7, | |
1346 | they are, | |
1347 | ||
1348 | movw Rn, #:lower16:__stack_chk_guard | |
1349 | movt Rn, #:upper16:__stack_chk_guard | |
1350 | ||
1351 | On ARMv5t, it is, | |
1352 | ||
1353 | ldr Rn, .Label | |
1354 | .... | |
1355 | .Lable: | |
1356 | .word __stack_chk_guard | |
1357 | ||
1358 | Since ldr/str is a very popular instruction, we can't use them as | |
1359 | 'fingerprint' or 'signature' of stack protector sequence. Here we choose | |
1360 | sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not | |
1361 | stripped, as the 'fingerprint' of a stack protector cdoe sequence. */ | |
1362 | ||
1363 | static CORE_ADDR | |
1364 | arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) | |
1365 | { | |
1366 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
22e048c9 | 1367 | unsigned int basereg; |
7cbd4a93 | 1368 | struct bound_minimal_symbol stack_chk_guard; |
621c6d5b YQ |
1369 | int offset; |
1370 | int is_thumb = arm_pc_is_thumb (gdbarch, pc); | |
1371 | CORE_ADDR addr; | |
1372 | ||
1373 | /* Try to parse the instructions in Step 1. */ | |
1374 | addr = arm_analyze_load_stack_chk_guard (pc, gdbarch, | |
1375 | &basereg, &offset); | |
1376 | if (!addr) | |
1377 | return pc; | |
1378 | ||
1379 | stack_chk_guard = lookup_minimal_symbol_by_pc (addr); | |
6041179a JB |
1380 | /* ADDR must correspond to a symbol whose name is __stack_chk_guard. |
1381 | Otherwise, this sequence cannot be for stack protector. */ | |
1382 | if (stack_chk_guard.minsym == NULL | |
c9d95fa3 | 1383 | || !startswith (stack_chk_guard.minsym->linkage_name (), "__stack_chk_guard")) |
621c6d5b YQ |
1384 | return pc; |
1385 | ||
1386 | if (is_thumb) | |
1387 | { | |
1388 | unsigned int destreg; | |
1389 | unsigned short insn | |
198cd59d | 1390 | = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); |
621c6d5b YQ |
1391 | |
1392 | /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ | |
1393 | if ((insn & 0xf800) != 0x6800) | |
1394 | return pc; | |
1395 | if (bits (insn, 3, 5) != basereg) | |
1396 | return pc; | |
1397 | destreg = bits (insn, 0, 2); | |
1398 | ||
198cd59d YQ |
1399 | insn = read_code_unsigned_integer (pc + offset + 2, 2, |
1400 | byte_order_for_code); | |
621c6d5b YQ |
1401 | /* Step 3: str Rd, [Rn, #immed], encoding T1. */ |
1402 | if ((insn & 0xf800) != 0x6000) | |
1403 | return pc; | |
1404 | if (destreg != bits (insn, 0, 2)) | |
1405 | return pc; | |
1406 | } | |
1407 | else | |
1408 | { | |
1409 | unsigned int destreg; | |
1410 | unsigned int insn | |
198cd59d | 1411 | = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); |
621c6d5b YQ |
1412 | |
1413 | /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ | |
1414 | if ((insn & 0x0e500000) != 0x04100000) | |
1415 | return pc; | |
1416 | if (bits (insn, 16, 19) != basereg) | |
1417 | return pc; | |
1418 | destreg = bits (insn, 12, 15); | |
1419 | /* Step 3: str Rd, [Rn, #immed], encoding A1. */ | |
198cd59d | 1420 | insn = read_code_unsigned_integer (pc + offset + 4, |
621c6d5b YQ |
1421 | 4, byte_order_for_code); |
1422 | if ((insn & 0x0e500000) != 0x04000000) | |
1423 | return pc; | |
1424 | if (bits (insn, 12, 15) != destreg) | |
1425 | return pc; | |
1426 | } | |
1427 | /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8 | |
1428 | on arm. */ | |
1429 | if (is_thumb) | |
1430 | return pc + offset + 4; | |
1431 | else | |
1432 | return pc + offset + 8; | |
1433 | } | |
1434 | ||
da3c6d4a MS |
1435 | /* Advance the PC across any function entry prologue instructions to |
1436 | reach some "real" code. | |
34e8f22d RE |
1437 | |
1438 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 1439 | prologue: |
c906108c | 1440 | |
c5aa993b JM |
1441 | mov ip, sp |
1442 | [stmfd sp!, {a1,a2,a3,a4}] | |
1443 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
1444 | [stfe f7, [sp, #-12]!] |
1445 | [stfe f6, [sp, #-12]!] | |
1446 | [stfe f5, [sp, #-12]!] | |
1447 | [stfe f4, [sp, #-12]!] | |
0963b4bd | 1448 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */ |
c906108c | 1449 | |
34e8f22d | 1450 | static CORE_ADDR |
6093d2eb | 1451 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1452 | { |
a89fea3c | 1453 | CORE_ADDR func_addr, limit_pc; |
c906108c | 1454 | |
a89fea3c JL |
1455 | /* See if we can determine the end of the prologue via the symbol table. |
1456 | If so, then return either PC, or the PC after the prologue, whichever | |
1457 | is greater. */ | |
1458 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
c906108c | 1459 | { |
d80b854b UW |
1460 | CORE_ADDR post_prologue_pc |
1461 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1462 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
0d39a070 | 1463 | |
621c6d5b YQ |
1464 | if (post_prologue_pc) |
1465 | post_prologue_pc | |
1466 | = arm_skip_stack_protector (post_prologue_pc, gdbarch); | |
1467 | ||
1468 | ||
0d39a070 DJ |
1469 | /* GCC always emits a line note before the prologue and another |
1470 | one after, even if the two are at the same address or on the | |
1471 | same line. Take advantage of this so that we do not need to | |
1472 | know every instruction that might appear in the prologue. We | |
1473 | will have producer information for most binaries; if it is | |
1474 | missing (e.g. for -gstabs), assuming the GNU tools. */ | |
1475 | if (post_prologue_pc | |
43f3e411 | 1476 | && (cust == NULL |
ab5f850e SM |
1477 | || cust->producer () == NULL |
1478 | || startswith (cust->producer (), "GNU ") | |
1479 | || producer_is_llvm (cust->producer ()))) | |
0d39a070 DJ |
1480 | return post_prologue_pc; |
1481 | ||
a89fea3c | 1482 | if (post_prologue_pc != 0) |
0d39a070 DJ |
1483 | { |
1484 | CORE_ADDR analyzed_limit; | |
1485 | ||
1486 | /* For non-GCC compilers, make sure the entire line is an | |
1487 | acceptable prologue; GDB will round this function's | |
1488 | return value up to the end of the following line so we | |
1489 | can not skip just part of a line (and we do not want to). | |
1490 | ||
1491 | RealView does not treat the prologue specially, but does | |
1492 | associate prologue code with the opening brace; so this | |
1493 | lets us skip the first line if we think it is the opening | |
1494 | brace. */ | |
9779414d | 1495 | if (arm_pc_is_thumb (gdbarch, func_addr)) |
0d39a070 DJ |
1496 | analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, |
1497 | post_prologue_pc, NULL); | |
1498 | else | |
9ecab40c SM |
1499 | analyzed_limit |
1500 | = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, | |
1501 | NULL, target_arm_instruction_reader ()); | |
0d39a070 DJ |
1502 | |
1503 | if (analyzed_limit != post_prologue_pc) | |
1504 | return func_addr; | |
1505 | ||
1506 | return post_prologue_pc; | |
1507 | } | |
c906108c SS |
1508 | } |
1509 | ||
a89fea3c JL |
1510 | /* Can't determine prologue from the symbol table, need to examine |
1511 | instructions. */ | |
c906108c | 1512 | |
a89fea3c JL |
1513 | /* Find an upper limit on the function prologue using the debug |
1514 | information. If the debug information could not be used to provide | |
1515 | that bound, then use an arbitrary large number as the upper bound. */ | |
0963b4bd | 1516 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
d80b854b | 1517 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
a89fea3c JL |
1518 | if (limit_pc == 0) |
1519 | limit_pc = pc + 64; /* Magic. */ | |
1520 | ||
c906108c | 1521 | |
29d73ae4 | 1522 | /* Check if this is Thumb code. */ |
9779414d | 1523 | if (arm_pc_is_thumb (gdbarch, pc)) |
a89fea3c | 1524 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
21daaaaf | 1525 | else |
9ecab40c SM |
1526 | return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL, |
1527 | target_arm_instruction_reader ()); | |
c906108c | 1528 | } |
94c30b78 | 1529 | |
c5aa993b | 1530 | /* *INDENT-OFF* */ |
c906108c SS |
1531 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
1532 | This function decodes a Thumb function prologue to determine: | |
1533 | 1) the size of the stack frame | |
1534 | 2) which registers are saved on it | |
1535 | 3) the offsets of saved regs | |
1536 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 1537 | |
da59e081 JM |
1538 | A typical Thumb function prologue would create this stack frame |
1539 | (offsets relative to FP) | |
c906108c SS |
1540 | old SP -> 24 stack parameters |
1541 | 20 LR | |
1542 | 16 R7 | |
1543 | R7 -> 0 local variables (16 bytes) | |
1544 | SP -> -12 additional stack space (12 bytes) | |
1545 | The frame size would thus be 36 bytes, and the frame offset would be | |
0963b4bd | 1546 | 12 bytes. The frame register is R7. |
da59e081 | 1547 | |
da3c6d4a MS |
1548 | The comments for thumb_skip_prolog() describe the algorithm we use |
1549 | to detect the end of the prolog. */ | |
c5aa993b JM |
1550 | /* *INDENT-ON* */ |
1551 | ||
c906108c | 1552 | static void |
be8626e0 | 1553 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 1554 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
1555 | { |
1556 | CORE_ADDR prologue_start; | |
1557 | CORE_ADDR prologue_end; | |
c906108c | 1558 | |
b39cc962 DJ |
1559 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
1560 | &prologue_end)) | |
c906108c | 1561 | { |
ec3d575a UW |
1562 | /* See comment in arm_scan_prologue for an explanation of |
1563 | this heuristics. */ | |
1564 | if (prologue_end > prologue_start + 64) | |
1565 | { | |
1566 | prologue_end = prologue_start + 64; | |
1567 | } | |
c906108c SS |
1568 | } |
1569 | else | |
f7060f85 DJ |
1570 | /* We're in the boondocks: we have no idea where the start of the |
1571 | function is. */ | |
1572 | return; | |
c906108c | 1573 | |
325fac50 | 1574 | prologue_end = std::min (prologue_end, prev_pc); |
c906108c | 1575 | |
be8626e0 | 1576 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
1577 | } |
1578 | ||
f303bc3e YQ |
1579 | /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 |
1580 | otherwise. */ | |
1581 | ||
1582 | static int | |
1583 | arm_instruction_restores_sp (unsigned int insn) | |
1584 | { | |
1585 | if (bits (insn, 28, 31) != INST_NV) | |
1586 | { | |
1587 | if ((insn & 0x0df0f000) == 0x0080d000 | |
1588 | /* ADD SP (register or immediate). */ | |
1589 | || (insn & 0x0df0f000) == 0x0040d000 | |
1590 | /* SUB SP (register or immediate). */ | |
1591 | || (insn & 0x0ffffff0) == 0x01a0d000 | |
1592 | /* MOV SP. */ | |
1593 | || (insn & 0x0fff0000) == 0x08bd0000 | |
1594 | /* POP (LDMIA). */ | |
1595 | || (insn & 0x0fff0000) == 0x049d0000) | |
1596 | /* POP of a single register. */ | |
1597 | return 1; | |
1598 | } | |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
9ecab40c SM |
1603 | /* Implement immediate value decoding, as described in section A5.2.4 |
1604 | (Modified immediate constants in ARM instructions) of the ARM Architecture | |
1605 | Reference Manual (ARMv7-A and ARMv7-R edition). */ | |
1606 | ||
1607 | static uint32_t | |
1608 | arm_expand_immediate (uint32_t imm) | |
1609 | { | |
1610 | /* Immediate values are 12 bits long. */ | |
1611 | gdb_assert ((imm & 0xfffff000) == 0); | |
1612 | ||
1613 | uint32_t unrotated_value = imm & 0xff; | |
1614 | uint32_t rotate_amount = (imm & 0xf00) >> 7; | |
1615 | ||
1616 | if (rotate_amount == 0) | |
1617 | return unrotated_value; | |
1618 | ||
1619 | return ((unrotated_value >> rotate_amount) | |
1620 | | (unrotated_value << (32 - rotate_amount))); | |
1621 | } | |
1622 | ||
0d39a070 DJ |
1623 | /* Analyze an ARM mode prologue starting at PROLOGUE_START and |
1624 | continuing no further than PROLOGUE_END. If CACHE is non-NULL, | |
1625 | fill it in. Return the first address not recognized as a prologue | |
1626 | instruction. | |
eb5492fa | 1627 | |
0d39a070 DJ |
1628 | We recognize all the instructions typically found in ARM prologues, |
1629 | plus harmless instructions which can be skipped (either for analysis | |
1630 | purposes, or a more restrictive set that can be skipped when finding | |
1631 | the end of the prologue). */ | |
1632 | ||
1633 | static CORE_ADDR | |
1634 | arm_analyze_prologue (struct gdbarch *gdbarch, | |
1635 | CORE_ADDR prologue_start, CORE_ADDR prologue_end, | |
9ecab40c SM |
1636 | struct arm_prologue_cache *cache, |
1637 | const arm_instruction_reader &insn_reader) | |
0d39a070 | 1638 | { |
0d39a070 DJ |
1639 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
1640 | int regno; | |
1641 | CORE_ADDR offset, current_pc; | |
1642 | pv_t regs[ARM_FPS_REGNUM]; | |
0d39a070 | 1643 | CORE_ADDR unrecognized_pc = 0; |
345bd07c | 1644 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
0d39a070 DJ |
1645 | |
1646 | /* Search the prologue looking for instructions that set up the | |
96baa820 | 1647 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 1648 | |
96baa820 JM |
1649 | Be careful, however, and if it doesn't look like a prologue, |
1650 | don't try to scan it. If, for instance, a frameless function | |
1651 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 1652 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 | 1653 | and other operations that rely on a knowledge of the stack |
0d39a070 | 1654 | traceback. */ |
d4473757 | 1655 | |
4be43953 DJ |
1656 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
1657 | regs[regno] = pv_register (regno, 0); | |
f7b7ed97 | 1658 | pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
4be43953 | 1659 | |
94c30b78 MS |
1660 | for (current_pc = prologue_start; |
1661 | current_pc < prologue_end; | |
f43845b3 | 1662 | current_pc += 4) |
96baa820 | 1663 | { |
9ecab40c | 1664 | uint32_t insn = insn_reader.read (current_pc, byte_order_for_code); |
9d4fde75 | 1665 | |
94c30b78 | 1666 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 1667 | { |
4be43953 | 1668 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
1669 | continue; |
1670 | } | |
0d39a070 DJ |
1671 | else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ |
1672 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1673 | { |
9ecab40c | 1674 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1675 | int rd = bits (insn, 12, 15); |
0d39a070 | 1676 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); |
28cd8767 JG |
1677 | continue; |
1678 | } | |
0d39a070 DJ |
1679 | else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ |
1680 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
28cd8767 | 1681 | { |
9ecab40c | 1682 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
0d39a070 | 1683 | int rd = bits (insn, 12, 15); |
0d39a070 | 1684 | regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); |
f43845b3 MS |
1685 | continue; |
1686 | } | |
0963b4bd MS |
1687 | else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, |
1688 | [sp, #-4]! */ | |
f43845b3 | 1689 | { |
f7b7ed97 | 1690 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1691 | break; |
1692 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 TT |
1693 | stack.store (regs[ARM_SP_REGNUM], 4, |
1694 | regs[bits (insn, 12, 15)]); | |
f43845b3 MS |
1695 | continue; |
1696 | } | |
1697 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
1698 | /* stmfd sp!, {..., fp, ip, lr, pc} |
1699 | or | |
1700 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 1701 | { |
d4473757 | 1702 | int mask = insn & 0xffff; |
ed9a39eb | 1703 | |
f7b7ed97 | 1704 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1705 | break; |
1706 | ||
94c30b78 | 1707 | /* Calculate offsets of saved registers. */ |
34e8f22d | 1708 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
1709 | if (mask & (1 << regno)) |
1710 | { | |
0963b4bd MS |
1711 | regs[ARM_SP_REGNUM] |
1712 | = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
f7b7ed97 | 1713 | stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]); |
d4473757 KB |
1714 | } |
1715 | } | |
0d39a070 DJ |
1716 | else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
1717 | || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ | |
f8bf5763 | 1718 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
b8d5e71d MS |
1719 | { |
1720 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1721 | continue; | |
1722 | } | |
0d39a070 DJ |
1723 | else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
1724 | || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ | |
f8bf5763 | 1725 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
f43845b3 MS |
1726 | { |
1727 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
1728 | continue; | |
1729 | } | |
0963b4bd MS |
1730 | else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, |
1731 | { registers } */ | |
0d39a070 DJ |
1732 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) |
1733 | { | |
1734 | /* No need to add this to saved_regs -- it's just arg regs. */ | |
1735 | continue; | |
1736 | } | |
d4473757 KB |
1737 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
1738 | { | |
9ecab40c | 1739 | uint32_t imm = arm_expand_immediate (insn & 0xfff); |
4be43953 | 1740 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
1741 | } |
1742 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
1743 | { | |
9ecab40c | 1744 | uint32_t imm = arm_expand_immediate(insn & 0xfff); |
4be43953 | 1745 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 1746 | } |
0963b4bd MS |
1747 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, |
1748 | [sp, -#c]! */ | |
345bd07c | 1749 | && tdep->have_fpa_registers) |
d4473757 | 1750 | { |
f7b7ed97 | 1751 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1752 | break; |
1753 | ||
1754 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 1755 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
f7b7ed97 | 1756 | stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 1757 | } |
0963b4bd MS |
1758 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, |
1759 | [sp!] */ | |
345bd07c | 1760 | && tdep->have_fpa_registers) |
d4473757 KB |
1761 | { |
1762 | int n_saved_fp_regs; | |
1763 | unsigned int fp_start_reg, fp_bound_reg; | |
1764 | ||
f7b7ed97 | 1765 | if (stack.store_would_trash (regs[ARM_SP_REGNUM])) |
4be43953 DJ |
1766 | break; |
1767 | ||
94c30b78 | 1768 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 1769 | { |
d4473757 KB |
1770 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1771 | n_saved_fp_regs = 3; | |
1772 | else | |
1773 | n_saved_fp_regs = 1; | |
96baa820 | 1774 | } |
d4473757 | 1775 | else |
96baa820 | 1776 | { |
d4473757 KB |
1777 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
1778 | n_saved_fp_regs = 2; | |
1779 | else | |
1780 | n_saved_fp_regs = 4; | |
96baa820 | 1781 | } |
d4473757 | 1782 | |
34e8f22d | 1783 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
1784 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
1785 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 1786 | { |
4be43953 | 1787 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
f7b7ed97 TT |
1788 | stack.store (regs[ARM_SP_REGNUM], 12, |
1789 | regs[fp_start_reg++]); | |
96baa820 | 1790 | } |
c906108c | 1791 | } |
0d39a070 DJ |
1792 | else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ |
1793 | { | |
1794 | /* Allow some special function calls when skipping the | |
1795 | prologue; GCC generates these before storing arguments to | |
1796 | the stack. */ | |
1797 | CORE_ADDR dest = BranchDest (current_pc, insn); | |
1798 | ||
e0634ccf | 1799 | if (skip_prologue_function (gdbarch, dest, 0)) |
0d39a070 DJ |
1800 | continue; |
1801 | else | |
1802 | break; | |
1803 | } | |
d4473757 | 1804 | else if ((insn & 0xf0000000) != 0xe0000000) |
0963b4bd | 1805 | break; /* Condition not true, exit early. */ |
0d39a070 DJ |
1806 | else if (arm_instruction_changes_pc (insn)) |
1807 | /* Don't scan past anything that might change control flow. */ | |
1808 | break; | |
f303bc3e YQ |
1809 | else if (arm_instruction_restores_sp (insn)) |
1810 | { | |
1811 | /* Don't scan past the epilogue. */ | |
1812 | break; | |
1813 | } | |
d19f7eee UW |
1814 | else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ |
1815 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1816 | /* Ignore block loads from the stack, potentially copying | |
1817 | parameters from memory. */ | |
1818 | continue; | |
1819 | else if ((insn & 0xfc500000) == 0xe4100000 | |
1820 | && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) | |
1821 | /* Similarly ignore single loads from the stack. */ | |
1822 | continue; | |
0d39a070 DJ |
1823 | else if ((insn & 0xffff0ff0) == 0xe1a00000) |
1824 | /* MOV Rd, Rm. Skip register copies, i.e. saves to another | |
1825 | register instead of the stack. */ | |
d4473757 | 1826 | continue; |
0d39a070 DJ |
1827 | else |
1828 | { | |
21daaaaf YQ |
1829 | /* The optimizer might shove anything into the prologue, if |
1830 | we build up cache (cache != NULL) from scanning prologue, | |
1831 | we just skip what we don't recognize and scan further to | |
1832 | make cache as complete as possible. However, if we skip | |
1833 | prologue, we'll stop immediately on unrecognized | |
1834 | instruction. */ | |
0d39a070 | 1835 | unrecognized_pc = current_pc; |
21daaaaf YQ |
1836 | if (cache != NULL) |
1837 | continue; | |
1838 | else | |
1839 | break; | |
0d39a070 | 1840 | } |
c906108c SS |
1841 | } |
1842 | ||
0d39a070 DJ |
1843 | if (unrecognized_pc == 0) |
1844 | unrecognized_pc = current_pc; | |
1845 | ||
0d39a070 DJ |
1846 | if (cache) |
1847 | { | |
4072f920 YQ |
1848 | int framereg, framesize; |
1849 | ||
1850 | /* The frame size is just the distance from the frame register | |
1851 | to the original stack pointer. */ | |
1852 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
1853 | { | |
1854 | /* Frame pointer is fp. */ | |
1855 | framereg = ARM_FP_REGNUM; | |
1856 | framesize = -regs[ARM_FP_REGNUM].k; | |
1857 | } | |
1858 | else | |
1859 | { | |
1860 | /* Try the stack pointer... this is a bit desperate. */ | |
1861 | framereg = ARM_SP_REGNUM; | |
1862 | framesize = -regs[ARM_SP_REGNUM].k; | |
1863 | } | |
1864 | ||
0d39a070 DJ |
1865 | cache->framereg = framereg; |
1866 | cache->framesize = framesize; | |
1867 | ||
1868 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
f7b7ed97 | 1869 | if (stack.find_reg (gdbarch, regno, &offset)) |
098caef4 | 1870 | cache->saved_regs[regno].set_addr (offset); |
0d39a070 DJ |
1871 | } |
1872 | ||
7cb6d92a SM |
1873 | arm_debug_printf ("Prologue scan stopped at %s", |
1874 | paddress (gdbarch, unrecognized_pc)); | |
4be43953 | 1875 | |
0d39a070 DJ |
1876 | return unrecognized_pc; |
1877 | } | |
1878 | ||
1879 | static void | |
1880 | arm_scan_prologue (struct frame_info *this_frame, | |
1881 | struct arm_prologue_cache *cache) | |
1882 | { | |
1883 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1884 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
bec2ab5a | 1885 | CORE_ADDR prologue_start, prologue_end; |
0d39a070 DJ |
1886 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
1887 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
345bd07c | 1888 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
0d39a070 DJ |
1889 | |
1890 | /* Assume there is no frame until proven otherwise. */ | |
1891 | cache->framereg = ARM_SP_REGNUM; | |
1892 | cache->framesize = 0; | |
1893 | ||
1894 | /* Check for Thumb prologue. */ | |
1895 | if (arm_frame_is_thumb (this_frame)) | |
1896 | { | |
1897 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); | |
1898 | return; | |
1899 | } | |
1900 | ||
1901 | /* Find the function prologue. If we can't find the function in | |
1902 | the symbol table, peek in the stack frame to find the PC. */ | |
1903 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
1904 | &prologue_end)) | |
1905 | { | |
1906 | /* One way to find the end of the prologue (which works well | |
dda83cd7 | 1907 | for unoptimized code) is to do the following: |
0d39a070 DJ |
1908 | |
1909 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
1910 | ||
1911 | if (sal.line == 0) | |
1912 | prologue_end = prev_pc; | |
1913 | else if (sal.end < prologue_end) | |
1914 | prologue_end = sal.end; | |
1915 | ||
1916 | This mechanism is very accurate so long as the optimizer | |
1917 | doesn't move any instructions from the function body into the | |
1918 | prologue. If this happens, sal.end will be the last | |
1919 | instruction in the first hunk of prologue code just before | |
1920 | the first instruction that the scheduler has moved from | |
1921 | the body to the prologue. | |
1922 | ||
1923 | In order to make sure that we scan all of the prologue | |
1924 | instructions, we use a slightly less accurate mechanism which | |
1925 | may scan more than necessary. To help compensate for this | |
1926 | lack of accuracy, the prologue scanning loop below contains | |
1927 | several clauses which'll cause the loop to terminate early if | |
1928 | an implausible prologue instruction is encountered. | |
1929 | ||
1930 | The expression | |
1931 | ||
1932 | prologue_start + 64 | |
1933 | ||
1934 | is a suitable endpoint since it accounts for the largest | |
1935 | possible prologue plus up to five instructions inserted by | |
1936 | the scheduler. */ | |
1937 | ||
1938 | if (prologue_end > prologue_start + 64) | |
1939 | { | |
1940 | prologue_end = prologue_start + 64; /* See above. */ | |
1941 | } | |
1942 | } | |
1943 | else | |
1944 | { | |
1945 | /* We have no symbol information. Our only option is to assume this | |
1946 | function has a standard stack frame and the normal frame register. | |
1947 | Then, we can find the value of our frame pointer on entrance to | |
1948 | the callee (or at the present moment if this is the innermost frame). | |
1949 | The value stored there should be the address of the stmfd + 8. */ | |
1950 | CORE_ADDR frame_loc; | |
7913a64c | 1951 | ULONGEST return_value; |
0d39a070 | 1952 | |
9e237747 | 1953 | /* AAPCS does not use a frame register, so we can abort here. */ |
345bd07c | 1954 | if (tdep->arm_abi == ARM_ABI_AAPCS) |
dda83cd7 | 1955 | return; |
9e237747 | 1956 | |
0d39a070 | 1957 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
7913a64c YQ |
1958 | if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, |
1959 | &return_value)) | |
dda83cd7 | 1960 | return; |
0d39a070 | 1961 | else |
dda83cd7 SM |
1962 | { |
1963 | prologue_start = gdbarch_addr_bits_remove | |
0d39a070 | 1964 | (gdbarch, return_value) - 8; |
dda83cd7 SM |
1965 | prologue_end = prologue_start + 64; /* See above. */ |
1966 | } | |
0d39a070 DJ |
1967 | } |
1968 | ||
1969 | if (prev_pc < prologue_end) | |
1970 | prologue_end = prev_pc; | |
1971 | ||
9ecab40c SM |
1972 | arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache, |
1973 | target_arm_instruction_reader ()); | |
c906108c SS |
1974 | } |
1975 | ||
eb5492fa | 1976 | static struct arm_prologue_cache * |
a262aec2 | 1977 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 1978 | { |
eb5492fa DJ |
1979 | int reg; |
1980 | struct arm_prologue_cache *cache; | |
1981 | CORE_ADDR unwound_fp; | |
c5aa993b | 1982 | |
35d5d4ee | 1983 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1984 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1985 | |
a262aec2 | 1986 | arm_scan_prologue (this_frame, cache); |
848cfffb | 1987 | |
a262aec2 | 1988 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
1989 | if (unwound_fp == 0) |
1990 | return cache; | |
c906108c | 1991 | |
4be43953 | 1992 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 1993 | |
eb5492fa DJ |
1994 | /* Calculate actual addresses of saved registers using offsets |
1995 | determined by arm_scan_prologue. */ | |
a262aec2 | 1996 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
a9a87d35 | 1997 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
1998 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
1999 | + cache->prev_sp); | |
eb5492fa DJ |
2000 | |
2001 | return cache; | |
c906108c SS |
2002 | } |
2003 | ||
c1ee9414 LM |
2004 | /* Implementation of the stop_reason hook for arm_prologue frames. */ |
2005 | ||
2006 | static enum unwind_stop_reason | |
2007 | arm_prologue_unwind_stop_reason (struct frame_info *this_frame, | |
2008 | void **this_cache) | |
2009 | { | |
2010 | struct arm_prologue_cache *cache; | |
2011 | CORE_ADDR pc; | |
2012 | ||
2013 | if (*this_cache == NULL) | |
2014 | *this_cache = arm_make_prologue_cache (this_frame); | |
9a3c8263 | 2015 | cache = (struct arm_prologue_cache *) *this_cache; |
c1ee9414 LM |
2016 | |
2017 | /* This is meant to halt the backtrace at "_start". */ | |
2018 | pc = get_frame_pc (this_frame); | |
345bd07c SM |
2019 | gdbarch *arch = get_frame_arch (this_frame); |
2020 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (arch); | |
2021 | if (pc <= tdep->lowest_pc) | |
c1ee9414 LM |
2022 | return UNWIND_OUTERMOST; |
2023 | ||
2024 | /* If we've hit a wall, stop. */ | |
2025 | if (cache->prev_sp == 0) | |
2026 | return UNWIND_OUTERMOST; | |
2027 | ||
2028 | return UNWIND_NO_REASON; | |
2029 | } | |
2030 | ||
eb5492fa DJ |
2031 | /* Our frame ID for a normal frame is the current function's starting PC |
2032 | and the caller's SP when we were called. */ | |
c906108c | 2033 | |
148754e5 | 2034 | static void |
a262aec2 | 2035 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
2036 | void **this_cache, |
2037 | struct frame_id *this_id) | |
c906108c | 2038 | { |
eb5492fa DJ |
2039 | struct arm_prologue_cache *cache; |
2040 | struct frame_id id; | |
2c404490 | 2041 | CORE_ADDR pc, func; |
f079148d | 2042 | |
eb5492fa | 2043 | if (*this_cache == NULL) |
a262aec2 | 2044 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2045 | cache = (struct arm_prologue_cache *) *this_cache; |
2a451106 | 2046 | |
0e9e9abd UW |
2047 | /* Use function start address as part of the frame ID. If we cannot |
2048 | identify the start address (due to missing symbol information), | |
2049 | fall back to just using the current PC. */ | |
c1ee9414 | 2050 | pc = get_frame_pc (this_frame); |
2c404490 | 2051 | func = get_frame_func (this_frame); |
0e9e9abd UW |
2052 | if (!func) |
2053 | func = pc; | |
2054 | ||
eb5492fa | 2055 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 2056 | *this_id = id; |
c906108c SS |
2057 | } |
2058 | ||
a262aec2 DJ |
2059 | static struct value * |
2060 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 2061 | void **this_cache, |
a262aec2 | 2062 | int prev_regnum) |
24de872b | 2063 | { |
24568a2c | 2064 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
24de872b DJ |
2065 | struct arm_prologue_cache *cache; |
2066 | ||
eb5492fa | 2067 | if (*this_cache == NULL) |
a262aec2 | 2068 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 2069 | cache = (struct arm_prologue_cache *) *this_cache; |
24de872b | 2070 | |
a01567f4 LM |
2071 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
2072 | ||
2073 | /* If this frame has signed the return address, mark it as so. */ | |
2074 | if (tdep->have_pacbti && cache->ra_signed_state.has_value () | |
2075 | && *cache->ra_signed_state) | |
2076 | set_frame_previous_pc_masked (this_frame); | |
2077 | ||
eb5492fa | 2078 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
2079 | instead. The prologue may save PC, but it will point into this |
2080 | frame's prologue, not the next frame's resume location. Also | |
2081 | strip the saved T bit. A valid LR may have the low bit set, but | |
2082 | a valid PC never does. */ | |
eb5492fa | 2083 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
2084 | { |
2085 | CORE_ADDR lr; | |
2086 | ||
2087 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2088 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
24568a2c | 2089 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 | 2090 | } |
24de872b | 2091 | |
eb5492fa | 2092 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 2093 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
2094 | The value was already reconstructed into PREV_SP. */ |
2095 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 2096 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 2097 | |
b39cc962 DJ |
2098 | /* The CPSR may have been changed by the call instruction and by the |
2099 | called function. The only bit we can reconstruct is the T bit, | |
2100 | by checking the low bit of LR as of the call. This is a reliable | |
2101 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
2102 | Thumb code, which could get away with a clear low bit as long as | |
2103 | the called function did not use bx. Guess that all other | |
2104 | bits are unchanged; the condition flags are presumably lost, | |
2105 | but the processor status is likely valid. */ | |
2106 | if (prev_regnum == ARM_PS_REGNUM) | |
2107 | { | |
2108 | CORE_ADDR lr, cpsr; | |
9779414d | 2109 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
2110 | |
2111 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
2112 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
2113 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 2114 | cpsr |= t_bit; |
b39cc962 | 2115 | else |
9779414d | 2116 | cpsr &= ~t_bit; |
b39cc962 DJ |
2117 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
2118 | } | |
2119 | ||
a262aec2 DJ |
2120 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
2121 | prev_regnum); | |
eb5492fa DJ |
2122 | } |
2123 | ||
6bd434d6 | 2124 | static frame_unwind arm_prologue_unwind = { |
a154d838 | 2125 | "arm prologue", |
eb5492fa | 2126 | NORMAL_FRAME, |
c1ee9414 | 2127 | arm_prologue_unwind_stop_reason, |
eb5492fa | 2128 | arm_prologue_this_id, |
a262aec2 DJ |
2129 | arm_prologue_prev_register, |
2130 | NULL, | |
2131 | default_frame_sniffer | |
eb5492fa DJ |
2132 | }; |
2133 | ||
0e9e9abd UW |
2134 | /* Maintain a list of ARM exception table entries per objfile, similar to the |
2135 | list of mapping symbols. We only cache entries for standard ARM-defined | |
2136 | personality routines; the cache will contain only the frame unwinding | |
2137 | instructions associated with the entry (not the descriptors). */ | |
2138 | ||
0e9e9abd UW |
2139 | struct arm_exidx_entry |
2140 | { | |
227031b2 | 2141 | CORE_ADDR addr; |
0e9e9abd | 2142 | gdb_byte *entry; |
7a5d944b TT |
2143 | |
2144 | bool operator< (const arm_exidx_entry &other) const | |
2145 | { | |
2146 | return addr < other.addr; | |
2147 | } | |
0e9e9abd | 2148 | }; |
0e9e9abd UW |
2149 | |
2150 | struct arm_exidx_data | |
2151 | { | |
7a5d944b | 2152 | std::vector<std::vector<arm_exidx_entry>> section_maps; |
0e9e9abd UW |
2153 | }; |
2154 | ||
a2726d4f LM |
2155 | /* Per-BFD key to store exception handling information. */ |
2156 | static const struct bfd_key<arm_exidx_data> arm_exidx_data_key; | |
0e9e9abd UW |
2157 | |
2158 | static struct obj_section * | |
2159 | arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma) | |
2160 | { | |
2161 | struct obj_section *osect; | |
2162 | ||
2163 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
fd361982 | 2164 | if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC) |
0e9e9abd UW |
2165 | { |
2166 | bfd_vma start, size; | |
fd361982 AM |
2167 | start = bfd_section_vma (osect->the_bfd_section); |
2168 | size = bfd_section_size (osect->the_bfd_section); | |
0e9e9abd UW |
2169 | |
2170 | if (start <= vma && vma < start + size) | |
2171 | return osect; | |
2172 | } | |
2173 | ||
2174 | return NULL; | |
2175 | } | |
2176 | ||
2177 | /* Parse contents of exception table and exception index sections | |
2178 | of OBJFILE, and fill in the exception table entry cache. | |
2179 | ||
2180 | For each entry that refers to a standard ARM-defined personality | |
2181 | routine, extract the frame unwinding instructions (from either | |
2182 | the index or the table section). The unwinding instructions | |
2183 | are normalized by: | |
2184 | - extracting them from the rest of the table data | |
2185 | - converting to host endianness | |
2186 | - appending the implicit 0xb0 ("Finish") code | |
2187 | ||
2188 | The extracted and normalized instructions are stored for later | |
2189 | retrieval by the arm_find_exidx_entry routine. */ | |
2190 | ||
2191 | static void | |
2192 | arm_exidx_new_objfile (struct objfile *objfile) | |
2193 | { | |
0e9e9abd UW |
2194 | struct arm_exidx_data *data; |
2195 | asection *exidx, *extab; | |
2196 | bfd_vma exidx_vma = 0, extab_vma = 0; | |
0e9e9abd UW |
2197 | LONGEST i; |
2198 | ||
2199 | /* If we've already touched this file, do nothing. */ | |
a2726d4f | 2200 | if (!objfile || arm_exidx_data_key.get (objfile->obfd) != NULL) |
0e9e9abd UW |
2201 | return; |
2202 | ||
2203 | /* Read contents of exception table and index. */ | |
a5eda10c | 2204 | exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); |
984c7238 | 2205 | gdb::byte_vector exidx_data; |
0e9e9abd UW |
2206 | if (exidx) |
2207 | { | |
fd361982 AM |
2208 | exidx_vma = bfd_section_vma (exidx); |
2209 | exidx_data.resize (bfd_section_size (exidx)); | |
0e9e9abd UW |
2210 | |
2211 | if (!bfd_get_section_contents (objfile->obfd, exidx, | |
984c7238 TT |
2212 | exidx_data.data (), 0, |
2213 | exidx_data.size ())) | |
2214 | return; | |
0e9e9abd UW |
2215 | } |
2216 | ||
2217 | extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab"); | |
984c7238 | 2218 | gdb::byte_vector extab_data; |
0e9e9abd UW |
2219 | if (extab) |
2220 | { | |
fd361982 AM |
2221 | extab_vma = bfd_section_vma (extab); |
2222 | extab_data.resize (bfd_section_size (extab)); | |
0e9e9abd UW |
2223 | |
2224 | if (!bfd_get_section_contents (objfile->obfd, extab, | |
984c7238 TT |
2225 | extab_data.data (), 0, |
2226 | extab_data.size ())) | |
2227 | return; | |
0e9e9abd UW |
2228 | } |
2229 | ||
2230 | /* Allocate exception table data structure. */ | |
a2726d4f | 2231 | data = arm_exidx_data_key.emplace (objfile->obfd); |
7a5d944b | 2232 | data->section_maps.resize (objfile->obfd->section_count); |
0e9e9abd UW |
2233 | |
2234 | /* Fill in exception table. */ | |
984c7238 | 2235 | for (i = 0; i < exidx_data.size () / 8; i++) |
0e9e9abd UW |
2236 | { |
2237 | struct arm_exidx_entry new_exidx_entry; | |
984c7238 TT |
2238 | bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8); |
2239 | bfd_vma val = bfd_h_get_32 (objfile->obfd, | |
2240 | exidx_data.data () + i * 8 + 4); | |
0e9e9abd UW |
2241 | bfd_vma addr = 0, word = 0; |
2242 | int n_bytes = 0, n_words = 0; | |
2243 | struct obj_section *sec; | |
2244 | gdb_byte *entry = NULL; | |
2245 | ||
2246 | /* Extract address of start of function. */ | |
2247 | idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2248 | idx += exidx_vma + i * 8; | |
2249 | ||
2250 | /* Find section containing function and compute section offset. */ | |
2251 | sec = arm_obj_section_from_vma (objfile, idx); | |
2252 | if (sec == NULL) | |
2253 | continue; | |
fd361982 | 2254 | idx -= bfd_section_vma (sec->the_bfd_section); |
0e9e9abd UW |
2255 | |
2256 | /* Determine address of exception table entry. */ | |
2257 | if (val == 1) | |
2258 | { | |
2259 | /* EXIDX_CANTUNWIND -- no exception table entry present. */ | |
2260 | } | |
2261 | else if ((val & 0xff000000) == 0x80000000) | |
2262 | { | |
2263 | /* Exception table entry embedded in .ARM.exidx | |
2264 | -- must be short form. */ | |
2265 | word = val; | |
2266 | n_bytes = 3; | |
2267 | } | |
2268 | else if (!(val & 0x80000000)) | |
2269 | { | |
2270 | /* Exception table entry in .ARM.extab. */ | |
2271 | addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2272 | addr += exidx_vma + i * 8 + 4; | |
2273 | ||
984c7238 | 2274 | if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2275 | { |
2276 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2277 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2278 | addr += 4; |
2279 | ||
2280 | if ((word & 0xff000000) == 0x80000000) | |
2281 | { | |
2282 | /* Short form. */ | |
2283 | n_bytes = 3; | |
2284 | } | |
2285 | else if ((word & 0xff000000) == 0x81000000 | |
2286 | || (word & 0xff000000) == 0x82000000) | |
2287 | { | |
2288 | /* Long form. */ | |
2289 | n_bytes = 2; | |
2290 | n_words = ((word >> 16) & 0xff); | |
2291 | } | |
2292 | else if (!(word & 0x80000000)) | |
2293 | { | |
2294 | bfd_vma pers; | |
2295 | struct obj_section *pers_sec; | |
2296 | int gnu_personality = 0; | |
2297 | ||
2298 | /* Custom personality routine. */ | |
2299 | pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000; | |
2300 | pers = UNMAKE_THUMB_ADDR (pers + addr - 4); | |
2301 | ||
2302 | /* Check whether we've got one of the variants of the | |
2303 | GNU personality routines. */ | |
2304 | pers_sec = arm_obj_section_from_vma (objfile, pers); | |
2305 | if (pers_sec) | |
2306 | { | |
2307 | static const char *personality[] = | |
2308 | { | |
2309 | "__gcc_personality_v0", | |
2310 | "__gxx_personality_v0", | |
2311 | "__gcj_personality_v0", | |
2312 | "__gnu_objc_personality_v0", | |
2313 | NULL | |
2314 | }; | |
2315 | ||
0c1bcd23 | 2316 | CORE_ADDR pc = pers + pers_sec->offset (); |
0e9e9abd UW |
2317 | int k; |
2318 | ||
2319 | for (k = 0; personality[k]; k++) | |
2320 | if (lookup_minimal_symbol_by_pc_name | |
2321 | (pc, personality[k], objfile)) | |
2322 | { | |
2323 | gnu_personality = 1; | |
2324 | break; | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | /* If so, the next word contains a word count in the high | |
2329 | byte, followed by the same unwind instructions as the | |
2330 | pre-defined forms. */ | |
2331 | if (gnu_personality | |
984c7238 | 2332 | && addr + 4 <= extab_vma + extab_data.size ()) |
0e9e9abd UW |
2333 | { |
2334 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 TT |
2335 | (extab_data.data () |
2336 | + addr - extab_vma)); | |
0e9e9abd UW |
2337 | addr += 4; |
2338 | n_bytes = 3; | |
2339 | n_words = ((word >> 24) & 0xff); | |
2340 | } | |
2341 | } | |
2342 | } | |
2343 | } | |
2344 | ||
2345 | /* Sanity check address. */ | |
2346 | if (n_words) | |
984c7238 TT |
2347 | if (addr < extab_vma |
2348 | || addr + 4 * n_words > extab_vma + extab_data.size ()) | |
0e9e9abd UW |
2349 | n_words = n_bytes = 0; |
2350 | ||
2351 | /* The unwind instructions reside in WORD (only the N_BYTES least | |
2352 | significant bytes are valid), followed by N_WORDS words in the | |
2353 | extab section starting at ADDR. */ | |
2354 | if (n_bytes || n_words) | |
2355 | { | |
224c3ddb SM |
2356 | gdb_byte *p = entry |
2357 | = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, | |
2358 | n_bytes + n_words * 4 + 1); | |
0e9e9abd UW |
2359 | |
2360 | while (n_bytes--) | |
2361 | *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); | |
2362 | ||
2363 | while (n_words--) | |
2364 | { | |
2365 | word = bfd_h_get_32 (objfile->obfd, | |
984c7238 | 2366 | extab_data.data () + addr - extab_vma); |
0e9e9abd UW |
2367 | addr += 4; |
2368 | ||
2369 | *p++ = (gdb_byte) ((word >> 24) & 0xff); | |
2370 | *p++ = (gdb_byte) ((word >> 16) & 0xff); | |
2371 | *p++ = (gdb_byte) ((word >> 8) & 0xff); | |
2372 | *p++ = (gdb_byte) (word & 0xff); | |
2373 | } | |
2374 | ||
2375 | /* Implied "Finish" to terminate the list. */ | |
2376 | *p++ = 0xb0; | |
2377 | } | |
2378 | ||
2379 | /* Push entry onto vector. They are guaranteed to always | |
2380 | appear in order of increasing addresses. */ | |
2381 | new_exidx_entry.addr = idx; | |
2382 | new_exidx_entry.entry = entry; | |
7a5d944b TT |
2383 | data->section_maps[sec->the_bfd_section->index].push_back |
2384 | (new_exidx_entry); | |
0e9e9abd | 2385 | } |
0e9e9abd UW |
2386 | } |
2387 | ||
2388 | /* Search for the exception table entry covering MEMADDR. If one is found, | |
2389 | return a pointer to its data. Otherwise, return 0. If START is non-NULL, | |
2390 | set *START to the start of the region covered by this entry. */ | |
2391 | ||
2392 | static gdb_byte * | |
2393 | arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) | |
2394 | { | |
2395 | struct obj_section *sec; | |
2396 | ||
2397 | sec = find_pc_section (memaddr); | |
2398 | if (sec != NULL) | |
2399 | { | |
2400 | struct arm_exidx_data *data; | |
0c1bcd23 | 2401 | struct arm_exidx_entry map_key = { memaddr - sec->addr (), 0 }; |
0e9e9abd | 2402 | |
a2726d4f | 2403 | data = arm_exidx_data_key.get (sec->objfile->obfd); |
0e9e9abd UW |
2404 | if (data != NULL) |
2405 | { | |
7a5d944b TT |
2406 | std::vector<arm_exidx_entry> &map |
2407 | = data->section_maps[sec->the_bfd_section->index]; | |
2408 | if (!map.empty ()) | |
0e9e9abd | 2409 | { |
7a5d944b | 2410 | auto idx = std::lower_bound (map.begin (), map.end (), map_key); |
0e9e9abd | 2411 | |
7a5d944b | 2412 | /* std::lower_bound finds the earliest ordered insertion |
0e9e9abd UW |
2413 | point. If the following symbol starts at this exact |
2414 | address, we use that; otherwise, the preceding | |
2415 | exception table entry covers this address. */ | |
7a5d944b | 2416 | if (idx < map.end ()) |
0e9e9abd | 2417 | { |
7a5d944b | 2418 | if (idx->addr == map_key.addr) |
0e9e9abd UW |
2419 | { |
2420 | if (start) | |
0c1bcd23 | 2421 | *start = idx->addr + sec->addr (); |
7a5d944b | 2422 | return idx->entry; |
0e9e9abd UW |
2423 | } |
2424 | } | |
2425 | ||
7a5d944b | 2426 | if (idx > map.begin ()) |
0e9e9abd | 2427 | { |
7a5d944b | 2428 | idx = idx - 1; |
0e9e9abd | 2429 | if (start) |
0c1bcd23 | 2430 | *start = idx->addr + sec->addr (); |
7a5d944b | 2431 | return idx->entry; |
0e9e9abd UW |
2432 | } |
2433 | } | |
2434 | } | |
2435 | } | |
2436 | ||
2437 | return NULL; | |
2438 | } | |
2439 | ||
2440 | /* Given the current frame THIS_FRAME, and its associated frame unwinding | |
2441 | instruction list from the ARM exception table entry ENTRY, allocate and | |
2442 | return a prologue cache structure describing how to unwind this frame. | |
2443 | ||
2444 | Return NULL if the unwinding instruction list contains a "spare", | |
2445 | "reserved" or "refuse to unwind" instruction as defined in section | |
2446 | "9.3 Frame unwinding instructions" of the "Exception Handling ABI | |
2447 | for the ARM Architecture" document. */ | |
2448 | ||
2449 | static struct arm_prologue_cache * | |
2450 | arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) | |
2451 | { | |
2452 | CORE_ADDR vsp = 0; | |
2453 | int vsp_valid = 0; | |
2454 | ||
2455 | struct arm_prologue_cache *cache; | |
2456 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2457 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2458 | ||
2459 | for (;;) | |
2460 | { | |
2461 | gdb_byte insn; | |
2462 | ||
2463 | /* Whenever we reload SP, we actually have to retrieve its | |
2464 | actual value in the current frame. */ | |
2465 | if (!vsp_valid) | |
2466 | { | |
a9a87d35 | 2467 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
0e9e9abd | 2468 | { |
098caef4 | 2469 | int reg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2470 | vsp = get_frame_register_unsigned (this_frame, reg); |
2471 | } | |
2472 | else | |
2473 | { | |
098caef4 | 2474 | CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr (); |
0e9e9abd UW |
2475 | vsp = get_frame_memory_unsigned (this_frame, addr, 4); |
2476 | } | |
2477 | ||
2478 | vsp_valid = 1; | |
2479 | } | |
2480 | ||
2481 | /* Decode next unwind instruction. */ | |
2482 | insn = *entry++; | |
2483 | ||
2484 | if ((insn & 0xc0) == 0) | |
2485 | { | |
2486 | int offset = insn & 0x3f; | |
2487 | vsp += (offset << 2) + 4; | |
2488 | } | |
2489 | else if ((insn & 0xc0) == 0x40) | |
2490 | { | |
2491 | int offset = insn & 0x3f; | |
2492 | vsp -= (offset << 2) + 4; | |
2493 | } | |
2494 | else if ((insn & 0xf0) == 0x80) | |
2495 | { | |
2496 | int mask = ((insn & 0xf) << 8) | *entry++; | |
2497 | int i; | |
2498 | ||
2499 | /* The special case of an all-zero mask identifies | |
2500 | "Refuse to unwind". We return NULL to fall back | |
2501 | to the prologue analyzer. */ | |
2502 | if (mask == 0) | |
2503 | return NULL; | |
2504 | ||
2505 | /* Pop registers r4..r15 under mask. */ | |
2506 | for (i = 0; i < 12; i++) | |
2507 | if (mask & (1 << i)) | |
2508 | { | |
098caef4 | 2509 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2510 | vsp += 4; |
2511 | } | |
2512 | ||
2513 | /* Special-case popping SP -- we need to reload vsp. */ | |
2514 | if (mask & (1 << (ARM_SP_REGNUM - 4))) | |
2515 | vsp_valid = 0; | |
2516 | } | |
2517 | else if ((insn & 0xf0) == 0x90) | |
2518 | { | |
2519 | int reg = insn & 0xf; | |
2520 | ||
2521 | /* Reserved cases. */ | |
2522 | if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM) | |
2523 | return NULL; | |
2524 | ||
2525 | /* Set SP from another register and mark VSP for reload. */ | |
2526 | cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg]; | |
2527 | vsp_valid = 0; | |
2528 | } | |
2529 | else if ((insn & 0xf0) == 0xa0) | |
2530 | { | |
2531 | int count = insn & 0x7; | |
2532 | int pop_lr = (insn & 0x8) != 0; | |
2533 | int i; | |
2534 | ||
2535 | /* Pop r4..r[4+count]. */ | |
2536 | for (i = 0; i <= count; i++) | |
2537 | { | |
098caef4 | 2538 | cache->saved_regs[4 + i].set_addr (vsp); |
0e9e9abd UW |
2539 | vsp += 4; |
2540 | } | |
2541 | ||
2542 | /* If indicated by flag, pop LR as well. */ | |
2543 | if (pop_lr) | |
2544 | { | |
098caef4 | 2545 | cache->saved_regs[ARM_LR_REGNUM].set_addr (vsp); |
0e9e9abd UW |
2546 | vsp += 4; |
2547 | } | |
2548 | } | |
2549 | else if (insn == 0xb0) | |
2550 | { | |
2551 | /* We could only have updated PC by popping into it; if so, it | |
2552 | will show up as address. Otherwise, copy LR into PC. */ | |
a9a87d35 | 2553 | if (!cache->saved_regs[ARM_PC_REGNUM].is_addr ()) |
0e9e9abd UW |
2554 | cache->saved_regs[ARM_PC_REGNUM] |
2555 | = cache->saved_regs[ARM_LR_REGNUM]; | |
2556 | ||
2557 | /* We're done. */ | |
2558 | break; | |
2559 | } | |
2560 | else if (insn == 0xb1) | |
2561 | { | |
2562 | int mask = *entry++; | |
2563 | int i; | |
2564 | ||
2565 | /* All-zero mask and mask >= 16 is "spare". */ | |
2566 | if (mask == 0 || mask >= 16) | |
2567 | return NULL; | |
2568 | ||
2569 | /* Pop r0..r3 under mask. */ | |
2570 | for (i = 0; i < 4; i++) | |
2571 | if (mask & (1 << i)) | |
2572 | { | |
098caef4 | 2573 | cache->saved_regs[i].set_addr (vsp); |
0e9e9abd UW |
2574 | vsp += 4; |
2575 | } | |
2576 | } | |
2577 | else if (insn == 0xb2) | |
2578 | { | |
2579 | ULONGEST offset = 0; | |
2580 | unsigned shift = 0; | |
2581 | ||
2582 | do | |
2583 | { | |
2584 | offset |= (*entry & 0x7f) << shift; | |
2585 | shift += 7; | |
2586 | } | |
2587 | while (*entry++ & 0x80); | |
2588 | ||
2589 | vsp += 0x204 + (offset << 2); | |
2590 | } | |
2591 | else if (insn == 0xb3) | |
2592 | { | |
2593 | int start = *entry >> 4; | |
2594 | int count = (*entry++) & 0xf; | |
2595 | int i; | |
2596 | ||
2597 | /* Only registers D0..D15 are valid here. */ | |
2598 | if (start + count >= 16) | |
2599 | return NULL; | |
2600 | ||
2601 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2602 | for (i = 0; i <= count; i++) | |
2603 | { | |
098caef4 | 2604 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2605 | vsp += 8; |
2606 | } | |
2607 | ||
2608 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2609 | vsp += 4; | |
2610 | } | |
2611 | else if ((insn & 0xf8) == 0xb8) | |
2612 | { | |
2613 | int count = insn & 0x7; | |
2614 | int i; | |
2615 | ||
2616 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2617 | for (i = 0; i <= count; i++) | |
2618 | { | |
098caef4 | 2619 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2620 | vsp += 8; |
2621 | } | |
2622 | ||
2623 | /* Add an extra 4 bytes for FSTMFDX-style stack. */ | |
2624 | vsp += 4; | |
2625 | } | |
2626 | else if (insn == 0xc6) | |
2627 | { | |
2628 | int start = *entry >> 4; | |
2629 | int count = (*entry++) & 0xf; | |
2630 | int i; | |
2631 | ||
2632 | /* Only registers WR0..WR15 are valid. */ | |
2633 | if (start + count >= 16) | |
2634 | return NULL; | |
2635 | ||
2636 | /* Pop iwmmx registers WR[start]..WR[start+count]. */ | |
2637 | for (i = 0; i <= count; i++) | |
2638 | { | |
098caef4 | 2639 | cache->saved_regs[ARM_WR0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2640 | vsp += 8; |
2641 | } | |
2642 | } | |
2643 | else if (insn == 0xc7) | |
2644 | { | |
2645 | int mask = *entry++; | |
2646 | int i; | |
2647 | ||
2648 | /* All-zero mask and mask >= 16 is "spare". */ | |
2649 | if (mask == 0 || mask >= 16) | |
2650 | return NULL; | |
2651 | ||
2652 | /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */ | |
2653 | for (i = 0; i < 4; i++) | |
2654 | if (mask & (1 << i)) | |
2655 | { | |
098caef4 | 2656 | cache->saved_regs[ARM_WCGR0_REGNUM + i].set_addr (vsp); |
0e9e9abd UW |
2657 | vsp += 4; |
2658 | } | |
2659 | } | |
2660 | else if ((insn & 0xf8) == 0xc0) | |
2661 | { | |
2662 | int count = insn & 0x7; | |
2663 | int i; | |
2664 | ||
2665 | /* Pop iwmmx registers WR[10]..WR[10+count]. */ | |
2666 | for (i = 0; i <= count; i++) | |
2667 | { | |
098caef4 | 2668 | cache->saved_regs[ARM_WR0_REGNUM + 10 + i].set_addr (vsp); |
0e9e9abd UW |
2669 | vsp += 8; |
2670 | } | |
2671 | } | |
2672 | else if (insn == 0xc8) | |
2673 | { | |
2674 | int start = *entry >> 4; | |
2675 | int count = (*entry++) & 0xf; | |
2676 | int i; | |
2677 | ||
2678 | /* Only registers D0..D31 are valid. */ | |
2679 | if (start + count >= 16) | |
2680 | return NULL; | |
2681 | ||
2682 | /* Pop VFP double-precision registers | |
2683 | D[16+start]..D[16+start+count]. */ | |
2684 | for (i = 0; i <= count; i++) | |
2685 | { | |
098caef4 | 2686 | cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].set_addr (vsp); |
0e9e9abd UW |
2687 | vsp += 8; |
2688 | } | |
2689 | } | |
2690 | else if (insn == 0xc9) | |
2691 | { | |
2692 | int start = *entry >> 4; | |
2693 | int count = (*entry++) & 0xf; | |
2694 | int i; | |
2695 | ||
2696 | /* Pop VFP double-precision registers D[start]..D[start+count]. */ | |
2697 | for (i = 0; i <= count; i++) | |
2698 | { | |
098caef4 | 2699 | cache->saved_regs[ARM_D0_REGNUM + start + i].set_addr (vsp); |
0e9e9abd UW |
2700 | vsp += 8; |
2701 | } | |
2702 | } | |
2703 | else if ((insn & 0xf8) == 0xd0) | |
2704 | { | |
2705 | int count = insn & 0x7; | |
2706 | int i; | |
2707 | ||
2708 | /* Pop VFP double-precision registers D[8]..D[8+count]. */ | |
2709 | for (i = 0; i <= count; i++) | |
2710 | { | |
098caef4 | 2711 | cache->saved_regs[ARM_D0_REGNUM + 8 + i].set_addr (vsp); |
0e9e9abd UW |
2712 | vsp += 8; |
2713 | } | |
2714 | } | |
2715 | else | |
2716 | { | |
2717 | /* Everything else is "spare". */ | |
2718 | return NULL; | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | /* If we restore SP from a register, assume this was the frame register. | |
2723 | Otherwise just fall back to SP as frame register. */ | |
a9a87d35 | 2724 | if (cache->saved_regs[ARM_SP_REGNUM].is_realreg ()) |
098caef4 | 2725 | cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg (); |
0e9e9abd UW |
2726 | else |
2727 | cache->framereg = ARM_SP_REGNUM; | |
2728 | ||
2729 | /* Determine offset to previous frame. */ | |
2730 | cache->framesize | |
2731 | = vsp - get_frame_register_unsigned (this_frame, cache->framereg); | |
2732 | ||
2733 | /* We already got the previous SP. */ | |
2734 | cache->prev_sp = vsp; | |
2735 | ||
2736 | return cache; | |
2737 | } | |
2738 | ||
2739 | /* Unwinding via ARM exception table entries. Note that the sniffer | |
2740 | already computes a filled-in prologue cache, which is then used | |
2741 | with the same arm_prologue_this_id and arm_prologue_prev_register | |
2742 | routines also used for prologue-parsing based unwinding. */ | |
2743 | ||
2744 | static int | |
2745 | arm_exidx_unwind_sniffer (const struct frame_unwind *self, | |
2746 | struct frame_info *this_frame, | |
2747 | void **this_prologue_cache) | |
2748 | { | |
2749 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2750 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2751 | CORE_ADDR addr_in_block, exidx_region, func_start; | |
2752 | struct arm_prologue_cache *cache; | |
2753 | gdb_byte *entry; | |
2754 | ||
2755 | /* See if we have an ARM exception table entry covering this address. */ | |
2756 | addr_in_block = get_frame_address_in_block (this_frame); | |
2757 | entry = arm_find_exidx_entry (addr_in_block, &exidx_region); | |
2758 | if (!entry) | |
2759 | return 0; | |
2760 | ||
2761 | /* The ARM exception table does not describe unwind information | |
2762 | for arbitrary PC values, but is guaranteed to be correct only | |
2763 | at call sites. We have to decide here whether we want to use | |
2764 | ARM exception table information for this frame, or fall back | |
2765 | to using prologue parsing. (Note that if we have DWARF CFI, | |
2766 | this sniffer isn't even called -- CFI is always preferred.) | |
2767 | ||
2768 | Before we make this decision, however, we check whether we | |
2769 | actually have *symbol* information for the current frame. | |
2770 | If not, prologue parsing would not work anyway, so we might | |
2771 | as well use the exception table and hope for the best. */ | |
2772 | if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL)) | |
2773 | { | |
2774 | int exc_valid = 0; | |
2775 | ||
2776 | /* If the next frame is "normal", we are at a call site in this | |
2777 | frame, so exception information is guaranteed to be valid. */ | |
2778 | if (get_next_frame (this_frame) | |
2779 | && get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME) | |
2780 | exc_valid = 1; | |
2781 | ||
2782 | /* We also assume exception information is valid if we're currently | |
2783 | blocked in a system call. The system library is supposed to | |
d9311bfa AT |
2784 | ensure this, so that e.g. pthread cancellation works. */ |
2785 | if (arm_frame_is_thumb (this_frame)) | |
0e9e9abd | 2786 | { |
7913a64c | 2787 | ULONGEST insn; |
416dc9c6 | 2788 | |
7913a64c YQ |
2789 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, |
2790 | 2, byte_order_for_code, &insn) | |
d9311bfa AT |
2791 | && (insn & 0xff00) == 0xdf00 /* svc */) |
2792 | exc_valid = 1; | |
0e9e9abd | 2793 | } |
d9311bfa AT |
2794 | else |
2795 | { | |
7913a64c | 2796 | ULONGEST insn; |
416dc9c6 | 2797 | |
7913a64c YQ |
2798 | if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, |
2799 | 4, byte_order_for_code, &insn) | |
d9311bfa AT |
2800 | && (insn & 0x0f000000) == 0x0f000000 /* svc */) |
2801 | exc_valid = 1; | |
2802 | } | |
2803 | ||
0e9e9abd UW |
2804 | /* Bail out if we don't know that exception information is valid. */ |
2805 | if (!exc_valid) | |
2806 | return 0; | |
2807 | ||
2808 | /* The ARM exception index does not mark the *end* of the region | |
2809 | covered by the entry, and some functions will not have any entry. | |
2810 | To correctly recognize the end of the covered region, the linker | |
2811 | should have inserted dummy records with a CANTUNWIND marker. | |
2812 | ||
2813 | Unfortunately, current versions of GNU ld do not reliably do | |
2814 | this, and thus we may have found an incorrect entry above. | |
2815 | As a (temporary) sanity check, we only use the entry if it | |
2816 | lies *within* the bounds of the function. Note that this check | |
2817 | might reject perfectly valid entries that just happen to cover | |
2818 | multiple functions; therefore this check ought to be removed | |
2819 | once the linker is fixed. */ | |
2820 | if (func_start > exidx_region) | |
2821 | return 0; | |
2822 | } | |
2823 | ||
2824 | /* Decode the list of unwinding instructions into a prologue cache. | |
2825 | Note that this may fail due to e.g. a "refuse to unwind" code. */ | |
2826 | cache = arm_exidx_fill_cache (this_frame, entry); | |
2827 | if (!cache) | |
2828 | return 0; | |
2829 | ||
2830 | *this_prologue_cache = cache; | |
2831 | return 1; | |
2832 | } | |
2833 | ||
2834 | struct frame_unwind arm_exidx_unwind = { | |
a154d838 | 2835 | "arm exidx", |
0e9e9abd | 2836 | NORMAL_FRAME, |
8fbca658 | 2837 | default_frame_unwind_stop_reason, |
0e9e9abd UW |
2838 | arm_prologue_this_id, |
2839 | arm_prologue_prev_register, | |
2840 | NULL, | |
2841 | arm_exidx_unwind_sniffer | |
2842 | }; | |
2843 | ||
779aa56f YQ |
2844 | static struct arm_prologue_cache * |
2845 | arm_make_epilogue_frame_cache (struct frame_info *this_frame) | |
2846 | { | |
2847 | struct arm_prologue_cache *cache; | |
779aa56f YQ |
2848 | int reg; |
2849 | ||
2850 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
2851 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2852 | ||
2853 | /* Still rely on the offset calculated from prologue. */ | |
2854 | arm_scan_prologue (this_frame, cache); | |
2855 | ||
2856 | /* Since we are in epilogue, the SP has been restored. */ | |
2857 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
2858 | ||
2859 | /* Calculate actual addresses of saved registers using offsets | |
2860 | determined by arm_scan_prologue. */ | |
2861 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 2862 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
2863 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
2864 | + cache->prev_sp); | |
779aa56f YQ |
2865 | |
2866 | return cache; | |
2867 | } | |
2868 | ||
2869 | /* Implementation of function hook 'this_id' in | |
2870 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2871 | ||
2872 | static void | |
2873 | arm_epilogue_frame_this_id (struct frame_info *this_frame, | |
2874 | void **this_cache, | |
2875 | struct frame_id *this_id) | |
2876 | { | |
2877 | struct arm_prologue_cache *cache; | |
2878 | CORE_ADDR pc, func; | |
2879 | ||
2880 | if (*this_cache == NULL) | |
2881 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
2882 | cache = (struct arm_prologue_cache *) *this_cache; | |
2883 | ||
2884 | /* Use function start address as part of the frame ID. If we cannot | |
2885 | identify the start address (due to missing symbol information), | |
2886 | fall back to just using the current PC. */ | |
2887 | pc = get_frame_pc (this_frame); | |
2888 | func = get_frame_func (this_frame); | |
fb3f3d25 | 2889 | if (func == 0) |
779aa56f YQ |
2890 | func = pc; |
2891 | ||
2892 | (*this_id) = frame_id_build (cache->prev_sp, pc); | |
2893 | } | |
2894 | ||
2895 | /* Implementation of function hook 'prev_register' in | |
2896 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2897 | ||
2898 | static struct value * | |
2899 | arm_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2900 | void **this_cache, int regnum) | |
2901 | { | |
779aa56f YQ |
2902 | if (*this_cache == NULL) |
2903 | *this_cache = arm_make_epilogue_frame_cache (this_frame); | |
779aa56f YQ |
2904 | |
2905 | return arm_prologue_prev_register (this_frame, this_cache, regnum); | |
2906 | } | |
2907 | ||
2908 | static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, | |
2909 | CORE_ADDR pc); | |
2910 | static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, | |
2911 | CORE_ADDR pc); | |
2912 | ||
2913 | /* Implementation of function hook 'sniffer' in | |
2914 | 'struct frame_uwnind' for epilogue unwinder. */ | |
2915 | ||
2916 | static int | |
2917 | arm_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2918 | struct frame_info *this_frame, | |
2919 | void **this_prologue_cache) | |
2920 | { | |
2921 | if (frame_relative_level (this_frame) == 0) | |
2922 | { | |
2923 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2924 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2925 | ||
2926 | if (arm_frame_is_thumb (this_frame)) | |
2927 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
2928 | else | |
2929 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
2930 | } | |
2931 | else | |
2932 | return 0; | |
2933 | } | |
2934 | ||
2935 | /* Frame unwinder from epilogue. */ | |
2936 | ||
2937 | static const struct frame_unwind arm_epilogue_frame_unwind = | |
2938 | { | |
a154d838 | 2939 | "arm epilogue", |
779aa56f YQ |
2940 | NORMAL_FRAME, |
2941 | default_frame_unwind_stop_reason, | |
2942 | arm_epilogue_frame_this_id, | |
2943 | arm_epilogue_frame_prev_register, | |
2944 | NULL, | |
2945 | arm_epilogue_frame_sniffer, | |
2946 | }; | |
2947 | ||
80d8d390 YQ |
2948 | /* Recognize GCC's trampoline for thumb call-indirect. If we are in a |
2949 | trampoline, return the target PC. Otherwise return 0. | |
2950 | ||
2951 | void call0a (char c, short s, int i, long l) {} | |
2952 | ||
2953 | int main (void) | |
2954 | { | |
2955 | (*pointer_to_call0a) (c, s, i, l); | |
2956 | } | |
2957 | ||
2958 | Instead of calling a stub library function _call_via_xx (xx is | |
2959 | the register name), GCC may inline the trampoline in the object | |
2960 | file as below (register r2 has the address of call0a). | |
2961 | ||
2962 | .global main | |
2963 | .type main, %function | |
2964 | ... | |
2965 | bl .L1 | |
2966 | ... | |
2967 | .size main, .-main | |
2968 | ||
2969 | .L1: | |
2970 | bx r2 | |
2971 | ||
2972 | The trampoline 'bx r2' doesn't belong to main. */ | |
2973 | ||
2974 | static CORE_ADDR | |
2975 | arm_skip_bx_reg (struct frame_info *frame, CORE_ADDR pc) | |
2976 | { | |
2977 | /* The heuristics of recognizing such trampoline is that FRAME is | |
2978 | executing in Thumb mode and the instruction on PC is 'bx Rm'. */ | |
2979 | if (arm_frame_is_thumb (frame)) | |
2980 | { | |
2981 | gdb_byte buf[2]; | |
2982 | ||
2983 | if (target_read_memory (pc, buf, 2) == 0) | |
2984 | { | |
2985 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2986 | enum bfd_endian byte_order_for_code | |
2987 | = gdbarch_byte_order_for_code (gdbarch); | |
2988 | uint16_t insn | |
2989 | = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
2990 | ||
2991 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
2992 | { | |
2993 | CORE_ADDR dest | |
2994 | = get_frame_register_unsigned (frame, bits (insn, 3, 6)); | |
2995 | ||
2996 | /* Clear the LSB so that gdb core sets step-resume | |
2997 | breakpoint at the right address. */ | |
2998 | return UNMAKE_THUMB_ADDR (dest); | |
2999 | } | |
3000 | } | |
3001 | } | |
3002 | ||
3003 | return 0; | |
3004 | } | |
3005 | ||
909cf6ea | 3006 | static struct arm_prologue_cache * |
a262aec2 | 3007 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea | 3008 | { |
909cf6ea | 3009 | struct arm_prologue_cache *cache; |
909cf6ea | 3010 | |
35d5d4ee | 3011 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 3012 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 3013 | |
a262aec2 | 3014 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
3015 | |
3016 | return cache; | |
3017 | } | |
3018 | ||
3019 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3020 | ||
3021 | static void | |
a262aec2 | 3022 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
3023 | void **this_cache, |
3024 | struct frame_id *this_id) | |
3025 | { | |
3026 | struct arm_prologue_cache *cache; | |
3027 | ||
3028 | if (*this_cache == NULL) | |
a262aec2 | 3029 | *this_cache = arm_make_stub_cache (this_frame); |
9a3c8263 | 3030 | cache = (struct arm_prologue_cache *) *this_cache; |
909cf6ea | 3031 | |
a262aec2 | 3032 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
3033 | } |
3034 | ||
a262aec2 DJ |
3035 | static int |
3036 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
3037 | struct frame_info *this_frame, | |
3038 | void **this_prologue_cache) | |
909cf6ea | 3039 | { |
93d42b30 | 3040 | CORE_ADDR addr_in_block; |
948f8e3d | 3041 | gdb_byte dummy[4]; |
18d18ac8 YQ |
3042 | CORE_ADDR pc, start_addr; |
3043 | const char *name; | |
909cf6ea | 3044 | |
a262aec2 | 3045 | addr_in_block = get_frame_address_in_block (this_frame); |
18d18ac8 | 3046 | pc = get_frame_pc (this_frame); |
3e5d3a5a | 3047 | if (in_plt_section (addr_in_block) |
fc36e839 DE |
3048 | /* We also use the stub winder if the target memory is unreadable |
3049 | to avoid having the prologue unwinder trying to read it. */ | |
18d18ac8 YQ |
3050 | || target_read_memory (pc, dummy, 4) != 0) |
3051 | return 1; | |
3052 | ||
3053 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0 | |
3054 | && arm_skip_bx_reg (this_frame, pc) != 0) | |
a262aec2 | 3055 | return 1; |
909cf6ea | 3056 | |
a262aec2 | 3057 | return 0; |
909cf6ea DJ |
3058 | } |
3059 | ||
a262aec2 | 3060 | struct frame_unwind arm_stub_unwind = { |
a154d838 | 3061 | "arm stub", |
a262aec2 | 3062 | NORMAL_FRAME, |
8fbca658 | 3063 | default_frame_unwind_stop_reason, |
a262aec2 DJ |
3064 | arm_stub_this_id, |
3065 | arm_prologue_prev_register, | |
3066 | NULL, | |
3067 | arm_stub_unwind_sniffer | |
3068 | }; | |
3069 | ||
2ae28aa9 YQ |
3070 | /* Put here the code to store, into CACHE->saved_regs, the addresses |
3071 | of the saved registers of frame described by THIS_FRAME. CACHE is | |
3072 | returned. */ | |
3073 | ||
3074 | static struct arm_prologue_cache * | |
3075 | arm_m_exception_cache (struct frame_info *this_frame) | |
3076 | { | |
3077 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3078 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3079 | struct arm_prologue_cache *cache; | |
55ea94da FH |
3080 | CORE_ADDR lr; |
3081 | CORE_ADDR sp; | |
2ae28aa9 YQ |
3082 | CORE_ADDR unwound_sp; |
3083 | LONGEST xpsr; | |
55ea94da FH |
3084 | uint32_t exc_return; |
3085 | uint32_t process_stack_used; | |
3086 | uint32_t extended_frame_used; | |
3087 | uint32_t secure_stack_used; | |
2ae28aa9 YQ |
3088 | |
3089 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); | |
3090 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
3091 | ||
55ea94da FH |
3092 | /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" |
3093 | describes which bits in LR that define which stack was used prior | |
3094 | to the exception and if FPU is used (causing extended stack frame). */ | |
3095 | ||
3096 | lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM); | |
3097 | sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); | |
3098 | ||
3099 | /* Check EXC_RETURN indicator bits. */ | |
3100 | exc_return = (((lr >> 28) & 0xf) == 0xf); | |
3101 | ||
3102 | /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */ | |
3103 | process_stack_used = ((lr & (1 << 2)) != 0); | |
3104 | if (exc_return && process_stack_used) | |
3105 | { | |
3106 | /* Thread (process) stack used. | |
dda83cd7 SM |
3107 | Potentially this could be other register defined by target, but PSP |
3108 | can be considered a standard name for the "Process Stack Pointer". | |
3109 | To be fully aware of system registers like MSP and PSP, these could | |
3110 | be added to a separate XML arm-m-system-profile that is valid for | |
3111 | ARMv6-M and ARMv7-M architectures. Also to be able to debug eg a | |
3112 | corefile off-line, then these registers must be defined by GDB, | |
3113 | and also be included in the corefile regsets. */ | |
55ea94da FH |
3114 | |
3115 | int psp_regnum = user_reg_map_name_to_regnum (gdbarch, "psp", -1); | |
3116 | if (psp_regnum == -1) | |
dda83cd7 SM |
3117 | { |
3118 | /* Thread (process) stack could not be fetched, | |
3119 | give warning and exit. */ | |
55ea94da | 3120 | |
dda83cd7 | 3121 | warning (_("no PSP thread stack unwinding supported.")); |
55ea94da | 3122 | |
dda83cd7 SM |
3123 | /* Terminate any further stack unwinding by refer to self. */ |
3124 | cache->prev_sp = sp; | |
3125 | return cache; | |
3126 | } | |
55ea94da | 3127 | else |
dda83cd7 SM |
3128 | { |
3129 | /* Thread (process) stack used, use PSP as SP. */ | |
3130 | unwound_sp = get_frame_register_unsigned (this_frame, psp_regnum); | |
3131 | } | |
55ea94da FH |
3132 | } |
3133 | else | |
3134 | { | |
3135 | /* Main stack used, use MSP as SP. */ | |
3136 | unwound_sp = sp; | |
3137 | } | |
2ae28aa9 YQ |
3138 | |
3139 | /* The hardware saves eight 32-bit words, comprising xPSR, | |
3140 | ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in | |
3141 | "B1.5.6 Exception entry behavior" in | |
3142 | "ARMv7-M Architecture Reference Manual". */ | |
098caef4 LM |
3143 | cache->saved_regs[0].set_addr (unwound_sp); |
3144 | cache->saved_regs[1].set_addr (unwound_sp + 4); | |
3145 | cache->saved_regs[2].set_addr (unwound_sp + 8); | |
3146 | cache->saved_regs[3].set_addr (unwound_sp + 12); | |
3147 | cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + 16); | |
3148 | cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 20); | |
3149 | cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 24); | |
3150 | cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 28); | |
2ae28aa9 | 3151 | |
55ea94da FH |
3152 | /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) |
3153 | type used. */ | |
3154 | extended_frame_used = ((lr & (1 << 4)) == 0); | |
3155 | if (exc_return && extended_frame_used) | |
3156 | { | |
3157 | int i; | |
3158 | int fpu_regs_stack_offset; | |
3159 | ||
3160 | /* This code does not take into account the lazy stacking, see "Lazy | |
dda83cd7 SM |
3161 | context save of FP state", in B1.5.7, also ARM AN298, supported |
3162 | by Cortex-M4F architecture. | |
3163 | To fully handle this the FPCCR register (Floating-point Context | |
3164 | Control Register) needs to be read out and the bits ASPEN and LSPEN | |
3165 | could be checked to setup correct lazy stacked FP registers. | |
3166 | This register is located at address 0xE000EF34. */ | |
55ea94da FH |
3167 | |
3168 | /* Extended stack frame type used. */ | |
3169 | fpu_regs_stack_offset = unwound_sp + 0x20; | |
3170 | for (i = 0; i < 16; i++) | |
dda83cd7 | 3171 | { |
098caef4 | 3172 | cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); |
dda83cd7 SM |
3173 | fpu_regs_stack_offset += 4; |
3174 | } | |
098caef4 | 3175 | cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + 0x60); |
55ea94da FH |
3176 | |
3177 | /* Offset 0x64 is reserved. */ | |
3178 | cache->prev_sp = unwound_sp + 0x68; | |
3179 | } | |
3180 | else | |
3181 | { | |
3182 | /* Standard stack frame type used. */ | |
3183 | cache->prev_sp = unwound_sp + 0x20; | |
3184 | } | |
3185 | ||
3186 | /* Check EXC_RETURN bit S if Secure or Non-secure stack used. */ | |
3187 | secure_stack_used = ((lr & (1 << 6)) != 0); | |
3188 | if (exc_return && secure_stack_used) | |
3189 | { | |
3190 | /* ARMv8-M Exception and interrupt handling is not considered here. | |
3191 | In the ARMv8-M architecture also EXC_RETURN bit S is controlling if | |
3192 | the Secure or Non-secure stack was used. To separate Secure and | |
3193 | Non-secure stacks, processors that are based on the ARMv8-M | |
3194 | architecture support 4 stack pointers: MSP_S, PSP_S, MSP_NS, PSP_NS. | |
3195 | In addition, a stack limit feature is provided using stack limit | |
3196 | registers (accessible using MSR and MRS instructions) in Privileged | |
3197 | level. */ | |
3198 | } | |
3199 | ||
2ae28aa9 YQ |
3200 | /* If bit 9 of the saved xPSR is set, then there is a four-byte |
3201 | aligner between the top of the 32-byte stack frame and the | |
3202 | previous context's stack pointer. */ | |
2ae28aa9 YQ |
3203 | if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) |
3204 | && (xpsr & (1 << 9)) != 0) | |
3205 | cache->prev_sp += 4; | |
3206 | ||
3207 | return cache; | |
3208 | } | |
3209 | ||
3210 | /* Implementation of function hook 'this_id' in | |
3211 | 'struct frame_uwnind'. */ | |
3212 | ||
3213 | static void | |
3214 | arm_m_exception_this_id (struct frame_info *this_frame, | |
3215 | void **this_cache, | |
3216 | struct frame_id *this_id) | |
3217 | { | |
3218 | struct arm_prologue_cache *cache; | |
3219 | ||
3220 | if (*this_cache == NULL) | |
3221 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3222 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3223 | |
3224 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
3225 | *this_id = frame_id_build (cache->prev_sp, | |
3226 | get_frame_pc (this_frame)); | |
3227 | } | |
3228 | ||
3229 | /* Implementation of function hook 'prev_register' in | |
3230 | 'struct frame_uwnind'. */ | |
3231 | ||
3232 | static struct value * | |
3233 | arm_m_exception_prev_register (struct frame_info *this_frame, | |
3234 | void **this_cache, | |
3235 | int prev_regnum) | |
3236 | { | |
2ae28aa9 YQ |
3237 | struct arm_prologue_cache *cache; |
3238 | ||
3239 | if (*this_cache == NULL) | |
3240 | *this_cache = arm_m_exception_cache (this_frame); | |
9a3c8263 | 3241 | cache = (struct arm_prologue_cache *) *this_cache; |
2ae28aa9 YQ |
3242 | |
3243 | /* The value was already reconstructed into PREV_SP. */ | |
3244 | if (prev_regnum == ARM_SP_REGNUM) | |
3245 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
3246 | cache->prev_sp); | |
3247 | ||
3248 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
3249 | prev_regnum); | |
3250 | } | |
3251 | ||
3252 | /* Implementation of function hook 'sniffer' in | |
3253 | 'struct frame_uwnind'. */ | |
3254 | ||
3255 | static int | |
3256 | arm_m_exception_unwind_sniffer (const struct frame_unwind *self, | |
3257 | struct frame_info *this_frame, | |
3258 | void **this_prologue_cache) | |
3259 | { | |
3260 | CORE_ADDR this_pc = get_frame_pc (this_frame); | |
3261 | ||
3262 | /* No need to check is_m; this sniffer is only registered for | |
3263 | M-profile architectures. */ | |
3264 | ||
ca90e760 FH |
3265 | /* Check if exception frame returns to a magic PC value. */ |
3266 | return arm_m_addr_is_magic (this_pc); | |
2ae28aa9 YQ |
3267 | } |
3268 | ||
3269 | /* Frame unwinder for M-profile exceptions. */ | |
3270 | ||
3271 | struct frame_unwind arm_m_exception_unwind = | |
3272 | { | |
a154d838 | 3273 | "arm m exception", |
2ae28aa9 YQ |
3274 | SIGTRAMP_FRAME, |
3275 | default_frame_unwind_stop_reason, | |
3276 | arm_m_exception_this_id, | |
3277 | arm_m_exception_prev_register, | |
3278 | NULL, | |
3279 | arm_m_exception_unwind_sniffer | |
3280 | }; | |
3281 | ||
24de872b | 3282 | static CORE_ADDR |
a262aec2 | 3283 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
3284 | { |
3285 | struct arm_prologue_cache *cache; | |
3286 | ||
eb5492fa | 3287 | if (*this_cache == NULL) |
a262aec2 | 3288 | *this_cache = arm_make_prologue_cache (this_frame); |
9a3c8263 | 3289 | cache = (struct arm_prologue_cache *) *this_cache; |
eb5492fa | 3290 | |
4be43953 | 3291 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
3292 | } |
3293 | ||
eb5492fa DJ |
3294 | struct frame_base arm_normal_base = { |
3295 | &arm_prologue_unwind, | |
3296 | arm_normal_frame_base, | |
3297 | arm_normal_frame_base, | |
3298 | arm_normal_frame_base | |
3299 | }; | |
3300 | ||
b39cc962 DJ |
3301 | static struct value * |
3302 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
3303 | int regnum) | |
3304 | { | |
24568a2c | 3305 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
a01567f4 | 3306 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
b39cc962 | 3307 | CORE_ADDR lr, cpsr; |
9779414d | 3308 | ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); |
b39cc962 DJ |
3309 | |
3310 | switch (regnum) | |
3311 | { | |
3312 | case ARM_PC_REGNUM: | |
3313 | /* The PC is normally copied from the return column, which | |
3314 | describes saves of LR. However, that version may have an | |
3315 | extra bit set to indicate Thumb state. The bit is not | |
3316 | part of the PC. */ | |
a01567f4 LM |
3317 | |
3318 | /* Record in the frame whether the return address was signed. */ | |
3319 | if (tdep->have_pacbti) | |
3320 | { | |
3321 | CORE_ADDR ra_auth_code | |
3322 | = frame_unwind_register_unsigned (this_frame, | |
3323 | tdep->pacbti_pseudo_base); | |
3324 | ||
3325 | if (ra_auth_code != 0) | |
3326 | set_frame_previous_pc_masked (this_frame); | |
3327 | } | |
3328 | ||
b39cc962 DJ |
3329 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3330 | return frame_unwind_got_constant (this_frame, regnum, | |
24568a2c | 3331 | arm_addr_bits_remove (gdbarch, lr)); |
b39cc962 DJ |
3332 | |
3333 | case ARM_PS_REGNUM: | |
3334 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 3335 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
3336 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
3337 | if (IS_THUMB_ADDR (lr)) | |
9779414d | 3338 | cpsr |= t_bit; |
b39cc962 | 3339 | else |
9779414d | 3340 | cpsr &= ~t_bit; |
ca38c58e | 3341 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
3342 | |
3343 | default: | |
3344 | internal_error (__FILE__, __LINE__, | |
3345 | _("Unexpected register %d"), regnum); | |
3346 | } | |
3347 | } | |
3348 | ||
c9cf6e20 | 3349 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
4024ca99 UW |
3350 | |
3351 | static int | |
c9cf6e20 | 3352 | thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3353 | { |
3354 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3355 | unsigned int insn, insn2; | |
3356 | int found_return = 0, found_stack_adjust = 0; | |
3357 | CORE_ADDR func_start, func_end; | |
3358 | CORE_ADDR scan_pc; | |
3359 | gdb_byte buf[4]; | |
3360 | ||
3361 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3362 | return 0; | |
3363 | ||
3364 | /* The epilogue is a sequence of instructions along the following lines: | |
3365 | ||
3366 | - add stack frame size to SP or FP | |
3367 | - [if frame pointer used] restore SP from FP | |
3368 | - restore registers from SP [may include PC] | |
3369 | - a return-type instruction [if PC wasn't already restored] | |
3370 | ||
3371 | In a first pass, we scan forward from the current PC and verify the | |
3372 | instructions we find as compatible with this sequence, ending in a | |
3373 | return instruction. | |
3374 | ||
3375 | However, this is not sufficient to distinguish indirect function calls | |
3376 | within a function from indirect tail calls in the epilogue in some cases. | |
3377 | Therefore, if we didn't already find any SP-changing instruction during | |
3378 | forward scan, we add a backward scanning heuristic to ensure we actually | |
3379 | are in the epilogue. */ | |
3380 | ||
3381 | scan_pc = pc; | |
3382 | while (scan_pc < func_end && !found_return) | |
3383 | { | |
3384 | if (target_read_memory (scan_pc, buf, 2)) | |
3385 | break; | |
3386 | ||
3387 | scan_pc += 2; | |
3388 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3389 | ||
3390 | if ((insn & 0xff80) == 0x4700) /* bx <Rm> */ | |
3391 | found_return = 1; | |
3392 | else if (insn == 0x46f7) /* mov pc, lr */ | |
3393 | found_return = 1; | |
540314bd | 3394 | else if (thumb_instruction_restores_sp (insn)) |
4024ca99 | 3395 | { |
b7576e5c | 3396 | if ((insn & 0xff00) == 0xbd00) /* pop <registers, PC> */ |
4024ca99 UW |
3397 | found_return = 1; |
3398 | } | |
db24da6d | 3399 | else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ |
4024ca99 UW |
3400 | { |
3401 | if (target_read_memory (scan_pc, buf, 2)) | |
3402 | break; | |
3403 | ||
3404 | scan_pc += 2; | |
3405 | insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); | |
3406 | ||
3407 | if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3408 | { | |
4024ca99 UW |
3409 | if (insn2 & 0x8000) /* <registers> include PC. */ |
3410 | found_return = 1; | |
3411 | } | |
3412 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3413 | && (insn2 & 0x0fff) == 0x0b04) | |
3414 | { | |
4024ca99 UW |
3415 | if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */ |
3416 | found_return = 1; | |
3417 | } | |
3418 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3419 | && (insn2 & 0x0e00) == 0x0a00) | |
6b65d1b6 | 3420 | ; |
4024ca99 UW |
3421 | else |
3422 | break; | |
3423 | } | |
3424 | else | |
3425 | break; | |
3426 | } | |
3427 | ||
3428 | if (!found_return) | |
3429 | return 0; | |
3430 | ||
3431 | /* Since any instruction in the epilogue sequence, with the possible | |
3432 | exception of return itself, updates the stack pointer, we need to | |
3433 | scan backwards for at most one instruction. Try either a 16-bit or | |
3434 | a 32-bit instruction. This is just a heuristic, so we do not worry | |
0963b4bd | 3435 | too much about false positives. */ |
4024ca99 | 3436 | |
6b65d1b6 YQ |
3437 | if (pc - 4 < func_start) |
3438 | return 0; | |
3439 | if (target_read_memory (pc - 4, buf, 4)) | |
3440 | return 0; | |
4024ca99 | 3441 | |
6b65d1b6 YQ |
3442 | insn = extract_unsigned_integer (buf, 2, byte_order_for_code); |
3443 | insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); | |
3444 | ||
3445 | if (thumb_instruction_restores_sp (insn2)) | |
3446 | found_stack_adjust = 1; | |
3447 | else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */ | |
3448 | found_stack_adjust = 1; | |
3449 | else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */ | |
3450 | && (insn2 & 0x0fff) == 0x0b04) | |
3451 | found_stack_adjust = 1; | |
3452 | else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */ | |
3453 | && (insn2 & 0x0e00) == 0x0a00) | |
3454 | found_stack_adjust = 1; | |
4024ca99 UW |
3455 | |
3456 | return found_stack_adjust; | |
3457 | } | |
3458 | ||
4024ca99 | 3459 | static int |
c58b006a | 3460 | arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) |
4024ca99 UW |
3461 | { |
3462 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3463 | unsigned int insn; | |
f303bc3e | 3464 | int found_return; |
4024ca99 UW |
3465 | CORE_ADDR func_start, func_end; |
3466 | ||
4024ca99 UW |
3467 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
3468 | return 0; | |
3469 | ||
3470 | /* We are in the epilogue if the previous instruction was a stack | |
3471 | adjustment and the next instruction is a possible return (bx, mov | |
3472 | pc, or pop). We could have to scan backwards to find the stack | |
3473 | adjustment, or forwards to find the return, but this is a decent | |
3474 | approximation. First scan forwards. */ | |
3475 | ||
3476 | found_return = 0; | |
3477 | insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3478 | if (bits (insn, 28, 31) != INST_NV) | |
3479 | { | |
3480 | if ((insn & 0x0ffffff0) == 0x012fff10) | |
3481 | /* BX. */ | |
3482 | found_return = 1; | |
3483 | else if ((insn & 0x0ffffff0) == 0x01a0f000) | |
3484 | /* MOV PC. */ | |
3485 | found_return = 1; | |
3486 | else if ((insn & 0x0fff0000) == 0x08bd0000 | |
3487 | && (insn & 0x0000c000) != 0) | |
3488 | /* POP (LDMIA), including PC or LR. */ | |
3489 | found_return = 1; | |
3490 | } | |
3491 | ||
3492 | if (!found_return) | |
3493 | return 0; | |
3494 | ||
3495 | /* Scan backwards. This is just a heuristic, so do not worry about | |
3496 | false positives from mode changes. */ | |
3497 | ||
3498 | if (pc < func_start + 4) | |
3499 | return 0; | |
3500 | ||
3501 | insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); | |
f303bc3e | 3502 | if (arm_instruction_restores_sp (insn)) |
4024ca99 UW |
3503 | return 1; |
3504 | ||
3505 | return 0; | |
3506 | } | |
3507 | ||
c58b006a YQ |
3508 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3509 | ||
3510 | static int | |
3511 | arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3512 | { | |
3513 | if (arm_pc_is_thumb (gdbarch, pc)) | |
3514 | return thumb_stack_frame_destroyed_p (gdbarch, pc); | |
3515 | else | |
3516 | return arm_stack_frame_destroyed_p_1 (gdbarch, pc); | |
3517 | } | |
4024ca99 | 3518 | |
2dd604e7 RE |
3519 | /* When arguments must be pushed onto the stack, they go on in reverse |
3520 | order. The code below implements a FILO (stack) to do this. */ | |
3521 | ||
3522 | struct stack_item | |
3523 | { | |
3524 | int len; | |
3525 | struct stack_item *prev; | |
7c543f7b | 3526 | gdb_byte *data; |
2dd604e7 RE |
3527 | }; |
3528 | ||
3529 | static struct stack_item * | |
df3b6708 | 3530 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2dd604e7 RE |
3531 | { |
3532 | struct stack_item *si; | |
8d749320 | 3533 | si = XNEW (struct stack_item); |
7c543f7b | 3534 | si->data = (gdb_byte *) xmalloc (len); |
2dd604e7 RE |
3535 | si->len = len; |
3536 | si->prev = prev; | |
3537 | memcpy (si->data, contents, len); | |
3538 | return si; | |
3539 | } | |
3540 | ||
3541 | static struct stack_item * | |
3542 | pop_stack_item (struct stack_item *si) | |
3543 | { | |
3544 | struct stack_item *dead = si; | |
3545 | si = si->prev; | |
3546 | xfree (dead->data); | |
3547 | xfree (dead); | |
3548 | return si; | |
3549 | } | |
3550 | ||
030197b4 AB |
3551 | /* Implement the gdbarch type alignment method, overrides the generic |
3552 | alignment algorithm for anything that is arm specific. */ | |
2af48f68 | 3553 | |
030197b4 AB |
3554 | static ULONGEST |
3555 | arm_type_align (gdbarch *gdbarch, struct type *t) | |
2af48f68 | 3556 | { |
2af48f68 | 3557 | t = check_typedef (t); |
bd63c870 | 3558 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
2af48f68 | 3559 | { |
030197b4 AB |
3560 | /* Use the natural alignment for vector types (the same for |
3561 | scalar type), but the maximum alignment is 64-bit. */ | |
3562 | if (TYPE_LENGTH (t) > 8) | |
3563 | return 8; | |
c4312b19 | 3564 | else |
030197b4 | 3565 | return TYPE_LENGTH (t); |
2af48f68 | 3566 | } |
030197b4 AB |
3567 | |
3568 | /* Allow the common code to calculate the alignment. */ | |
3569 | return 0; | |
2af48f68 PB |
3570 | } |
3571 | ||
90445bd3 DJ |
3572 | /* Possible base types for a candidate for passing and returning in |
3573 | VFP registers. */ | |
3574 | ||
3575 | enum arm_vfp_cprc_base_type | |
3576 | { | |
3577 | VFP_CPRC_UNKNOWN, | |
3578 | VFP_CPRC_SINGLE, | |
3579 | VFP_CPRC_DOUBLE, | |
3580 | VFP_CPRC_VEC64, | |
3581 | VFP_CPRC_VEC128 | |
3582 | }; | |
3583 | ||
3584 | /* The length of one element of base type B. */ | |
3585 | ||
3586 | static unsigned | |
3587 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) | |
3588 | { | |
3589 | switch (b) | |
3590 | { | |
3591 | case VFP_CPRC_SINGLE: | |
3592 | return 4; | |
3593 | case VFP_CPRC_DOUBLE: | |
3594 | return 8; | |
3595 | case VFP_CPRC_VEC64: | |
3596 | return 8; | |
3597 | case VFP_CPRC_VEC128: | |
3598 | return 16; | |
3599 | default: | |
3600 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3601 | (int) b); | |
3602 | } | |
3603 | } | |
3604 | ||
3605 | /* The character ('s', 'd' or 'q') for the type of VFP register used | |
3606 | for passing base type B. */ | |
3607 | ||
3608 | static int | |
3609 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) | |
3610 | { | |
3611 | switch (b) | |
3612 | { | |
3613 | case VFP_CPRC_SINGLE: | |
3614 | return 's'; | |
3615 | case VFP_CPRC_DOUBLE: | |
3616 | return 'd'; | |
3617 | case VFP_CPRC_VEC64: | |
3618 | return 'd'; | |
3619 | case VFP_CPRC_VEC128: | |
3620 | return 'q'; | |
3621 | default: | |
3622 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), | |
3623 | (int) b); | |
3624 | } | |
3625 | } | |
3626 | ||
3627 | /* Determine whether T may be part of a candidate for passing and | |
3628 | returning in VFP registers, ignoring the limit on the total number | |
3629 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the | |
3630 | classification of the first valid component found; if it is not | |
3631 | VFP_CPRC_UNKNOWN, all components must have the same classification | |
3632 | as *BASE_TYPE. If it is found that T contains a type not permitted | |
3633 | for passing and returning in VFP registers, a type differently | |
3634 | classified from *BASE_TYPE, or two types differently classified | |
3635 | from each other, return -1, otherwise return the total number of | |
3636 | base-type elements found (possibly 0 in an empty structure or | |
817e0957 YQ |
3637 | array). Vector types are not currently supported, matching the |
3638 | generic AAPCS support. */ | |
90445bd3 DJ |
3639 | |
3640 | static int | |
3641 | arm_vfp_cprc_sub_candidate (struct type *t, | |
3642 | enum arm_vfp_cprc_base_type *base_type) | |
3643 | { | |
3644 | t = check_typedef (t); | |
78134374 | 3645 | switch (t->code ()) |
90445bd3 DJ |
3646 | { |
3647 | case TYPE_CODE_FLT: | |
3648 | switch (TYPE_LENGTH (t)) | |
3649 | { | |
3650 | case 4: | |
3651 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3652 | *base_type = VFP_CPRC_SINGLE; | |
3653 | else if (*base_type != VFP_CPRC_SINGLE) | |
3654 | return -1; | |
3655 | return 1; | |
3656 | ||
3657 | case 8: | |
3658 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3659 | *base_type = VFP_CPRC_DOUBLE; | |
3660 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3661 | return -1; | |
3662 | return 1; | |
3663 | ||
3664 | default: | |
3665 | return -1; | |
3666 | } | |
3667 | break; | |
3668 | ||
817e0957 YQ |
3669 | case TYPE_CODE_COMPLEX: |
3670 | /* Arguments of complex T where T is one of the types float or | |
3671 | double get treated as if they are implemented as: | |
3672 | ||
3673 | struct complexT | |
3674 | { | |
3675 | T real; | |
3676 | T imag; | |
5f52445b YQ |
3677 | }; |
3678 | ||
3679 | */ | |
817e0957 YQ |
3680 | switch (TYPE_LENGTH (t)) |
3681 | { | |
3682 | case 8: | |
3683 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3684 | *base_type = VFP_CPRC_SINGLE; | |
3685 | else if (*base_type != VFP_CPRC_SINGLE) | |
3686 | return -1; | |
3687 | return 2; | |
3688 | ||
3689 | case 16: | |
3690 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3691 | *base_type = VFP_CPRC_DOUBLE; | |
3692 | else if (*base_type != VFP_CPRC_DOUBLE) | |
3693 | return -1; | |
3694 | return 2; | |
3695 | ||
3696 | default: | |
3697 | return -1; | |
3698 | } | |
3699 | break; | |
3700 | ||
90445bd3 DJ |
3701 | case TYPE_CODE_ARRAY: |
3702 | { | |
bd63c870 | 3703 | if (t->is_vector ()) |
90445bd3 | 3704 | { |
c4312b19 YQ |
3705 | /* A 64-bit or 128-bit containerized vector type are VFP |
3706 | CPRCs. */ | |
3707 | switch (TYPE_LENGTH (t)) | |
3708 | { | |
3709 | case 8: | |
3710 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3711 | *base_type = VFP_CPRC_VEC64; | |
3712 | return 1; | |
3713 | case 16: | |
3714 | if (*base_type == VFP_CPRC_UNKNOWN) | |
3715 | *base_type = VFP_CPRC_VEC128; | |
3716 | return 1; | |
3717 | default: | |
3718 | return -1; | |
3719 | } | |
3720 | } | |
3721 | else | |
3722 | { | |
3723 | int count; | |
3724 | unsigned unitlen; | |
3725 | ||
3726 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), | |
3727 | base_type); | |
3728 | if (count == -1) | |
3729 | return -1; | |
3730 | if (TYPE_LENGTH (t) == 0) | |
3731 | { | |
3732 | gdb_assert (count == 0); | |
3733 | return 0; | |
3734 | } | |
3735 | else if (count == 0) | |
3736 | return -1; | |
3737 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3738 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); | |
3739 | return TYPE_LENGTH (t) / unitlen; | |
90445bd3 | 3740 | } |
90445bd3 DJ |
3741 | } |
3742 | break; | |
3743 | ||
3744 | case TYPE_CODE_STRUCT: | |
3745 | { | |
3746 | int count = 0; | |
3747 | unsigned unitlen; | |
3748 | int i; | |
1f704f76 | 3749 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3750 | { |
1040b979 YQ |
3751 | int sub_count = 0; |
3752 | ||
ceacbf6e | 3753 | if (!field_is_static (&t->field (i))) |
940da03e | 3754 | sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
1040b979 | 3755 | base_type); |
90445bd3 DJ |
3756 | if (sub_count == -1) |
3757 | return -1; | |
3758 | count += sub_count; | |
3759 | } | |
3760 | if (TYPE_LENGTH (t) == 0) | |
3761 | { | |
3762 | gdb_assert (count == 0); | |
3763 | return 0; | |
3764 | } | |
3765 | else if (count == 0) | |
3766 | return -1; | |
3767 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3768 | if (TYPE_LENGTH (t) != unitlen * count) | |
3769 | return -1; | |
3770 | return count; | |
3771 | } | |
3772 | ||
3773 | case TYPE_CODE_UNION: | |
3774 | { | |
3775 | int count = 0; | |
3776 | unsigned unitlen; | |
3777 | int i; | |
1f704f76 | 3778 | for (i = 0; i < t->num_fields (); i++) |
90445bd3 | 3779 | { |
940da03e | 3780 | int sub_count = arm_vfp_cprc_sub_candidate (t->field (i).type (), |
90445bd3 DJ |
3781 | base_type); |
3782 | if (sub_count == -1) | |
3783 | return -1; | |
3784 | count = (count > sub_count ? count : sub_count); | |
3785 | } | |
3786 | if (TYPE_LENGTH (t) == 0) | |
3787 | { | |
3788 | gdb_assert (count == 0); | |
3789 | return 0; | |
3790 | } | |
3791 | else if (count == 0) | |
3792 | return -1; | |
3793 | unitlen = arm_vfp_cprc_unit_length (*base_type); | |
3794 | if (TYPE_LENGTH (t) != unitlen * count) | |
3795 | return -1; | |
3796 | return count; | |
3797 | } | |
3798 | ||
3799 | default: | |
3800 | break; | |
3801 | } | |
3802 | ||
3803 | return -1; | |
3804 | } | |
3805 | ||
3806 | /* Determine whether T is a VFP co-processor register candidate (CPRC) | |
3807 | if passed to or returned from a non-variadic function with the VFP | |
3808 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set | |
3809 | *BASE_TYPE to the base type for T and *COUNT to the number of | |
3810 | elements of that base type before returning. */ | |
3811 | ||
3812 | static int | |
3813 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, | |
3814 | int *count) | |
3815 | { | |
3816 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; | |
3817 | int c = arm_vfp_cprc_sub_candidate (t, &b); | |
3818 | if (c <= 0 || c > 4) | |
3819 | return 0; | |
3820 | *base_type = b; | |
3821 | *count = c; | |
3822 | return 1; | |
3823 | } | |
3824 | ||
3825 | /* Return 1 if the VFP ABI should be used for passing arguments to and | |
3826 | returning values from a function of type FUNC_TYPE, 0 | |
3827 | otherwise. */ | |
3828 | ||
3829 | static int | |
3830 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) | |
3831 | { | |
345bd07c SM |
3832 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
3833 | ||
90445bd3 DJ |
3834 | /* Variadic functions always use the base ABI. Assume that functions |
3835 | without debug info are not variadic. */ | |
a409645d | 3836 | if (func_type && check_typedef (func_type)->has_varargs ()) |
90445bd3 | 3837 | return 0; |
345bd07c | 3838 | |
90445bd3 DJ |
3839 | /* The VFP ABI is only supported as a variant of AAPCS. */ |
3840 | if (tdep->arm_abi != ARM_ABI_AAPCS) | |
3841 | return 0; | |
345bd07c SM |
3842 | |
3843 | return tdep->fp_model == ARM_FLOAT_VFP; | |
90445bd3 DJ |
3844 | } |
3845 | ||
3846 | /* We currently only support passing parameters in integer registers, which | |
3847 | conforms with GCC's default model, and VFP argument passing following | |
3848 | the VFP variant of AAPCS. Several other variants exist and | |
2dd604e7 RE |
3849 | we should probably support some of them based on the selected ABI. */ |
3850 | ||
3851 | static CORE_ADDR | |
7d9b040b | 3852 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 3853 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
3854 | struct value **args, CORE_ADDR sp, |
3855 | function_call_return_method return_method, | |
6a65450a | 3856 | CORE_ADDR struct_addr) |
2dd604e7 | 3857 | { |
e17a4113 | 3858 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2dd604e7 RE |
3859 | int argnum; |
3860 | int argreg; | |
3861 | int nstack; | |
3862 | struct stack_item *si = NULL; | |
90445bd3 DJ |
3863 | int use_vfp_abi; |
3864 | struct type *ftype; | |
3865 | unsigned vfp_regs_free = (1 << 16) - 1; | |
345bd07c | 3866 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
90445bd3 DJ |
3867 | |
3868 | /* Determine the type of this function and whether the VFP ABI | |
3869 | applies. */ | |
3870 | ftype = check_typedef (value_type (function)); | |
78134374 | 3871 | if (ftype->code () == TYPE_CODE_PTR) |
90445bd3 DJ |
3872 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
3873 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); | |
2dd604e7 | 3874 | |
6a65450a AC |
3875 | /* Set the return address. For the ARM, the return breakpoint is |
3876 | always at BP_ADDR. */ | |
9779414d | 3877 | if (arm_pc_is_thumb (gdbarch, bp_addr)) |
9dca5578 | 3878 | bp_addr |= 1; |
6a65450a | 3879 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
3880 | |
3881 | /* Walk through the list of args and determine how large a temporary | |
3882 | stack is required. Need to take care here as structs may be | |
7a9dd1b2 | 3883 | passed on the stack, and we have to push them. */ |
2dd604e7 RE |
3884 | nstack = 0; |
3885 | ||
3886 | argreg = ARM_A1_REGNUM; | |
3887 | nstack = 0; | |
3888 | ||
2dd604e7 RE |
3889 | /* The struct_return pointer occupies the first parameter |
3890 | passing register. */ | |
cf84fa6b | 3891 | if (return_method == return_method_struct) |
2dd604e7 | 3892 | { |
7cb6d92a SM |
3893 | arm_debug_printf ("struct return in %s = %s", |
3894 | gdbarch_register_name (gdbarch, argreg), | |
3895 | paddress (gdbarch, struct_addr)); | |
3896 | ||
2dd604e7 RE |
3897 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
3898 | argreg++; | |
3899 | } | |
3900 | ||
3901 | for (argnum = 0; argnum < nargs; argnum++) | |
3902 | { | |
3903 | int len; | |
3904 | struct type *arg_type; | |
3905 | struct type *target_type; | |
3906 | enum type_code typecode; | |
8c6363cf | 3907 | const bfd_byte *val; |
2af48f68 | 3908 | int align; |
90445bd3 DJ |
3909 | enum arm_vfp_cprc_base_type vfp_base_type; |
3910 | int vfp_base_count; | |
3911 | int may_use_core_reg = 1; | |
2dd604e7 | 3912 | |
df407dfe | 3913 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
3914 | len = TYPE_LENGTH (arg_type); |
3915 | target_type = TYPE_TARGET_TYPE (arg_type); | |
78134374 | 3916 | typecode = arg_type->code (); |
50888e42 | 3917 | val = value_contents (args[argnum]).data (); |
2dd604e7 | 3918 | |
030197b4 | 3919 | align = type_align (arg_type); |
2af48f68 | 3920 | /* Round alignment up to a whole number of words. */ |
f0452268 AH |
3921 | align = (align + ARM_INT_REGISTER_SIZE - 1) |
3922 | & ~(ARM_INT_REGISTER_SIZE - 1); | |
2af48f68 | 3923 | /* Different ABIs have different maximum alignments. */ |
345bd07c | 3924 | if (tdep->arm_abi == ARM_ABI_APCS) |
2af48f68 PB |
3925 | { |
3926 | /* The APCS ABI only requires word alignment. */ | |
f0452268 | 3927 | align = ARM_INT_REGISTER_SIZE; |
2af48f68 PB |
3928 | } |
3929 | else | |
3930 | { | |
3931 | /* The AAPCS requires at most doubleword alignment. */ | |
f0452268 AH |
3932 | if (align > ARM_INT_REGISTER_SIZE * 2) |
3933 | align = ARM_INT_REGISTER_SIZE * 2; | |
2af48f68 PB |
3934 | } |
3935 | ||
90445bd3 DJ |
3936 | if (use_vfp_abi |
3937 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, | |
3938 | &vfp_base_count)) | |
3939 | { | |
3940 | int regno; | |
3941 | int unit_length; | |
3942 | int shift; | |
3943 | unsigned mask; | |
3944 | ||
3945 | /* Because this is a CPRC it cannot go in a core register or | |
3946 | cause a core register to be skipped for alignment. | |
3947 | Either it goes in VFP registers and the rest of this loop | |
3948 | iteration is skipped for this argument, or it goes on the | |
3949 | stack (and the stack alignment code is correct for this | |
3950 | case). */ | |
3951 | may_use_core_reg = 0; | |
3952 | ||
3953 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
3954 | shift = unit_length / 4; | |
3955 | mask = (1 << (shift * vfp_base_count)) - 1; | |
3956 | for (regno = 0; regno < 16; regno += shift) | |
3957 | if (((vfp_regs_free >> regno) & mask) == mask) | |
3958 | break; | |
3959 | ||
3960 | if (regno < 16) | |
3961 | { | |
3962 | int reg_char; | |
3963 | int reg_scaled; | |
3964 | int i; | |
3965 | ||
3966 | vfp_regs_free &= ~(mask << regno); | |
3967 | reg_scaled = regno / shift; | |
3968 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
3969 | for (i = 0; i < vfp_base_count; i++) | |
3970 | { | |
3971 | char name_buf[4]; | |
3972 | int regnum; | |
58d6951d DJ |
3973 | if (reg_char == 'q') |
3974 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, | |
90445bd3 | 3975 | val + i * unit_length); |
58d6951d DJ |
3976 | else |
3977 | { | |
8c042590 PM |
3978 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", |
3979 | reg_char, reg_scaled + i); | |
58d6951d DJ |
3980 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
3981 | strlen (name_buf)); | |
b66f5587 | 3982 | regcache->cooked_write (regnum, val + i * unit_length); |
58d6951d | 3983 | } |
90445bd3 DJ |
3984 | } |
3985 | continue; | |
3986 | } | |
3987 | else | |
3988 | { | |
3989 | /* This CPRC could not go in VFP registers, so all VFP | |
3990 | registers are now marked as used. */ | |
3991 | vfp_regs_free = 0; | |
3992 | } | |
3993 | } | |
3994 | ||
85102364 | 3995 | /* Push stack padding for doubleword alignment. */ |
2af48f68 PB |
3996 | if (nstack & (align - 1)) |
3997 | { | |
f0452268 AH |
3998 | si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE); |
3999 | nstack += ARM_INT_REGISTER_SIZE; | |
2af48f68 PB |
4000 | } |
4001 | ||
4002 | /* Doubleword aligned quantities must go in even register pairs. */ | |
90445bd3 DJ |
4003 | if (may_use_core_reg |
4004 | && argreg <= ARM_LAST_ARG_REGNUM | |
f0452268 | 4005 | && align > ARM_INT_REGISTER_SIZE |
2af48f68 PB |
4006 | && argreg & 1) |
4007 | argreg++; | |
4008 | ||
2dd604e7 RE |
4009 | /* If the argument is a pointer to a function, and it is a |
4010 | Thumb function, create a LOCAL copy of the value and set | |
4011 | the THUMB bit in it. */ | |
4012 | if (TYPE_CODE_PTR == typecode | |
4013 | && target_type != NULL | |
78134374 | 4014 | && TYPE_CODE_FUNC == check_typedef (target_type)->code ()) |
2dd604e7 | 4015 | { |
e17a4113 | 4016 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
9779414d | 4017 | if (arm_pc_is_thumb (gdbarch, regval)) |
2dd604e7 | 4018 | { |
224c3ddb | 4019 | bfd_byte *copy = (bfd_byte *) alloca (len); |
8c6363cf | 4020 | store_unsigned_integer (copy, len, byte_order, |
e17a4113 | 4021 | MAKE_THUMB_ADDR (regval)); |
8c6363cf | 4022 | val = copy; |
2dd604e7 RE |
4023 | } |
4024 | } | |
4025 | ||
4026 | /* Copy the argument to general registers or the stack in | |
4027 | register-sized pieces. Large arguments are split between | |
4028 | registers and stack. */ | |
4029 | while (len > 0) | |
4030 | { | |
f0452268 AH |
4031 | int partial_len = len < ARM_INT_REGISTER_SIZE |
4032 | ? len : ARM_INT_REGISTER_SIZE; | |
ef9bd0b8 YQ |
4033 | CORE_ADDR regval |
4034 | = extract_unsigned_integer (val, partial_len, byte_order); | |
2dd604e7 | 4035 | |
90445bd3 | 4036 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
2dd604e7 RE |
4037 | { |
4038 | /* The argument is being passed in a general purpose | |
4039 | register. */ | |
e17a4113 | 4040 | if (byte_order == BFD_ENDIAN_BIG) |
f0452268 | 4041 | regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8; |
7cb6d92a SM |
4042 | |
4043 | arm_debug_printf ("arg %d in %s = 0x%s", argnum, | |
4044 | gdbarch_register_name (gdbarch, argreg), | |
4045 | phex (regval, ARM_INT_REGISTER_SIZE)); | |
4046 | ||
2dd604e7 RE |
4047 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
4048 | argreg++; | |
4049 | } | |
4050 | else | |
4051 | { | |
f0452268 | 4052 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
ef9bd0b8 YQ |
4053 | |
4054 | memset (buf, 0, sizeof (buf)); | |
4055 | store_unsigned_integer (buf, partial_len, byte_order, regval); | |
4056 | ||
2dd604e7 | 4057 | /* Push the arguments onto the stack. */ |
7cb6d92a | 4058 | arm_debug_printf ("arg %d @ sp + %d", argnum, nstack); |
f0452268 AH |
4059 | si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE); |
4060 | nstack += ARM_INT_REGISTER_SIZE; | |
2dd604e7 RE |
4061 | } |
4062 | ||
4063 | len -= partial_len; | |
4064 | val += partial_len; | |
4065 | } | |
4066 | } | |
4067 | /* If we have an odd number of words to push, then decrement the stack | |
4068 | by one word now, so first stack argument will be dword aligned. */ | |
4069 | if (nstack & 4) | |
4070 | sp -= 4; | |
4071 | ||
4072 | while (si) | |
4073 | { | |
4074 | sp -= si->len; | |
4075 | write_memory (sp, si->data, si->len); | |
4076 | si = pop_stack_item (si); | |
4077 | } | |
4078 | ||
4079 | /* Finally, update teh SP register. */ | |
4080 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
4081 | ||
4082 | return sp; | |
4083 | } | |
4084 | ||
f53f0d0b PB |
4085 | |
4086 | /* Always align the frame to an 8-byte boundary. This is required on | |
4087 | some platforms and harmless on the rest. */ | |
4088 | ||
4089 | static CORE_ADDR | |
4090 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
4091 | { | |
4092 | /* Align the stack to eight bytes. */ | |
4093 | return sp & ~ (CORE_ADDR) 7; | |
4094 | } | |
4095 | ||
c906108c | 4096 | static void |
12b27276 | 4097 | print_fpu_flags (struct ui_file *file, int flags) |
c906108c | 4098 | { |
c5aa993b | 4099 | if (flags & (1 << 0)) |
0426ad51 | 4100 | gdb_puts ("IVO ", file); |
c5aa993b | 4101 | if (flags & (1 << 1)) |
0426ad51 | 4102 | gdb_puts ("DVZ ", file); |
c5aa993b | 4103 | if (flags & (1 << 2)) |
0426ad51 | 4104 | gdb_puts ("OFL ", file); |
c5aa993b | 4105 | if (flags & (1 << 3)) |
0426ad51 | 4106 | gdb_puts ("UFL ", file); |
c5aa993b | 4107 | if (flags & (1 << 4)) |
0426ad51 | 4108 | gdb_puts ("INX ", file); |
a11ac3b3 | 4109 | gdb_putc ('\n', file); |
c906108c SS |
4110 | } |
4111 | ||
5e74b15c RE |
4112 | /* Print interesting information about the floating point processor |
4113 | (if present) or emulator. */ | |
34e8f22d | 4114 | static void |
d855c300 | 4115 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 4116 | struct frame_info *frame, const char *args) |
c906108c | 4117 | { |
9c9acae0 | 4118 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
4119 | int type; |
4120 | ||
4121 | type = (status >> 24) & 127; | |
edefbb7c | 4122 | if (status & (1 << 31)) |
6cb06a8c | 4123 | gdb_printf (file, _("Hardware FPU type %d\n"), type); |
edefbb7c | 4124 | else |
6cb06a8c | 4125 | gdb_printf (file, _("Software FPU type %d\n"), type); |
edefbb7c | 4126 | /* i18n: [floating point unit] mask */ |
0426ad51 | 4127 | gdb_puts (_("mask: "), file); |
12b27276 | 4128 | print_fpu_flags (file, status >> 16); |
edefbb7c | 4129 | /* i18n: [floating point unit] flags */ |
0426ad51 | 4130 | gdb_puts (_("flags: "), file); |
12b27276 | 4131 | print_fpu_flags (file, status); |
c906108c SS |
4132 | } |
4133 | ||
27067745 UW |
4134 | /* Construct the ARM extended floating point type. */ |
4135 | static struct type * | |
4136 | arm_ext_type (struct gdbarch *gdbarch) | |
4137 | { | |
345bd07c | 4138 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
27067745 UW |
4139 | |
4140 | if (!tdep->arm_ext_type) | |
4141 | tdep->arm_ext_type | |
e9bb382b | 4142 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
27067745 UW |
4143 | floatformats_arm_ext); |
4144 | ||
4145 | return tdep->arm_ext_type; | |
4146 | } | |
4147 | ||
58d6951d DJ |
4148 | static struct type * |
4149 | arm_neon_double_type (struct gdbarch *gdbarch) | |
4150 | { | |
345bd07c | 4151 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d DJ |
4152 | |
4153 | if (tdep->neon_double_type == NULL) | |
4154 | { | |
4155 | struct type *t, *elem; | |
4156 | ||
4157 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", | |
4158 | TYPE_CODE_UNION); | |
4159 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4160 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); | |
4161 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4162 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); | |
4163 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4164 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); | |
4165 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4166 | append_composite_type_field (t, "u64", elem); | |
4167 | elem = builtin_type (gdbarch)->builtin_float; | |
4168 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); | |
4169 | elem = builtin_type (gdbarch)->builtin_double; | |
4170 | append_composite_type_field (t, "f64", elem); | |
4171 | ||
2062087b | 4172 | t->set_is_vector (true); |
d0e39ea2 | 4173 | t->set_name ("neon_d"); |
58d6951d DJ |
4174 | tdep->neon_double_type = t; |
4175 | } | |
4176 | ||
4177 | return tdep->neon_double_type; | |
4178 | } | |
4179 | ||
4180 | /* FIXME: The vector types are not correctly ordered on big-endian | |
4181 | targets. Just as s0 is the low bits of d0, d0[0] is also the low | |
4182 | bits of d0 - regardless of what unit size is being held in d0. So | |
4183 | the offset of the first uint8 in d0 is 7, but the offset of the | |
4184 | first float is 4. This code works as-is for little-endian | |
4185 | targets. */ | |
4186 | ||
4187 | static struct type * | |
4188 | arm_neon_quad_type (struct gdbarch *gdbarch) | |
4189 | { | |
345bd07c | 4190 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d DJ |
4191 | |
4192 | if (tdep->neon_quad_type == NULL) | |
4193 | { | |
4194 | struct type *t, *elem; | |
4195 | ||
4196 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", | |
4197 | TYPE_CODE_UNION); | |
4198 | elem = builtin_type (gdbarch)->builtin_uint8; | |
4199 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); | |
4200 | elem = builtin_type (gdbarch)->builtin_uint16; | |
4201 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); | |
4202 | elem = builtin_type (gdbarch)->builtin_uint32; | |
4203 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); | |
4204 | elem = builtin_type (gdbarch)->builtin_uint64; | |
4205 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); | |
4206 | elem = builtin_type (gdbarch)->builtin_float; | |
4207 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); | |
4208 | elem = builtin_type (gdbarch)->builtin_double; | |
4209 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); | |
4210 | ||
2062087b | 4211 | t->set_is_vector (true); |
d0e39ea2 | 4212 | t->set_name ("neon_q"); |
58d6951d DJ |
4213 | tdep->neon_quad_type = t; |
4214 | } | |
4215 | ||
4216 | return tdep->neon_quad_type; | |
4217 | } | |
4218 | ||
ecbf5d4f LM |
4219 | /* Return true if REGNUM is a Q pseudo register. Return false |
4220 | otherwise. | |
4221 | ||
4222 | REGNUM is the raw register number and not a pseudo-relative register | |
4223 | number. */ | |
4224 | ||
4225 | static bool | |
4226 | is_q_pseudo (struct gdbarch *gdbarch, int regnum) | |
4227 | { | |
345bd07c | 4228 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
ecbf5d4f | 4229 | |
ae66a8f1 SP |
4230 | /* Q pseudo registers are available for both NEON (Q0~Q15) and |
4231 | MVE (Q0~Q7) features. */ | |
ecbf5d4f LM |
4232 | if (tdep->have_q_pseudos |
4233 | && regnum >= tdep->q_pseudo_base | |
4234 | && regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count)) | |
4235 | return true; | |
4236 | ||
4237 | return false; | |
4238 | } | |
4239 | ||
4240 | /* Return true if REGNUM is a VFP S pseudo register. Return false | |
4241 | otherwise. | |
4242 | ||
4243 | REGNUM is the raw register number and not a pseudo-relative register | |
4244 | number. */ | |
4245 | ||
4246 | static bool | |
4247 | is_s_pseudo (struct gdbarch *gdbarch, int regnum) | |
4248 | { | |
345bd07c | 4249 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
ecbf5d4f LM |
4250 | |
4251 | if (tdep->have_s_pseudos | |
4252 | && regnum >= tdep->s_pseudo_base | |
4253 | && regnum < (tdep->s_pseudo_base + tdep->s_pseudo_count)) | |
4254 | return true; | |
4255 | ||
4256 | return false; | |
4257 | } | |
4258 | ||
ae66a8f1 SP |
4259 | /* Return true if REGNUM is a MVE pseudo register (P0). Return false |
4260 | otherwise. | |
4261 | ||
4262 | REGNUM is the raw register number and not a pseudo-relative register | |
4263 | number. */ | |
4264 | ||
4265 | static bool | |
4266 | is_mve_pseudo (struct gdbarch *gdbarch, int regnum) | |
4267 | { | |
345bd07c | 4268 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
ae66a8f1 SP |
4269 | |
4270 | if (tdep->have_mve | |
4271 | && regnum >= tdep->mve_pseudo_base | |
4272 | && regnum < tdep->mve_pseudo_base + tdep->mve_pseudo_count) | |
4273 | return true; | |
4274 | ||
4275 | return false; | |
4276 | } | |
4277 | ||
a01567f4 LM |
4278 | /* Return true if REGNUM is a PACBTI pseudo register (ra_auth_code). Return |
4279 | false otherwise. | |
4280 | ||
4281 | REGNUM is the raw register number and not a pseudo-relative register | |
4282 | number. */ | |
4283 | ||
4284 | static bool | |
4285 | is_pacbti_pseudo (struct gdbarch *gdbarch, int regnum) | |
4286 | { | |
4287 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); | |
4288 | ||
4289 | if (tdep->have_pacbti | |
4290 | && regnum >= tdep->pacbti_pseudo_base | |
4291 | && regnum < tdep->pacbti_pseudo_base + tdep->pacbti_pseudo_count) | |
4292 | return true; | |
4293 | ||
4294 | return false; | |
4295 | } | |
4296 | ||
34e8f22d RE |
4297 | /* Return the GDB type object for the "standard" data type of data in |
4298 | register N. */ | |
4299 | ||
4300 | static struct type * | |
7a5ea0d4 | 4301 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 4302 | { |
345bd07c | 4303 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d | 4304 | |
ecbf5d4f | 4305 | if (is_s_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4306 | return builtin_type (gdbarch)->builtin_float; |
4307 | ||
ecbf5d4f | 4308 | if (is_q_pseudo (gdbarch, regnum)) |
58d6951d DJ |
4309 | return arm_neon_quad_type (gdbarch); |
4310 | ||
ae66a8f1 SP |
4311 | if (is_mve_pseudo (gdbarch, regnum)) |
4312 | return builtin_type (gdbarch)->builtin_int16; | |
4313 | ||
a01567f4 LM |
4314 | if (is_pacbti_pseudo (gdbarch, regnum)) |
4315 | return builtin_type (gdbarch)->builtin_uint32; | |
4316 | ||
58d6951d DJ |
4317 | /* If the target description has register information, we are only |
4318 | in this function so that we can override the types of | |
4319 | double-precision registers for NEON. */ | |
4320 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
4321 | { | |
4322 | struct type *t = tdesc_register_type (gdbarch, regnum); | |
4323 | ||
4324 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 | |
78134374 | 4325 | && t->code () == TYPE_CODE_FLT |
ecbf5d4f | 4326 | && tdep->have_neon) |
58d6951d DJ |
4327 | return arm_neon_double_type (gdbarch); |
4328 | else | |
4329 | return t; | |
4330 | } | |
4331 | ||
34e8f22d | 4332 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
58d6951d | 4333 | { |
ecbf5d4f | 4334 | if (!tdep->have_fpa_registers) |
58d6951d DJ |
4335 | return builtin_type (gdbarch)->builtin_void; |
4336 | ||
4337 | return arm_ext_type (gdbarch); | |
4338 | } | |
e4c16157 | 4339 | else if (regnum == ARM_SP_REGNUM) |
0dfff4cb | 4340 | return builtin_type (gdbarch)->builtin_data_ptr; |
e4c16157 | 4341 | else if (regnum == ARM_PC_REGNUM) |
0dfff4cb | 4342 | return builtin_type (gdbarch)->builtin_func_ptr; |
ff6f572f DJ |
4343 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
4344 | /* These registers are only supported on targets which supply | |
4345 | an XML description. */ | |
df4df182 | 4346 | return builtin_type (gdbarch)->builtin_int0; |
032758dc | 4347 | else |
df4df182 | 4348 | return builtin_type (gdbarch)->builtin_uint32; |
032758dc AC |
4349 | } |
4350 | ||
ff6f572f DJ |
4351 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
4352 | number. */ | |
4353 | ||
4354 | static int | |
d3f73121 | 4355 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
4356 | { |
4357 | /* Core integer regs. */ | |
4358 | if (reg >= 0 && reg <= 15) | |
4359 | return reg; | |
4360 | ||
4361 | /* Legacy FPA encoding. These were once used in a way which | |
4362 | overlapped with VFP register numbering, so their use is | |
4363 | discouraged, but GDB doesn't support the ARM toolchain | |
4364 | which used them for VFP. */ | |
4365 | if (reg >= 16 && reg <= 23) | |
4366 | return ARM_F0_REGNUM + reg - 16; | |
4367 | ||
4368 | /* New assignments for the FPA registers. */ | |
4369 | if (reg >= 96 && reg <= 103) | |
4370 | return ARM_F0_REGNUM + reg - 96; | |
4371 | ||
4372 | /* WMMX register assignments. */ | |
4373 | if (reg >= 104 && reg <= 111) | |
4374 | return ARM_WCGR0_REGNUM + reg - 104; | |
4375 | ||
4376 | if (reg >= 112 && reg <= 127) | |
4377 | return ARM_WR0_REGNUM + reg - 112; | |
4378 | ||
a01567f4 LM |
4379 | /* PACBTI register containing the Pointer Authentication Code. */ |
4380 | if (reg == ARM_DWARF_RA_AUTH_CODE) | |
4381 | { | |
4382 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); | |
4383 | ||
4384 | if (tdep->have_pacbti) | |
4385 | return tdep->pacbti_pseudo_base; | |
4386 | ||
4387 | return -1; | |
4388 | } | |
4389 | ||
ff6f572f DJ |
4390 | if (reg >= 192 && reg <= 199) |
4391 | return ARM_WC0_REGNUM + reg - 192; | |
4392 | ||
58d6951d DJ |
4393 | /* VFP v2 registers. A double precision value is actually |
4394 | in d1 rather than s2, but the ABI only defines numbering | |
4395 | for the single precision registers. This will "just work" | |
4396 | in GDB for little endian targets (we'll read eight bytes, | |
4397 | starting in s0 and then progressing to s1), but will be | |
4398 | reversed on big endian targets with VFP. This won't | |
4399 | be a problem for the new Neon quad registers; you're supposed | |
4400 | to use DW_OP_piece for those. */ | |
4401 | if (reg >= 64 && reg <= 95) | |
4402 | { | |
4403 | char name_buf[4]; | |
4404 | ||
8c042590 | 4405 | xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); |
58d6951d DJ |
4406 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4407 | strlen (name_buf)); | |
4408 | } | |
4409 | ||
4410 | /* VFP v3 / Neon registers. This range is also used for VFP v2 | |
4411 | registers, except that it now describes d0 instead of s0. */ | |
4412 | if (reg >= 256 && reg <= 287) | |
4413 | { | |
4414 | char name_buf[4]; | |
4415 | ||
8c042590 | 4416 | xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); |
58d6951d DJ |
4417 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
4418 | strlen (name_buf)); | |
4419 | } | |
4420 | ||
ff6f572f DJ |
4421 | return -1; |
4422 | } | |
4423 | ||
26216b98 AC |
4424 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
4425 | static int | |
e7faf938 | 4426 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
4427 | { |
4428 | int reg = regnum; | |
e7faf938 | 4429 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 4430 | |
ff6f572f DJ |
4431 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
4432 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
4433 | ||
4434 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
4435 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
4436 | ||
4437 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
4438 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
4439 | ||
26216b98 AC |
4440 | if (reg < NUM_GREGS) |
4441 | return SIM_ARM_R0_REGNUM + reg; | |
4442 | reg -= NUM_GREGS; | |
4443 | ||
4444 | if (reg < NUM_FREGS) | |
4445 | return SIM_ARM_FP0_REGNUM + reg; | |
4446 | reg -= NUM_FREGS; | |
4447 | ||
4448 | if (reg < NUM_SREGS) | |
4449 | return SIM_ARM_FPS_REGNUM + reg; | |
4450 | reg -= NUM_SREGS; | |
4451 | ||
edefbb7c | 4452 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 4453 | } |
34e8f22d | 4454 | |
a01567f4 LM |
4455 | static const unsigned char op_lit0 = DW_OP_lit0; |
4456 | ||
4457 | static void | |
4458 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
4459 | struct dwarf2_frame_state_reg *reg, | |
4460 | struct frame_info *this_frame) | |
4461 | { | |
4462 | if (is_pacbti_pseudo (gdbarch, regnum)) | |
4463 | { | |
4464 | /* Initialize RA_AUTH_CODE to zero. */ | |
4465 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
4466 | reg->loc.exp.start = &op_lit0; | |
4467 | reg->loc.exp.len = 1; | |
4468 | return; | |
4469 | } | |
4470 | ||
4471 | switch (regnum) | |
4472 | { | |
4473 | case ARM_PC_REGNUM: | |
4474 | case ARM_PS_REGNUM: | |
4475 | reg->how = DWARF2_FRAME_REG_FN; | |
4476 | reg->loc.fn = arm_dwarf2_prev_register; | |
4477 | break; | |
4478 | case ARM_SP_REGNUM: | |
4479 | reg->how = DWARF2_FRAME_REG_CFA; | |
4480 | break; | |
4481 | } | |
4482 | } | |
4483 | ||
d9311bfa AT |
4484 | /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand |
4485 | the buffer to be NEW_LEN bytes ending at ENDADDR. Return | |
4486 | NULL if an error occurs. BUF is freed. */ | |
c906108c | 4487 | |
d9311bfa AT |
4488 | static gdb_byte * |
4489 | extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, | |
4490 | int old_len, int new_len) | |
4491 | { | |
4492 | gdb_byte *new_buf; | |
4493 | int bytes_to_read = new_len - old_len; | |
c906108c | 4494 | |
d9311bfa AT |
4495 | new_buf = (gdb_byte *) xmalloc (new_len); |
4496 | memcpy (new_buf + bytes_to_read, buf, old_len); | |
4497 | xfree (buf); | |
198cd59d | 4498 | if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) |
d9311bfa AT |
4499 | { |
4500 | xfree (new_buf); | |
4501 | return NULL; | |
c906108c | 4502 | } |
d9311bfa | 4503 | return new_buf; |
c906108c SS |
4504 | } |
4505 | ||
d9311bfa AT |
4506 | /* An IT block is at most the 2-byte IT instruction followed by |
4507 | four 4-byte instructions. The furthest back we must search to | |
4508 | find an IT block that affects the current instruction is thus | |
4509 | 2 + 3 * 4 == 14 bytes. */ | |
4510 | #define MAX_IT_BLOCK_PREFIX 14 | |
177321bd | 4511 | |
d9311bfa AT |
4512 | /* Use a quick scan if there are more than this many bytes of |
4513 | code. */ | |
4514 | #define IT_SCAN_THRESHOLD 32 | |
177321bd | 4515 | |
d9311bfa AT |
4516 | /* Adjust a breakpoint's address to move breakpoints out of IT blocks. |
4517 | A breakpoint in an IT block may not be hit, depending on the | |
4518 | condition flags. */ | |
ad527d2e | 4519 | static CORE_ADDR |
d9311bfa | 4520 | arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
c906108c | 4521 | { |
d9311bfa AT |
4522 | gdb_byte *buf; |
4523 | char map_type; | |
4524 | CORE_ADDR boundary, func_start; | |
4525 | int buf_len; | |
4526 | enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); | |
4527 | int i, any, last_it, last_it_count; | |
345bd07c | 4528 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
177321bd | 4529 | |
d9311bfa | 4530 | /* If we are using BKPT breakpoints, none of this is necessary. */ |
345bd07c | 4531 | if (tdep->thumb2_breakpoint == NULL) |
d9311bfa | 4532 | return bpaddr; |
177321bd | 4533 | |
d9311bfa AT |
4534 | /* ARM mode does not have this problem. */ |
4535 | if (!arm_pc_is_thumb (gdbarch, bpaddr)) | |
4536 | return bpaddr; | |
177321bd | 4537 | |
d9311bfa AT |
4538 | /* We are setting a breakpoint in Thumb code that could potentially |
4539 | contain an IT block. The first step is to find how much Thumb | |
4540 | code there is; we do not need to read outside of known Thumb | |
4541 | sequences. */ | |
4542 | map_type = arm_find_mapping_symbol (bpaddr, &boundary); | |
4543 | if (map_type == 0) | |
4544 | /* Thumb-2 code must have mapping symbols to have a chance. */ | |
4545 | return bpaddr; | |
9dca5578 | 4546 | |
d9311bfa | 4547 | bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); |
177321bd | 4548 | |
d9311bfa AT |
4549 | if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) |
4550 | && func_start > boundary) | |
4551 | boundary = func_start; | |
9dca5578 | 4552 | |
d9311bfa AT |
4553 | /* Search for a candidate IT instruction. We have to do some fancy |
4554 | footwork to distinguish a real IT instruction from the second | |
4555 | half of a 32-bit instruction, but there is no need for that if | |
4556 | there's no candidate. */ | |
325fac50 | 4557 | buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); |
d9311bfa AT |
4558 | if (buf_len == 0) |
4559 | /* No room for an IT instruction. */ | |
4560 | return bpaddr; | |
c906108c | 4561 | |
d9311bfa | 4562 | buf = (gdb_byte *) xmalloc (buf_len); |
198cd59d | 4563 | if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) |
d9311bfa AT |
4564 | return bpaddr; |
4565 | any = 0; | |
4566 | for (i = 0; i < buf_len; i += 2) | |
c906108c | 4567 | { |
d9311bfa AT |
4568 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); |
4569 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
25b41d01 | 4570 | { |
d9311bfa AT |
4571 | any = 1; |
4572 | break; | |
25b41d01 | 4573 | } |
c906108c | 4574 | } |
d9311bfa AT |
4575 | |
4576 | if (any == 0) | |
c906108c | 4577 | { |
d9311bfa AT |
4578 | xfree (buf); |
4579 | return bpaddr; | |
f9d67f43 DJ |
4580 | } |
4581 | ||
4582 | /* OK, the code bytes before this instruction contain at least one | |
4583 | halfword which resembles an IT instruction. We know that it's | |
4584 | Thumb code, but there are still two possibilities. Either the | |
4585 | halfword really is an IT instruction, or it is the second half of | |
4586 | a 32-bit Thumb instruction. The only way we can tell is to | |
4587 | scan forwards from a known instruction boundary. */ | |
4588 | if (bpaddr - boundary > IT_SCAN_THRESHOLD) | |
4589 | { | |
4590 | int definite; | |
4591 | ||
4592 | /* There's a lot of code before this instruction. Start with an | |
4593 | optimistic search; it's easy to recognize halfwords that can | |
4594 | not be the start of a 32-bit instruction, and use that to | |
4595 | lock on to the instruction boundaries. */ | |
4596 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); | |
4597 | if (buf == NULL) | |
4598 | return bpaddr; | |
4599 | buf_len = IT_SCAN_THRESHOLD; | |
4600 | ||
4601 | definite = 0; | |
4602 | for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) | |
4603 | { | |
4604 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4605 | if (thumb_insn_size (inst1) == 2) | |
4606 | { | |
4607 | definite = 1; | |
4608 | break; | |
4609 | } | |
4610 | } | |
4611 | ||
4612 | /* At this point, if DEFINITE, BUF[I] is the first place we | |
4613 | are sure that we know the instruction boundaries, and it is far | |
4614 | enough from BPADDR that we could not miss an IT instruction | |
4615 | affecting BPADDR. If ! DEFINITE, give up - start from a | |
4616 | known boundary. */ | |
4617 | if (! definite) | |
4618 | { | |
0963b4bd MS |
4619 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, |
4620 | bpaddr - boundary); | |
f9d67f43 DJ |
4621 | if (buf == NULL) |
4622 | return bpaddr; | |
4623 | buf_len = bpaddr - boundary; | |
4624 | i = 0; | |
4625 | } | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); | |
4630 | if (buf == NULL) | |
4631 | return bpaddr; | |
4632 | buf_len = bpaddr - boundary; | |
4633 | i = 0; | |
4634 | } | |
4635 | ||
4636 | /* Scan forwards. Find the last IT instruction before BPADDR. */ | |
4637 | last_it = -1; | |
4638 | last_it_count = 0; | |
4639 | while (i < buf_len) | |
4640 | { | |
4641 | unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); | |
4642 | last_it_count--; | |
4643 | if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) | |
4644 | { | |
4645 | last_it = i; | |
4646 | if (inst1 & 0x0001) | |
4647 | last_it_count = 4; | |
4648 | else if (inst1 & 0x0002) | |
4649 | last_it_count = 3; | |
4650 | else if (inst1 & 0x0004) | |
4651 | last_it_count = 2; | |
4652 | else | |
4653 | last_it_count = 1; | |
4654 | } | |
4655 | i += thumb_insn_size (inst1); | |
4656 | } | |
4657 | ||
4658 | xfree (buf); | |
4659 | ||
4660 | if (last_it == -1) | |
4661 | /* There wasn't really an IT instruction after all. */ | |
4662 | return bpaddr; | |
4663 | ||
4664 | if (last_it_count < 1) | |
4665 | /* It was too far away. */ | |
4666 | return bpaddr; | |
4667 | ||
4668 | /* This really is a trouble spot. Move the breakpoint to the IT | |
4669 | instruction. */ | |
4670 | return bpaddr - buf_len + last_it; | |
4671 | } | |
4672 | ||
cca44b1b | 4673 | /* ARM displaced stepping support. |
c906108c | 4674 | |
cca44b1b | 4675 | Generally ARM displaced stepping works as follows: |
c906108c | 4676 | |
cca44b1b | 4677 | 1. When an instruction is to be single-stepped, it is first decoded by |
2ba163c8 SM |
4678 | arm_process_displaced_insn. Depending on the type of instruction, it is |
4679 | then copied to a scratch location, possibly in a modified form. The | |
4680 | copy_* set of functions performs such modification, as necessary. A | |
4681 | breakpoint is placed after the modified instruction in the scratch space | |
4682 | to return control to GDB. Note in particular that instructions which | |
4683 | modify the PC will no longer do so after modification. | |
c5aa993b | 4684 | |
cca44b1b JB |
4685 | 2. The instruction is single-stepped, by setting the PC to the scratch |
4686 | location address, and resuming. Control returns to GDB when the | |
4687 | breakpoint is hit. | |
c5aa993b | 4688 | |
cca44b1b JB |
4689 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
4690 | function used for the current instruction. This function's job is to | |
4691 | put the CPU/memory state back to what it would have been if the | |
4692 | instruction had been executed unmodified in its original location. */ | |
c5aa993b | 4693 | |
cca44b1b JB |
4694 | /* NOP instruction (mov r0, r0). */ |
4695 | #define ARM_NOP 0xe1a00000 | |
34518530 | 4696 | #define THUMB_NOP 0x4600 |
cca44b1b JB |
4697 | |
4698 | /* Helper for register reads for displaced stepping. In particular, this | |
4699 | returns the PC as it would be seen by the instruction at its original | |
4700 | location. */ | |
4701 | ||
4702 | ULONGEST | |
1152d984 | 4703 | displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4704 | int regno) |
cca44b1b JB |
4705 | { |
4706 | ULONGEST ret; | |
36073a92 | 4707 | CORE_ADDR from = dsc->insn_addr; |
cca44b1b | 4708 | |
bf9f652a | 4709 | if (regno == ARM_PC_REGNUM) |
cca44b1b | 4710 | { |
4db71c0b YQ |
4711 | /* Compute pipeline offset: |
4712 | - When executing an ARM instruction, PC reads as the address of the | |
4713 | current instruction plus 8. | |
4714 | - When executing a Thumb instruction, PC reads as the address of the | |
4715 | current instruction plus 4. */ | |
4716 | ||
36073a92 | 4717 | if (!dsc->is_thumb) |
4db71c0b YQ |
4718 | from += 8; |
4719 | else | |
4720 | from += 4; | |
4721 | ||
136821d9 SM |
4722 | displaced_debug_printf ("read pc value %.8lx", |
4723 | (unsigned long) from); | |
4db71c0b | 4724 | return (ULONGEST) from; |
cca44b1b | 4725 | } |
c906108c | 4726 | else |
cca44b1b JB |
4727 | { |
4728 | regcache_cooked_read_unsigned (regs, regno, &ret); | |
136821d9 SM |
4729 | |
4730 | displaced_debug_printf ("read r%d value %.8lx", | |
4731 | regno, (unsigned long) ret); | |
4732 | ||
cca44b1b JB |
4733 | return ret; |
4734 | } | |
c906108c SS |
4735 | } |
4736 | ||
cca44b1b JB |
4737 | static int |
4738 | displaced_in_arm_mode (struct regcache *regs) | |
4739 | { | |
4740 | ULONGEST ps; | |
ac7936df | 4741 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
66e810cd | 4742 | |
cca44b1b | 4743 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
66e810cd | 4744 | |
9779414d | 4745 | return (ps & t_bit) == 0; |
cca44b1b | 4746 | } |
66e810cd | 4747 | |
cca44b1b | 4748 | /* Write to the PC as from a branch instruction. */ |
c906108c | 4749 | |
cca44b1b | 4750 | static void |
1152d984 | 4751 | branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4752 | ULONGEST val) |
c906108c | 4753 | { |
36073a92 | 4754 | if (!dsc->is_thumb) |
cca44b1b JB |
4755 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
4756 | architecture versions < 6. */ | |
0963b4bd MS |
4757 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4758 | val & ~(ULONGEST) 0x3); | |
cca44b1b | 4759 | else |
0963b4bd MS |
4760 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
4761 | val & ~(ULONGEST) 0x1); | |
cca44b1b | 4762 | } |
66e810cd | 4763 | |
cca44b1b JB |
4764 | /* Write to the PC as from a branch-exchange instruction. */ |
4765 | ||
4766 | static void | |
4767 | bx_write_pc (struct regcache *regs, ULONGEST val) | |
4768 | { | |
4769 | ULONGEST ps; | |
ac7936df | 4770 | ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ()); |
cca44b1b JB |
4771 | |
4772 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); | |
4773 | ||
4774 | if ((val & 1) == 1) | |
c906108c | 4775 | { |
9779414d | 4776 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); |
cca44b1b JB |
4777 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
4778 | } | |
4779 | else if ((val & 2) == 0) | |
4780 | { | |
9779414d | 4781 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4782 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
c906108c SS |
4783 | } |
4784 | else | |
4785 | { | |
cca44b1b JB |
4786 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
4787 | mode, align dest to 4 bytes). */ | |
4788 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); | |
9779414d | 4789 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); |
cca44b1b | 4790 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
c906108c SS |
4791 | } |
4792 | } | |
ed9a39eb | 4793 | |
cca44b1b | 4794 | /* Write to the PC as if from a load instruction. */ |
ed9a39eb | 4795 | |
34e8f22d | 4796 | static void |
1152d984 | 4797 | load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4798 | ULONGEST val) |
ed9a39eb | 4799 | { |
cca44b1b JB |
4800 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
4801 | bx_write_pc (regs, val); | |
4802 | else | |
36073a92 | 4803 | branch_write_pc (regs, dsc, val); |
cca44b1b | 4804 | } |
be8626e0 | 4805 | |
cca44b1b JB |
4806 | /* Write to the PC as if from an ALU instruction. */ |
4807 | ||
4808 | static void | |
1152d984 | 4809 | alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
36073a92 | 4810 | ULONGEST val) |
cca44b1b | 4811 | { |
36073a92 | 4812 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb) |
cca44b1b JB |
4813 | bx_write_pc (regs, val); |
4814 | else | |
36073a92 | 4815 | branch_write_pc (regs, dsc, val); |
cca44b1b JB |
4816 | } |
4817 | ||
4818 | /* Helper for writing to registers for displaced stepping. Writing to the PC | |
4819 | has a varying effects depending on the instruction which does the write: | |
4820 | this is controlled by the WRITE_PC argument. */ | |
4821 | ||
4822 | void | |
1152d984 | 4823 | displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, |
cca44b1b JB |
4824 | int regno, ULONGEST val, enum pc_write_style write_pc) |
4825 | { | |
bf9f652a | 4826 | if (regno == ARM_PC_REGNUM) |
08216dd7 | 4827 | { |
136821d9 SM |
4828 | displaced_debug_printf ("writing pc %.8lx", (unsigned long) val); |
4829 | ||
cca44b1b | 4830 | switch (write_pc) |
08216dd7 | 4831 | { |
cca44b1b | 4832 | case BRANCH_WRITE_PC: |
36073a92 | 4833 | branch_write_pc (regs, dsc, val); |
08216dd7 RE |
4834 | break; |
4835 | ||
cca44b1b JB |
4836 | case BX_WRITE_PC: |
4837 | bx_write_pc (regs, val); | |
24b21115 | 4838 | break; |
cca44b1b JB |
4839 | |
4840 | case LOAD_WRITE_PC: | |
36073a92 | 4841 | load_write_pc (regs, dsc, val); |
24b21115 | 4842 | break; |
cca44b1b JB |
4843 | |
4844 | case ALU_WRITE_PC: | |
36073a92 | 4845 | alu_write_pc (regs, dsc, val); |
24b21115 | 4846 | break; |
cca44b1b JB |
4847 | |
4848 | case CANNOT_WRITE_PC: | |
4849 | warning (_("Instruction wrote to PC in an unexpected way when " | |
4850 | "single-stepping")); | |
08216dd7 RE |
4851 | break; |
4852 | ||
4853 | default: | |
97b9747c JB |
4854 | internal_error (__FILE__, __LINE__, |
4855 | _("Invalid argument to displaced_write_reg")); | |
08216dd7 | 4856 | } |
b508a996 | 4857 | |
cca44b1b | 4858 | dsc->wrote_to_pc = 1; |
b508a996 | 4859 | } |
ed9a39eb | 4860 | else |
b508a996 | 4861 | { |
136821d9 SM |
4862 | displaced_debug_printf ("writing r%d value %.8lx", |
4863 | regno, (unsigned long) val); | |
cca44b1b | 4864 | regcache_cooked_write_unsigned (regs, regno, val); |
b508a996 | 4865 | } |
34e8f22d RE |
4866 | } |
4867 | ||
cca44b1b JB |
4868 | /* This function is used to concisely determine if an instruction INSN |
4869 | references PC. Register fields of interest in INSN should have the | |
0963b4bd MS |
4870 | corresponding fields of BITMASK set to 0b1111. The function |
4871 | returns return 1 if any of these fields in INSN reference the PC | |
4872 | (also 0b1111, r15), else it returns 0. */ | |
67255d04 RE |
4873 | |
4874 | static int | |
cca44b1b | 4875 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
67255d04 | 4876 | { |
cca44b1b | 4877 | uint32_t lowbit = 1; |
67255d04 | 4878 | |
cca44b1b JB |
4879 | while (bitmask != 0) |
4880 | { | |
4881 | uint32_t mask; | |
44e1a9eb | 4882 | |
cca44b1b JB |
4883 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
4884 | ; | |
67255d04 | 4885 | |
cca44b1b JB |
4886 | if (!lowbit) |
4887 | break; | |
67255d04 | 4888 | |
cca44b1b | 4889 | mask = lowbit * 0xf; |
67255d04 | 4890 | |
cca44b1b JB |
4891 | if ((insn & mask) == mask) |
4892 | return 1; | |
4893 | ||
4894 | bitmask &= ~mask; | |
67255d04 RE |
4895 | } |
4896 | ||
cca44b1b JB |
4897 | return 0; |
4898 | } | |
2af48f68 | 4899 | |
cca44b1b JB |
4900 | /* The simplest copy function. Many instructions have the same effect no |
4901 | matter what address they are executed at: in those cases, use this. */ | |
67255d04 | 4902 | |
cca44b1b | 4903 | static int |
1152d984 SM |
4904 | arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, |
4905 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 4906 | { |
136821d9 SM |
4907 | displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified", |
4908 | (unsigned long) insn, iname); | |
67255d04 | 4909 | |
cca44b1b | 4910 | dsc->modinsn[0] = insn; |
67255d04 | 4911 | |
cca44b1b JB |
4912 | return 0; |
4913 | } | |
4914 | ||
34518530 YQ |
4915 | static int |
4916 | thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
4917 | uint16_t insn2, const char *iname, | |
1152d984 | 4918 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4919 | { |
136821d9 SM |
4920 | displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' " |
4921 | "unmodified", insn1, insn2, iname); | |
34518530 YQ |
4922 | |
4923 | dsc->modinsn[0] = insn1; | |
4924 | dsc->modinsn[1] = insn2; | |
4925 | dsc->numinsns = 2; | |
4926 | ||
4927 | return 0; | |
4928 | } | |
4929 | ||
4930 | /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any | |
4931 | modification. */ | |
4932 | static int | |
615234c1 | 4933 | thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, |
34518530 | 4934 | const char *iname, |
1152d984 | 4935 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 4936 | { |
136821d9 SM |
4937 | displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified", |
4938 | insn, iname); | |
34518530 YQ |
4939 | |
4940 | dsc->modinsn[0] = insn; | |
4941 | ||
4942 | return 0; | |
4943 | } | |
4944 | ||
cca44b1b JB |
4945 | /* Preload instructions with immediate offset. */ |
4946 | ||
4947 | static void | |
1152d984 SM |
4948 | cleanup_preload (struct gdbarch *gdbarch, regcache *regs, |
4949 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b JB |
4950 | { |
4951 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
4952 | if (!dsc->u.preload.immed) | |
4953 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
4954 | } | |
4955 | ||
7ff120b4 YQ |
4956 | static void |
4957 | install_preload (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 4958 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn) |
cca44b1b | 4959 | { |
cca44b1b | 4960 | ULONGEST rn_val; |
cca44b1b JB |
4961 | /* Preload instructions: |
4962 | ||
4963 | {pli/pld} [rn, #+/-imm] | |
4964 | -> | |
4965 | {pli/pld} [r0, #+/-imm]. */ | |
4966 | ||
36073a92 YQ |
4967 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
4968 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 4969 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
cca44b1b JB |
4970 | dsc->u.preload.immed = 1; |
4971 | ||
cca44b1b | 4972 | dsc->cleanup = &cleanup_preload; |
cca44b1b JB |
4973 | } |
4974 | ||
cca44b1b | 4975 | static int |
7ff120b4 | 4976 | arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 4977 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
4978 | { |
4979 | unsigned int rn = bits (insn, 16, 19); | |
cca44b1b | 4980 | |
7ff120b4 YQ |
4981 | if (!insn_references_pc (insn, 0x000f0000ul)) |
4982 | return arm_copy_unmodified (gdbarch, insn, "preload", dsc); | |
cca44b1b | 4983 | |
136821d9 | 4984 | displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn); |
cca44b1b | 4985 | |
7ff120b4 YQ |
4986 | dsc->modinsn[0] = insn & 0xfff0ffff; |
4987 | ||
4988 | install_preload (gdbarch, regs, dsc, rn); | |
4989 | ||
4990 | return 0; | |
4991 | } | |
4992 | ||
34518530 YQ |
4993 | static int |
4994 | thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 4995 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
4996 | { |
4997 | unsigned int rn = bits (insn1, 0, 3); | |
4998 | unsigned int u_bit = bit (insn1, 7); | |
4999 | int imm12 = bits (insn2, 0, 11); | |
5000 | ULONGEST pc_val; | |
5001 | ||
5002 | if (rn != ARM_PC_REGNUM) | |
5003 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc); | |
5004 | ||
5005 | /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and | |
5006 | PLD (literal) Encoding T1. */ | |
136821d9 SM |
5007 | displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x", |
5008 | (unsigned int) dsc->insn_addr, u_bit ? '+' : '-', | |
5009 | imm12); | |
34518530 YQ |
5010 | |
5011 | if (!u_bit) | |
5012 | imm12 = -1 * imm12; | |
5013 | ||
5014 | /* Rewrite instruction {pli/pld} PC imm12 into: | |
5015 | Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12 | |
5016 | ||
5017 | {pli/pld} [r0, r1] | |
5018 | ||
5019 | Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */ | |
5020 | ||
5021 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5022 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5023 | ||
5024 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5025 | ||
5026 | displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC); | |
5027 | displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC); | |
5028 | dsc->u.preload.immed = 0; | |
5029 | ||
5030 | /* {pli/pld} [r0, r1] */ | |
5031 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5032 | dsc->modinsn[1] = 0xf001; | |
5033 | dsc->numinsns = 2; | |
5034 | ||
5035 | dsc->cleanup = &cleanup_preload; | |
5036 | return 0; | |
5037 | } | |
5038 | ||
7ff120b4 YQ |
5039 | /* Preload instructions with register offset. */ |
5040 | ||
5041 | static void | |
5042 | install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5043 | arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, |
7ff120b4 YQ |
5044 | unsigned int rm) |
5045 | { | |
5046 | ULONGEST rn_val, rm_val; | |
5047 | ||
cca44b1b JB |
5048 | /* Preload register-offset instructions: |
5049 | ||
5050 | {pli/pld} [rn, rm {, shift}] | |
5051 | -> | |
5052 | {pli/pld} [r0, r1 {, shift}]. */ | |
5053 | ||
36073a92 YQ |
5054 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5055 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5056 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5057 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5058 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5059 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); | |
cca44b1b JB |
5060 | dsc->u.preload.immed = 0; |
5061 | ||
cca44b1b | 5062 | dsc->cleanup = &cleanup_preload; |
7ff120b4 YQ |
5063 | } |
5064 | ||
5065 | static int | |
5066 | arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5067 | struct regcache *regs, | |
1152d984 | 5068 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5069 | { |
5070 | unsigned int rn = bits (insn, 16, 19); | |
5071 | unsigned int rm = bits (insn, 0, 3); | |
5072 | ||
5073 | ||
5074 | if (!insn_references_pc (insn, 0x000f000ful)) | |
5075 | return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc); | |
5076 | ||
136821d9 SM |
5077 | displaced_debug_printf ("copying preload insn %.8lx", |
5078 | (unsigned long) insn); | |
7ff120b4 YQ |
5079 | |
5080 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; | |
cca44b1b | 5081 | |
7ff120b4 | 5082 | install_preload_reg (gdbarch, regs, dsc, rn, rm); |
cca44b1b JB |
5083 | return 0; |
5084 | } | |
5085 | ||
5086 | /* Copy/cleanup coprocessor load and store instructions. */ | |
5087 | ||
5088 | static void | |
6e39997a | 5089 | cleanup_copro_load_store (struct gdbarch *gdbarch, |
cca44b1b | 5090 | struct regcache *regs, |
1152d984 | 5091 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5092 | { |
36073a92 | 5093 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5094 | |
5095 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5096 | ||
5097 | if (dsc->u.ldst.writeback) | |
5098 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); | |
5099 | } | |
5100 | ||
7ff120b4 YQ |
5101 | static void |
5102 | install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5103 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5104 | int writeback, unsigned int rn) |
cca44b1b | 5105 | { |
cca44b1b | 5106 | ULONGEST rn_val; |
cca44b1b | 5107 | |
cca44b1b JB |
5108 | /* Coprocessor load/store instructions: |
5109 | ||
5110 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) | |
5111 | -> | |
5112 | {stc/stc2} [r0, #+/-imm]. | |
5113 | ||
5114 | ldc/ldc2 are handled identically. */ | |
5115 | ||
36073a92 YQ |
5116 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5117 | rn_val = displaced_read_reg (regs, dsc, rn); | |
2b16b2e3 YQ |
5118 | /* PC should be 4-byte aligned. */ |
5119 | rn_val = rn_val & 0xfffffffc; | |
cca44b1b JB |
5120 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
5121 | ||
7ff120b4 | 5122 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5123 | dsc->u.ldst.rn = rn; |
5124 | ||
7ff120b4 YQ |
5125 | dsc->cleanup = &cleanup_copro_load_store; |
5126 | } | |
5127 | ||
5128 | static int | |
5129 | arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, | |
5130 | struct regcache *regs, | |
1152d984 | 5131 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5132 | { |
5133 | unsigned int rn = bits (insn, 16, 19); | |
5134 | ||
5135 | if (!insn_references_pc (insn, 0x000f0000ul)) | |
5136 | return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc); | |
5137 | ||
136821d9 SM |
5138 | displaced_debug_printf ("copying coprocessor load/store insn %.8lx", |
5139 | (unsigned long) insn); | |
7ff120b4 | 5140 | |
cca44b1b JB |
5141 | dsc->modinsn[0] = insn & 0xfff0ffff; |
5142 | ||
7ff120b4 | 5143 | install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn); |
cca44b1b JB |
5144 | |
5145 | return 0; | |
5146 | } | |
5147 | ||
34518530 YQ |
5148 | static int |
5149 | thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, | |
5150 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5151 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5152 | { |
5153 | unsigned int rn = bits (insn1, 0, 3); | |
5154 | ||
5155 | if (rn != ARM_PC_REGNUM) | |
5156 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
5157 | "copro load/store", dsc); | |
5158 | ||
136821d9 SM |
5159 | displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x", |
5160 | insn1, insn2); | |
34518530 YQ |
5161 | |
5162 | dsc->modinsn[0] = insn1 & 0xfff0; | |
5163 | dsc->modinsn[1] = insn2; | |
5164 | dsc->numinsns = 2; | |
5165 | ||
5166 | /* This function is called for copying instruction LDC/LDC2/VLDR, which | |
5167 | doesn't support writeback, so pass 0. */ | |
5168 | install_copro_load_store (gdbarch, regs, dsc, 0, rn); | |
5169 | ||
5170 | return 0; | |
5171 | } | |
5172 | ||
cca44b1b JB |
5173 | /* Clean up branch instructions (actually perform the branch, by setting |
5174 | PC). */ | |
5175 | ||
5176 | static void | |
6e39997a | 5177 | cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5178 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5179 | { |
36073a92 | 5180 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
5181 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
5182 | enum pc_write_style write_pc = dsc->u.branch.exchange | |
5183 | ? BX_WRITE_PC : BRANCH_WRITE_PC; | |
5184 | ||
5185 | if (!branch_taken) | |
5186 | return; | |
5187 | ||
5188 | if (dsc->u.branch.link) | |
5189 | { | |
8c8dba6d | 5190 | /* The value of LR should be the next insn of current one. In order |
85102364 | 5191 | not to confuse logic handling later insn `bx lr', if current insn mode |
8c8dba6d YQ |
5192 | is Thumb, the bit 0 of LR value should be set to 1. */ |
5193 | ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size; | |
5194 | ||
5195 | if (dsc->is_thumb) | |
5196 | next_insn_addr |= 0x1; | |
5197 | ||
5198 | displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr, | |
5199 | CANNOT_WRITE_PC); | |
cca44b1b JB |
5200 | } |
5201 | ||
bf9f652a | 5202 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); |
cca44b1b JB |
5203 | } |
5204 | ||
5205 | /* Copy B/BL/BLX instructions with immediate destinations. */ | |
5206 | ||
7ff120b4 YQ |
5207 | static void |
5208 | install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5209 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5210 | unsigned int cond, int exchange, int link, long offset) |
5211 | { | |
5212 | /* Implement "BL<cond> <label>" as: | |
5213 | ||
5214 | Preparation: cond <- instruction condition | |
5215 | Insn: mov r0, r0 (nop) | |
5216 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. | |
5217 | ||
5218 | B<cond> similar, but don't set r14 in cleanup. */ | |
5219 | ||
5220 | dsc->u.branch.cond = cond; | |
5221 | dsc->u.branch.link = link; | |
5222 | dsc->u.branch.exchange = exchange; | |
5223 | ||
2b16b2e3 YQ |
5224 | dsc->u.branch.dest = dsc->insn_addr; |
5225 | if (link && exchange) | |
5226 | /* For BLX, offset is computed from the Align (PC, 4). */ | |
5227 | dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc; | |
5228 | ||
7ff120b4 | 5229 | if (dsc->is_thumb) |
2b16b2e3 | 5230 | dsc->u.branch.dest += 4 + offset; |
7ff120b4 | 5231 | else |
2b16b2e3 | 5232 | dsc->u.branch.dest += 8 + offset; |
7ff120b4 YQ |
5233 | |
5234 | dsc->cleanup = &cleanup_branch; | |
5235 | } | |
cca44b1b | 5236 | static int |
7ff120b4 | 5237 | arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 5238 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5239 | { |
5240 | unsigned int cond = bits (insn, 28, 31); | |
5241 | int exchange = (cond == 0xf); | |
5242 | int link = exchange || bit (insn, 24); | |
cca44b1b JB |
5243 | long offset; |
5244 | ||
136821d9 SM |
5245 | displaced_debug_printf ("copying %s immediate insn %.8lx", |
5246 | (exchange) ? "blx" : (link) ? "bl" : "b", | |
5247 | (unsigned long) insn); | |
cca44b1b JB |
5248 | if (exchange) |
5249 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will | |
5250 | then arrange the switch into Thumb mode. */ | |
5251 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; | |
5252 | else | |
5253 | offset = bits (insn, 0, 23) << 2; | |
5254 | ||
5255 | if (bit (offset, 25)) | |
5256 | offset = offset | ~0x3ffffff; | |
5257 | ||
cca44b1b JB |
5258 | dsc->modinsn[0] = ARM_NOP; |
5259 | ||
7ff120b4 | 5260 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); |
cca44b1b JB |
5261 | return 0; |
5262 | } | |
5263 | ||
34518530 YQ |
5264 | static int |
5265 | thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, | |
5266 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5267 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5268 | { |
5269 | int link = bit (insn2, 14); | |
5270 | int exchange = link && !bit (insn2, 12); | |
5271 | int cond = INST_AL; | |
5272 | long offset = 0; | |
5273 | int j1 = bit (insn2, 13); | |
5274 | int j2 = bit (insn2, 11); | |
5275 | int s = sbits (insn1, 10, 10); | |
5276 | int i1 = !(j1 ^ bit (insn1, 10)); | |
5277 | int i2 = !(j2 ^ bit (insn1, 10)); | |
5278 | ||
5279 | if (!link && !exchange) /* B */ | |
5280 | { | |
5281 | offset = (bits (insn2, 0, 10) << 1); | |
5282 | if (bit (insn2, 12)) /* Encoding T4 */ | |
5283 | { | |
5284 | offset |= (bits (insn1, 0, 9) << 12) | |
5285 | | (i2 << 22) | |
5286 | | (i1 << 23) | |
5287 | | (s << 24); | |
5288 | cond = INST_AL; | |
5289 | } | |
5290 | else /* Encoding T3 */ | |
5291 | { | |
5292 | offset |= (bits (insn1, 0, 5) << 12) | |
5293 | | (j1 << 18) | |
5294 | | (j2 << 19) | |
5295 | | (s << 20); | |
5296 | cond = bits (insn1, 6, 9); | |
5297 | } | |
5298 | } | |
5299 | else | |
5300 | { | |
5301 | offset = (bits (insn1, 0, 9) << 12); | |
5302 | offset |= ((i2 << 22) | (i1 << 23) | (s << 24)); | |
5303 | offset |= exchange ? | |
5304 | (bits (insn2, 1, 10) << 2) : (bits (insn2, 0, 10) << 1); | |
5305 | } | |
5306 | ||
136821d9 SM |
5307 | displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx", |
5308 | link ? (exchange) ? "blx" : "bl" : "b", | |
5309 | insn1, insn2, offset); | |
34518530 YQ |
5310 | |
5311 | dsc->modinsn[0] = THUMB_NOP; | |
5312 | ||
5313 | install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset); | |
5314 | return 0; | |
5315 | } | |
5316 | ||
5317 | /* Copy B Thumb instructions. */ | |
5318 | static int | |
615234c1 | 5319 | thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, |
1152d984 | 5320 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5321 | { |
5322 | unsigned int cond = 0; | |
5323 | int offset = 0; | |
5324 | unsigned short bit_12_15 = bits (insn, 12, 15); | |
5325 | CORE_ADDR from = dsc->insn_addr; | |
5326 | ||
5327 | if (bit_12_15 == 0xd) | |
5328 | { | |
5329 | /* offset = SignExtend (imm8:0, 32) */ | |
5330 | offset = sbits ((insn << 1), 0, 8); | |
5331 | cond = bits (insn, 8, 11); | |
5332 | } | |
5333 | else if (bit_12_15 == 0xe) /* Encoding T2 */ | |
5334 | { | |
5335 | offset = sbits ((insn << 1), 0, 11); | |
5336 | cond = INST_AL; | |
5337 | } | |
5338 | ||
136821d9 SM |
5339 | displaced_debug_printf ("copying b immediate insn %.4x with offset %d", |
5340 | insn, offset); | |
34518530 YQ |
5341 | |
5342 | dsc->u.branch.cond = cond; | |
5343 | dsc->u.branch.link = 0; | |
5344 | dsc->u.branch.exchange = 0; | |
5345 | dsc->u.branch.dest = from + 4 + offset; | |
5346 | ||
5347 | dsc->modinsn[0] = THUMB_NOP; | |
5348 | ||
5349 | dsc->cleanup = &cleanup_branch; | |
5350 | ||
5351 | return 0; | |
5352 | } | |
5353 | ||
cca44b1b JB |
5354 | /* Copy BX/BLX with register-specified destinations. */ |
5355 | ||
7ff120b4 YQ |
5356 | static void |
5357 | install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5358 | arm_displaced_step_copy_insn_closure *dsc, int link, |
7ff120b4 | 5359 | unsigned int cond, unsigned int rm) |
cca44b1b | 5360 | { |
cca44b1b JB |
5361 | /* Implement {BX,BLX}<cond> <reg>" as: |
5362 | ||
5363 | Preparation: cond <- instruction condition | |
5364 | Insn: mov r0, r0 (nop) | |
5365 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. | |
5366 | ||
5367 | Don't set r14 in cleanup for BX. */ | |
5368 | ||
36073a92 | 5369 | dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5370 | |
5371 | dsc->u.branch.cond = cond; | |
5372 | dsc->u.branch.link = link; | |
cca44b1b | 5373 | |
7ff120b4 | 5374 | dsc->u.branch.exchange = 1; |
cca44b1b JB |
5375 | |
5376 | dsc->cleanup = &cleanup_branch; | |
7ff120b4 | 5377 | } |
cca44b1b | 5378 | |
7ff120b4 YQ |
5379 | static int |
5380 | arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 5381 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5382 | { |
5383 | unsigned int cond = bits (insn, 28, 31); | |
5384 | /* BX: x12xxx1x | |
5385 | BLX: x12xxx3x. */ | |
5386 | int link = bit (insn, 5); | |
5387 | unsigned int rm = bits (insn, 0, 3); | |
5388 | ||
136821d9 | 5389 | displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn); |
7ff120b4 YQ |
5390 | |
5391 | dsc->modinsn[0] = ARM_NOP; | |
5392 | ||
5393 | install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm); | |
cca44b1b JB |
5394 | return 0; |
5395 | } | |
5396 | ||
34518530 YQ |
5397 | static int |
5398 | thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5399 | struct regcache *regs, | |
1152d984 | 5400 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5401 | { |
5402 | int link = bit (insn, 7); | |
5403 | unsigned int rm = bits (insn, 3, 6); | |
5404 | ||
136821d9 | 5405 | displaced_debug_printf ("copying insn %.4x", (unsigned short) insn); |
34518530 YQ |
5406 | |
5407 | dsc->modinsn[0] = THUMB_NOP; | |
5408 | ||
5409 | install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm); | |
5410 | ||
5411 | return 0; | |
5412 | } | |
5413 | ||
5414 | ||
0963b4bd | 5415 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
cca44b1b JB |
5416 | |
5417 | static void | |
6e39997a | 5418 | cleanup_alu_imm (struct gdbarch *gdbarch, |
1152d984 | 5419 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5420 | { |
36073a92 | 5421 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5422 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
5423 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5424 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5425 | } | |
5426 | ||
5427 | static int | |
7ff120b4 | 5428 | arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
1152d984 | 5429 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5430 | { |
5431 | unsigned int rn = bits (insn, 16, 19); | |
5432 | unsigned int rd = bits (insn, 12, 15); | |
5433 | unsigned int op = bits (insn, 21, 24); | |
5434 | int is_mov = (op == 0xd); | |
5435 | ULONGEST rd_val, rn_val; | |
cca44b1b JB |
5436 | |
5437 | if (!insn_references_pc (insn, 0x000ff000ul)) | |
7ff120b4 | 5438 | return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
cca44b1b | 5439 | |
136821d9 SM |
5440 | displaced_debug_printf ("copying immediate %s insn %.8lx", |
5441 | is_mov ? "move" : "ALU", | |
5442 | (unsigned long) insn); | |
cca44b1b JB |
5443 | |
5444 | /* Instruction is of form: | |
5445 | ||
5446 | <op><cond> rd, [rn,] #imm | |
5447 | ||
5448 | Rewrite as: | |
5449 | ||
5450 | Preparation: tmp1, tmp2 <- r0, r1; | |
5451 | r0, r1 <- rd, rn | |
5452 | Insn: <op><cond> r0, r1, #imm | |
5453 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5454 | */ | |
5455 | ||
36073a92 YQ |
5456 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5457 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5458 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5459 | rd_val = displaced_read_reg (regs, dsc, rd); | |
cca44b1b JB |
5460 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5461 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5462 | dsc->rd = rd; | |
5463 | ||
5464 | if (is_mov) | |
5465 | dsc->modinsn[0] = insn & 0xfff00fff; | |
5466 | else | |
5467 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; | |
5468 | ||
5469 | dsc->cleanup = &cleanup_alu_imm; | |
5470 | ||
5471 | return 0; | |
5472 | } | |
5473 | ||
34518530 YQ |
5474 | static int |
5475 | thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5476 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5477 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
5478 | { |
5479 | unsigned int op = bits (insn1, 5, 8); | |
5480 | unsigned int rn, rm, rd; | |
5481 | ULONGEST rd_val, rn_val; | |
5482 | ||
5483 | rn = bits (insn1, 0, 3); /* Rn */ | |
5484 | rm = bits (insn2, 0, 3); /* Rm */ | |
5485 | rd = bits (insn2, 8, 11); /* Rd */ | |
5486 | ||
5487 | /* This routine is only called for instruction MOV. */ | |
5488 | gdb_assert (op == 0x2 && rn == 0xf); | |
5489 | ||
5490 | if (rm != ARM_PC_REGNUM && rd != ARM_PC_REGNUM) | |
5491 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc); | |
5492 | ||
136821d9 | 5493 | displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1, insn2); |
34518530 YQ |
5494 | |
5495 | /* Instruction is of form: | |
5496 | ||
5497 | <op><cond> rd, [rn,] #imm | |
5498 | ||
5499 | Rewrite as: | |
5500 | ||
5501 | Preparation: tmp1, tmp2 <- r0, r1; | |
5502 | r0, r1 <- rd, rn | |
5503 | Insn: <op><cond> r0, r1, #imm | |
5504 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 | |
5505 | */ | |
5506 | ||
5507 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5508 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5509 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5510 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5511 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); | |
5512 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5513 | dsc->rd = rd; | |
5514 | ||
5515 | dsc->modinsn[0] = insn1; | |
5516 | dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1); | |
5517 | dsc->numinsns = 2; | |
5518 | ||
5519 | dsc->cleanup = &cleanup_alu_imm; | |
5520 | ||
5521 | return 0; | |
5522 | } | |
5523 | ||
cca44b1b JB |
5524 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
5525 | ||
5526 | static void | |
6e39997a | 5527 | cleanup_alu_reg (struct gdbarch *gdbarch, |
1152d984 | 5528 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5529 | { |
5530 | ULONGEST rd_val; | |
5531 | int i; | |
5532 | ||
36073a92 | 5533 | rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5534 | |
5535 | for (i = 0; i < 3; i++) | |
5536 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5537 | ||
5538 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5539 | } | |
5540 | ||
7ff120b4 YQ |
5541 | static void |
5542 | install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5543 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 | 5544 | unsigned int rd, unsigned int rn, unsigned int rm) |
cca44b1b | 5545 | { |
cca44b1b | 5546 | ULONGEST rd_val, rn_val, rm_val; |
cca44b1b | 5547 | |
cca44b1b JB |
5548 | /* Instruction is of form: |
5549 | ||
5550 | <op><cond> rd, [rn,] rm [, <shift>] | |
5551 | ||
5552 | Rewrite as: | |
5553 | ||
5554 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; | |
5555 | r0, r1, r2 <- rd, rn, rm | |
ef713951 | 5556 | Insn: <op><cond> r0, [r1,] r2 [, <shift>] |
cca44b1b JB |
5557 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
5558 | */ | |
5559 | ||
36073a92 YQ |
5560 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5561 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5562 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5563 | rd_val = displaced_read_reg (regs, dsc, rd); | |
5564 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5565 | rm_val = displaced_read_reg (regs, dsc, rm); | |
cca44b1b JB |
5566 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5567 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5568 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5569 | dsc->rd = rd; | |
5570 | ||
7ff120b4 YQ |
5571 | dsc->cleanup = &cleanup_alu_reg; |
5572 | } | |
5573 | ||
5574 | static int | |
5575 | arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, | |
1152d984 | 5576 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5577 | { |
5578 | unsigned int op = bits (insn, 21, 24); | |
5579 | int is_mov = (op == 0xd); | |
5580 | ||
5581 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
5582 | return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc); | |
5583 | ||
136821d9 SM |
5584 | displaced_debug_printf ("copying reg %s insn %.8lx", |
5585 | is_mov ? "move" : "ALU", (unsigned long) insn); | |
7ff120b4 | 5586 | |
cca44b1b JB |
5587 | if (is_mov) |
5588 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; | |
5589 | else | |
5590 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; | |
5591 | ||
7ff120b4 YQ |
5592 | install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19), |
5593 | bits (insn, 0, 3)); | |
cca44b1b JB |
5594 | return 0; |
5595 | } | |
5596 | ||
34518530 YQ |
5597 | static int |
5598 | thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, | |
5599 | struct regcache *regs, | |
1152d984 | 5600 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 | 5601 | { |
ef713951 | 5602 | unsigned rm, rd; |
34518530 | 5603 | |
ef713951 YQ |
5604 | rm = bits (insn, 3, 6); |
5605 | rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); | |
34518530 | 5606 | |
ef713951 | 5607 | if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) |
34518530 YQ |
5608 | return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); |
5609 | ||
136821d9 | 5610 | displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn); |
34518530 | 5611 | |
ef713951 | 5612 | dsc->modinsn[0] = ((insn & 0xff00) | 0x10); |
34518530 | 5613 | |
ef713951 | 5614 | install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); |
34518530 YQ |
5615 | |
5616 | return 0; | |
5617 | } | |
5618 | ||
cca44b1b JB |
5619 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
5620 | ||
5621 | static void | |
6e39997a | 5622 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch, |
cca44b1b | 5623 | struct regcache *regs, |
1152d984 | 5624 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5625 | { |
36073a92 | 5626 | ULONGEST rd_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b JB |
5627 | int i; |
5628 | ||
5629 | for (i = 0; i < 4; i++) | |
5630 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); | |
5631 | ||
5632 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); | |
5633 | } | |
5634 | ||
7ff120b4 YQ |
5635 | static void |
5636 | install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 5637 | arm_displaced_step_copy_insn_closure *dsc, |
7ff120b4 YQ |
5638 | unsigned int rd, unsigned int rn, unsigned int rm, |
5639 | unsigned rs) | |
cca44b1b | 5640 | { |
7ff120b4 | 5641 | int i; |
cca44b1b | 5642 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
cca44b1b | 5643 | |
cca44b1b JB |
5644 | /* Instruction is of form: |
5645 | ||
5646 | <op><cond> rd, [rn,] rm, <shift> rs | |
5647 | ||
5648 | Rewrite as: | |
5649 | ||
5650 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 | |
5651 | r0, r1, r2, r3 <- rd, rn, rm, rs | |
5652 | Insn: <op><cond> r0, r1, r2, <shift> r3 | |
5653 | Cleanup: tmp5 <- r0 | |
5654 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 | |
5655 | rd <- tmp5 | |
5656 | */ | |
5657 | ||
5658 | for (i = 0; i < 4; i++) | |
36073a92 | 5659 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b | 5660 | |
36073a92 YQ |
5661 | rd_val = displaced_read_reg (regs, dsc, rd); |
5662 | rn_val = displaced_read_reg (regs, dsc, rn); | |
5663 | rm_val = displaced_read_reg (regs, dsc, rm); | |
5664 | rs_val = displaced_read_reg (regs, dsc, rs); | |
cca44b1b JB |
5665 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
5666 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); | |
5667 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); | |
5668 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); | |
5669 | dsc->rd = rd; | |
7ff120b4 YQ |
5670 | dsc->cleanup = &cleanup_alu_shifted_reg; |
5671 | } | |
5672 | ||
5673 | static int | |
5674 | arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, | |
5675 | struct regcache *regs, | |
1152d984 | 5676 | arm_displaced_step_copy_insn_closure *dsc) |
7ff120b4 YQ |
5677 | { |
5678 | unsigned int op = bits (insn, 21, 24); | |
5679 | int is_mov = (op == 0xd); | |
5680 | unsigned int rd, rn, rm, rs; | |
5681 | ||
5682 | if (!insn_references_pc (insn, 0x000fff0ful)) | |
5683 | return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); | |
5684 | ||
136821d9 SM |
5685 | displaced_debug_printf ("copying shifted reg %s insn %.8lx", |
5686 | is_mov ? "move" : "ALU", | |
5687 | (unsigned long) insn); | |
7ff120b4 YQ |
5688 | |
5689 | rn = bits (insn, 16, 19); | |
5690 | rm = bits (insn, 0, 3); | |
5691 | rs = bits (insn, 8, 11); | |
5692 | rd = bits (insn, 12, 15); | |
cca44b1b JB |
5693 | |
5694 | if (is_mov) | |
5695 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; | |
5696 | else | |
5697 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; | |
5698 | ||
7ff120b4 | 5699 | install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs); |
cca44b1b JB |
5700 | |
5701 | return 0; | |
5702 | } | |
5703 | ||
5704 | /* Clean up load instructions. */ | |
5705 | ||
5706 | static void | |
6e39997a | 5707 | cleanup_load (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5708 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5709 | { |
5710 | ULONGEST rt_val, rt_val2 = 0, rn_val; | |
cca44b1b | 5711 | |
36073a92 | 5712 | rt_val = displaced_read_reg (regs, dsc, 0); |
cca44b1b | 5713 | if (dsc->u.ldst.xfersize == 8) |
36073a92 YQ |
5714 | rt_val2 = displaced_read_reg (regs, dsc, 1); |
5715 | rn_val = displaced_read_reg (regs, dsc, 2); | |
cca44b1b JB |
5716 | |
5717 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5718 | if (dsc->u.ldst.xfersize > 4) | |
5719 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5720 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5721 | if (!dsc->u.ldst.immed) | |
5722 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5723 | ||
5724 | /* Handle register writeback. */ | |
5725 | if (dsc->u.ldst.writeback) | |
5726 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5727 | /* Put result in right place. */ | |
5728 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); | |
5729 | if (dsc->u.ldst.xfersize == 8) | |
5730 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); | |
5731 | } | |
5732 | ||
5733 | /* Clean up store instructions. */ | |
5734 | ||
5735 | static void | |
6e39997a | 5736 | cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5737 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 5738 | { |
36073a92 | 5739 | ULONGEST rn_val = displaced_read_reg (regs, dsc, 2); |
cca44b1b JB |
5740 | |
5741 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); | |
5742 | if (dsc->u.ldst.xfersize > 4) | |
5743 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); | |
5744 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); | |
5745 | if (!dsc->u.ldst.immed) | |
5746 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); | |
5747 | if (!dsc->u.ldst.restore_r4) | |
5748 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); | |
5749 | ||
5750 | /* Writeback. */ | |
5751 | if (dsc->u.ldst.writeback) | |
5752 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); | |
5753 | } | |
5754 | ||
5755 | /* Copy "extra" load/store instructions. These are halfword/doubleword | |
5756 | transfers, which have a different encoding to byte/word transfers. */ | |
5757 | ||
5758 | static int | |
550dc4e2 | 5759 | arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, |
1152d984 | 5760 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
5761 | { |
5762 | unsigned int op1 = bits (insn, 20, 24); | |
5763 | unsigned int op2 = bits (insn, 5, 6); | |
5764 | unsigned int rt = bits (insn, 12, 15); | |
5765 | unsigned int rn = bits (insn, 16, 19); | |
5766 | unsigned int rm = bits (insn, 0, 3); | |
5767 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; | |
5768 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; | |
5769 | int immed = (op1 & 0x4) != 0; | |
5770 | int opcode; | |
5771 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; | |
cca44b1b JB |
5772 | |
5773 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
7ff120b4 | 5774 | return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
cca44b1b | 5775 | |
136821d9 SM |
5776 | displaced_debug_printf ("copying %sextra load/store insn %.8lx", |
5777 | unprivileged ? "unprivileged " : "", | |
5778 | (unsigned long) insn); | |
cca44b1b JB |
5779 | |
5780 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; | |
5781 | ||
5782 | if (opcode < 0) | |
5783 | internal_error (__FILE__, __LINE__, | |
5784 | _("copy_extra_ld_st: instruction decode error")); | |
5785 | ||
36073a92 YQ |
5786 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5787 | dsc->tmp[1] = displaced_read_reg (regs, dsc, 1); | |
5788 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5789 | if (!immed) |
36073a92 | 5790 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5791 | |
36073a92 | 5792 | rt_val = displaced_read_reg (regs, dsc, rt); |
cca44b1b | 5793 | if (bytesize[opcode] == 8) |
36073a92 YQ |
5794 | rt_val2 = displaced_read_reg (regs, dsc, rt + 1); |
5795 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5796 | if (!immed) |
36073a92 | 5797 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5798 | |
5799 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5800 | if (bytesize[opcode] == 8) | |
5801 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); | |
5802 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5803 | if (!immed) | |
5804 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
5805 | ||
5806 | dsc->rd = rt; | |
5807 | dsc->u.ldst.xfersize = bytesize[opcode]; | |
5808 | dsc->u.ldst.rn = rn; | |
5809 | dsc->u.ldst.immed = immed; | |
5810 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; | |
5811 | dsc->u.ldst.restore_r4 = 0; | |
5812 | ||
5813 | if (immed) | |
5814 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] | |
5815 | -> | |
5816 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ | |
5817 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
5818 | else | |
5819 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] | |
5820 | -> | |
5821 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ | |
5822 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
5823 | ||
5824 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; | |
5825 | ||
5826 | return 0; | |
5827 | } | |
5828 | ||
0f6f04ba | 5829 | /* Copy byte/half word/word loads and stores. */ |
cca44b1b | 5830 | |
7ff120b4 | 5831 | static void |
0f6f04ba | 5832 | install_load_store (struct gdbarch *gdbarch, struct regcache *regs, |
1152d984 | 5833 | arm_displaced_step_copy_insn_closure *dsc, int load, |
0f6f04ba YQ |
5834 | int immed, int writeback, int size, int usermode, |
5835 | int rt, int rm, int rn) | |
cca44b1b | 5836 | { |
cca44b1b | 5837 | ULONGEST rt_val, rn_val, rm_val = 0; |
cca44b1b | 5838 | |
36073a92 YQ |
5839 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); |
5840 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
cca44b1b | 5841 | if (!immed) |
36073a92 | 5842 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); |
cca44b1b | 5843 | if (!load) |
36073a92 | 5844 | dsc->tmp[4] = displaced_read_reg (regs, dsc, 4); |
cca44b1b | 5845 | |
36073a92 YQ |
5846 | rt_val = displaced_read_reg (regs, dsc, rt); |
5847 | rn_val = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 5848 | if (!immed) |
36073a92 | 5849 | rm_val = displaced_read_reg (regs, dsc, rm); |
cca44b1b JB |
5850 | |
5851 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); | |
5852 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); | |
5853 | if (!immed) | |
5854 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); | |
cca44b1b | 5855 | dsc->rd = rt; |
0f6f04ba | 5856 | dsc->u.ldst.xfersize = size; |
cca44b1b JB |
5857 | dsc->u.ldst.rn = rn; |
5858 | dsc->u.ldst.immed = immed; | |
7ff120b4 | 5859 | dsc->u.ldst.writeback = writeback; |
cca44b1b JB |
5860 | |
5861 | /* To write PC we can do: | |
5862 | ||
494e194e YQ |
5863 | Before this sequence of instructions: |
5864 | r0 is the PC value got from displaced_read_reg, so r0 = from + 8; | |
85102364 | 5865 | r2 is the Rn value got from displaced_read_reg. |
494e194e YQ |
5866 | |
5867 | Insn1: push {pc} Write address of STR instruction + offset on stack | |
5868 | Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset | |
5869 | Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc | |
dda83cd7 SM |
5870 | = addr(Insn1) + offset - addr(Insn3) - 8 |
5871 | = offset - 16 | |
494e194e YQ |
5872 | Insn4: add r4, r4, #8 r4 = offset - 8 |
5873 | Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8 | |
dda83cd7 | 5874 | = from + offset |
494e194e | 5875 | Insn6: str r0, [r2, #imm] (or str r0, [r2, r3]) |
cca44b1b JB |
5876 | |
5877 | Otherwise we don't know what value to write for PC, since the offset is | |
494e194e YQ |
5878 | architecture-dependent (sometimes PC+8, sometimes PC+12). More details |
5879 | of this can be found in Section "Saving from r15" in | |
5880 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ | |
cca44b1b | 5881 | |
7ff120b4 YQ |
5882 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
5883 | } | |
5884 | ||
34518530 YQ |
5885 | |
5886 | static int | |
5887 | thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1, | |
5888 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5889 | arm_displaced_step_copy_insn_closure *dsc, int size) |
34518530 YQ |
5890 | { |
5891 | unsigned int u_bit = bit (insn1, 7); | |
5892 | unsigned int rt = bits (insn2, 12, 15); | |
5893 | int imm12 = bits (insn2, 0, 11); | |
5894 | ULONGEST pc_val; | |
5895 | ||
136821d9 SM |
5896 | displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x", |
5897 | (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-', | |
5898 | imm12); | |
34518530 YQ |
5899 | |
5900 | if (!u_bit) | |
5901 | imm12 = -1 * imm12; | |
5902 | ||
5903 | /* Rewrite instruction LDR Rt imm12 into: | |
5904 | ||
5905 | Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12 | |
5906 | ||
5907 | LDR R0, R2, R3, | |
5908 | ||
5909 | Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */ | |
5910 | ||
5911 | ||
5912 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
5913 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
5914 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
5915 | ||
5916 | pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
5917 | ||
5918 | pc_val = pc_val & 0xfffffffc; | |
5919 | ||
5920 | displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC); | |
5921 | displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC); | |
5922 | ||
5923 | dsc->rd = rt; | |
5924 | ||
5925 | dsc->u.ldst.xfersize = size; | |
5926 | dsc->u.ldst.immed = 0; | |
5927 | dsc->u.ldst.writeback = 0; | |
5928 | dsc->u.ldst.restore_r4 = 0; | |
5929 | ||
5930 | /* LDR R0, R2, R3 */ | |
5931 | dsc->modinsn[0] = 0xf852; | |
5932 | dsc->modinsn[1] = 0x3; | |
5933 | dsc->numinsns = 2; | |
5934 | ||
5935 | dsc->cleanup = &cleanup_load; | |
5936 | ||
5937 | return 0; | |
5938 | } | |
5939 | ||
5940 | static int | |
5941 | thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1, | |
5942 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 5943 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
5944 | int writeback, int immed) |
5945 | { | |
5946 | unsigned int rt = bits (insn2, 12, 15); | |
5947 | unsigned int rn = bits (insn1, 0, 3); | |
5948 | unsigned int rm = bits (insn2, 0, 3); /* Only valid if !immed. */ | |
5949 | /* In LDR (register), there is also a register Rm, which is not allowed to | |
5950 | be PC, so we don't have to check it. */ | |
5951 | ||
5952 | if (rt != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) | |
5953 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "load", | |
5954 | dsc); | |
5955 | ||
136821d9 SM |
5956 | displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x", |
5957 | rt, rn, insn1, insn2); | |
34518530 YQ |
5958 | |
5959 | install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4, | |
5960 | 0, rt, rm, rn); | |
5961 | ||
5962 | dsc->u.ldst.restore_r4 = 0; | |
5963 | ||
5964 | if (immed) | |
5965 | /* ldr[b]<cond> rt, [rn, #imm], etc. | |
5966 | -> | |
5967 | ldr[b]<cond> r0, [r2, #imm]. */ | |
5968 | { | |
5969 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5970 | dsc->modinsn[1] = insn2 & 0x0fff; | |
5971 | } | |
5972 | else | |
5973 | /* ldr[b]<cond> rt, [rn, rm], etc. | |
5974 | -> | |
5975 | ldr[b]<cond> r0, [r2, r3]. */ | |
5976 | { | |
5977 | dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2; | |
5978 | dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3; | |
5979 | } | |
5980 | ||
5981 | dsc->numinsns = 2; | |
5982 | ||
5983 | return 0; | |
5984 | } | |
5985 | ||
5986 | ||
7ff120b4 YQ |
5987 | static int |
5988 | arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, | |
5989 | struct regcache *regs, | |
1152d984 | 5990 | arm_displaced_step_copy_insn_closure *dsc, |
0f6f04ba | 5991 | int load, int size, int usermode) |
7ff120b4 YQ |
5992 | { |
5993 | int immed = !bit (insn, 25); | |
5994 | int writeback = (bit (insn, 24) == 0 || bit (insn, 21) != 0); | |
5995 | unsigned int rt = bits (insn, 12, 15); | |
5996 | unsigned int rn = bits (insn, 16, 19); | |
5997 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ | |
5998 | ||
5999 | if (!insn_references_pc (insn, 0x000ff00ful)) | |
6000 | return arm_copy_unmodified (gdbarch, insn, "load/store", dsc); | |
6001 | ||
136821d9 SM |
6002 | displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx", |
6003 | load ? (size == 1 ? "ldrb" : "ldr") | |
6004 | : (size == 1 ? "strb" : "str"), | |
6005 | usermode ? "t" : "", | |
6006 | rt, rn, | |
6007 | (unsigned long) insn); | |
7ff120b4 | 6008 | |
0f6f04ba YQ |
6009 | install_load_store (gdbarch, regs, dsc, load, immed, writeback, size, |
6010 | usermode, rt, rm, rn); | |
7ff120b4 | 6011 | |
bf9f652a | 6012 | if (load || rt != ARM_PC_REGNUM) |
cca44b1b JB |
6013 | { |
6014 | dsc->u.ldst.restore_r4 = 0; | |
6015 | ||
6016 | if (immed) | |
6017 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. | |
6018 | -> | |
6019 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ | |
6020 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; | |
6021 | else | |
6022 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. | |
6023 | -> | |
6024 | {ldr,str}[b]<cond> r0, [r2, r3]. */ | |
6025 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; | |
6026 | } | |
6027 | else | |
6028 | { | |
6029 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ | |
6030 | dsc->u.ldst.restore_r4 = 1; | |
494e194e YQ |
6031 | dsc->modinsn[0] = 0xe92d8000; /* push {pc} */ |
6032 | dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */ | |
cca44b1b JB |
6033 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
6034 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ | |
6035 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ | |
6036 | ||
6037 | /* As above. */ | |
6038 | if (immed) | |
6039 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; | |
6040 | else | |
6041 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; | |
6042 | ||
cca44b1b JB |
6043 | dsc->numinsns = 6; |
6044 | } | |
6045 | ||
6046 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; | |
6047 | ||
6048 | return 0; | |
6049 | } | |
6050 | ||
6051 | /* Cleanup LDM instructions with fully-populated register list. This is an | |
6052 | unfortunate corner case: it's impossible to implement correctly by modifying | |
6053 | the instruction. The issue is as follows: we have an instruction, | |
6054 | ||
6055 | ldm rN, {r0-r15} | |
6056 | ||
6057 | which we must rewrite to avoid loading PC. A possible solution would be to | |
6058 | do the load in two halves, something like (with suitable cleanup | |
6059 | afterwards): | |
6060 | ||
6061 | mov r8, rN | |
6062 | ldm[id][ab] r8!, {r0-r7} | |
6063 | str r7, <temp> | |
6064 | ldm[id][ab] r8, {r7-r14} | |
6065 | <bkpt> | |
6066 | ||
6067 | but at present there's no suitable place for <temp>, since the scratch space | |
6068 | is overwritten before the cleanup routine is called. For now, we simply | |
6069 | emulate the instruction. */ | |
6070 | ||
6071 | static void | |
6072 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6073 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6074 | { |
cca44b1b JB |
6075 | int inc = dsc->u.block.increment; |
6076 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; | |
6077 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); | |
6078 | uint32_t regmask = dsc->u.block.regmask; | |
6079 | int regno = inc ? 0 : 15; | |
6080 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; | |
6081 | int exception_return = dsc->u.block.load && dsc->u.block.user | |
6082 | && (regmask & 0x8000) != 0; | |
36073a92 | 6083 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b JB |
6084 | int do_transfer = condition_true (dsc->u.block.cond, status); |
6085 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6086 | ||
6087 | if (!do_transfer) | |
6088 | return; | |
6089 | ||
6090 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything | |
6091 | sensible we can do here. Complain loudly. */ | |
6092 | if (exception_return) | |
6093 | error (_("Cannot single-step exception return")); | |
6094 | ||
6095 | /* We don't handle any stores here for now. */ | |
6096 | gdb_assert (dsc->u.block.load != 0); | |
6097 | ||
136821d9 SM |
6098 | displaced_debug_printf ("emulating block transfer: %s %s %s", |
6099 | dsc->u.block.load ? "ldm" : "stm", | |
6100 | dsc->u.block.increment ? "inc" : "dec", | |
6101 | dsc->u.block.before ? "before" : "after"); | |
cca44b1b JB |
6102 | |
6103 | while (regmask) | |
6104 | { | |
6105 | uint32_t memword; | |
6106 | ||
6107 | if (inc) | |
bf9f652a | 6108 | while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) |
cca44b1b JB |
6109 | regno++; |
6110 | else | |
6111 | while (regno >= 0 && (regmask & (1 << regno)) == 0) | |
6112 | regno--; | |
6113 | ||
6114 | xfer_addr += bump_before; | |
6115 | ||
6116 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); | |
6117 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); | |
6118 | ||
6119 | xfer_addr += bump_after; | |
6120 | ||
6121 | regmask &= ~(1 << regno); | |
6122 | } | |
6123 | ||
6124 | if (dsc->u.block.writeback) | |
6125 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, | |
6126 | CANNOT_WRITE_PC); | |
6127 | } | |
6128 | ||
6129 | /* Clean up an STM which included the PC in the register list. */ | |
6130 | ||
6131 | static void | |
6132 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6133 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6134 | { |
36073a92 | 6135 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
cca44b1b | 6136 | int store_executed = condition_true (dsc->u.block.cond, status); |
5f661e03 SM |
6137 | CORE_ADDR pc_stored_at, transferred_regs |
6138 | = count_one_bits (dsc->u.block.regmask); | |
cca44b1b JB |
6139 | CORE_ADDR stm_insn_addr; |
6140 | uint32_t pc_val; | |
6141 | long offset; | |
6142 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6143 | ||
6144 | /* If condition code fails, there's nothing else to do. */ | |
6145 | if (!store_executed) | |
6146 | return; | |
6147 | ||
6148 | if (dsc->u.block.increment) | |
6149 | { | |
6150 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; | |
6151 | ||
6152 | if (dsc->u.block.before) | |
6153 | pc_stored_at += 4; | |
6154 | } | |
6155 | else | |
6156 | { | |
6157 | pc_stored_at = dsc->u.block.xfer_addr; | |
6158 | ||
6159 | if (dsc->u.block.before) | |
6160 | pc_stored_at -= 4; | |
6161 | } | |
6162 | ||
6163 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); | |
6164 | stm_insn_addr = dsc->scratch_base; | |
6165 | offset = pc_val - stm_insn_addr; | |
6166 | ||
136821d9 SM |
6167 | displaced_debug_printf ("detected PC offset %.8lx for STM instruction", |
6168 | offset); | |
cca44b1b JB |
6169 | |
6170 | /* Rewrite the stored PC to the proper value for the non-displaced original | |
6171 | instruction. */ | |
6172 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, | |
6173 | dsc->insn_addr + offset); | |
6174 | } | |
6175 | ||
6176 | /* Clean up an LDM which includes the PC in the register list. We clumped all | |
6177 | the registers in the transferred list into a contiguous range r0...rX (to | |
6178 | avoid loading PC directly and losing control of the debugged program), so we | |
6179 | must undo that here. */ | |
6180 | ||
6181 | static void | |
6e39997a | 6182 | cleanup_block_load_pc (struct gdbarch *gdbarch, |
cca44b1b | 6183 | struct regcache *regs, |
1152d984 | 6184 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6185 | { |
36073a92 | 6186 | uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM); |
22e048c9 | 6187 | int load_executed = condition_true (dsc->u.block.cond, status); |
bf9f652a | 6188 | unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; |
5f661e03 | 6189 | unsigned int regs_loaded = count_one_bits (mask); |
cca44b1b JB |
6190 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
6191 | ||
6192 | /* The method employed here will fail if the register list is fully populated | |
6193 | (we need to avoid loading PC directly). */ | |
6194 | gdb_assert (num_to_shuffle < 16); | |
6195 | ||
6196 | if (!load_executed) | |
6197 | return; | |
6198 | ||
6199 | clobbered = (1 << num_to_shuffle) - 1; | |
6200 | ||
6201 | while (num_to_shuffle > 0) | |
6202 | { | |
6203 | if ((mask & (1 << write_reg)) != 0) | |
6204 | { | |
6205 | unsigned int read_reg = num_to_shuffle - 1; | |
6206 | ||
6207 | if (read_reg != write_reg) | |
6208 | { | |
36073a92 | 6209 | ULONGEST rval = displaced_read_reg (regs, dsc, read_reg); |
cca44b1b | 6210 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
136821d9 SM |
6211 | displaced_debug_printf ("LDM: move loaded register r%d to r%d", |
6212 | read_reg, write_reg); | |
cca44b1b | 6213 | } |
136821d9 SM |
6214 | else |
6215 | displaced_debug_printf ("LDM: register r%d already in the right " | |
6216 | "place", write_reg); | |
cca44b1b JB |
6217 | |
6218 | clobbered &= ~(1 << write_reg); | |
6219 | ||
6220 | num_to_shuffle--; | |
6221 | } | |
6222 | ||
6223 | write_reg--; | |
6224 | } | |
6225 | ||
6226 | /* Restore any registers we scribbled over. */ | |
6227 | for (write_reg = 0; clobbered != 0; write_reg++) | |
6228 | { | |
6229 | if ((clobbered & (1 << write_reg)) != 0) | |
6230 | { | |
6231 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], | |
6232 | CANNOT_WRITE_PC); | |
136821d9 SM |
6233 | displaced_debug_printf ("LDM: restored clobbered register r%d", |
6234 | write_reg); | |
cca44b1b JB |
6235 | clobbered &= ~(1 << write_reg); |
6236 | } | |
6237 | } | |
6238 | ||
6239 | /* Perform register writeback manually. */ | |
6240 | if (dsc->u.block.writeback) | |
6241 | { | |
6242 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; | |
6243 | ||
6244 | if (dsc->u.block.increment) | |
6245 | new_rn_val += regs_loaded * 4; | |
6246 | else | |
6247 | new_rn_val -= regs_loaded * 4; | |
6248 | ||
6249 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, | |
6250 | CANNOT_WRITE_PC); | |
6251 | } | |
6252 | } | |
6253 | ||
6254 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur | |
6255 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ | |
6256 | ||
6257 | static int | |
7ff120b4 YQ |
6258 | arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, |
6259 | struct regcache *regs, | |
1152d984 | 6260 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6261 | { |
6262 | int load = bit (insn, 20); | |
6263 | int user = bit (insn, 22); | |
6264 | int increment = bit (insn, 23); | |
6265 | int before = bit (insn, 24); | |
6266 | int writeback = bit (insn, 21); | |
6267 | int rn = bits (insn, 16, 19); | |
cca44b1b | 6268 | |
0963b4bd MS |
6269 | /* Block transfers which don't mention PC can be run directly |
6270 | out-of-line. */ | |
bf9f652a | 6271 | if (rn != ARM_PC_REGNUM && (insn & 0x8000) == 0) |
7ff120b4 | 6272 | return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
cca44b1b | 6273 | |
bf9f652a | 6274 | if (rn == ARM_PC_REGNUM) |
cca44b1b | 6275 | { |
0963b4bd MS |
6276 | warning (_("displaced: Unpredictable LDM or STM with " |
6277 | "base register r15")); | |
7ff120b4 | 6278 | return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
cca44b1b JB |
6279 | } |
6280 | ||
136821d9 SM |
6281 | displaced_debug_printf ("copying block transfer insn %.8lx", |
6282 | (unsigned long) insn); | |
cca44b1b | 6283 | |
36073a92 | 6284 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); |
cca44b1b JB |
6285 | dsc->u.block.rn = rn; |
6286 | ||
6287 | dsc->u.block.load = load; | |
6288 | dsc->u.block.user = user; | |
6289 | dsc->u.block.increment = increment; | |
6290 | dsc->u.block.before = before; | |
6291 | dsc->u.block.writeback = writeback; | |
6292 | dsc->u.block.cond = bits (insn, 28, 31); | |
6293 | ||
6294 | dsc->u.block.regmask = insn & 0xffff; | |
6295 | ||
6296 | if (load) | |
6297 | { | |
6298 | if ((insn & 0xffff) == 0xffff) | |
6299 | { | |
6300 | /* LDM with a fully-populated register list. This case is | |
6301 | particularly tricky. Implement for now by fully emulating the | |
6302 | instruction (which might not behave perfectly in all cases, but | |
6303 | these instructions should be rare enough for that not to matter | |
6304 | too much). */ | |
6305 | dsc->modinsn[0] = ARM_NOP; | |
6306 | ||
6307 | dsc->cleanup = &cleanup_block_load_all; | |
6308 | } | |
6309 | else | |
6310 | { | |
6311 | /* LDM of a list of registers which includes PC. Implement by | |
6312 | rewriting the list of registers to be transferred into a | |
6313 | contiguous chunk r0...rX before doing the transfer, then shuffling | |
6314 | registers into the correct places in the cleanup routine. */ | |
6315 | unsigned int regmask = insn & 0xffff; | |
5f661e03 | 6316 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6317 | unsigned int i; |
cca44b1b JB |
6318 | |
6319 | for (i = 0; i < num_in_list; i++) | |
36073a92 | 6320 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); |
cca44b1b JB |
6321 | |
6322 | /* Writeback makes things complicated. We need to avoid clobbering | |
6323 | the base register with one of the registers in our modified | |
6324 | register list, but just using a different register can't work in | |
6325 | all cases, e.g.: | |
6326 | ||
6327 | ldm r14!, {r0-r13,pc} | |
6328 | ||
6329 | which would need to be rewritten as: | |
6330 | ||
6331 | ldm rN!, {r0-r14} | |
6332 | ||
6333 | but that can't work, because there's no free register for N. | |
6334 | ||
6335 | Solve this by turning off the writeback bit, and emulating | |
6336 | writeback manually in the cleanup routine. */ | |
6337 | ||
6338 | if (writeback) | |
6339 | insn &= ~(1 << 21); | |
6340 | ||
6341 | new_regmask = (1 << num_in_list) - 1; | |
6342 | ||
136821d9 SM |
6343 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6344 | "%.4x, modified list %.4x", | |
6345 | rn, writeback ? "!" : "", | |
6346 | (int) insn & 0xffff, new_regmask); | |
cca44b1b JB |
6347 | |
6348 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); | |
6349 | ||
6350 | dsc->cleanup = &cleanup_block_load_pc; | |
6351 | } | |
6352 | } | |
6353 | else | |
6354 | { | |
6355 | /* STM of a list of registers which includes PC. Run the instruction | |
6356 | as-is, but out of line: this will store the wrong value for the PC, | |
6357 | so we must manually fix up the memory in the cleanup routine. | |
6358 | Doing things this way has the advantage that we can auto-detect | |
6359 | the offset of the PC write (which is architecture-dependent) in | |
6360 | the cleanup routine. */ | |
6361 | dsc->modinsn[0] = insn; | |
6362 | ||
6363 | dsc->cleanup = &cleanup_block_store_pc; | |
6364 | } | |
6365 | ||
6366 | return 0; | |
6367 | } | |
6368 | ||
34518530 YQ |
6369 | static int |
6370 | thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
6371 | struct regcache *regs, | |
1152d984 | 6372 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6373 | { |
34518530 YQ |
6374 | int rn = bits (insn1, 0, 3); |
6375 | int load = bit (insn1, 4); | |
6376 | int writeback = bit (insn1, 5); | |
cca44b1b | 6377 | |
34518530 YQ |
6378 | /* Block transfers which don't mention PC can be run directly |
6379 | out-of-line. */ | |
6380 | if (rn != ARM_PC_REGNUM && (insn2 & 0x8000) == 0) | |
6381 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc); | |
7ff120b4 | 6382 | |
34518530 YQ |
6383 | if (rn == ARM_PC_REGNUM) |
6384 | { | |
6385 | warning (_("displaced: Unpredictable LDM or STM with " | |
6386 | "base register r15")); | |
6387 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
6388 | "unpredictable ldm/stm", dsc); | |
6389 | } | |
cca44b1b | 6390 | |
136821d9 SM |
6391 | displaced_debug_printf ("copying block transfer insn %.4x%.4x", |
6392 | insn1, insn2); | |
cca44b1b | 6393 | |
34518530 YQ |
6394 | /* Clear bit 13, since it should be always zero. */ |
6395 | dsc->u.block.regmask = (insn2 & 0xdfff); | |
6396 | dsc->u.block.rn = rn; | |
cca44b1b | 6397 | |
34518530 YQ |
6398 | dsc->u.block.load = load; |
6399 | dsc->u.block.user = 0; | |
6400 | dsc->u.block.increment = bit (insn1, 7); | |
6401 | dsc->u.block.before = bit (insn1, 8); | |
6402 | dsc->u.block.writeback = writeback; | |
6403 | dsc->u.block.cond = INST_AL; | |
6404 | dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn); | |
cca44b1b | 6405 | |
34518530 YQ |
6406 | if (load) |
6407 | { | |
6408 | if (dsc->u.block.regmask == 0xffff) | |
6409 | { | |
6410 | /* This branch is impossible to happen. */ | |
6411 | gdb_assert (0); | |
6412 | } | |
6413 | else | |
6414 | { | |
6415 | unsigned int regmask = dsc->u.block.regmask; | |
5f661e03 | 6416 | unsigned int num_in_list = count_one_bits (regmask), new_regmask; |
bec2ab5a | 6417 | unsigned int i; |
34518530 YQ |
6418 | |
6419 | for (i = 0; i < num_in_list; i++) | |
6420 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
6421 | ||
6422 | if (writeback) | |
6423 | insn1 &= ~(1 << 5); | |
6424 | ||
6425 | new_regmask = (1 << num_in_list) - 1; | |
6426 | ||
136821d9 SM |
6427 | displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list " |
6428 | "%.4x, modified list %.4x", | |
6429 | rn, writeback ? "!" : "", | |
6430 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
6431 | |
6432 | dsc->modinsn[0] = insn1; | |
6433 | dsc->modinsn[1] = (new_regmask & 0xffff); | |
6434 | dsc->numinsns = 2; | |
6435 | ||
6436 | dsc->cleanup = &cleanup_block_load_pc; | |
6437 | } | |
6438 | } | |
6439 | else | |
6440 | { | |
6441 | dsc->modinsn[0] = insn1; | |
6442 | dsc->modinsn[1] = insn2; | |
6443 | dsc->numinsns = 2; | |
6444 | dsc->cleanup = &cleanup_block_store_pc; | |
6445 | } | |
6446 | return 0; | |
6447 | } | |
6448 | ||
d9311bfa AT |
6449 | /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. |
6450 | This is used to avoid a dependency on BFD's bfd_endian enum. */ | |
6451 | ||
6452 | ULONGEST | |
6453 | arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, | |
6454 | int byte_order) | |
6455 | { | |
5f2dfcfd AT |
6456 | return read_memory_unsigned_integer (memaddr, len, |
6457 | (enum bfd_endian) byte_order); | |
d9311bfa AT |
6458 | } |
6459 | ||
6460 | /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ | |
6461 | ||
6462 | CORE_ADDR | |
6463 | arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
6464 | CORE_ADDR val) | |
6465 | { | |
ac7936df | 6466 | return gdbarch_addr_bits_remove (self->regcache->arch (), val); |
d9311bfa AT |
6467 | } |
6468 | ||
6469 | /* Wrapper over syscall_next_pc for use in get_next_pcs. */ | |
6470 | ||
e7cf25a8 | 6471 | static CORE_ADDR |
553cb527 | 6472 | arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa | 6473 | { |
d9311bfa AT |
6474 | return 0; |
6475 | } | |
6476 | ||
6477 | /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ | |
6478 | ||
6479 | int | |
6480 | arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
6481 | { | |
6482 | return arm_is_thumb (self->regcache); | |
6483 | } | |
6484 | ||
6485 | /* single_step() is called just before we want to resume the inferior, | |
6486 | if we want to single-step it but there is no hardware or kernel | |
6487 | single-step support. We find the target of the coming instructions | |
6488 | and breakpoint them. */ | |
6489 | ||
a0ff9e1a | 6490 | std::vector<CORE_ADDR> |
f5ea389a | 6491 | arm_software_single_step (struct regcache *regcache) |
d9311bfa | 6492 | { |
ac7936df | 6493 | struct gdbarch *gdbarch = regcache->arch (); |
d9311bfa | 6494 | struct arm_get_next_pcs next_pcs_ctx; |
d9311bfa AT |
6495 | |
6496 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
6497 | &arm_get_next_pcs_ops, | |
6498 | gdbarch_byte_order (gdbarch), | |
6499 | gdbarch_byte_order_for_code (gdbarch), | |
1b451dda | 6500 | 0, |
d9311bfa AT |
6501 | regcache); |
6502 | ||
a0ff9e1a | 6503 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa | 6504 | |
a0ff9e1a SM |
6505 | for (CORE_ADDR &pc_ref : next_pcs) |
6506 | pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); | |
d9311bfa | 6507 | |
93f9a11f | 6508 | return next_pcs; |
d9311bfa AT |
6509 | } |
6510 | ||
34518530 YQ |
6511 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
6512 | for Linux, where some SVC instructions must be treated specially. */ | |
6513 | ||
6514 | static void | |
6515 | cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6516 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6517 | { |
6518 | CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size; | |
6519 | ||
136821d9 SM |
6520 | displaced_debug_printf ("cleanup for svc, resume at %.8lx", |
6521 | (unsigned long) resume_addr); | |
34518530 YQ |
6522 | |
6523 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); | |
6524 | } | |
6525 | ||
6526 | ||
85102364 | 6527 | /* Common copy routine for svc instruction. */ |
34518530 YQ |
6528 | |
6529 | static int | |
6530 | install_svc (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 6531 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6532 | { |
6533 | /* Preparation: none. | |
6534 | Insn: unmodified svc. | |
6535 | Cleanup: pc <- insn_addr + insn_size. */ | |
6536 | ||
6537 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next | |
6538 | instruction. */ | |
6539 | dsc->wrote_to_pc = 1; | |
6540 | ||
6541 | /* Allow OS-specific code to override SVC handling. */ | |
bd18283a YQ |
6542 | if (dsc->u.svc.copy_svc_os) |
6543 | return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc); | |
6544 | else | |
6545 | { | |
6546 | dsc->cleanup = &cleanup_svc; | |
6547 | return 0; | |
6548 | } | |
34518530 YQ |
6549 | } |
6550 | ||
6551 | static int | |
6552 | arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn, | |
1152d984 | 6553 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6554 | { |
6555 | ||
136821d9 SM |
6556 | displaced_debug_printf ("copying svc insn %.8lx", |
6557 | (unsigned long) insn); | |
34518530 YQ |
6558 | |
6559 | dsc->modinsn[0] = insn; | |
6560 | ||
6561 | return install_svc (gdbarch, regs, dsc); | |
6562 | } | |
6563 | ||
6564 | static int | |
6565 | thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn, | |
1152d984 | 6566 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6567 | { |
6568 | ||
136821d9 | 6569 | displaced_debug_printf ("copying svc insn %.4x", insn); |
bd18283a | 6570 | |
34518530 YQ |
6571 | dsc->modinsn[0] = insn; |
6572 | ||
6573 | return install_svc (gdbarch, regs, dsc); | |
cca44b1b JB |
6574 | } |
6575 | ||
6576 | /* Copy undefined instructions. */ | |
6577 | ||
6578 | static int | |
7ff120b4 | 6579 | arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6580 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6581 | { |
136821d9 SM |
6582 | displaced_debug_printf ("copying undefined insn %.8lx", |
6583 | (unsigned long) insn); | |
cca44b1b JB |
6584 | |
6585 | dsc->modinsn[0] = insn; | |
6586 | ||
6587 | return 0; | |
6588 | } | |
6589 | ||
34518530 YQ |
6590 | static int |
6591 | thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, | |
1152d984 | 6592 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
6593 | { |
6594 | ||
136821d9 SM |
6595 | displaced_debug_printf ("copying undefined insn %.4x %.4x", |
6596 | (unsigned short) insn1, (unsigned short) insn2); | |
34518530 YQ |
6597 | |
6598 | dsc->modinsn[0] = insn1; | |
6599 | dsc->modinsn[1] = insn2; | |
6600 | dsc->numinsns = 2; | |
6601 | ||
6602 | return 0; | |
6603 | } | |
6604 | ||
cca44b1b JB |
6605 | /* Copy unpredictable instructions. */ |
6606 | ||
6607 | static int | |
7ff120b4 | 6608 | arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6609 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b | 6610 | { |
136821d9 SM |
6611 | displaced_debug_printf ("copying unpredictable insn %.8lx", |
6612 | (unsigned long) insn); | |
cca44b1b JB |
6613 | |
6614 | dsc->modinsn[0] = insn; | |
6615 | ||
6616 | return 0; | |
6617 | } | |
6618 | ||
6619 | /* The decode_* functions are instruction decoding helpers. They mostly follow | |
6620 | the presentation in the ARM ARM. */ | |
6621 | ||
6622 | static int | |
7ff120b4 YQ |
6623 | arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
6624 | struct regcache *regs, | |
1152d984 | 6625 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6626 | { |
6627 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); | |
6628 | unsigned int rn = bits (insn, 16, 19); | |
6629 | ||
2f924de6 | 6630 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0) |
7ff120b4 | 6631 | return arm_copy_unmodified (gdbarch, insn, "cps", dsc); |
2f924de6 | 6632 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1) |
7ff120b4 | 6633 | return arm_copy_unmodified (gdbarch, insn, "setend", dsc); |
cca44b1b | 6634 | else if ((op1 & 0x60) == 0x20) |
7ff120b4 | 6635 | return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
cca44b1b | 6636 | else if ((op1 & 0x71) == 0x40) |
7ff120b4 YQ |
6637 | return arm_copy_unmodified (gdbarch, insn, "neon elt/struct load/store", |
6638 | dsc); | |
cca44b1b | 6639 | else if ((op1 & 0x77) == 0x41) |
7ff120b4 | 6640 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6641 | else if ((op1 & 0x77) == 0x45) |
7ff120b4 | 6642 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
cca44b1b JB |
6643 | else if ((op1 & 0x77) == 0x51) |
6644 | { | |
6645 | if (rn != 0xf) | |
7ff120b4 | 6646 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b | 6647 | else |
7ff120b4 | 6648 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6649 | } |
6650 | else if ((op1 & 0x77) == 0x55) | |
7ff120b4 | 6651 | return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
cca44b1b JB |
6652 | else if (op1 == 0x57) |
6653 | switch (op2) | |
6654 | { | |
7ff120b4 YQ |
6655 | case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc); |
6656 | case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc); | |
6657 | case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc); | |
6658 | case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc); | |
6659 | default: return arm_copy_unpred (gdbarch, insn, dsc); | |
cca44b1b JB |
6660 | } |
6661 | else if ((op1 & 0x63) == 0x43) | |
7ff120b4 | 6662 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b JB |
6663 | else if ((op2 & 0x1) == 0x0) |
6664 | switch (op1 & ~0x80) | |
6665 | { | |
6666 | case 0x61: | |
7ff120b4 | 6667 | return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
cca44b1b | 6668 | case 0x65: |
7ff120b4 | 6669 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
cca44b1b | 6670 | case 0x71: case 0x75: |
dda83cd7 | 6671 | /* pld/pldw reg. */ |
7ff120b4 | 6672 | return arm_copy_preload_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6673 | case 0x63: case 0x67: case 0x73: case 0x77: |
7ff120b4 | 6674 | return arm_copy_unpred (gdbarch, insn, dsc); |
cca44b1b | 6675 | default: |
7ff120b4 | 6676 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6677 | } |
6678 | else | |
7ff120b4 | 6679 | return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
cca44b1b JB |
6680 | } |
6681 | ||
6682 | static int | |
7ff120b4 YQ |
6683 | arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
6684 | struct regcache *regs, | |
1152d984 | 6685 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6686 | { |
6687 | if (bit (insn, 27) == 0) | |
7ff120b4 | 6688 | return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6689 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
6690 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) | |
6691 | { | |
6692 | case 0x0: case 0x2: | |
7ff120b4 | 6693 | return arm_copy_unmodified (gdbarch, insn, "srs", dsc); |
cca44b1b JB |
6694 | |
6695 | case 0x1: case 0x3: | |
7ff120b4 | 6696 | return arm_copy_unmodified (gdbarch, insn, "rfe", dsc); |
cca44b1b JB |
6697 | |
6698 | case 0x4: case 0x5: case 0x6: case 0x7: | |
7ff120b4 | 6699 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6700 | |
6701 | case 0x8: | |
6702 | switch ((insn & 0xe00000) >> 21) | |
6703 | { | |
6704 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: | |
6705 | /* stc/stc2. */ | |
7ff120b4 | 6706 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6707 | |
6708 | case 0x2: | |
7ff120b4 | 6709 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b JB |
6710 | |
6711 | default: | |
7ff120b4 | 6712 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6713 | } |
6714 | ||
6715 | case 0x9: | |
6716 | { | |
6717 | int rn_f = (bits (insn, 16, 19) == 0xf); | |
6718 | switch ((insn & 0xe00000) >> 21) | |
6719 | { | |
6720 | case 0x1: case 0x3: | |
6721 | /* ldc/ldc2 imm (undefined for rn == pc). */ | |
7ff120b4 YQ |
6722 | return rn_f ? arm_copy_undef (gdbarch, insn, dsc) |
6723 | : arm_copy_copro_load_store (gdbarch, insn, regs, dsc); | |
cca44b1b JB |
6724 | |
6725 | case 0x2: | |
7ff120b4 | 6726 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
6727 | |
6728 | case 0x4: case 0x5: case 0x6: case 0x7: | |
6729 | /* ldc/ldc2 lit (undefined for rn != pc). */ | |
7ff120b4 YQ |
6730 | return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc) |
6731 | : arm_copy_undef (gdbarch, insn, dsc); | |
cca44b1b JB |
6732 | |
6733 | default: | |
7ff120b4 | 6734 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6735 | } |
6736 | } | |
6737 | ||
6738 | case 0xa: | |
7ff120b4 | 6739 | return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
cca44b1b JB |
6740 | |
6741 | case 0xb: | |
6742 | if (bits (insn, 16, 19) == 0xf) | |
dda83cd7 | 6743 | /* ldc/ldc2 lit. */ |
7ff120b4 | 6744 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 6745 | else |
7ff120b4 | 6746 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6747 | |
6748 | case 0xc: | |
6749 | if (bit (insn, 4)) | |
7ff120b4 | 6750 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 6751 | else |
7ff120b4 | 6752 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6753 | |
6754 | case 0xd: | |
6755 | if (bit (insn, 4)) | |
7ff120b4 | 6756 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 6757 | else |
7ff120b4 | 6758 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
6759 | |
6760 | default: | |
7ff120b4 | 6761 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6762 | } |
6763 | } | |
6764 | ||
6765 | /* Decode miscellaneous instructions in dp/misc encoding space. */ | |
6766 | ||
6767 | static int | |
7ff120b4 YQ |
6768 | arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
6769 | struct regcache *regs, | |
1152d984 | 6770 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6771 | { |
6772 | unsigned int op2 = bits (insn, 4, 6); | |
6773 | unsigned int op = bits (insn, 21, 22); | |
cca44b1b JB |
6774 | |
6775 | switch (op2) | |
6776 | { | |
6777 | case 0x0: | |
7ff120b4 | 6778 | return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
cca44b1b JB |
6779 | |
6780 | case 0x1: | |
6781 | if (op == 0x1) /* bx. */ | |
7ff120b4 | 6782 | return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6783 | else if (op == 0x3) |
7ff120b4 | 6784 | return arm_copy_unmodified (gdbarch, insn, "clz", dsc); |
cca44b1b | 6785 | else |
7ff120b4 | 6786 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6787 | |
6788 | case 0x2: | |
6789 | if (op == 0x1) | |
dda83cd7 | 6790 | /* Not really supported. */ |
7ff120b4 | 6791 | return arm_copy_unmodified (gdbarch, insn, "bxj", dsc); |
cca44b1b | 6792 | else |
7ff120b4 | 6793 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6794 | |
6795 | case 0x3: | |
6796 | if (op == 0x1) | |
7ff120b4 | 6797 | return arm_copy_bx_blx_reg (gdbarch, insn, |
0963b4bd | 6798 | regs, dsc); /* blx register. */ |
cca44b1b | 6799 | else |
7ff120b4 | 6800 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6801 | |
6802 | case 0x5: | |
7ff120b4 | 6803 | return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
cca44b1b JB |
6804 | |
6805 | case 0x7: | |
6806 | if (op == 0x1) | |
7ff120b4 | 6807 | return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc); |
cca44b1b | 6808 | else if (op == 0x3) |
dda83cd7 | 6809 | /* Not really supported. */ |
7ff120b4 | 6810 | return arm_copy_unmodified (gdbarch, insn, "smc", dsc); |
86a73007 | 6811 | /* Fall through. */ |
cca44b1b JB |
6812 | |
6813 | default: | |
7ff120b4 | 6814 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6815 | } |
6816 | } | |
6817 | ||
6818 | static int | |
7ff120b4 YQ |
6819 | arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, |
6820 | struct regcache *regs, | |
1152d984 | 6821 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6822 | { |
6823 | if (bit (insn, 25)) | |
6824 | switch (bits (insn, 20, 24)) | |
6825 | { | |
6826 | case 0x10: | |
7ff120b4 | 6827 | return arm_copy_unmodified (gdbarch, insn, "movw", dsc); |
cca44b1b JB |
6828 | |
6829 | case 0x14: | |
7ff120b4 | 6830 | return arm_copy_unmodified (gdbarch, insn, "movt", dsc); |
cca44b1b JB |
6831 | |
6832 | case 0x12: case 0x16: | |
7ff120b4 | 6833 | return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); |
cca44b1b JB |
6834 | |
6835 | default: | |
7ff120b4 | 6836 | return arm_copy_alu_imm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6837 | } |
6838 | else | |
6839 | { | |
6840 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); | |
6841 | ||
6842 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) | |
7ff120b4 | 6843 | return arm_copy_alu_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6844 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
7ff120b4 | 6845 | return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
cca44b1b | 6846 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
7ff120b4 | 6847 | return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); |
cca44b1b | 6848 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
7ff120b4 | 6849 | return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
cca44b1b | 6850 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
7ff120b4 | 6851 | return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
cca44b1b | 6852 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
7ff120b4 | 6853 | return arm_copy_unmodified (gdbarch, insn, "synch", dsc); |
cca44b1b | 6854 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
550dc4e2 | 6855 | /* 2nd arg means "unprivileged". */ |
7ff120b4 YQ |
6856 | return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
6857 | dsc); | |
cca44b1b JB |
6858 | } |
6859 | ||
6860 | /* Should be unreachable. */ | |
6861 | return 1; | |
6862 | } | |
6863 | ||
6864 | static int | |
7ff120b4 YQ |
6865 | arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
6866 | struct regcache *regs, | |
1152d984 | 6867 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6868 | { |
6869 | int a = bit (insn, 25), b = bit (insn, 4); | |
6870 | uint32_t op1 = bits (insn, 20, 24); | |
cca44b1b JB |
6871 | |
6872 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) | |
6873 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) | |
0f6f04ba | 6874 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0); |
cca44b1b JB |
6875 | else if ((!a && (op1 & 0x17) == 0x02) |
6876 | || (a && (op1 & 0x17) == 0x02 && !b)) | |
0f6f04ba | 6877 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1); |
cca44b1b JB |
6878 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
6879 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) | |
0f6f04ba | 6880 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0); |
cca44b1b JB |
6881 | else if ((!a && (op1 & 0x17) == 0x03) |
6882 | || (a && (op1 & 0x17) == 0x03 && !b)) | |
0f6f04ba | 6883 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1); |
cca44b1b JB |
6884 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
6885 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) | |
7ff120b4 | 6886 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
cca44b1b JB |
6887 | else if ((!a && (op1 & 0x17) == 0x06) |
6888 | || (a && (op1 & 0x17) == 0x06 && !b)) | |
7ff120b4 | 6889 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
cca44b1b JB |
6890 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
6891 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) | |
7ff120b4 | 6892 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
cca44b1b JB |
6893 | else if ((!a && (op1 & 0x17) == 0x07) |
6894 | || (a && (op1 & 0x17) == 0x07 && !b)) | |
7ff120b4 | 6895 | return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
cca44b1b JB |
6896 | |
6897 | /* Should be unreachable. */ | |
6898 | return 1; | |
6899 | } | |
6900 | ||
6901 | static int | |
7ff120b4 | 6902 | arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 6903 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6904 | { |
6905 | switch (bits (insn, 20, 24)) | |
6906 | { | |
6907 | case 0x00: case 0x01: case 0x02: case 0x03: | |
7ff120b4 | 6908 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
cca44b1b JB |
6909 | |
6910 | case 0x04: case 0x05: case 0x06: case 0x07: | |
7ff120b4 | 6911 | return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
cca44b1b JB |
6912 | |
6913 | case 0x08: case 0x09: case 0x0a: case 0x0b: | |
6914 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: | |
7ff120b4 | 6915 | return arm_copy_unmodified (gdbarch, insn, |
cca44b1b JB |
6916 | "decode/pack/unpack/saturate/reverse", dsc); |
6917 | ||
6918 | case 0x18: | |
6919 | if (bits (insn, 5, 7) == 0) /* op2. */ | |
6920 | { | |
6921 | if (bits (insn, 12, 15) == 0xf) | |
7ff120b4 | 6922 | return arm_copy_unmodified (gdbarch, insn, "usad8", dsc); |
cca44b1b | 6923 | else |
7ff120b4 | 6924 | return arm_copy_unmodified (gdbarch, insn, "usada8", dsc); |
cca44b1b JB |
6925 | } |
6926 | else | |
7ff120b4 | 6927 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6928 | |
6929 | case 0x1a: case 0x1b: | |
6930 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6931 | return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc); |
cca44b1b | 6932 | else |
7ff120b4 | 6933 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6934 | |
6935 | case 0x1c: case 0x1d: | |
6936 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ | |
6937 | { | |
6938 | if (bits (insn, 0, 3) == 0xf) | |
7ff120b4 | 6939 | return arm_copy_unmodified (gdbarch, insn, "bfc", dsc); |
cca44b1b | 6940 | else |
7ff120b4 | 6941 | return arm_copy_unmodified (gdbarch, insn, "bfi", dsc); |
cca44b1b JB |
6942 | } |
6943 | else | |
7ff120b4 | 6944 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6945 | |
6946 | case 0x1e: case 0x1f: | |
6947 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ | |
7ff120b4 | 6948 | return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc); |
cca44b1b | 6949 | else |
7ff120b4 | 6950 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b JB |
6951 | } |
6952 | ||
6953 | /* Should be unreachable. */ | |
6954 | return 1; | |
6955 | } | |
6956 | ||
6957 | static int | |
615234c1 | 6958 | arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, |
7ff120b4 | 6959 | struct regcache *regs, |
1152d984 | 6960 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6961 | { |
6962 | if (bit (insn, 25)) | |
7ff120b4 | 6963 | return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc); |
cca44b1b | 6964 | else |
7ff120b4 | 6965 | return arm_copy_block_xfer (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6966 | } |
6967 | ||
6968 | static int | |
7ff120b4 YQ |
6969 | arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
6970 | struct regcache *regs, | |
1152d984 | 6971 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
6972 | { |
6973 | unsigned int opcode = bits (insn, 20, 24); | |
6974 | ||
6975 | switch (opcode) | |
6976 | { | |
6977 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ | |
7ff120b4 | 6978 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
cca44b1b JB |
6979 | |
6980 | case 0x08: case 0x0a: case 0x0c: case 0x0e: | |
6981 | case 0x12: case 0x16: | |
7ff120b4 | 6982 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
cca44b1b JB |
6983 | |
6984 | case 0x09: case 0x0b: case 0x0d: case 0x0f: | |
6985 | case 0x13: case 0x17: | |
7ff120b4 | 6986 | return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
cca44b1b JB |
6987 | |
6988 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
6989 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
6990 | /* Note: no writeback for these instructions. Bit 25 will always be | |
6991 | zero though (via caller), so the following works OK. */ | |
7ff120b4 | 6992 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
6993 | } |
6994 | ||
6995 | /* Should be unreachable. */ | |
6996 | return 1; | |
6997 | } | |
6998 | ||
34518530 YQ |
6999 | /* Decode shifted register instructions. */ |
7000 | ||
7001 | static int | |
7002 | thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1, | |
7003 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7004 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7005 | { |
7006 | /* PC is only allowed to be used in instruction MOV. */ | |
7007 | ||
7008 | unsigned int op = bits (insn1, 5, 8); | |
7009 | unsigned int rn = bits (insn1, 0, 3); | |
7010 | ||
7011 | if (op == 0x2 && rn == 0xf) /* MOV */ | |
7012 | return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc); | |
7013 | else | |
7014 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7015 | "dp (shift reg)", dsc); | |
7016 | } | |
7017 | ||
7018 | ||
7019 | /* Decode extension register load/store. Exactly the same as | |
7020 | arm_decode_ext_reg_ld_st. */ | |
7021 | ||
7022 | static int | |
7023 | thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, | |
7024 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7025 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7026 | { |
7027 | unsigned int opcode = bits (insn1, 4, 8); | |
7028 | ||
7029 | switch (opcode) | |
7030 | { | |
7031 | case 0x04: case 0x05: | |
7032 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7033 | "vfp/neon vmov", dsc); | |
7034 | ||
7035 | case 0x08: case 0x0c: /* 01x00 */ | |
7036 | case 0x0a: case 0x0e: /* 01x10 */ | |
7037 | case 0x12: case 0x16: /* 10x10 */ | |
7038 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7039 | "vfp/neon vstm/vpush", dsc); | |
7040 | ||
7041 | case 0x09: case 0x0d: /* 01x01 */ | |
7042 | case 0x0b: case 0x0f: /* 01x11 */ | |
7043 | case 0x13: case 0x17: /* 10x11 */ | |
7044 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7045 | "vfp/neon vldm/vpop", dsc); | |
7046 | ||
7047 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ | |
7048 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7049 | "vstr", dsc); | |
7050 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ | |
7051 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc); | |
7052 | } | |
7053 | ||
7054 | /* Should be unreachable. */ | |
7055 | return 1; | |
7056 | } | |
7057 | ||
cca44b1b | 7058 | static int |
12545665 | 7059 | arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, |
1152d984 | 7060 | regcache *regs, arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7061 | { |
7062 | unsigned int op1 = bits (insn, 20, 25); | |
7063 | int op = bit (insn, 4); | |
7064 | unsigned int coproc = bits (insn, 8, 11); | |
cca44b1b JB |
7065 | |
7066 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) | |
7ff120b4 | 7067 | return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7068 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
7069 | && (coproc & 0xe) != 0xa) | |
7070 | /* stc/stc2. */ | |
7ff120b4 | 7071 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7072 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
7073 | && (coproc & 0xe) != 0xa) | |
7074 | /* ldc/ldc2 imm/lit. */ | |
7ff120b4 | 7075 | return arm_copy_copro_load_store (gdbarch, insn, regs, dsc); |
cca44b1b | 7076 | else if ((op1 & 0x3e) == 0x00) |
7ff120b4 | 7077 | return arm_copy_undef (gdbarch, insn, dsc); |
cca44b1b | 7078 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
7ff120b4 | 7079 | return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
cca44b1b | 7080 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7081 | return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
cca44b1b | 7082 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
7ff120b4 | 7083 | return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
cca44b1b JB |
7084 | else if ((op1 & 0x30) == 0x20 && !op) |
7085 | { | |
7086 | if ((coproc & 0xe) == 0xa) | |
7ff120b4 | 7087 | return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
cca44b1b | 7088 | else |
7ff120b4 | 7089 | return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
cca44b1b JB |
7090 | } |
7091 | else if ((op1 & 0x30) == 0x20 && op) | |
7ff120b4 | 7092 | return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
cca44b1b | 7093 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7094 | return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
cca44b1b | 7095 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
7ff120b4 | 7096 | return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
cca44b1b | 7097 | else if ((op1 & 0x30) == 0x30) |
7ff120b4 | 7098 | return arm_copy_svc (gdbarch, insn, regs, dsc); |
cca44b1b | 7099 | else |
7ff120b4 | 7100 | return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
cca44b1b JB |
7101 | } |
7102 | ||
34518530 YQ |
7103 | static int |
7104 | thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, | |
7105 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7106 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7107 | { |
7108 | unsigned int coproc = bits (insn2, 8, 11); | |
34518530 YQ |
7109 | unsigned int bit_5_8 = bits (insn1, 5, 8); |
7110 | unsigned int bit_9 = bit (insn1, 9); | |
7111 | unsigned int bit_4 = bit (insn1, 4); | |
34518530 YQ |
7112 | |
7113 | if (bit_9 == 0) | |
7114 | { | |
7115 | if (bit_5_8 == 2) | |
7116 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7117 | "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2", | |
7118 | dsc); | |
7119 | else if (bit_5_8 == 0) /* UNDEFINED. */ | |
7120 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7121 | else | |
7122 | { | |
7123 | /*coproc is 101x. SIMD/VFP, ext registers load/store. */ | |
7124 | if ((coproc & 0xe) == 0xa) | |
7125 | return thumb2_decode_ext_reg_ld_st (gdbarch, insn1, insn2, regs, | |
7126 | dsc); | |
7127 | else /* coproc is not 101x. */ | |
7128 | { | |
7129 | if (bit_4 == 0) /* STC/STC2. */ | |
7130 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7131 | "stc/stc2", dsc); | |
405feb71 | 7132 | else /* LDC/LDC2 {literal, immediate}. */ |
34518530 YQ |
7133 | return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, |
7134 | regs, dsc); | |
7135 | } | |
7136 | } | |
7137 | } | |
7138 | else | |
7139 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc); | |
7140 | ||
7141 | return 0; | |
7142 | } | |
7143 | ||
7144 | static void | |
7145 | install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7146 | arm_displaced_step_copy_insn_closure *dsc, int rd) |
34518530 YQ |
7147 | { |
7148 | /* ADR Rd, #imm | |
7149 | ||
7150 | Rewrite as: | |
7151 | ||
7152 | Preparation: Rd <- PC | |
7153 | Insn: ADD Rd, #imm | |
7154 | Cleanup: Null. | |
7155 | */ | |
7156 | ||
7157 | /* Rd <- PC */ | |
7158 | int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7159 | displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC); | |
7160 | } | |
7161 | ||
7162 | static int | |
7163 | thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7164 | arm_displaced_step_copy_insn_closure *dsc, |
34518530 YQ |
7165 | int rd, unsigned int imm) |
7166 | { | |
7167 | ||
7168 | /* Encoding T2: ADDS Rd, #imm */ | |
7169 | dsc->modinsn[0] = (0x3000 | (rd << 8) | imm); | |
7170 | ||
7171 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7172 | ||
7173 | return 0; | |
7174 | } | |
7175 | ||
7176 | static int | |
7177 | thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn, | |
7178 | struct regcache *regs, | |
1152d984 | 7179 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7180 | { |
7181 | unsigned int rd = bits (insn, 8, 10); | |
7182 | unsigned int imm8 = bits (insn, 0, 7); | |
7183 | ||
136821d9 SM |
7184 | displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x", |
7185 | rd, imm8, insn); | |
34518530 YQ |
7186 | |
7187 | return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8); | |
7188 | } | |
7189 | ||
7190 | static int | |
7191 | thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, | |
7192 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7193 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7194 | { |
7195 | unsigned int rd = bits (insn2, 8, 11); | |
7196 | /* Since immediate has the same encoding in ADR ADD and SUB, so we simply | |
7197 | extract raw immediate encoding rather than computing immediate. When | |
7198 | generating ADD or SUB instruction, we can simply perform OR operation to | |
7199 | set immediate into ADD. */ | |
7200 | unsigned int imm_3_8 = insn2 & 0x70ff; | |
7201 | unsigned int imm_i = insn1 & 0x0400; /* Clear all bits except bit 10. */ | |
7202 | ||
136821d9 SM |
7203 | displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x", |
7204 | rd, imm_i, imm_3_8, insn1, insn2); | |
34518530 YQ |
7205 | |
7206 | if (bit (insn1, 7)) /* Encoding T2 */ | |
7207 | { | |
7208 | /* Encoding T3: SUB Rd, Rd, #imm */ | |
7209 | dsc->modinsn[0] = (0xf1a0 | rd | imm_i); | |
7210 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7211 | } | |
7212 | else /* Encoding T3 */ | |
7213 | { | |
7214 | /* Encoding T3: ADD Rd, Rd, #imm */ | |
7215 | dsc->modinsn[0] = (0xf100 | rd | imm_i); | |
7216 | dsc->modinsn[1] = ((rd << 8) | imm_3_8); | |
7217 | } | |
7218 | dsc->numinsns = 2; | |
7219 | ||
7220 | install_pc_relative (gdbarch, regs, dsc, rd); | |
7221 | ||
7222 | return 0; | |
7223 | } | |
7224 | ||
7225 | static int | |
615234c1 | 7226 | thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7227 | struct regcache *regs, |
1152d984 | 7228 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7229 | { |
7230 | unsigned int rt = bits (insn1, 8, 10); | |
7231 | unsigned int pc; | |
7232 | int imm8 = (bits (insn1, 0, 7) << 2); | |
34518530 YQ |
7233 | |
7234 | /* LDR Rd, #imm8 | |
7235 | ||
7236 | Rwrite as: | |
7237 | ||
7238 | Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8; | |
7239 | ||
7240 | Insn: LDR R0, [R2, R3]; | |
7241 | Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */ | |
7242 | ||
136821d9 | 7243 | displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt, imm8); |
34518530 YQ |
7244 | |
7245 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 0); | |
7246 | dsc->tmp[2] = displaced_read_reg (regs, dsc, 2); | |
7247 | dsc->tmp[3] = displaced_read_reg (regs, dsc, 3); | |
7248 | pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM); | |
7249 | /* The assembler calculates the required value of the offset from the | |
7250 | Align(PC,4) value of this instruction to the label. */ | |
7251 | pc = pc & 0xfffffffc; | |
7252 | ||
7253 | displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC); | |
7254 | displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC); | |
7255 | ||
7256 | dsc->rd = rt; | |
7257 | dsc->u.ldst.xfersize = 4; | |
7258 | dsc->u.ldst.rn = 0; | |
7259 | dsc->u.ldst.immed = 0; | |
7260 | dsc->u.ldst.writeback = 0; | |
7261 | dsc->u.ldst.restore_r4 = 0; | |
7262 | ||
7263 | dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/ | |
7264 | ||
7265 | dsc->cleanup = &cleanup_load; | |
7266 | ||
7267 | return 0; | |
7268 | } | |
7269 | ||
405feb71 | 7270 | /* Copy Thumb cbnz/cbz instruction. */ |
34518530 YQ |
7271 | |
7272 | static int | |
7273 | thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1, | |
7274 | struct regcache *regs, | |
1152d984 | 7275 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7276 | { |
7277 | int non_zero = bit (insn1, 11); | |
7278 | unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1); | |
7279 | CORE_ADDR from = dsc->insn_addr; | |
7280 | int rn = bits (insn1, 0, 2); | |
7281 | int rn_val = displaced_read_reg (regs, dsc, rn); | |
7282 | ||
7283 | dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero); | |
7284 | /* CBNZ and CBZ do not affect the condition flags. If condition is true, | |
7285 | set it INST_AL, so cleanup_branch will know branch is taken, otherwise, | |
7286 | condition is false, let it be, cleanup_branch will do nothing. */ | |
7287 | if (dsc->u.branch.cond) | |
7288 | { | |
7289 | dsc->u.branch.cond = INST_AL; | |
7290 | dsc->u.branch.dest = from + 4 + imm5; | |
7291 | } | |
7292 | else | |
7293 | dsc->u.branch.dest = from + 2; | |
7294 | ||
7295 | dsc->u.branch.link = 0; | |
7296 | dsc->u.branch.exchange = 0; | |
7297 | ||
136821d9 SM |
7298 | displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx", |
7299 | non_zero ? "cbnz" : "cbz", | |
7300 | rn, rn_val, insn1, dsc->u.branch.dest); | |
34518530 YQ |
7301 | |
7302 | dsc->modinsn[0] = THUMB_NOP; | |
7303 | ||
7304 | dsc->cleanup = &cleanup_branch; | |
7305 | return 0; | |
7306 | } | |
7307 | ||
7308 | /* Copy Table Branch Byte/Halfword */ | |
7309 | static int | |
7310 | thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1, | |
7311 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7312 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7313 | { |
7314 | ULONGEST rn_val, rm_val; | |
7315 | int is_tbh = bit (insn2, 4); | |
7316 | CORE_ADDR halfwords = 0; | |
7317 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7318 | ||
7319 | rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3)); | |
7320 | rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3)); | |
7321 | ||
7322 | if (is_tbh) | |
7323 | { | |
7324 | gdb_byte buf[2]; | |
7325 | ||
7326 | target_read_memory (rn_val + 2 * rm_val, buf, 2); | |
7327 | halfwords = extract_unsigned_integer (buf, 2, byte_order); | |
7328 | } | |
7329 | else | |
7330 | { | |
7331 | gdb_byte buf[1]; | |
7332 | ||
7333 | target_read_memory (rn_val + rm_val, buf, 1); | |
7334 | halfwords = extract_unsigned_integer (buf, 1, byte_order); | |
7335 | } | |
7336 | ||
136821d9 SM |
7337 | displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x", |
7338 | is_tbh ? "tbh" : "tbb", | |
7339 | (unsigned int) rn_val, (unsigned int) rm_val, | |
7340 | (unsigned int) halfwords); | |
34518530 YQ |
7341 | |
7342 | dsc->u.branch.cond = INST_AL; | |
7343 | dsc->u.branch.link = 0; | |
7344 | dsc->u.branch.exchange = 0; | |
7345 | dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords; | |
7346 | ||
7347 | dsc->cleanup = &cleanup_branch; | |
7348 | ||
7349 | return 0; | |
7350 | } | |
7351 | ||
7352 | static void | |
7353 | cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, | |
1152d984 | 7354 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7355 | { |
7356 | /* PC <- r7 */ | |
7357 | int val = displaced_read_reg (regs, dsc, 7); | |
7358 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC); | |
7359 | ||
7360 | /* r7 <- r8 */ | |
7361 | val = displaced_read_reg (regs, dsc, 8); | |
7362 | displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC); | |
7363 | ||
7364 | /* r8 <- tmp[0] */ | |
7365 | displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC); | |
7366 | ||
7367 | } | |
7368 | ||
7369 | static int | |
615234c1 | 7370 | thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, |
34518530 | 7371 | struct regcache *regs, |
1152d984 | 7372 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7373 | { |
7374 | dsc->u.block.regmask = insn1 & 0x00ff; | |
7375 | ||
7376 | /* Rewrite instruction: POP {rX, rY, ...,rZ, PC} | |
7377 | to : | |
7378 | ||
7379 | (1) register list is full, that is, r0-r7 are used. | |
7380 | Prepare: tmp[0] <- r8 | |
7381 | ||
7382 | POP {r0, r1, ...., r6, r7}; remove PC from reglist | |
7383 | MOV r8, r7; Move value of r7 to r8; | |
7384 | POP {r7}; Store PC value into r7. | |
7385 | ||
7386 | Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0] | |
7387 | ||
7388 | (2) register list is not full, supposing there are N registers in | |
7389 | register list (except PC, 0 <= N <= 7). | |
7390 | Prepare: for each i, 0 - N, tmp[i] <- ri. | |
7391 | ||
7392 | POP {r0, r1, ...., rN}; | |
7393 | ||
7394 | Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN | |
7395 | from tmp[] properly. | |
7396 | */ | |
136821d9 SM |
7397 | displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x", |
7398 | dsc->u.block.regmask, insn1); | |
34518530 YQ |
7399 | |
7400 | if (dsc->u.block.regmask == 0xff) | |
7401 | { | |
7402 | dsc->tmp[0] = displaced_read_reg (regs, dsc, 8); | |
7403 | ||
7404 | dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */ | |
7405 | dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */ | |
7406 | dsc->modinsn[2] = 0xbc80; /* POP {r7} */ | |
7407 | ||
7408 | dsc->numinsns = 3; | |
7409 | dsc->cleanup = &cleanup_pop_pc_16bit_all; | |
7410 | } | |
7411 | else | |
7412 | { | |
5f661e03 | 7413 | unsigned int num_in_list = count_one_bits (dsc->u.block.regmask); |
bec2ab5a SM |
7414 | unsigned int i; |
7415 | unsigned int new_regmask; | |
34518530 YQ |
7416 | |
7417 | for (i = 0; i < num_in_list + 1; i++) | |
7418 | dsc->tmp[i] = displaced_read_reg (regs, dsc, i); | |
7419 | ||
7420 | new_regmask = (1 << (num_in_list + 1)) - 1; | |
7421 | ||
136821d9 SM |
7422 | displaced_debug_printf ("POP {..., pc}: original reg list %.4x, " |
7423 | "modified list %.4x", | |
7424 | (int) dsc->u.block.regmask, new_regmask); | |
34518530 YQ |
7425 | |
7426 | dsc->u.block.regmask |= 0x8000; | |
7427 | dsc->u.block.writeback = 0; | |
7428 | dsc->u.block.cond = INST_AL; | |
7429 | ||
7430 | dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff); | |
7431 | ||
7432 | dsc->cleanup = &cleanup_block_load_pc; | |
7433 | } | |
7434 | ||
7435 | return 0; | |
7436 | } | |
7437 | ||
7438 | static void | |
7439 | thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7440 | struct regcache *regs, | |
1152d984 | 7441 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7442 | { |
7443 | unsigned short op_bit_12_15 = bits (insn1, 12, 15); | |
7444 | unsigned short op_bit_10_11 = bits (insn1, 10, 11); | |
7445 | int err = 0; | |
7446 | ||
7447 | /* 16-bit thumb instructions. */ | |
7448 | switch (op_bit_12_15) | |
7449 | { | |
7450 | /* Shift (imme), add, subtract, move and compare. */ | |
7451 | case 0: case 1: case 2: case 3: | |
7452 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7453 | "shift/add/sub/mov/cmp", | |
7454 | dsc); | |
7455 | break; | |
7456 | case 4: | |
7457 | switch (op_bit_10_11) | |
7458 | { | |
7459 | case 0: /* Data-processing */ | |
7460 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, | |
7461 | "data-processing", | |
7462 | dsc); | |
7463 | break; | |
7464 | case 1: /* Special data instructions and branch and exchange. */ | |
7465 | { | |
7466 | unsigned short op = bits (insn1, 7, 9); | |
7467 | if (op == 6 || op == 7) /* BX or BLX */ | |
7468 | err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc); | |
7469 | else if (bits (insn1, 6, 7) != 0) /* ADD/MOV/CMP high registers. */ | |
7470 | err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc); | |
7471 | else | |
7472 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "special data", | |
7473 | dsc); | |
7474 | } | |
7475 | break; | |
7476 | default: /* LDR (literal) */ | |
7477 | err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc); | |
7478 | } | |
7479 | break; | |
7480 | case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */ | |
7481 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc); | |
7482 | break; | |
7483 | case 10: | |
7484 | if (op_bit_10_11 < 2) /* Generate PC-relative address */ | |
7485 | err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc); | |
7486 | else /* Generate SP-relative address */ | |
7487 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc); | |
7488 | break; | |
7489 | case 11: /* Misc 16-bit instructions */ | |
7490 | { | |
7491 | switch (bits (insn1, 8, 11)) | |
7492 | { | |
7493 | case 1: case 3: case 9: case 11: /* CBNZ, CBZ */ | |
7494 | err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc); | |
7495 | break; | |
7496 | case 12: case 13: /* POP */ | |
7497 | if (bit (insn1, 8)) /* PC is in register list. */ | |
7498 | err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc); | |
7499 | else | |
7500 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc); | |
7501 | break; | |
7502 | case 15: /* If-Then, and hints */ | |
7503 | if (bits (insn1, 0, 3)) | |
7504 | /* If-Then makes up to four following instructions conditional. | |
7505 | IT instruction itself is not conditional, so handle it as a | |
7506 | common unmodified instruction. */ | |
7507 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "If-Then", | |
7508 | dsc); | |
7509 | else | |
7510 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc); | |
7511 | break; | |
7512 | default: | |
7513 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc); | |
7514 | } | |
7515 | } | |
7516 | break; | |
7517 | case 12: | |
7518 | if (op_bit_10_11 < 2) /* Store multiple registers */ | |
7519 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc); | |
7520 | else /* Load multiple registers */ | |
7521 | err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc); | |
7522 | break; | |
7523 | case 13: /* Conditional branch and supervisor call */ | |
7524 | if (bits (insn1, 9, 11) != 7) /* conditional branch */ | |
7525 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7526 | else | |
7527 | err = thumb_copy_svc (gdbarch, insn1, regs, dsc); | |
7528 | break; | |
7529 | case 14: /* Unconditional branch */ | |
7530 | err = thumb_copy_b (gdbarch, insn1, dsc); | |
7531 | break; | |
7532 | default: | |
7533 | err = 1; | |
7534 | } | |
7535 | ||
7536 | if (err) | |
7537 | internal_error (__FILE__, __LINE__, | |
7538 | _("thumb_process_displaced_16bit_insn: Instruction decode error")); | |
7539 | } | |
7540 | ||
7541 | static int | |
7542 | decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, | |
7543 | uint16_t insn1, uint16_t insn2, | |
7544 | struct regcache *regs, | |
1152d984 | 7545 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7546 | { |
7547 | int rt = bits (insn2, 12, 15); | |
7548 | int rn = bits (insn1, 0, 3); | |
7549 | int op1 = bits (insn1, 7, 8); | |
34518530 YQ |
7550 | |
7551 | switch (bits (insn1, 5, 6)) | |
7552 | { | |
7553 | case 0: /* Load byte and memory hints */ | |
7554 | if (rt == 0xf) /* PLD/PLI */ | |
7555 | { | |
7556 | if (rn == 0xf) | |
7557 | /* PLD literal or Encoding T3 of PLI(immediate, literal). */ | |
7558 | return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc); | |
7559 | else | |
7560 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7561 | "pli/pld", dsc); | |
7562 | } | |
7563 | else | |
7564 | { | |
7565 | if (rn == 0xf) /* LDRB/LDRSB (literal) */ | |
7566 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7567 | 1); | |
7568 | else | |
7569 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7570 | "ldrb{reg, immediate}/ldrbt", | |
7571 | dsc); | |
7572 | } | |
7573 | ||
7574 | break; | |
7575 | case 1: /* Load halfword and memory hints. */ | |
7576 | if (rt == 0xf) /* PLD{W} and Unalloc memory hint. */ | |
7577 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7578 | "pld/unalloc memhint", dsc); | |
7579 | else | |
7580 | { | |
7581 | if (rn == 0xf) | |
7582 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, | |
7583 | 2); | |
7584 | else | |
7585 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7586 | "ldrh/ldrht", dsc); | |
7587 | } | |
7588 | break; | |
7589 | case 2: /* Load word */ | |
7590 | { | |
7591 | int insn2_bit_8_11 = bits (insn2, 8, 11); | |
7592 | ||
7593 | if (rn == 0xf) | |
7594 | return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4); | |
7595 | else if (op1 == 0x1) /* Encoding T3 */ | |
7596 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc, | |
7597 | 0, 1); | |
7598 | else /* op1 == 0x0 */ | |
7599 | { | |
7600 | if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9) | |
7601 | /* LDR (immediate) */ | |
7602 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7603 | dsc, bit (insn2, 8), 1); | |
7604 | else if (insn2_bit_8_11 == 0xe) /* LDRT */ | |
7605 | return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7606 | "ldrt", dsc); | |
7607 | else | |
7608 | /* LDR (register) */ | |
7609 | return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, | |
7610 | dsc, 0, 0); | |
7611 | } | |
7612 | break; | |
7613 | } | |
7614 | default: | |
7615 | return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc); | |
7616 | break; | |
7617 | } | |
7618 | return 0; | |
7619 | } | |
7620 | ||
7621 | static void | |
7622 | thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, | |
7623 | uint16_t insn2, struct regcache *regs, | |
1152d984 | 7624 | arm_displaced_step_copy_insn_closure *dsc) |
34518530 YQ |
7625 | { |
7626 | int err = 0; | |
7627 | unsigned short op = bit (insn2, 15); | |
7628 | unsigned int op1 = bits (insn1, 11, 12); | |
7629 | ||
7630 | switch (op1) | |
7631 | { | |
7632 | case 1: | |
7633 | { | |
7634 | switch (bits (insn1, 9, 10)) | |
7635 | { | |
7636 | case 0: | |
7637 | if (bit (insn1, 6)) | |
7638 | { | |
405feb71 | 7639 | /* Load/store {dual, exclusive}, table branch. */ |
34518530 YQ |
7640 | if (bits (insn1, 7, 8) == 1 && bits (insn1, 4, 5) == 1 |
7641 | && bits (insn2, 5, 7) == 0) | |
7642 | err = thumb2_copy_table_branch (gdbarch, insn1, insn2, regs, | |
7643 | dsc); | |
7644 | else | |
7645 | /* PC is not allowed to use in load/store {dual, exclusive} | |
7646 | instructions. */ | |
7647 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7648 | "load/store dual/ex", dsc); | |
7649 | } | |
7650 | else /* load/store multiple */ | |
7651 | { | |
7652 | switch (bits (insn1, 7, 8)) | |
7653 | { | |
7654 | case 0: case 3: /* SRS, RFE */ | |
7655 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7656 | "srs/rfe", dsc); | |
7657 | break; | |
7658 | case 1: case 2: /* LDM/STM/PUSH/POP */ | |
7659 | err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc); | |
7660 | break; | |
7661 | } | |
7662 | } | |
7663 | break; | |
7664 | ||
7665 | case 1: | |
7666 | /* Data-processing (shift register). */ | |
7667 | err = thumb2_decode_dp_shift_reg (gdbarch, insn1, insn2, regs, | |
7668 | dsc); | |
7669 | break; | |
7670 | default: /* Coprocessor instructions. */ | |
7671 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7672 | break; | |
7673 | } | |
7674 | break; | |
7675 | } | |
7676 | case 2: /* op1 = 2 */ | |
7677 | if (op) /* Branch and misc control. */ | |
7678 | { | |
7679 | if (bit (insn2, 14) /* BLX/BL */ | |
7680 | || bit (insn2, 12) /* Unconditional branch */ | |
7681 | || (bits (insn1, 7, 9) != 0x7)) /* Conditional branch */ | |
7682 | err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc); | |
7683 | else | |
7684 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7685 | "misc ctrl", dsc); | |
7686 | } | |
7687 | else | |
7688 | { | |
7689 | if (bit (insn1, 9)) /* Data processing (plain binary imm). */ | |
7690 | { | |
b926417a | 7691 | int dp_op = bits (insn1, 4, 8); |
34518530 | 7692 | int rn = bits (insn1, 0, 3); |
b926417a | 7693 | if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf) |
34518530 YQ |
7694 | err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2, |
7695 | regs, dsc); | |
7696 | else | |
7697 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7698 | "dp/pb", dsc); | |
7699 | } | |
405feb71 | 7700 | else /* Data processing (modified immediate) */ |
34518530 YQ |
7701 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, |
7702 | "dp/mi", dsc); | |
7703 | } | |
7704 | break; | |
7705 | case 3: /* op1 = 3 */ | |
7706 | switch (bits (insn1, 9, 10)) | |
7707 | { | |
7708 | case 0: | |
7709 | if (bit (insn1, 4)) | |
7710 | err = decode_thumb_32bit_ld_mem_hints (gdbarch, insn1, insn2, | |
7711 | regs, dsc); | |
7712 | else /* NEON Load/Store and Store single data item */ | |
7713 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7714 | "neon elt/struct load/store", | |
7715 | dsc); | |
7716 | break; | |
7717 | case 1: /* op1 = 3, bits (9, 10) == 1 */ | |
7718 | switch (bits (insn1, 7, 8)) | |
7719 | { | |
7720 | case 0: case 1: /* Data processing (register) */ | |
7721 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7722 | "dp(reg)", dsc); | |
7723 | break; | |
7724 | case 2: /* Multiply and absolute difference */ | |
7725 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7726 | "mul/mua/diff", dsc); | |
7727 | break; | |
7728 | case 3: /* Long multiply and divide */ | |
7729 | err = thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, | |
7730 | "lmul/lmua", dsc); | |
7731 | break; | |
7732 | } | |
7733 | break; | |
7734 | default: /* Coprocessor instructions */ | |
7735 | err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc); | |
7736 | break; | |
7737 | } | |
7738 | break; | |
7739 | default: | |
7740 | err = 1; | |
7741 | } | |
7742 | ||
7743 | if (err) | |
7744 | internal_error (__FILE__, __LINE__, | |
7745 | _("thumb_process_displaced_32bit_insn: Instruction decode error")); | |
7746 | ||
7747 | } | |
7748 | ||
b434a28f YQ |
7749 | static void |
7750 | thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, | |
12545665 | 7751 | struct regcache *regs, |
1152d984 | 7752 | arm_displaced_step_copy_insn_closure *dsc) |
b434a28f | 7753 | { |
34518530 YQ |
7754 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7755 | uint16_t insn1 | |
7756 | = read_memory_unsigned_integer (from, 2, byte_order_for_code); | |
7757 | ||
136821d9 SM |
7758 | displaced_debug_printf ("process thumb insn %.4x at %.8lx", |
7759 | insn1, (unsigned long) from); | |
34518530 YQ |
7760 | |
7761 | dsc->is_thumb = 1; | |
7762 | dsc->insn_size = thumb_insn_size (insn1); | |
7763 | if (thumb_insn_size (insn1) == 4) | |
7764 | { | |
7765 | uint16_t insn2 | |
7766 | = read_memory_unsigned_integer (from + 2, 2, byte_order_for_code); | |
7767 | thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc); | |
7768 | } | |
7769 | else | |
7770 | thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc); | |
b434a28f YQ |
7771 | } |
7772 | ||
cca44b1b | 7773 | void |
b434a28f YQ |
7774 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
7775 | CORE_ADDR to, struct regcache *regs, | |
1152d984 | 7776 | arm_displaced_step_copy_insn_closure *dsc) |
cca44b1b JB |
7777 | { |
7778 | int err = 0; | |
b434a28f YQ |
7779 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
7780 | uint32_t insn; | |
cca44b1b JB |
7781 | |
7782 | /* Most displaced instructions use a 1-instruction scratch space, so set this | |
7783 | here and override below if/when necessary. */ | |
7784 | dsc->numinsns = 1; | |
7785 | dsc->insn_addr = from; | |
7786 | dsc->scratch_base = to; | |
7787 | dsc->cleanup = NULL; | |
7788 | dsc->wrote_to_pc = 0; | |
7789 | ||
b434a28f | 7790 | if (!displaced_in_arm_mode (regs)) |
12545665 | 7791 | return thumb_process_displaced_insn (gdbarch, from, regs, dsc); |
b434a28f | 7792 | |
4db71c0b YQ |
7793 | dsc->is_thumb = 0; |
7794 | dsc->insn_size = 4; | |
b434a28f | 7795 | insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
136821d9 SM |
7796 | displaced_debug_printf ("stepping insn %.8lx at %.8lx", |
7797 | (unsigned long) insn, (unsigned long) from); | |
b434a28f | 7798 | |
cca44b1b | 7799 | if ((insn & 0xf0000000) == 0xf0000000) |
7ff120b4 | 7800 | err = arm_decode_unconditional (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7801 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
7802 | { | |
7803 | case 0x0: case 0x1: case 0x2: case 0x3: | |
7ff120b4 | 7804 | err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7805 | break; |
7806 | ||
7807 | case 0x4: case 0x5: case 0x6: | |
7ff120b4 | 7808 | err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7809 | break; |
7810 | ||
7811 | case 0x7: | |
7ff120b4 | 7812 | err = arm_decode_media (gdbarch, insn, dsc); |
cca44b1b JB |
7813 | break; |
7814 | ||
7815 | case 0x8: case 0x9: case 0xa: case 0xb: | |
7ff120b4 | 7816 | err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7817 | break; |
7818 | ||
7819 | case 0xc: case 0xd: case 0xe: case 0xf: | |
12545665 | 7820 | err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); |
cca44b1b JB |
7821 | break; |
7822 | } | |
7823 | ||
7824 | if (err) | |
7825 | internal_error (__FILE__, __LINE__, | |
7826 | _("arm_process_displaced_insn: Instruction decode error")); | |
7827 | } | |
7828 | ||
7829 | /* Actually set up the scratch space for a displaced instruction. */ | |
7830 | ||
7831 | void | |
7832 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, | |
1152d984 SM |
7833 | CORE_ADDR to, |
7834 | arm_displaced_step_copy_insn_closure *dsc) | |
cca44b1b | 7835 | { |
345bd07c | 7836 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
4db71c0b | 7837 | unsigned int i, len, offset; |
cca44b1b | 7838 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
4db71c0b | 7839 | int size = dsc->is_thumb? 2 : 4; |
948f8e3d | 7840 | const gdb_byte *bkp_insn; |
cca44b1b | 7841 | |
4db71c0b | 7842 | offset = 0; |
cca44b1b JB |
7843 | /* Poke modified instruction(s). */ |
7844 | for (i = 0; i < dsc->numinsns; i++) | |
7845 | { | |
136821d9 SM |
7846 | if (size == 4) |
7847 | displaced_debug_printf ("writing insn %.8lx at %.8lx", | |
7848 | dsc->modinsn[i], (unsigned long) to + offset); | |
7849 | else if (size == 2) | |
7850 | displaced_debug_printf ("writing insn %.4x at %.8lx", | |
7851 | (unsigned short) dsc->modinsn[i], | |
7852 | (unsigned long) to + offset); | |
4db71c0b | 7853 | |
4db71c0b YQ |
7854 | write_memory_unsigned_integer (to + offset, size, |
7855 | byte_order_for_code, | |
cca44b1b | 7856 | dsc->modinsn[i]); |
4db71c0b YQ |
7857 | offset += size; |
7858 | } | |
7859 | ||
7860 | /* Choose the correct breakpoint instruction. */ | |
7861 | if (dsc->is_thumb) | |
7862 | { | |
7863 | bkp_insn = tdep->thumb_breakpoint; | |
7864 | len = tdep->thumb_breakpoint_size; | |
7865 | } | |
7866 | else | |
7867 | { | |
7868 | bkp_insn = tdep->arm_breakpoint; | |
7869 | len = tdep->arm_breakpoint_size; | |
cca44b1b JB |
7870 | } |
7871 | ||
7872 | /* Put breakpoint afterwards. */ | |
4db71c0b | 7873 | write_memory (to + offset, bkp_insn, len); |
cca44b1b | 7874 | |
136821d9 SM |
7875 | displaced_debug_printf ("copy %s->%s", paddress (gdbarch, from), |
7876 | paddress (gdbarch, to)); | |
cca44b1b JB |
7877 | } |
7878 | ||
cca44b1b JB |
7879 | /* Entry point for cleaning things up after a displaced instruction has been |
7880 | single-stepped. */ | |
7881 | ||
7882 | void | |
7883 | arm_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 7884 | struct displaced_step_copy_insn_closure *dsc_, |
cca44b1b JB |
7885 | CORE_ADDR from, CORE_ADDR to, |
7886 | struct regcache *regs) | |
7887 | { | |
1152d984 SM |
7888 | arm_displaced_step_copy_insn_closure *dsc |
7889 | = (arm_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 7890 | |
cca44b1b JB |
7891 | if (dsc->cleanup) |
7892 | dsc->cleanup (gdbarch, regs, dsc); | |
7893 | ||
7894 | if (!dsc->wrote_to_pc) | |
4db71c0b YQ |
7895 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, |
7896 | dsc->insn_addr + dsc->insn_size); | |
7897 | ||
cca44b1b JB |
7898 | } |
7899 | ||
7900 | #include "bfd-in2.h" | |
7901 | #include "libcoff.h" | |
7902 | ||
7903 | static int | |
7904 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) | |
7905 | { | |
e47ad6c0 YQ |
7906 | gdb_disassembler *di |
7907 | = static_cast<gdb_disassembler *>(info->application_data); | |
7908 | struct gdbarch *gdbarch = di->arch (); | |
9779414d DJ |
7909 | |
7910 | if (arm_pc_is_thumb (gdbarch, memaddr)) | |
cca44b1b JB |
7911 | { |
7912 | static asymbol *asym; | |
7913 | static combined_entry_type ce; | |
7914 | static struct coff_symbol_struct csym; | |
7915 | static struct bfd fake_bfd; | |
7916 | static bfd_target fake_target; | |
7917 | ||
7918 | if (csym.native == NULL) | |
7919 | { | |
7920 | /* Create a fake symbol vector containing a Thumb symbol. | |
7921 | This is solely so that the code in print_insn_little_arm() | |
7922 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
7923 | the presence of a Thumb symbol and switch to decoding | |
7924 | Thumb instructions. */ | |
7925 | ||
7926 | fake_target.flavour = bfd_target_coff_flavour; | |
7927 | fake_bfd.xvec = &fake_target; | |
7928 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; | |
7929 | csym.native = &ce; | |
7930 | csym.symbol.the_bfd = &fake_bfd; | |
7931 | csym.symbol.name = "fake"; | |
7932 | asym = (asymbol *) & csym; | |
7933 | } | |
7934 | ||
7935 | memaddr = UNMAKE_THUMB_ADDR (memaddr); | |
7936 | info->symbols = &asym; | |
7937 | } | |
7938 | else | |
7939 | info->symbols = NULL; | |
7940 | ||
e60eb288 YQ |
7941 | /* GDB is able to get bfd_mach from the exe_bfd, info->mach is |
7942 | accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise, | |
7943 | opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger | |
7e10abd1 TT |
7944 | the assert on the mismatch of info->mach and |
7945 | bfd_get_mach (current_program_space->exec_bfd ()) in | |
7946 | default_print_insn. */ | |
3047c786 TV |
7947 | if (current_program_space->exec_bfd () != NULL |
7948 | && (current_program_space->exec_bfd ()->arch_info | |
7949 | == gdbarch_bfd_arch_info (gdbarch))) | |
e60eb288 YQ |
7950 | info->flags |= USER_SPECIFIED_MACHINE_TYPE; |
7951 | ||
6394c606 | 7952 | return default_print_insn (memaddr, info); |
cca44b1b JB |
7953 | } |
7954 | ||
7955 | /* The following define instruction sequences that will cause ARM | |
7956 | cpu's to take an undefined instruction trap. These are used to | |
7957 | signal a breakpoint to GDB. | |
7958 | ||
7959 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
7960 | modes. A different instruction is required for each mode. The ARM | |
7961 | cpu's can also be big or little endian. Thus four different | |
7962 | instructions are needed to support all cases. | |
7963 | ||
7964 | Note: ARMv4 defines several new instructions that will take the | |
7965 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
7966 | not in fact add the new instructions. The new undefined | |
7967 | instructions in ARMv4 are all instructions that had no defined | |
7968 | behaviour in earlier chips. There is no guarantee that they will | |
7969 | raise an exception, but may be treated as NOP's. In practice, it | |
7970 | may only safe to rely on instructions matching: | |
7971 | ||
7972 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
7973 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
7974 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
7975 | ||
0963b4bd | 7976 | Even this may only true if the condition predicate is true. The |
cca44b1b JB |
7977 | following use a condition predicate of ALWAYS so it is always TRUE. |
7978 | ||
7979 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
7980 | and NetBSD all use a software interrupt rather than an undefined | |
7981 | instruction to force a trap. This can be handled by by the | |
7982 | abi-specific code during establishment of the gdbarch vector. */ | |
7983 | ||
7984 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
7985 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
7986 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} | |
7987 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
7988 | ||
948f8e3d PA |
7989 | static const gdb_byte arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
7990 | static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
7991 | static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
7992 | static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
cca44b1b | 7993 | |
cd6c3b4f YQ |
7994 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7995 | ||
d19280ad YQ |
7996 | static int |
7997 | arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cca44b1b | 7998 | { |
345bd07c | 7999 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
177321bd | 8000 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
cca44b1b | 8001 | |
9779414d | 8002 | if (arm_pc_is_thumb (gdbarch, *pcptr)) |
cca44b1b JB |
8003 | { |
8004 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
177321bd DJ |
8005 | |
8006 | /* If we have a separate 32-bit breakpoint instruction for Thumb-2, | |
8007 | check whether we are replacing a 32-bit instruction. */ | |
8008 | if (tdep->thumb2_breakpoint != NULL) | |
8009 | { | |
8010 | gdb_byte buf[2]; | |
d19280ad | 8011 | |
177321bd DJ |
8012 | if (target_read_memory (*pcptr, buf, 2) == 0) |
8013 | { | |
8014 | unsigned short inst1; | |
d19280ad | 8015 | |
177321bd | 8016 | inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); |
db24da6d | 8017 | if (thumb_insn_size (inst1) == 4) |
d19280ad | 8018 | return ARM_BP_KIND_THUMB2; |
177321bd DJ |
8019 | } |
8020 | } | |
8021 | ||
d19280ad | 8022 | return ARM_BP_KIND_THUMB; |
cca44b1b JB |
8023 | } |
8024 | else | |
d19280ad YQ |
8025 | return ARM_BP_KIND_ARM; |
8026 | ||
8027 | } | |
8028 | ||
cd6c3b4f YQ |
8029 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
8030 | ||
d19280ad YQ |
8031 | static const gdb_byte * |
8032 | arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
8033 | { | |
345bd07c | 8034 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
d19280ad YQ |
8035 | |
8036 | switch (kind) | |
cca44b1b | 8037 | { |
d19280ad YQ |
8038 | case ARM_BP_KIND_ARM: |
8039 | *size = tdep->arm_breakpoint_size; | |
cca44b1b | 8040 | return tdep->arm_breakpoint; |
d19280ad YQ |
8041 | case ARM_BP_KIND_THUMB: |
8042 | *size = tdep->thumb_breakpoint_size; | |
8043 | return tdep->thumb_breakpoint; | |
8044 | case ARM_BP_KIND_THUMB2: | |
8045 | *size = tdep->thumb2_breakpoint_size; | |
8046 | return tdep->thumb2_breakpoint; | |
8047 | default: | |
8048 | gdb_assert_not_reached ("unexpected arm breakpoint kind"); | |
cca44b1b JB |
8049 | } |
8050 | } | |
8051 | ||
833b7ab5 YQ |
8052 | /* Implement the breakpoint_kind_from_current_state gdbarch method. */ |
8053 | ||
8054 | static int | |
8055 | arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, | |
8056 | struct regcache *regcache, | |
8057 | CORE_ADDR *pcptr) | |
8058 | { | |
8059 | gdb_byte buf[4]; | |
8060 | ||
8061 | /* Check the memory pointed by PC is readable. */ | |
8062 | if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) | |
8063 | { | |
8064 | struct arm_get_next_pcs next_pcs_ctx; | |
833b7ab5 YQ |
8065 | |
8066 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
8067 | &arm_get_next_pcs_ops, | |
8068 | gdbarch_byte_order (gdbarch), | |
8069 | gdbarch_byte_order_for_code (gdbarch), | |
8070 | 0, | |
8071 | regcache); | |
8072 | ||
a0ff9e1a | 8073 | std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx); |
833b7ab5 YQ |
8074 | |
8075 | /* If MEMADDR is the next instruction of current pc, do the | |
8076 | software single step computation, and get the thumb mode by | |
8077 | the destination address. */ | |
a0ff9e1a | 8078 | for (CORE_ADDR pc : next_pcs) |
833b7ab5 YQ |
8079 | { |
8080 | if (UNMAKE_THUMB_ADDR (pc) == *pcptr) | |
8081 | { | |
833b7ab5 YQ |
8082 | if (IS_THUMB_ADDR (pc)) |
8083 | { | |
8084 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
8085 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8086 | } | |
8087 | else | |
8088 | return ARM_BP_KIND_ARM; | |
8089 | } | |
8090 | } | |
833b7ab5 YQ |
8091 | } |
8092 | ||
8093 | return arm_breakpoint_kind_from_pc (gdbarch, pcptr); | |
8094 | } | |
8095 | ||
cca44b1b JB |
8096 | /* Extract from an array REGBUF containing the (raw) register state a |
8097 | function return value of type TYPE, and copy that, in virtual | |
8098 | format, into VALBUF. */ | |
8099 | ||
8100 | static void | |
8101 | arm_extract_return_value (struct type *type, struct regcache *regs, | |
8102 | gdb_byte *valbuf) | |
8103 | { | |
ac7936df | 8104 | struct gdbarch *gdbarch = regs->arch (); |
cca44b1b | 8105 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
345bd07c | 8106 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
cca44b1b | 8107 | |
78134374 | 8108 | if (TYPE_CODE_FLT == type->code ()) |
cca44b1b | 8109 | { |
345bd07c | 8110 | switch (tdep->fp_model) |
cca44b1b JB |
8111 | { |
8112 | case ARM_FLOAT_FPA: | |
8113 | { | |
8114 | /* The value is in register F0 in internal format. We need to | |
8115 | extract the raw value and then convert it to the desired | |
8116 | internal type. */ | |
f0452268 | 8117 | bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE]; |
cca44b1b | 8118 | |
dca08e1f | 8119 | regs->cooked_read (ARM_F0_REGNUM, tmpbuf); |
3b2ca824 UW |
8120 | target_float_convert (tmpbuf, arm_ext_type (gdbarch), |
8121 | valbuf, type); | |
cca44b1b JB |
8122 | } |
8123 | break; | |
8124 | ||
8125 | case ARM_FLOAT_SOFT_FPA: | |
8126 | case ARM_FLOAT_SOFT_VFP: | |
8127 | /* ARM_FLOAT_VFP can arise if this is a variadic function so | |
8128 | not using the VFP ABI code. */ | |
8129 | case ARM_FLOAT_VFP: | |
dca08e1f | 8130 | regs->cooked_read (ARM_A1_REGNUM, valbuf); |
cca44b1b | 8131 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8132 | regs->cooked_read (ARM_A1_REGNUM + 1, |
8133 | valbuf + ARM_INT_REGISTER_SIZE); | |
cca44b1b JB |
8134 | break; |
8135 | ||
8136 | default: | |
0963b4bd MS |
8137 | internal_error (__FILE__, __LINE__, |
8138 | _("arm_extract_return_value: " | |
8139 | "Floating point model not supported")); | |
cca44b1b JB |
8140 | break; |
8141 | } | |
8142 | } | |
78134374 SM |
8143 | else if (type->code () == TYPE_CODE_INT |
8144 | || type->code () == TYPE_CODE_CHAR | |
8145 | || type->code () == TYPE_CODE_BOOL | |
8146 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8147 | || TYPE_IS_REFERENCE (type) |
a6617193 JB |
8148 | || type->code () == TYPE_CODE_ENUM |
8149 | || is_fixed_point_type (type)) | |
cca44b1b | 8150 | { |
b021a221 MS |
8151 | /* If the type is a plain integer, then the access is |
8152 | straight-forward. Otherwise we have to play around a bit | |
8153 | more. */ | |
cca44b1b JB |
8154 | int len = TYPE_LENGTH (type); |
8155 | int regno = ARM_A1_REGNUM; | |
8156 | ULONGEST tmp; | |
8157 | ||
8158 | while (len > 0) | |
8159 | { | |
8160 | /* By using store_unsigned_integer we avoid having to do | |
8161 | anything special for small big-endian values. */ | |
8162 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
8163 | store_unsigned_integer (valbuf, | |
f0452268 AH |
8164 | (len > ARM_INT_REGISTER_SIZE |
8165 | ? ARM_INT_REGISTER_SIZE : len), | |
cca44b1b | 8166 | byte_order, tmp); |
f0452268 AH |
8167 | len -= ARM_INT_REGISTER_SIZE; |
8168 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8169 | } |
8170 | } | |
8171 | else | |
8172 | { | |
8173 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8174 | been stored to word-aligned memory and then loaded into |
8175 | registers with 32-bit load instruction(s). */ | |
cca44b1b JB |
8176 | int len = TYPE_LENGTH (type); |
8177 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8178 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
cca44b1b JB |
8179 | |
8180 | while (len > 0) | |
8181 | { | |
dca08e1f | 8182 | regs->cooked_read (regno++, tmpbuf); |
cca44b1b | 8183 | memcpy (valbuf, tmpbuf, |
f0452268 AH |
8184 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
8185 | len -= ARM_INT_REGISTER_SIZE; | |
8186 | valbuf += ARM_INT_REGISTER_SIZE; | |
cca44b1b JB |
8187 | } |
8188 | } | |
8189 | } | |
8190 | ||
8191 | ||
8192 | /* Will a function return an aggregate type in memory or in a | |
8193 | register? Return 0 if an aggregate type can be returned in a | |
8194 | register, 1 if it must be returned in memory. */ | |
8195 | ||
8196 | static int | |
8197 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
8198 | { | |
cca44b1b JB |
8199 | enum type_code code; |
8200 | ||
f168693b | 8201 | type = check_typedef (type); |
cca44b1b | 8202 | |
b13c8ab2 YQ |
8203 | /* Simple, non-aggregate types (ie not including vectors and |
8204 | complex) are always returned in a register (or registers). */ | |
78134374 | 8205 | code = type->code (); |
b13c8ab2 YQ |
8206 | if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code |
8207 | && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) | |
8208 | return 0; | |
cca44b1b | 8209 | |
bd63c870 | 8210 | if (TYPE_CODE_ARRAY == code && type->is_vector ()) |
c4312b19 YQ |
8211 | { |
8212 | /* Vector values should be returned using ARM registers if they | |
8213 | are not over 16 bytes. */ | |
8214 | return (TYPE_LENGTH (type) > 16); | |
8215 | } | |
8216 | ||
345bd07c SM |
8217 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
8218 | if (tdep->arm_abi != ARM_ABI_APCS) | |
cca44b1b | 8219 | { |
b13c8ab2 YQ |
8220 | /* The AAPCS says all aggregates not larger than a word are returned |
8221 | in a register. */ | |
bab22d06 LM |
8222 | if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE |
8223 | && language_pass_by_reference (type).trivially_copyable) | |
b13c8ab2 YQ |
8224 | return 0; |
8225 | ||
cca44b1b JB |
8226 | return 1; |
8227 | } | |
b13c8ab2 YQ |
8228 | else |
8229 | { | |
8230 | int nRc; | |
cca44b1b | 8231 | |
b13c8ab2 YQ |
8232 | /* All aggregate types that won't fit in a register must be returned |
8233 | in memory. */ | |
bab22d06 LM |
8234 | if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE |
8235 | || !language_pass_by_reference (type).trivially_copyable) | |
b13c8ab2 | 8236 | return 1; |
cca44b1b | 8237 | |
b13c8ab2 YQ |
8238 | /* In the ARM ABI, "integer" like aggregate types are returned in |
8239 | registers. For an aggregate type to be integer like, its size | |
f0452268 | 8240 | must be less than or equal to ARM_INT_REGISTER_SIZE and the |
b13c8ab2 YQ |
8241 | offset of each addressable subfield must be zero. Note that bit |
8242 | fields are not addressable, and all addressable subfields of | |
8243 | unions always start at offset zero. | |
cca44b1b | 8244 | |
b13c8ab2 YQ |
8245 | This function is based on the behaviour of GCC 2.95.1. |
8246 | See: gcc/arm.c: arm_return_in_memory() for details. | |
cca44b1b | 8247 | |
b13c8ab2 YQ |
8248 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
8249 | parameters correctly for a function returning the following | |
8250 | structure: struct { float f;}; This should be returned in memory, | |
8251 | not a register. Richard Earnshaw sent me a patch, but I do not | |
8252 | know of any way to detect if a function like the above has been | |
8253 | compiled with the correct calling convention. */ | |
8254 | ||
8255 | /* Assume all other aggregate types can be returned in a register. | |
8256 | Run a check for structures, unions and arrays. */ | |
8257 | nRc = 0; | |
67255d04 | 8258 | |
b13c8ab2 YQ |
8259 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
8260 | { | |
8261 | int i; | |
8262 | /* Need to check if this struct/union is "integer" like. For | |
8263 | this to be true, its size must be less than or equal to | |
f0452268 | 8264 | ARM_INT_REGISTER_SIZE and the offset of each addressable |
b13c8ab2 YQ |
8265 | subfield must be zero. Note that bit fields are not |
8266 | addressable, and unions always start at offset zero. If any | |
8267 | of the subfields is a floating point type, the struct/union | |
8268 | cannot be an integer type. */ | |
8269 | ||
8270 | /* For each field in the object, check: | |
8271 | 1) Is it FP? --> yes, nRc = 1; | |
8272 | 2) Is it addressable (bitpos != 0) and | |
8273 | not packed (bitsize == 0)? | |
8274 | --> yes, nRc = 1 | |
8275 | */ | |
8276 | ||
1f704f76 | 8277 | for (i = 0; i < type->num_fields (); i++) |
67255d04 | 8278 | { |
b13c8ab2 YQ |
8279 | enum type_code field_type_code; |
8280 | ||
8281 | field_type_code | |
940da03e | 8282 | = check_typedef (type->field (i).type ())->code (); |
b13c8ab2 YQ |
8283 | |
8284 | /* Is it a floating point type field? */ | |
8285 | if (field_type_code == TYPE_CODE_FLT) | |
67255d04 RE |
8286 | { |
8287 | nRc = 1; | |
8288 | break; | |
8289 | } | |
b13c8ab2 YQ |
8290 | |
8291 | /* If bitpos != 0, then we have to care about it. */ | |
b610c045 | 8292 | if (type->field (i).loc_bitpos () != 0) |
b13c8ab2 YQ |
8293 | { |
8294 | /* Bitfields are not addressable. If the field bitsize is | |
8295 | zero, then the field is not packed. Hence it cannot be | |
8296 | a bitfield or any other packed type. */ | |
8297 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
8298 | { | |
8299 | nRc = 1; | |
8300 | break; | |
8301 | } | |
8302 | } | |
67255d04 RE |
8303 | } |
8304 | } | |
67255d04 | 8305 | |
b13c8ab2 YQ |
8306 | return nRc; |
8307 | } | |
67255d04 RE |
8308 | } |
8309 | ||
34e8f22d RE |
8310 | /* Write into appropriate registers a function return value of type |
8311 | TYPE, given in virtual format. */ | |
8312 | ||
8313 | static void | |
b508a996 | 8314 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 8315 | const gdb_byte *valbuf) |
34e8f22d | 8316 | { |
ac7936df | 8317 | struct gdbarch *gdbarch = regs->arch (); |
e17a4113 | 8318 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
be8626e0 | 8319 | |
78134374 | 8320 | if (type->code () == TYPE_CODE_FLT) |
34e8f22d | 8321 | { |
f0452268 | 8322 | gdb_byte buf[ARM_FP_REGISTER_SIZE]; |
345bd07c | 8323 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
34e8f22d | 8324 | |
345bd07c | 8325 | switch (tdep->fp_model) |
08216dd7 RE |
8326 | { |
8327 | case ARM_FLOAT_FPA: | |
8328 | ||
3b2ca824 | 8329 | target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch)); |
b66f5587 | 8330 | regs->cooked_write (ARM_F0_REGNUM, buf); |
08216dd7 RE |
8331 | break; |
8332 | ||
fd50bc42 | 8333 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 8334 | case ARM_FLOAT_SOFT_VFP: |
90445bd3 DJ |
8335 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
8336 | not using the VFP ABI code. */ | |
8337 | case ARM_FLOAT_VFP: | |
b66f5587 | 8338 | regs->cooked_write (ARM_A1_REGNUM, valbuf); |
b508a996 | 8339 | if (TYPE_LENGTH (type) > 4) |
f0452268 AH |
8340 | regs->cooked_write (ARM_A1_REGNUM + 1, |
8341 | valbuf + ARM_INT_REGISTER_SIZE); | |
08216dd7 RE |
8342 | break; |
8343 | ||
8344 | default: | |
9b20d036 MS |
8345 | internal_error (__FILE__, __LINE__, |
8346 | _("arm_store_return_value: Floating " | |
8347 | "point model not supported")); | |
08216dd7 RE |
8348 | break; |
8349 | } | |
34e8f22d | 8350 | } |
78134374 SM |
8351 | else if (type->code () == TYPE_CODE_INT |
8352 | || type->code () == TYPE_CODE_CHAR | |
8353 | || type->code () == TYPE_CODE_BOOL | |
8354 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 8355 | || TYPE_IS_REFERENCE (type) |
78134374 | 8356 | || type->code () == TYPE_CODE_ENUM) |
b508a996 RE |
8357 | { |
8358 | if (TYPE_LENGTH (type) <= 4) | |
8359 | { | |
8360 | /* Values of one word or less are zero/sign-extended and | |
8361 | returned in r0. */ | |
f0452268 | 8362 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8363 | LONGEST val = unpack_long (type, valbuf); |
8364 | ||
f0452268 | 8365 | store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val); |
b66f5587 | 8366 | regs->cooked_write (ARM_A1_REGNUM, tmpbuf); |
b508a996 RE |
8367 | } |
8368 | else | |
8369 | { | |
8370 | /* Integral values greater than one word are stored in consecutive | |
8371 | registers starting with r0. This will always be a multiple of | |
8372 | the regiser size. */ | |
8373 | int len = TYPE_LENGTH (type); | |
8374 | int regno = ARM_A1_REGNUM; | |
8375 | ||
8376 | while (len > 0) | |
8377 | { | |
b66f5587 | 8378 | regs->cooked_write (regno++, valbuf); |
f0452268 AH |
8379 | len -= ARM_INT_REGISTER_SIZE; |
8380 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8381 | } |
8382 | } | |
8383 | } | |
34e8f22d | 8384 | else |
b508a996 RE |
8385 | { |
8386 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
8387 | been stored to word-aligned memory and then loaded into |
8388 | registers with 32-bit load instruction(s). */ | |
b508a996 RE |
8389 | int len = TYPE_LENGTH (type); |
8390 | int regno = ARM_A1_REGNUM; | |
f0452268 | 8391 | bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE]; |
b508a996 RE |
8392 | |
8393 | while (len > 0) | |
8394 | { | |
8395 | memcpy (tmpbuf, valbuf, | |
f0452268 | 8396 | len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len); |
b66f5587 | 8397 | regs->cooked_write (regno++, tmpbuf); |
f0452268 AH |
8398 | len -= ARM_INT_REGISTER_SIZE; |
8399 | valbuf += ARM_INT_REGISTER_SIZE; | |
b508a996 RE |
8400 | } |
8401 | } | |
34e8f22d RE |
8402 | } |
8403 | ||
2af48f68 PB |
8404 | |
8405 | /* Handle function return values. */ | |
8406 | ||
8407 | static enum return_value_convention | |
6a3a010b | 8408 | arm_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
8409 | struct type *valtype, struct regcache *regcache, |
8410 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 8411 | { |
345bd07c | 8412 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
6a3a010b | 8413 | struct type *func_type = function ? value_type (function) : NULL; |
90445bd3 DJ |
8414 | enum arm_vfp_cprc_base_type vfp_base_type; |
8415 | int vfp_base_count; | |
8416 | ||
8417 | if (arm_vfp_abi_for_function (gdbarch, func_type) | |
8418 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) | |
8419 | { | |
8420 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); | |
8421 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); | |
8422 | int i; | |
8423 | for (i = 0; i < vfp_base_count; i++) | |
8424 | { | |
58d6951d DJ |
8425 | if (reg_char == 'q') |
8426 | { | |
8427 | if (writebuf) | |
8428 | arm_neon_quad_write (gdbarch, regcache, i, | |
8429 | writebuf + i * unit_length); | |
8430 | ||
8431 | if (readbuf) | |
8432 | arm_neon_quad_read (gdbarch, regcache, i, | |
8433 | readbuf + i * unit_length); | |
8434 | } | |
8435 | else | |
8436 | { | |
8437 | char name_buf[4]; | |
8438 | int regnum; | |
8439 | ||
8c042590 | 8440 | xsnprintf (name_buf, sizeof (name_buf), "%c%d", reg_char, i); |
58d6951d DJ |
8441 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8442 | strlen (name_buf)); | |
8443 | if (writebuf) | |
b66f5587 | 8444 | regcache->cooked_write (regnum, writebuf + i * unit_length); |
58d6951d | 8445 | if (readbuf) |
dca08e1f | 8446 | regcache->cooked_read (regnum, readbuf + i * unit_length); |
58d6951d | 8447 | } |
90445bd3 DJ |
8448 | } |
8449 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8450 | } | |
7c00367c | 8451 | |
78134374 SM |
8452 | if (valtype->code () == TYPE_CODE_STRUCT |
8453 | || valtype->code () == TYPE_CODE_UNION | |
8454 | || valtype->code () == TYPE_CODE_ARRAY) | |
2af48f68 | 8455 | { |
bab22d06 LM |
8456 | /* From the AAPCS document: |
8457 | ||
8458 | Result return: | |
8459 | ||
8460 | A Composite Type larger than 4 bytes, or whose size cannot be | |
8461 | determined statically by both caller and callee, is stored in memory | |
8462 | at an address passed as an extra argument when the function was | |
8463 | called (Parameter Passing, rule A.4). The memory to be used for the | |
8464 | result may be modified at any point during the function call. | |
8465 | ||
8466 | Parameter Passing: | |
8467 | ||
8468 | A.4: If the subroutine is a function that returns a result in memory, | |
8469 | then the address for the result is placed in r0 and the NCRN is set | |
8470 | to r1. */ | |
7c00367c MK |
8471 | if (tdep->struct_return == pcc_struct_return |
8472 | || arm_return_in_memory (gdbarch, valtype)) | |
bab22d06 LM |
8473 | { |
8474 | if (readbuf) | |
8475 | { | |
8476 | CORE_ADDR addr; | |
8477 | ||
8478 | regcache->cooked_read (ARM_A1_REGNUM, &addr); | |
8479 | read_memory (addr, readbuf, TYPE_LENGTH (valtype)); | |
8480 | } | |
8481 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
8482 | } | |
2af48f68 | 8483 | } |
78134374 | 8484 | else if (valtype->code () == TYPE_CODE_COMPLEX) |
b13c8ab2 YQ |
8485 | { |
8486 | if (arm_return_in_memory (gdbarch, valtype)) | |
8487 | return RETURN_VALUE_STRUCT_CONVENTION; | |
8488 | } | |
7052e42c | 8489 | |
2af48f68 PB |
8490 | if (writebuf) |
8491 | arm_store_return_value (valtype, regcache, writebuf); | |
8492 | ||
8493 | if (readbuf) | |
8494 | arm_extract_return_value (valtype, regcache, readbuf); | |
8495 | ||
8496 | return RETURN_VALUE_REGISTER_CONVENTION; | |
8497 | } | |
8498 | ||
8499 | ||
9df628e0 | 8500 | static int |
60ade65d | 8501 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 | 8502 | { |
e17a4113 | 8503 | struct gdbarch *gdbarch = get_frame_arch (frame); |
345bd07c | 8504 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
e17a4113 | 8505 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9df628e0 | 8506 | CORE_ADDR jb_addr; |
f0452268 | 8507 | gdb_byte buf[ARM_INT_REGISTER_SIZE]; |
9df628e0 | 8508 | |
60ade65d | 8509 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
8510 | |
8511 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
f0452268 | 8512 | ARM_INT_REGISTER_SIZE)) |
9df628e0 RE |
8513 | return 0; |
8514 | ||
f0452268 | 8515 | *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order); |
9df628e0 RE |
8516 | return 1; |
8517 | } | |
40eadf04 SP |
8518 | /* A call to cmse secure entry function "foo" at "a" is modified by |
8519 | GNU ld as "b". | |
8520 | a) bl xxxx <foo> | |
8521 | ||
8522 | <foo> | |
8523 | xxxx: | |
8524 | ||
8525 | b) bl yyyy <__acle_se_foo> | |
8526 | ||
8527 | section .gnu.sgstubs: | |
8528 | <foo> | |
8529 | yyyy: sg // secure gateway | |
8530 | b.w xxxx <__acle_se_foo> // original_branch_dest | |
8531 | ||
8532 | <__acle_se_foo> | |
8533 | xxxx: | |
8534 | ||
8535 | When the control at "b", the pc contains "yyyy" (sg address) which is a | |
8536 | trampoline and does not exist in source code. This function returns the | |
8537 | target pc "xxxx". For more details please refer to section 5.4 | |
8538 | (Entry functions) and section 3.4.4 (C level development flow of secure code) | |
8539 | of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification" | |
8540 | document on www.developer.arm.com. */ | |
8541 | ||
8542 | static CORE_ADDR | |
8543 | arm_skip_cmse_entry (CORE_ADDR pc, const char *name, struct objfile *objfile) | |
8544 | { | |
8545 | int target_len = strlen (name) + strlen ("__acle_se_") + 1; | |
8546 | char *target_name = (char *) alloca (target_len); | |
8547 | xsnprintf (target_name, target_len, "%s%s", "__acle_se_", name); | |
8548 | ||
8549 | struct bound_minimal_symbol minsym | |
8550 | = lookup_minimal_symbol (target_name, NULL, objfile); | |
8551 | ||
8552 | if (minsym.minsym != nullptr) | |
4aeddc50 | 8553 | return minsym.value_address (); |
40eadf04 SP |
8554 | |
8555 | return 0; | |
8556 | } | |
8557 | ||
8558 | /* Return true when SEC points to ".gnu.sgstubs" section. */ | |
8559 | ||
8560 | static bool | |
8561 | arm_is_sgstubs_section (struct obj_section *sec) | |
8562 | { | |
8563 | return (sec != nullptr | |
8564 | && sec->the_bfd_section != nullptr | |
8565 | && sec->the_bfd_section->name != nullptr | |
8566 | && streq (sec->the_bfd_section->name, ".gnu.sgstubs")); | |
8567 | } | |
9df628e0 | 8568 | |
faa95490 DJ |
8569 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
8570 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
8571 | |
8572 | CORE_ADDR | |
52f729a7 | 8573 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 8574 | { |
2c02bd72 | 8575 | const char *name; |
faa95490 | 8576 | int namelen; |
c906108c SS |
8577 | CORE_ADDR start_addr; |
8578 | ||
8579 | /* Find the starting address and name of the function containing the PC. */ | |
8580 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
80d8d390 YQ |
8581 | { |
8582 | /* Trampoline 'bx reg' doesn't belong to any functions. Do the | |
8583 | check here. */ | |
8584 | start_addr = arm_skip_bx_reg (frame, pc); | |
8585 | if (start_addr != 0) | |
8586 | return start_addr; | |
8587 | ||
8588 | return 0; | |
8589 | } | |
c906108c | 8590 | |
faa95490 DJ |
8591 | /* If PC is in a Thumb call or return stub, return the address of the |
8592 | target PC, which is in a register. The thunk functions are called | |
8593 | _call_via_xx, where x is the register name. The possible names | |
3d8d5e79 DJ |
8594 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
8595 | functions, named __ARM_call_via_r[0-7]. */ | |
61012eef GB |
8596 | if (startswith (name, "_call_via_") |
8597 | || startswith (name, "__ARM_call_via_")) | |
c906108c | 8598 | { |
ed9a39eb | 8599 | /* Use the name suffix to determine which register contains the |
dda83cd7 | 8600 | target PC. */ |
a121b7c1 | 8601 | static const char *table[15] = |
c5aa993b JM |
8602 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
8603 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
8604 | }; | |
c906108c | 8605 | int regno; |
faa95490 | 8606 | int offset = strlen (name) - 2; |
c906108c SS |
8607 | |
8608 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 8609 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 8610 | return get_frame_register_unsigned (frame, regno); |
c906108c | 8611 | } |
ed9a39eb | 8612 | |
faa95490 DJ |
8613 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
8614 | non-interworking calls to foo. We could decode the stubs | |
8615 | to find the target but it's easier to use the symbol table. */ | |
8616 | namelen = strlen (name); | |
8617 | if (name[0] == '_' && name[1] == '_' | |
8618 | && ((namelen > 2 + strlen ("_from_thumb") | |
61012eef | 8619 | && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) |
faa95490 | 8620 | || (namelen > 2 + strlen ("_from_arm") |
61012eef | 8621 | && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) |
faa95490 DJ |
8622 | { |
8623 | char *target_name; | |
8624 | int target_len = namelen - 2; | |
3b7344d5 | 8625 | struct bound_minimal_symbol minsym; |
faa95490 DJ |
8626 | struct objfile *objfile; |
8627 | struct obj_section *sec; | |
8628 | ||
8629 | if (name[namelen - 1] == 'b') | |
8630 | target_len -= strlen ("_from_thumb"); | |
8631 | else | |
8632 | target_len -= strlen ("_from_arm"); | |
8633 | ||
224c3ddb | 8634 | target_name = (char *) alloca (target_len + 1); |
faa95490 DJ |
8635 | memcpy (target_name, name + 2, target_len); |
8636 | target_name[target_len] = '\0'; | |
8637 | ||
8638 | sec = find_pc_section (pc); | |
8639 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
8640 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
3b7344d5 | 8641 | if (minsym.minsym != NULL) |
4aeddc50 | 8642 | return minsym.value_address (); |
faa95490 DJ |
8643 | else |
8644 | return 0; | |
8645 | } | |
8646 | ||
40eadf04 SP |
8647 | struct obj_section *section = find_pc_section (pc); |
8648 | ||
8649 | /* Check whether SECTION points to the ".gnu.sgstubs" section. */ | |
8650 | if (arm_is_sgstubs_section (section)) | |
8651 | return arm_skip_cmse_entry (pc, name, section->objfile); | |
8652 | ||
c5aa993b | 8653 | return 0; /* not a stub */ |
c906108c SS |
8654 | } |
8655 | ||
28e97307 DJ |
8656 | static void |
8657 | arm_update_current_architecture (void) | |
fd50bc42 | 8658 | { |
28e97307 | 8659 | /* If the current architecture is not ARM, we have nothing to do. */ |
f5656ead | 8660 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_arm) |
28e97307 | 8661 | return; |
fd50bc42 | 8662 | |
28e97307 | 8663 | /* Update the architecture. */ |
b447dd03 | 8664 | gdbarch_info info; |
28e97307 | 8665 | if (!gdbarch_update_p (info)) |
9b20d036 | 8666 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
fd50bc42 RE |
8667 | } |
8668 | ||
8669 | static void | |
eb4c3f4a | 8670 | set_fp_model_sfunc (const char *args, int from_tty, |
fd50bc42 RE |
8671 | struct cmd_list_element *c) |
8672 | { | |
570dc176 | 8673 | int fp_model; |
fd50bc42 RE |
8674 | |
8675 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
8676 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
8677 | { | |
aead7601 | 8678 | arm_fp_model = (enum arm_float_model) fp_model; |
fd50bc42 RE |
8679 | break; |
8680 | } | |
8681 | ||
8682 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 8683 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
8684 | current_fp_model); |
8685 | ||
28e97307 | 8686 | arm_update_current_architecture (); |
fd50bc42 RE |
8687 | } |
8688 | ||
8689 | static void | |
08546159 AC |
8690 | show_fp_model (struct ui_file *file, int from_tty, |
8691 | struct cmd_list_element *c, const char *value) | |
fd50bc42 | 8692 | { |
345bd07c SM |
8693 | arm_gdbarch_tdep *tdep |
8694 | = (arm_gdbarch_tdep *) gdbarch_tdep (target_gdbarch ()); | |
fd50bc42 | 8695 | |
28e97307 | 8696 | if (arm_fp_model == ARM_FLOAT_AUTO |
f5656ead | 8697 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6cb06a8c | 8698 | gdb_printf (file, _("\ |
28e97307 | 8699 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
6cb06a8c | 8700 | fp_model_strings[tdep->fp_model]); |
28e97307 | 8701 | else |
6cb06a8c | 8702 | gdb_printf (file, _("\ |
28e97307 | 8703 | The current ARM floating point model is \"%s\".\n"), |
6cb06a8c | 8704 | fp_model_strings[arm_fp_model]); |
28e97307 DJ |
8705 | } |
8706 | ||
8707 | static void | |
eb4c3f4a | 8708 | arm_set_abi (const char *args, int from_tty, |
28e97307 DJ |
8709 | struct cmd_list_element *c) |
8710 | { | |
570dc176 | 8711 | int arm_abi; |
28e97307 DJ |
8712 | |
8713 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
8714 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
8715 | { | |
aead7601 | 8716 | arm_abi_global = (enum arm_abi_kind) arm_abi; |
28e97307 DJ |
8717 | break; |
8718 | } | |
8719 | ||
8720 | if (arm_abi == ARM_ABI_LAST) | |
8721 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
8722 | arm_abi_string); | |
8723 | ||
8724 | arm_update_current_architecture (); | |
8725 | } | |
8726 | ||
8727 | static void | |
8728 | arm_show_abi (struct ui_file *file, int from_tty, | |
8729 | struct cmd_list_element *c, const char *value) | |
8730 | { | |
345bd07c SM |
8731 | arm_gdbarch_tdep *tdep |
8732 | = (arm_gdbarch_tdep *) gdbarch_tdep (target_gdbarch ()); | |
28e97307 DJ |
8733 | |
8734 | if (arm_abi_global == ARM_ABI_AUTO | |
f5656ead | 8735 | && gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_arm) |
6cb06a8c | 8736 | gdb_printf (file, _("\ |
28e97307 | 8737 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
6cb06a8c | 8738 | arm_abi_strings[tdep->arm_abi]); |
28e97307 | 8739 | else |
6cb06a8c TT |
8740 | gdb_printf (file, _("The current ARM ABI is \"%s\".\n"), |
8741 | arm_abi_string); | |
fd50bc42 RE |
8742 | } |
8743 | ||
0428b8f5 DJ |
8744 | static void |
8745 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
8746 | struct cmd_list_element *c, const char *value) | |
8747 | { | |
6cb06a8c TT |
8748 | gdb_printf (file, |
8749 | _("The current execution mode assumed " | |
8750 | "(when symbols are unavailable) is \"%s\".\n"), | |
8751 | arm_fallback_mode_string); | |
0428b8f5 DJ |
8752 | } |
8753 | ||
8754 | static void | |
8755 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
8756 | struct cmd_list_element *c, const char *value) | |
8757 | { | |
6cb06a8c TT |
8758 | gdb_printf (file, |
8759 | _("The current execution mode assumed " | |
8760 | "(even when symbols are available) is \"%s\".\n"), | |
8761 | arm_force_mode_string); | |
0428b8f5 DJ |
8762 | } |
8763 | ||
afd7eef0 RE |
8764 | /* If the user changes the register disassembly style used for info |
8765 | register and other commands, we have to also switch the style used | |
8766 | in opcodes for disassembly output. This function is run in the "set | |
8767 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
8768 | |
8769 | static void | |
eb4c3f4a | 8770 | set_disassembly_style_sfunc (const char *args, int from_tty, |
65b48a81 | 8771 | struct cmd_list_element *c) |
bc90b915 | 8772 | { |
65b48a81 PB |
8773 | /* Convert the short style name into the long style name (eg, reg-names-*) |
8774 | before calling the generic set_disassembler_options() function. */ | |
8775 | std::string long_name = std::string ("reg-names-") + disassembly_style; | |
8776 | set_disassembler_options (&long_name[0]); | |
8777 | } | |
8778 | ||
8779 | static void | |
8780 | show_disassembly_style_sfunc (struct ui_file *file, int from_tty, | |
8781 | struct cmd_list_element *c, const char *value) | |
8782 | { | |
8783 | struct gdbarch *gdbarch = get_current_arch (); | |
8784 | char *options = get_disassembler_options (gdbarch); | |
8785 | const char *style = ""; | |
8786 | int len = 0; | |
f995bbe8 | 8787 | const char *opt; |
65b48a81 PB |
8788 | |
8789 | FOR_EACH_DISASSEMBLER_OPTION (opt, options) | |
08dedd66 | 8790 | if (startswith (opt, "reg-names-")) |
65b48a81 PB |
8791 | { |
8792 | style = &opt[strlen ("reg-names-")]; | |
8793 | len = strcspn (style, ","); | |
8794 | } | |
8795 | ||
6cb06a8c | 8796 | gdb_printf (file, "The disassembly style is \"%.*s\".\n", len, style); |
bc90b915 FN |
8797 | } |
8798 | \f | |
966fbf70 | 8799 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 8800 | static const char * |
d93859e2 | 8801 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 8802 | { |
345bd07c | 8803 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d | 8804 | |
ecbf5d4f | 8805 | if (is_s_pseudo (gdbarch, i)) |
58d6951d | 8806 | { |
ecbf5d4f | 8807 | static const char *const s_pseudo_names[] = { |
58d6951d DJ |
8808 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
8809 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", | |
8810 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", | |
8811 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", | |
8812 | }; | |
8813 | ||
ecbf5d4f | 8814 | return s_pseudo_names[i - tdep->s_pseudo_base]; |
58d6951d DJ |
8815 | } |
8816 | ||
ecbf5d4f | 8817 | if (is_q_pseudo (gdbarch, i)) |
58d6951d | 8818 | { |
ecbf5d4f | 8819 | static const char *const q_pseudo_names[] = { |
58d6951d DJ |
8820 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", |
8821 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", | |
8822 | }; | |
8823 | ||
ecbf5d4f | 8824 | return q_pseudo_names[i - tdep->q_pseudo_base]; |
58d6951d DJ |
8825 | } |
8826 | ||
ae66a8f1 SP |
8827 | if (is_mve_pseudo (gdbarch, i)) |
8828 | return "p0"; | |
8829 | ||
a01567f4 LM |
8830 | /* RA_AUTH_CODE is used for unwinding only. Do not assign it a name. */ |
8831 | if (is_pacbti_pseudo (gdbarch, i)) | |
8832 | return ""; | |
8833 | ||
ff6f572f DJ |
8834 | if (i >= ARRAY_SIZE (arm_register_names)) |
8835 | /* These registers are only supported on targets which supply | |
8836 | an XML description. */ | |
8837 | return ""; | |
8838 | ||
ecbf5d4f | 8839 | /* Non-pseudo registers. */ |
966fbf70 RE |
8840 | return arm_register_names[i]; |
8841 | } | |
8842 | ||
082fc60d RE |
8843 | /* Test whether the coff symbol specific value corresponds to a Thumb |
8844 | function. */ | |
8845 | ||
8846 | static int | |
8847 | coff_sym_is_thumb (int val) | |
8848 | { | |
f8bf5763 PM |
8849 | return (val == C_THUMBEXT |
8850 | || val == C_THUMBSTAT | |
8851 | || val == C_THUMBEXTFUNC | |
8852 | || val == C_THUMBSTATFUNC | |
8853 | || val == C_THUMBLABEL); | |
082fc60d RE |
8854 | } |
8855 | ||
8856 | /* arm_coff_make_msymbol_special() | |
8857 | arm_elf_make_msymbol_special() | |
8858 | ||
8859 | These functions test whether the COFF or ELF symbol corresponds to | |
8860 | an address in thumb code, and set a "special" bit in a minimal | |
8861 | symbol to indicate that it does. */ | |
8862 | ||
34e8f22d | 8863 | static void |
082fc60d RE |
8864 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
8865 | { | |
39d911fc TP |
8866 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
8867 | ||
8868 | if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) | |
467d42c4 | 8869 | == ST_BRANCH_TO_THUMB) |
082fc60d RE |
8870 | MSYMBOL_SET_SPECIAL (msym); |
8871 | } | |
8872 | ||
34e8f22d | 8873 | static void |
082fc60d RE |
8874 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
8875 | { | |
8876 | if (coff_sym_is_thumb (val)) | |
8877 | MSYMBOL_SET_SPECIAL (msym); | |
8878 | } | |
8879 | ||
60c5725c DJ |
8880 | static void |
8881 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, | |
8882 | asymbol *sym) | |
8883 | { | |
8884 | const char *name = bfd_asymbol_name (sym); | |
bd5766ec | 8885 | struct arm_per_bfd *data; |
60c5725c DJ |
8886 | struct arm_mapping_symbol new_map_sym; |
8887 | ||
8888 | gdb_assert (name[0] == '$'); | |
8889 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') | |
8890 | return; | |
8891 | ||
bd5766ec | 8892 | data = arm_bfd_data_key.get (objfile->obfd); |
60c5725c | 8893 | if (data == NULL) |
bd5766ec LM |
8894 | data = arm_bfd_data_key.emplace (objfile->obfd, |
8895 | objfile->obfd->section_count); | |
54cc7474 | 8896 | arm_mapping_symbol_vec &map |
e6f7f6d1 | 8897 | = data->section_maps[bfd_asymbol_section (sym)->index]; |
60c5725c DJ |
8898 | |
8899 | new_map_sym.value = sym->value; | |
8900 | new_map_sym.type = name[1]; | |
8901 | ||
4838e44c SM |
8902 | /* Insert at the end, the vector will be sorted on first use. */ |
8903 | map.push_back (new_map_sym); | |
60c5725c DJ |
8904 | } |
8905 | ||
756fe439 | 8906 | static void |
61a1198a | 8907 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 8908 | { |
ac7936df | 8909 | struct gdbarch *gdbarch = regcache->arch (); |
61a1198a | 8910 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
8911 | |
8912 | /* If necessary, set the T bit. */ | |
8913 | if (arm_apcs_32) | |
8914 | { | |
9779414d | 8915 | ULONGEST val, t_bit; |
61a1198a | 8916 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
9779414d DJ |
8917 | t_bit = arm_psr_thumb_bit (gdbarch); |
8918 | if (arm_pc_is_thumb (gdbarch, pc)) | |
8919 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, | |
8920 | val | t_bit); | |
756fe439 | 8921 | else |
61a1198a | 8922 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
9779414d | 8923 | val & ~t_bit); |
756fe439 DJ |
8924 | } |
8925 | } | |
123dc839 | 8926 | |
58d6951d DJ |
8927 | /* Read the contents of a NEON quad register, by reading from two |
8928 | double registers. This is used to implement the quad pseudo | |
8929 | registers, and for argument passing in case the quad registers are | |
8930 | missing; vectors are passed in quad registers when using the VFP | |
8931 | ABI, even if a NEON unit is not present. REGNUM is the index of | |
8932 | the quad register, in [0, 15]. */ | |
8933 | ||
05d1431c | 8934 | static enum register_status |
849d0ba8 | 8935 | arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8936 | int regnum, gdb_byte *buf) |
8937 | { | |
8938 | char name_buf[4]; | |
8939 | gdb_byte reg_buf[8]; | |
8940 | int offset, double_regnum; | |
05d1431c | 8941 | enum register_status status; |
58d6951d | 8942 | |
8c042590 | 8943 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
8944 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
8945 | strlen (name_buf)); | |
8946 | ||
8947 | /* d0 is always the least significant half of q0. */ | |
8948 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
8949 | offset = 8; | |
8950 | else | |
8951 | offset = 0; | |
8952 | ||
03f50fc8 | 8953 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
8954 | if (status != REG_VALID) |
8955 | return status; | |
58d6951d DJ |
8956 | memcpy (buf + offset, reg_buf, 8); |
8957 | ||
8958 | offset = 8 - offset; | |
03f50fc8 | 8959 | status = regcache->raw_read (double_regnum + 1, reg_buf); |
05d1431c PA |
8960 | if (status != REG_VALID) |
8961 | return status; | |
58d6951d | 8962 | memcpy (buf + offset, reg_buf, 8); |
05d1431c PA |
8963 | |
8964 | return REG_VALID; | |
58d6951d DJ |
8965 | } |
8966 | ||
ae66a8f1 SP |
8967 | /* Read the contents of the MVE pseudo register REGNUM and store it |
8968 | in BUF. */ | |
8969 | ||
8970 | static enum register_status | |
8971 | arm_mve_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, | |
8972 | int regnum, gdb_byte *buf) | |
8973 | { | |
345bd07c | 8974 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
ae66a8f1 SP |
8975 | |
8976 | /* P0 is the first 16 bits of VPR. */ | |
8977 | return regcache->raw_read_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
8978 | } | |
8979 | ||
05d1431c | 8980 | static enum register_status |
849d0ba8 | 8981 | arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
58d6951d DJ |
8982 | int regnum, gdb_byte *buf) |
8983 | { | |
8984 | const int num_regs = gdbarch_num_regs (gdbarch); | |
8985 | char name_buf[4]; | |
8986 | gdb_byte reg_buf[8]; | |
8987 | int offset, double_regnum; | |
345bd07c | 8988 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d DJ |
8989 | |
8990 | gdb_assert (regnum >= num_regs); | |
58d6951d | 8991 | |
ecbf5d4f LM |
8992 | if (is_q_pseudo (gdbarch, regnum)) |
8993 | { | |
8994 | /* Quad-precision register. */ | |
8995 | return arm_neon_quad_read (gdbarch, regcache, | |
8996 | regnum - tdep->q_pseudo_base, buf); | |
8997 | } | |
ae66a8f1 SP |
8998 | else if (is_mve_pseudo (gdbarch, regnum)) |
8999 | return arm_mve_pseudo_read (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9000 | else |
9001 | { | |
05d1431c PA |
9002 | enum register_status status; |
9003 | ||
ecbf5d4f | 9004 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9005 | /* Single-precision register. */ |
9006 | gdb_assert (regnum < 32); | |
9007 | ||
9008 | /* s0 is always the least significant half of d0. */ | |
9009 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9010 | offset = (regnum & 1) ? 0 : 4; | |
9011 | else | |
9012 | offset = (regnum & 1) ? 4 : 0; | |
9013 | ||
8c042590 | 9014 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9015 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9016 | strlen (name_buf)); | |
9017 | ||
03f50fc8 | 9018 | status = regcache->raw_read (double_regnum, reg_buf); |
05d1431c PA |
9019 | if (status == REG_VALID) |
9020 | memcpy (buf, reg_buf + offset, 4); | |
9021 | return status; | |
58d6951d DJ |
9022 | } |
9023 | } | |
9024 | ||
9025 | /* Store the contents of BUF to a NEON quad register, by writing to | |
9026 | two double registers. This is used to implement the quad pseudo | |
9027 | registers, and for argument passing in case the quad registers are | |
9028 | missing; vectors are passed in quad registers when using the VFP | |
9029 | ABI, even if a NEON unit is not present. REGNUM is the index | |
9030 | of the quad register, in [0, 15]. */ | |
9031 | ||
9032 | static void | |
9033 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9034 | int regnum, const gdb_byte *buf) | |
9035 | { | |
9036 | char name_buf[4]; | |
58d6951d DJ |
9037 | int offset, double_regnum; |
9038 | ||
8c042590 | 9039 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum << 1); |
58d6951d DJ |
9040 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9041 | strlen (name_buf)); | |
9042 | ||
9043 | /* d0 is always the least significant half of q0. */ | |
9044 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9045 | offset = 8; | |
9046 | else | |
9047 | offset = 0; | |
9048 | ||
10eaee5f | 9049 | regcache->raw_write (double_regnum, buf + offset); |
58d6951d | 9050 | offset = 8 - offset; |
10eaee5f | 9051 | regcache->raw_write (double_regnum + 1, buf + offset); |
58d6951d DJ |
9052 | } |
9053 | ||
ae66a8f1 SP |
9054 | /* Store the contents of BUF to the MVE pseudo register REGNUM. */ |
9055 | ||
9056 | static void | |
9057 | arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9058 | int regnum, const gdb_byte *buf) | |
9059 | { | |
345bd07c | 9060 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
ae66a8f1 SP |
9061 | |
9062 | /* P0 is the first 16 bits of VPR. */ | |
9063 | regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf); | |
9064 | } | |
9065 | ||
58d6951d DJ |
9066 | static void |
9067 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
9068 | int regnum, const gdb_byte *buf) | |
9069 | { | |
9070 | const int num_regs = gdbarch_num_regs (gdbarch); | |
9071 | char name_buf[4]; | |
9072 | gdb_byte reg_buf[8]; | |
9073 | int offset, double_regnum; | |
345bd07c | 9074 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
58d6951d DJ |
9075 | |
9076 | gdb_assert (regnum >= num_regs); | |
58d6951d | 9077 | |
ecbf5d4f LM |
9078 | if (is_q_pseudo (gdbarch, regnum)) |
9079 | { | |
9080 | /* Quad-precision register. */ | |
9081 | arm_neon_quad_write (gdbarch, regcache, | |
9082 | regnum - tdep->q_pseudo_base, buf); | |
9083 | } | |
ae66a8f1 SP |
9084 | else if (is_mve_pseudo (gdbarch, regnum)) |
9085 | arm_mve_pseudo_write (gdbarch, regcache, regnum, buf); | |
58d6951d DJ |
9086 | else |
9087 | { | |
ecbf5d4f | 9088 | regnum -= tdep->s_pseudo_base; |
58d6951d DJ |
9089 | /* Single-precision register. */ |
9090 | gdb_assert (regnum < 32); | |
9091 | ||
9092 | /* s0 is always the least significant half of d0. */ | |
9093 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
9094 | offset = (regnum & 1) ? 0 : 4; | |
9095 | else | |
9096 | offset = (regnum & 1) ? 4 : 0; | |
9097 | ||
8c042590 | 9098 | xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); |
58d6951d DJ |
9099 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
9100 | strlen (name_buf)); | |
9101 | ||
0b883586 | 9102 | regcache->raw_read (double_regnum, reg_buf); |
58d6951d | 9103 | memcpy (reg_buf + offset, buf, 4); |
10eaee5f | 9104 | regcache->raw_write (double_regnum, reg_buf); |
58d6951d DJ |
9105 | } |
9106 | } | |
9107 | ||
123dc839 DJ |
9108 | static struct value * |
9109 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
9110 | { | |
9a3c8263 | 9111 | const int *reg_p = (const int *) baton; |
123dc839 DJ |
9112 | return value_of_register (*reg_p, frame); |
9113 | } | |
97e03143 | 9114 | \f |
70f80edf JT |
9115 | static enum gdb_osabi |
9116 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 9117 | { |
2af48f68 | 9118 | unsigned int elfosabi; |
70f80edf | 9119 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 9120 | |
70f80edf | 9121 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 9122 | |
28e97307 DJ |
9123 | if (elfosabi == ELFOSABI_ARM) |
9124 | /* GNU tools use this value. Check note sections in this case, | |
9125 | as well. */ | |
b35c1d1c TT |
9126 | { |
9127 | for (asection *sect : gdb_bfd_sections (abfd)) | |
9128 | generic_elf_osabi_sniff_abi_tag_sections (abfd, sect, &osabi); | |
9129 | } | |
97e03143 | 9130 | |
28e97307 | 9131 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 9132 | return osabi; |
97e03143 RE |
9133 | } |
9134 | ||
54483882 YQ |
9135 | static int |
9136 | arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 9137 | const struct reggroup *group) |
54483882 | 9138 | { |
2c291032 YQ |
9139 | /* FPS register's type is INT, but belongs to float_reggroup. Beside |
9140 | this, FPS register belongs to save_regroup, restore_reggroup, and | |
9141 | all_reggroup, of course. */ | |
54483882 | 9142 | if (regnum == ARM_FPS_REGNUM) |
2c291032 YQ |
9143 | return (group == float_reggroup |
9144 | || group == save_reggroup | |
9145 | || group == restore_reggroup | |
9146 | || group == all_reggroup); | |
54483882 YQ |
9147 | else |
9148 | return default_register_reggroup_p (gdbarch, regnum, group); | |
9149 | } | |
9150 | ||
25f8c692 JL |
9151 | /* For backward-compatibility we allow two 'g' packet lengths with |
9152 | the remote protocol depending on whether FPA registers are | |
9153 | supplied. M-profile targets do not have FPA registers, but some | |
9154 | stubs already exist in the wild which use a 'g' packet which | |
9155 | supplies them albeit with dummy values. The packet format which | |
9156 | includes FPA registers should be considered deprecated for | |
9157 | M-profile targets. */ | |
9158 | ||
9159 | static void | |
9160 | arm_register_g_packet_guesses (struct gdbarch *gdbarch) | |
9161 | { | |
345bd07c SM |
9162 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
9163 | ||
9164 | if (tdep->is_m) | |
25f8c692 | 9165 | { |
d105cce5 AH |
9166 | const target_desc *tdesc; |
9167 | ||
25f8c692 JL |
9168 | /* If we know from the executable this is an M-profile target, |
9169 | cater for remote targets whose register set layout is the | |
9170 | same as the FPA layout. */ | |
d105cce5 | 9171 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA); |
25f8c692 | 9172 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9173 | ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, |
d105cce5 | 9174 | tdesc); |
25f8c692 JL |
9175 | |
9176 | /* The regular M-profile layout. */ | |
d105cce5 | 9177 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE); |
350fab54 | 9178 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, |
d105cce5 | 9179 | tdesc); |
3184d3f9 JL |
9180 | |
9181 | /* M-profile plus M4F VFP. */ | |
d105cce5 | 9182 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_VFP_D16); |
3184d3f9 | 9183 | register_remote_g_packet_guess (gdbarch, |
350fab54 | 9184 | ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, |
d105cce5 | 9185 | tdesc); |
ae66a8f1 SP |
9186 | /* M-profile plus MVE. */ |
9187 | tdesc = arm_read_mprofile_description (ARM_M_TYPE_MVE); | |
9188 | register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE | |
9189 | + ARM_VFP2_REGS_SIZE | |
9190 | + ARM_INT_REGISTER_SIZE, tdesc); | |
25f8c692 JL |
9191 | } |
9192 | ||
9193 | /* Otherwise we don't have a useful guess. */ | |
9194 | } | |
9195 | ||
7eb89530 YQ |
9196 | /* Implement the code_of_frame_writable gdbarch method. */ |
9197 | ||
9198 | static int | |
9199 | arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame) | |
9200 | { | |
345bd07c SM |
9201 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
9202 | ||
9203 | if (tdep->is_m && get_frame_type (frame) == SIGTRAMP_FRAME) | |
7eb89530 YQ |
9204 | { |
9205 | /* M-profile exception frames return to some magic PCs, where | |
9206 | isn't writable at all. */ | |
9207 | return 0; | |
9208 | } | |
9209 | else | |
9210 | return 1; | |
9211 | } | |
9212 | ||
3426ae57 AH |
9213 | /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it |
9214 | to be postfixed by a version (eg armv7hl). */ | |
9215 | ||
9216 | static const char * | |
9217 | arm_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
9218 | { | |
9219 | if (strcmp (gdbarch_bfd_arch_info (gdbarch)->arch_name, "arm") == 0) | |
9220 | return "arm(v[^- ]*)?"; | |
9221 | return gdbarch_bfd_arch_info (gdbarch)->arch_name; | |
9222 | } | |
9223 | ||
a01567f4 LM |
9224 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
9225 | ||
9226 | static std::string | |
9227 | arm_get_pc_address_flags (frame_info *frame, CORE_ADDR pc) | |
9228 | { | |
9229 | if (get_frame_pc_masked (frame)) | |
9230 | return "PAC"; | |
9231 | ||
9232 | return ""; | |
9233 | } | |
9234 | ||
da3c6d4a MS |
9235 | /* Initialize the current architecture based on INFO. If possible, |
9236 | re-use an architecture from ARCHES, which is a list of | |
9237 | architectures already created during this debugging session. | |
97e03143 | 9238 | |
da3c6d4a MS |
9239 | Called e.g. at program startup, when reading a core file, and when |
9240 | reading a binary file. */ | |
97e03143 | 9241 | |
39bbf761 RE |
9242 | static struct gdbarch * |
9243 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
9244 | { | |
9245 | struct gdbarch *gdbarch; | |
28e97307 DJ |
9246 | struct gdbarch_list *best_arch; |
9247 | enum arm_abi_kind arm_abi = arm_abi_global; | |
9248 | enum arm_float_model fp_model = arm_fp_model; | |
c1e1314d | 9249 | tdesc_arch_data_up tdesc_data; |
7559c217 CB |
9250 | int i; |
9251 | bool is_m = false; | |
9252 | int vfp_register_count = 0; | |
ecbf5d4f | 9253 | bool have_s_pseudos = false, have_q_pseudos = false; |
7559c217 CB |
9254 | bool have_wmmx_registers = false; |
9255 | bool have_neon = false; | |
9256 | bool have_fpa_registers = true; | |
9779414d | 9257 | const struct target_desc *tdesc = info.target_desc; |
ae66a8f1 SP |
9258 | bool have_vfp = false; |
9259 | bool have_mve = false; | |
a01567f4 | 9260 | bool have_pacbti = false; |
ae66a8f1 | 9261 | int mve_vpr_regnum = -1; |
ecbf5d4f | 9262 | int register_count = ARM_NUM_REGS; |
9779414d DJ |
9263 | |
9264 | /* If we have an object to base this architecture on, try to determine | |
9265 | its ABI. */ | |
9266 | ||
9267 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) | |
9268 | { | |
9269 | int ei_osabi, e_flags; | |
9270 | ||
9271 | switch (bfd_get_flavour (info.abfd)) | |
9272 | { | |
9779414d DJ |
9273 | case bfd_target_coff_flavour: |
9274 | /* Assume it's an old APCS-style ABI. */ | |
9275 | /* XXX WinCE? */ | |
9276 | arm_abi = ARM_ABI_APCS; | |
9277 | break; | |
9278 | ||
9279 | case bfd_target_elf_flavour: | |
9280 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
9281 | e_flags = elf_elfheader (info.abfd)->e_flags; | |
9282 | ||
9283 | if (ei_osabi == ELFOSABI_ARM) | |
9284 | { | |
9285 | /* GNU tools used to use this value, but do not for EABI | |
9286 | objects. There's nowhere to tag an EABI version | |
9287 | anyway, so assume APCS. */ | |
9288 | arm_abi = ARM_ABI_APCS; | |
9289 | } | |
d403db27 | 9290 | else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) |
9779414d DJ |
9291 | { |
9292 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); | |
9779414d DJ |
9293 | |
9294 | switch (eabi_ver) | |
9295 | { | |
9296 | case EF_ARM_EABI_UNKNOWN: | |
9297 | /* Assume GNU tools. */ | |
9298 | arm_abi = ARM_ABI_APCS; | |
9299 | break; | |
9300 | ||
9301 | case EF_ARM_EABI_VER4: | |
9302 | case EF_ARM_EABI_VER5: | |
9303 | arm_abi = ARM_ABI_AAPCS; | |
9304 | /* EABI binaries default to VFP float ordering. | |
9305 | They may also contain build attributes that can | |
9306 | be used to identify if the VFP argument-passing | |
9307 | ABI is in use. */ | |
9308 | if (fp_model == ARM_FLOAT_AUTO) | |
9309 | { | |
9310 | #ifdef HAVE_ELF | |
9311 | switch (bfd_elf_get_obj_attr_int (info.abfd, | |
9312 | OBJ_ATTR_PROC, | |
9313 | Tag_ABI_VFP_args)) | |
9314 | { | |
b35b0298 | 9315 | case AEABI_VFP_args_base: |
9779414d DJ |
9316 | /* "The user intended FP parameter/result |
9317 | passing to conform to AAPCS, base | |
9318 | variant". */ | |
9319 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9320 | break; | |
b35b0298 | 9321 | case AEABI_VFP_args_vfp: |
9779414d DJ |
9322 | /* "The user intended FP parameter/result |
9323 | passing to conform to AAPCS, VFP | |
9324 | variant". */ | |
9325 | fp_model = ARM_FLOAT_VFP; | |
9326 | break; | |
b35b0298 | 9327 | case AEABI_VFP_args_toolchain: |
9779414d DJ |
9328 | /* "The user intended FP parameter/result |
9329 | passing to conform to tool chain-specific | |
9330 | conventions" - we don't know any such | |
9331 | conventions, so leave it as "auto". */ | |
9332 | break; | |
b35b0298 | 9333 | case AEABI_VFP_args_compatible: |
5c294fee TG |
9334 | /* "Code is compatible with both the base |
9335 | and VFP variants; the user did not permit | |
9336 | non-variadic functions to pass FP | |
9337 | parameters/results" - leave it as | |
9338 | "auto". */ | |
9339 | break; | |
9779414d DJ |
9340 | default: |
9341 | /* Attribute value not mentioned in the | |
5c294fee | 9342 | November 2012 ABI, so leave it as |
9779414d DJ |
9343 | "auto". */ |
9344 | break; | |
9345 | } | |
9346 | #else | |
9347 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9348 | #endif | |
9349 | } | |
9350 | break; | |
9351 | ||
9352 | default: | |
9353 | /* Leave it as "auto". */ | |
9354 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); | |
9355 | break; | |
9356 | } | |
9357 | ||
9358 | #ifdef HAVE_ELF | |
9359 | /* Detect M-profile programs. This only works if the | |
9360 | executable file includes build attributes; GCC does | |
9361 | copy them to the executable, but e.g. RealView does | |
9362 | not. */ | |
17cbafdb SM |
9363 | int attr_arch |
9364 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9365 | Tag_CPU_arch); | |
9366 | int attr_profile | |
9367 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9368 | Tag_CPU_arch_profile); | |
9369 | ||
9779414d DJ |
9370 | /* GCC specifies the profile for v6-M; RealView only |
9371 | specifies the profile for architectures starting with | |
9372 | V7 (as opposed to architectures with a tag | |
9373 | numerically greater than TAG_CPU_ARCH_V7). */ | |
9374 | if (!tdesc_has_registers (tdesc) | |
9375 | && (attr_arch == TAG_CPU_ARCH_V6_M | |
9376 | || attr_arch == TAG_CPU_ARCH_V6S_M | |
131a355f LM |
9377 | || attr_arch == TAG_CPU_ARCH_V7E_M |
9378 | || attr_arch == TAG_CPU_ARCH_V8M_BASE | |
9379 | || attr_arch == TAG_CPU_ARCH_V8M_MAIN | |
ae66a8f1 | 9380 | || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN |
9779414d | 9381 | || attr_profile == 'M')) |
7559c217 | 9382 | is_m = true; |
a01567f4 LM |
9383 | |
9384 | /* Look for attributes that indicate support for ARMv8.1-m | |
9385 | PACBTI. */ | |
9386 | if (!tdesc_has_registers (tdesc) && is_m) | |
9387 | { | |
9388 | int attr_pac_extension | |
9389 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9390 | Tag_PAC_extension); | |
9391 | ||
9392 | int attr_bti_extension | |
9393 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9394 | Tag_BTI_extension); | |
9395 | ||
9396 | int attr_pacret_use | |
9397 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9398 | Tag_PACRET_use); | |
9399 | ||
9400 | int attr_bti_use | |
9401 | = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC, | |
9402 | Tag_BTI_use); | |
9403 | ||
9404 | if (attr_pac_extension != 0 || attr_bti_extension != 0 | |
9405 | || attr_pacret_use != 0 || attr_bti_use != 0) | |
9406 | have_pacbti = true; | |
9407 | } | |
9779414d DJ |
9408 | #endif |
9409 | } | |
9410 | ||
9411 | if (fp_model == ARM_FLOAT_AUTO) | |
9412 | { | |
9779414d DJ |
9413 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
9414 | { | |
9415 | case 0: | |
9416 | /* Leave it as "auto". Strictly speaking this case | |
9417 | means FPA, but almost nobody uses that now, and | |
9418 | many toolchains fail to set the appropriate bits | |
9419 | for the floating-point model they use. */ | |
9420 | break; | |
9421 | case EF_ARM_SOFT_FLOAT: | |
9422 | fp_model = ARM_FLOAT_SOFT_FPA; | |
9423 | break; | |
9424 | case EF_ARM_VFP_FLOAT: | |
9425 | fp_model = ARM_FLOAT_VFP; | |
9426 | break; | |
9427 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
9428 | fp_model = ARM_FLOAT_SOFT_VFP; | |
9429 | break; | |
9430 | } | |
9431 | } | |
9432 | ||
9433 | if (e_flags & EF_ARM_BE8) | |
9434 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
9435 | ||
9436 | break; | |
9437 | ||
9438 | default: | |
9439 | /* Leave it as "auto". */ | |
9440 | break; | |
9441 | } | |
9442 | } | |
123dc839 DJ |
9443 | |
9444 | /* Check any target description for validity. */ | |
9779414d | 9445 | if (tdesc_has_registers (tdesc)) |
123dc839 DJ |
9446 | { |
9447 | /* For most registers we require GDB's default names; but also allow | |
9448 | the numeric names for sp / lr / pc, as a convenience. */ | |
9449 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
9450 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
9451 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
9452 | ||
9453 | const struct tdesc_feature *feature; | |
58d6951d | 9454 | int valid_p; |
123dc839 | 9455 | |
9779414d | 9456 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9457 | "org.gnu.gdb.arm.core"); |
9458 | if (feature == NULL) | |
9779414d DJ |
9459 | { |
9460 | feature = tdesc_find_feature (tdesc, | |
9461 | "org.gnu.gdb.arm.m-profile"); | |
9462 | if (feature == NULL) | |
9463 | return NULL; | |
9464 | else | |
7559c217 | 9465 | is_m = true; |
9779414d | 9466 | } |
123dc839 DJ |
9467 | |
9468 | tdesc_data = tdesc_data_alloc (); | |
9469 | ||
9470 | valid_p = 1; | |
9471 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
c1e1314d | 9472 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 | 9473 | arm_register_names[i]); |
c1e1314d | 9474 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9475 | ARM_SP_REGNUM, |
9476 | arm_sp_names); | |
c1e1314d | 9477 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9478 | ARM_LR_REGNUM, |
9479 | arm_lr_names); | |
c1e1314d | 9480 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
123dc839 DJ |
9481 | ARM_PC_REGNUM, |
9482 | arm_pc_names); | |
9779414d | 9483 | if (is_m) |
c1e1314d | 9484 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d DJ |
9485 | ARM_PS_REGNUM, "xpsr"); |
9486 | else | |
c1e1314d | 9487 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
9779414d | 9488 | ARM_PS_REGNUM, "cpsr"); |
123dc839 DJ |
9489 | |
9490 | if (!valid_p) | |
c1e1314d | 9491 | return NULL; |
123dc839 | 9492 | |
9779414d | 9493 | feature = tdesc_find_feature (tdesc, |
123dc839 DJ |
9494 | "org.gnu.gdb.arm.fpa"); |
9495 | if (feature != NULL) | |
9496 | { | |
9497 | valid_p = 1; | |
9498 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
c1e1314d | 9499 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
123dc839 DJ |
9500 | arm_register_names[i]); |
9501 | if (!valid_p) | |
c1e1314d | 9502 | return NULL; |
123dc839 | 9503 | } |
ff6f572f | 9504 | else |
7559c217 | 9505 | have_fpa_registers = false; |
ff6f572f | 9506 | |
9779414d | 9507 | feature = tdesc_find_feature (tdesc, |
ff6f572f DJ |
9508 | "org.gnu.gdb.xscale.iwmmxt"); |
9509 | if (feature != NULL) | |
9510 | { | |
9511 | static const char *const iwmmxt_names[] = { | |
9512 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
9513 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
9514 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
9515 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
9516 | }; | |
9517 | ||
9518 | valid_p = 1; | |
9519 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
9520 | valid_p | |
c1e1314d | 9521 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9522 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9523 | ||
9524 | /* Check for the control registers, but do not fail if they | |
9525 | are missing. */ | |
9526 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
c1e1314d | 9527 | tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9528 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9529 | ||
9530 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
9531 | valid_p | |
c1e1314d | 9532 | &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
ff6f572f DJ |
9533 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
9534 | ||
9535 | if (!valid_p) | |
c1e1314d | 9536 | return NULL; |
a56cc1ce | 9537 | |
7559c217 | 9538 | have_wmmx_registers = true; |
ff6f572f | 9539 | } |
58d6951d DJ |
9540 | |
9541 | /* If we have a VFP unit, check whether the single precision registers | |
9542 | are present. If not, then we will synthesize them as pseudo | |
9543 | registers. */ | |
9779414d | 9544 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9545 | "org.gnu.gdb.arm.vfp"); |
9546 | if (feature != NULL) | |
9547 | { | |
9548 | static const char *const vfp_double_names[] = { | |
9549 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
9550 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", | |
9551 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", | |
9552 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", | |
9553 | }; | |
9554 | ||
9555 | /* Require the double precision registers. There must be either | |
9556 | 16 or 32. */ | |
9557 | valid_p = 1; | |
9558 | for (i = 0; i < 32; i++) | |
9559 | { | |
c1e1314d | 9560 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
58d6951d DJ |
9561 | ARM_D0_REGNUM + i, |
9562 | vfp_double_names[i]); | |
9563 | if (!valid_p) | |
9564 | break; | |
9565 | } | |
2b9e5ea6 UW |
9566 | if (!valid_p && i == 16) |
9567 | valid_p = 1; | |
58d6951d | 9568 | |
2b9e5ea6 | 9569 | /* Also require FPSCR. */ |
c1e1314d | 9570 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
2b9e5ea6 UW |
9571 | ARM_FPSCR_REGNUM, "fpscr"); |
9572 | if (!valid_p) | |
c1e1314d | 9573 | return NULL; |
58d6951d | 9574 | |
ae66a8f1 SP |
9575 | have_vfp = true; |
9576 | ||
58d6951d | 9577 | if (tdesc_unnumbered_register (feature, "s0") == 0) |
ecbf5d4f | 9578 | have_s_pseudos = true; |
58d6951d | 9579 | |
330c6ca9 | 9580 | vfp_register_count = i; |
58d6951d DJ |
9581 | |
9582 | /* If we have VFP, also check for NEON. The architecture allows | |
9583 | NEON without VFP (integer vector operations only), but GDB | |
9584 | does not support that. */ | |
9779414d | 9585 | feature = tdesc_find_feature (tdesc, |
58d6951d DJ |
9586 | "org.gnu.gdb.arm.neon"); |
9587 | if (feature != NULL) | |
9588 | { | |
9589 | /* NEON requires 32 double-precision registers. */ | |
9590 | if (i != 32) | |
c1e1314d | 9591 | return NULL; |
58d6951d DJ |
9592 | |
9593 | /* If there are quad registers defined by the stub, use | |
9594 | their type; otherwise (normally) provide them with | |
9595 | the default type. */ | |
9596 | if (tdesc_unnumbered_register (feature, "q0") == 0) | |
ecbf5d4f | 9597 | have_q_pseudos = true; |
ae66a8f1 SP |
9598 | } |
9599 | } | |
9600 | ||
9601 | /* Check for MVE after all the checks for GPR's, VFP and Neon. | |
9602 | MVE (Helium) is an M-profile extension. */ | |
9603 | if (is_m) | |
9604 | { | |
9605 | /* Do we have the MVE feature? */ | |
9606 | feature = tdesc_find_feature (tdesc,"org.gnu.gdb.arm.m-profile-mve"); | |
9607 | ||
9608 | if (feature != nullptr) | |
9609 | { | |
9610 | /* If we have MVE, we must always have the VPR register. */ | |
9611 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
9612 | register_count, "vpr"); | |
9613 | if (!valid_p) | |
9614 | { | |
9615 | warning (_("MVE feature is missing required register vpr.")); | |
9616 | return nullptr; | |
9617 | } | |
58d6951d | 9618 | |
ae66a8f1 SP |
9619 | have_mve = true; |
9620 | mve_vpr_regnum = register_count; | |
9621 | register_count++; | |
9622 | ||
9623 | /* We can't have Q pseudo registers available here, as that | |
9624 | would mean we have NEON features, and that is only available | |
9625 | on A and R profiles. */ | |
9626 | gdb_assert (!have_q_pseudos); | |
9627 | ||
9628 | /* Given we have a M-profile target description, if MVE is | |
9629 | enabled and there are VFP registers, we should have Q | |
9630 | pseudo registers (Q0 ~ Q7). */ | |
9631 | if (have_vfp) | |
9632 | have_q_pseudos = true; | |
58d6951d | 9633 | } |
a01567f4 LM |
9634 | |
9635 | /* Do we have the ARMv8.1-m PACBTI feature? */ | |
9636 | feature = tdesc_find_feature (tdesc, | |
9637 | "org.gnu.gdb.arm.m-profile-pacbti"); | |
9638 | if (feature != nullptr) | |
9639 | { | |
9640 | /* By advertising this feature, the target acknowledges the | |
9641 | presence of the ARMv8.1-m PACBTI extensions. | |
9642 | ||
9643 | We don't care for any particular registers in this group, so | |
9644 | the target is free to include whatever it deems appropriate. | |
9645 | ||
9646 | The expectation is for this feature to include the PAC | |
9647 | keys. */ | |
9648 | have_pacbti = true; | |
9649 | } | |
58d6951d | 9650 | } |
123dc839 | 9651 | } |
39bbf761 | 9652 | |
28e97307 DJ |
9653 | /* If there is already a candidate, use it. */ |
9654 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
9655 | best_arch != NULL; | |
9656 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
9657 | { | |
345bd07c SM |
9658 | arm_gdbarch_tdep *tdep |
9659 | = (arm_gdbarch_tdep *) gdbarch_tdep (best_arch->gdbarch); | |
9660 | ||
9661 | if (arm_abi != ARM_ABI_AUTO && arm_abi != tdep->arm_abi) | |
28e97307 DJ |
9662 | continue; |
9663 | ||
345bd07c | 9664 | if (fp_model != ARM_FLOAT_AUTO && fp_model != tdep->fp_model) |
28e97307 DJ |
9665 | continue; |
9666 | ||
58d6951d DJ |
9667 | /* There are various other properties in tdep that we do not |
9668 | need to check here: those derived from a target description, | |
9669 | since gdbarches with a different target description are | |
9670 | automatically disqualified. */ | |
9671 | ||
9779414d | 9672 | /* Do check is_m, though, since it might come from the binary. */ |
345bd07c | 9673 | if (is_m != tdep->is_m) |
9779414d DJ |
9674 | continue; |
9675 | ||
a01567f4 LM |
9676 | /* Also check for ARMv8.1-m PACBTI support, since it might come from |
9677 | the binary. */ | |
9678 | if (have_pacbti != tdep->have_pacbti) | |
9679 | continue; | |
9680 | ||
28e97307 DJ |
9681 | /* Found a match. */ |
9682 | break; | |
9683 | } | |
97e03143 | 9684 | |
28e97307 | 9685 | if (best_arch != NULL) |
c1e1314d | 9686 | return best_arch->gdbarch; |
28e97307 | 9687 | |
345bd07c | 9688 | arm_gdbarch_tdep *tdep = new arm_gdbarch_tdep; |
97e03143 RE |
9689 | gdbarch = gdbarch_alloc (&info, tdep); |
9690 | ||
28e97307 DJ |
9691 | /* Record additional information about the architecture we are defining. |
9692 | These are gdbarch discriminators, like the OSABI. */ | |
9693 | tdep->arm_abi = arm_abi; | |
9694 | tdep->fp_model = fp_model; | |
9779414d | 9695 | tdep->is_m = is_m; |
ff6f572f | 9696 | tdep->have_fpa_registers = have_fpa_registers; |
a56cc1ce | 9697 | tdep->have_wmmx_registers = have_wmmx_registers; |
330c6ca9 YQ |
9698 | gdb_assert (vfp_register_count == 0 |
9699 | || vfp_register_count == 16 | |
9700 | || vfp_register_count == 32); | |
9701 | tdep->vfp_register_count = vfp_register_count; | |
ecbf5d4f LM |
9702 | tdep->have_s_pseudos = have_s_pseudos; |
9703 | tdep->have_q_pseudos = have_q_pseudos; | |
58d6951d | 9704 | tdep->have_neon = have_neon; |
08216dd7 | 9705 | |
ae66a8f1 SP |
9706 | /* Adjust the MVE feature settings. */ |
9707 | if (have_mve) | |
9708 | { | |
9709 | tdep->have_mve = true; | |
9710 | tdep->mve_vpr_regnum = mve_vpr_regnum; | |
9711 | } | |
9712 | ||
a01567f4 LM |
9713 | /* Adjust the PACBTI feature settings. */ |
9714 | tdep->have_pacbti = have_pacbti; | |
9715 | ||
25f8c692 JL |
9716 | arm_register_g_packet_guesses (gdbarch); |
9717 | ||
08216dd7 | 9718 | /* Breakpoints. */ |
9d4fde75 | 9719 | switch (info.byte_order_for_code) |
67255d04 RE |
9720 | { |
9721 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
9722 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
9723 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
9724 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
9725 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
9726 | ||
67255d04 RE |
9727 | break; |
9728 | ||
9729 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
9730 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
9731 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
9732 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
9733 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
9734 | ||
67255d04 RE |
9735 | break; |
9736 | ||
9737 | default: | |
9738 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 9739 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
9740 | } |
9741 | ||
d7b486e7 RE |
9742 | /* On ARM targets char defaults to unsigned. */ |
9743 | set_gdbarch_char_signed (gdbarch, 0); | |
9744 | ||
53375380 PA |
9745 | /* wchar_t is unsigned under the AAPCS. */ |
9746 | if (tdep->arm_abi == ARM_ABI_AAPCS) | |
9747 | set_gdbarch_wchar_signed (gdbarch, 0); | |
9748 | else | |
9749 | set_gdbarch_wchar_signed (gdbarch, 1); | |
53375380 | 9750 | |
030197b4 AB |
9751 | /* Compute type alignment. */ |
9752 | set_gdbarch_type_align (gdbarch, arm_type_align); | |
9753 | ||
cca44b1b JB |
9754 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
9755 | of additional scratch space. This setting isn't used for anything beside | |
9756 | displaced stepping at present. */ | |
e935475c | 9757 | set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS); |
cca44b1b | 9758 | |
9df628e0 | 9759 | /* This should be low enough for everything. */ |
97e03143 | 9760 | tdep->lowest_pc = 0x20; |
94c30b78 | 9761 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 9762 | |
7c00367c MK |
9763 | /* The default, for both APCS and AAPCS, is to return small |
9764 | structures in registers. */ | |
9765 | tdep->struct_return = reg_struct_return; | |
9766 | ||
2dd604e7 | 9767 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 9768 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 9769 | |
7eb89530 YQ |
9770 | if (is_m) |
9771 | set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); | |
9772 | ||
756fe439 DJ |
9773 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
9774 | ||
eb5492fa | 9775 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 9776 | |
34e8f22d | 9777 | /* Address manipulation. */ |
34e8f22d RE |
9778 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
9779 | ||
34e8f22d RE |
9780 | /* Advance PC across function entry code. */ |
9781 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
9782 | ||
c9cf6e20 MG |
9783 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
9784 | set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); | |
4024ca99 | 9785 | |
190dce09 UW |
9786 | /* Skip trampolines. */ |
9787 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
9788 | ||
34e8f22d RE |
9789 | /* The stack grows downward. */ |
9790 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
9791 | ||
9792 | /* Breakpoint manipulation. */ | |
04180708 YQ |
9793 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); |
9794 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); | |
833b7ab5 YQ |
9795 | set_gdbarch_breakpoint_kind_from_current_state (gdbarch, |
9796 | arm_breakpoint_kind_from_current_state); | |
34e8f22d RE |
9797 | |
9798 | /* Information about registers, etc. */ | |
34e8f22d RE |
9799 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
9800 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ecbf5d4f | 9801 | set_gdbarch_num_regs (gdbarch, register_count); |
7a5ea0d4 | 9802 | set_gdbarch_register_type (gdbarch, arm_register_type); |
54483882 | 9803 | set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p); |
34e8f22d | 9804 | |
ff6f572f DJ |
9805 | /* This "info float" is FPA-specific. Use the generic version if we |
9806 | do not have FPA. */ | |
345bd07c | 9807 | if (tdep->have_fpa_registers) |
ff6f572f DJ |
9808 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
9809 | ||
26216b98 | 9810 | /* Internal <-> external register number maps. */ |
ff6f572f | 9811 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
26216b98 AC |
9812 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
9813 | ||
34e8f22d RE |
9814 | set_gdbarch_register_name (gdbarch, arm_register_name); |
9815 | ||
9816 | /* Returning results. */ | |
2af48f68 | 9817 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 9818 | |
03d48a7d RE |
9819 | /* Disassembly. */ |
9820 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
9821 | ||
34e8f22d RE |
9822 | /* Minsymbol frobbing. */ |
9823 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
9824 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
9825 | arm_coff_make_msymbol_special); | |
60c5725c | 9826 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
34e8f22d | 9827 | |
f9d67f43 DJ |
9828 | /* Thumb-2 IT block support. */ |
9829 | set_gdbarch_adjust_breakpoint_address (gdbarch, | |
9830 | arm_adjust_breakpoint_address); | |
9831 | ||
0d5de010 DJ |
9832 | /* Virtual tables. */ |
9833 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
9834 | ||
97e03143 | 9835 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 9836 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 9837 | |
b39cc962 DJ |
9838 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
9839 | ||
eb5492fa | 9840 | /* Add some default predicates. */ |
2ae28aa9 YQ |
9841 | if (is_m) |
9842 | frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); | |
a262aec2 DJ |
9843 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
9844 | dwarf2_append_unwinders (gdbarch); | |
0e9e9abd | 9845 | frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); |
779aa56f | 9846 | frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); |
a262aec2 | 9847 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
eb5492fa | 9848 | |
97e03143 RE |
9849 | /* Now we have tuned the configuration, set a few final things, |
9850 | based on what the OS ABI has told us. */ | |
9851 | ||
b8926edc DJ |
9852 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
9853 | binaries are always marked. */ | |
9854 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
9855 | tdep->arm_abi = ARM_ABI_APCS; | |
9856 | ||
e3039479 UW |
9857 | /* Watchpoints are not steppable. */ |
9858 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
9859 | ||
b8926edc DJ |
9860 | /* We used to default to FPA for generic ARM, but almost nobody |
9861 | uses that now, and we now provide a way for the user to force | |
9862 | the model. So default to the most useful variant. */ | |
9863 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
9864 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
9865 | ||
9df628e0 RE |
9866 | if (tdep->jb_pc >= 0) |
9867 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
9868 | ||
08216dd7 | 9869 | /* Floating point sizes and format. */ |
8da61cc4 | 9870 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 9871 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 9872 | { |
8da61cc4 DJ |
9873 | set_gdbarch_double_format |
9874 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9875 | set_gdbarch_long_double_format | |
9876 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
9877 | } | |
9878 | else | |
9879 | { | |
9880 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
9881 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
9882 | } |
9883 | ||
a01567f4 LM |
9884 | /* Hook used to decorate frames with signed return addresses, only available |
9885 | for ARMv8.1-m PACBTI. */ | |
9886 | if (is_m && have_pacbti) | |
9887 | set_gdbarch_get_pc_address_flags (gdbarch, arm_get_pc_address_flags); | |
9888 | ||
dc22c61a LM |
9889 | if (tdesc_data != nullptr) |
9890 | { | |
9891 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); | |
9892 | ||
9893 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
ecbf5d4f | 9894 | register_count = gdbarch_num_regs (gdbarch); |
dc22c61a LM |
9895 | |
9896 | /* Override tdesc_register_type to adjust the types of VFP | |
9897 | registers for NEON. */ | |
9898 | set_gdbarch_register_type (gdbarch, arm_register_type); | |
9899 | } | |
9900 | ||
ecbf5d4f | 9901 | /* Initialize the pseudo register data. */ |
ae66a8f1 | 9902 | int num_pseudos = 0; |
ecbf5d4f | 9903 | if (tdep->have_s_pseudos) |
58d6951d | 9904 | { |
ecbf5d4f LM |
9905 | /* VFP single precision pseudo registers (S0~S31). */ |
9906 | tdep->s_pseudo_base = register_count; | |
9907 | tdep->s_pseudo_count = 32; | |
ae66a8f1 | 9908 | num_pseudos += tdep->s_pseudo_count; |
ecbf5d4f LM |
9909 | |
9910 | if (tdep->have_q_pseudos) | |
9911 | { | |
9912 | /* NEON quad precision pseudo registers (Q0~Q15). */ | |
9913 | tdep->q_pseudo_base = register_count + num_pseudos; | |
ae66a8f1 SP |
9914 | |
9915 | if (have_neon) | |
9916 | tdep->q_pseudo_count = 16; | |
9917 | else if (have_mve) | |
9918 | tdep->q_pseudo_count = ARM_MVE_NUM_Q_REGS; | |
9919 | ||
ecbf5d4f LM |
9920 | num_pseudos += tdep->q_pseudo_count; |
9921 | } | |
ae66a8f1 SP |
9922 | } |
9923 | ||
9924 | /* Do we have any MVE pseudo registers? */ | |
9925 | if (have_mve) | |
9926 | { | |
9927 | tdep->mve_pseudo_base = register_count + num_pseudos; | |
9928 | tdep->mve_pseudo_count = 1; | |
9929 | num_pseudos += tdep->mve_pseudo_count; | |
9930 | } | |
58d6951d | 9931 | |
a01567f4 LM |
9932 | /* Do we have any ARMv8.1-m PACBTI pseudo registers. */ |
9933 | if (have_pacbti) | |
9934 | { | |
9935 | tdep->pacbti_pseudo_base = register_count + num_pseudos; | |
9936 | tdep->pacbti_pseudo_count = 1; | |
9937 | num_pseudos += tdep->pacbti_pseudo_count; | |
9938 | } | |
9939 | ||
ae66a8f1 | 9940 | /* Set some pseudo register hooks, if we have pseudo registers. */ |
a01567f4 | 9941 | if (tdep->have_s_pseudos || have_mve || have_pacbti) |
ae66a8f1 | 9942 | { |
58d6951d DJ |
9943 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); |
9944 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); | |
9945 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); | |
9946 | } | |
9947 | ||
123dc839 | 9948 | /* Add standard register aliases. We add aliases even for those |
85102364 | 9949 | names which are used by the current architecture - it's simpler, |
123dc839 DJ |
9950 | and does no harm, since nothing ever lists user registers. */ |
9951 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
9952 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
9953 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
9954 | ||
65b48a81 PB |
9955 | set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options); |
9956 | set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ()); | |
9957 | ||
3426ae57 AH |
9958 | set_gdbarch_gnu_triplet_regexp (gdbarch, arm_gnu_triplet_regexp); |
9959 | ||
39bbf761 RE |
9960 | return gdbarch; |
9961 | } | |
9962 | ||
97e03143 | 9963 | static void |
2af46ca0 | 9964 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 9965 | { |
345bd07c | 9966 | arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
97e03143 RE |
9967 | |
9968 | if (tdep == NULL) | |
9969 | return; | |
9970 | ||
6cb06a8c TT |
9971 | gdb_printf (file, _("arm_dump_tdep: fp_model = %i\n"), |
9972 | (int) tdep->fp_model); | |
9973 | gdb_printf (file, _("arm_dump_tdep: have_fpa_registers = %i\n"), | |
9974 | (int) tdep->have_fpa_registers); | |
9975 | gdb_printf (file, _("arm_dump_tdep: have_wmmx_registers = %i\n"), | |
9976 | (int) tdep->have_wmmx_registers); | |
9977 | gdb_printf (file, _("arm_dump_tdep: vfp_register_count = %i\n"), | |
9978 | (int) tdep->vfp_register_count); | |
9979 | gdb_printf (file, _("arm_dump_tdep: have_s_pseudos = %s\n"), | |
9980 | tdep->have_s_pseudos? "true" : "false"); | |
9981 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_base = %i\n"), | |
9982 | (int) tdep->s_pseudo_base); | |
9983 | gdb_printf (file, _("arm_dump_tdep: s_pseudo_count = %i\n"), | |
9984 | (int) tdep->s_pseudo_count); | |
9985 | gdb_printf (file, _("arm_dump_tdep: have_q_pseudos = %s\n"), | |
9986 | tdep->have_q_pseudos? "true" : "false"); | |
9987 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_base = %i\n"), | |
9988 | (int) tdep->q_pseudo_base); | |
9989 | gdb_printf (file, _("arm_dump_tdep: q_pseudo_count = %i\n"), | |
9990 | (int) tdep->q_pseudo_count); | |
9991 | gdb_printf (file, _("arm_dump_tdep: have_neon = %i\n"), | |
9992 | (int) tdep->have_neon); | |
9993 | gdb_printf (file, _("arm_dump_tdep: have_mve = %s\n"), | |
9994 | tdep->have_mve? "yes" : "no"); | |
9995 | gdb_printf (file, _("arm_dump_tdep: mve_vpr_regnum = %i\n"), | |
9996 | tdep->mve_vpr_regnum); | |
9997 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_base = %i\n"), | |
9998 | tdep->mve_pseudo_base); | |
9999 | gdb_printf (file, _("arm_dump_tdep: mve_pseudo_count = %i\n"), | |
10000 | tdep->mve_pseudo_count); | |
10001 | gdb_printf (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"), | |
10002 | (unsigned long) tdep->lowest_pc); | |
a01567f4 LM |
10003 | gdb_printf (file, _("arm_dump_tdep: have_pacbti = %s\n"), |
10004 | tdep->have_pacbti? "yes" : "no"); | |
10005 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_base = %i\n"), | |
10006 | tdep->pacbti_pseudo_base); | |
10007 | gdb_printf (file, _("arm_dump_tdep: pacbti_pseudo_count = %i\n"), | |
10008 | tdep->pacbti_pseudo_count); | |
10009 | gdb_printf (file, _("arm_dump_tdep: is_m = %s\n"), | |
10010 | tdep->is_m? "yes" : "no"); | |
97e03143 RE |
10011 | } |
10012 | ||
0d4c07af | 10013 | #if GDB_SELF_TEST |
b121eeb9 YQ |
10014 | namespace selftests |
10015 | { | |
10016 | static void arm_record_test (void); | |
9ecab40c | 10017 | static void arm_analyze_prologue_test (); |
b121eeb9 | 10018 | } |
0d4c07af | 10019 | #endif |
b121eeb9 | 10020 | |
6c265988 | 10021 | void _initialize_arm_tdep (); |
c906108c | 10022 | void |
6c265988 | 10023 | _initialize_arm_tdep () |
c906108c | 10024 | { |
bc90b915 | 10025 | long length; |
65b48a81 | 10026 | int i, j; |
edefbb7c AC |
10027 | char regdesc[1024], *rdptr = regdesc; |
10028 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 10029 | |
42cf1509 | 10030 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 10031 | |
0e9e9abd | 10032 | /* Add ourselves to objfile event chain. */ |
c90e7d63 | 10033 | gdb::observers::new_objfile.attach (arm_exidx_new_objfile, "arm-tdep"); |
0e9e9abd | 10034 | |
70f80edf JT |
10035 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
10036 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
10037 | bfd_target_elf_flavour, | |
10038 | arm_elf_osabi_sniffer); | |
10039 | ||
afd7eef0 | 10040 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
f54bdb6d SM |
10041 | add_setshow_prefix_cmd ("arm", no_class, |
10042 | _("Various ARM-specific commands."), | |
10043 | _("Various ARM-specific commands."), | |
10044 | &setarmcmdlist, &showarmcmdlist, | |
10045 | &setlist, &showlist); | |
c5aa993b | 10046 | |
65b48a81 | 10047 | arm_disassembler_options = xstrdup ("reg-names-std"); |
471b9d15 MR |
10048 | const disasm_options_t *disasm_options |
10049 | = &disassembler_options_arm ()->options; | |
65b48a81 PB |
10050 | int num_disassembly_styles = 0; |
10051 | for (i = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10052 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10053 | num_disassembly_styles++; |
10054 | ||
10055 | /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ | |
8d749320 | 10056 | valid_disassembly_styles = XNEWVEC (const char *, |
65b48a81 PB |
10057 | num_disassembly_styles + 1); |
10058 | for (i = j = 0; disasm_options->name[i] != NULL; i++) | |
08dedd66 | 10059 | if (startswith (disasm_options->name[i], "reg-names-")) |
65b48a81 PB |
10060 | { |
10061 | size_t offset = strlen ("reg-names-"); | |
10062 | const char *style = disasm_options->name[i]; | |
10063 | valid_disassembly_styles[j++] = &style[offset]; | |
dedb7102 TT |
10064 | if (strcmp (&style[offset], "std") == 0) |
10065 | disassembly_style = &style[offset]; | |
65b48a81 PB |
10066 | length = snprintf (rdptr, rest, "%s - %s\n", &style[offset], |
10067 | disasm_options->description[i]); | |
10068 | rdptr += length; | |
10069 | rest -= length; | |
10070 | } | |
94c30b78 | 10071 | /* Mark the end of valid options. */ |
65b48a81 | 10072 | valid_disassembly_styles[num_disassembly_styles] = NULL; |
c906108c | 10073 | |
edefbb7c | 10074 | /* Create the help text. */ |
d7e74731 PA |
10075 | std::string helptext = string_printf ("%s%s%s", |
10076 | _("The valid values are:\n"), | |
10077 | regdesc, | |
10078 | _("The default is \"std\".")); | |
ed9a39eb | 10079 | |
edefbb7c AC |
10080 | add_setshow_enum_cmd("disassembler", no_class, |
10081 | valid_disassembly_styles, &disassembly_style, | |
10082 | _("Set the disassembly style."), | |
10083 | _("Show the disassembly style."), | |
09b0e4b0 | 10084 | helptext.c_str (), |
2c5b56ce | 10085 | set_disassembly_style_sfunc, |
65b48a81 | 10086 | show_disassembly_style_sfunc, |
7376b4c2 | 10087 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
10088 | |
10089 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
10090 | _("Set usage of ARM 32-bit mode."), | |
10091 | _("Show usage of ARM 32-bit mode."), | |
10092 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 10093 | NULL, |
0963b4bd MS |
10094 | NULL, /* FIXME: i18n: Usage of ARM 32-bit |
10095 | mode is %s. */ | |
26304000 | 10096 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 10097 | |
fd50bc42 | 10098 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
10099 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
10100 | _("Set the floating point type."), | |
10101 | _("Show the floating point type."), | |
10102 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
10103 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
10104 | fpa - FPA co-processor (GCC compiled).\n\ | |
10105 | softvfp - Software FP with pure-endian doubles.\n\ | |
10106 | vfp - VFP co-processor."), | |
edefbb7c | 10107 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 10108 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 10109 | |
28e97307 DJ |
10110 | /* Add a command to allow the user to force the ABI. */ |
10111 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
10112 | _("Set the ABI."), | |
10113 | _("Show the ABI."), | |
10114 | NULL, arm_set_abi, arm_show_abi, | |
10115 | &setarmcmdlist, &showarmcmdlist); | |
10116 | ||
0428b8f5 DJ |
10117 | /* Add two commands to allow the user to force the assumed |
10118 | execution mode. */ | |
10119 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
10120 | arm_mode_strings, &arm_fallback_mode_string, | |
10121 | _("Set the mode assumed when symbols are unavailable."), | |
10122 | _("Show the mode assumed when symbols are unavailable."), | |
10123 | NULL, NULL, arm_show_fallback_mode, | |
10124 | &setarmcmdlist, &showarmcmdlist); | |
10125 | add_setshow_enum_cmd ("force-mode", class_support, | |
10126 | arm_mode_strings, &arm_force_mode_string, | |
10127 | _("Set the mode assumed even when symbols are available."), | |
10128 | _("Show the mode assumed even when symbols are available."), | |
10129 | NULL, NULL, arm_show_force_mode, | |
10130 | &setarmcmdlist, &showarmcmdlist); | |
10131 | ||
6529d2dd | 10132 | /* Debugging flag. */ |
edefbb7c AC |
10133 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
10134 | _("Set ARM debugging."), | |
10135 | _("Show ARM debugging."), | |
10136 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 10137 | NULL, |
7915a72c | 10138 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 10139 | &setdebuglist, &showdebuglist); |
b121eeb9 YQ |
10140 | |
10141 | #if GDB_SELF_TEST | |
1526853e | 10142 | selftests::register_test ("arm-record", selftests::arm_record_test); |
9ecab40c | 10143 | selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test); |
b121eeb9 YQ |
10144 | #endif |
10145 | ||
c906108c | 10146 | } |
72508ac0 PO |
10147 | |
10148 | /* ARM-reversible process record data structures. */ | |
10149 | ||
10150 | #define ARM_INSN_SIZE_BYTES 4 | |
10151 | #define THUMB_INSN_SIZE_BYTES 2 | |
10152 | #define THUMB2_INSN_SIZE_BYTES 4 | |
10153 | ||
10154 | ||
71e396f9 LM |
10155 | /* Position of the bit within a 32-bit ARM instruction |
10156 | that defines whether the instruction is a load or store. */ | |
72508ac0 PO |
10157 | #define INSN_S_L_BIT_NUM 20 |
10158 | ||
10159 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10160 | do \ |
10161 | { \ | |
10162 | unsigned int reg_len = LENGTH; \ | |
10163 | if (reg_len) \ | |
10164 | { \ | |
10165 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
10166 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
10167 | } \ | |
10168 | } \ | |
10169 | while (0) | |
72508ac0 PO |
10170 | |
10171 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
10172 | do \ |
10173 | { \ | |
10174 | unsigned int mem_len = LENGTH; \ | |
10175 | if (mem_len) \ | |
01add95b SM |
10176 | { \ |
10177 | MEMS = XNEWVEC (struct arm_mem_r, mem_len); \ | |
10178 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
10179 | sizeof(struct arm_mem_r) * LENGTH); \ | |
10180 | } \ | |
dda83cd7 SM |
10181 | } \ |
10182 | while (0) | |
72508ac0 PO |
10183 | |
10184 | /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */ | |
10185 | #define INSN_RECORDED(ARM_RECORD) \ | |
dda83cd7 | 10186 | (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count) |
72508ac0 PO |
10187 | |
10188 | /* ARM memory record structure. */ | |
10189 | struct arm_mem_r | |
10190 | { | |
10191 | uint32_t len; /* Record length. */ | |
bfbbec00 | 10192 | uint32_t addr; /* Memory address. */ |
72508ac0 PO |
10193 | }; |
10194 | ||
10195 | /* ARM instruction record contains opcode of current insn | |
10196 | and execution state (before entry to decode_insn()), | |
10197 | contains list of to-be-modified registers and | |
10198 | memory blocks (on return from decode_insn()). */ | |
10199 | ||
10200 | typedef struct insn_decode_record_t | |
10201 | { | |
10202 | struct gdbarch *gdbarch; | |
10203 | struct regcache *regcache; | |
10204 | CORE_ADDR this_addr; /* Address of the insn being decoded. */ | |
10205 | uint32_t arm_insn; /* Should accommodate thumb. */ | |
10206 | uint32_t cond; /* Condition code. */ | |
10207 | uint32_t opcode; /* Insn opcode. */ | |
10208 | uint32_t decode; /* Insn decode bits. */ | |
10209 | uint32_t mem_rec_count; /* No of mem records. */ | |
10210 | uint32_t reg_rec_count; /* No of reg records. */ | |
10211 | uint32_t *arm_regs; /* Registers to be saved for this record. */ | |
10212 | struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ | |
10213 | } insn_decode_record; | |
10214 | ||
10215 | ||
10216 | /* Checks ARM SBZ and SBO mandatory fields. */ | |
10217 | ||
10218 | static int | |
10219 | sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) | |
10220 | { | |
10221 | uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); | |
10222 | ||
10223 | if (!len) | |
10224 | return 1; | |
10225 | ||
10226 | if (!sbo) | |
10227 | ones = ~ones; | |
10228 | ||
10229 | while (ones) | |
10230 | { | |
10231 | if (!(ones & sbo)) | |
dda83cd7 SM |
10232 | { |
10233 | return 0; | |
10234 | } | |
72508ac0 PO |
10235 | ones = ones >> 1; |
10236 | } | |
10237 | return 1; | |
10238 | } | |
10239 | ||
c6ec2b30 OJ |
10240 | enum arm_record_result |
10241 | { | |
10242 | ARM_RECORD_SUCCESS = 0, | |
10243 | ARM_RECORD_FAILURE = 1 | |
10244 | }; | |
10245 | ||
72508ac0 PO |
10246 | typedef enum |
10247 | { | |
10248 | ARM_RECORD_STRH=1, | |
10249 | ARM_RECORD_STRD | |
10250 | } arm_record_strx_t; | |
10251 | ||
10252 | typedef enum | |
10253 | { | |
10254 | ARM_RECORD=1, | |
10255 | THUMB_RECORD, | |
10256 | THUMB2_RECORD | |
10257 | } record_type_t; | |
10258 | ||
10259 | ||
10260 | static int | |
10261 | arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, | |
dda83cd7 | 10262 | uint32_t *record_buf_mem, arm_record_strx_t str_type) |
72508ac0 PO |
10263 | { |
10264 | ||
10265 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10266 | ULONGEST u_regval[2]= {0}; | |
10267 | ||
10268 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
10269 | uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; | |
72508ac0 PO |
10270 | |
10271 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10272 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
72508ac0 PO |
10273 | |
10274 | if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10275 | { | |
10276 | /* 1) Handle misc store, immediate offset. */ | |
10277 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10278 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10279 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10280 | regcache_raw_read_unsigned (reg_cache, reg_src1, | |
dda83cd7 | 10281 | &u_regval[0]); |
72508ac0 | 10282 | if (ARM_PC_REGNUM == reg_src1) |
dda83cd7 SM |
10283 | { |
10284 | /* If R15 was used as Rn, hence current PC+8. */ | |
10285 | u_regval[0] = u_regval[0] + 8; | |
10286 | } | |
72508ac0 PO |
10287 | offset_8 = (immed_high << 4) | immed_low; |
10288 | /* Calculate target store address. */ | |
10289 | if (14 == arm_insn_r->opcode) | |
dda83cd7 SM |
10290 | { |
10291 | tgt_mem_addr = u_regval[0] + offset_8; | |
10292 | } | |
72508ac0 | 10293 | else |
dda83cd7 SM |
10294 | { |
10295 | tgt_mem_addr = u_regval[0] - offset_8; | |
10296 | } | |
72508ac0 | 10297 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10298 | { |
10299 | record_buf_mem[0] = 2; | |
10300 | record_buf_mem[1] = tgt_mem_addr; | |
10301 | arm_insn_r->mem_rec_count = 1; | |
10302 | } | |
72508ac0 | 10303 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10304 | { |
10305 | record_buf_mem[0] = 4; | |
10306 | record_buf_mem[1] = tgt_mem_addr; | |
10307 | record_buf_mem[2] = 4; | |
10308 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10309 | arm_insn_r->mem_rec_count = 2; | |
10310 | } | |
72508ac0 PO |
10311 | } |
10312 | else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode) | |
10313 | { | |
10314 | /* 2) Store, register offset. */ | |
10315 | /* Get Rm. */ | |
10316 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10317 | /* Get Rn. */ | |
10318 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10319 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10320 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10321 | if (15 == reg_src2) | |
dda83cd7 SM |
10322 | { |
10323 | /* If R15 was used as Rn, hence current PC+8. */ | |
10324 | u_regval[0] = u_regval[0] + 8; | |
10325 | } | |
72508ac0 PO |
10326 | /* Calculate target store address, Rn +/- Rm, register offset. */ |
10327 | if (12 == arm_insn_r->opcode) | |
dda83cd7 SM |
10328 | { |
10329 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10330 | } | |
72508ac0 | 10331 | else |
dda83cd7 SM |
10332 | { |
10333 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10334 | } | |
72508ac0 | 10335 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10336 | { |
10337 | record_buf_mem[0] = 2; | |
10338 | record_buf_mem[1] = tgt_mem_addr; | |
10339 | arm_insn_r->mem_rec_count = 1; | |
10340 | } | |
72508ac0 | 10341 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10342 | { |
10343 | record_buf_mem[0] = 4; | |
10344 | record_buf_mem[1] = tgt_mem_addr; | |
10345 | record_buf_mem[2] = 4; | |
10346 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10347 | arm_insn_r->mem_rec_count = 2; | |
10348 | } | |
72508ac0 PO |
10349 | } |
10350 | else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
dda83cd7 | 10351 | || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) |
72508ac0 PO |
10352 | { |
10353 | /* 3) Store, immediate pre-indexed. */ | |
10354 | /* 5) Store, immediate post-indexed. */ | |
10355 | immed_low = bits (arm_insn_r->arm_insn, 0, 3); | |
10356 | immed_high = bits (arm_insn_r->arm_insn, 8, 11); | |
10357 | offset_8 = (immed_high << 4) | immed_low; | |
10358 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10359 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10360 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10361 | if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode) | |
dda83cd7 SM |
10362 | { |
10363 | tgt_mem_addr = u_regval[0] + offset_8; | |
10364 | } | |
72508ac0 | 10365 | else |
dda83cd7 SM |
10366 | { |
10367 | tgt_mem_addr = u_regval[0] - offset_8; | |
10368 | } | |
72508ac0 | 10369 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10370 | { |
10371 | record_buf_mem[0] = 2; | |
10372 | record_buf_mem[1] = tgt_mem_addr; | |
10373 | arm_insn_r->mem_rec_count = 1; | |
10374 | } | |
72508ac0 | 10375 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10376 | { |
10377 | record_buf_mem[0] = 4; | |
10378 | record_buf_mem[1] = tgt_mem_addr; | |
10379 | record_buf_mem[2] = 4; | |
10380 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10381 | arm_insn_r->mem_rec_count = 2; | |
10382 | } | |
72508ac0 PO |
10383 | /* Record Rn also as it changes. */ |
10384 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
10385 | arm_insn_r->reg_rec_count = 1; | |
10386 | } | |
10387 | else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode | |
dda83cd7 | 10388 | || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) |
72508ac0 PO |
10389 | { |
10390 | /* 4) Store, register pre-indexed. */ | |
10391 | /* 6) Store, register post -indexed. */ | |
10392 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
10393 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
10394 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10395 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
10396 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
10397 | if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode) | |
dda83cd7 SM |
10398 | { |
10399 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
10400 | } | |
72508ac0 | 10401 | else |
dda83cd7 SM |
10402 | { |
10403 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
10404 | } | |
72508ac0 | 10405 | if (ARM_RECORD_STRH == str_type) |
dda83cd7 SM |
10406 | { |
10407 | record_buf_mem[0] = 2; | |
10408 | record_buf_mem[1] = tgt_mem_addr; | |
10409 | arm_insn_r->mem_rec_count = 1; | |
10410 | } | |
72508ac0 | 10411 | else if (ARM_RECORD_STRD == str_type) |
dda83cd7 SM |
10412 | { |
10413 | record_buf_mem[0] = 4; | |
10414 | record_buf_mem[1] = tgt_mem_addr; | |
10415 | record_buf_mem[2] = 4; | |
10416 | record_buf_mem[3] = tgt_mem_addr + 4; | |
10417 | arm_insn_r->mem_rec_count = 2; | |
10418 | } | |
72508ac0 PO |
10419 | /* Record Rn also as it changes. */ |
10420 | *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19); | |
10421 | arm_insn_r->reg_rec_count = 1; | |
10422 | } | |
10423 | return 0; | |
10424 | } | |
10425 | ||
10426 | /* Handling ARM extension space insns. */ | |
10427 | ||
10428 | static int | |
10429 | arm_record_extension_space (insn_decode_record *arm_insn_r) | |
10430 | { | |
df95a9cf | 10431 | int ret = 0; /* Return value: -1:record failure ; 0:success */ |
72508ac0 PO |
10432 | uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; |
10433 | uint32_t record_buf[8], record_buf_mem[8]; | |
10434 | uint32_t reg_src1 = 0; | |
72508ac0 PO |
10435 | struct regcache *reg_cache = arm_insn_r->regcache; |
10436 | ULONGEST u_regval = 0; | |
10437 | ||
10438 | gdb_assert (!INSN_RECORDED(arm_insn_r)); | |
10439 | /* Handle unconditional insn extension space. */ | |
10440 | ||
10441 | opcode1 = bits (arm_insn_r->arm_insn, 20, 27); | |
10442 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
10443 | if (arm_insn_r->cond) | |
10444 | { | |
10445 | /* PLD has no affect on architectural state, it just affects | |
dda83cd7 | 10446 | the caches. */ |
72508ac0 | 10447 | if (5 == ((opcode1 & 0xE0) >> 5)) |
dda83cd7 SM |
10448 | { |
10449 | /* BLX(1) */ | |
10450 | record_buf[0] = ARM_PS_REGNUM; | |
10451 | record_buf[1] = ARM_LR_REGNUM; | |
10452 | arm_insn_r->reg_rec_count = 2; | |
10453 | } | |
72508ac0 PO |
10454 | /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */ |
10455 | } | |
10456 | ||
10457 | ||
10458 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10459 | if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4)) | |
10460 | { | |
10461 | ret = -1; | |
10462 | /* Undefined instruction on ARM V5; need to handle if later | |
dda83cd7 | 10463 | versions define it. */ |
72508ac0 PO |
10464 | } |
10465 | ||
10466 | opcode1 = bits (arm_insn_r->arm_insn, 24, 27); | |
10467 | opcode2 = bits (arm_insn_r->arm_insn, 4, 7); | |
10468 | insn_op1 = bits (arm_insn_r->arm_insn, 20, 23); | |
10469 | ||
10470 | /* Handle arithmetic insn extension space. */ | |
10471 | if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond | |
10472 | && !INSN_RECORDED(arm_insn_r)) | |
10473 | { | |
10474 | /* Handle MLA(S) and MUL(S). */ | |
b020ff80 | 10475 | if (in_inclusive_range (insn_op1, 0U, 3U)) |
01add95b SM |
10476 | { |
10477 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10478 | record_buf[1] = ARM_PS_REGNUM; | |
10479 | arm_insn_r->reg_rec_count = 2; | |
10480 | } | |
b020ff80 | 10481 | else if (in_inclusive_range (insn_op1, 4U, 15U)) |
01add95b SM |
10482 | { |
10483 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
10484 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10485 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10486 | record_buf[2] = ARM_PS_REGNUM; | |
10487 | arm_insn_r->reg_rec_count = 3; | |
10488 | } | |
72508ac0 PO |
10489 | } |
10490 | ||
10491 | opcode1 = bits (arm_insn_r->arm_insn, 26, 27); | |
10492 | opcode2 = bits (arm_insn_r->arm_insn, 23, 24); | |
10493 | insn_op1 = bits (arm_insn_r->arm_insn, 21, 22); | |
10494 | ||
10495 | /* Handle control insn extension space. */ | |
10496 | ||
10497 | if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20) | |
10498 | && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r)) | |
10499 | { | |
10500 | if (!bit (arm_insn_r->arm_insn,25)) | |
dda83cd7 SM |
10501 | { |
10502 | if (!bits (arm_insn_r->arm_insn, 4, 7)) | |
10503 | { | |
10504 | if ((0 == insn_op1) || (2 == insn_op1)) | |
10505 | { | |
10506 | /* MRS. */ | |
10507 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10508 | arm_insn_r->reg_rec_count = 1; | |
10509 | } | |
10510 | else if (1 == insn_op1) | |
10511 | { | |
10512 | /* CSPR is going to be changed. */ | |
10513 | record_buf[0] = ARM_PS_REGNUM; | |
10514 | arm_insn_r->reg_rec_count = 1; | |
10515 | } | |
10516 | else if (3 == insn_op1) | |
10517 | { | |
10518 | /* SPSR is going to be changed. */ | |
10519 | /* We need to get SPSR value, which is yet to be done. */ | |
10520 | return -1; | |
10521 | } | |
10522 | } | |
10523 | else if (1 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10524 | { | |
10525 | if (1 == insn_op1) | |
10526 | { | |
10527 | /* BX. */ | |
10528 | record_buf[0] = ARM_PS_REGNUM; | |
10529 | arm_insn_r->reg_rec_count = 1; | |
10530 | } | |
10531 | else if (3 == insn_op1) | |
10532 | { | |
10533 | /* CLZ. */ | |
10534 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10535 | arm_insn_r->reg_rec_count = 1; | |
10536 | } | |
10537 | } | |
10538 | else if (3 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10539 | { | |
10540 | /* BLX. */ | |
10541 | record_buf[0] = ARM_PS_REGNUM; | |
10542 | record_buf[1] = ARM_LR_REGNUM; | |
10543 | arm_insn_r->reg_rec_count = 2; | |
10544 | } | |
10545 | else if (5 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10546 | { | |
10547 | /* QADD, QSUB, QDADD, QDSUB */ | |
10548 | record_buf[0] = ARM_PS_REGNUM; | |
10549 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10550 | arm_insn_r->reg_rec_count = 2; | |
10551 | } | |
10552 | else if (7 == bits (arm_insn_r->arm_insn, 4, 7)) | |
10553 | { | |
10554 | /* BKPT. */ | |
10555 | record_buf[0] = ARM_PS_REGNUM; | |
10556 | record_buf[1] = ARM_LR_REGNUM; | |
10557 | arm_insn_r->reg_rec_count = 2; | |
10558 | ||
10559 | /* Save SPSR also;how? */ | |
10560 | return -1; | |
10561 | } | |
10562 | else if(8 == bits (arm_insn_r->arm_insn, 4, 7) | |
10563 | || 10 == bits (arm_insn_r->arm_insn, 4, 7) | |
10564 | || 12 == bits (arm_insn_r->arm_insn, 4, 7) | |
10565 | || 14 == bits (arm_insn_r->arm_insn, 4, 7) | |
10566 | ) | |
10567 | { | |
10568 | if (0 == insn_op1 || 1 == insn_op1) | |
10569 | { | |
10570 | /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */ | |
10571 | /* We dont do optimization for SMULW<y> where we | |
10572 | need only Rd. */ | |
10573 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10574 | record_buf[1] = ARM_PS_REGNUM; | |
10575 | arm_insn_r->reg_rec_count = 2; | |
10576 | } | |
10577 | else if (2 == insn_op1) | |
10578 | { | |
10579 | /* SMLAL<x><y>. */ | |
10580 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10581 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
10582 | arm_insn_r->reg_rec_count = 2; | |
10583 | } | |
10584 | else if (3 == insn_op1) | |
10585 | { | |
10586 | /* SMUL<x><y>. */ | |
10587 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10588 | arm_insn_r->reg_rec_count = 1; | |
10589 | } | |
10590 | } | |
10591 | } | |
72508ac0 | 10592 | else |
dda83cd7 SM |
10593 | { |
10594 | /* MSR : immediate form. */ | |
10595 | if (1 == insn_op1) | |
10596 | { | |
10597 | /* CSPR is going to be changed. */ | |
10598 | record_buf[0] = ARM_PS_REGNUM; | |
10599 | arm_insn_r->reg_rec_count = 1; | |
10600 | } | |
10601 | else if (3 == insn_op1) | |
10602 | { | |
10603 | /* SPSR is going to be changed. */ | |
10604 | /* we need to get SPSR value, which is yet to be done */ | |
10605 | return -1; | |
10606 | } | |
10607 | } | |
72508ac0 PO |
10608 | } |
10609 | ||
10610 | opcode1 = bits (arm_insn_r->arm_insn, 25, 27); | |
10611 | opcode2 = bits (arm_insn_r->arm_insn, 20, 24); | |
10612 | insn_op1 = bits (arm_insn_r->arm_insn, 5, 6); | |
10613 | ||
10614 | /* Handle load/store insn extension space. */ | |
10615 | ||
10616 | if (!opcode1 && bit (arm_insn_r->arm_insn, 7) | |
10617 | && bit (arm_insn_r->arm_insn, 4) && 1 != arm_insn_r->cond | |
10618 | && !INSN_RECORDED(arm_insn_r)) | |
10619 | { | |
10620 | /* SWP/SWPB. */ | |
10621 | if (0 == insn_op1) | |
dda83cd7 SM |
10622 | { |
10623 | /* These insn, changes register and memory as well. */ | |
10624 | /* SWP or SWPB insn. */ | |
10625 | /* Get memory address given by Rn. */ | |
10626 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10627 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
10628 | /* SWP insn ?, swaps word. */ | |
10629 | if (8 == arm_insn_r->opcode) | |
10630 | { | |
10631 | record_buf_mem[0] = 4; | |
10632 | } | |
10633 | else | |
10634 | { | |
10635 | /* SWPB insn, swaps only byte. */ | |
10636 | record_buf_mem[0] = 1; | |
10637 | } | |
10638 | record_buf_mem[1] = u_regval; | |
10639 | arm_insn_r->mem_rec_count = 1; | |
10640 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10641 | arm_insn_r->reg_rec_count = 1; | |
10642 | } | |
72508ac0 | 10643 | else if (1 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10644 | { |
10645 | /* STRH. */ | |
10646 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10647 | ARM_RECORD_STRH); | |
10648 | } | |
72508ac0 | 10649 | else if (2 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10650 | { |
10651 | /* LDRD. */ | |
10652 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10653 | record_buf[1] = record_buf[0] + 1; | |
10654 | arm_insn_r->reg_rec_count = 2; | |
10655 | } | |
72508ac0 | 10656 | else if (3 == insn_op1 && !bit (arm_insn_r->arm_insn, 20)) |
dda83cd7 SM |
10657 | { |
10658 | /* STRD. */ | |
10659 | arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0], | |
10660 | ARM_RECORD_STRD); | |
10661 | } | |
72508ac0 | 10662 | else if (bit (arm_insn_r->arm_insn, 20) && insn_op1 <= 3) |
dda83cd7 SM |
10663 | { |
10664 | /* LDRH, LDRSB, LDRSH. */ | |
10665 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10666 | arm_insn_r->reg_rec_count = 1; | |
10667 | } | |
72508ac0 PO |
10668 | |
10669 | } | |
10670 | ||
10671 | opcode1 = bits (arm_insn_r->arm_insn, 23, 27); | |
10672 | if (24 == opcode1 && bit (arm_insn_r->arm_insn, 21) | |
10673 | && !INSN_RECORDED(arm_insn_r)) | |
10674 | { | |
10675 | ret = -1; | |
10676 | /* Handle coprocessor insn extension space. */ | |
10677 | } | |
10678 | ||
10679 | /* To be done for ARMv5 and later; as of now we return -1. */ | |
10680 | if (-1 == ret) | |
ca92db2d | 10681 | return ret; |
72508ac0 PO |
10682 | |
10683 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10684 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10685 | ||
10686 | return ret; | |
10687 | } | |
10688 | ||
10689 | /* Handling opcode 000 insns. */ | |
10690 | ||
10691 | static int | |
10692 | arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) | |
10693 | { | |
10694 | struct regcache *reg_cache = arm_insn_r->regcache; | |
10695 | uint32_t record_buf[8], record_buf_mem[8]; | |
10696 | ULONGEST u_regval[2] = {0}; | |
10697 | ||
8d49165d | 10698 | uint32_t reg_src1 = 0; |
72508ac0 PO |
10699 | uint32_t opcode1 = 0; |
10700 | ||
10701 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10702 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10703 | opcode1 = bits (arm_insn_r->arm_insn, 20, 24); | |
10704 | ||
2d9e6acb | 10705 | if (!((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10706 | { |
2d9e6acb YQ |
10707 | /* Data-processing (register) and Data-processing (register-shifted |
10708 | register */ | |
10709 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
10710 | register, which is specified by 13-16 decode. */ | |
10711 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10712 | record_buf[1] = ARM_PS_REGNUM; | |
10713 | arm_insn_r->reg_rec_count = 2; | |
72508ac0 | 10714 | } |
2d9e6acb | 10715 | else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10)) |
72508ac0 | 10716 | { |
2d9e6acb YQ |
10717 | /* Miscellaneous instructions */ |
10718 | ||
10719 | if (3 == arm_insn_r->decode && 0x12 == opcode1 | |
10720 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10721 | { | |
10722 | /* Handle BLX, branch and link/exchange. */ | |
10723 | if (9 == arm_insn_r->opcode) | |
10724 | { | |
10725 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm, | |
10726 | and R14 stores the return address. */ | |
10727 | record_buf[0] = ARM_PS_REGNUM; | |
10728 | record_buf[1] = ARM_LR_REGNUM; | |
10729 | arm_insn_r->reg_rec_count = 2; | |
10730 | } | |
10731 | } | |
10732 | else if (7 == arm_insn_r->decode && 0x12 == opcode1) | |
10733 | { | |
10734 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
10735 | /* CPSR is changed to be executed in ARM state, disabling normal | |
10736 | interrupts, entering abort mode. */ | |
10737 | /* According to high vector configuration PC is set. */ | |
10738 | /* user hit breakpoint and type reverse, in | |
10739 | that case, we need to go back with previous CPSR and | |
10740 | Program Counter. */ | |
10741 | record_buf[0] = ARM_PS_REGNUM; | |
10742 | record_buf[1] = ARM_LR_REGNUM; | |
10743 | arm_insn_r->reg_rec_count = 2; | |
10744 | ||
10745 | /* Save SPSR also; how? */ | |
10746 | return -1; | |
10747 | } | |
10748 | else if (1 == arm_insn_r->decode && 0x12 == opcode1 | |
10749 | && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) | |
10750 | { | |
10751 | /* Handle BX, branch and link/exchange. */ | |
10752 | /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ | |
10753 | record_buf[0] = ARM_PS_REGNUM; | |
10754 | arm_insn_r->reg_rec_count = 1; | |
10755 | } | |
10756 | else if (1 == arm_insn_r->decode && 0x16 == opcode1 | |
10757 | && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1) | |
10758 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) | |
10759 | { | |
10760 | /* Count leading zeros: CLZ. */ | |
10761 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10762 | arm_insn_r->reg_rec_count = 1; | |
10763 | } | |
10764 | else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM) | |
10765 | && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) | |
10766 | && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1) | |
10767 | && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) | |
10768 | { | |
10769 | /* Handle MRS insn. */ | |
10770 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10771 | arm_insn_r->reg_rec_count = 1; | |
10772 | } | |
72508ac0 | 10773 | } |
2d9e6acb | 10774 | else if (9 == arm_insn_r->decode && opcode1 < 0x10) |
72508ac0 | 10775 | { |
2d9e6acb YQ |
10776 | /* Multiply and multiply-accumulate */ |
10777 | ||
10778 | /* Handle multiply instructions. */ | |
10779 | /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ | |
10780 | if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) | |
f2a883a8 SM |
10781 | { |
10782 | /* Handle MLA and MUL. */ | |
10783 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10784 | record_buf[1] = ARM_PS_REGNUM; | |
10785 | arm_insn_r->reg_rec_count = 2; | |
10786 | } | |
10787 | else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) | |
10788 | { | |
10789 | /* Handle SMLAL, SMULL, UMLAL, UMULL. */ | |
10790 | record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); | |
10791 | record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); | |
10792 | record_buf[2] = ARM_PS_REGNUM; | |
10793 | arm_insn_r->reg_rec_count = 3; | |
10794 | } | |
2d9e6acb YQ |
10795 | } |
10796 | else if (9 == arm_insn_r->decode && opcode1 > 0x10) | |
10797 | { | |
10798 | /* Synchronization primitives */ | |
10799 | ||
72508ac0 PO |
10800 | /* Handling SWP, SWPB. */ |
10801 | /* These insn, changes register and memory as well. */ | |
10802 | /* SWP or SWPB insn. */ | |
10803 | ||
10804 | reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); | |
10805 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
10806 | /* SWP insn ?, swaps word. */ | |
10807 | if (8 == arm_insn_r->opcode) | |
2d9e6acb YQ |
10808 | { |
10809 | record_buf_mem[0] = 4; | |
10810 | } | |
10811 | else | |
10812 | { | |
10813 | /* SWPB insn, swaps only byte. */ | |
10814 | record_buf_mem[0] = 1; | |
10815 | } | |
72508ac0 PO |
10816 | record_buf_mem[1] = u_regval[0]; |
10817 | arm_insn_r->mem_rec_count = 1; | |
10818 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10819 | arm_insn_r->reg_rec_count = 1; | |
10820 | } | |
2d9e6acb YQ |
10821 | else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode |
10822 | || 15 == arm_insn_r->decode) | |
72508ac0 | 10823 | { |
2d9e6acb YQ |
10824 | if ((opcode1 & 0x12) == 2) |
10825 | { | |
10826 | /* Extra load/store (unprivileged) */ | |
10827 | return -1; | |
10828 | } | |
10829 | else | |
10830 | { | |
10831 | /* Extra load/store */ | |
10832 | switch (bits (arm_insn_r->arm_insn, 5, 6)) | |
10833 | { | |
10834 | case 1: | |
10835 | if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4) | |
10836 | { | |
10837 | /* STRH (register), STRH (immediate) */ | |
10838 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10839 | &record_buf_mem[0], ARM_RECORD_STRH); | |
10840 | } | |
10841 | else if ((opcode1 & 0x05) == 0x1) | |
10842 | { | |
10843 | /* LDRH (register) */ | |
10844 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10845 | arm_insn_r->reg_rec_count = 1; | |
72508ac0 | 10846 | |
2d9e6acb YQ |
10847 | if (bit (arm_insn_r->arm_insn, 21)) |
10848 | { | |
10849 | /* Write back to Rn. */ | |
10850 | record_buf[arm_insn_r->reg_rec_count++] | |
10851 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10852 | } | |
10853 | } | |
10854 | else if ((opcode1 & 0x05) == 0x5) | |
10855 | { | |
10856 | /* LDRH (immediate), LDRH (literal) */ | |
10857 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 10858 | |
2d9e6acb YQ |
10859 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
10860 | arm_insn_r->reg_rec_count = 1; | |
10861 | ||
10862 | if (rn != 15) | |
10863 | { | |
10864 | /*LDRH (immediate) */ | |
10865 | if (bit (arm_insn_r->arm_insn, 21)) | |
10866 | { | |
10867 | /* Write back to Rn. */ | |
10868 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10869 | } | |
10870 | } | |
10871 | } | |
10872 | else | |
10873 | return -1; | |
10874 | break; | |
10875 | case 2: | |
10876 | if ((opcode1 & 0x05) == 0x0) | |
10877 | { | |
10878 | /* LDRD (register) */ | |
10879 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10880 | record_buf[1] = record_buf[0] + 1; | |
10881 | arm_insn_r->reg_rec_count = 2; | |
10882 | ||
10883 | if (bit (arm_insn_r->arm_insn, 21)) | |
10884 | { | |
10885 | /* Write back to Rn. */ | |
10886 | record_buf[arm_insn_r->reg_rec_count++] | |
10887 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10888 | } | |
10889 | } | |
10890 | else if ((opcode1 & 0x05) == 0x1) | |
10891 | { | |
10892 | /* LDRSB (register) */ | |
10893 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10894 | arm_insn_r->reg_rec_count = 1; | |
10895 | ||
10896 | if (bit (arm_insn_r->arm_insn, 21)) | |
10897 | { | |
10898 | /* Write back to Rn. */ | |
10899 | record_buf[arm_insn_r->reg_rec_count++] | |
10900 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10901 | } | |
10902 | } | |
10903 | else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5) | |
10904 | { | |
10905 | /* LDRD (immediate), LDRD (literal), LDRSB (immediate), | |
10906 | LDRSB (literal) */ | |
10907 | int rn = bits (arm_insn_r->arm_insn, 16, 19); | |
10908 | ||
10909 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10910 | arm_insn_r->reg_rec_count = 1; | |
10911 | ||
10912 | if (rn != 15) | |
10913 | { | |
10914 | /*LDRD (immediate), LDRSB (immediate) */ | |
10915 | if (bit (arm_insn_r->arm_insn, 21)) | |
10916 | { | |
10917 | /* Write back to Rn. */ | |
10918 | record_buf[arm_insn_r->reg_rec_count++] = rn; | |
10919 | } | |
10920 | } | |
10921 | } | |
10922 | else | |
10923 | return -1; | |
10924 | break; | |
10925 | case 3: | |
10926 | if ((opcode1 & 0x05) == 0x0) | |
10927 | { | |
10928 | /* STRD (register) */ | |
10929 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10930 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10931 | } | |
10932 | else if ((opcode1 & 0x05) == 0x1) | |
10933 | { | |
10934 | /* LDRSH (register) */ | |
10935 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10936 | arm_insn_r->reg_rec_count = 1; | |
10937 | ||
10938 | if (bit (arm_insn_r->arm_insn, 21)) | |
10939 | { | |
10940 | /* Write back to Rn. */ | |
10941 | record_buf[arm_insn_r->reg_rec_count++] | |
10942 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10943 | } | |
10944 | } | |
10945 | else if ((opcode1 & 0x05) == 0x4) | |
10946 | { | |
10947 | /* STRD (immediate) */ | |
10948 | arm_record_strx (arm_insn_r, &record_buf[0], | |
10949 | &record_buf_mem[0], ARM_RECORD_STRD); | |
10950 | } | |
10951 | else if ((opcode1 & 0x05) == 0x5) | |
10952 | { | |
10953 | /* LDRSH (immediate), LDRSH (literal) */ | |
10954 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
10955 | arm_insn_r->reg_rec_count = 1; | |
10956 | ||
10957 | if (bit (arm_insn_r->arm_insn, 21)) | |
10958 | { | |
10959 | /* Write back to Rn. */ | |
10960 | record_buf[arm_insn_r->reg_rec_count++] | |
10961 | = bits (arm_insn_r->arm_insn, 16, 19); | |
10962 | } | |
10963 | } | |
10964 | else | |
10965 | return -1; | |
10966 | break; | |
10967 | default: | |
10968 | return -1; | |
10969 | } | |
10970 | } | |
72508ac0 PO |
10971 | } |
10972 | else | |
10973 | { | |
10974 | return -1; | |
10975 | } | |
10976 | ||
10977 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
10978 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
10979 | return 0; | |
10980 | } | |
10981 | ||
10982 | /* Handling opcode 001 insns. */ | |
10983 | ||
10984 | static int | |
10985 | arm_record_data_proc_imm (insn_decode_record *arm_insn_r) | |
10986 | { | |
10987 | uint32_t record_buf[8], record_buf_mem[8]; | |
10988 | ||
10989 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); | |
10990 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
10991 | ||
10992 | if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode) | |
10993 | && 2 == bits (arm_insn_r->arm_insn, 20, 21) | |
10994 | && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1) | |
10995 | ) | |
10996 | { | |
10997 | /* Handle MSR insn. */ | |
10998 | if (9 == arm_insn_r->opcode) | |
dda83cd7 SM |
10999 | { |
11000 | /* CSPR is going to be changed. */ | |
11001 | record_buf[0] = ARM_PS_REGNUM; | |
11002 | arm_insn_r->reg_rec_count = 1; | |
11003 | } | |
72508ac0 | 11004 | else |
dda83cd7 SM |
11005 | { |
11006 | /* SPSR is going to be changed. */ | |
11007 | } | |
72508ac0 PO |
11008 | } |
11009 | else if (arm_insn_r->opcode <= 15) | |
11010 | { | |
11011 | /* Normal data processing insns. */ | |
11012 | /* Out of 11 shifter operands mode, all the insn modifies destination | |
dda83cd7 | 11013 | register, which is specified by 13-16 decode. */ |
72508ac0 PO |
11014 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); |
11015 | record_buf[1] = ARM_PS_REGNUM; | |
11016 | arm_insn_r->reg_rec_count = 2; | |
11017 | } | |
11018 | else | |
11019 | { | |
11020 | return -1; | |
11021 | } | |
11022 | ||
11023 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11024 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11025 | return 0; | |
11026 | } | |
11027 | ||
c55978a6 YQ |
11028 | static int |
11029 | arm_record_media (insn_decode_record *arm_insn_r) | |
11030 | { | |
11031 | uint32_t record_buf[8]; | |
11032 | ||
11033 | switch (bits (arm_insn_r->arm_insn, 22, 24)) | |
11034 | { | |
11035 | case 0: | |
11036 | /* Parallel addition and subtraction, signed */ | |
11037 | case 1: | |
11038 | /* Parallel addition and subtraction, unsigned */ | |
11039 | case 2: | |
11040 | case 3: | |
11041 | /* Packing, unpacking, saturation and reversal */ | |
11042 | { | |
11043 | int rd = bits (arm_insn_r->arm_insn, 12, 15); | |
11044 | ||
11045 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11046 | } | |
11047 | break; | |
11048 | ||
11049 | case 4: | |
11050 | case 5: | |
11051 | /* Signed multiplies */ | |
11052 | { | |
11053 | int rd = bits (arm_insn_r->arm_insn, 16, 19); | |
11054 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); | |
11055 | ||
11056 | record_buf[arm_insn_r->reg_rec_count++] = rd; | |
11057 | if (op1 == 0x0) | |
11058 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11059 | else if (op1 == 0x4) | |
11060 | record_buf[arm_insn_r->reg_rec_count++] | |
11061 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11062 | } | |
11063 | break; | |
11064 | ||
11065 | case 6: | |
11066 | { | |
11067 | if (bit (arm_insn_r->arm_insn, 21) | |
11068 | && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) | |
11069 | { | |
11070 | /* SBFX */ | |
11071 | record_buf[arm_insn_r->reg_rec_count++] | |
11072 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11073 | } | |
11074 | else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 | |
11075 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) | |
11076 | { | |
11077 | /* USAD8 and USADA8 */ | |
11078 | record_buf[arm_insn_r->reg_rec_count++] | |
11079 | = bits (arm_insn_r->arm_insn, 16, 19); | |
11080 | } | |
11081 | } | |
11082 | break; | |
11083 | ||
11084 | case 7: | |
11085 | { | |
11086 | if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 | |
11087 | && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) | |
11088 | { | |
11089 | /* Permanently UNDEFINED */ | |
11090 | return -1; | |
11091 | } | |
11092 | else | |
11093 | { | |
11094 | /* BFC, BFI and UBFX */ | |
11095 | record_buf[arm_insn_r->reg_rec_count++] | |
11096 | = bits (arm_insn_r->arm_insn, 12, 15); | |
11097 | } | |
11098 | } | |
11099 | break; | |
11100 | ||
11101 | default: | |
11102 | return -1; | |
11103 | } | |
11104 | ||
11105 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11106 | ||
11107 | return 0; | |
11108 | } | |
11109 | ||
71e396f9 | 11110 | /* Handle ARM mode instructions with opcode 010. */ |
72508ac0 PO |
11111 | |
11112 | static int | |
11113 | arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) | |
11114 | { | |
11115 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11116 | ||
71e396f9 LM |
11117 | uint32_t reg_base , reg_dest; |
11118 | uint32_t offset_12, tgt_mem_addr; | |
72508ac0 | 11119 | uint32_t record_buf[8], record_buf_mem[8]; |
71e396f9 LM |
11120 | unsigned char wback; |
11121 | ULONGEST u_regval; | |
72508ac0 | 11122 | |
71e396f9 LM |
11123 | /* Calculate wback. */ |
11124 | wback = (bit (arm_insn_r->arm_insn, 24) == 0) | |
11125 | || (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 | 11126 | |
71e396f9 LM |
11127 | arm_insn_r->reg_rec_count = 0; |
11128 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 PO |
11129 | |
11130 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11131 | { | |
71e396f9 LM |
11132 | /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT |
11133 | and LDRT. */ | |
11134 | ||
72508ac0 | 11135 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); |
71e396f9 LM |
11136 | record_buf[arm_insn_r->reg_rec_count++] = reg_dest; |
11137 | ||
11138 | /* The LDR instruction is capable of doing branching. If MOV LR, PC | |
11139 | preceeds a LDR instruction having R15 as reg_base, it | |
11140 | emulates a branch and link instruction, and hence we need to save | |
11141 | CPSR and PC as well. */ | |
11142 | if (ARM_PC_REGNUM == reg_dest) | |
11143 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
11144 | ||
11145 | /* If wback is true, also save the base register, which is going to be | |
11146 | written to. */ | |
11147 | if (wback) | |
11148 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11149 | } |
11150 | else | |
11151 | { | |
71e396f9 LM |
11152 | /* STR (immediate), STRB (immediate), STRBT and STRT. */ |
11153 | ||
72508ac0 | 11154 | offset_12 = bits (arm_insn_r->arm_insn, 0, 11); |
71e396f9 LM |
11155 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); |
11156 | ||
11157 | /* Handle bit U. */ | |
72508ac0 | 11158 | if (bit (arm_insn_r->arm_insn, 23)) |
71e396f9 LM |
11159 | { |
11160 | /* U == 1: Add the offset. */ | |
11161 | tgt_mem_addr = (uint32_t) u_regval + offset_12; | |
11162 | } | |
72508ac0 | 11163 | else |
71e396f9 LM |
11164 | { |
11165 | /* U == 0: subtract the offset. */ | |
11166 | tgt_mem_addr = (uint32_t) u_regval - offset_12; | |
11167 | } | |
11168 | ||
11169 | /* Bit 22 tells us whether the store instruction writes 1 byte or 4 | |
11170 | bytes. */ | |
11171 | if (bit (arm_insn_r->arm_insn, 22)) | |
11172 | { | |
11173 | /* STRB and STRBT: 1 byte. */ | |
11174 | record_buf_mem[0] = 1; | |
11175 | } | |
11176 | else | |
11177 | { | |
11178 | /* STR and STRT: 4 bytes. */ | |
11179 | record_buf_mem[0] = 4; | |
11180 | } | |
11181 | ||
11182 | /* Handle bit P. */ | |
11183 | if (bit (arm_insn_r->arm_insn, 24)) | |
11184 | record_buf_mem[1] = tgt_mem_addr; | |
11185 | else | |
11186 | record_buf_mem[1] = (uint32_t) u_regval; | |
72508ac0 | 11187 | |
72508ac0 PO |
11188 | arm_insn_r->mem_rec_count = 1; |
11189 | ||
71e396f9 LM |
11190 | /* If wback is true, also save the base register, which is going to be |
11191 | written to. */ | |
11192 | if (wback) | |
11193 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11194 | } |
11195 | ||
11196 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11197 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11198 | return 0; | |
11199 | } | |
11200 | ||
11201 | /* Handling opcode 011 insns. */ | |
11202 | ||
11203 | static int | |
11204 | arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) | |
11205 | { | |
11206 | struct regcache *reg_cache = arm_insn_r->regcache; | |
11207 | ||
11208 | uint32_t shift_imm = 0; | |
11209 | uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; | |
11210 | uint32_t offset_12 = 0, tgt_mem_addr = 0; | |
11211 | uint32_t record_buf[8], record_buf_mem[8]; | |
11212 | ||
11213 | LONGEST s_word; | |
11214 | ULONGEST u_regval[2]; | |
11215 | ||
c55978a6 YQ |
11216 | if (bit (arm_insn_r->arm_insn, 4)) |
11217 | return arm_record_media (arm_insn_r); | |
11218 | ||
72508ac0 PO |
11219 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); |
11220 | arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); | |
11221 | ||
11222 | /* Handle enhanced store insns and LDRD DSP insn, | |
11223 | order begins according to addressing modes for store insns | |
11224 | STRH insn. */ | |
11225 | ||
11226 | /* LDR or STR? */ | |
11227 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11228 | { | |
11229 | reg_dest = bits (arm_insn_r->arm_insn, 12, 15); | |
11230 | /* LDR insn has a capability to do branching, if | |
dda83cd7 SM |
11231 | MOV LR, PC is preceded by LDR insn having Rn as R15 |
11232 | in that case, it emulates branch and link insn, and hence we | |
11233 | need to save CSPR and PC as well. */ | |
72508ac0 | 11234 | if (15 != reg_dest) |
dda83cd7 SM |
11235 | { |
11236 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11237 | arm_insn_r->reg_rec_count = 1; | |
11238 | } | |
72508ac0 | 11239 | else |
dda83cd7 SM |
11240 | { |
11241 | record_buf[0] = reg_dest; | |
11242 | record_buf[1] = ARM_PS_REGNUM; | |
11243 | arm_insn_r->reg_rec_count = 2; | |
11244 | } | |
72508ac0 PO |
11245 | } |
11246 | else | |
11247 | { | |
11248 | if (! bits (arm_insn_r->arm_insn, 4, 11)) | |
dda83cd7 SM |
11249 | { |
11250 | /* Store insn, register offset and register pre-indexed, | |
11251 | register post-indexed. */ | |
11252 | /* Get Rm. */ | |
11253 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11254 | /* Get Rn. */ | |
11255 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11256 | regcache_raw_read_unsigned (reg_cache, reg_src1 | |
11257 | , &u_regval[0]); | |
11258 | regcache_raw_read_unsigned (reg_cache, reg_src2 | |
11259 | , &u_regval[1]); | |
11260 | if (15 == reg_src2) | |
11261 | { | |
11262 | /* If R15 was used as Rn, hence current PC+8. */ | |
11263 | /* Pre-indexed mode doesnt reach here ; illegal insn. */ | |
11264 | u_regval[0] = u_regval[0] + 8; | |
11265 | } | |
11266 | /* Calculate target store address, Rn +/- Rm, register offset. */ | |
11267 | /* U == 1. */ | |
11268 | if (bit (arm_insn_r->arm_insn, 23)) | |
11269 | { | |
11270 | tgt_mem_addr = u_regval[0] + u_regval[1]; | |
11271 | } | |
11272 | else | |
11273 | { | |
11274 | tgt_mem_addr = u_regval[1] - u_regval[0]; | |
11275 | } | |
11276 | ||
11277 | switch (arm_insn_r->opcode) | |
11278 | { | |
11279 | /* STR. */ | |
11280 | case 8: | |
11281 | case 12: | |
11282 | /* STR. */ | |
11283 | case 9: | |
11284 | case 13: | |
11285 | /* STRT. */ | |
11286 | case 1: | |
11287 | case 5: | |
11288 | /* STR. */ | |
11289 | case 0: | |
11290 | case 4: | |
11291 | record_buf_mem[0] = 4; | |
11292 | break; | |
11293 | ||
11294 | /* STRB. */ | |
11295 | case 10: | |
11296 | case 14: | |
11297 | /* STRB. */ | |
11298 | case 11: | |
11299 | case 15: | |
11300 | /* STRBT. */ | |
11301 | case 3: | |
11302 | case 7: | |
11303 | /* STRB. */ | |
11304 | case 2: | |
11305 | case 6: | |
11306 | record_buf_mem[0] = 1; | |
11307 | break; | |
11308 | ||
11309 | default: | |
11310 | gdb_assert_not_reached ("no decoding pattern found"); | |
11311 | break; | |
11312 | } | |
11313 | record_buf_mem[1] = tgt_mem_addr; | |
11314 | arm_insn_r->mem_rec_count = 1; | |
11315 | ||
11316 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
11317 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
11318 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
11319 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
11320 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
11321 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
11322 | ) | |
11323 | { | |
11324 | /* Rn is going to be changed in pre-indexed mode and | |
11325 | post-indexed mode as well. */ | |
11326 | record_buf[0] = reg_src2; | |
11327 | arm_insn_r->reg_rec_count = 1; | |
11328 | } | |
11329 | } | |
72508ac0 | 11330 | else |
dda83cd7 SM |
11331 | { |
11332 | /* Store insn, scaled register offset; scaled pre-indexed. */ | |
11333 | offset_12 = bits (arm_insn_r->arm_insn, 5, 6); | |
11334 | /* Get Rm. */ | |
11335 | reg_src1 = bits (arm_insn_r->arm_insn, 0, 3); | |
11336 | /* Get Rn. */ | |
11337 | reg_src2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11338 | /* Get shift_imm. */ | |
11339 | shift_imm = bits (arm_insn_r->arm_insn, 7, 11); | |
11340 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
11341 | regcache_raw_read_signed (reg_cache, reg_src1, &s_word); | |
11342 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11343 | /* Offset_12 used as shift. */ | |
11344 | switch (offset_12) | |
11345 | { | |
11346 | case 0: | |
11347 | /* Offset_12 used as index. */ | |
11348 | offset_12 = u_regval[0] << shift_imm; | |
11349 | break; | |
11350 | ||
11351 | case 1: | |
11352 | offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm; | |
11353 | break; | |
11354 | ||
11355 | case 2: | |
11356 | if (!shift_imm) | |
11357 | { | |
11358 | if (bit (u_regval[0], 31)) | |
11359 | { | |
11360 | offset_12 = 0xFFFFFFFF; | |
11361 | } | |
11362 | else | |
11363 | { | |
11364 | offset_12 = 0; | |
11365 | } | |
11366 | } | |
11367 | else | |
11368 | { | |
11369 | /* This is arithmetic shift. */ | |
11370 | offset_12 = s_word >> shift_imm; | |
11371 | } | |
11372 | break; | |
11373 | ||
11374 | case 3: | |
11375 | if (!shift_imm) | |
11376 | { | |
11377 | regcache_raw_read_unsigned (reg_cache, ARM_PS_REGNUM, | |
11378 | &u_regval[1]); | |
11379 | /* Get C flag value and shift it by 31. */ | |
11380 | offset_12 = (((bit (u_regval[1], 29)) << 31) \ | |
11381 | | (u_regval[0]) >> 1); | |
11382 | } | |
11383 | else | |
11384 | { | |
11385 | offset_12 = (u_regval[0] >> shift_imm) \ | |
11386 | | (u_regval[0] << | |
11387 | (sizeof(uint32_t) - shift_imm)); | |
11388 | } | |
11389 | break; | |
11390 | ||
11391 | default: | |
11392 | gdb_assert_not_reached ("no decoding pattern found"); | |
11393 | break; | |
11394 | } | |
11395 | ||
11396 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
11397 | /* bit U set. */ | |
11398 | if (bit (arm_insn_r->arm_insn, 23)) | |
11399 | { | |
11400 | tgt_mem_addr = u_regval[1] + offset_12; | |
11401 | } | |
11402 | else | |
11403 | { | |
11404 | tgt_mem_addr = u_regval[1] - offset_12; | |
11405 | } | |
11406 | ||
11407 | switch (arm_insn_r->opcode) | |
11408 | { | |
11409 | /* STR. */ | |
11410 | case 8: | |
11411 | case 12: | |
11412 | /* STR. */ | |
11413 | case 9: | |
11414 | case 13: | |
11415 | /* STRT. */ | |
11416 | case 1: | |
11417 | case 5: | |
11418 | /* STR. */ | |
11419 | case 0: | |
11420 | case 4: | |
11421 | record_buf_mem[0] = 4; | |
11422 | break; | |
11423 | ||
11424 | /* STRB. */ | |
11425 | case 10: | |
11426 | case 14: | |
11427 | /* STRB. */ | |
11428 | case 11: | |
11429 | case 15: | |
11430 | /* STRBT. */ | |
11431 | case 3: | |
11432 | case 7: | |
11433 | /* STRB. */ | |
11434 | case 2: | |
11435 | case 6: | |
11436 | record_buf_mem[0] = 1; | |
11437 | break; | |
11438 | ||
11439 | default: | |
11440 | gdb_assert_not_reached ("no decoding pattern found"); | |
11441 | break; | |
11442 | } | |
11443 | record_buf_mem[1] = tgt_mem_addr; | |
11444 | arm_insn_r->mem_rec_count = 1; | |
11445 | ||
11446 | if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode | |
11447 | || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode | |
11448 | || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode | |
11449 | || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode | |
11450 | || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode | |
11451 | || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode | |
11452 | ) | |
11453 | { | |
11454 | /* Rn is going to be changed in register scaled pre-indexed | |
11455 | mode,and scaled post indexed mode. */ | |
11456 | record_buf[0] = reg_src2; | |
11457 | arm_insn_r->reg_rec_count = 1; | |
11458 | } | |
11459 | } | |
72508ac0 PO |
11460 | } |
11461 | ||
11462 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11463 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11464 | return 0; | |
11465 | } | |
11466 | ||
71e396f9 | 11467 | /* Handle ARM mode instructions with opcode 100. */ |
72508ac0 PO |
11468 | |
11469 | static int | |
11470 | arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) | |
11471 | { | |
11472 | struct regcache *reg_cache = arm_insn_r->regcache; | |
71e396f9 LM |
11473 | uint32_t register_count = 0, register_bits; |
11474 | uint32_t reg_base, addr_mode; | |
72508ac0 | 11475 | uint32_t record_buf[24], record_buf_mem[48]; |
71e396f9 LM |
11476 | uint32_t wback; |
11477 | ULONGEST u_regval; | |
72508ac0 | 11478 | |
71e396f9 LM |
11479 | /* Fetch the list of registers. */ |
11480 | register_bits = bits (arm_insn_r->arm_insn, 0, 15); | |
11481 | arm_insn_r->reg_rec_count = 0; | |
11482 | ||
11483 | /* Fetch the base register that contains the address we are loading data | |
11484 | to. */ | |
11485 | reg_base = bits (arm_insn_r->arm_insn, 16, 19); | |
72508ac0 | 11486 | |
71e396f9 LM |
11487 | /* Calculate wback. */ |
11488 | wback = (bit (arm_insn_r->arm_insn, 21) == 1); | |
72508ac0 PO |
11489 | |
11490 | if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
11491 | { | |
71e396f9 | 11492 | /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ |
72508ac0 | 11493 | |
71e396f9 | 11494 | /* Find out which registers are going to be loaded from memory. */ |
72508ac0 | 11495 | while (register_bits) |
71e396f9 LM |
11496 | { |
11497 | if (register_bits & 0x00000001) | |
11498 | record_buf[arm_insn_r->reg_rec_count++] = register_count; | |
11499 | register_bits = register_bits >> 1; | |
11500 | register_count++; | |
11501 | } | |
72508ac0 | 11502 | |
71e396f9 LM |
11503 | |
11504 | /* If wback is true, also save the base register, which is going to be | |
11505 | written to. */ | |
11506 | if (wback) | |
11507 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
11508 | ||
11509 | /* Save the CPSR register. */ | |
11510 | record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; | |
72508ac0 PO |
11511 | } |
11512 | else | |
11513 | { | |
71e396f9 | 11514 | /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ |
72508ac0 | 11515 | |
71e396f9 LM |
11516 | addr_mode = bits (arm_insn_r->arm_insn, 23, 24); |
11517 | ||
11518 | regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); | |
11519 | ||
11520 | /* Find out how many registers are going to be stored to memory. */ | |
72508ac0 | 11521 | while (register_bits) |
71e396f9 LM |
11522 | { |
11523 | if (register_bits & 0x00000001) | |
11524 | register_count++; | |
11525 | register_bits = register_bits >> 1; | |
11526 | } | |
72508ac0 PO |
11527 | |
11528 | switch (addr_mode) | |
71e396f9 LM |
11529 | { |
11530 | /* STMDA (STMED): Decrement after. */ | |
11531 | case 0: | |
11532 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11533 | - register_count * ARM_INT_REGISTER_SIZE + 4; |
71e396f9 LM |
11534 | break; |
11535 | /* STM (STMIA, STMEA): Increment after. */ | |
11536 | case 1: | |
11537 | record_buf_mem[1] = (uint32_t) u_regval; | |
11538 | break; | |
11539 | /* STMDB (STMFD): Decrement before. */ | |
11540 | case 2: | |
11541 | record_buf_mem[1] = (uint32_t) u_regval | |
f0452268 | 11542 | - register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11543 | break; |
11544 | /* STMIB (STMFA): Increment before. */ | |
11545 | case 3: | |
f0452268 | 11546 | record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11547 | break; |
11548 | default: | |
11549 | gdb_assert_not_reached ("no decoding pattern found"); | |
11550 | break; | |
11551 | } | |
72508ac0 | 11552 | |
f0452268 | 11553 | record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE; |
71e396f9 LM |
11554 | arm_insn_r->mem_rec_count = 1; |
11555 | ||
11556 | /* If wback is true, also save the base register, which is going to be | |
11557 | written to. */ | |
11558 | if (wback) | |
11559 | record_buf[arm_insn_r->reg_rec_count++] = reg_base; | |
72508ac0 PO |
11560 | } |
11561 | ||
11562 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11563 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11564 | return 0; | |
11565 | } | |
11566 | ||
11567 | /* Handling opcode 101 insns. */ | |
11568 | ||
11569 | static int | |
11570 | arm_record_b_bl (insn_decode_record *arm_insn_r) | |
11571 | { | |
11572 | uint32_t record_buf[8]; | |
11573 | ||
11574 | /* Handle B, BL, BLX(1) insns. */ | |
11575 | /* B simply branches so we do nothing here. */ | |
11576 | /* Note: BLX(1) doesnt fall here but instead it falls into | |
11577 | extension space. */ | |
11578 | if (bit (arm_insn_r->arm_insn, 24)) | |
01add95b SM |
11579 | { |
11580 | record_buf[0] = ARM_LR_REGNUM; | |
11581 | arm_insn_r->reg_rec_count = 1; | |
11582 | } | |
72508ac0 PO |
11583 | |
11584 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11585 | ||
11586 | return 0; | |
11587 | } | |
11588 | ||
72508ac0 | 11589 | static int |
c6ec2b30 | 11590 | arm_record_unsupported_insn (insn_decode_record *arm_insn_r) |
72508ac0 | 11591 | { |
6cb06a8c TT |
11592 | gdb_printf (gdb_stderr, |
11593 | _("Process record does not support instruction " | |
11594 | "0x%0x at address %s.\n"),arm_insn_r->arm_insn, | |
11595 | paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); | |
72508ac0 PO |
11596 | |
11597 | return -1; | |
11598 | } | |
11599 | ||
5a578da5 OJ |
11600 | /* Record handler for vector data transfer instructions. */ |
11601 | ||
11602 | static int | |
11603 | arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) | |
11604 | { | |
11605 | uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; | |
11606 | uint32_t record_buf[4]; | |
11607 | ||
5a578da5 OJ |
11608 | reg_t = bits (arm_insn_r->arm_insn, 12, 15); |
11609 | reg_v = bits (arm_insn_r->arm_insn, 21, 23); | |
11610 | bits_a = bits (arm_insn_r->arm_insn, 21, 23); | |
11611 | bit_l = bit (arm_insn_r->arm_insn, 20); | |
11612 | bit_c = bit (arm_insn_r->arm_insn, 8); | |
11613 | ||
11614 | /* Handle VMOV instruction. */ | |
11615 | if (bit_l && bit_c) | |
11616 | { | |
11617 | record_buf[0] = reg_t; | |
11618 | arm_insn_r->reg_rec_count = 1; | |
11619 | } | |
11620 | else if (bit_l && !bit_c) | |
11621 | { | |
11622 | /* Handle VMOV instruction. */ | |
11623 | if (bits_a == 0x00) | |
dda83cd7 | 11624 | { |
f1771dce | 11625 | record_buf[0] = reg_t; |
dda83cd7 SM |
11626 | arm_insn_r->reg_rec_count = 1; |
11627 | } | |
5a578da5 OJ |
11628 | /* Handle VMRS instruction. */ |
11629 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11630 | { |
11631 | if (reg_t == 15) | |
11632 | reg_t = ARM_PS_REGNUM; | |
5a578da5 | 11633 | |
dda83cd7 SM |
11634 | record_buf[0] = reg_t; |
11635 | arm_insn_r->reg_rec_count = 1; | |
11636 | } | |
5a578da5 OJ |
11637 | } |
11638 | else if (!bit_l && !bit_c) | |
11639 | { | |
11640 | /* Handle VMOV instruction. */ | |
11641 | if (bits_a == 0x00) | |
dda83cd7 | 11642 | { |
f1771dce | 11643 | record_buf[0] = ARM_D0_REGNUM + reg_v; |
5a578da5 | 11644 | |
dda83cd7 SM |
11645 | arm_insn_r->reg_rec_count = 1; |
11646 | } | |
5a578da5 OJ |
11647 | /* Handle VMSR instruction. */ |
11648 | else if (bits_a == 0x07) | |
dda83cd7 SM |
11649 | { |
11650 | record_buf[0] = ARM_FPSCR_REGNUM; | |
11651 | arm_insn_r->reg_rec_count = 1; | |
11652 | } | |
5a578da5 OJ |
11653 | } |
11654 | else if (!bit_l && bit_c) | |
11655 | { | |
11656 | /* Handle VMOV instruction. */ | |
11657 | if (!(bits_a & 0x04)) | |
dda83cd7 SM |
11658 | { |
11659 | record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) | |
11660 | + ARM_D0_REGNUM; | |
11661 | arm_insn_r->reg_rec_count = 1; | |
11662 | } | |
5a578da5 OJ |
11663 | /* Handle VDUP instruction. */ |
11664 | else | |
dda83cd7 SM |
11665 | { |
11666 | if (bit (arm_insn_r->arm_insn, 21)) | |
11667 | { | |
11668 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11669 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11670 | record_buf[1] = reg_v + ARM_D0_REGNUM + 1; | |
11671 | arm_insn_r->reg_rec_count = 2; | |
11672 | } | |
11673 | else | |
11674 | { | |
11675 | reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); | |
11676 | record_buf[0] = reg_v + ARM_D0_REGNUM; | |
11677 | arm_insn_r->reg_rec_count = 1; | |
11678 | } | |
11679 | } | |
11680 | } | |
11681 | ||
11682 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11683 | return 0; | |
11684 | } | |
11685 | ||
f20f80dd OJ |
11686 | /* Record handler for extension register load/store instructions. */ |
11687 | ||
11688 | static int | |
11689 | arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) | |
11690 | { | |
11691 | uint32_t opcode, single_reg; | |
11692 | uint8_t op_vldm_vstm; | |
11693 | uint32_t record_buf[8], record_buf_mem[128]; | |
11694 | ULONGEST u_regval = 0; | |
11695 | ||
11696 | struct regcache *reg_cache = arm_insn_r->regcache; | |
f20f80dd OJ |
11697 | |
11698 | opcode = bits (arm_insn_r->arm_insn, 20, 24); | |
9fde51ed | 11699 | single_reg = !bit (arm_insn_r->arm_insn, 8); |
f20f80dd OJ |
11700 | op_vldm_vstm = opcode & 0x1b; |
11701 | ||
11702 | /* Handle VMOV instructions. */ | |
11703 | if ((opcode & 0x1e) == 0x04) | |
11704 | { | |
9fde51ed | 11705 | if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ |
01e57735 YQ |
11706 | { |
11707 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
11708 | record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
11709 | arm_insn_r->reg_rec_count = 2; | |
11710 | } | |
f20f80dd | 11711 | else |
01e57735 | 11712 | { |
9fde51ed YQ |
11713 | uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); |
11714 | uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); | |
f20f80dd | 11715 | |
9fde51ed | 11716 | if (single_reg) |
01e57735 | 11717 | { |
9fde51ed YQ |
11718 | /* The first S register number m is REG_M:M (M is bit 5), |
11719 | the corresponding D register number is REG_M:M / 2, which | |
11720 | is REG_M. */ | |
11721 | record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; | |
11722 | /* The second S register number is REG_M:M + 1, the | |
11723 | corresponding D register number is (REG_M:M + 1) / 2. | |
11724 | IOW, if bit M is 1, the first and second S registers | |
11725 | are mapped to different D registers, otherwise, they are | |
11726 | in the same D register. */ | |
11727 | if (bit_m) | |
11728 | { | |
11729 | record_buf[arm_insn_r->reg_rec_count++] | |
11730 | = ARM_D0_REGNUM + reg_m + 1; | |
11731 | } | |
01e57735 YQ |
11732 | } |
11733 | else | |
11734 | { | |
9fde51ed | 11735 | record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); |
01e57735 YQ |
11736 | arm_insn_r->reg_rec_count = 1; |
11737 | } | |
11738 | } | |
f20f80dd OJ |
11739 | } |
11740 | /* Handle VSTM and VPUSH instructions. */ | |
11741 | else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a | |
01e57735 | 11742 | || op_vldm_vstm == 0x12) |
f20f80dd OJ |
11743 | { |
11744 | uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; | |
11745 | uint32_t memory_index = 0; | |
11746 | ||
11747 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11748 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11749 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11750 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11751 | memory_count = imm_off8; |
11752 | ||
11753 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11754 | start_address = u_regval; |
f20f80dd | 11755 | else |
01e57735 | 11756 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11757 | |
11758 | if (bit (arm_insn_r->arm_insn, 21)) | |
01e57735 YQ |
11759 | { |
11760 | record_buf[0] = reg_rn; | |
11761 | arm_insn_r->reg_rec_count = 1; | |
11762 | } | |
f20f80dd OJ |
11763 | |
11764 | while (memory_count > 0) | |
01e57735 | 11765 | { |
9fde51ed | 11766 | if (single_reg) |
01e57735 | 11767 | { |
9fde51ed YQ |
11768 | record_buf_mem[memory_index] = 4; |
11769 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11770 | start_address = start_address + 4; |
11771 | memory_index = memory_index + 2; | |
11772 | } | |
11773 | else | |
11774 | { | |
9fde51ed YQ |
11775 | record_buf_mem[memory_index] = 4; |
11776 | record_buf_mem[memory_index + 1] = start_address; | |
11777 | record_buf_mem[memory_index + 2] = 4; | |
11778 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11779 | start_address = start_address + 8; |
11780 | memory_index = memory_index + 4; | |
11781 | } | |
11782 | memory_count--; | |
11783 | } | |
f20f80dd OJ |
11784 | arm_insn_r->mem_rec_count = (memory_index >> 1); |
11785 | } | |
11786 | /* Handle VLDM instructions. */ | |
11787 | else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b | |
01e57735 | 11788 | || op_vldm_vstm == 0x13) |
f20f80dd OJ |
11789 | { |
11790 | uint32_t reg_count, reg_vd; | |
11791 | uint32_t reg_index = 0; | |
9fde51ed | 11792 | uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); |
f20f80dd OJ |
11793 | |
11794 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11795 | reg_count = bits (arm_insn_r->arm_insn, 0, 7); | |
11796 | ||
9fde51ed YQ |
11797 | /* REG_VD is the first D register number. If the instruction |
11798 | loads memory to S registers (SINGLE_REG is TRUE), the register | |
11799 | number is (REG_VD << 1 | bit D), so the corresponding D | |
11800 | register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ | |
11801 | if (!single_reg) | |
11802 | reg_vd = reg_vd | (bit_d << 4); | |
f20f80dd | 11803 | |
9fde51ed | 11804 | if (bit (arm_insn_r->arm_insn, 21) /* write back */) |
01e57735 | 11805 | record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); |
f20f80dd | 11806 | |
9fde51ed YQ |
11807 | /* If the instruction loads memory to D register, REG_COUNT should |
11808 | be divided by 2, according to the ARM Architecture Reference | |
11809 | Manual. If the instruction loads memory to S register, divide by | |
11810 | 2 as well because two S registers are mapped to D register. */ | |
11811 | reg_count = reg_count / 2; | |
11812 | if (single_reg && bit_d) | |
01e57735 | 11813 | { |
9fde51ed YQ |
11814 | /* Increase the register count if S register list starts from |
11815 | an odd number (bit d is one). */ | |
11816 | reg_count++; | |
11817 | } | |
f20f80dd | 11818 | |
9fde51ed YQ |
11819 | while (reg_count > 0) |
11820 | { | |
11821 | record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; | |
01e57735 YQ |
11822 | reg_count--; |
11823 | } | |
f20f80dd OJ |
11824 | arm_insn_r->reg_rec_count = reg_index; |
11825 | } | |
11826 | /* VSTR Vector store register. */ | |
11827 | else if ((opcode & 0x13) == 0x10) | |
11828 | { | |
bec2ab5a | 11829 | uint32_t start_address, reg_rn, imm_off32, imm_off8; |
f20f80dd OJ |
11830 | uint32_t memory_index = 0; |
11831 | ||
11832 | reg_rn = bits (arm_insn_r->arm_insn, 16, 19); | |
11833 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
11834 | imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); | |
9fde51ed | 11835 | imm_off32 = imm_off8 << 2; |
f20f80dd OJ |
11836 | |
11837 | if (bit (arm_insn_r->arm_insn, 23)) | |
01e57735 | 11838 | start_address = u_regval + imm_off32; |
f20f80dd | 11839 | else |
01e57735 | 11840 | start_address = u_regval - imm_off32; |
f20f80dd OJ |
11841 | |
11842 | if (single_reg) | |
01e57735 | 11843 | { |
9fde51ed YQ |
11844 | record_buf_mem[memory_index] = 4; |
11845 | record_buf_mem[memory_index + 1] = start_address; | |
01e57735 YQ |
11846 | arm_insn_r->mem_rec_count = 1; |
11847 | } | |
f20f80dd | 11848 | else |
01e57735 | 11849 | { |
9fde51ed YQ |
11850 | record_buf_mem[memory_index] = 4; |
11851 | record_buf_mem[memory_index + 1] = start_address; | |
11852 | record_buf_mem[memory_index + 2] = 4; | |
11853 | record_buf_mem[memory_index + 3] = start_address + 4; | |
01e57735 YQ |
11854 | arm_insn_r->mem_rec_count = 2; |
11855 | } | |
f20f80dd OJ |
11856 | } |
11857 | /* VLDR Vector load register. */ | |
11858 | else if ((opcode & 0x13) == 0x11) | |
11859 | { | |
11860 | uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11861 | ||
11862 | if (!single_reg) | |
01e57735 YQ |
11863 | { |
11864 | reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); | |
11865 | record_buf[0] = ARM_D0_REGNUM + reg_vd; | |
11866 | } | |
f20f80dd | 11867 | else |
01e57735 YQ |
11868 | { |
11869 | reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); | |
9fde51ed YQ |
11870 | /* Record register D rather than pseudo register S. */ |
11871 | record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; | |
01e57735 | 11872 | } |
f20f80dd OJ |
11873 | arm_insn_r->reg_rec_count = 1; |
11874 | } | |
11875 | ||
11876 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
11877 | MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); | |
11878 | return 0; | |
11879 | } | |
11880 | ||
851f26ae OJ |
11881 | /* Record handler for arm/thumb mode VFP data processing instructions. */ |
11882 | ||
11883 | static int | |
11884 | arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) | |
11885 | { | |
11886 | uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; | |
11887 | uint32_t record_buf[4]; | |
11888 | enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; | |
11889 | enum insn_types curr_insn_type = INSN_INV; | |
11890 | ||
11891 | reg_vd = bits (arm_insn_r->arm_insn, 12, 15); | |
11892 | opc1 = bits (arm_insn_r->arm_insn, 20, 23); | |
11893 | opc2 = bits (arm_insn_r->arm_insn, 16, 19); | |
11894 | opc3 = bits (arm_insn_r->arm_insn, 6, 7); | |
11895 | dp_op_sz = bit (arm_insn_r->arm_insn, 8); | |
11896 | bit_d = bit (arm_insn_r->arm_insn, 22); | |
ce887586 TT |
11897 | /* Mask off the "D" bit. */ |
11898 | opc1 = opc1 & ~0x04; | |
851f26ae OJ |
11899 | |
11900 | /* Handle VMLA, VMLS. */ | |
11901 | if (opc1 == 0x00) | |
11902 | { | |
11903 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11904 | { |
11905 | if (bit (arm_insn_r->arm_insn, 6)) | |
11906 | curr_insn_type = INSN_T0; | |
11907 | else | |
11908 | curr_insn_type = INSN_T1; | |
11909 | } | |
851f26ae | 11910 | else |
dda83cd7 SM |
11911 | { |
11912 | if (dp_op_sz) | |
11913 | curr_insn_type = INSN_T1; | |
11914 | else | |
11915 | curr_insn_type = INSN_T2; | |
11916 | } | |
851f26ae OJ |
11917 | } |
11918 | /* Handle VNMLA, VNMLS, VNMUL. */ | |
11919 | else if (opc1 == 0x01) | |
11920 | { | |
11921 | if (dp_op_sz) | |
dda83cd7 | 11922 | curr_insn_type = INSN_T1; |
851f26ae | 11923 | else |
dda83cd7 | 11924 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11925 | } |
11926 | /* Handle VMUL. */ | |
11927 | else if (opc1 == 0x02 && !(opc3 & 0x01)) | |
11928 | { | |
11929 | if (bit (arm_insn_r->arm_insn, 10)) | |
dda83cd7 SM |
11930 | { |
11931 | if (bit (arm_insn_r->arm_insn, 6)) | |
11932 | curr_insn_type = INSN_T0; | |
11933 | else | |
11934 | curr_insn_type = INSN_T1; | |
11935 | } | |
851f26ae | 11936 | else |
dda83cd7 SM |
11937 | { |
11938 | if (dp_op_sz) | |
11939 | curr_insn_type = INSN_T1; | |
11940 | else | |
11941 | curr_insn_type = INSN_T2; | |
11942 | } | |
851f26ae OJ |
11943 | } |
11944 | /* Handle VADD, VSUB. */ | |
11945 | else if (opc1 == 0x03) | |
11946 | { | |
11947 | if (!bit (arm_insn_r->arm_insn, 9)) | |
dda83cd7 SM |
11948 | { |
11949 | if (bit (arm_insn_r->arm_insn, 6)) | |
11950 | curr_insn_type = INSN_T0; | |
11951 | else | |
11952 | curr_insn_type = INSN_T1; | |
11953 | } | |
851f26ae | 11954 | else |
dda83cd7 SM |
11955 | { |
11956 | if (dp_op_sz) | |
11957 | curr_insn_type = INSN_T1; | |
11958 | else | |
11959 | curr_insn_type = INSN_T2; | |
11960 | } | |
851f26ae OJ |
11961 | } |
11962 | /* Handle VDIV. */ | |
ce887586 | 11963 | else if (opc1 == 0x08) |
851f26ae OJ |
11964 | { |
11965 | if (dp_op_sz) | |
dda83cd7 | 11966 | curr_insn_type = INSN_T1; |
851f26ae | 11967 | else |
dda83cd7 | 11968 | curr_insn_type = INSN_T2; |
851f26ae OJ |
11969 | } |
11970 | /* Handle all other vfp data processing instructions. */ | |
11971 | else if (opc1 == 0x0b) | |
11972 | { | |
11973 | /* Handle VMOV. */ | |
11974 | if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) | |
dda83cd7 SM |
11975 | { |
11976 | if (bit (arm_insn_r->arm_insn, 4)) | |
11977 | { | |
11978 | if (bit (arm_insn_r->arm_insn, 6)) | |
11979 | curr_insn_type = INSN_T0; | |
11980 | else | |
11981 | curr_insn_type = INSN_T1; | |
11982 | } | |
11983 | else | |
11984 | { | |
11985 | if (dp_op_sz) | |
11986 | curr_insn_type = INSN_T1; | |
11987 | else | |
11988 | curr_insn_type = INSN_T2; | |
11989 | } | |
11990 | } | |
851f26ae OJ |
11991 | /* Handle VNEG and VABS. */ |
11992 | else if ((opc2 == 0x01 && opc3 == 0x01) | |
dda83cd7 SM |
11993 | || (opc2 == 0x00 && opc3 == 0x03)) |
11994 | { | |
11995 | if (!bit (arm_insn_r->arm_insn, 11)) | |
11996 | { | |
11997 | if (bit (arm_insn_r->arm_insn, 6)) | |
11998 | curr_insn_type = INSN_T0; | |
11999 | else | |
12000 | curr_insn_type = INSN_T1; | |
12001 | } | |
12002 | else | |
12003 | { | |
12004 | if (dp_op_sz) | |
12005 | curr_insn_type = INSN_T1; | |
12006 | else | |
12007 | curr_insn_type = INSN_T2; | |
12008 | } | |
12009 | } | |
851f26ae OJ |
12010 | /* Handle VSQRT. */ |
12011 | else if (opc2 == 0x01 && opc3 == 0x03) | |
dda83cd7 SM |
12012 | { |
12013 | if (dp_op_sz) | |
12014 | curr_insn_type = INSN_T1; | |
12015 | else | |
12016 | curr_insn_type = INSN_T2; | |
12017 | } | |
851f26ae OJ |
12018 | /* Handle VCVT. */ |
12019 | else if (opc2 == 0x07 && opc3 == 0x03) | |
dda83cd7 SM |
12020 | { |
12021 | if (!dp_op_sz) | |
12022 | curr_insn_type = INSN_T1; | |
12023 | else | |
12024 | curr_insn_type = INSN_T2; | |
12025 | } | |
851f26ae | 12026 | else if (opc3 & 0x01) |
dda83cd7 SM |
12027 | { |
12028 | /* Handle VCVT. */ | |
12029 | if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) | |
12030 | { | |
12031 | if (!bit (arm_insn_r->arm_insn, 18)) | |
12032 | curr_insn_type = INSN_T2; | |
12033 | else | |
12034 | { | |
12035 | if (dp_op_sz) | |
12036 | curr_insn_type = INSN_T1; | |
12037 | else | |
12038 | curr_insn_type = INSN_T2; | |
12039 | } | |
12040 | } | |
12041 | /* Handle VCVT. */ | |
12042 | else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) | |
12043 | { | |
12044 | if (dp_op_sz) | |
12045 | curr_insn_type = INSN_T1; | |
12046 | else | |
12047 | curr_insn_type = INSN_T2; | |
12048 | } | |
12049 | /* Handle VCVTB, VCVTT. */ | |
12050 | else if ((opc2 & 0x0e) == 0x02) | |
12051 | curr_insn_type = INSN_T2; | |
12052 | /* Handle VCMP, VCMPE. */ | |
12053 | else if ((opc2 & 0x0e) == 0x04) | |
12054 | curr_insn_type = INSN_T3; | |
12055 | } | |
851f26ae OJ |
12056 | } |
12057 | ||
12058 | switch (curr_insn_type) | |
12059 | { | |
12060 | case INSN_T0: | |
dda83cd7 SM |
12061 | reg_vd = reg_vd | (bit_d << 4); |
12062 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12063 | record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; | |
12064 | arm_insn_r->reg_rec_count = 2; | |
12065 | break; | |
851f26ae OJ |
12066 | |
12067 | case INSN_T1: | |
dda83cd7 SM |
12068 | reg_vd = reg_vd | (bit_d << 4); |
12069 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12070 | arm_insn_r->reg_rec_count = 1; | |
12071 | break; | |
851f26ae OJ |
12072 | |
12073 | case INSN_T2: | |
dda83cd7 SM |
12074 | reg_vd = (reg_vd << 1) | bit_d; |
12075 | record_buf[0] = reg_vd + ARM_D0_REGNUM; | |
12076 | arm_insn_r->reg_rec_count = 1; | |
12077 | break; | |
851f26ae OJ |
12078 | |
12079 | case INSN_T3: | |
dda83cd7 SM |
12080 | record_buf[0] = ARM_FPSCR_REGNUM; |
12081 | arm_insn_r->reg_rec_count = 1; | |
12082 | break; | |
851f26ae OJ |
12083 | |
12084 | default: | |
dda83cd7 SM |
12085 | gdb_assert_not_reached ("no decoding pattern found"); |
12086 | break; | |
851f26ae OJ |
12087 | } |
12088 | ||
12089 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); | |
12090 | return 0; | |
12091 | } | |
12092 | ||
60cc5e93 OJ |
12093 | /* Handling opcode 110 insns. */ |
12094 | ||
12095 | static int | |
12096 | arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) | |
12097 | { | |
bec2ab5a | 12098 | uint32_t op1, op1_ebit, coproc; |
60cc5e93 OJ |
12099 | |
12100 | coproc = bits (arm_insn_r->arm_insn, 8, 11); | |
12101 | op1 = bits (arm_insn_r->arm_insn, 20, 25); | |
12102 | op1_ebit = bit (arm_insn_r->arm_insn, 20); | |
12103 | ||
12104 | if ((coproc & 0x0e) == 0x0a) | |
12105 | { | |
12106 | /* Handle extension register ld/st instructions. */ | |
12107 | if (!(op1 & 0x20)) | |
dda83cd7 | 12108 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12109 | |
12110 | /* 64-bit transfers between arm core and extension registers. */ | |
12111 | if ((op1 & 0x3e) == 0x04) | |
dda83cd7 | 12112 | return arm_record_exreg_ld_st_insn (arm_insn_r); |
60cc5e93 OJ |
12113 | } |
12114 | else | |
12115 | { | |
12116 | /* Handle coprocessor ld/st instructions. */ | |
12117 | if (!(op1 & 0x3a)) | |
dda83cd7 SM |
12118 | { |
12119 | /* Store. */ | |
12120 | if (!op1_ebit) | |
12121 | return arm_record_unsupported_insn (arm_insn_r); | |
12122 | else | |
12123 | /* Load. */ | |
12124 | return arm_record_unsupported_insn (arm_insn_r); | |
12125 | } | |
60cc5e93 OJ |
12126 | |
12127 | /* Move to coprocessor from two arm core registers. */ | |
12128 | if (op1 == 0x4) | |
dda83cd7 | 12129 | return arm_record_unsupported_insn (arm_insn_r); |
60cc5e93 OJ |
12130 | |
12131 | /* Move to two arm core registers from coprocessor. */ | |
12132 | if (op1 == 0x5) | |
dda83cd7 SM |
12133 | { |
12134 | uint32_t reg_t[2]; | |
60cc5e93 | 12135 | |
dda83cd7 SM |
12136 | reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); |
12137 | reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); | |
12138 | arm_insn_r->reg_rec_count = 2; | |
60cc5e93 | 12139 | |
dda83cd7 SM |
12140 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); |
12141 | return 0; | |
60cc5e93 OJ |
12142 | } |
12143 | } | |
12144 | return arm_record_unsupported_insn (arm_insn_r); | |
12145 | } | |
12146 | ||
72508ac0 PO |
12147 | /* Handling opcode 111 insns. */ |
12148 | ||
12149 | static int | |
12150 | arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) | |
12151 | { | |
2d9e6acb | 12152 | uint32_t op, op1_ebit, coproc, bits_24_25; |
345bd07c SM |
12153 | arm_gdbarch_tdep *tdep |
12154 | = (arm_gdbarch_tdep *) gdbarch_tdep (arm_insn_r->gdbarch); | |
72508ac0 | 12155 | struct regcache *reg_cache = arm_insn_r->regcache; |
72508ac0 PO |
12156 | |
12157 | arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); | |
60cc5e93 | 12158 | coproc = bits (arm_insn_r->arm_insn, 8, 11); |
60cc5e93 OJ |
12159 | op1_ebit = bit (arm_insn_r->arm_insn, 20); |
12160 | op = bit (arm_insn_r->arm_insn, 4); | |
2d9e6acb | 12161 | bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25); |
97dfe206 OJ |
12162 | |
12163 | /* Handle arm SWI/SVC system call instructions. */ | |
2d9e6acb | 12164 | if (bits_24_25 == 0x3) |
97dfe206 OJ |
12165 | { |
12166 | if (tdep->arm_syscall_record != NULL) | |
dda83cd7 SM |
12167 | { |
12168 | ULONGEST svc_operand, svc_number; | |
97dfe206 | 12169 | |
dda83cd7 | 12170 | svc_operand = (0x00ffffff & arm_insn_r->arm_insn); |
97dfe206 | 12171 | |
dda83cd7 SM |
12172 | if (svc_operand) /* OABI. */ |
12173 | svc_number = svc_operand - 0x900000; | |
12174 | else /* EABI. */ | |
12175 | regcache_raw_read_unsigned (reg_cache, 7, &svc_number); | |
97dfe206 | 12176 | |
dda83cd7 SM |
12177 | return tdep->arm_syscall_record (reg_cache, svc_number); |
12178 | } | |
97dfe206 | 12179 | else |
dda83cd7 | 12180 | { |
6cb06a8c | 12181 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
12182 | return -1; |
12183 | } | |
97dfe206 | 12184 | } |
2d9e6acb | 12185 | else if (bits_24_25 == 0x02) |
60cc5e93 | 12186 | { |
2d9e6acb YQ |
12187 | if (op) |
12188 | { | |
12189 | if ((coproc & 0x0e) == 0x0a) | |
12190 | { | |
12191 | /* 8, 16, and 32-bit transfer */ | |
12192 | return arm_record_vdata_transfer_insn (arm_insn_r); | |
12193 | } | |
12194 | else | |
12195 | { | |
12196 | if (op1_ebit) | |
12197 | { | |
12198 | /* MRC, MRC2 */ | |
12199 | uint32_t record_buf[1]; | |
12200 | ||
12201 | record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); | |
12202 | if (record_buf[0] == 15) | |
12203 | record_buf[0] = ARM_PS_REGNUM; | |
60cc5e93 | 12204 | |
2d9e6acb YQ |
12205 | arm_insn_r->reg_rec_count = 1; |
12206 | REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, | |
12207 | record_buf); | |
12208 | return 0; | |
12209 | } | |
12210 | else | |
12211 | { | |
12212 | /* MCR, MCR2 */ | |
12213 | return -1; | |
12214 | } | |
12215 | } | |
12216 | } | |
12217 | else | |
12218 | { | |
12219 | if ((coproc & 0x0e) == 0x0a) | |
12220 | { | |
12221 | /* VFP data-processing instructions. */ | |
12222 | return arm_record_vfp_data_proc_insn (arm_insn_r); | |
12223 | } | |
12224 | else | |
12225 | { | |
12226 | /* CDP, CDP2 */ | |
12227 | return -1; | |
12228 | } | |
12229 | } | |
60cc5e93 | 12230 | } |
97dfe206 OJ |
12231 | else |
12232 | { | |
2d9e6acb | 12233 | unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25); |
60cc5e93 | 12234 | |
2d9e6acb YQ |
12235 | if (op1 == 5) |
12236 | { | |
12237 | if ((coproc & 0x0e) != 0x0a) | |
12238 | { | |
12239 | /* MRRC, MRRC2 */ | |
12240 | return -1; | |
12241 | } | |
12242 | } | |
12243 | else if (op1 == 4 || op1 == 5) | |
12244 | { | |
12245 | if ((coproc & 0x0e) == 0x0a) | |
12246 | { | |
12247 | /* 64-bit transfers between ARM core and extension */ | |
12248 | return -1; | |
12249 | } | |
12250 | else if (op1 == 4) | |
12251 | { | |
12252 | /* MCRR, MCRR2 */ | |
12253 | return -1; | |
12254 | } | |
12255 | } | |
12256 | else if (op1 == 0 || op1 == 1) | |
12257 | { | |
12258 | /* UNDEFINED */ | |
12259 | return -1; | |
12260 | } | |
12261 | else | |
12262 | { | |
12263 | if ((coproc & 0x0e) == 0x0a) | |
12264 | { | |
12265 | /* Extension register load/store */ | |
12266 | } | |
12267 | else | |
12268 | { | |
12269 | /* STC, STC2, LDC, LDC2 */ | |
12270 | } | |
12271 | return -1; | |
12272 | } | |
97dfe206 | 12273 | } |
72508ac0 | 12274 | |
2d9e6acb | 12275 | return -1; |
72508ac0 PO |
12276 | } |
12277 | ||
12278 | /* Handling opcode 000 insns. */ | |
12279 | ||
12280 | static int | |
12281 | thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) | |
12282 | { | |
12283 | uint32_t record_buf[8]; | |
12284 | uint32_t reg_src1 = 0; | |
12285 | ||
12286 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12287 | ||
12288 | record_buf[0] = ARM_PS_REGNUM; | |
12289 | record_buf[1] = reg_src1; | |
12290 | thumb_insn_r->reg_rec_count = 2; | |
12291 | ||
12292 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12293 | ||
12294 | return 0; | |
12295 | } | |
12296 | ||
12297 | ||
12298 | /* Handling opcode 001 insns. */ | |
12299 | ||
12300 | static int | |
12301 | thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) | |
12302 | { | |
12303 | uint32_t record_buf[8]; | |
12304 | uint32_t reg_src1 = 0; | |
12305 | ||
12306 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12307 | ||
12308 | record_buf[0] = ARM_PS_REGNUM; | |
12309 | record_buf[1] = reg_src1; | |
12310 | thumb_insn_r->reg_rec_count = 2; | |
12311 | ||
12312 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12313 | ||
12314 | return 0; | |
12315 | } | |
12316 | ||
12317 | /* Handling opcode 010 insns. */ | |
12318 | ||
12319 | static int | |
12320 | thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) | |
12321 | { | |
12322 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12323 | uint32_t record_buf[8], record_buf_mem[8]; | |
12324 | ||
12325 | uint32_t reg_src1 = 0, reg_src2 = 0; | |
12326 | uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0; | |
12327 | ||
12328 | ULONGEST u_regval[2] = {0}; | |
12329 | ||
12330 | opcode1 = bits (thumb_insn_r->arm_insn, 10, 12); | |
12331 | ||
12332 | if (bit (thumb_insn_r->arm_insn, 12)) | |
12333 | { | |
12334 | /* Handle load/store register offset. */ | |
b121eeb9 YQ |
12335 | uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11); |
12336 | ||
b020ff80 | 12337 | if (in_inclusive_range (opB, 4U, 7U)) |
dda83cd7 SM |
12338 | { |
12339 | /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ | |
12340 | reg_src1 = bits (thumb_insn_r->arm_insn,0, 2); | |
12341 | record_buf[0] = reg_src1; | |
12342 | thumb_insn_r->reg_rec_count = 1; | |
12343 | } | |
b020ff80 | 12344 | else if (in_inclusive_range (opB, 0U, 2U)) |
dda83cd7 SM |
12345 | { |
12346 | /* STR(2), STRB(2), STRH(2) . */ | |
12347 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12348 | reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8); | |
12349 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); | |
12350 | regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]); | |
12351 | if (0 == opB) | |
12352 | record_buf_mem[0] = 4; /* STR (2). */ | |
12353 | else if (2 == opB) | |
12354 | record_buf_mem[0] = 1; /* STRB (2). */ | |
12355 | else if (1 == opB) | |
12356 | record_buf_mem[0] = 2; /* STRH (2). */ | |
12357 | record_buf_mem[1] = u_regval[0] + u_regval[1]; | |
12358 | thumb_insn_r->mem_rec_count = 1; | |
12359 | } | |
72508ac0 PO |
12360 | } |
12361 | else if (bit (thumb_insn_r->arm_insn, 11)) | |
12362 | { | |
12363 | /* Handle load from literal pool. */ | |
12364 | /* LDR(3). */ | |
12365 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12366 | record_buf[0] = reg_src1; | |
12367 | thumb_insn_r->reg_rec_count = 1; | |
12368 | } | |
12369 | else if (opcode1) | |
12370 | { | |
b121eeb9 | 12371 | /* Special data instructions and branch and exchange */ |
72508ac0 PO |
12372 | opcode2 = bits (thumb_insn_r->arm_insn, 8, 9); |
12373 | opcode3 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12374 | if ((3 == opcode2) && (!opcode3)) | |
dda83cd7 SM |
12375 | { |
12376 | /* Branch with exchange. */ | |
12377 | record_buf[0] = ARM_PS_REGNUM; | |
12378 | thumb_insn_r->reg_rec_count = 1; | |
12379 | } | |
72508ac0 | 12380 | else |
dda83cd7 | 12381 | { |
1f33efec YQ |
12382 | /* Format 8; special data processing insns. */ |
12383 | record_buf[0] = ARM_PS_REGNUM; | |
12384 | record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 | |
12385 | | bits (thumb_insn_r->arm_insn, 0, 2)); | |
dda83cd7 SM |
12386 | thumb_insn_r->reg_rec_count = 2; |
12387 | } | |
72508ac0 PO |
12388 | } |
12389 | else | |
12390 | { | |
12391 | /* Format 5; data processing insns. */ | |
12392 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12393 | if (bit (thumb_insn_r->arm_insn, 7)) | |
dda83cd7 SM |
12394 | { |
12395 | reg_src1 = reg_src1 + 8; | |
12396 | } | |
72508ac0 PO |
12397 | record_buf[0] = ARM_PS_REGNUM; |
12398 | record_buf[1] = reg_src1; | |
12399 | thumb_insn_r->reg_rec_count = 2; | |
12400 | } | |
12401 | ||
12402 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12403 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12404 | record_buf_mem); |
72508ac0 PO |
12405 | |
12406 | return 0; | |
12407 | } | |
12408 | ||
12409 | /* Handling opcode 001 insns. */ | |
12410 | ||
12411 | static int | |
12412 | thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) | |
12413 | { | |
12414 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12415 | uint32_t record_buf[8], record_buf_mem[8]; | |
12416 | ||
12417 | uint32_t reg_src1 = 0; | |
12418 | uint32_t opcode = 0, immed_5 = 0; | |
12419 | ||
12420 | ULONGEST u_regval = 0; | |
12421 | ||
12422 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
12423 | ||
12424 | if (opcode) | |
12425 | { | |
12426 | /* LDR(1). */ | |
12427 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12428 | record_buf[0] = reg_src1; | |
12429 | thumb_insn_r->reg_rec_count = 1; | |
12430 | } | |
12431 | else | |
12432 | { | |
12433 | /* STR(1). */ | |
12434 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12435 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12436 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12437 | record_buf_mem[0] = 4; | |
12438 | record_buf_mem[1] = u_regval + (immed_5 * 4); | |
12439 | thumb_insn_r->mem_rec_count = 1; | |
12440 | } | |
12441 | ||
12442 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12443 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12444 | record_buf_mem); |
72508ac0 PO |
12445 | |
12446 | return 0; | |
12447 | } | |
12448 | ||
12449 | /* Handling opcode 100 insns. */ | |
12450 | ||
12451 | static int | |
12452 | thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) | |
12453 | { | |
12454 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12455 | uint32_t record_buf[8], record_buf_mem[8]; | |
12456 | ||
12457 | uint32_t reg_src1 = 0; | |
12458 | uint32_t opcode = 0, immed_8 = 0, immed_5 = 0; | |
12459 | ||
12460 | ULONGEST u_regval = 0; | |
12461 | ||
12462 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
12463 | ||
12464 | if (3 == opcode) | |
12465 | { | |
12466 | /* LDR(4). */ | |
12467 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12468 | record_buf[0] = reg_src1; | |
12469 | thumb_insn_r->reg_rec_count = 1; | |
12470 | } | |
12471 | else if (1 == opcode) | |
12472 | { | |
12473 | /* LDRH(1). */ | |
12474 | reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); | |
12475 | record_buf[0] = reg_src1; | |
12476 | thumb_insn_r->reg_rec_count = 1; | |
12477 | } | |
12478 | else if (2 == opcode) | |
12479 | { | |
12480 | /* STR(3). */ | |
12481 | immed_8 = bits (thumb_insn_r->arm_insn, 0, 7); | |
12482 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12483 | record_buf_mem[0] = 4; | |
12484 | record_buf_mem[1] = u_regval + (immed_8 * 4); | |
12485 | thumb_insn_r->mem_rec_count = 1; | |
12486 | } | |
12487 | else if (0 == opcode) | |
12488 | { | |
12489 | /* STRH(1). */ | |
12490 | immed_5 = bits (thumb_insn_r->arm_insn, 6, 10); | |
12491 | reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5); | |
12492 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12493 | record_buf_mem[0] = 2; | |
12494 | record_buf_mem[1] = u_regval + (immed_5 * 2); | |
12495 | thumb_insn_r->mem_rec_count = 1; | |
12496 | } | |
12497 | ||
12498 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12499 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12500 | record_buf_mem); |
72508ac0 PO |
12501 | |
12502 | return 0; | |
12503 | } | |
12504 | ||
12505 | /* Handling opcode 101 insns. */ | |
12506 | ||
12507 | static int | |
12508 | thumb_record_misc (insn_decode_record *thumb_insn_r) | |
12509 | { | |
12510 | struct regcache *reg_cache = thumb_insn_r->regcache; | |
12511 | ||
b121eeb9 | 12512 | uint32_t opcode = 0; |
72508ac0 | 12513 | uint32_t register_bits = 0, register_count = 0; |
bec2ab5a | 12514 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12515 | uint32_t record_buf[24], record_buf_mem[48]; |
12516 | uint32_t reg_src1; | |
12517 | ||
12518 | ULONGEST u_regval = 0; | |
12519 | ||
12520 | opcode = bits (thumb_insn_r->arm_insn, 11, 12); | |
72508ac0 | 12521 | |
b121eeb9 | 12522 | if (opcode == 0 || opcode == 1) |
72508ac0 | 12523 | { |
b121eeb9 YQ |
12524 | /* ADR and ADD (SP plus immediate) */ |
12525 | ||
72508ac0 PO |
12526 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); |
12527 | record_buf[0] = reg_src1; | |
12528 | thumb_insn_r->reg_rec_count = 1; | |
12529 | } | |
b121eeb9 | 12530 | else |
72508ac0 | 12531 | { |
b121eeb9 YQ |
12532 | /* Miscellaneous 16-bit instructions */ |
12533 | uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11); | |
12534 | ||
12535 | switch (opcode2) | |
12536 | { | |
12537 | case 6: | |
12538 | /* SETEND and CPS */ | |
12539 | break; | |
12540 | case 0: | |
12541 | /* ADD/SUB (SP plus immediate) */ | |
12542 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12543 | record_buf[0] = ARM_SP_REGNUM; | |
12544 | thumb_insn_r->reg_rec_count = 1; | |
12545 | break; | |
12546 | case 1: /* fall through */ | |
12547 | case 3: /* fall through */ | |
12548 | case 9: /* fall through */ | |
12549 | case 11: | |
12550 | /* CBNZ, CBZ */ | |
b121eeb9 YQ |
12551 | break; |
12552 | case 2: | |
12553 | /* SXTH, SXTB, UXTH, UXTB */ | |
12554 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); | |
12555 | thumb_insn_r->reg_rec_count = 1; | |
12556 | break; | |
12557 | case 4: /* fall through */ | |
12558 | case 5: | |
12559 | /* PUSH. */ | |
12560 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12561 | regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval); | |
12562 | while (register_bits) | |
12563 | { | |
12564 | if (register_bits & 0x00000001) | |
12565 | register_count++; | |
12566 | register_bits = register_bits >> 1; | |
12567 | } | |
12568 | start_address = u_regval - \ | |
12569 | (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)); | |
12570 | thumb_insn_r->mem_rec_count = register_count; | |
12571 | while (register_count) | |
12572 | { | |
12573 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12574 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12575 | start_address = start_address + 4; | |
12576 | register_count--; | |
12577 | } | |
12578 | record_buf[0] = ARM_SP_REGNUM; | |
12579 | thumb_insn_r->reg_rec_count = 1; | |
12580 | break; | |
12581 | case 10: | |
12582 | /* REV, REV16, REVSH */ | |
ba14f379 YQ |
12583 | record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2); |
12584 | thumb_insn_r->reg_rec_count = 1; | |
b121eeb9 YQ |
12585 | break; |
12586 | case 12: /* fall through */ | |
12587 | case 13: | |
12588 | /* POP. */ | |
12589 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12590 | while (register_bits) | |
12591 | { | |
12592 | if (register_bits & 0x00000001) | |
12593 | record_buf[index++] = register_count; | |
12594 | register_bits = register_bits >> 1; | |
12595 | register_count++; | |
12596 | } | |
12597 | record_buf[index++] = ARM_PS_REGNUM; | |
12598 | record_buf[index++] = ARM_SP_REGNUM; | |
12599 | thumb_insn_r->reg_rec_count = index; | |
12600 | break; | |
12601 | case 0xe: | |
12602 | /* BKPT insn. */ | |
12603 | /* Handle enhanced software breakpoint insn, BKPT. */ | |
12604 | /* CPSR is changed to be executed in ARM state, disabling normal | |
12605 | interrupts, entering abort mode. */ | |
12606 | /* According to high vector configuration PC is set. */ | |
12607 | /* User hits breakpoint and type reverse, in that case, we need to go back with | |
12608 | previous CPSR and Program Counter. */ | |
12609 | record_buf[0] = ARM_PS_REGNUM; | |
12610 | record_buf[1] = ARM_LR_REGNUM; | |
12611 | thumb_insn_r->reg_rec_count = 2; | |
12612 | /* We need to save SPSR value, which is not yet done. */ | |
6cb06a8c TT |
12613 | gdb_printf (gdb_stderr, |
12614 | _("Process record does not support instruction " | |
12615 | "0x%0x at address %s.\n"), | |
12616 | thumb_insn_r->arm_insn, | |
12617 | paddress (thumb_insn_r->gdbarch, | |
12618 | thumb_insn_r->this_addr)); | |
b121eeb9 YQ |
12619 | return -1; |
12620 | ||
12621 | case 0xf: | |
12622 | /* If-Then, and hints */ | |
12623 | break; | |
12624 | default: | |
12625 | return -1; | |
12626 | }; | |
72508ac0 PO |
12627 | } |
12628 | ||
12629 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12630 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12631 | record_buf_mem); |
72508ac0 PO |
12632 | |
12633 | return 0; | |
12634 | } | |
12635 | ||
12636 | /* Handling opcode 110 insns. */ | |
12637 | ||
12638 | static int | |
345bd07c | 12639 | thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) |
72508ac0 | 12640 | { |
345bd07c SM |
12641 | arm_gdbarch_tdep *tdep |
12642 | = (arm_gdbarch_tdep *) gdbarch_tdep (thumb_insn_r->gdbarch); | |
72508ac0 PO |
12643 | struct regcache *reg_cache = thumb_insn_r->regcache; |
12644 | ||
12645 | uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ | |
12646 | uint32_t reg_src1 = 0; | |
12647 | uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; | |
bec2ab5a | 12648 | uint32_t index = 0, start_address = 0; |
72508ac0 PO |
12649 | uint32_t record_buf[24], record_buf_mem[48]; |
12650 | ||
12651 | ULONGEST u_regval = 0; | |
12652 | ||
12653 | opcode1 = bits (thumb_insn_r->arm_insn, 8, 12); | |
12654 | opcode2 = bits (thumb_insn_r->arm_insn, 11, 12); | |
12655 | ||
12656 | if (1 == opcode2) | |
12657 | { | |
12658 | ||
12659 | /* LDMIA. */ | |
12660 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12661 | /* Get Rn. */ | |
12662 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12663 | while (register_bits) | |
dda83cd7 SM |
12664 | { |
12665 | if (register_bits & 0x00000001) | |
12666 | record_buf[index++] = register_count; | |
12667 | register_bits = register_bits >> 1; | |
12668 | register_count++; | |
12669 | } | |
f969241e OJ |
12670 | record_buf[index++] = reg_src1; |
12671 | thumb_insn_r->reg_rec_count = index; | |
72508ac0 PO |
12672 | } |
12673 | else if (0 == opcode2) | |
12674 | { | |
12675 | /* It handles both STMIA. */ | |
12676 | register_bits = bits (thumb_insn_r->arm_insn, 0, 7); | |
12677 | /* Get Rn. */ | |
12678 | reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10); | |
12679 | regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); | |
12680 | while (register_bits) | |
dda83cd7 SM |
12681 | { |
12682 | if (register_bits & 0x00000001) | |
12683 | register_count++; | |
12684 | register_bits = register_bits >> 1; | |
12685 | } | |
72508ac0 PO |
12686 | start_address = u_regval; |
12687 | thumb_insn_r->mem_rec_count = register_count; | |
12688 | while (register_count) | |
dda83cd7 SM |
12689 | { |
12690 | record_buf_mem[(register_count * 2) - 1] = start_address; | |
12691 | record_buf_mem[(register_count * 2) - 2] = 4; | |
12692 | start_address = start_address + 4; | |
12693 | register_count--; | |
12694 | } | |
72508ac0 PO |
12695 | } |
12696 | else if (0x1F == opcode1) | |
12697 | { | |
dda83cd7 SM |
12698 | /* Handle arm syscall insn. */ |
12699 | if (tdep->arm_syscall_record != NULL) | |
12700 | { | |
12701 | regcache_raw_read_unsigned (reg_cache, 7, &u_regval); | |
12702 | ret = tdep->arm_syscall_record (reg_cache, u_regval); | |
12703 | } | |
12704 | else | |
12705 | { | |
6cb06a8c | 12706 | gdb_printf (gdb_stderr, _("no syscall record support\n")); |
dda83cd7 SM |
12707 | return -1; |
12708 | } | |
72508ac0 PO |
12709 | } |
12710 | ||
12711 | /* B (1), conditional branch is automatically taken care in process_record, | |
12712 | as PC is saved there. */ | |
12713 | ||
12714 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12715 | MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count, | |
dda83cd7 | 12716 | record_buf_mem); |
72508ac0 PO |
12717 | |
12718 | return ret; | |
12719 | } | |
12720 | ||
12721 | /* Handling opcode 111 insns. */ | |
12722 | ||
12723 | static int | |
12724 | thumb_record_branch (insn_decode_record *thumb_insn_r) | |
12725 | { | |
12726 | uint32_t record_buf[8]; | |
12727 | uint32_t bits_h = 0; | |
12728 | ||
12729 | bits_h = bits (thumb_insn_r->arm_insn, 11, 12); | |
12730 | ||
12731 | if (2 == bits_h || 3 == bits_h) | |
12732 | { | |
12733 | /* BL */ | |
12734 | record_buf[0] = ARM_LR_REGNUM; | |
12735 | thumb_insn_r->reg_rec_count = 1; | |
12736 | } | |
12737 | else if (1 == bits_h) | |
12738 | { | |
12739 | /* BLX(1). */ | |
12740 | record_buf[0] = ARM_PS_REGNUM; | |
12741 | record_buf[1] = ARM_LR_REGNUM; | |
12742 | thumb_insn_r->reg_rec_count = 2; | |
12743 | } | |
12744 | ||
12745 | /* B(2) is automatically taken care in process_record, as PC is | |
12746 | saved there. */ | |
12747 | ||
12748 | REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf); | |
12749 | ||
12750 | return 0; | |
12751 | } | |
12752 | ||
c6ec2b30 OJ |
12753 | /* Handler for thumb2 load/store multiple instructions. */ |
12754 | ||
12755 | static int | |
12756 | thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) | |
12757 | { | |
12758 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12759 | ||
12760 | uint32_t reg_rn, op; | |
12761 | uint32_t register_bits = 0, register_count = 0; | |
12762 | uint32_t index = 0, start_address = 0; | |
12763 | uint32_t record_buf[24], record_buf_mem[48]; | |
12764 | ||
12765 | ULONGEST u_regval = 0; | |
12766 | ||
12767 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12768 | op = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12769 | ||
12770 | if (0 == op || 3 == op) | |
12771 | { | |
12772 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12773 | { |
12774 | /* Handle RFE instruction. */ | |
12775 | record_buf[0] = ARM_PS_REGNUM; | |
12776 | thumb2_insn_r->reg_rec_count = 1; | |
12777 | } | |
c6ec2b30 | 12778 | else |
dda83cd7 SM |
12779 | { |
12780 | /* Handle SRS instruction after reading banked SP. */ | |
12781 | return arm_record_unsupported_insn (thumb2_insn_r); | |
12782 | } | |
c6ec2b30 OJ |
12783 | } |
12784 | else if (1 == op || 2 == op) | |
12785 | { | |
12786 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
dda83cd7 SM |
12787 | { |
12788 | /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */ | |
12789 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12790 | while (register_bits) | |
12791 | { | |
12792 | if (register_bits & 0x00000001) | |
12793 | record_buf[index++] = register_count; | |
12794 | ||
12795 | register_count++; | |
12796 | register_bits = register_bits >> 1; | |
12797 | } | |
12798 | record_buf[index++] = reg_rn; | |
12799 | record_buf[index++] = ARM_PS_REGNUM; | |
12800 | thumb2_insn_r->reg_rec_count = index; | |
12801 | } | |
c6ec2b30 | 12802 | else |
dda83cd7 SM |
12803 | { |
12804 | /* Handle STM/STMIA/STMEA and STMDB/STMFD. */ | |
12805 | register_bits = bits (thumb2_insn_r->arm_insn, 0, 15); | |
12806 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
12807 | while (register_bits) | |
12808 | { | |
12809 | if (register_bits & 0x00000001) | |
12810 | register_count++; | |
12811 | ||
12812 | register_bits = register_bits >> 1; | |
12813 | } | |
12814 | ||
12815 | if (1 == op) | |
12816 | { | |
12817 | /* Start address calculation for LDMDB/LDMEA. */ | |
12818 | start_address = u_regval; | |
12819 | } | |
12820 | else if (2 == op) | |
12821 | { | |
12822 | /* Start address calculation for LDMDB/LDMEA. */ | |
12823 | start_address = u_regval - register_count * 4; | |
12824 | } | |
12825 | ||
12826 | thumb2_insn_r->mem_rec_count = register_count; | |
12827 | while (register_count) | |
12828 | { | |
12829 | record_buf_mem[register_count * 2 - 1] = start_address; | |
12830 | record_buf_mem[register_count * 2 - 2] = 4; | |
12831 | start_address = start_address + 4; | |
12832 | register_count--; | |
12833 | } | |
12834 | record_buf[0] = reg_rn; | |
12835 | record_buf[1] = ARM_PS_REGNUM; | |
12836 | thumb2_insn_r->reg_rec_count = 2; | |
12837 | } | |
c6ec2b30 OJ |
12838 | } |
12839 | ||
12840 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, | |
dda83cd7 | 12841 | record_buf_mem); |
c6ec2b30 | 12842 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, |
dda83cd7 | 12843 | record_buf); |
c6ec2b30 OJ |
12844 | return ARM_RECORD_SUCCESS; |
12845 | } | |
12846 | ||
12847 | /* Handler for thumb2 load/store (dual/exclusive) and table branch | |
12848 | instructions. */ | |
12849 | ||
12850 | static int | |
12851 | thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) | |
12852 | { | |
12853 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
12854 | ||
12855 | uint32_t reg_rd, reg_rn, offset_imm; | |
12856 | uint32_t reg_dest1, reg_dest2; | |
12857 | uint32_t address, offset_addr; | |
12858 | uint32_t record_buf[8], record_buf_mem[8]; | |
12859 | uint32_t op1, op2, op3; | |
c6ec2b30 OJ |
12860 | |
12861 | ULONGEST u_regval[2]; | |
12862 | ||
12863 | op1 = bits (thumb2_insn_r->arm_insn, 23, 24); | |
12864 | op2 = bits (thumb2_insn_r->arm_insn, 20, 21); | |
12865 | op3 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
12866 | ||
12867 | if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM)) | |
12868 | { | |
12869 | if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3))) | |
dda83cd7 SM |
12870 | { |
12871 | reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15); | |
12872 | record_buf[0] = reg_dest1; | |
12873 | record_buf[1] = ARM_PS_REGNUM; | |
12874 | thumb2_insn_r->reg_rec_count = 2; | |
12875 | } | |
c6ec2b30 OJ |
12876 | |
12877 | if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3)) | |
dda83cd7 SM |
12878 | { |
12879 | reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12880 | record_buf[2] = reg_dest2; | |
12881 | thumb2_insn_r->reg_rec_count = 3; | |
12882 | } | |
c6ec2b30 OJ |
12883 | } |
12884 | else | |
12885 | { | |
12886 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
12887 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
12888 | ||
12889 | if (0 == op1 && 0 == op2) | |
dda83cd7 SM |
12890 | { |
12891 | /* Handle STREX. */ | |
12892 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12893 | address = u_regval[0] + (offset_imm * 4); | |
12894 | record_buf_mem[0] = 4; | |
12895 | record_buf_mem[1] = address; | |
12896 | thumb2_insn_r->mem_rec_count = 1; | |
12897 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12898 | record_buf[0] = reg_rd; | |
12899 | thumb2_insn_r->reg_rec_count = 1; | |
12900 | } | |
c6ec2b30 | 12901 | else if (1 == op1 && 0 == op2) |
dda83cd7 SM |
12902 | { |
12903 | reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3); | |
12904 | record_buf[0] = reg_rd; | |
12905 | thumb2_insn_r->reg_rec_count = 1; | |
12906 | address = u_regval[0]; | |
12907 | record_buf_mem[1] = address; | |
12908 | ||
12909 | if (4 == op3) | |
12910 | { | |
12911 | /* Handle STREXB. */ | |
12912 | record_buf_mem[0] = 1; | |
12913 | thumb2_insn_r->mem_rec_count = 1; | |
12914 | } | |
12915 | else if (5 == op3) | |
12916 | { | |
12917 | /* Handle STREXH. */ | |
12918 | record_buf_mem[0] = 2 ; | |
12919 | thumb2_insn_r->mem_rec_count = 1; | |
12920 | } | |
12921 | else if (7 == op3) | |
12922 | { | |
12923 | /* Handle STREXD. */ | |
12924 | address = u_regval[0]; | |
12925 | record_buf_mem[0] = 4; | |
12926 | record_buf_mem[2] = 4; | |
12927 | record_buf_mem[3] = address + 4; | |
12928 | thumb2_insn_r->mem_rec_count = 2; | |
12929 | } | |
12930 | } | |
c6ec2b30 | 12931 | else |
dda83cd7 SM |
12932 | { |
12933 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
12934 | ||
12935 | if (bit (thumb2_insn_r->arm_insn, 24)) | |
12936 | { | |
12937 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
12938 | offset_addr = u_regval[0] + (offset_imm * 4); | |
12939 | else | |
12940 | offset_addr = u_regval[0] - (offset_imm * 4); | |
12941 | ||
12942 | address = offset_addr; | |
12943 | } | |
12944 | else | |
12945 | address = u_regval[0]; | |
12946 | ||
12947 | record_buf_mem[0] = 4; | |
12948 | record_buf_mem[1] = address; | |
12949 | record_buf_mem[2] = 4; | |
12950 | record_buf_mem[3] = address + 4; | |
12951 | thumb2_insn_r->mem_rec_count = 2; | |
12952 | record_buf[0] = reg_rn; | |
12953 | thumb2_insn_r->reg_rec_count = 1; | |
12954 | } | |
c6ec2b30 OJ |
12955 | } |
12956 | ||
12957 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12958 | record_buf); |
c6ec2b30 | 12959 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 12960 | record_buf_mem); |
c6ec2b30 OJ |
12961 | return ARM_RECORD_SUCCESS; |
12962 | } | |
12963 | ||
12964 | /* Handler for thumb2 data processing (shift register and modified immediate) | |
12965 | instructions. */ | |
12966 | ||
12967 | static int | |
12968 | thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) | |
12969 | { | |
12970 | uint32_t reg_rd, op; | |
12971 | uint32_t record_buf[8]; | |
12972 | ||
12973 | op = bits (thumb2_insn_r->arm_insn, 21, 24); | |
12974 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
12975 | ||
12976 | if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd) | |
12977 | { | |
12978 | record_buf[0] = ARM_PS_REGNUM; | |
12979 | thumb2_insn_r->reg_rec_count = 1; | |
12980 | } | |
12981 | else | |
12982 | { | |
12983 | record_buf[0] = reg_rd; | |
12984 | record_buf[1] = ARM_PS_REGNUM; | |
12985 | thumb2_insn_r->reg_rec_count = 2; | |
12986 | } | |
12987 | ||
12988 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 12989 | record_buf); |
c6ec2b30 OJ |
12990 | return ARM_RECORD_SUCCESS; |
12991 | } | |
12992 | ||
12993 | /* Generic handler for thumb2 instructions which effect destination and PS | |
12994 | registers. */ | |
12995 | ||
12996 | static int | |
12997 | thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) | |
12998 | { | |
12999 | uint32_t reg_rd; | |
13000 | uint32_t record_buf[8]; | |
13001 | ||
13002 | reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13003 | ||
13004 | record_buf[0] = reg_rd; | |
13005 | record_buf[1] = ARM_PS_REGNUM; | |
13006 | thumb2_insn_r->reg_rec_count = 2; | |
13007 | ||
13008 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13009 | record_buf); |
c6ec2b30 OJ |
13010 | return ARM_RECORD_SUCCESS; |
13011 | } | |
13012 | ||
13013 | /* Handler for thumb2 branch and miscellaneous control instructions. */ | |
13014 | ||
13015 | static int | |
13016 | thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) | |
13017 | { | |
13018 | uint32_t op, op1, op2; | |
13019 | uint32_t record_buf[8]; | |
13020 | ||
13021 | op = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13022 | op1 = bits (thumb2_insn_r->arm_insn, 12, 14); | |
13023 | op2 = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13024 | ||
13025 | /* Handle MSR insn. */ | |
13026 | if (!(op1 & 0x2) && 0x38 == op) | |
13027 | { | |
13028 | if (!(op2 & 0x3)) | |
dda83cd7 SM |
13029 | { |
13030 | /* CPSR is going to be changed. */ | |
13031 | record_buf[0] = ARM_PS_REGNUM; | |
13032 | thumb2_insn_r->reg_rec_count = 1; | |
13033 | } | |
c6ec2b30 | 13034 | else |
dda83cd7 SM |
13035 | { |
13036 | arm_record_unsupported_insn(thumb2_insn_r); | |
13037 | return -1; | |
13038 | } | |
c6ec2b30 OJ |
13039 | } |
13040 | else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5)) | |
13041 | { | |
13042 | /* BLX. */ | |
13043 | record_buf[0] = ARM_PS_REGNUM; | |
13044 | record_buf[1] = ARM_LR_REGNUM; | |
13045 | thumb2_insn_r->reg_rec_count = 2; | |
13046 | } | |
13047 | ||
13048 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13049 | record_buf); |
c6ec2b30 OJ |
13050 | return ARM_RECORD_SUCCESS; |
13051 | } | |
13052 | ||
13053 | /* Handler for thumb2 store single data item instructions. */ | |
13054 | ||
13055 | static int | |
13056 | thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) | |
13057 | { | |
13058 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13059 | ||
13060 | uint32_t reg_rn, reg_rm, offset_imm, shift_imm; | |
13061 | uint32_t address, offset_addr; | |
13062 | uint32_t record_buf[8], record_buf_mem[8]; | |
13063 | uint32_t op1, op2; | |
13064 | ||
13065 | ULONGEST u_regval[2]; | |
13066 | ||
13067 | op1 = bits (thumb2_insn_r->arm_insn, 21, 23); | |
13068 | op2 = bits (thumb2_insn_r->arm_insn, 6, 11); | |
13069 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13070 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]); | |
13071 | ||
13072 | if (bit (thumb2_insn_r->arm_insn, 23)) | |
13073 | { | |
13074 | /* T2 encoding. */ | |
13075 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11); | |
13076 | offset_addr = u_regval[0] + offset_imm; | |
13077 | address = offset_addr; | |
13078 | } | |
13079 | else | |
13080 | { | |
13081 | /* T3 encoding. */ | |
13082 | if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20)) | |
dda83cd7 SM |
13083 | { |
13084 | /* Handle STRB (register). */ | |
13085 | reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3); | |
13086 | regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]); | |
13087 | shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5); | |
13088 | offset_addr = u_regval[1] << shift_imm; | |
13089 | address = u_regval[0] + offset_addr; | |
13090 | } | |
c6ec2b30 | 13091 | else |
dda83cd7 SM |
13092 | { |
13093 | offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7); | |
13094 | if (bit (thumb2_insn_r->arm_insn, 10)) | |
13095 | { | |
13096 | if (bit (thumb2_insn_r->arm_insn, 9)) | |
13097 | offset_addr = u_regval[0] + offset_imm; | |
13098 | else | |
13099 | offset_addr = u_regval[0] - offset_imm; | |
13100 | ||
13101 | address = offset_addr; | |
13102 | } | |
13103 | else | |
13104 | address = u_regval[0]; | |
13105 | } | |
c6ec2b30 OJ |
13106 | } |
13107 | ||
13108 | switch (op1) | |
13109 | { | |
13110 | /* Store byte instructions. */ | |
13111 | case 4: | |
13112 | case 0: | |
dda83cd7 SM |
13113 | record_buf_mem[0] = 1; |
13114 | break; | |
c6ec2b30 OJ |
13115 | /* Store half word instructions. */ |
13116 | case 1: | |
13117 | case 5: | |
dda83cd7 SM |
13118 | record_buf_mem[0] = 2; |
13119 | break; | |
c6ec2b30 OJ |
13120 | /* Store word instructions. */ |
13121 | case 2: | |
13122 | case 6: | |
dda83cd7 SM |
13123 | record_buf_mem[0] = 4; |
13124 | break; | |
c6ec2b30 OJ |
13125 | |
13126 | default: | |
dda83cd7 SM |
13127 | gdb_assert_not_reached ("no decoding pattern found"); |
13128 | break; | |
c6ec2b30 OJ |
13129 | } |
13130 | ||
13131 | record_buf_mem[1] = address; | |
13132 | thumb2_insn_r->mem_rec_count = 1; | |
13133 | record_buf[0] = reg_rn; | |
13134 | thumb2_insn_r->reg_rec_count = 1; | |
13135 | ||
13136 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13137 | record_buf); |
c6ec2b30 | 13138 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13139 | record_buf_mem); |
c6ec2b30 OJ |
13140 | return ARM_RECORD_SUCCESS; |
13141 | } | |
13142 | ||
13143 | /* Handler for thumb2 load memory hints instructions. */ | |
13144 | ||
13145 | static int | |
13146 | thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) | |
13147 | { | |
13148 | uint32_t record_buf[8]; | |
13149 | uint32_t reg_rt, reg_rn; | |
13150 | ||
13151 | reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13152 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13153 | ||
13154 | if (ARM_PC_REGNUM != reg_rt) | |
13155 | { | |
13156 | record_buf[0] = reg_rt; | |
13157 | record_buf[1] = reg_rn; | |
13158 | record_buf[2] = ARM_PS_REGNUM; | |
13159 | thumb2_insn_r->reg_rec_count = 3; | |
13160 | ||
13161 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13162 | record_buf); |
c6ec2b30 OJ |
13163 | return ARM_RECORD_SUCCESS; |
13164 | } | |
13165 | ||
13166 | return ARM_RECORD_FAILURE; | |
13167 | } | |
13168 | ||
13169 | /* Handler for thumb2 load word instructions. */ | |
13170 | ||
13171 | static int | |
13172 | thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) | |
13173 | { | |
c6ec2b30 OJ |
13174 | uint32_t record_buf[8]; |
13175 | ||
13176 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13177 | record_buf[1] = ARM_PS_REGNUM; | |
13178 | thumb2_insn_r->reg_rec_count = 2; | |
13179 | ||
13180 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13181 | record_buf); |
c6ec2b30 OJ |
13182 | return ARM_RECORD_SUCCESS; |
13183 | } | |
13184 | ||
13185 | /* Handler for thumb2 long multiply, long multiply accumulate, and | |
13186 | divide instructions. */ | |
13187 | ||
13188 | static int | |
13189 | thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) | |
13190 | { | |
13191 | uint32_t opcode1 = 0, opcode2 = 0; | |
13192 | uint32_t record_buf[8]; | |
c6ec2b30 OJ |
13193 | |
13194 | opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); | |
13195 | opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); | |
13196 | ||
13197 | if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6)) | |
13198 | { | |
13199 | /* Handle SMULL, UMULL, SMULAL. */ | |
13200 | /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */ | |
13201 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13202 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13203 | record_buf[2] = ARM_PS_REGNUM; | |
13204 | thumb2_insn_r->reg_rec_count = 3; | |
13205 | } | |
13206 | else if (1 == opcode1 || 3 == opcode2) | |
13207 | { | |
13208 | /* Handle SDIV and UDIV. */ | |
13209 | record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13210 | record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13211 | record_buf[2] = ARM_PS_REGNUM; | |
13212 | thumb2_insn_r->reg_rec_count = 3; | |
13213 | } | |
13214 | else | |
13215 | return ARM_RECORD_FAILURE; | |
13216 | ||
13217 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13218 | record_buf); |
c6ec2b30 OJ |
13219 | return ARM_RECORD_SUCCESS; |
13220 | } | |
13221 | ||
60cc5e93 OJ |
13222 | /* Record handler for thumb32 coprocessor instructions. */ |
13223 | ||
13224 | static int | |
13225 | thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) | |
13226 | { | |
13227 | if (bit (thumb2_insn_r->arm_insn, 25)) | |
13228 | return arm_record_coproc_data_proc (thumb2_insn_r); | |
13229 | else | |
13230 | return arm_record_asimd_vfp_coproc (thumb2_insn_r); | |
13231 | } | |
13232 | ||
1e1b6563 OJ |
13233 | /* Record handler for advance SIMD structure load/store instructions. */ |
13234 | ||
13235 | static int | |
13236 | thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) | |
13237 | { | |
13238 | struct regcache *reg_cache = thumb2_insn_r->regcache; | |
13239 | uint32_t l_bit, a_bit, b_bits; | |
13240 | uint32_t record_buf[128], record_buf_mem[128]; | |
bec2ab5a | 13241 | uint32_t reg_rn, reg_vd, address, f_elem; |
1e1b6563 OJ |
13242 | uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; |
13243 | uint8_t f_ebytes; | |
13244 | ||
13245 | l_bit = bit (thumb2_insn_r->arm_insn, 21); | |
13246 | a_bit = bit (thumb2_insn_r->arm_insn, 23); | |
13247 | b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); | |
13248 | reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); | |
13249 | reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); | |
13250 | reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; | |
13251 | f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); | |
1e1b6563 OJ |
13252 | f_elem = 8 / f_ebytes; |
13253 | ||
13254 | if (!l_bit) | |
13255 | { | |
13256 | ULONGEST u_regval = 0; | |
13257 | regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); | |
13258 | address = u_regval; | |
13259 | ||
13260 | if (!a_bit) | |
dda83cd7 SM |
13261 | { |
13262 | /* Handle VST1. */ | |
13263 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
13264 | { | |
13265 | if (b_bits == 0x07) | |
13266 | bf_regs = 1; | |
13267 | else if (b_bits == 0x0a) | |
13268 | bf_regs = 2; | |
13269 | else if (b_bits == 0x06) | |
13270 | bf_regs = 3; | |
13271 | else if (b_bits == 0x02) | |
13272 | bf_regs = 4; | |
13273 | else | |
13274 | bf_regs = 0; | |
13275 | ||
13276 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13277 | { | |
13278 | for (index_e = 0; index_e < f_elem; index_e++) | |
13279 | { | |
13280 | record_buf_mem[index_m++] = f_ebytes; | |
13281 | record_buf_mem[index_m++] = address; | |
13282 | address = address + f_ebytes; | |
13283 | thumb2_insn_r->mem_rec_count += 1; | |
13284 | } | |
13285 | } | |
13286 | } | |
13287 | /* Handle VST2. */ | |
13288 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
13289 | { | |
13290 | if (b_bits == 0x09 || b_bits == 0x08) | |
13291 | bf_regs = 1; | |
13292 | else if (b_bits == 0x03) | |
13293 | bf_regs = 2; | |
13294 | else | |
13295 | bf_regs = 0; | |
13296 | ||
13297 | for (index_r = 0; index_r < bf_regs; index_r++) | |
13298 | for (index_e = 0; index_e < f_elem; index_e++) | |
13299 | { | |
13300 | for (loop_t = 0; loop_t < 2; loop_t++) | |
13301 | { | |
13302 | record_buf_mem[index_m++] = f_ebytes; | |
13303 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13304 | thumb2_insn_r->mem_rec_count += 1; | |
13305 | } | |
13306 | address = address + (2 * f_ebytes); | |
13307 | } | |
13308 | } | |
13309 | /* Handle VST3. */ | |
13310 | else if ((b_bits & 0x0e) == 0x04) | |
13311 | { | |
13312 | for (index_e = 0; index_e < f_elem; index_e++) | |
13313 | { | |
13314 | for (loop_t = 0; loop_t < 3; loop_t++) | |
13315 | { | |
13316 | record_buf_mem[index_m++] = f_ebytes; | |
13317 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13318 | thumb2_insn_r->mem_rec_count += 1; | |
13319 | } | |
13320 | address = address + (3 * f_ebytes); | |
13321 | } | |
13322 | } | |
13323 | /* Handle VST4. */ | |
13324 | else if (!(b_bits & 0x0e)) | |
13325 | { | |
13326 | for (index_e = 0; index_e < f_elem; index_e++) | |
13327 | { | |
13328 | for (loop_t = 0; loop_t < 4; loop_t++) | |
13329 | { | |
13330 | record_buf_mem[index_m++] = f_ebytes; | |
13331 | record_buf_mem[index_m++] = address + (loop_t * f_ebytes); | |
13332 | thumb2_insn_r->mem_rec_count += 1; | |
13333 | } | |
13334 | address = address + (4 * f_ebytes); | |
13335 | } | |
13336 | } | |
13337 | } | |
1e1b6563 | 13338 | else |
dda83cd7 SM |
13339 | { |
13340 | uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); | |
13341 | ||
13342 | if (bft_size == 0x00) | |
13343 | f_ebytes = 1; | |
13344 | else if (bft_size == 0x01) | |
13345 | f_ebytes = 2; | |
13346 | else if (bft_size == 0x02) | |
13347 | f_ebytes = 4; | |
13348 | else | |
13349 | f_ebytes = 0; | |
13350 | ||
13351 | /* Handle VST1. */ | |
13352 | if (!(b_bits & 0x0b) || b_bits == 0x08) | |
13353 | thumb2_insn_r->mem_rec_count = 1; | |
13354 | /* Handle VST2. */ | |
13355 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) | |
13356 | thumb2_insn_r->mem_rec_count = 2; | |
13357 | /* Handle VST3. */ | |
13358 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) | |
13359 | thumb2_insn_r->mem_rec_count = 3; | |
13360 | /* Handle VST4. */ | |
13361 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) | |
13362 | thumb2_insn_r->mem_rec_count = 4; | |
13363 | ||
13364 | for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) | |
13365 | { | |
13366 | record_buf_mem[index_m] = f_ebytes; | |
13367 | record_buf_mem[index_m] = address + (index_m * f_ebytes); | |
13368 | } | |
13369 | } | |
1e1b6563 OJ |
13370 | } |
13371 | else | |
13372 | { | |
13373 | if (!a_bit) | |
dda83cd7 SM |
13374 | { |
13375 | /* Handle VLD1. */ | |
13376 | if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) | |
13377 | thumb2_insn_r->reg_rec_count = 1; | |
13378 | /* Handle VLD2. */ | |
13379 | else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) | |
13380 | thumb2_insn_r->reg_rec_count = 2; | |
13381 | /* Handle VLD3. */ | |
13382 | else if ((b_bits & 0x0e) == 0x04) | |
13383 | thumb2_insn_r->reg_rec_count = 3; | |
13384 | /* Handle VLD4. */ | |
13385 | else if (!(b_bits & 0x0e)) | |
13386 | thumb2_insn_r->reg_rec_count = 4; | |
13387 | } | |
1e1b6563 | 13388 | else |
dda83cd7 SM |
13389 | { |
13390 | /* Handle VLD1. */ | |
13391 | if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) | |
13392 | thumb2_insn_r->reg_rec_count = 1; | |
13393 | /* Handle VLD2. */ | |
13394 | else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) | |
13395 | thumb2_insn_r->reg_rec_count = 2; | |
13396 | /* Handle VLD3. */ | |
13397 | else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) | |
13398 | thumb2_insn_r->reg_rec_count = 3; | |
13399 | /* Handle VLD4. */ | |
13400 | else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) | |
13401 | thumb2_insn_r->reg_rec_count = 4; | |
13402 | ||
13403 | for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) | |
13404 | record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; | |
13405 | } | |
1e1b6563 OJ |
13406 | } |
13407 | ||
13408 | if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) | |
13409 | { | |
13410 | record_buf[index_r] = reg_rn; | |
13411 | thumb2_insn_r->reg_rec_count += 1; | |
13412 | } | |
13413 | ||
13414 | REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, | |
dda83cd7 | 13415 | record_buf); |
1e1b6563 | 13416 | MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, |
dda83cd7 | 13417 | record_buf_mem); |
1e1b6563 OJ |
13418 | return 0; |
13419 | } | |
13420 | ||
c6ec2b30 OJ |
13421 | /* Decodes thumb2 instruction type and invokes its record handler. */ |
13422 | ||
13423 | static unsigned int | |
13424 | thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) | |
13425 | { | |
13426 | uint32_t op, op1, op2; | |
13427 | ||
13428 | op = bit (thumb2_insn_r->arm_insn, 15); | |
13429 | op1 = bits (thumb2_insn_r->arm_insn, 27, 28); | |
13430 | op2 = bits (thumb2_insn_r->arm_insn, 20, 26); | |
13431 | ||
13432 | if (op1 == 0x01) | |
13433 | { | |
13434 | if (!(op2 & 0x64 )) | |
dda83cd7 SM |
13435 | { |
13436 | /* Load/store multiple instruction. */ | |
13437 | return thumb2_record_ld_st_multiple (thumb2_insn_r); | |
13438 | } | |
b121eeb9 | 13439 | else if ((op2 & 0x64) == 0x4) |
dda83cd7 SM |
13440 | { |
13441 | /* Load/store (dual/exclusive) and table branch instruction. */ | |
13442 | return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r); | |
13443 | } | |
b121eeb9 | 13444 | else if ((op2 & 0x60) == 0x20) |
dda83cd7 SM |
13445 | { |
13446 | /* Data-processing (shifted register). */ | |
13447 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
13448 | } | |
c6ec2b30 | 13449 | else if (op2 & 0x40) |
dda83cd7 SM |
13450 | { |
13451 | /* Co-processor instructions. */ | |
13452 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
13453 | } | |
c6ec2b30 OJ |
13454 | } |
13455 | else if (op1 == 0x02) | |
13456 | { | |
13457 | if (op) | |
dda83cd7 SM |
13458 | { |
13459 | /* Branches and miscellaneous control instructions. */ | |
13460 | return thumb2_record_branch_misc_cntrl (thumb2_insn_r); | |
13461 | } | |
c6ec2b30 | 13462 | else if (op2 & 0x20) |
dda83cd7 SM |
13463 | { |
13464 | /* Data-processing (plain binary immediate) instruction. */ | |
13465 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13466 | } | |
c6ec2b30 | 13467 | else |
dda83cd7 SM |
13468 | { |
13469 | /* Data-processing (modified immediate). */ | |
13470 | return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r); | |
13471 | } | |
c6ec2b30 OJ |
13472 | } |
13473 | else if (op1 == 0x03) | |
13474 | { | |
13475 | if (!(op2 & 0x71 )) | |
dda83cd7 SM |
13476 | { |
13477 | /* Store single data item. */ | |
13478 | return thumb2_record_str_single_data (thumb2_insn_r); | |
13479 | } | |
c6ec2b30 | 13480 | else if (!((op2 & 0x71) ^ 0x10)) |
dda83cd7 SM |
13481 | { |
13482 | /* Advanced SIMD or structure load/store instructions. */ | |
13483 | return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); | |
13484 | } | |
c6ec2b30 | 13485 | else if (!((op2 & 0x67) ^ 0x01)) |
dda83cd7 SM |
13486 | { |
13487 | /* Load byte, memory hints instruction. */ | |
13488 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13489 | } | |
c6ec2b30 | 13490 | else if (!((op2 & 0x67) ^ 0x03)) |
dda83cd7 SM |
13491 | { |
13492 | /* Load halfword, memory hints instruction. */ | |
13493 | return thumb2_record_ld_mem_hints (thumb2_insn_r); | |
13494 | } | |
c6ec2b30 | 13495 | else if (!((op2 & 0x67) ^ 0x05)) |
dda83cd7 SM |
13496 | { |
13497 | /* Load word instruction. */ | |
13498 | return thumb2_record_ld_word (thumb2_insn_r); | |
13499 | } | |
c6ec2b30 | 13500 | else if (!((op2 & 0x70) ^ 0x20)) |
dda83cd7 SM |
13501 | { |
13502 | /* Data-processing (register) instruction. */ | |
13503 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13504 | } | |
c6ec2b30 | 13505 | else if (!((op2 & 0x78) ^ 0x30)) |
dda83cd7 SM |
13506 | { |
13507 | /* Multiply, multiply accumulate, abs diff instruction. */ | |
13508 | return thumb2_record_ps_dest_generic (thumb2_insn_r); | |
13509 | } | |
c6ec2b30 | 13510 | else if (!((op2 & 0x78) ^ 0x38)) |
dda83cd7 SM |
13511 | { |
13512 | /* Long multiply, long multiply accumulate, and divide. */ | |
13513 | return thumb2_record_lmul_lmla_div (thumb2_insn_r); | |
13514 | } | |
c6ec2b30 | 13515 | else if (op2 & 0x40) |
dda83cd7 SM |
13516 | { |
13517 | /* Co-processor instructions. */ | |
13518 | return thumb2_record_coproc_insn (thumb2_insn_r); | |
13519 | } | |
c6ec2b30 OJ |
13520 | } |
13521 | ||
13522 | return -1; | |
13523 | } | |
72508ac0 | 13524 | |
ffdbe864 | 13525 | namespace { |
728a7913 YQ |
13526 | /* Abstract memory reader. */ |
13527 | ||
13528 | class abstract_memory_reader | |
13529 | { | |
13530 | public: | |
13531 | /* Read LEN bytes of target memory at address MEMADDR, placing the | |
13532 | results in GDB's memory at BUF. Return true on success. */ | |
13533 | ||
13534 | virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0; | |
13535 | }; | |
13536 | ||
13537 | /* Instruction reader from real target. */ | |
13538 | ||
13539 | class instruction_reader : public abstract_memory_reader | |
13540 | { | |
13541 | public: | |
632e107b | 13542 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
728a7913 YQ |
13543 | { |
13544 | if (target_read_memory (memaddr, buf, len)) | |
13545 | return false; | |
13546 | else | |
13547 | return true; | |
13548 | } | |
13549 | }; | |
13550 | ||
ffdbe864 YQ |
13551 | } // namespace |
13552 | ||
72508ac0 | 13553 | /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success |
85102364 | 13554 | and positive val on failure. */ |
72508ac0 PO |
13555 | |
13556 | static int | |
728a7913 YQ |
13557 | extract_arm_insn (abstract_memory_reader& reader, |
13558 | insn_decode_record *insn_record, uint32_t insn_size) | |
72508ac0 PO |
13559 | { |
13560 | gdb_byte buf[insn_size]; | |
13561 | ||
13562 | memset (&buf[0], 0, insn_size); | |
13563 | ||
728a7913 | 13564 | if (!reader.read (insn_record->this_addr, buf, insn_size)) |
72508ac0 PO |
13565 | return 1; |
13566 | insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], | |
dda83cd7 | 13567 | insn_size, |
2959fed9 | 13568 | gdbarch_byte_order_for_code (insn_record->gdbarch)); |
72508ac0 PO |
13569 | return 0; |
13570 | } | |
13571 | ||
13572 | typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); | |
13573 | ||
13574 | /* Decode arm/thumb insn depending on condition cods and opcodes; and | |
13575 | dispatch it. */ | |
13576 | ||
13577 | static int | |
728a7913 YQ |
13578 | decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record, |
13579 | record_type_t record_type, uint32_t insn_size) | |
72508ac0 PO |
13580 | { |
13581 | ||
01e57735 YQ |
13582 | /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm |
13583 | instruction. */ | |
0fa9c223 | 13584 | static const sti_arm_hdl_fp_t arm_handle_insn[8] = |
72508ac0 PO |
13585 | { |
13586 | arm_record_data_proc_misc_ld_str, /* 000. */ | |
13587 | arm_record_data_proc_imm, /* 001. */ | |
13588 | arm_record_ld_st_imm_offset, /* 010. */ | |
13589 | arm_record_ld_st_reg_offset, /* 011. */ | |
13590 | arm_record_ld_st_multiple, /* 100. */ | |
13591 | arm_record_b_bl, /* 101. */ | |
60cc5e93 | 13592 | arm_record_asimd_vfp_coproc, /* 110. */ |
72508ac0 PO |
13593 | arm_record_coproc_data_proc /* 111. */ |
13594 | }; | |
13595 | ||
01e57735 YQ |
13596 | /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb |
13597 | instruction. */ | |
0fa9c223 | 13598 | static const sti_arm_hdl_fp_t thumb_handle_insn[8] = |
72508ac0 PO |
13599 | { \ |
13600 | thumb_record_shift_add_sub, /* 000. */ | |
13601 | thumb_record_add_sub_cmp_mov, /* 001. */ | |
13602 | thumb_record_ld_st_reg_offset, /* 010. */ | |
13603 | thumb_record_ld_st_imm_offset, /* 011. */ | |
13604 | thumb_record_ld_st_stack, /* 100. */ | |
13605 | thumb_record_misc, /* 101. */ | |
13606 | thumb_record_ldm_stm_swi, /* 110. */ | |
13607 | thumb_record_branch /* 111. */ | |
13608 | }; | |
13609 | ||
13610 | uint32_t ret = 0; /* return value: negative:failure 0:success. */ | |
13611 | uint32_t insn_id = 0; | |
13612 | ||
728a7913 | 13613 | if (extract_arm_insn (reader, arm_record, insn_size)) |
72508ac0 PO |
13614 | { |
13615 | if (record_debug) | |
01e57735 | 13616 | { |
6cb06a8c TT |
13617 | gdb_printf (gdb_stdlog, |
13618 | _("Process record: error reading memory at " | |
13619 | "addr %s len = %d.\n"), | |
13620 | paddress (arm_record->gdbarch, | |
13621 | arm_record->this_addr), insn_size); | |
01e57735 | 13622 | } |
72508ac0 PO |
13623 | return -1; |
13624 | } | |
13625 | else if (ARM_RECORD == record_type) | |
13626 | { | |
13627 | arm_record->cond = bits (arm_record->arm_insn, 28, 31); | |
13628 | insn_id = bits (arm_record->arm_insn, 25, 27); | |
ca92db2d YQ |
13629 | |
13630 | if (arm_record->cond == 0xf) | |
13631 | ret = arm_record_extension_space (arm_record); | |
13632 | else | |
01e57735 | 13633 | { |
ca92db2d YQ |
13634 | /* If this insn has fallen into extension space |
13635 | then we need not decode it anymore. */ | |
01e57735 YQ |
13636 | ret = arm_handle_insn[insn_id] (arm_record); |
13637 | } | |
ca92db2d YQ |
13638 | if (ret != ARM_RECORD_SUCCESS) |
13639 | { | |
13640 | arm_record_unsupported_insn (arm_record); | |
13641 | ret = -1; | |
13642 | } | |
72508ac0 PO |
13643 | } |
13644 | else if (THUMB_RECORD == record_type) | |
13645 | { | |
13646 | /* As thumb does not have condition codes, we set negative. */ | |
13647 | arm_record->cond = -1; | |
13648 | insn_id = bits (arm_record->arm_insn, 13, 15); | |
13649 | ret = thumb_handle_insn[insn_id] (arm_record); | |
ca92db2d YQ |
13650 | if (ret != ARM_RECORD_SUCCESS) |
13651 | { | |
13652 | arm_record_unsupported_insn (arm_record); | |
13653 | ret = -1; | |
13654 | } | |
72508ac0 PO |
13655 | } |
13656 | else if (THUMB2_RECORD == record_type) | |
13657 | { | |
c6ec2b30 OJ |
13658 | /* As thumb does not have condition codes, we set negative. */ |
13659 | arm_record->cond = -1; | |
13660 | ||
13661 | /* Swap first half of 32bit thumb instruction with second half. */ | |
13662 | arm_record->arm_insn | |
01e57735 | 13663 | = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); |
c6ec2b30 | 13664 | |
ca92db2d | 13665 | ret = thumb2_record_decode_insn_handler (arm_record); |
c6ec2b30 | 13666 | |
ca92db2d | 13667 | if (ret != ARM_RECORD_SUCCESS) |
01e57735 YQ |
13668 | { |
13669 | arm_record_unsupported_insn (arm_record); | |
13670 | ret = -1; | |
13671 | } | |
72508ac0 PO |
13672 | } |
13673 | else | |
13674 | { | |
13675 | /* Throw assertion. */ | |
13676 | gdb_assert_not_reached ("not a valid instruction, could not decode"); | |
13677 | } | |
13678 | ||
13679 | return ret; | |
13680 | } | |
13681 | ||
b121eeb9 YQ |
13682 | #if GDB_SELF_TEST |
13683 | namespace selftests { | |
13684 | ||
13685 | /* Provide both 16-bit and 32-bit thumb instructions. */ | |
13686 | ||
13687 | class instruction_reader_thumb : public abstract_memory_reader | |
13688 | { | |
13689 | public: | |
13690 | template<size_t SIZE> | |
13691 | instruction_reader_thumb (enum bfd_endian endian, | |
13692 | const uint16_t (&insns)[SIZE]) | |
13693 | : m_endian (endian), m_insns (insns), m_insns_size (SIZE) | |
13694 | {} | |
13695 | ||
632e107b | 13696 | bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override |
b121eeb9 YQ |
13697 | { |
13698 | SELF_CHECK (len == 4 || len == 2); | |
13699 | SELF_CHECK (memaddr % 2 == 0); | |
13700 | SELF_CHECK ((memaddr / 2) < m_insns_size); | |
13701 | ||
13702 | store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]); | |
13703 | if (len == 4) | |
13704 | { | |
13705 | store_unsigned_integer (&buf[2], 2, m_endian, | |
13706 | m_insns[memaddr / 2 + 1]); | |
13707 | } | |
13708 | return true; | |
13709 | } | |
13710 | ||
13711 | private: | |
13712 | enum bfd_endian m_endian; | |
13713 | const uint16_t *m_insns; | |
13714 | size_t m_insns_size; | |
13715 | }; | |
13716 | ||
13717 | static void | |
13718 | arm_record_test (void) | |
13719 | { | |
13720 | struct gdbarch_info info; | |
b121eeb9 YQ |
13721 | info.bfd_arch_info = bfd_scan_arch ("arm"); |
13722 | ||
13723 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13724 | ||
13725 | SELF_CHECK (gdbarch != NULL); | |
13726 | ||
13727 | /* 16-bit Thumb instructions. */ | |
13728 | { | |
13729 | insn_decode_record arm_record; | |
13730 | ||
13731 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13732 | arm_record.gdbarch = gdbarch; | |
13733 | ||
13734 | static const uint16_t insns[] = { | |
13735 | /* db b2 uxtb r3, r3 */ | |
13736 | 0xb2db, | |
13737 | /* cd 58 ldr r5, [r1, r3] */ | |
13738 | 0x58cd, | |
13739 | }; | |
13740 | ||
13741 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13742 | instruction_reader_thumb reader (endian, insns); | |
13743 | int ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13744 | THUMB_INSN_SIZE_BYTES); | |
13745 | ||
13746 | SELF_CHECK (ret == 0); | |
13747 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13748 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13749 | SELF_CHECK (arm_record.arm_regs[0] == 3); | |
13750 | ||
13751 | arm_record.this_addr += 2; | |
13752 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, | |
13753 | THUMB_INSN_SIZE_BYTES); | |
13754 | ||
13755 | SELF_CHECK (ret == 0); | |
13756 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13757 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13758 | SELF_CHECK (arm_record.arm_regs[0] == 5); | |
13759 | } | |
13760 | ||
13761 | /* 32-bit Thumb-2 instructions. */ | |
13762 | { | |
13763 | insn_decode_record arm_record; | |
13764 | ||
13765 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13766 | arm_record.gdbarch = gdbarch; | |
13767 | ||
13768 | static const uint16_t insns[] = { | |
13769 | /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ | |
13770 | 0xee1d, 0x7f70, | |
13771 | }; | |
13772 | ||
13773 | enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); | |
13774 | instruction_reader_thumb reader (endian, insns); | |
13775 | int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, | |
13776 | THUMB2_INSN_SIZE_BYTES); | |
13777 | ||
13778 | SELF_CHECK (ret == 0); | |
13779 | SELF_CHECK (arm_record.mem_rec_count == 0); | |
13780 | SELF_CHECK (arm_record.reg_rec_count == 1); | |
13781 | SELF_CHECK (arm_record.arm_regs[0] == 7); | |
13782 | } | |
13783 | } | |
9ecab40c SM |
13784 | |
13785 | /* Instruction reader from manually cooked instruction sequences. */ | |
13786 | ||
13787 | class test_arm_instruction_reader : public arm_instruction_reader | |
13788 | { | |
13789 | public: | |
13790 | explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns) | |
13791 | : m_insns (insns) | |
13792 | {} | |
13793 | ||
13794 | uint32_t read (CORE_ADDR memaddr, enum bfd_endian byte_order) const override | |
13795 | { | |
13796 | SELF_CHECK (memaddr % 4 == 0); | |
13797 | SELF_CHECK (memaddr / 4 < m_insns.size ()); | |
13798 | ||
13799 | return m_insns[memaddr / 4]; | |
13800 | } | |
13801 | ||
13802 | private: | |
13803 | const gdb::array_view<const uint32_t> m_insns; | |
13804 | }; | |
13805 | ||
13806 | static void | |
13807 | arm_analyze_prologue_test () | |
13808 | { | |
13809 | for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG}) | |
13810 | { | |
13811 | struct gdbarch_info info; | |
9ecab40c SM |
13812 | info.byte_order = endianness; |
13813 | info.byte_order_for_code = endianness; | |
13814 | info.bfd_arch_info = bfd_scan_arch ("arm"); | |
13815 | ||
13816 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
13817 | ||
13818 | SELF_CHECK (gdbarch != NULL); | |
13819 | ||
13820 | /* The "sub" instruction contains an immediate value rotate count of 0, | |
13821 | which resulted in a 32-bit shift of a 32-bit value, caught by | |
13822 | UBSan. */ | |
13823 | const uint32_t insns[] = { | |
13824 | 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */ | |
13825 | 0xe1a05000, /* mov r5, r0 */ | |
13826 | 0xe5903020, /* ldr r3, [r0, #32] */ | |
13827 | 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */ | |
13828 | }; | |
13829 | ||
13830 | test_arm_instruction_reader mem_reader (insns); | |
13831 | arm_prologue_cache cache; | |
13832 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
13833 | ||
13834 | arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); | |
13835 | } | |
13836 | } | |
13837 | ||
b121eeb9 YQ |
13838 | } // namespace selftests |
13839 | #endif /* GDB_SELF_TEST */ | |
72508ac0 PO |
13840 | |
13841 | /* Cleans up local record registers and memory allocations. */ | |
13842 | ||
13843 | static void | |
13844 | deallocate_reg_mem (insn_decode_record *record) | |
13845 | { | |
13846 | xfree (record->arm_regs); | |
13847 | xfree (record->arm_mems); | |
13848 | } | |
13849 | ||
13850 | ||
01e57735 | 13851 | /* Parse the current instruction and record the values of the registers and |
72508ac0 PO |
13852 | memory that will be changed in current instruction to record_arch_list". |
13853 | Return -1 if something is wrong. */ | |
13854 | ||
13855 | int | |
01e57735 YQ |
13856 | arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
13857 | CORE_ADDR insn_addr) | |
72508ac0 PO |
13858 | { |
13859 | ||
72508ac0 PO |
13860 | uint32_t no_of_rec = 0; |
13861 | uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ | |
13862 | ULONGEST t_bit = 0, insn_id = 0; | |
13863 | ||
13864 | ULONGEST u_regval = 0; | |
13865 | ||
13866 | insn_decode_record arm_record; | |
13867 | ||
13868 | memset (&arm_record, 0, sizeof (insn_decode_record)); | |
13869 | arm_record.regcache = regcache; | |
13870 | arm_record.this_addr = insn_addr; | |
13871 | arm_record.gdbarch = gdbarch; | |
13872 | ||
13873 | ||
13874 | if (record_debug > 1) | |
13875 | { | |
6cb06a8c TT |
13876 | gdb_printf (gdb_stdlog, "Process record: arm_process_record " |
13877 | "addr = %s\n", | |
13878 | paddress (gdbarch, arm_record.this_addr)); | |
72508ac0 PO |
13879 | } |
13880 | ||
728a7913 YQ |
13881 | instruction_reader reader; |
13882 | if (extract_arm_insn (reader, &arm_record, 2)) | |
72508ac0 PO |
13883 | { |
13884 | if (record_debug) | |
01e57735 | 13885 | { |
6cb06a8c TT |
13886 | gdb_printf (gdb_stdlog, |
13887 | _("Process record: error reading memory at " | |
13888 | "addr %s len = %d.\n"), | |
13889 | paddress (arm_record.gdbarch, | |
13890 | arm_record.this_addr), 2); | |
01e57735 | 13891 | } |
72508ac0 PO |
13892 | return -1; |
13893 | } | |
13894 | ||
13895 | /* Check the insn, whether it is thumb or arm one. */ | |
13896 | ||
13897 | t_bit = arm_psr_thumb_bit (arm_record.gdbarch); | |
13898 | regcache_raw_read_unsigned (arm_record.regcache, ARM_PS_REGNUM, &u_regval); | |
13899 | ||
13900 | ||
13901 | if (!(u_regval & t_bit)) | |
13902 | { | |
13903 | /* We are decoding arm insn. */ | |
728a7913 | 13904 | ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES); |
72508ac0 PO |
13905 | } |
13906 | else | |
13907 | { | |
13908 | insn_id = bits (arm_record.arm_insn, 11, 15); | |
13909 | /* is it thumb2 insn? */ | |
13910 | if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) | |
01e57735 | 13911 | { |
728a7913 | 13912 | ret = decode_insn (reader, &arm_record, THUMB2_RECORD, |
01e57735 YQ |
13913 | THUMB2_INSN_SIZE_BYTES); |
13914 | } | |
72508ac0 | 13915 | else |
01e57735 YQ |
13916 | { |
13917 | /* We are decoding thumb insn. */ | |
728a7913 YQ |
13918 | ret = decode_insn (reader, &arm_record, THUMB_RECORD, |
13919 | THUMB_INSN_SIZE_BYTES); | |
01e57735 | 13920 | } |
72508ac0 PO |
13921 | } |
13922 | ||
13923 | if (0 == ret) | |
13924 | { | |
13925 | /* Record registers. */ | |
25ea693b | 13926 | record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); |
72508ac0 | 13927 | if (arm_record.arm_regs) |
01e57735 YQ |
13928 | { |
13929 | for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) | |
13930 | { | |
13931 | if (record_full_arch_list_add_reg | |
25ea693b | 13932 | (arm_record.regcache , arm_record.arm_regs[no_of_rec])) |
01e57735 YQ |
13933 | ret = -1; |
13934 | } | |
13935 | } | |
72508ac0 PO |
13936 | /* Record memories. */ |
13937 | if (arm_record.arm_mems) | |
01e57735 YQ |
13938 | { |
13939 | for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) | |
13940 | { | |
13941 | if (record_full_arch_list_add_mem | |
13942 | ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, | |
25ea693b | 13943 | arm_record.arm_mems[no_of_rec].len)) |
01e57735 YQ |
13944 | ret = -1; |
13945 | } | |
13946 | } | |
72508ac0 | 13947 | |
25ea693b | 13948 | if (record_full_arch_list_add_end ()) |
01e57735 | 13949 | ret = -1; |
72508ac0 PO |
13950 | } |
13951 | ||
13952 | ||
13953 | deallocate_reg_mem (&arm_record); | |
13954 | ||
13955 | return ret; | |
13956 | } | |
d105cce5 AH |
13957 | |
13958 | /* See arm-tdep.h. */ | |
13959 | ||
13960 | const target_desc * | |
13961 | arm_read_description (arm_fp_type fp_type) | |
13962 | { | |
13963 | struct target_desc *tdesc = tdesc_arm_list[fp_type]; | |
13964 | ||
13965 | if (tdesc == nullptr) | |
13966 | { | |
13967 | tdesc = arm_create_target_description (fp_type); | |
13968 | tdesc_arm_list[fp_type] = tdesc; | |
13969 | } | |
13970 | ||
13971 | return tdesc; | |
13972 | } | |
13973 | ||
13974 | /* See arm-tdep.h. */ | |
13975 | ||
13976 | const target_desc * | |
13977 | arm_read_mprofile_description (arm_m_profile_type m_type) | |
13978 | { | |
13979 | struct target_desc *tdesc = tdesc_arm_mprofile_list[m_type]; | |
13980 | ||
13981 | if (tdesc == nullptr) | |
13982 | { | |
13983 | tdesc = arm_create_mprofile_target_description (m_type); | |
13984 | tdesc_arm_mprofile_list[m_type] = tdesc; | |
13985 | } | |
13986 | ||
13987 | return tdesc; | |
13988 | } |