]> git.ipfire.org Git - thirdparty/qemu.git/blame - hw/sd/sdhci.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sdhci: convert the DPRINT() calls into trace events
[thirdparty/qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
0430891c 25#include "qemu/osdep.h"
b635d98c 26#include "qapi/error.h"
83c9f4ca 27#include "hw/hw.h"
fa1d36df 28#include "sysemu/block-backend.h"
d7dfca08
IM		 29#include "sysemu/blockdev.h"
30#include "sysemu/dma.h"
31#include "qemu/timer.h"
d7dfca08 32#include "qemu/bitops.h"
f82a0f44 33#include "hw/sd/sdhci.h"
637d23be 34#include "sdhci-internal.h"
8b7455c7 35#include "qapi/error.h"
03dd024f 36#include "qemu/log.h"
8be487d8 37#include "trace.h"
d7dfca08 38
40bbc194
PM		 39#define TYPE_SDHCI_BUS "sdhci-bus"
40#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
41
d7dfca08
IM		 42/* Default SD/MMC host controller features information, which will be
43 * presented in CAPABILITIES register of generic SD host controller at reset.
44 * If not stated otherwise:
45 * 0 - not supported, 1 - supported, other - prohibited.
46 */
47#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
48#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
49#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
50#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
51#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
52#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
53#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
54#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
55#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
56/* Maximum host controller R/W buffers size
57 * Possible values: 512, 1024, 2048 bytes */
58#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
59/* Maximum clock frequency for SDclock in MHz
60 * value in range 10-63 MHz, 0 - not defined */
c7ff8daa 61#define SDHC_CAPAB_BASECLKFREQ 52ul
d7dfca08
IM		 62#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
63/* Timeout clock frequency 1-63, 0 - not defined */
c7ff8daa 64#define SDHC_CAPAB_TOCLKFREQ 52ul
d7dfca08
IM		 65
66/* Now check all parameters and calculate CAPABILITIES REGISTER value */
67#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
68 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
69 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
70 SDHC_CAPAB_TOUNIT > 1
71#error Capabilities features can have value 0 or 1 only!
72#endif
73
74#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
75#define MAX_BLOCK_LENGTH 0ul
76#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
77#define MAX_BLOCK_LENGTH 1ul
78#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
79#define MAX_BLOCK_LENGTH 2ul
80#else
81#error Max host controller block size can have value 512, 1024 or 2048 only!
82#endif
83
84#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
85 SDHC_CAPAB_BASECLKFREQ > 63
86#error SDclock frequency can have value in range 0, 10-63 only!
87#endif
88
89#if SDHC_CAPAB_TOCLKFREQ > 63
90#error Timeout clock frequency can have value in range 0-63 only!
91#endif
92
93#define SDHC_CAPAB_REG_DEFAULT \
94 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
95 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
96 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
97 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
98 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
99 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
100 (SDHC_CAPAB_TOCLKFREQ))
101
8b20aefa 102#define MASK_TRNMOD 0x0037
d7dfca08
IM		 103#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
104
105static uint8_t sdhci_slotint(SDHCIState *s)
106{
107 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
108 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
109 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
110}
111
112static inline void sdhci_update_irq(SDHCIState *s)
113{
114 qemu_set_irq(s->irq, sdhci_slotint(s));
115}
116
117static void sdhci_raise_insertion_irq(void *opaque)
118{
119 SDHCIState *s = (SDHCIState *)opaque;
120
121 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 122 timer_mod(s->insert_timer,
123 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 124 } else {
125 s->prnsts = 0x1ff0000;
126 if (s->norintstsen & SDHC_NISEN_INSERT) {
127 s->norintsts |= SDHC_NIS_INSERT;
128 }
129 sdhci_update_irq(s);
130 }
131}
132
40bbc194 133static void sdhci_set_inserted(DeviceState *dev, bool level)
d7dfca08 134{
40bbc194 135 SDHCIState *s = (SDHCIState *)dev;
d7dfca08 136
8be487d8 137 trace_sdhci_set_inserted(level ? "insert" : "eject");
d7dfca08
IM		 138 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
139 /* Give target some time to notice card ejection */
bc72ad67
AB		 140 timer_mod(s->insert_timer,
141 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 142 } else {
143 if (level) {
144 s->prnsts = 0x1ff0000;
145 if (s->norintstsen & SDHC_NISEN_INSERT) {
146 s->norintsts |= SDHC_NIS_INSERT;
147 }
148 } else {
149 s->prnsts = 0x1fa0000;
150 s->pwrcon &= ~SDHC_POWER_ON;
151 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
152 if (s->norintstsen & SDHC_NISEN_REMOVE) {
153 s->norintsts |= SDHC_NIS_REMOVE;
154 }
155 }
156 sdhci_update_irq(s);
157 }
158}
159
40bbc194 160static void sdhci_set_readonly(DeviceState *dev, bool level)
d7dfca08 161{
40bbc194 162 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 163
164 if (level) {
165 s->prnsts &= ~SDHC_WRITE_PROTECT;
166 } else {
167 /* Write enabled */
168 s->prnsts |= SDHC_WRITE_PROTECT;
169 }
170}
171
172static void sdhci_reset(SDHCIState *s)
173{
40bbc194
PM		 174 DeviceState *dev = DEVICE(s);
175
bc72ad67
AB		 176 timer_del(s->insert_timer);
177 timer_del(s->transfer_timer);
d7dfca08
IM		 178 /* Set all registers to 0. Capabilities registers are not cleared
179 * and assumed to always preserve their value, given to them during
180 * initialization */
181 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
182
5c1bc9a2
AB		 183 /* Reset other state based on current card insertion/readonly status */
184 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
185 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
40bbc194 186
d7dfca08
IM		 187 s->data_count = 0;
188 s->stopped_state = sdhc_not_stopped;
0a7ac9f9 189 s->pending_insert_state = false;
d7dfca08
IM		 190}
191
8b41c305
PM		 192static void sdhci_poweron_reset(DeviceState *dev)
193{
194 /* QOM (ie power-on) reset. This is identical to reset
195 * commanded via device register apart from handling of the
196 * 'pending insert on powerup' quirk.
197 */
198 SDHCIState *s = (SDHCIState *)dev;
199
200 sdhci_reset(s);
201
202 if (s->pending_insert_quirk) {
203 s->pending_insert_state = true;
204 }
205}
206
d368ba43 207static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 208
209static void sdhci_send_command(SDHCIState *s)
210{
211 SDRequest request;
212 uint8_t response[16];
213 int rlen;
214
215 s->errintsts = 0;
216 s->acmd12errsts = 0;
217 request.cmd = s->cmdreg >> 8;
218 request.arg = s->argument;
8be487d8
PMD		 219
220 trace_sdhci_send_command(request.cmd, request.arg);
40bbc194 221 rlen = sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 222
223 if (s->cmdreg & SDHC_CMD_RESPONSE) {
224 if (rlen == 4) {
225 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
226 (response[2] << 8) | response[3];
227 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
8be487d8 228 trace_sdhci_response4(s->rspreg[0]);
d7dfca08
IM		 229 } else if (rlen == 16) {
230 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
231 (response[13] << 8) | response[14];
232 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) |
233 (response[9] << 8) | response[10];
234 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) |
235 (response[5] << 8) | response[6];
236 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
237 response[2];
8be487d8
PMD		 238 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
239 s->rspreg[1], s->rspreg[0]);
d7dfca08 240 } else {
8be487d8 241 trace_sdhci_error("timeout waiting for command response");
d7dfca08
IM		 242 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
243 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
244 s->norintsts |= SDHC_NIS_ERR;
245 }
246 }
247
248 if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
249 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
250 s->norintsts |= SDHC_NIS_TRSCMP;
251 }
d7dfca08
IM		 252 }
253
254 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
255 s->norintsts |= SDHC_NIS_CMDCMP;
256 }
257
258 sdhci_update_irq(s);
259
260 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 261 s->data_count = 0;
d368ba43 262 sdhci_data_transfer(s);
d7dfca08
IM		 263 }
264}
265
266static void sdhci_end_transfer(SDHCIState *s)
267{
268 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
269 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
270 SDRequest request;
271 uint8_t response[16];
272
273 request.cmd = 0x0C;
274 request.arg = 0;
8be487d8 275 trace_sdhci_end_transfer(request.cmd, request.arg);
40bbc194 276 sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 277 /* Auto CMD12 response goes to the upper Response register */
278 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
279 (response[2] << 8) | response[3];
280 }
281
282 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
283 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
284 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
285
286 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
287 s->norintsts |= SDHC_NIS_TRSCMP;
288 }
289
290 sdhci_update_irq(s);
291}
292
293/*
294 * Programmed i/o data transfer
295 */
296
297/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
298static void sdhci_read_block_from_card(SDHCIState *s)
299{
300 int index = 0;
301
302 if ((s->trnmod & SDHC_TRNS_MULTI) &&
303 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
304 return;
305 }
306
307 for (index = 0; index < (s->blksize & 0x0fff); index++) {
40bbc194 308 s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 309 }
310
311 /* New data now available for READ through Buffer Port Register */
312 s->prnsts |= SDHC_DATA_AVAILABLE;
313 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
314 s->norintsts |= SDHC_NIS_RBUFRDY;
315 }
316
317 /* Clear DAT line active status if that was the last block */
318 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
319 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
320 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
321 }
322
323 /* If stop at block gap request was set and it's not the last block of
324 * data - generate Block Event interrupt */
325 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
326 s->blkcnt != 1) {
327 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
328 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
329 s->norintsts |= SDHC_EIS_BLKGAP;
330 }
331 }
332
333 sdhci_update_irq(s);
334}
335
336/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
337static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
338{
339 uint32_t value = 0;
340 int i;
341
342 /* first check that a valid data exists in host controller input buffer */
343 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
8be487d8 344 trace_sdhci_error("read from empty buffer");
d7dfca08
IM		 345 return 0;
346 }
347
348 for (i = 0; i < size; i++) {
349 value |= s->fifo_buffer[s->data_count] << i * 8;
350 s->data_count++;
351 /* check if we've read all valid data (blksize bytes) from buffer */
352 if ((s->data_count) >= (s->blksize & 0x0fff)) {
8be487d8 353 trace_sdhci_read_dataport(s->data_count);
d7dfca08
IM		 354 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
355 s->data_count = 0; /* next buff read must start at position [0] */
356
357 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
358 s->blkcnt--;
359 }
360
361 /* if that was the last block of data */
362 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
363 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
364 /* stop at gap request */
365 (s->stopped_state == sdhc_gap_read &&
366 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 367 sdhci_end_transfer(s);
d7dfca08 368 } else { /* if there are more data, read next block from card */
d368ba43 369 sdhci_read_block_from_card(s);
d7dfca08
IM		 370 }
371 break;
372 }
373 }
374
375 return value;
376}
377
378/* Write data from host controller FIFO to card */
379static void sdhci_write_block_to_card(SDHCIState *s)
380{
381 int index = 0;
382
383 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
384 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
385 s->norintsts |= SDHC_NIS_WBUFRDY;
386 }
387 sdhci_update_irq(s);
388 return;
389 }
390
391 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
392 if (s->blkcnt == 0) {
393 return;
394 } else {
395 s->blkcnt--;
396 }
397 }
398
399 for (index = 0; index < (s->blksize & 0x0fff); index++) {
40bbc194 400 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
d7dfca08
IM		 401 }
402
403 /* Next data can be written through BUFFER DATORT register */
404 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 405
406 /* Finish transfer if that was the last block of data */
407 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
408 ((s->trnmod & SDHC_TRNS_MULTI) &&
409 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 410 sdhci_end_transfer(s);
dcdb4cd8
PC		 411 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
412 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 413 }
414
415 /* Generate Block Gap Event if requested and if not the last block */
416 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
417 s->blkcnt > 0) {
418 s->prnsts &= ~SDHC_DOING_WRITE;
419 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
420 s->norintsts |= SDHC_EIS_BLKGAP;
421 }
d368ba43 422 sdhci_end_transfer(s);
d7dfca08
IM		 423 }
424
425 sdhci_update_irq(s);
426}
427
428/* Write @size bytes of @value data to host controller @s Buffer Data Port
429 * register */
430static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
431{
432 unsigned i;
433
434 /* Check that there is free space left in a buffer */
435 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
8be487d8 436 trace_sdhci_error("Can't write to data buffer: buffer full");
d7dfca08
IM		 437 return;
438 }
439
440 for (i = 0; i < size; i++) {
441 s->fifo_buffer[s->data_count] = value & 0xFF;
442 s->data_count++;
443 value >>= 8;
444 if (s->data_count >= (s->blksize & 0x0fff)) {
8be487d8 445 trace_sdhci_write_dataport(s->data_count);
d7dfca08
IM		 446 s->data_count = 0;
447 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
448 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 449 sdhci_write_block_to_card(s);
d7dfca08
IM		 450 }
451 }
452 }
453}
454
455/*
456 * Single DMA data transfer
457 */
458
459/* Multi block SDMA transfer */
460static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
461{
462 bool page_aligned = false;
463 unsigned int n, begin;
464 const uint16_t block_size = s->blksize & 0x0fff;
465 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
466 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
467
6e86d903
PP		 468 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
469 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
470 return;
471 }
472
d7dfca08
IM		 473 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
474 * possible stop at page boundary if initial address is not page aligned,
475 * allow them to work properly */
476 if ((s->sdmasysad % boundary_chk) == 0) {
477 page_aligned = true;
478 }
479
480 if (s->trnmod & SDHC_TRNS_READ) {
481 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
482 SDHC_DAT_LINE_ACTIVE;
483 while (s->blkcnt) {
484 if (s->data_count == 0) {
485 for (n = 0; n < block_size; n++) {
40bbc194 486 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 487 }
488 }
489 begin = s->data_count;
490 if (((boundary_count + begin) < block_size) && page_aligned) {
491 s->data_count = boundary_count + begin;
492 boundary_count = 0;
493 } else {
494 s->data_count = block_size;
495 boundary_count -= block_size - begin;
496 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
497 s->blkcnt--;
498 }
499 }
df32fd1c 500 dma_memory_write(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 501 &s->fifo_buffer[begin], s->data_count - begin);
502 s->sdmasysad += s->data_count - begin;
503 if (s->data_count == block_size) {
504 s->data_count = 0;
505 }
506 if (page_aligned && boundary_count == 0) {
507 break;
508 }
509 }
510 } else {
511 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
512 SDHC_DAT_LINE_ACTIVE;
513 while (s->blkcnt) {
514 begin = s->data_count;
515 if (((boundary_count + begin) < block_size) && page_aligned) {
516 s->data_count = boundary_count + begin;
517 boundary_count = 0;
518 } else {
519 s->data_count = block_size;
520 boundary_count -= block_size - begin;
521 }
df32fd1c 522 dma_memory_read(&address_space_memory, s->sdmasysad,
42922105 523 &s->fifo_buffer[begin], s->data_count - begin);
d7dfca08
IM		 524 s->sdmasysad += s->data_count - begin;
525 if (s->data_count == block_size) {
526 for (n = 0; n < block_size; n++) {
40bbc194 527 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 528 }
529 s->data_count = 0;
530 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
531 s->blkcnt--;
532 }
533 }
534 if (page_aligned && boundary_count == 0) {
535 break;
536 }
537 }
538 }
539
540 if (s->blkcnt == 0) {
d368ba43 541 sdhci_end_transfer(s);
d7dfca08
IM		 542 } else {
543 if (s->norintstsen & SDHC_NISEN_DMA) {
544 s->norintsts |= SDHC_NIS_DMA;
545 }
546 sdhci_update_irq(s);
547 }
548}
549
550/* single block SDMA transfer */
d7dfca08
IM		 551static void sdhci_sdma_transfer_single_block(SDHCIState *s)
552{
553 int n;
554 uint32_t datacnt = s->blksize & 0x0fff;
555
556 if (s->trnmod & SDHC_TRNS_READ) {
557 for (n = 0; n < datacnt; n++) {
40bbc194 558 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08 559 }
df32fd1c 560 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 561 datacnt);
562 } else {
df32fd1c 563 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 564 datacnt);
565 for (n = 0; n < datacnt; n++) {
40bbc194 566 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 567 }
568 }
241999bf 569 s->blkcnt--;
d7dfca08 570
d368ba43 571 sdhci_end_transfer(s);
d7dfca08
IM		 572}
573
574typedef struct ADMADescr {
575 hwaddr addr;
576 uint16_t length;
577 uint8_t attr;
578 uint8_t incr;
579} ADMADescr;
580
581static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
582{
583 uint32_t adma1 = 0;
584 uint64_t adma2 = 0;
585 hwaddr entry_addr = (hwaddr)s->admasysaddr;
586 switch (SDHC_DMA_TYPE(s->hostctl)) {
587 case SDHC_CTRL_ADMA2_32:
df32fd1c 588 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
d7dfca08
IM		 589 sizeof(adma2));
590 adma2 = le64_to_cpu(adma2);
591 /* The spec does not specify endianness of descriptor table.
592 * We currently assume that it is LE.
593 */
594 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
595 dscr->length = (uint16_t)extract64(adma2, 16, 16);
596 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
597 dscr->incr = 8;
598 break;
599 case SDHC_CTRL_ADMA1_32:
df32fd1c 600 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
d7dfca08
IM		 601 sizeof(adma1));
602 adma1 = le32_to_cpu(adma1);
603 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
604 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
605 dscr->incr = 4;
606 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
607 dscr->length = (uint16_t)extract32(adma1, 12, 16);
608 } else {
609 dscr->length = 4096;
610 }
611 break;
612 case SDHC_CTRL_ADMA2_64:
df32fd1c 613 dma_memory_read(&address_space_memory, entry_addr,
d7dfca08 614 (uint8_t *)(&dscr->attr), 1);
df32fd1c 615 dma_memory_read(&address_space_memory, entry_addr + 2,
d7dfca08
IM		 616 (uint8_t *)(&dscr->length), 2);
617 dscr->length = le16_to_cpu(dscr->length);
df32fd1c 618 dma_memory_read(&address_space_memory, entry_addr + 4,
d7dfca08
IM		 619 (uint8_t *)(&dscr->addr), 8);
620 dscr->attr = le64_to_cpu(dscr->attr);
621 dscr->attr &= 0xfffffff8;
622 dscr->incr = 12;
623 break;
624 }
625}
626
627/* Advanced DMA data transfer */
628
629static void sdhci_do_adma(SDHCIState *s)
630{
631 unsigned int n, begin, length;
632 const uint16_t block_size = s->blksize & 0x0fff;
8be487d8 633 ADMADescr dscr = {};
d7dfca08
IM		 634 int i;
635
636 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
637 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
638
639 get_adma_description(s, &dscr);
8be487d8 640 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
d7dfca08
IM		 641
642 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
643 /* Indicate that error occurred in ST_FDS state */
644 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
645 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
646
647 /* Generate ADMA error interrupt */
648 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
649 s->errintsts |= SDHC_EIS_ADMAERR;
650 s->norintsts |= SDHC_NIS_ERR;
651 }
652
653 sdhci_update_irq(s);
654 return;
655 }
656
657 length = dscr.length ? dscr.length : 65536;
658
659 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
660 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
661
662 if (s->trnmod & SDHC_TRNS_READ) {
663 while (length) {
664 if (s->data_count == 0) {
665 for (n = 0; n < block_size; n++) {
40bbc194 666 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 667 }
668 }
669 begin = s->data_count;
670 if ((length + begin) < block_size) {
671 s->data_count = length + begin;
672 length = 0;
673 } else {
674 s->data_count = block_size;
675 length -= block_size - begin;
676 }
df32fd1c 677 dma_memory_write(&address_space_memory, dscr.addr,
d7dfca08
IM		 678 &s->fifo_buffer[begin],
679 s->data_count - begin);
680 dscr.addr += s->data_count - begin;
681 if (s->data_count == block_size) {
682 s->data_count = 0;
683 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
684 s->blkcnt--;
685 if (s->blkcnt == 0) {
686 break;
687 }
688 }
689 }
690 }
691 } else {
692 while (length) {
693 begin = s->data_count;
694 if ((length + begin) < block_size) {
695 s->data_count = length + begin;
696 length = 0;
697 } else {
698 s->data_count = block_size;
699 length -= block_size - begin;
700 }
df32fd1c 701 dma_memory_read(&address_space_memory, dscr.addr,
9db11cef
PC		 702 &s->fifo_buffer[begin],
703 s->data_count - begin);
d7dfca08
IM		 704 dscr.addr += s->data_count - begin;
705 if (s->data_count == block_size) {
706 for (n = 0; n < block_size; n++) {
40bbc194 707 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 708 }
709 s->data_count = 0;
710 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
711 s->blkcnt--;
712 if (s->blkcnt == 0) {
713 break;
714 }
715 }
716 }
717 }
718 }
719 s->admasysaddr += dscr.incr;
720 break;
721 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
722 s->admasysaddr = dscr.addr;
8be487d8 723 trace_sdhci_adma("link", s->admasysaddr);
d7dfca08
IM		 724 break;
725 default:
726 s->admasysaddr += dscr.incr;
727 break;
728 }
729
1d32c26f 730 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
8be487d8 731 trace_sdhci_adma("interrupt", s->admasysaddr);
1d32c26f
PC		 732 if (s->norintstsen & SDHC_NISEN_DMA) {
733 s->norintsts |= SDHC_NIS_DMA;
734 }
735
736 sdhci_update_irq(s);
737 }
738
d7dfca08
IM		 739 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
740 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
741 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
8be487d8 742 trace_sdhci_adma_transfer_completed();
d7dfca08
IM		 743 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
744 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
745 s->blkcnt != 0)) {
8be487d8 746 trace_sdhci_error("SD/MMC host ADMA length mismatch");
d7dfca08
IM		 747 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
748 SDHC_ADMAERR_STATE_ST_TFR;
749 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
8be487d8 750 trace_sdhci_error("Set ADMA error flag");
d7dfca08
IM		 751 s->errintsts |= SDHC_EIS_ADMAERR;
752 s->norintsts |= SDHC_NIS_ERR;
753 }
754
755 sdhci_update_irq(s);
756 }
d368ba43 757 sdhci_end_transfer(s);
d7dfca08
IM		 758 return;
759 }
760
d7dfca08
IM		 761 }
762
085d8134 763 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 764 timer_mod(s->transfer_timer,
765 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 766}
767
768/* Perform data transfer according to controller configuration */
769
d368ba43 770static void sdhci_data_transfer(void *opaque)
d7dfca08 771{
d368ba43 772 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 773
774 if (s->trnmod & SDHC_TRNS_DMA) {
775 switch (SDHC_DMA_TYPE(s->hostctl)) {
776 case SDHC_CTRL_SDMA:
d7dfca08 777 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 778 sdhci_sdma_transfer_single_block(s);
d7dfca08 779 } else {
d368ba43 780 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 781 }
782
783 break;
784 case SDHC_CTRL_ADMA1_32:
785 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
8be487d8 786 trace_sdhci_error("ADMA1 not supported");
d7dfca08
IM		 787 break;
788 }
789
d368ba43 790 sdhci_do_adma(s);
d7dfca08
IM		 791 break;
792 case SDHC_CTRL_ADMA2_32:
793 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
8be487d8 794 trace_sdhci_error("ADMA2 not supported");
d7dfca08
IM		 795 break;
796 }
797
d368ba43 798 sdhci_do_adma(s);
d7dfca08
IM		 799 break;
800 case SDHC_CTRL_ADMA2_64:
801 if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
802 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
8be487d8 803 trace_sdhci_error("64 bit ADMA not supported");
d7dfca08
IM		 804 break;
805 }
806
d368ba43 807 sdhci_do_adma(s);
d7dfca08
IM		 808 break;
809 default:
8be487d8 810 trace_sdhci_error("Unsupported DMA type");
d7dfca08
IM		 811 break;
812 }
813 } else {
40bbc194 814 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
d7dfca08
IM		 815 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
816 SDHC_DAT_LINE_ACTIVE;
d368ba43 817 sdhci_read_block_from_card(s);
d7dfca08
IM		 818 } else {
819 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
820 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 821 sdhci_write_block_to_card(s);
d7dfca08
IM		 822 }
823 }
824}
825
826static bool sdhci_can_issue_command(SDHCIState *s)
827{
6890a695 828 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
d7dfca08
IM		 829 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
830 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
831 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
832 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
833 return false;
834 }
835
836 return true;
837}
838
839/* The Buffer Data Port register must be accessed in sequential and
840 * continuous manner */
841static inline bool
842sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
843{
844 if ((s->data_count & 0x3) != byte_num) {
8be487d8
PMD		 845 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
846 "is prohibited\n");
d7dfca08
IM		 847 return false;
848 }
849 return true;
850}
851
d368ba43 852static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 853{
d368ba43 854 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 855 uint32_t ret = 0;
856
857 switch (offset & ~0x3) {
858 case SDHC_SYSAD:
859 ret = s->sdmasysad;
860 break;
861 case SDHC_BLKSIZE:
862 ret = s->blksize | (s->blkcnt << 16);
863 break;
864 case SDHC_ARGUMENT:
865 ret = s->argument;
866 break;
867 case SDHC_TRNMOD:
868 ret = s->trnmod | (s->cmdreg << 16);
869 break;
870 case SDHC_RSPREG0 ... SDHC_RSPREG3:
871 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
872 break;
873 case SDHC_BDATA:
874 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 875 ret = sdhci_read_dataport(s, size);
8be487d8 876 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 877 return ret;
878 }
879 break;
880 case SDHC_PRNSTS:
881 ret = s->prnsts;
882 break;
883 case SDHC_HOSTCTL:
884 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
885 (s->wakcon << 24);
886 break;
887 case SDHC_CLKCON:
888 ret = s->clkcon | (s->timeoutcon << 16);
889 break;
890 case SDHC_NORINTSTS:
891 ret = s->norintsts | (s->errintsts << 16);
892 break;
893 case SDHC_NORINTSTSEN:
894 ret = s->norintstsen | (s->errintstsen << 16);
895 break;
896 case SDHC_NORINTSIGEN:
897 ret = s->norintsigen | (s->errintsigen << 16);
898 break;
899 case SDHC_ACMD12ERRSTS:
900 ret = s->acmd12errsts;
901 break;
902 case SDHC_CAPAREG:
903 ret = s->capareg;
904 break;
905 case SDHC_MAXCURR:
906 ret = s->maxcurr;
907 break;
908 case SDHC_ADMAERR:
909 ret = s->admaerr;
910 break;
911 case SDHC_ADMASYSADDR:
912 ret = (uint32_t)s->admasysaddr;
913 break;
914 case SDHC_ADMASYSADDR + 4:
915 ret = (uint32_t)(s->admasysaddr >> 32);
916 break;
917 case SDHC_SLOT_INT_STATUS:
918 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
919 break;
920 default:
00b004b3
PMD		 921 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
922 "not implemented\n", size, offset);
d7dfca08
IM		 923 break;
924 }
925
926 ret >>= (offset & 0x3) * 8;
927 ret &= (1ULL << (size * 8)) - 1;
8be487d8 928 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 929 return ret;
930}
931
932static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
933{
934 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
935 return;
936 }
937 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
938
939 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
940 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
941 if (s->stopped_state == sdhc_gap_read) {
942 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 943 sdhci_read_block_from_card(s);
d7dfca08
IM		 944 } else {
945 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 946 sdhci_write_block_to_card(s);
d7dfca08
IM		 947 }
948 s->stopped_state = sdhc_not_stopped;
949 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
950 if (s->prnsts & SDHC_DOING_READ) {
951 s->stopped_state = sdhc_gap_read;
952 } else if (s->prnsts & SDHC_DOING_WRITE) {
953 s->stopped_state = sdhc_gap_write;
954 }
955 }
956}
957
958static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
959{
960 switch (value) {
961 case SDHC_RESET_ALL:
d368ba43 962 sdhci_reset(s);
d7dfca08
IM		 963 break;
964 case SDHC_RESET_CMD:
965 s->prnsts &= ~SDHC_CMD_INHIBIT;
966 s->norintsts &= ~SDHC_NIS_CMDCMP;
967 break;
968 case SDHC_RESET_DATA:
969 s->data_count = 0;
970 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
971 SDHC_DOING_READ | SDHC_DOING_WRITE |
972 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
973 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
974 s->stopped_state = sdhc_not_stopped;
975 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
976 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
977 break;
978 }
979}
980
981static void
d368ba43 982sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 983{
d368ba43 984 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 985 unsigned shift = 8 * (offset & 0x3);
986 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 987 uint32_t value = val;
d7dfca08
IM		 988 value <<= shift;
989
990 switch (offset & ~0x3) {
991 case SDHC_SYSAD:
992 s->sdmasysad = (s->sdmasysad & mask) | value;
993 MASKED_WRITE(s->sdmasysad, mask, value);
994 /* Writing to last byte of sdmasysad might trigger transfer */
995 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
996 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
45ba9f76
PP		 997 if (s->trnmod & SDHC_TRNS_MULTI) {
998 sdhci_sdma_transfer_multi_blocks(s);
999 } else {
1000 sdhci_sdma_transfer_single_block(s);
1001 }
d7dfca08
IM		 1002 }
1003 break;
1004 case SDHC_BLKSIZE:
1005 if (!TRANSFERRING_DATA(s->prnsts)) {
1006 MASKED_WRITE(s->blksize, mask, value);
1007 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1008 }
9201bb9a
AF		 1009
1010 /* Limit block size to the maximum buffer size */
1011 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1012 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \
1013 "the maximum buffer 0x%x", __func__, s->blksize,
1014 s->buf_maxsz);
1015
1016 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1017 }
1018
d7dfca08
IM		 1019 break;
1020 case SDHC_ARGUMENT:
1021 MASKED_WRITE(s->argument, mask, value);
1022 break;
1023 case SDHC_TRNMOD:
1024 /* DMA can be enabled only if it is supported as indicated by
1025 * capabilities register */
1026 if (!(s->capareg & SDHC_CAN_DO_DMA)) {
1027 value &= ~SDHC_TRNS_DMA;
1028 }
8b20aefa 1029 MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
d7dfca08
IM		 1030 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1031
1032 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1033 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1034 break;
1035 }
1036
d368ba43 1037 sdhci_send_command(s);
d7dfca08
IM		 1038 break;
1039 case SDHC_BDATA:
1040 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1041 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1042 }
1043 break;
1044 case SDHC_HOSTCTL:
1045 if (!(mask & 0xFF0000)) {
1046 sdhci_blkgap_write(s, value >> 16);
1047 }
1048 MASKED_WRITE(s->hostctl, mask, value);
1049 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1050 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1051 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1052 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1053 s->pwrcon &= ~SDHC_POWER_ON;
1054 }
1055 break;
1056 case SDHC_CLKCON:
1057 if (!(mask & 0xFF000000)) {
1058 sdhci_reset_write(s, value >> 24);
1059 }
1060 MASKED_WRITE(s->clkcon, mask, value);
1061 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1062 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1063 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1064 } else {
1065 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1066 }
1067 break;
1068 case SDHC_NORINTSTS:
1069 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1070 value &= ~SDHC_NIS_CARDINT;
1071 }
1072 s->norintsts &= mask | ~value;
1073 s->errintsts &= (mask >> 16) | ~(value >> 16);
1074 if (s->errintsts) {
1075 s->norintsts |= SDHC_NIS_ERR;
1076 } else {
1077 s->norintsts &= ~SDHC_NIS_ERR;
1078 }
1079 sdhci_update_irq(s);
1080 break;
1081 case SDHC_NORINTSTSEN:
1082 MASKED_WRITE(s->norintstsen, mask, value);
1083 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1084 s->norintsts &= s->norintstsen;
1085 s->errintsts &= s->errintstsen;
1086 if (s->errintsts) {
1087 s->norintsts |= SDHC_NIS_ERR;
1088 } else {
1089 s->norintsts &= ~SDHC_NIS_ERR;
1090 }
0a7ac9f9
AB		 1091 /* Quirk for Raspberry Pi: pending card insert interrupt
1092 * appears when first enabled after power on */
1093 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1094 assert(s->pending_insert_quirk);
1095 s->norintsts |= SDHC_NIS_INSERT;
1096 s->pending_insert_state = false;
1097 }
d7dfca08
IM		 1098 sdhci_update_irq(s);
1099 break;
1100 case SDHC_NORINTSIGEN:
1101 MASKED_WRITE(s->norintsigen, mask, value);
1102 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1103 sdhci_update_irq(s);
1104 break;
1105 case SDHC_ADMAERR:
1106 MASKED_WRITE(s->admaerr, mask, value);
1107 break;
1108 case SDHC_ADMASYSADDR:
1109 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1110 (uint64_t)mask)) | (uint64_t)value;
1111 break;
1112 case SDHC_ADMASYSADDR + 4:
1113 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1114 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1115 break;
1116 case SDHC_FEAER:
1117 s->acmd12errsts |= value;
1118 s->errintsts |= (value >> 16) & s->errintstsen;
1119 if (s->acmd12errsts) {
1120 s->errintsts |= SDHC_EIS_CMD12ERR;
1121 }
1122 if (s->errintsts) {
1123 s->norintsts |= SDHC_NIS_ERR;
1124 }
1125 sdhci_update_irq(s);
1126 break;
1127 default:
00b004b3
PMD		 1128 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1129 "not implemented\n", size, offset, value >> shift);
d7dfca08
IM		 1130 break;
1131 }
8be487d8
PMD		 1132 trace_sdhci_access("wr", size << 3, offset, "<-",
1133 value >> shift, value >> shift);
d7dfca08
IM		 1134}
1135
1136static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1137 .read = sdhci_read,
1138 .write = sdhci_write,
d7dfca08
IM		 1139 .valid = {
1140 .min_access_size = 1,
1141 .max_access_size = 4,
1142 .unaligned = false
1143 },
1144 .endianness = DEVICE_LITTLE_ENDIAN,
1145};
1146
1147static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
1148{
1149 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
1150 case 0:
1151 return 512;
1152 case 1:
1153 return 1024;
1154 case 2:
1155 return 2048;
1156 default:
1157 hw_error("SDHC: unsupported value for maximum block size\n");
1158 return 0;
1159 }
1160}
1161
b635d98c
PMD		 1162/* --- qdev common --- */
1163
1164#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
1165 /* Capabilities registers provide information on supported features
1166 * of this specific host controller implementation */ \
1167 DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
1168 DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
1169
40bbc194 1170static void sdhci_initfn(SDHCIState *s)
d7dfca08 1171{
40bbc194
PM		 1172 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1173 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
d7dfca08 1174
bc72ad67 1175 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1176 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
d7dfca08
IM		 1177}
1178
7302dcd6 1179static void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1180{
bc72ad67
AB		 1181 timer_del(s->insert_timer);
1182 timer_free(s->insert_timer);
1183 timer_del(s->transfer_timer);
1184 timer_free(s->transfer_timer);
d7dfca08 1185
012aef07
MA		 1186 g_free(s->fifo_buffer);
1187 s->fifo_buffer = NULL;
d7dfca08
IM		 1188}
1189
25367498
PMD		 1190static void sdhci_common_realize(SDHCIState *s, Error **errp)
1191{
1192 s->buf_maxsz = sdhci_get_fifolen(s);
1193 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1194
1195 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
1196 SDHC_REGISTERS_MAP_SIZE);
1197}
1198
8b7455c7
PMD		 1199static void sdhci_common_unrealize(SDHCIState *s, Error **errp)
1200{
1201 /* This function is expected to be called only once for each class:
1202 * - SysBus: via DeviceClass->unrealize(),
1203 * - PCI: via PCIDeviceClass->exit().
1204 * However to avoid double-free and/or use-after-free we still nullify
1205 * this variable (better safe than sorry!). */
1206 g_free(s->fifo_buffer);
1207 s->fifo_buffer = NULL;
1208}
1209
0a7ac9f9
AB		 1210static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1211{
1212 SDHCIState *s = opaque;
1213
1214 return s->pending_insert_state;
1215}
1216
1217static const VMStateDescription sdhci_pending_insert_vmstate = {
1218 .name = "sdhci/pending-insert",
1219 .version_id = 1,
1220 .minimum_version_id = 1,
1221 .needed = sdhci_pending_insert_vmstate_needed,
1222 .fields = (VMStateField[]) {
1223 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1224 VMSTATE_END_OF_LIST()
1225 },
1226};
1227
d7dfca08
IM		 1228const VMStateDescription sdhci_vmstate = {
1229 .name = "sdhci",
1230 .version_id = 1,
1231 .minimum_version_id = 1,
35d08458 1232 .fields = (VMStateField[]) {
d7dfca08
IM		 1233 VMSTATE_UINT32(sdmasysad, SDHCIState),
1234 VMSTATE_UINT16(blksize, SDHCIState),
1235 VMSTATE_UINT16(blkcnt, SDHCIState),
1236 VMSTATE_UINT32(argument, SDHCIState),
1237 VMSTATE_UINT16(trnmod, SDHCIState),
1238 VMSTATE_UINT16(cmdreg, SDHCIState),
1239 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1240 VMSTATE_UINT32(prnsts, SDHCIState),
1241 VMSTATE_UINT8(hostctl, SDHCIState),
1242 VMSTATE_UINT8(pwrcon, SDHCIState),
1243 VMSTATE_UINT8(blkgap, SDHCIState),
1244 VMSTATE_UINT8(wakcon, SDHCIState),
1245 VMSTATE_UINT16(clkcon, SDHCIState),
1246 VMSTATE_UINT8(timeoutcon, SDHCIState),
1247 VMSTATE_UINT8(admaerr, SDHCIState),
1248 VMSTATE_UINT16(norintsts, SDHCIState),
1249 VMSTATE_UINT16(errintsts, SDHCIState),
1250 VMSTATE_UINT16(norintstsen, SDHCIState),
1251 VMSTATE_UINT16(errintstsen, SDHCIState),
1252 VMSTATE_UINT16(norintsigen, SDHCIState),
1253 VMSTATE_UINT16(errintsigen, SDHCIState),
1254 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1255 VMSTATE_UINT16(data_count, SDHCIState),
1256 VMSTATE_UINT64(admasysaddr, SDHCIState),
1257 VMSTATE_UINT8(stopped_state, SDHCIState),
59046ec2 1258 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
e720677e
PB		 1259 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1260 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08 1261 VMSTATE_END_OF_LIST()
0a7ac9f9
AB		 1262 },
1263 .subsections = (const VMStateDescription*[]) {
1264 &sdhci_pending_insert_vmstate,
1265 NULL
1266 },
d7dfca08
IM		 1267};
1268
1c92c505
PMD		 1269static void sdhci_common_class_init(ObjectClass *klass, void *data)
1270{
1271 DeviceClass *dc = DEVICE_CLASS(klass);
1272
1273 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1274 dc->vmsd = &sdhci_vmstate;
1275 dc->reset = sdhci_poweron_reset;
1276}
1277
b635d98c
PMD		 1278/* --- qdev PCI --- */
1279
5ec911c3 1280static Property sdhci_pci_properties[] = {
b635d98c 1281 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
d7dfca08
IM		 1282 DEFINE_PROP_END_OF_LIST(),
1283};
1284
9af21dbe 1285static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
224d10ff
KC		 1286{
1287 SDHCIState *s = PCI_SDHCI(dev);
25367498
PMD		 1288
1289 sdhci_initfn(s);
1290 sdhci_common_realize(s, errp);
1291 if (errp && *errp) {
1292 return;
1293 }
1294
224d10ff
KC		 1295 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
1296 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
224d10ff 1297 s->irq = pci_allocate_irq(dev);
224d10ff 1298 pci_register_bar(dev, 0, 0, &s->iomem);
224d10ff
KC		 1299}
1300
1301static void sdhci_pci_exit(PCIDevice *dev)
1302{
1303 SDHCIState *s = PCI_SDHCI(dev);
8b7455c7
PMD		 1304
1305 sdhci_common_unrealize(s, &error_abort);
224d10ff
KC		 1306 sdhci_uninitfn(s);
1307}
1308
1309static void sdhci_pci_class_init(ObjectClass *klass, void *data)
1310{
1311 DeviceClass *dc = DEVICE_CLASS(klass);
1312 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1313
9af21dbe 1314 k->realize = sdhci_pci_realize;
224d10ff
KC		 1315 k->exit = sdhci_pci_exit;
1316 k->vendor_id = PCI_VENDOR_ID_REDHAT;
1317 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
1318 k->class_id = PCI_CLASS_SYSTEM_SDHCI;
5ec911c3 1319 dc->props = sdhci_pci_properties;
1c92c505
PMD		 1320
1321 sdhci_common_class_init(klass, data);
224d10ff
KC		 1322}
1323
1324static const TypeInfo sdhci_pci_info = {
1325 .name = TYPE_PCI_SDHCI,
1326 .parent = TYPE_PCI_DEVICE,
1327 .instance_size = sizeof(SDHCIState),
1328 .class_init = sdhci_pci_class_init,
fd3b02c8
EH		 1329 .interfaces = (InterfaceInfo[]) {
1330 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1331 { },
1332 },
224d10ff
KC		 1333};
1334
b635d98c
PMD		 1335/* --- qdev SysBus --- */
1336
5ec911c3 1337static Property sdhci_sysbus_properties[] = {
b635d98c 1338 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
0a7ac9f9
AB		 1339 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1340 false),
5ec911c3
KC		 1341 DEFINE_PROP_END_OF_LIST(),
1342};
1343
7302dcd6
KC		 1344static void sdhci_sysbus_init(Object *obj)
1345{
1346 SDHCIState *s = SYSBUS_SDHCI(obj);
5ec911c3 1347
40bbc194 1348 sdhci_initfn(s);
7302dcd6
KC		 1349}
1350
1351static void sdhci_sysbus_finalize(Object *obj)
1352{
1353 SDHCIState *s = SYSBUS_SDHCI(obj);
1354 sdhci_uninitfn(s);
1355}
1356
1357static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
d7dfca08 1358{
7302dcd6 1359 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08
IM		 1360 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1361
25367498
PMD		 1362 sdhci_common_realize(s, errp);
1363 if (errp && *errp) {
1364 return;
1365 }
1366
d7dfca08 1367 sysbus_init_irq(sbd, &s->irq);
d7dfca08
IM		 1368 sysbus_init_mmio(sbd, &s->iomem);
1369}
1370
8b7455c7
PMD		 1371static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
1372{
1373 SDHCIState *s = SYSBUS_SDHCI(dev);
1374
1375 sdhci_common_unrealize(s, &error_abort);
1376}
1377
7302dcd6 1378static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1379{
1380 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08 1381
5ec911c3 1382 dc->props = sdhci_sysbus_properties;
7302dcd6 1383 dc->realize = sdhci_sysbus_realize;
8b7455c7 1384 dc->unrealize = sdhci_sysbus_unrealize;
1c92c505
PMD		 1385
1386 sdhci_common_class_init(klass, data);
d7dfca08
IM		 1387}
1388
7302dcd6
KC		 1389static const TypeInfo sdhci_sysbus_info = {
1390 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1391 .parent = TYPE_SYS_BUS_DEVICE,
1392 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1393 .instance_init = sdhci_sysbus_init,
1394 .instance_finalize = sdhci_sysbus_finalize,
1395 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1396};
1397
b635d98c
PMD		 1398/* --- qdev bus master --- */
1399
40bbc194
PM		 1400static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1401{
1402 SDBusClass *sbc = SD_BUS_CLASS(klass);
1403
1404 sbc->set_inserted = sdhci_set_inserted;
1405 sbc->set_readonly = sdhci_set_readonly;
1406}
1407
1408static const TypeInfo sdhci_bus_info = {
1409 .name = TYPE_SDHCI_BUS,
1410 .parent = TYPE_SD_BUS,
1411 .instance_size = sizeof(SDBus),
1412 .class_init = sdhci_bus_class_init,
1413};
1414
d7dfca08
IM		 1415static void sdhci_register_types(void)
1416{
224d10ff 1417 type_register_static(&sdhci_pci_info);
7302dcd6 1418 type_register_static(&sdhci_sysbus_info);
40bbc194 1419 type_register_static(&sdhci_bus_info);
d7dfca08
IM		 1420}
1421
1422type_init(sdhci_register_types)
Mirror of https://git.qemu.org/git/qemu.git