[thirdparty/binutils-gdb.git] / sim / m68hc11 / interp.c

/* interp.c -- Simulator for Motorola 68HC11/68HC12
   Copyright (C) 1999-2022 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#include "sim-main.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "sim-options.h"
#include "hw-tree.h"
#include "hw-device.h"
#include "hw-ports.h"
#include "elf32-m68hc1x.h"

#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
#endif

static void sim_get_info (SIM_DESC sd, char *cmd);

struct sim_info_list
{
  const char *name;
  const char *device;
};

struct sim_info_list dev_list_68hc11[] = {
  {"cpu", "/m68hc11"},
  {"timer", "/m68hc11/m68hc11tim"},
  {"sio", "/m68hc11/m68hc11sio"},
  {"spi", "/m68hc11/m68hc11spi"},
  {"eeprom", "/m68hc11/m68hc11eepr"},
  {0, 0}
};

struct sim_info_list dev_list_68hc12[] = {
  {"cpu", "/m68hc12"},
  {"timer", "/m68hc12/m68hc12tim"},
  {"sio", "/m68hc12/m68hc12sio"},
  {"spi", "/m68hc12/m68hc12spi"},
  {"eeprom", "/m68hc12/m68hc12eepr"},
  {0, 0}
};

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);

  sim_state_free (sd);
}

/* Give some information about the simulator.  */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
    {
      int i;
      struct hw *hw_dev;
      struct sim_info_list *dev_list;
      const struct bfd_arch_info *arch;

      arch = STATE_ARCHITECTURE (sd);
      cmd++;

      if (arch->arch == bfd_arch_m68hc11)
        dev_list = dev_list_68hc11;
      else
        dev_list = dev_list_68hc12;

      for (i = 0; dev_list[i].name; i++)
	if (strcmp (cmd, dev_list[i].name) == 0)
	  break;

      if (dev_list[i].name == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	  sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	  return;
	}
      hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
      if (hw_dev == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	  return;
	}
      hw_ioctl (hw_dev, 23, 0);
      return;
    }

  cpu_info (sd, cpu);
  interrupts_info (sd, &M68HC11_SIM_CPU (cpu)->cpu_interrupts);
}


void
sim_board_reset (SIM_DESC sd)
{
  struct hw *hw_cpu;
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  const struct bfd_arch_info *arch;
  const char *cpu_type;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);
  arch = STATE_ARCHITECTURE (sd);

  /*  hw_cpu = sim_hw_parse (sd, "/"); */
  if (arch->arch == bfd_arch_m68hc11)
    {
      m68hc11_cpu->cpu_type = CPU_M6811;
      cpu_type = "/m68hc11";
    }
  else
    {
      m68hc11_cpu->cpu_type = CPU_M6812;
      cpu_type = "/m68hc12";
    }
  
  hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
  if (hw_cpu == 0)
    {
      sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
      return;
    }

  cpu_reset (cpu);
  hw_port_event (hw_cpu, 3, 0);
  cpu_restart (cpu);
}

static int
sim_hw_configure (SIM_DESC sd)
{
  const struct bfd_arch_info *arch;
  struct hw *device_tree;
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  
  arch = STATE_ARCHITECTURE (sd);
  if (arch == 0)
    return 0;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);
  m68hc11_cpu->cpu_configured_arch = arch;
  device_tree = sim_hw_parse (sd, "/");
  if (arch->arch == bfd_arch_m68hc11)
    {
      m68hc11_cpu->cpu_interpretor = cpu_interp_m6811;
      if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	{
	  /* Allocate core managed memory */

	  /* the monitor  */
	  sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
			   /* MONITOR_BASE, MONITOR_SIZE */
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
	  sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
          if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
                               m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc11/use_bank 1");
            }
	}
      if (m68hc11_cpu->cpu_start_mode)
        {
          sim_hw_parse (sd, "/m68hc11/mode %s", m68hc11_cpu->cpu_start_mode);
        }
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
          sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	  sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	  sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	  /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	}
      sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
      m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
    }
  else
    {
      m68hc11_cpu->cpu_interpretor = cpu_interp_m6812;
      if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	{
	  /* Allocate core external memory.  */
	  sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
          if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
                               m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc12/use_bank 1");
            }
	  sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	}

      if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
          sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	  sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	  sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	}

      sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
      m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
    }
  return 1;
}

/* Get the memory bank parameters by looking at the global symbols
   defined by the linker.  */
static int
sim_get_bank_parameters (SIM_DESC sd)
{
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  unsigned size;
  bfd_vma addr;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
  if (addr != -1)
    m68hc11_cpu->bank_start = addr;

  size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
  if (size == -1)
    size = 0;

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
  if (addr != -1)
    m68hc11_cpu->bank_virtual = addr;

  m68hc11_cpu->bank_end = m68hc11_cpu->bank_start + size;
  m68hc11_cpu->bank_shift = 0;
  for (; size > 1; size >>= 1)
    m68hc11_cpu->bank_shift++;

  return 0;
}

static int
sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
{
  sim_cpu *cpu;
  struct m68hc11_sim_cpu *m68hc11_cpu;
  int elf_flags = 0;

  cpu = STATE_CPU (sd, 0);
  m68hc11_cpu = M68HC11_SIM_CPU (cpu);

  if (abfd != NULL)
    {
      asection *s;

      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
        elf_flags = elf_elfheader (abfd)->e_flags;

      m68hc11_cpu->cpu_elf_start = bfd_get_start_address (abfd);
      /* See if any section sets the reset address */
      m68hc11_cpu->cpu_use_elf_start = 1;
      for (s = abfd->sections; s && m68hc11_cpu->cpu_use_elf_start; s = s->next)
        {
          if (s->flags & SEC_LOAD)
            {
              bfd_size_type size;

	      size = bfd_section_size (s);
              if (size > 0)
                {
                  bfd_vma lma;

                  if (STATE_LOAD_AT_LMA_P (sd))
		    lma = bfd_section_lma (s);
                  else
		    lma = bfd_section_vma (s);

                  if (lma <= 0xFFFE && lma+size >= 0x10000)
                    m68hc11_cpu->cpu_use_elf_start = 0;
                }
            }
        }

      if (elf_flags & E_M68HC12_BANKS)
        {
          if (sim_get_bank_parameters (sd) != 0)
            sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
        }
    }

  if (!sim_hw_configure (sd))
    return SIM_RC_FAIL;

  /* reset all state information */
  sim_board_reset (sd);

  return SIM_RC_OK;
}

static sim_cia
m68hc11_pc_get (sim_cpu *cpu)
{
  return cpu_get_pc (cpu);
}

static void
m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
{
  cpu_set_pc (cpu, pc);
}

static int m68hc11_reg_fetch (SIM_CPU *, int, void *, int);
static int m68hc11_reg_store (SIM_CPU *, int, const void *, int);

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
	  bfd *abfd, char * const *argv)
{
  int i;
  SIM_DESC sd;
  sim_cpu *cpu;

  sd = sim_state_alloc (kind, callback);

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* Set default options before parsing user options.  */
  current_target_byte_order = BFD_ENDIAN_BIG;

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m68hc11_sim_cpu))
      != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  cpu = STATE_CPU (sd, 0);

  cpu_initialize (sd, cpu);

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }
  if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }      

  /* CPU specific initialization.  */
  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
    {
      SIM_CPU *cpu = STATE_CPU (sd, i);

      CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
      CPU_REG_STORE (cpu) = m68hc11_reg_store;
      CPU_PC_FETCH (cpu) = m68hc11_pc_get;
      CPU_PC_STORE (cpu) = m68hc11_pc_set;
    }

  return sd;
}

/* Generic implementation of sim_engine_run that works within the
   sim_engine setjmp/longjmp framework. */

void
sim_engine_run (SIM_DESC sd,
                int next_cpu_nr,	/* ignore */
		int nr_cpus,	/* ignore */
		int siggnal)	/* ignore */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  cpu = STATE_CPU (sd, 0);
  while (1)
    {
      cpu_single_step (cpu);

      /* process any events */
      if (sim_events_tickn (sd, M68HC11_SIM_CPU (cpu)->cpu_current_cycle))
	{
	  sim_events_process (sd);
	}
    }
}

void
sim_info (SIM_DESC sd, int verbose)
{
  const char *cpu_type;
  const struct bfd_arch_info *arch;

  /* Nothing to do if there is no verbose flag set.  */
  if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
    return;

  arch = STATE_ARCHITECTURE (sd);
  if (arch->arch == bfd_arch_m68hc11)
    cpu_type = "68HC11";
  else
    cpu_type = "68HC12";

  sim_io_eprintf (sd, "Simulator info:\n");
  sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
  sim_get_info (sd, 0);
  sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
                     char * const *argv, char * const *env)
{
  return sim_prepare_for_program (sd, abfd);
}

static int
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length)
{
  unsigned char *memory = buf;
  uint16_t val;
  int size = 2;

  switch (rn)
    {
    case A_REGNUM:
      val = cpu_get_a (cpu);
      size = 1;
      break;

    case B_REGNUM:
      val = cpu_get_b (cpu);
      size = 1;
      break;

    case D_REGNUM:
      val = cpu_get_d (cpu);
      break;

    case X_REGNUM:
      val = cpu_get_x (cpu);
      break;

    case Y_REGNUM:
      val = cpu_get_y (cpu);
      break;

    case SP_REGNUM:
      val = cpu_get_sp (cpu);
      break;

    case PC_REGNUM:
      val = cpu_get_pc (cpu);
      break;

    case PSW_REGNUM:
      val = cpu_get_ccr (cpu);
      size = 1;
      break;

    case PAGE_REGNUM:
      val = cpu_get_page (cpu);
      size = 1;
      break;

    default:
      val = 0;
      break;
    }
  if (size == 1)
    {
      memory[0] = val;
    }
  else
    {
      memory[0] = val >> 8;
      memory[1] = val & 0x0FF;
    }
  return size;
}

static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length)
{
  const unsigned char *memory = buf;
  uint16_t val;

  val = *memory++;
  if (length == 2)
    val = (val << 8) | *memory;

  switch (rn)
    {
    case D_REGNUM:
      cpu_set_d (cpu, val);
      break;

    case A_REGNUM:
      cpu_set_a (cpu, val);
      return 1;

    case B_REGNUM:
      cpu_set_b (cpu, val);
      return 1;

    case X_REGNUM:
      cpu_set_x (cpu, val);
      break;

    case Y_REGNUM:
      cpu_set_y (cpu, val);
      break;

    case SP_REGNUM:
      cpu_set_sp (cpu, val);
      break;

    case PC_REGNUM:
      cpu_set_pc (cpu, val);
      break;

    case PSW_REGNUM:
      cpu_set_ccr (cpu, val);
      return 1;

    case PAGE_REGNUM:
      cpu_set_page (cpu, val);
      return 1;

    default:
      break;
    }

  return 2;
}
Commit	Line	Data
5abb9efa	1	/* interp.c -- Simulator for Motorola 68HC11/68HC12
4a94e368	2	Copyright (C) 1999-2022 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50	19
6df01ab8 MF	20	/* This must come before any other includes. */
	21	#include "defs.h"
	22
e0709f50 AC	23	#include "sim-main.h"
	24	#include "sim-assert.h"
	25	#include "sim-hw.h"
	26	#include "sim-options.h"
	27	#include "hw-tree.h"
	28	#include "hw-device.h"
	29	#include "hw-ports.h"
77342e5e	30	#include "elf32-m68hc1x.h"
e0709f50 AC	31
	32	#ifndef MONITOR_BASE
	33	# define MONITOR_BASE (0x0C000)
	34	# define MONITOR_SIZE (0x04000)
	35	#endif
	36
	37	static void sim_get_info (SIM_DESC sd, char *cmd);
	38
e0709f50 AC	39	struct sim_info_list
	40	{
	41	const char *name;
	42	const char *device;
	43	};
	44
81e09ed8	45	struct sim_info_list dev_list_68hc11[] = {
e0709f50 AC	46	{"cpu", "/m68hc11"},
	47	{"timer", "/m68hc11/m68hc11tim"},
	48	{"sio", "/m68hc11/m68hc11sio"},
	49	{"spi", "/m68hc11/m68hc11spi"},
	50	{"eeprom", "/m68hc11/m68hc11eepr"},
	51	{0, 0}
	52	};
	53
81e09ed8 SC	54	struct sim_info_list dev_list_68hc12[] = {
	55	{"cpu", "/m68hc12"},
	56	{"timer", "/m68hc12/m68hc12tim"},
	57	{"sio", "/m68hc12/m68hc12sio"},
	58	{"spi", "/m68hc12/m68hc12spi"},
	59	{"eeprom", "/m68hc12/m68hc12eepr"},
	60	{0, 0}
	61	};
	62
	63	/* Cover function of sim_state_free to free the cpu buffers as well. */
	64
	65	static void
	66	free_state (SIM_DESC sd)
	67	{
	68	if (STATE_MODULES (sd) != NULL)
	69	sim_module_uninstall (sd);
	70
	71	sim_state_free (sd);
	72	}
	73
e0709f50 AC	74	/* Give some information about the simulator. */
	75	static void
	76	sim_get_info (SIM_DESC sd, char *cmd)
	77	{
	78	sim_cpu *cpu;
	79
81e09ed8	80	cpu = STATE_CPU (sd, 0);
e0709f50 AC	81	if (cmd != 0 && (cmd[0] == ' ' \|\| cmd[0] == '-'))
	82	{
	83	int i;
	84	struct hw *hw_dev;
81e09ed8 SC	85	struct sim_info_list *dev_list;
	86	const struct bfd_arch_info *arch;
	87
	88	arch = STATE_ARCHITECTURE (sd);
e0709f50 AC	89	cmd++;
e0709f50 AC	90
81e09ed8 SC	91	if (arch->arch == bfd_arch_m68hc11)
	92	dev_list = dev_list_68hc11;
	93	else
	94	dev_list = dev_list_68hc12;
	95
e0709f50 AC	96	for (i = 0; dev_list[i].name; i++)
	97	if (strcmp (cmd, dev_list[i].name) == 0)
	98	break;
	99
	100	if (dev_list[i].name == 0)
	101	{
	102	sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	103	sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	104	return;
	105	}
fb8d4e59	106	hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
e0709f50 AC	107	if (hw_dev == 0)
	108	{
	109	sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	110	return;
	111	}
	112	hw_ioctl (hw_dev, 23, 0);
	113	return;
	114	}
	115
e0709f50	116	cpu_info (sd, cpu);
79d784ae	117	interrupts_info (sd, &M68HC11_SIM_CPU (cpu)->cpu_interrupts);
e0709f50 AC	118	}
	119
	120
	121	void
	122	sim_board_reset (SIM_DESC sd)
	123	{
	124	struct hw *hw_cpu;
	125	sim_cpu *cpu;
79d784ae	126	struct m68hc11_sim_cpu *m68hc11_cpu;
81e09ed8 SC	127	const struct bfd_arch_info *arch;
81e09ed8 SC	128	const char *cpu_type;
e0709f50 AC	129
e0709f50 AC	130	cpu = STATE_CPU (sd, 0);
79d784ae	131	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
81e09ed8 SC	132	arch = STATE_ARCHITECTURE (sd);
81e09ed8 SC	133
e0709f50	134	/* hw_cpu = sim_hw_parse (sd, "/"); */
81e09ed8 SC	135	if (arch->arch == bfd_arch_m68hc11)
81e09ed8 SC	136	{
79d784ae	137	m68hc11_cpu->cpu_type = CPU_M6811;
81e09ed8 SC	138	cpu_type = "/m68hc11";
	139	}
	140	else
	141	{
79d784ae	142	m68hc11_cpu->cpu_type = CPU_M6812;
81e09ed8 SC	143	cpu_type = "/m68hc12";
	144	}
	145
fb8d4e59	146	hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
e0709f50 AC	147	if (hw_cpu == 0)
e0709f50 AC	148	{
81e09ed8	149	sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
e0709f50 AC	150	return;
	151	}
	152
	153	cpu_reset (cpu);
	154	hw_port_event (hw_cpu, 3, 0);
	155	cpu_restart (cpu);
	156	}
	157
39762100	158	static int
81e09ed8 SC	159	sim_hw_configure (SIM_DESC sd)
	160	{
	161	const struct bfd_arch_info *arch;
	162	struct hw *device_tree;
81e09ed8	163	sim_cpu *cpu;
79d784ae	164	struct m68hc11_sim_cpu *m68hc11_cpu;
81e09ed8 SC	165
	166	arch = STATE_ARCHITECTURE (sd);
	167	if (arch == 0)
	168	return 0;
	169
	170	cpu = STATE_CPU (sd, 0);
79d784ae MF	171	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
79d784ae MF	172	m68hc11_cpu->cpu_configured_arch = arch;
81e09ed8 SC	173	device_tree = sim_hw_parse (sd, "/");
	174	if (arch->arch == bfd_arch_m68hc11)
	175	{
79d784ae	176	m68hc11_cpu->cpu_interpretor = cpu_interp_m6811;
81e09ed8 SC	177	if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	178	{
	179	/* Allocate core managed memory */
	180
	181	/* the monitor */
8e78e9b9	182	sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
81e09ed8 SC	183	/* MONITOR_BASE, MONITOR_SIZE */
	184	0x8000, M6811_RAM_LEVEL, 0x8000);
	185	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	186	M6811_RAM_LEVEL);
	187	sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
79d784ae	188	if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
77342e5e	189	{
8e78e9b9	190	sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
79d784ae	191	m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
77342e5e SC	192	sim_hw_parse (sd, "/m68hc11/use_bank 1");
77342e5e SC	193	}
81e09ed8	194	}
79d784ae	195	if (m68hc11_cpu->cpu_start_mode)
77342e5e	196	{
79d784ae	197	sim_hw_parse (sd, "/m68hc11/mode %s", m68hc11_cpu->cpu_start_mode);
77342e5e	198	}
81e09ed8 SC	199	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	200	{
	201	sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	202	sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	203	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	204	}
	205	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	206	{
	207	/* M68hc11 Timer configuration. */
	208	sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	209	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
827ec39a	210	sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
81e09ed8 SC	211	}
	212
	213	/* Create the SPI device. */
	214	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	215	{
	216	sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	217	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	218	}
	219	if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	220	{
	221	/* M68hc11 persistent ram configuration. */
	222	sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	223	sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	224	sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	225	/sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); /
	226	}
	227	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	228	{
	229	sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	230	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	231	}
dcceded2 SC	232	sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
	233	sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
	234	sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
	235	sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
79d784ae	236	m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
81e09ed8 SC	237	}
	238	else
	239	{
79d784ae	240	m68hc11_cpu->cpu_interpretor = cpu_interp_m6812;
81e09ed8 SC	241	if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	242	{
	243	/* Allocate core external memory. */
8e78e9b9	244	sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
77342e5e	245	0x8000, M6811_RAM_LEVEL, 0x8000);
81e09ed8 SC	246	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
81e09ed8 SC	247	M6811_RAM_LEVEL);
79d784ae	248	if (m68hc11_cpu->bank_start < m68hc11_cpu->bank_end)
77342e5e	249	{
8e78e9b9	250	sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
79d784ae	251	m68hc11_cpu->bank_virtual, M6811_RAM_LEVEL);
77342e5e SC	252	sim_hw_parse (sd, "/m68hc12/use_bank 1");
77342e5e SC	253	}
81e09ed8 SC	254	sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	255	}
	256
	257	if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	258	{
	259	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	260	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	261	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	262	}
81e09ed8 SC	263	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	264	{
	265	/* M68hc11 Timer configuration. */
	266	sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	267	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
dcceded2	268	sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
81e09ed8 SC	269	}
	270
	271	/* Create the SPI device. */
	272	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	273	{
	274	sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	275	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	276	}
	277	if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	278	{
	279	/* M68hc11 persistent ram configuration. */
	280	sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	281	sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	282	sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	283	}
	284	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	285	{
	286	sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	287	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	288	}
827ec39a	289
dcceded2 SC	290	sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
	291	sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
	292	sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
	293	sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
79d784ae	294	m68hc11_cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
81e09ed8	295	}
39762100	296	return 1;
81e09ed8 SC	297	}
81e09ed8 SC	298
77342e5e SC	299	/* Get the memory bank parameters by looking at the global symbols
77342e5e SC	300	defined by the linker. */
81e09ed8	301	static int
5357150c	302	sim_get_bank_parameters (SIM_DESC sd)
81e09ed8 SC	303	{
81e09ed8 SC	304	sim_cpu *cpu;
79d784ae	305	struct m68hc11_sim_cpu *m68hc11_cpu;
77342e5e	306	unsigned size;
5357150c	307	bfd_vma addr;
81e09ed8 SC	308
81e09ed8 SC	309	cpu = STATE_CPU (sd, 0);
79d784ae	310	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
81e09ed8	311
5357150c MF	312	addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
5357150c MF	313	if (addr != -1)
79d784ae	314	m68hc11_cpu->bank_start = addr;
77342e5e	315
5357150c MF	316	size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
	317	if (size == -1)
	318	size = 0;
77342e5e	319
5357150c MF	320	addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
5357150c MF	321	if (addr != -1)
79d784ae	322	m68hc11_cpu->bank_virtual = addr;
77342e5e	323
79d784ae MF	324	m68hc11_cpu->bank_end = m68hc11_cpu->bank_start + size;
79d784ae MF	325	m68hc11_cpu->bank_shift = 0;
77342e5e	326	for (; size > 1; size >>= 1)
79d784ae	327	m68hc11_cpu->bank_shift++;
77342e5e SC	328
	329	return 0;
	330	}
	331
	332	static int
	333	sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
	334	{
	335	sim_cpu *cpu;
79d784ae	336	struct m68hc11_sim_cpu *m68hc11_cpu;
77342e5e SC	337	int elf_flags = 0;
	338
	339	cpu = STATE_CPU (sd, 0);
79d784ae	340	m68hc11_cpu = M68HC11_SIM_CPU (cpu);
39762100	341
81e09ed8 SC	342	if (abfd != NULL)
81e09ed8 SC	343	{
31c7c532	344	asection *s;
77342e5e SC	345
	346	if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
	347	elf_flags = elf_elfheader (abfd)->e_flags;
	348
79d784ae	349	m68hc11_cpu->cpu_elf_start = bfd_get_start_address (abfd);
31c7c532	350	/* See if any section sets the reset address */
79d784ae MF	351	m68hc11_cpu->cpu_use_elf_start = 1;
79d784ae MF	352	for (s = abfd->sections; s && m68hc11_cpu->cpu_use_elf_start; s = s->next)
31c7c532 SC	353	{
	354	if (s->flags & SEC_LOAD)
	355	{
	356	bfd_size_type size;
	357
fd361982	358	size = bfd_section_size (s);
31c7c532 SC	359	if (size > 0)
	360	{
	361	bfd_vma lma;
	362
	363	if (STATE_LOAD_AT_LMA_P (sd))
fd361982	364	lma = bfd_section_lma (s);
31c7c532	365	else
fd361982	366	lma = bfd_section_vma (s);
31c7c532 SC	367
31c7c532 SC	368	if (lma <= 0xFFFE && lma+size >= 0x10000)
79d784ae	369	m68hc11_cpu->cpu_use_elf_start = 0;
31c7c532 SC	370	}
	371	}
	372	}
77342e5e SC	373
	374	if (elf_flags & E_M68HC12_BANKS)
	375	{
5357150c	376	if (sim_get_bank_parameters (sd) != 0)
77342e5e SC	377	sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
77342e5e SC	378	}
81e09ed8 SC	379	}
81e09ed8 SC	380
77342e5e SC	381	if (!sim_hw_configure (sd))
	382	return SIM_RC_FAIL;
	383
81e09ed8 SC	384	/* reset all state information */
	385	sim_board_reset (sd);
	386
	387	return SIM_RC_OK;
	388	}
	389
bea3f671 MF	390	static sim_cia
	391	m68hc11_pc_get (sim_cpu *cpu)
	392	{
	393	return cpu_get_pc (cpu);
	394	}
	395
	396	static void
	397	m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
	398	{
	399	cpu_set_pc (cpu, pc);
	400	}
	401
ee1cffd3 MF	402	static int m68hc11_reg_fetch (SIM_CPU , int, void , int);
ee1cffd3 MF	403	static int m68hc11_reg_store (SIM_CPU , int, const void , int);
e1211e55	404
e0709f50 AC	405	SIM_DESC
e0709f50 AC	406	sim_open (SIM_OPEN_KIND kind, host_callback *callback,
2e3d4f4d	407	bfd abfd, char const *argv)
e0709f50	408	{
bea3f671	409	int i;
e0709f50 AC	410	SIM_DESC sd;
e0709f50 AC	411	sim_cpu *cpu;
e0709f50 AC	412
e0709f50 AC	413	sd = sim_state_alloc (kind, callback);
e0709f50 AC	414
	415	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	416
f9a4d543 MF	417	/* Set default options before parsing user options. */
	418	current_target_byte_order = BFD_ENDIAN_BIG;
	419
bea3f671	420	/* The cpu data is kept in a separately allocated chunk of memory. */
79d784ae MF	421	if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m68hc11_sim_cpu))
79d784ae MF	422	!= SIM_RC_OK)
bea3f671 MF	423	{
	424	free_state (sd);
	425	return 0;
	426	}
	427
	428	cpu = STATE_CPU (sd, 0);
	429
e0709f50 AC	430	cpu_initialize (sd, cpu);
e0709f50 AC	431
e0709f50	432	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
81e09ed8 SC	433	{
	434	free_state (sd);
	435	return 0;
	436	}
e0709f50	437
77cf2ef5	438	/* The parser will print an error message for us, so we silently return. */
e0709f50 AC	439	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	440	{
	441	/* Uninstall the modules to avoid memory leaks,
	442	file descriptor leaks, etc. */
81e09ed8	443	free_state (sd);
e0709f50 AC	444	return 0;
	445	}
	446
e0709f50	447	/* Check for/establish the a reference program image. */
e8f20a28	448	if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
e0709f50	449	{
81e09ed8	450	free_state (sd);
e0709f50 AC	451	return 0;
	452	}
	453
	454	/* Establish any remaining configuration options. */
	455	if (sim_config (sd) != SIM_RC_OK)
	456	{
81e09ed8	457	free_state (sd);
e0709f50 AC	458	return 0;
	459	}
	460
	461	if (sim_post_argv_init (sd) != SIM_RC_OK)
	462	{
	463	/* Uninstall the modules to avoid memory leaks,
	464	file descriptor leaks, etc. */
81e09ed8	465	free_state (sd);
e0709f50 AC	466	return 0;
e0709f50 AC	467	}
77342e5e SC	468	if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
	469	{
	470	free_state (sd);
	471	return 0;
	472	}
e0709f50	473
bea3f671 MF	474	/* CPU specific initialization. */
	475	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
	476	{
	477	SIM_CPU *cpu = STATE_CPU (sd, i);
	478
e1211e55 MF	479	CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
e1211e55 MF	480	CPU_REG_STORE (cpu) = m68hc11_reg_store;
bea3f671 MF	481	CPU_PC_FETCH (cpu) = m68hc11_pc_get;
	482	CPU_PC_STORE (cpu) = m68hc11_pc_set;
	483	}
	484
e0709f50 AC	485	return sd;
	486	}
	487
e0709f50 AC	488	/* Generic implementation of sim_engine_run that works within the
	489	sim_engine setjmp/longjmp framework. */
	490
	491	void
	492	sim_engine_run (SIM_DESC sd,
	493	int next_cpu_nr, /* ignore */
	494	int nr_cpus, /* ignore */
	495	int siggnal) /* ignore */
	496	{
	497	sim_cpu *cpu;
	498
	499	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	500	cpu = STATE_CPU (sd, 0);
	501	while (1)
	502	{
	503	cpu_single_step (cpu);
	504
	505	/* process any events */
79d784ae	506	if (sim_events_tickn (sd, M68HC11_SIM_CPU (cpu)->cpu_current_cycle))
e0709f50 AC	507	{
	508	sim_events_process (sd);
	509	}
	510	}
	511	}
	512
e0709f50 AC	513	void
	514	sim_info (SIM_DESC sd, int verbose)
	515	{
81e09ed8 SC	516	const char *cpu_type;
	517	const struct bfd_arch_info *arch;
	518
00d0c012 SC	519	/* Nothing to do if there is no verbose flag set. */
	520	if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
	521	return;
	522
81e09ed8 SC	523	arch = STATE_ARCHITECTURE (sd);
	524	if (arch->arch == bfd_arch_m68hc11)
	525	cpu_type = "68HC11";
	526	else
	527	cpu_type = "68HC12";
	528
e0709f50	529	sim_io_eprintf (sd, "Simulator info:\n");
81e09ed8	530	sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
e0709f50 AC	531	sim_get_info (sd, 0);
	532	sim_module_info (sd, verbose \|\| STATE_VERBOSE_P (sd));
	533	}
	534
	535	SIM_RC
6b4a8935	536	sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
2e3d4f4d	537	char * const argv, char const *env)
e0709f50	538	{
81e09ed8	539	return sim_prepare_for_program (sd, abfd);
e0709f50 AC	540	}
e0709f50 AC	541
e1211e55	542	static int
ee1cffd3	543	m68hc11_reg_fetch (SIM_CPU cpu, int rn, void buf, int length)
e0709f50	544	{
ee1cffd3	545	unsigned char *memory = buf;
7606e1a3	546	uint16_t val;
63f36def	547	int size = 2;
e0709f50	548
e0709f50 AC	549	switch (rn)
	550	{
	551	case A_REGNUM:
	552	val = cpu_get_a (cpu);
63f36def	553	size = 1;
e0709f50 AC	554	break;
	555
	556	case B_REGNUM:
	557	val = cpu_get_b (cpu);
63f36def	558	size = 1;
e0709f50 AC	559	break;
	560
	561	case D_REGNUM:
	562	val = cpu_get_d (cpu);
	563	break;
	564
	565	case X_REGNUM:
	566	val = cpu_get_x (cpu);
	567	break;
	568
	569	case Y_REGNUM:
	570	val = cpu_get_y (cpu);
	571	break;
	572
	573	case SP_REGNUM:
	574	val = cpu_get_sp (cpu);
	575	break;
	576
	577	case PC_REGNUM:
	578	val = cpu_get_pc (cpu);
	579	break;
	580
	581	case PSW_REGNUM:
	582	val = cpu_get_ccr (cpu);
63f36def SC	583	size = 1;
	584	break;
	585
	586	case PAGE_REGNUM:
	587	val = cpu_get_page (cpu);
	588	size = 1;
e0709f50 AC	589	break;
e0709f50 AC	590
e0709f50	591	default:
9830501b	592	val = 0;
e0709f50 AC	593	break;
e0709f50 AC	594	}
00416c6e SC	595	if (size == 1)
	596	{
	597	memory[0] = val;
	598	}
	599	else
	600	{
	601	memory[0] = val >> 8;
	602	memory[1] = val & 0x0FF;
	603	}
63f36def	604	return size;
e0709f50 AC	605	}
e0709f50 AC	606
e1211e55	607	static int
ee1cffd3	608	m68hc11_reg_store (SIM_CPU cpu, int rn, const void buf, int length)
e0709f50	609	{
ee1cffd3	610	const unsigned char *memory = buf;
7606e1a3	611	uint16_t val;
e0709f50 AC	612
	613	val = *memory++;
	614	if (length == 2)
	615	val = (val << 8) \| *memory;
	616
	617	switch (rn)
	618	{
	619	case D_REGNUM:
	620	cpu_set_d (cpu, val);
	621	break;
	622
	623	case A_REGNUM:
	624	cpu_set_a (cpu, val);
63f36def	625	return 1;
e0709f50 AC	626
	627	case B_REGNUM:
	628	cpu_set_b (cpu, val);
63f36def	629	return 1;
e0709f50 AC	630
	631	case X_REGNUM:
	632	cpu_set_x (cpu, val);
	633	break;
	634
	635	case Y_REGNUM:
	636	cpu_set_y (cpu, val);
	637	break;
	638
	639	case SP_REGNUM:
	640	cpu_set_sp (cpu, val);
	641	break;
	642
	643	case PC_REGNUM:
	644	cpu_set_pc (cpu, val);
	645	break;
	646
	647	case PSW_REGNUM:
	648	cpu_set_ccr (cpu, val);
63f36def SC	649	return 1;
	650
	651	case PAGE_REGNUM:
	652	cpu_set_page (cpu, val);
	653	return 1;
e0709f50	654
e0709f50	655	default:
e0709f50 AC	656	break;
	657	}
	658
	659	return 2;
	660	}