[thirdparty/binutils-gdb.git] / sim / m68hc11 / interp.c

/* interp.c -- Simulator for Motorola 68HC11/68HC12
   Copyright (C) 1999-2021 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "sim-main.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "sim-options.h"
#include "hw-tree.h"
#include "hw-device.h"
#include "hw-ports.h"
#include "elf32-m68hc1x.h"

#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
#endif

static void sim_get_info (SIM_DESC sd, char *cmd);

struct sim_info_list
{
  const char *name;
  const char *device;
};

struct sim_info_list dev_list_68hc11[] = {
  {"cpu", "/m68hc11"},
  {"timer", "/m68hc11/m68hc11tim"},
  {"sio", "/m68hc11/m68hc11sio"},
  {"spi", "/m68hc11/m68hc11spi"},
  {"eeprom", "/m68hc11/m68hc11eepr"},
  {0, 0}
};

struct sim_info_list dev_list_68hc12[] = {
  {"cpu", "/m68hc12"},
  {"timer", "/m68hc12/m68hc12tim"},
  {"sio", "/m68hc12/m68hc12sio"},
  {"spi", "/m68hc12/m68hc12spi"},
  {"eeprom", "/m68hc12/m68hc12eepr"},
  {0, 0}
};

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);

  sim_state_free (sd);
}

/* Give some information about the simulator.  */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
    {
      int i;
      struct hw *hw_dev;
      struct sim_info_list *dev_list;
      const struct bfd_arch_info *arch;

      arch = STATE_ARCHITECTURE (sd);
      cmd++;

      if (arch->arch == bfd_arch_m68hc11)
        dev_list = dev_list_68hc11;
      else
        dev_list = dev_list_68hc12;

      for (i = 0; dev_list[i].name; i++)
	if (strcmp (cmd, dev_list[i].name) == 0)
	  break;

      if (dev_list[i].name == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	  sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	  return;
	}
      hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
      if (hw_dev == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	  return;
	}
      hw_ioctl (hw_dev, 23, 0);
      return;
    }

  cpu_info (sd, cpu);
  interrupts_info (sd, &cpu->cpu_interrupts);
}


void
sim_board_reset (SIM_DESC sd)
{
  struct hw *hw_cpu;
  sim_cpu *cpu;
  const struct bfd_arch_info *arch;
  const char *cpu_type;

  cpu = STATE_CPU (sd, 0);
  arch = STATE_ARCHITECTURE (sd);

  /*  hw_cpu = sim_hw_parse (sd, "/"); */
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_type = CPU_M6811;
      cpu_type = "/m68hc11";
    }
  else
    {
      cpu->cpu_type = CPU_M6812;
      cpu_type = "/m68hc12";
    }
  
  hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
  if (hw_cpu == 0)
    {
      sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
      return;
    }

  cpu_reset (cpu);
  hw_port_event (hw_cpu, 3, 0);
  cpu_restart (cpu);
}

static int
sim_hw_configure (SIM_DESC sd)
{
  const struct bfd_arch_info *arch;
  struct hw *device_tree;
  sim_cpu *cpu;
  
  arch = STATE_ARCHITECTURE (sd);
  if (arch == 0)
    return 0;

  cpu = STATE_CPU (sd, 0);
  cpu->cpu_configured_arch = arch;
  device_tree = sim_hw_parse (sd, "/");
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_interpretor = cpu_interp_m6811;
      if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	{
	  /* Allocate core managed memory */

	  /* the monitor  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   /* MONITOR_BASE, MONITOR_SIZE */
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
	  sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
          if (cpu->bank_start < cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
                               cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc11/use_bank 1");
            }
	}
      if (cpu->cpu_start_mode)
        {
          sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
        }
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
          sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	  sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	  sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	  /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	}
      sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
    }
  else
    {
      cpu->cpu_interpretor = cpu_interp_m6812;
      if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	{
	  /* Allocate core external memory.  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
          if (cpu->bank_start < cpu->bank_end)
            {
              sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
                               cpu->bank_virtual, M6811_RAM_LEVEL);
              sim_hw_parse (sd, "/m68hc12/use_bank 1");
            }
	  sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	}

      if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
          sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	  sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	  sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	}

      sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
    }
  return 1;
}

/* Get the memory bank parameters by looking at the global symbols
   defined by the linker.  */
static int
sim_get_bank_parameters (SIM_DESC sd)
{
  sim_cpu *cpu;
  unsigned size;
  bfd_vma addr;

  cpu = STATE_CPU (sd, 0);

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
  if (addr != -1)
    cpu->bank_start = addr;

  size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
  if (size == -1)
    size = 0;

  addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
  if (addr != -1)
    cpu->bank_virtual = addr;

  cpu->bank_end = cpu->bank_start + size;
  cpu->bank_shift = 0;
  for (; size > 1; size >>= 1)
    cpu->bank_shift++;

  return 0;
}

static int
sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
{
  sim_cpu *cpu;
  int elf_flags = 0;

  cpu = STATE_CPU (sd, 0);

  if (abfd != NULL)
    {
      asection *s;

      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
        elf_flags = elf_elfheader (abfd)->e_flags;

      cpu->cpu_elf_start = bfd_get_start_address (abfd);
      /* See if any section sets the reset address */
      cpu->cpu_use_elf_start = 1;
      for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next) 
        {
          if (s->flags & SEC_LOAD)
            {
              bfd_size_type size;

	      size = bfd_section_size (s);
              if (size > 0)
                {
                  bfd_vma lma;

                  if (STATE_LOAD_AT_LMA_P (sd))
		    lma = bfd_section_lma (s);
                  else
		    lma = bfd_section_vma (s);

                  if (lma <= 0xFFFE && lma+size >= 0x10000)
                    cpu->cpu_use_elf_start = 0;
                }
            }
        }

      if (elf_flags & E_M68HC12_BANKS)
        {
          if (sim_get_bank_parameters (sd) != 0)
            sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
        }
    }

  if (!sim_hw_configure (sd))
    return SIM_RC_FAIL;

  /* reset all state information */
  sim_board_reset (sd);

  return SIM_RC_OK;
}

static sim_cia
m68hc11_pc_get (sim_cpu *cpu)
{
  return cpu_get_pc (cpu);
}

static void
m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
{
  cpu_set_pc (cpu, pc);
}

static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int m68hc11_reg_store (SIM_CPU *, int, unsigned char *, int);

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
	  bfd *abfd, char * const *argv)
{
  int i;
  SIM_DESC sd;
  sim_cpu *cpu;

  sd = sim_state_alloc (kind, callback);

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  cpu = STATE_CPU (sd, 0);

  cpu_initialize (sd, cpu);

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }
  if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }      

  /* CPU specific initialization.  */
  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
    {
      SIM_CPU *cpu = STATE_CPU (sd, i);

      CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
      CPU_REG_STORE (cpu) = m68hc11_reg_store;
      CPU_PC_FETCH (cpu) = m68hc11_pc_get;
      CPU_PC_STORE (cpu) = m68hc11_pc_set;
    }

  return sd;
}

/* Generic implementation of sim_engine_run that works within the
   sim_engine setjmp/longjmp framework. */

void
sim_engine_run (SIM_DESC sd,
                int next_cpu_nr,	/* ignore */
		int nr_cpus,	/* ignore */
		int siggnal)	/* ignore */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  cpu = STATE_CPU (sd, 0);
  while (1)
    {
      cpu_single_step (cpu);

      /* process any events */
      if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	{
	  sim_events_process (sd);
	}
    }
}

void
sim_info (SIM_DESC sd, int verbose)
{
  const char *cpu_type;
  const struct bfd_arch_info *arch;

  /* Nothing to do if there is no verbose flag set.  */
  if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
    return;

  arch = STATE_ARCHITECTURE (sd);
  if (arch->arch == bfd_arch_m68hc11)
    cpu_type = "68HC11";
  else
    cpu_type = "68HC12";

  sim_io_eprintf (sd, "Simulator info:\n");
  sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
  sim_get_info (sd, 0);
  sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
                     char * const *argv, char * const *env)
{
  return sim_prepare_for_program (sd, abfd);
}

static int
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  uint16 val;
  int size = 2;

  switch (rn)
    {
    case A_REGNUM:
      val = cpu_get_a (cpu);
      size = 1;
      break;

    case B_REGNUM:
      val = cpu_get_b (cpu);
      size = 1;
      break;

    case D_REGNUM:
      val = cpu_get_d (cpu);
      break;

    case X_REGNUM:
      val = cpu_get_x (cpu);
      break;

    case Y_REGNUM:
      val = cpu_get_y (cpu);
      break;

    case SP_REGNUM:
      val = cpu_get_sp (cpu);
      break;

    case PC_REGNUM:
      val = cpu_get_pc (cpu);
      break;

    case PSW_REGNUM:
      val = cpu_get_ccr (cpu);
      size = 1;
      break;

    case PAGE_REGNUM:
      val = cpu_get_page (cpu);
      size = 1;
      break;

    default:
      val = 0;
      break;
    }
  if (size == 1)
    {
      memory[0] = val;
    }
  else
    {
      memory[0] = val >> 8;
      memory[1] = val & 0x0FF;
    }
  return size;
}

static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
  uint16 val;

  val = *memory++;
  if (length == 2)
    val = (val << 8) | *memory;

  switch (rn)
    {
    case D_REGNUM:
      cpu_set_d (cpu, val);
      break;

    case A_REGNUM:
      cpu_set_a (cpu, val);
      return 1;

    case B_REGNUM:
      cpu_set_b (cpu, val);
      return 1;

    case X_REGNUM:
      cpu_set_x (cpu, val);
      break;

    case Y_REGNUM:
      cpu_set_y (cpu, val);
      break;

    case SP_REGNUM:
      cpu_set_sp (cpu, val);
      break;

    case PC_REGNUM:
      cpu_set_pc (cpu, val);
      break;

    case PSW_REGNUM:
      cpu_set_ccr (cpu, val);
      return 1;

    case PAGE_REGNUM:
      cpu_set_page (cpu, val);
      return 1;

    default:
      break;
    }

  return 2;
}
Commit	Line	Data
5abb9efa	1	/* interp.c -- Simulator for Motorola 68HC11/68HC12
3666a048	2	Copyright (C) 1999-2021 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	19
	20	#include "sim-main.h"
	21	#include "sim-assert.h"
	22	#include "sim-hw.h"
	23	#include "sim-options.h"
	24	#include "hw-tree.h"
	25	#include "hw-device.h"
	26	#include "hw-ports.h"
77342e5e	27	#include "elf32-m68hc1x.h"
e0709f50 AC	28
	29	#ifndef MONITOR_BASE
	30	# define MONITOR_BASE (0x0C000)
	31	# define MONITOR_SIZE (0x04000)
	32	#endif
	33
	34	static void sim_get_info (SIM_DESC sd, char *cmd);
	35
e0709f50 AC	36	struct sim_info_list
	37	{
	38	const char *name;
	39	const char *device;
	40	};
	41
81e09ed8	42	struct sim_info_list dev_list_68hc11[] = {
e0709f50 AC	43	{"cpu", "/m68hc11"},
	44	{"timer", "/m68hc11/m68hc11tim"},
	45	{"sio", "/m68hc11/m68hc11sio"},
	46	{"spi", "/m68hc11/m68hc11spi"},
	47	{"eeprom", "/m68hc11/m68hc11eepr"},
	48	{0, 0}
	49	};
	50
81e09ed8 SC	51	struct sim_info_list dev_list_68hc12[] = {
	52	{"cpu", "/m68hc12"},
	53	{"timer", "/m68hc12/m68hc12tim"},
	54	{"sio", "/m68hc12/m68hc12sio"},
	55	{"spi", "/m68hc12/m68hc12spi"},
	56	{"eeprom", "/m68hc12/m68hc12eepr"},
	57	{0, 0}
	58	};
	59
	60	/* Cover function of sim_state_free to free the cpu buffers as well. */
	61
	62	static void
	63	free_state (SIM_DESC sd)
	64	{
	65	if (STATE_MODULES (sd) != NULL)
	66	sim_module_uninstall (sd);
	67
	68	sim_state_free (sd);
	69	}
	70
e0709f50 AC	71	/* Give some information about the simulator. */
	72	static void
	73	sim_get_info (SIM_DESC sd, char *cmd)
	74	{
	75	sim_cpu *cpu;
	76
81e09ed8	77	cpu = STATE_CPU (sd, 0);
e0709f50 AC	78	if (cmd != 0 && (cmd[0] == ' ' \|\| cmd[0] == '-'))
	79	{
	80	int i;
	81	struct hw *hw_dev;
81e09ed8 SC	82	struct sim_info_list *dev_list;
	83	const struct bfd_arch_info *arch;
	84
	85	arch = STATE_ARCHITECTURE (sd);
e0709f50 AC	86	cmd++;
e0709f50 AC	87
81e09ed8 SC	88	if (arch->arch == bfd_arch_m68hc11)
	89	dev_list = dev_list_68hc11;
	90	else
	91	dev_list = dev_list_68hc12;
	92
e0709f50 AC	93	for (i = 0; dev_list[i].name; i++)
	94	if (strcmp (cmd, dev_list[i].name) == 0)
	95	break;
	96
	97	if (dev_list[i].name == 0)
	98	{
	99	sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	100	sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	101	return;
	102	}
fb8d4e59	103	hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
e0709f50 AC	104	if (hw_dev == 0)
	105	{
	106	sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	107	return;
	108	}
	109	hw_ioctl (hw_dev, 23, 0);
	110	return;
	111	}
	112
e0709f50 AC	113	cpu_info (sd, cpu);
	114	interrupts_info (sd, &cpu->cpu_interrupts);
	115	}
	116
	117
	118	void
	119	sim_board_reset (SIM_DESC sd)
	120	{
	121	struct hw *hw_cpu;
	122	sim_cpu *cpu;
81e09ed8 SC	123	const struct bfd_arch_info *arch;
81e09ed8 SC	124	const char *cpu_type;
e0709f50 AC	125
e0709f50 AC	126	cpu = STATE_CPU (sd, 0);
81e09ed8 SC	127	arch = STATE_ARCHITECTURE (sd);
81e09ed8 SC	128
e0709f50	129	/* hw_cpu = sim_hw_parse (sd, "/"); */
81e09ed8 SC	130	if (arch->arch == bfd_arch_m68hc11)
	131	{
	132	cpu->cpu_type = CPU_M6811;
	133	cpu_type = "/m68hc11";
	134	}
	135	else
	136	{
	137	cpu->cpu_type = CPU_M6812;
	138	cpu_type = "/m68hc12";
	139	}
	140
fb8d4e59	141	hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
e0709f50 AC	142	if (hw_cpu == 0)
e0709f50 AC	143	{
81e09ed8	144	sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
e0709f50 AC	145	return;
	146	}
	147
	148	cpu_reset (cpu);
	149	hw_port_event (hw_cpu, 3, 0);
	150	cpu_restart (cpu);
	151	}
	152
39762100	153	static int
81e09ed8 SC	154	sim_hw_configure (SIM_DESC sd)
	155	{
	156	const struct bfd_arch_info *arch;
	157	struct hw *device_tree;
81e09ed8 SC	158	sim_cpu *cpu;
	159
	160	arch = STATE_ARCHITECTURE (sd);
	161	if (arch == 0)
	162	return 0;
	163
	164	cpu = STATE_CPU (sd, 0);
	165	cpu->cpu_configured_arch = arch;
	166	device_tree = sim_hw_parse (sd, "/");
	167	if (arch->arch == bfd_arch_m68hc11)
	168	{
	169	cpu->cpu_interpretor = cpu_interp_m6811;
	170	if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	171	{
	172	/* Allocate core managed memory */
	173
	174	/* the monitor */
	175	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
	176	/* MONITOR_BASE, MONITOR_SIZE */
	177	0x8000, M6811_RAM_LEVEL, 0x8000);
	178	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	179	M6811_RAM_LEVEL);
	180	sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
77342e5e SC	181	if (cpu->bank_start < cpu->bank_end)
	182	{
	183	sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
	184	cpu->bank_virtual, M6811_RAM_LEVEL);
	185	sim_hw_parse (sd, "/m68hc11/use_bank 1");
	186	}
81e09ed8	187	}
77342e5e SC	188	if (cpu->cpu_start_mode)
	189	{
	190	sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
	191	}
81e09ed8 SC	192	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	193	{
	194	sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	195	sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	196	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	197	}
	198	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	199	{
	200	/* M68hc11 Timer configuration. */
	201	sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	202	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
827ec39a	203	sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
81e09ed8 SC	204	}
	205
	206	/* Create the SPI device. */
	207	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	208	{
	209	sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	210	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	211	}
	212	if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	213	{
	214	/* M68hc11 persistent ram configuration. */
	215	sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	216	sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	217	sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	218	/sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); /
	219	}
	220	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	221	{
	222	sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	223	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	224	}
dcceded2 SC	225	sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
	226	sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
	227	sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
	228	sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
827ec39a	229	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
81e09ed8 SC	230	}
	231	else
	232	{
	233	cpu->cpu_interpretor = cpu_interp_m6812;
	234	if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	235	{
	236	/* Allocate core external memory. */
	237	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
77342e5e	238	0x8000, M6811_RAM_LEVEL, 0x8000);
81e09ed8 SC	239	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
81e09ed8 SC	240	M6811_RAM_LEVEL);
77342e5e SC	241	if (cpu->bank_start < cpu->bank_end)
	242	{
	243	sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000",
	244	cpu->bank_virtual, M6811_RAM_LEVEL);
	245	sim_hw_parse (sd, "/m68hc12/use_bank 1");
	246	}
81e09ed8 SC	247	sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	248	}
	249
	250	if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	251	{
	252	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	253	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	254	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	255	}
81e09ed8 SC	256	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	257	{
	258	/* M68hc11 Timer configuration. */
	259	sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	260	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
dcceded2	261	sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
81e09ed8 SC	262	}
	263
	264	/* Create the SPI device. */
	265	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	266	{
	267	sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	268	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	269	}
	270	if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	271	{
	272	/* M68hc11 persistent ram configuration. */
	273	sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	274	sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	275	sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	276	}
	277	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	278	{
	279	sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	280	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	281	}
827ec39a	282
dcceded2 SC	283	sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
	284	sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
	285	sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
	286	sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
827ec39a	287	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
81e09ed8	288	}
39762100	289	return 1;
81e09ed8 SC	290	}
81e09ed8 SC	291
77342e5e SC	292	/* Get the memory bank parameters by looking at the global symbols
77342e5e SC	293	defined by the linker. */
81e09ed8	294	static int
5357150c	295	sim_get_bank_parameters (SIM_DESC sd)
81e09ed8 SC	296	{
81e09ed8 SC	297	sim_cpu *cpu;
77342e5e	298	unsigned size;
5357150c	299	bfd_vma addr;
81e09ed8 SC	300
	301	cpu = STATE_CPU (sd, 0);
	302
5357150c MF	303	addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
	304	if (addr != -1)
	305	cpu->bank_start = addr;
77342e5e	306
5357150c MF	307	size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
	308	if (size == -1)
	309	size = 0;
77342e5e	310
5357150c MF	311	addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
	312	if (addr != -1)
	313	cpu->bank_virtual = addr;
77342e5e SC	314
	315	cpu->bank_end = cpu->bank_start + size;
	316	cpu->bank_shift = 0;
	317	for (; size > 1; size >>= 1)
	318	cpu->bank_shift++;
	319
	320	return 0;
	321	}
	322
	323	static int
	324	sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
	325	{
	326	sim_cpu *cpu;
	327	int elf_flags = 0;
	328
	329	cpu = STATE_CPU (sd, 0);
39762100	330
81e09ed8 SC	331	if (abfd != NULL)
81e09ed8 SC	332	{
31c7c532	333	asection *s;
77342e5e SC	334
	335	if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
	336	elf_flags = elf_elfheader (abfd)->e_flags;
	337
81e09ed8	338	cpu->cpu_elf_start = bfd_get_start_address (abfd);
31c7c532 SC	339	/* See if any section sets the reset address */
	340	cpu->cpu_use_elf_start = 1;
	341	for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next)
	342	{
	343	if (s->flags & SEC_LOAD)
	344	{
	345	bfd_size_type size;
	346
fd361982	347	size = bfd_section_size (s);
31c7c532 SC	348	if (size > 0)
	349	{
	350	bfd_vma lma;
	351
	352	if (STATE_LOAD_AT_LMA_P (sd))
fd361982	353	lma = bfd_section_lma (s);
31c7c532	354	else
fd361982	355	lma = bfd_section_vma (s);
31c7c532 SC	356
	357	if (lma <= 0xFFFE && lma+size >= 0x10000)
	358	cpu->cpu_use_elf_start = 0;
	359	}
	360	}
	361	}
77342e5e SC	362
	363	if (elf_flags & E_M68HC12_BANKS)
	364	{
5357150c	365	if (sim_get_bank_parameters (sd) != 0)
77342e5e SC	366	sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
77342e5e SC	367	}
81e09ed8 SC	368	}
81e09ed8 SC	369
77342e5e SC	370	if (!sim_hw_configure (sd))
	371	return SIM_RC_FAIL;
	372
81e09ed8 SC	373	/* reset all state information */
	374	sim_board_reset (sd);
	375
	376	return SIM_RC_OK;
	377	}
	378
bea3f671 MF	379	static sim_cia
	380	m68hc11_pc_get (sim_cpu *cpu)
	381	{
	382	return cpu_get_pc (cpu);
	383	}
	384
	385	static void
	386	m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
	387	{
	388	cpu_set_pc (cpu, pc);
	389	}
	390
e1211e55 MF	391	static int m68hc11_reg_fetch (SIM_CPU , int, unsigned char , int);
	392	static int m68hc11_reg_store (SIM_CPU , int, unsigned char , int);
	393
e0709f50 AC	394	SIM_DESC
e0709f50 AC	395	sim_open (SIM_OPEN_KIND kind, host_callback *callback,
2e3d4f4d	396	bfd abfd, char const *argv)
e0709f50	397	{
bea3f671	398	int i;
e0709f50 AC	399	SIM_DESC sd;
e0709f50 AC	400	sim_cpu *cpu;
e0709f50 AC	401
e0709f50 AC	402	sd = sim_state_alloc (kind, callback);
e0709f50 AC	403
	404	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	405
bea3f671	406	/* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11	407	if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
bea3f671 MF	408	{
	409	free_state (sd);
	410	return 0;
	411	}
	412
	413	cpu = STATE_CPU (sd, 0);
	414
e0709f50 AC	415	cpu_initialize (sd, cpu);
e0709f50 AC	416
e0709f50	417	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
81e09ed8 SC	418	{
	419	free_state (sd);
	420	return 0;
	421	}
e0709f50	422
77cf2ef5	423	/* The parser will print an error message for us, so we silently return. */
e0709f50 AC	424	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	425	{
	426	/* Uninstall the modules to avoid memory leaks,
	427	file descriptor leaks, etc. */
81e09ed8	428	free_state (sd);
e0709f50 AC	429	return 0;
	430	}
	431
e0709f50 AC	432	/* Check for/establish the a reference program image. */
	433	if (sim_analyze_program (sd,
	434	(STATE_PROG_ARGV (sd) != NULL
	435	? *STATE_PROG_ARGV (sd)
	436	: NULL), abfd) != SIM_RC_OK)
	437	{
81e09ed8	438	free_state (sd);
e0709f50 AC	439	return 0;
	440	}
	441
	442	/* Establish any remaining configuration options. */
	443	if (sim_config (sd) != SIM_RC_OK)
	444	{
81e09ed8	445	free_state (sd);
e0709f50 AC	446	return 0;
	447	}
	448
	449	if (sim_post_argv_init (sd) != SIM_RC_OK)
	450	{
	451	/* Uninstall the modules to avoid memory leaks,
	452	file descriptor leaks, etc. */
81e09ed8	453	free_state (sd);
e0709f50 AC	454	return 0;
e0709f50 AC	455	}
77342e5e SC	456	if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
	457	{
	458	free_state (sd);
	459	return 0;
	460	}
e0709f50	461
bea3f671 MF	462	/* CPU specific initialization. */
	463	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
	464	{
	465	SIM_CPU *cpu = STATE_CPU (sd, i);
	466
e1211e55 MF	467	CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
e1211e55 MF	468	CPU_REG_STORE (cpu) = m68hc11_reg_store;
bea3f671 MF	469	CPU_PC_FETCH (cpu) = m68hc11_pc_get;
	470	CPU_PC_STORE (cpu) = m68hc11_pc_set;
	471	}
	472
e0709f50 AC	473	return sd;
	474	}
	475
e0709f50 AC	476	/* Generic implementation of sim_engine_run that works within the
	477	sim_engine setjmp/longjmp framework. */
	478
	479	void
	480	sim_engine_run (SIM_DESC sd,
	481	int next_cpu_nr, /* ignore */
	482	int nr_cpus, /* ignore */
	483	int siggnal) /* ignore */
	484	{
	485	sim_cpu *cpu;
	486
	487	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	488	cpu = STATE_CPU (sd, 0);
	489	while (1)
	490	{
	491	cpu_single_step (cpu);
	492
	493	/* process any events */
	494	if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	495	{
	496	sim_events_process (sd);
	497	}
	498	}
	499	}
	500
e0709f50 AC	501	void
	502	sim_info (SIM_DESC sd, int verbose)
	503	{
81e09ed8 SC	504	const char *cpu_type;
	505	const struct bfd_arch_info *arch;
	506
00d0c012 SC	507	/* Nothing to do if there is no verbose flag set. */
	508	if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
	509	return;
	510
81e09ed8 SC	511	arch = STATE_ARCHITECTURE (sd);
	512	if (arch->arch == bfd_arch_m68hc11)
	513	cpu_type = "68HC11";
	514	else
	515	cpu_type = "68HC12";
	516
e0709f50	517	sim_io_eprintf (sd, "Simulator info:\n");
81e09ed8	518	sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
e0709f50 AC	519	sim_get_info (sd, 0);
	520	sim_module_info (sd, verbose \|\| STATE_VERBOSE_P (sd));
	521	}
	522
	523	SIM_RC
6b4a8935	524	sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
2e3d4f4d	525	char * const argv, char const *env)
e0709f50	526	{
81e09ed8	527	return sim_prepare_for_program (sd, abfd);
e0709f50 AC	528	}
e0709f50 AC	529
e1211e55 MF	530	static int
e1211e55 MF	531	m68hc11_reg_fetch (SIM_CPU cpu, int rn, unsigned char memory, int length)
e0709f50	532	{
e0709f50	533	uint16 val;
63f36def	534	int size = 2;
e0709f50	535
e0709f50 AC	536	switch (rn)
	537	{
	538	case A_REGNUM:
	539	val = cpu_get_a (cpu);
63f36def	540	size = 1;
e0709f50 AC	541	break;
	542
	543	case B_REGNUM:
	544	val = cpu_get_b (cpu);
63f36def	545	size = 1;
e0709f50 AC	546	break;
	547
	548	case D_REGNUM:
	549	val = cpu_get_d (cpu);
	550	break;
	551
	552	case X_REGNUM:
	553	val = cpu_get_x (cpu);
	554	break;
	555
	556	case Y_REGNUM:
	557	val = cpu_get_y (cpu);
	558	break;
	559
	560	case SP_REGNUM:
	561	val = cpu_get_sp (cpu);
	562	break;
	563
	564	case PC_REGNUM:
	565	val = cpu_get_pc (cpu);
	566	break;
	567
	568	case PSW_REGNUM:
	569	val = cpu_get_ccr (cpu);
63f36def SC	570	size = 1;
	571	break;
	572
	573	case PAGE_REGNUM:
	574	val = cpu_get_page (cpu);
	575	size = 1;
e0709f50 AC	576	break;
e0709f50 AC	577
e0709f50	578	default:
9830501b	579	val = 0;
e0709f50 AC	580	break;
e0709f50 AC	581	}
00416c6e SC	582	if (size == 1)
	583	{
	584	memory[0] = val;
	585	}
	586	else
	587	{
	588	memory[0] = val >> 8;
	589	memory[1] = val & 0x0FF;
	590	}
63f36def	591	return size;
e0709f50 AC	592	}
e0709f50 AC	593
e1211e55 MF	594	static int
e1211e55 MF	595	m68hc11_reg_store (SIM_CPU cpu, int rn, unsigned char memory, int length)
e0709f50 AC	596	{
e0709f50 AC	597	uint16 val;
e0709f50 AC	598
	599	val = *memory++;
	600	if (length == 2)
	601	val = (val << 8) \| *memory;
	602
	603	switch (rn)
	604	{
	605	case D_REGNUM:
	606	cpu_set_d (cpu, val);
	607	break;
	608
	609	case A_REGNUM:
	610	cpu_set_a (cpu, val);
63f36def	611	return 1;
e0709f50 AC	612
	613	case B_REGNUM:
	614	cpu_set_b (cpu, val);
63f36def	615	return 1;
e0709f50 AC	616
	617	case X_REGNUM:
	618	cpu_set_x (cpu, val);
	619	break;
	620
	621	case Y_REGNUM:
	622	cpu_set_y (cpu, val);
	623	break;
	624
	625	case SP_REGNUM:
	626	cpu_set_sp (cpu, val);
	627	break;
	628
	629	case PC_REGNUM:
	630	cpu_set_pc (cpu, val);
	631	break;
	632
	633	case PSW_REGNUM:
	634	cpu_set_ccr (cpu, val);
63f36def SC	635	return 1;
	636
	637	case PAGE_REGNUM:
	638	cpu_set_page (cpu, val);
	639	return 1;
e0709f50	640
e0709f50	641	default:
e0709f50 AC	642	break;
	643	}
	644
	645	return 2;
	646	}