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target-sparc: Implement ALIGNADDR* inline.
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
7a3f1944
FB		 21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
7a3f1944 28#include "disas.h"
1a2fb1c0 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
7a3f1944 31
a7812ae4
PB		 32#define GEN_HELPER 1
33#include "helper.h"
34
7a3f1944
FB		 35#define DEBUG_DISAS
36
72cbca10
FB		 37#define DYNAMIC_PC 1 /* dynamic pc value */
38#define JUMP_PC 2 /* dynamic pc value which takes only two values
39 according to jump_pc[T2] */
40
1a2fb1c0 41/* global register indexes */
a7812ae4 42static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 43static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
44static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 45static TCGv_i32 cpu_psr;
46static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 47static TCGv cpu_y;
48#ifndef CONFIG_USER_ONLY
49static TCGv cpu_tbr;
50#endif
42a8aa83 51static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
dc99a3f2 52#ifdef TARGET_SPARC64
a7812ae4
PB		 53static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
54static TCGv cpu_gsr;
255e1fcb 55static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 56static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
57static TCGv_i32 cpu_softint;
255e1fcb
BS		 58#else
59static TCGv cpu_wim;
dc99a3f2 60#endif
1a2fb1c0 61/* local register indexes (only used inside old micro ops) */
a7812ae4
PB		 62static TCGv cpu_tmp0;
63static TCGv_i32 cpu_tmp32;
64static TCGv_i64 cpu_tmp64;
714547bb 65/* Floating point registers */
30038fd8 66static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 67
1a7ff922
PB		 68static target_ulong gen_opc_npc[OPC_BUF_SIZE];
69static target_ulong gen_opc_jump_pc[2];
70
2e70f6ef
PB		 71#include "gen-icount.h"
72
7a3f1944 73typedef struct DisasContext {
0f8a249a
BS		 74 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
75 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 76 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 77 int is_br;
e8af50a3 78 int mem_idx;
a80dde08 79 int fpu_enabled;
2cade6a3 80 int address_mask_32bit;
060718c1 81 int singlestep;
8393617c 82 uint32_t cc_op; /* current CC operation */
cf495bcf 83 struct TranslationBlock *tb;
5578ceab 84 sparc_def_t *def;
30038fd8
RH		 85 TCGv_i32 t32[3];
86 int n_t32;
7a3f1944
FB		 87} DisasContext;
88
3475187d 89// This function uses non-native bit order
dc1a6971
BS		 90#define GET_FIELD(X, FROM, TO) \
91 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 92
3475187d 93// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 94#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 95 GET_FIELD(X, 31 - (TO), 31 - (FROM))
96
97#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 98#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 99
100#ifdef TARGET_SPARC64
0387d928 101#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 102#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 103#else
c185970a 104#define DFPREG(r) (r & 0x1e)
1f587329 105#define QFPREG(r) (r & 0x1c)
3475187d
FB		 106#endif
107
b158a785
BS		 108#define UA2005_HTRAP_MASK 0xff
109#define V8_TRAP_MASK 0x7f
110
3475187d
FB		 111static int sign_extend(int x, int len)
112{
113 len = 32 - len;
114 return (x << len) >> len;
115}
116
7a3f1944
FB		 117#define IS_IMM (insn & (1<<13))
118
141ae5c1
RH		 119static inline void gen_update_fprs_dirty(int rd)
120{
121#if defined(TARGET_SPARC64)
122 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
123#endif
124}
125
ff07ec83 126/* floating point registers moves */
208ae657
RH		 127static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
128{
30038fd8
RH		 129#if TCG_TARGET_REG_BITS == 32
130 if (src & 1) {
131 return TCGV_LOW(cpu_fpr[src / 2]);
132 } else {
133 return TCGV_HIGH(cpu_fpr[src / 2]);
134 }
135#else
136 if (src & 1) {
137 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
138 } else {
139 TCGv_i32 ret = tcg_temp_local_new_i32();
140 TCGv_i64 t = tcg_temp_new_i64();
141
142 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
143 tcg_gen_trunc_i64_i32(ret, t);
144 tcg_temp_free_i64(t);
145
146 dc->t32[dc->n_t32++] = ret;
147 assert(dc->n_t32 <= ARRAY_SIZE(dc->t32));
148
149 return ret;
150 }
151#endif
208ae657
RH		 152}
153
154static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
155{
30038fd8
RH		 156#if TCG_TARGET_REG_BITS == 32
157 if (dst & 1) {
158 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
159 } else {
160 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
161 }
162#else
163 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
164 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
165 (dst & 1 ? 0 : 32), 32);
166#endif
141ae5c1 167 gen_update_fprs_dirty(dst);
208ae657
RH		 168}
169
170static TCGv_i32 gen_dest_fpr_F(void)
171{
172 return cpu_tmp32;
173}
174
96eda024
RH		 175static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
176{
96eda024 177 src = DFPREG(src);
30038fd8 178 return cpu_fpr[src / 2];
96eda024
RH		 179}
180
181static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
182{
183 dst = DFPREG(dst);
30038fd8 184 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 185 gen_update_fprs_dirty(dst);
186}
187
188static TCGv_i64 gen_dest_fpr_D(void)
189{
190 return cpu_tmp64;
191}
192
ff07ec83
BS		 193static void gen_op_load_fpr_QT0(unsigned int src)
194{
30038fd8
RH		 195 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
196 offsetof(CPU_QuadU, ll.upper));
197 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
198 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 199}
200
201static void gen_op_load_fpr_QT1(unsigned int src)
202{
30038fd8
RH		 203 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
204 offsetof(CPU_QuadU, ll.upper));
205 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
206 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 207}
208
209static void gen_op_store_QT0_fpr(unsigned int dst)
210{
30038fd8
RH		 211 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
212 offsetof(CPU_QuadU, ll.upper));
213 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
214 offsetof(CPU_QuadU, ll.lower));
ff07ec83 215}
1f587329 216
ac11f776 217#ifdef TARGET_SPARC64
30038fd8 218static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 219{
220 rd = QFPREG(rd);
221 rs = QFPREG(rs);
222
30038fd8
RH		 223 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
224 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 225 gen_update_fprs_dirty(rd);
226}
227#endif
228
81ad8ba2
BS		 229/* moves */
230#ifdef CONFIG_USER_ONLY
3475187d 231#define supervisor(dc) 0
81ad8ba2 232#ifdef TARGET_SPARC64
e9ebed4d 233#define hypervisor(dc) 0
81ad8ba2 234#endif
3475187d 235#else
2aae2b8e 236#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 237#ifdef TARGET_SPARC64
2aae2b8e 238#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 239#else
3475187d 240#endif
81ad8ba2
BS		 241#endif
242
2cade6a3
BS		 243#ifdef TARGET_SPARC64
244#ifndef TARGET_ABI32
245#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 246#else
2cade6a3
BS		 247#define AM_CHECK(dc) (1)
248#endif
1a2fb1c0 249#endif
3391c818 250
2cade6a3
BS		 251static inline void gen_address_mask(DisasContext *dc, TCGv addr)
252{
253#ifdef TARGET_SPARC64
254 if (AM_CHECK(dc))
255 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
256#endif
257}
258
1a2fb1c0 259static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 260{
1a2fb1c0
BS		 261 if (reg == 0)
262 tcg_gen_movi_tl(tn, 0);
263 else if (reg < 8)
f5069b26 264 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 265 else {
1a2fb1c0 266 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 267 }
268}
269
1a2fb1c0 270static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 271{
1a2fb1c0
BS		 272 if (reg == 0)
273 return;
274 else if (reg < 8)
f5069b26 275 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 276 else {
1a2fb1c0 277 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 278 }
279}
280
5fafdf24 281static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 282 target_ulong pc, target_ulong npc)
283{
284 TranslationBlock *tb;
285
286 tb = s->tb;
287 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 288 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
289 !s->singlestep) {
6e256c93 290 /* jump to same page: we can use a direct jump */
57fec1fe 291 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 292 tcg_gen_movi_tl(cpu_pc, pc);
293 tcg_gen_movi_tl(cpu_npc, npc);
4b4a72e5 294 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
6e256c93
FB		 295 } else {
296 /* jump to another page: currently not optimized */
2f5680ee
BS		 297 tcg_gen_movi_tl(cpu_pc, pc);
298 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 299 tcg_gen_exit_tb(0);
6e256c93
FB		 300 }
301}
302
19f329ad 303// XXX suboptimal
a7812ae4 304static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 305{
8911f501 306 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 307 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 308 tcg_gen_andi_tl(reg, reg, 0x1);
309}
310
a7812ae4 311static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 312{
8911f501 313 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 314 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 315 tcg_gen_andi_tl(reg, reg, 0x1);
316}
317
a7812ae4 318static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 319{
8911f501 320 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 321 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 322 tcg_gen_andi_tl(reg, reg, 0x1);
323}
324
a7812ae4 325static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 326{
8911f501 327 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 328 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 329 tcg_gen_andi_tl(reg, reg, 0x1);
330}
331
dc99a3f2
BS		 332static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
333{
a7812ae4
PB		 334 TCGv r_temp;
335 TCGv_i32 r_const;
dc99a3f2
BS		 336 int l1;
337
338 l1 = gen_new_label();
339
a7812ae4 340 r_temp = tcg_temp_new();
dc99a3f2 341 tcg_gen_xor_tl(r_temp, src1, src2);
2576d836 342 tcg_gen_not_tl(r_temp, r_temp);
0425bee5
BS		 343 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
344 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
dd5e6304 345 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
cb63669a 346 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
2ea815ca 347 r_const = tcg_const_i32(TT_TOVF);
bc265319 348 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 349 tcg_temp_free_i32(r_const);
dc99a3f2 350 gen_set_label(l1);
2ea815ca 351 tcg_temp_free(r_temp);
dc99a3f2
BS		 352}
353
dc99a3f2
BS		 354static inline void gen_tag_tv(TCGv src1, TCGv src2)
355{
356 int l1;
a7812ae4 357 TCGv_i32 r_const;
dc99a3f2
BS		 358
359 l1 = gen_new_label();
0425bee5
BS		 360 tcg_gen_or_tl(cpu_tmp0, src1, src2);
361 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
cb63669a 362 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
2ea815ca 363 r_const = tcg_const_i32(TT_TOVF);
bc265319 364 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 365 tcg_temp_free_i32(r_const);
dc99a3f2
BS		 366 gen_set_label(l1);
367}
368
41d72852
BS		 369static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
370{
371 tcg_gen_mov_tl(cpu_cc_src, src1);
372 tcg_gen_movi_tl(cpu_cc_src2, src2);
373 tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
bdf9f35d 374 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 375}
376
4af984a7 377static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 378{
4af984a7 379 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 380 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 381 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 382 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 383}
384
70c48285 385static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 386{
70c48285
RH		 387 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
388
389 /* Carry is computed from a previous add: (dst < src) */
390#if TARGET_LONG_BITS == 64
391 cc_src1_32 = tcg_temp_new_i32();
392 cc_src2_32 = tcg_temp_new_i32();
393 tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst);
394 tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src);
395#else
396 cc_src1_32 = cpu_cc_dst;
397 cc_src2_32 = cpu_cc_src;
398#endif
399
400 carry_32 = tcg_temp_new_i32();
401 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
402
403#if TARGET_LONG_BITS == 64
404 tcg_temp_free_i32(cc_src1_32);
405 tcg_temp_free_i32(cc_src2_32);
406#endif
407
408 return carry_32;
41d72852
BS		 409}
410
70c48285 411static TCGv_i32 gen_sub32_carry32(void)
41d72852 412{
70c48285
RH		 413 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
414
415 /* Carry is computed from a previous borrow: (src1 < src2) */
416#if TARGET_LONG_BITS == 64
417 cc_src1_32 = tcg_temp_new_i32();
418 cc_src2_32 = tcg_temp_new_i32();
419 tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src);
420 tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2);
421#else
422 cc_src1_32 = cpu_cc_src;
423 cc_src2_32 = cpu_cc_src2;
424#endif
425
426 carry_32 = tcg_temp_new_i32();
427 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
428
429#if TARGET_LONG_BITS == 64
430 tcg_temp_free_i32(cc_src1_32);
431 tcg_temp_free_i32(cc_src2_32);
432#endif
433
434 return carry_32;
435}
436
437static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
438 TCGv src2, int update_cc)
439{
440 TCGv_i32 carry_32;
441 TCGv carry;
442
443 switch (dc->cc_op) {
444 case CC_OP_DIV:
445 case CC_OP_LOGIC:
446 /* Carry is known to be zero. Fall back to plain ADD. */
447 if (update_cc) {
448 gen_op_add_cc(dst, src1, src2);
449 } else {
450 tcg_gen_add_tl(dst, src1, src2);
451 }
452 return;
453
454 case CC_OP_ADD:
455 case CC_OP_TADD:
456 case CC_OP_TADDTV:
457#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
458 {
459 /* For 32-bit hosts, we can re-use the host's hardware carry
460 generation by using an ADD2 opcode. We discard the low
461 part of the output. Ideally we'd combine this operation
462 with the add that generated the carry in the first place. */
463 TCGv dst_low = tcg_temp_new();
464 tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst,
465 cpu_cc_src, src1, cpu_cc_src2, src2);
466 tcg_temp_free(dst_low);
467 goto add_done;
468 }
469#endif
470 carry_32 = gen_add32_carry32();
471 break;
472
473 case CC_OP_SUB:
474 case CC_OP_TSUB:
475 case CC_OP_TSUBTV:
476 carry_32 = gen_sub32_carry32();
477 break;
478
479 default:
480 /* We need external help to produce the carry. */
481 carry_32 = tcg_temp_new_i32();
2ffd9176 482 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 483 break;
484 }
485
486#if TARGET_LONG_BITS == 64
487 carry = tcg_temp_new();
488 tcg_gen_extu_i32_i64(carry, carry_32);
489#else
490 carry = carry_32;
491#endif
492
493 tcg_gen_add_tl(dst, src1, src2);
494 tcg_gen_add_tl(dst, dst, carry);
495
496 tcg_temp_free_i32(carry_32);
497#if TARGET_LONG_BITS == 64
498 tcg_temp_free(carry);
499#endif
500
501#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
502 add_done:
503#endif
504 if (update_cc) {
505 tcg_gen_mov_tl(cpu_cc_src, src1);
506 tcg_gen_mov_tl(cpu_cc_src2, src2);
507 tcg_gen_mov_tl(cpu_cc_dst, dst);
508 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
509 dc->cc_op = CC_OP_ADDX;
510 }
dc99a3f2
BS		 511}
512
4af984a7 513static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 514{
4af984a7 515 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 516 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 517 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
5c6a0628 518 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 519}
520
4af984a7 521static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 522{
4af984a7 523 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 524 tcg_gen_mov_tl(cpu_cc_src2, src2);
525 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
5c6a0628
BS		 526 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
527 gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
5c6a0628 528 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 529}
530
dc99a3f2
BS		 531static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
532{
a7812ae4
PB		 533 TCGv r_temp;
534 TCGv_i32 r_const;
dc99a3f2
BS		 535 int l1;
536
537 l1 = gen_new_label();
538
a7812ae4 539 r_temp = tcg_temp_new();
dc99a3f2 540 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 541 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
542 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
dd5e6304 543 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
cb63669a 544 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
2ea815ca 545 r_const = tcg_const_i32(TT_TOVF);
bc265319 546 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 547 tcg_temp_free_i32(r_const);
dc99a3f2 548 gen_set_label(l1);
2ea815ca 549 tcg_temp_free(r_temp);
dc99a3f2
BS		 550}
551
d4b0d468 552static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
41d72852
BS		 553{
554 tcg_gen_mov_tl(cpu_cc_src, src1);
555 tcg_gen_movi_tl(cpu_cc_src2, src2);
719f66a7 556 if (src2 == 0) {
d4b0d468
BS		 557 tcg_gen_mov_tl(cpu_cc_dst, src1);
558 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
559 dc->cc_op = CC_OP_LOGIC;
719f66a7
BS		 560 } else {
561 tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
d4b0d468
BS		 562 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
563 dc->cc_op = CC_OP_SUB;
719f66a7 564 }
d4b0d468 565 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 566}
567
568static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 569{
4af984a7 570 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 571 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 572 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 573 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 574}
575
70c48285
RH		 576static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
577 TCGv src2, int update_cc)
41d72852 578{
70c48285
RH		 579 TCGv_i32 carry_32;
580 TCGv carry;
41d72852 581
70c48285
RH		 582 switch (dc->cc_op) {
583 case CC_OP_DIV:
584 case CC_OP_LOGIC:
585 /* Carry is known to be zero. Fall back to plain SUB. */
586 if (update_cc) {
587 gen_op_sub_cc(dst, src1, src2);
588 } else {
589 tcg_gen_sub_tl(dst, src1, src2);
590 }
591 return;
592
593 case CC_OP_ADD:
594 case CC_OP_TADD:
595 case CC_OP_TADDTV:
596 carry_32 = gen_add32_carry32();
597 break;
598
599 case CC_OP_SUB:
600 case CC_OP_TSUB:
601 case CC_OP_TSUBTV:
602#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
603 {
604 /* For 32-bit hosts, we can re-use the host's hardware carry
605 generation by using a SUB2 opcode. We discard the low
606 part of the output. Ideally we'd combine this operation
607 with the add that generated the carry in the first place. */
608 TCGv dst_low = tcg_temp_new();
609 tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst,
610 cpu_cc_src, src1, cpu_cc_src2, src2);
611 tcg_temp_free(dst_low);
612 goto sub_done;
613 }
614#endif
615 carry_32 = gen_sub32_carry32();
616 break;
617
618 default:
619 /* We need external help to produce the carry. */
620 carry_32 = tcg_temp_new_i32();
2ffd9176 621 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 622 break;
623 }
624
625#if TARGET_LONG_BITS == 64
626 carry = tcg_temp_new();
627 tcg_gen_extu_i32_i64(carry, carry_32);
628#else
629 carry = carry_32;
630#endif
631
632 tcg_gen_sub_tl(dst, src1, src2);
633 tcg_gen_sub_tl(dst, dst, carry);
634
635 tcg_temp_free_i32(carry_32);
636#if TARGET_LONG_BITS == 64
637 tcg_temp_free(carry);
638#endif
639
640#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
641 sub_done:
642#endif
643 if (update_cc) {
644 tcg_gen_mov_tl(cpu_cc_src, src1);
645 tcg_gen_mov_tl(cpu_cc_src2, src2);
646 tcg_gen_mov_tl(cpu_cc_dst, dst);
647 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
648 dc->cc_op = CC_OP_SUBX;
649 }
dc99a3f2
BS		 650}
651
4af984a7 652static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 653{
4af984a7 654 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 655 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 656 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
5c6a0628 657 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 658}
659
4af984a7 660static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 661{
4af984a7 662 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 663 tcg_gen_mov_tl(cpu_cc_src2, src2);
664 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
5c6a0628
BS		 665 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
666 gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
5c6a0628 667 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 668}
669
4af984a7 670static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 671{
105a1f04 672 TCGv r_temp;
6f551262 673 int l1;
d9bdab86
BS		 674
675 l1 = gen_new_label();
a7812ae4 676 r_temp = tcg_temp_new();
d9bdab86
BS		 677
678 /* old op:
679 if (!(env->y & 1))
680 T1 = 0;
681 */
72ccba79 682 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 683 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 684 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
105a1f04 685 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
d9bdab86 686 tcg_gen_movi_tl(cpu_cc_src2, 0);
6f551262 687 gen_set_label(l1);
d9bdab86
BS		 688
689 // b2 = T0 & 1;
690 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 691 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
692 tcg_gen_shli_tl(r_temp, r_temp, 31);
255e1fcb 693 tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
72ccba79 694 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
5068cbd9
BS		 695 tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
696 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
d9bdab86
BS		 697
698 // b1 = N ^ V;
699 gen_mov_reg_N(cpu_tmp0, cpu_psr);
700 gen_mov_reg_V(r_temp, cpu_psr);
701 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
2ea815ca 702 tcg_temp_free(r_temp);
d9bdab86
BS		 703
704 // T0 = (b1 << 31) | (T0 >> 1);
705 // src1 = T0;
706 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
6f551262 707 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
d9bdab86
BS		 708 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
709
5c6a0628 710 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 711
5c6a0628 712 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 713}
714
fb170183 715static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 716{
fb170183 717 TCGv_i32 r_src1, r_src2;
a7812ae4 718 TCGv_i64 r_temp, r_temp2;
8879d139 719
fb170183
IK		 720 r_src1 = tcg_temp_new_i32();
721 r_src2 = tcg_temp_new_i32();
722
723 tcg_gen_trunc_tl_i32(r_src1, src1);
724 tcg_gen_trunc_tl_i32(r_src2, src2);
725
a7812ae4
PB		 726 r_temp = tcg_temp_new_i64();
727 r_temp2 = tcg_temp_new_i64();
8879d139 728
fb170183
IK		 729 if (sign_ext) {
730 tcg_gen_ext_i32_i64(r_temp, r_src2);
731 tcg_gen_ext_i32_i64(r_temp2, r_src1);
732 } else {
733 tcg_gen_extu_i32_i64(r_temp, r_src2);
734 tcg_gen_extu_i32_i64(r_temp2, r_src1);
735 }
736
8879d139
BS		 737 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
738
739 tcg_gen_shri_i64(r_temp, r_temp2, 32);
105a1f04 740 tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
a7812ae4 741 tcg_temp_free_i64(r_temp);
255e1fcb 742 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
fb170183 743
4af984a7 744 tcg_gen_trunc_i64_tl(dst, r_temp2);
fb170183 745
a7812ae4 746 tcg_temp_free_i64(r_temp2);
fb170183
IK		 747
748 tcg_temp_free_i32(r_src1);
749 tcg_temp_free_i32(r_src2);
8879d139
BS		 750}
751
fb170183 752static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 753{
fb170183
IK		 754 /* zero-extend truncated operands before multiplication */
755 gen_op_multiply(dst, src1, src2, 0);
756}
8879d139 757
fb170183
IK		 758static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
759{
760 /* sign-extend truncated operands before multiplication */
761 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 762}
763
1a7b60e7 764#ifdef TARGET_SPARC64
8911f501 765static inline void gen_trap_ifdivzero_tl(TCGv divisor)
1a7b60e7 766{
a7812ae4 767 TCGv_i32 r_const;
1a7b60e7
BS		 768 int l1;
769
770 l1 = gen_new_label();
cb63669a 771 tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
2ea815ca 772 r_const = tcg_const_i32(TT_DIV_ZERO);
bc265319 773 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 774 tcg_temp_free_i32(r_const);
1a7b60e7
BS		 775 gen_set_label(l1);
776}
777
4af984a7 778static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
1a7b60e7
BS		 779{
780 int l1, l2;
8e91ed30 781 TCGv r_temp1, r_temp2;
1a7b60e7
BS		 782
783 l1 = gen_new_label();
784 l2 = gen_new_label();
8e91ed30
AT		 785 r_temp1 = tcg_temp_local_new();
786 r_temp2 = tcg_temp_local_new();
787 tcg_gen_mov_tl(r_temp1, src1);
788 tcg_gen_mov_tl(r_temp2, src2);
789 gen_trap_ifdivzero_tl(r_temp2);
790 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp1, INT64_MIN, l1);
791 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp2, -1, l1);
4af984a7 792 tcg_gen_movi_i64(dst, INT64_MIN);
06b3e1b3 793 tcg_gen_br(l2);
1a7b60e7 794 gen_set_label(l1);
8e91ed30 795 tcg_gen_div_i64(dst, r_temp1, r_temp2);
1a7b60e7 796 gen_set_label(l2);
8e91ed30
AT		 797 tcg_temp_free(r_temp1);
798 tcg_temp_free(r_temp2);
1a7b60e7
BS		 799}
800#endif
801
19f329ad
BS		 802// 1
803static inline void gen_op_eval_ba(TCGv dst)
804{
805 tcg_gen_movi_tl(dst, 1);
806}
807
808// Z
a7812ae4 809static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 810{
811 gen_mov_reg_Z(dst, src);
812}
813
814// Z | (N ^ V)
a7812ae4 815static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 816{
0425bee5 817 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 818 gen_mov_reg_V(dst, src);
0425bee5
BS		 819 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
820 gen_mov_reg_Z(cpu_tmp0, src);
821 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 822}
823
824// N ^ V
a7812ae4 825static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 826{
0425bee5 827 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 828 gen_mov_reg_N(dst, src);
0425bee5 829 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 830}
831
832// C | Z
a7812ae4 833static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 834{
0425bee5 835 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 836 gen_mov_reg_C(dst, src);
0425bee5 837 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 838}
839
840// C
a7812ae4 841static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 842{
843 gen_mov_reg_C(dst, src);
844}
845
846// V
a7812ae4 847static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 848{
849 gen_mov_reg_V(dst, src);
850}
851
852// 0
853static inline void gen_op_eval_bn(TCGv dst)
854{
855 tcg_gen_movi_tl(dst, 0);
856}
857
858// N
a7812ae4 859static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 860{
861 gen_mov_reg_N(dst, src);
862}
863
864// !Z
a7812ae4 865static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 866{
867 gen_mov_reg_Z(dst, src);
868 tcg_gen_xori_tl(dst, dst, 0x1);
869}
870
871// !(Z | (N ^ V))
a7812ae4 872static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 873{
0425bee5 874 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 875 gen_mov_reg_V(dst, src);
0425bee5
BS		 876 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
877 gen_mov_reg_Z(cpu_tmp0, src);
878 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 879 tcg_gen_xori_tl(dst, dst, 0x1);
880}
881
882// !(N ^ V)
a7812ae4 883static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 884{
0425bee5 885 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 886 gen_mov_reg_N(dst, src);
0425bee5 887 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 888 tcg_gen_xori_tl(dst, dst, 0x1);
889}
890
891// !(C | Z)
a7812ae4 892static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 893{
0425bee5 894 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 895 gen_mov_reg_C(dst, src);
0425bee5 896 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 897 tcg_gen_xori_tl(dst, dst, 0x1);
898}
899
900// !C
a7812ae4 901static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 902{
903 gen_mov_reg_C(dst, src);
904 tcg_gen_xori_tl(dst, dst, 0x1);
905}
906
907// !N
a7812ae4 908static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 909{
910 gen_mov_reg_N(dst, src);
911 tcg_gen_xori_tl(dst, dst, 0x1);
912}
913
914// !V
a7812ae4 915static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 916{
917 gen_mov_reg_V(dst, src);
918 tcg_gen_xori_tl(dst, dst, 0x1);
919}
920
921/*
922 FPSR bit field FCC1 | FCC0:
923 0 =
924 1 <
925 2 >
926 3 unordered
927*/
928static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
929 unsigned int fcc_offset)
930{
ba6a9d8c 931 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 932 tcg_gen_andi_tl(reg, reg, 0x1);
933}
934
935static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
936 unsigned int fcc_offset)
937{
ba6a9d8c 938 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 939 tcg_gen_andi_tl(reg, reg, 0x1);
940}
941
942// !0: FCC0 | FCC1
943static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
944 unsigned int fcc_offset)
945{
19f329ad 946 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 947 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
948 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 949}
950
951// 1 or 2: FCC0 ^ FCC1
952static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
953 unsigned int fcc_offset)
954{
19f329ad 955 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 956 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
957 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 958}
959
960// 1 or 3: FCC0
961static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
962 unsigned int fcc_offset)
963{
964 gen_mov_reg_FCC0(dst, src, fcc_offset);
965}
966
967// 1: FCC0 & !FCC1
968static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
969 unsigned int fcc_offset)
970{
19f329ad 971 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 972 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
973 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
974 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 975}
976
977// 2 or 3: FCC1
978static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
979 unsigned int fcc_offset)
980{
981 gen_mov_reg_FCC1(dst, src, fcc_offset);
982}
983
984// 2: !FCC0 & FCC1
985static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
986 unsigned int fcc_offset)
987{
19f329ad
BS		 988 gen_mov_reg_FCC0(dst, src, fcc_offset);
989 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 990 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
991 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 992}
993
994// 3: FCC0 & FCC1
995static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
996 unsigned int fcc_offset)
997{
19f329ad 998 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 999 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1000 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1001}
1002
1003// 0: !(FCC0 | FCC1)
1004static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1005 unsigned int fcc_offset)
1006{
19f329ad 1007 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1008 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1009 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1010 tcg_gen_xori_tl(dst, dst, 0x1);
1011}
1012
1013// 0 or 3: !(FCC0 ^ FCC1)
1014static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1015 unsigned int fcc_offset)
1016{
19f329ad 1017 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1018 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1019 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1020 tcg_gen_xori_tl(dst, dst, 0x1);
1021}
1022
1023// 0 or 2: !FCC0
1024static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1025 unsigned int fcc_offset)
1026{
1027 gen_mov_reg_FCC0(dst, src, fcc_offset);
1028 tcg_gen_xori_tl(dst, dst, 0x1);
1029}
1030
1031// !1: !(FCC0 & !FCC1)
1032static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1033 unsigned int fcc_offset)
1034{
19f329ad 1035 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1036 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1037 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1038 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1039 tcg_gen_xori_tl(dst, dst, 0x1);
1040}
1041
1042// 0 or 1: !FCC1
1043static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1044 unsigned int fcc_offset)
1045{
1046 gen_mov_reg_FCC1(dst, src, fcc_offset);
1047 tcg_gen_xori_tl(dst, dst, 0x1);
1048}
1049
1050// !2: !(!FCC0 & FCC1)
1051static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1052 unsigned int fcc_offset)
1053{
19f329ad
BS		 1054 gen_mov_reg_FCC0(dst, src, fcc_offset);
1055 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1056 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1057 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1058 tcg_gen_xori_tl(dst, dst, 0x1);
1059}
1060
1061// !3: !(FCC0 & FCC1)
1062static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1063 unsigned int fcc_offset)
1064{
19f329ad 1065 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1066 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1067 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1068 tcg_gen_xori_tl(dst, dst, 0x1);
1069}
1070
46525e1f 1071static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1072 target_ulong pc2, TCGv r_cond)
83469015
FB		 1073{
1074 int l1;
1075
1076 l1 = gen_new_label();
1077
cb63669a 1078 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1079
6e256c93 1080 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1081
1082 gen_set_label(l1);
6e256c93 1083 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1084}
1085
46525e1f 1086static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1087 target_ulong pc2, TCGv r_cond)
83469015
FB		 1088{
1089 int l1;
1090
1091 l1 = gen_new_label();
1092
cb63669a 1093 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1094
6e256c93 1095 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1096
1097 gen_set_label(l1);
6e256c93 1098 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1099}
1100
19f329ad
BS		 1101static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1102 TCGv r_cond)
83469015
FB		 1103{
1104 int l1, l2;
1105
1106 l1 = gen_new_label();
1107 l2 = gen_new_label();
19f329ad 1108
cb63669a 1109 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1110
2f5680ee 1111 tcg_gen_movi_tl(cpu_npc, npc1);
06b3e1b3 1112 tcg_gen_br(l2);
83469015
FB		 1113
1114 gen_set_label(l1);
2f5680ee 1115 tcg_gen_movi_tl(cpu_npc, npc2);
83469015
FB		 1116 gen_set_label(l2);
1117}
1118
4af984a7
BS		 1119/* call this function before using the condition register as it may
1120 have been set for a jump */
1121static inline void flush_cond(DisasContext *dc, TCGv cond)
83469015
FB		 1122{
1123 if (dc->npc == JUMP_PC) {
4af984a7 1124 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
83469015
FB		 1125 dc->npc = DYNAMIC_PC;
1126 }
1127}
1128
4af984a7 1129static inline void save_npc(DisasContext *dc, TCGv cond)
72cbca10
FB		 1130{
1131 if (dc->npc == JUMP_PC) {
4af984a7 1132 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
72cbca10
FB		 1133 dc->npc = DYNAMIC_PC;
1134 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1135 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1136 }
1137}
1138
4af984a7 1139static inline void save_state(DisasContext *dc, TCGv cond)
72cbca10 1140{
2f5680ee 1141 tcg_gen_movi_tl(cpu_pc, dc->pc);
cfa90513
BS		 1142 /* flush pending conditional evaluations before exposing cpu state */
1143 if (dc->cc_op != CC_OP_FLAGS) {
1144 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1145 gen_helper_compute_psr(cpu_env);
cfa90513 1146 }
4af984a7 1147 save_npc(dc, cond);
72cbca10
FB		 1148}
1149
4af984a7 1150static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
0bee699e
FB		 1151{
1152 if (dc->npc == JUMP_PC) {
4af984a7 1153 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
48d5c82b 1154 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1155 dc->pc = DYNAMIC_PC;
1156 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1157 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1158 dc->pc = DYNAMIC_PC;
1159 } else {
1160 dc->pc = dc->npc;
1161 }
1162}
1163
38bc628b
BS		 1164static inline void gen_op_next_insn(void)
1165{
48d5c82b
BS		 1166 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1167 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1168}
1169
8393617c
BS		 1170static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1171 DisasContext *dc)
19f329ad 1172{
a7812ae4 1173 TCGv_i32 r_src;
3475187d 1174
3475187d 1175#ifdef TARGET_SPARC64
19f329ad 1176 if (cc)
dc99a3f2 1177 r_src = cpu_xcc;
19f329ad 1178 else
dc99a3f2 1179 r_src = cpu_psr;
3475187d 1180#else
dc99a3f2 1181 r_src = cpu_psr;
3475187d 1182#endif
8393617c
BS		 1183 switch (dc->cc_op) {
1184 case CC_OP_FLAGS:
1185 break;
1186 default:
2ffd9176 1187 gen_helper_compute_psr(cpu_env);
8393617c
BS		 1188 dc->cc_op = CC_OP_FLAGS;
1189 break;
1190 }
19f329ad
BS		 1191 switch (cond) {
1192 case 0x0:
1193 gen_op_eval_bn(r_dst);
1194 break;
1195 case 0x1:
1196 gen_op_eval_be(r_dst, r_src);
1197 break;
1198 case 0x2:
1199 gen_op_eval_ble(r_dst, r_src);
1200 break;
1201 case 0x3:
1202 gen_op_eval_bl(r_dst, r_src);
1203 break;
1204 case 0x4:
1205 gen_op_eval_bleu(r_dst, r_src);
1206 break;
1207 case 0x5:
1208 gen_op_eval_bcs(r_dst, r_src);
1209 break;
1210 case 0x6:
1211 gen_op_eval_bneg(r_dst, r_src);
1212 break;
1213 case 0x7:
1214 gen_op_eval_bvs(r_dst, r_src);
1215 break;
1216 case 0x8:
1217 gen_op_eval_ba(r_dst);
1218 break;
1219 case 0x9:
1220 gen_op_eval_bne(r_dst, r_src);
1221 break;
1222 case 0xa:
1223 gen_op_eval_bg(r_dst, r_src);
1224 break;
1225 case 0xb:
1226 gen_op_eval_bge(r_dst, r_src);
1227 break;
1228 case 0xc:
1229 gen_op_eval_bgu(r_dst, r_src);
1230 break;
1231 case 0xd:
1232 gen_op_eval_bcc(r_dst, r_src);
1233 break;
1234 case 0xe:
1235 gen_op_eval_bpos(r_dst, r_src);
1236 break;
1237 case 0xf:
1238 gen_op_eval_bvc(r_dst, r_src);
1239 break;
1240 }
1241}
7a3f1944 1242
19f329ad 1243static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1244{
19f329ad
BS		 1245 unsigned int offset;
1246
19f329ad
BS		 1247 switch (cc) {
1248 default:
1249 case 0x0:
1250 offset = 0;
1251 break;
1252 case 0x1:
1253 offset = 32 - 10;
1254 break;
1255 case 0x2:
1256 offset = 34 - 10;
1257 break;
1258 case 0x3:
1259 offset = 36 - 10;
1260 break;
1261 }
1262
1263 switch (cond) {
1264 case 0x0:
1265 gen_op_eval_bn(r_dst);
1266 break;
1267 case 0x1:
87e92502 1268 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1269 break;
1270 case 0x2:
87e92502 1271 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1272 break;
1273 case 0x3:
87e92502 1274 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1275 break;
1276 case 0x4:
87e92502 1277 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1278 break;
1279 case 0x5:
87e92502 1280 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1281 break;
1282 case 0x6:
87e92502 1283 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1284 break;
1285 case 0x7:
87e92502 1286 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1287 break;
1288 case 0x8:
1289 gen_op_eval_ba(r_dst);
1290 break;
1291 case 0x9:
87e92502 1292 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1293 break;
1294 case 0xa:
87e92502 1295 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1296 break;
1297 case 0xb:
87e92502 1298 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1299 break;
1300 case 0xc:
87e92502 1301 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1302 break;
1303 case 0xd:
87e92502 1304 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1305 break;
1306 case 0xe:
87e92502 1307 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1308 break;
1309 case 0xf:
87e92502 1310 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1311 break;
1312 }
e8af50a3 1313}
00f219bf 1314
19f329ad 1315#ifdef TARGET_SPARC64
00f219bf
BS		 1316// Inverted logic
1317static const int gen_tcg_cond_reg[8] = {
1318 -1,
1319 TCG_COND_NE,
1320 TCG_COND_GT,
1321 TCG_COND_GE,
1322 -1,
1323 TCG_COND_EQ,
1324 TCG_COND_LE,
1325 TCG_COND_LT,
1326};
19f329ad 1327
4af984a7 1328static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1329{
19f329ad
BS		 1330 int l1;
1331
1332 l1 = gen_new_label();
0425bee5 1333 tcg_gen_movi_tl(r_dst, 0);
cb63669a 1334 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
19f329ad
BS		 1335 tcg_gen_movi_tl(r_dst, 1);
1336 gen_set_label(l1);
1337}
3475187d 1338#endif
cf495bcf 1339
4af984a7
BS		 1340static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1341 TCGv r_cond)
7a3f1944 1342{
cf495bcf 1343 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1344 target_ulong target = dc->pc + offset;
5fafdf24 1345
cf495bcf 1346 if (cond == 0x0) {
0f8a249a
BS		 1347 /* unconditional not taken */
1348 if (a) {
1349 dc->pc = dc->npc + 4;
1350 dc->npc = dc->pc + 4;
1351 } else {
1352 dc->pc = dc->npc;
1353 dc->npc = dc->pc + 4;
1354 }
cf495bcf 1355 } else if (cond == 0x8) {
0f8a249a
BS		 1356 /* unconditional taken */
1357 if (a) {
1358 dc->pc = target;
1359 dc->npc = dc->pc + 4;
1360 } else {
1361 dc->pc = dc->npc;
1362 dc->npc = target;
c27e2752 1363 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1364 }
cf495bcf 1365 } else {
4af984a7 1366 flush_cond(dc, r_cond);
8393617c 1367 gen_cond(r_cond, cc, cond, dc);
0f8a249a 1368 if (a) {
4af984a7 1369 gen_branch_a(dc, target, dc->npc, r_cond);
cf495bcf 1370 dc->is_br = 1;
0f8a249a 1371 } else {
cf495bcf 1372 dc->pc = dc->npc;
72cbca10 1373 dc->jump_pc[0] = target;
548f66db
AT		 1374 if (unlikely(dc->npc == DYNAMIC_PC)) {
1375 dc->jump_pc[1] = DYNAMIC_PC;
1376 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1377 } else {
1378 dc->jump_pc[1] = dc->npc + 4;
1379 dc->npc = JUMP_PC;
1380 }
0f8a249a 1381 }
cf495bcf 1382 }
7a3f1944
FB		 1383}
1384
4af984a7
BS		 1385static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1386 TCGv r_cond)
e8af50a3
FB		 1387{
1388 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1389 target_ulong target = dc->pc + offset;
1390
e8af50a3 1391 if (cond == 0x0) {
0f8a249a
BS		 1392 /* unconditional not taken */
1393 if (a) {
1394 dc->pc = dc->npc + 4;
1395 dc->npc = dc->pc + 4;
1396 } else {
1397 dc->pc = dc->npc;
1398 dc->npc = dc->pc + 4;
1399 }
e8af50a3 1400 } else if (cond == 0x8) {
0f8a249a
BS		 1401 /* unconditional taken */
1402 if (a) {
1403 dc->pc = target;
1404 dc->npc = dc->pc + 4;
1405 } else {
1406 dc->pc = dc->npc;
1407 dc->npc = target;
c27e2752 1408 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1409 }
e8af50a3 1410 } else {
4af984a7
BS		 1411 flush_cond(dc, r_cond);
1412 gen_fcond(r_cond, cc, cond);
0f8a249a 1413 if (a) {
4af984a7 1414 gen_branch_a(dc, target, dc->npc, r_cond);
e8af50a3 1415 dc->is_br = 1;
0f8a249a 1416 } else {
e8af50a3
FB		 1417 dc->pc = dc->npc;
1418 dc->jump_pc[0] = target;
548f66db
AT		 1419 if (unlikely(dc->npc == DYNAMIC_PC)) {
1420 dc->jump_pc[1] = DYNAMIC_PC;
1421 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1422 } else {
1423 dc->jump_pc[1] = dc->npc + 4;
1424 dc->npc = JUMP_PC;
1425 }
0f8a249a 1426 }
e8af50a3
FB		 1427 }
1428}
1429
3475187d 1430#ifdef TARGET_SPARC64
4af984a7
BS		 1431static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1432 TCGv r_cond, TCGv r_reg)
7a3f1944 1433{
3475187d
FB		 1434 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1435 target_ulong target = dc->pc + offset;
1436
4af984a7
BS		 1437 flush_cond(dc, r_cond);
1438 gen_cond_reg(r_cond, cond, r_reg);
3475187d 1439 if (a) {
4af984a7 1440 gen_branch_a(dc, target, dc->npc, r_cond);
0f8a249a 1441 dc->is_br = 1;
3475187d 1442 } else {
0f8a249a
BS		 1443 dc->pc = dc->npc;
1444 dc->jump_pc[0] = target;
548f66db
AT		 1445 if (unlikely(dc->npc == DYNAMIC_PC)) {
1446 dc->jump_pc[1] = DYNAMIC_PC;
1447 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1448 } else {
1449 dc->jump_pc[1] = dc->npc + 4;
1450 dc->npc = JUMP_PC;
1451 }
3475187d 1452 }
7a3f1944
FB		 1453}
1454
a7812ae4 1455static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1456{
714547bb
BS		 1457 switch (fccno) {
1458 case 0:
2e2f4ade 1459 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1460 break;
1461 case 1:
2e2f4ade 1462 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1463 break;
1464 case 2:
2e2f4ade 1465 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1466 break;
1467 case 3:
2e2f4ade 1468 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1469 break;
1470 }
7e8c2b6c
BS		 1471}
1472
03fb8cfc 1473static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1474{
a7812ae4
PB		 1475 switch (fccno) {
1476 case 0:
03fb8cfc 1477 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1478 break;
1479 case 1:
03fb8cfc 1480 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1481 break;
1482 case 2:
03fb8cfc 1483 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1484 break;
1485 case 3:
03fb8cfc 1486 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1487 break;
1488 }
7e8c2b6c
BS		 1489}
1490
7e8c2b6c
BS		 1491static inline void gen_op_fcmpq(int fccno)
1492{
a7812ae4
PB		 1493 switch (fccno) {
1494 case 0:
2e2f4ade 1495 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1496 break;
1497 case 1:
2e2f4ade 1498 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1499 break;
1500 case 2:
2e2f4ade 1501 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1502 break;
1503 case 3:
2e2f4ade 1504 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1505 break;
1506 }
7e8c2b6c 1507}
7e8c2b6c 1508
a7812ae4 1509static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1510{
714547bb
BS		 1511 switch (fccno) {
1512 case 0:
2e2f4ade 1513 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1514 break;
1515 case 1:
2e2f4ade 1516 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1517 break;
1518 case 2:
2e2f4ade 1519 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1520 break;
1521 case 3:
2e2f4ade 1522 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1523 break;
1524 }
7e8c2b6c
BS		 1525}
1526
03fb8cfc 1527static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1528{
a7812ae4
PB		 1529 switch (fccno) {
1530 case 0:
03fb8cfc 1531 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1532 break;
1533 case 1:
03fb8cfc 1534 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1535 break;
1536 case 2:
03fb8cfc 1537 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1538 break;
1539 case 3:
03fb8cfc 1540 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1541 break;
1542 }
7e8c2b6c
BS		 1543}
1544
7e8c2b6c
BS		 1545static inline void gen_op_fcmpeq(int fccno)
1546{
a7812ae4
PB		 1547 switch (fccno) {
1548 case 0:
2e2f4ade 1549 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1550 break;
1551 case 1:
2e2f4ade 1552 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1553 break;
1554 case 2:
2e2f4ade 1555 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1556 break;
1557 case 3:
2e2f4ade 1558 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1559 break;
1560 }
7e8c2b6c 1561}
7e8c2b6c
BS		 1562
1563#else
1564
714547bb 1565static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1566{
2e2f4ade 1567 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1568}
1569
03fb8cfc 1570static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1571{
03fb8cfc 1572 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1573}
1574
7e8c2b6c
BS		 1575static inline void gen_op_fcmpq(int fccno)
1576{
2e2f4ade 1577 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1578}
7e8c2b6c 1579
714547bb 1580static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1581{
2e2f4ade 1582 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1583}
1584
03fb8cfc 1585static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1586{
03fb8cfc 1587 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1588}
1589
7e8c2b6c
BS		 1590static inline void gen_op_fcmpeq(int fccno)
1591{
2e2f4ade 1592 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1593}
1594#endif
1595
134d77a1
BS		 1596static inline void gen_op_fpexception_im(int fsr_flags)
1597{
a7812ae4 1598 TCGv_i32 r_const;
2ea815ca 1599
47ad35f1 1600 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1601 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1602 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1603 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1604 tcg_temp_free_i32(r_const);
134d77a1
BS		 1605}
1606
4af984a7 1607static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
a80dde08
FB		 1608{
1609#if !defined(CONFIG_USER_ONLY)
1610 if (!dc->fpu_enabled) {
a7812ae4 1611 TCGv_i32 r_const;
2ea815ca 1612
4af984a7 1613 save_state(dc, r_cond);
2ea815ca 1614 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1615 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1616 tcg_temp_free_i32(r_const);
a80dde08
FB		 1617 dc->is_br = 1;
1618 return 1;
1619 }
1620#endif
1621 return 0;
1622}
1623
7e8c2b6c
BS		 1624static inline void gen_op_clear_ieee_excp_and_FTT(void)
1625{
47ad35f1 1626 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1627}
1628
61f17f6e
RH		 1629static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1630 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1631{
1632 TCGv_i32 dst, src;
1633
61f17f6e
RH		 1634 src = gen_load_fpr_F(dc, rs);
1635 dst = gen_dest_fpr_F();
1636
1637 gen(dst, cpu_env, src);
1638
61f17f6e
RH		 1639 gen_store_fpr_F(dc, rd, dst);
1640}
1641
1642static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1643 void (*gen)(TCGv_i32, TCGv_i32))
1644{
1645 TCGv_i32 dst, src;
1646
1647 src = gen_load_fpr_F(dc, rs);
1648 dst = gen_dest_fpr_F();
1649
1650 gen(dst, src);
1651
1652 gen_store_fpr_F(dc, rd, dst);
1653}
1654
1655static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1656 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1657{
1658 TCGv_i32 dst, src1, src2;
1659
61f17f6e
RH		 1660 src1 = gen_load_fpr_F(dc, rs1);
1661 src2 = gen_load_fpr_F(dc, rs2);
1662 dst = gen_dest_fpr_F();
1663
1664 gen(dst, cpu_env, src1, src2);
1665
61f17f6e
RH		 1666 gen_store_fpr_F(dc, rd, dst);
1667}
1668
1669#ifdef TARGET_SPARC64
1670static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1671 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1672{
1673 TCGv_i32 dst, src1, src2;
1674
1675 src1 = gen_load_fpr_F(dc, rs1);
1676 src2 = gen_load_fpr_F(dc, rs2);
1677 dst = gen_dest_fpr_F();
1678
1679 gen(dst, src1, src2);
1680
1681 gen_store_fpr_F(dc, rd, dst);
1682}
1683#endif
1684
1685static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1686 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1687{
1688 TCGv_i64 dst, src;
1689
61f17f6e
RH		 1690 src = gen_load_fpr_D(dc, rs);
1691 dst = gen_dest_fpr_D();
1692
1693 gen(dst, cpu_env, src);
1694
61f17f6e
RH		 1695 gen_store_fpr_D(dc, rd, dst);
1696}
1697
1698#ifdef TARGET_SPARC64
1699static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1700 void (*gen)(TCGv_i64, TCGv_i64))
1701{
1702 TCGv_i64 dst, src;
1703
1704 src = gen_load_fpr_D(dc, rs);
1705 dst = gen_dest_fpr_D();
1706
1707 gen(dst, src);
1708
1709 gen_store_fpr_D(dc, rd, dst);
1710}
1711#endif
1712
1713static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1714 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1715{
1716 TCGv_i64 dst, src1, src2;
1717
61f17f6e
RH		 1718 src1 = gen_load_fpr_D(dc, rs1);
1719 src2 = gen_load_fpr_D(dc, rs2);
1720 dst = gen_dest_fpr_D();
1721
1722 gen(dst, cpu_env, src1, src2);
1723
61f17f6e
RH		 1724 gen_store_fpr_D(dc, rd, dst);
1725}
1726
1727#ifdef TARGET_SPARC64
1728static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1729 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1730{
1731 TCGv_i64 dst, src1, src2;
1732
1733 src1 = gen_load_fpr_D(dc, rs1);
1734 src2 = gen_load_fpr_D(dc, rs2);
1735 dst = gen_dest_fpr_D();
1736
1737 gen(dst, src1, src2);
1738
1739 gen_store_fpr_D(dc, rd, dst);
1740}
f888300b 1741
2dedf314
RH		 1742static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1743 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1744{
1745 TCGv_i64 dst, src1, src2;
1746
1747 src1 = gen_load_fpr_D(dc, rs1);
1748 src2 = gen_load_fpr_D(dc, rs2);
1749 dst = gen_dest_fpr_D();
1750
1751 gen(dst, cpu_gsr, src1, src2);
1752
1753 gen_store_fpr_D(dc, rd, dst);
1754}
1755
f888300b
RH		 1756static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1757 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1758{
1759 TCGv_i64 dst, src0, src1, src2;
1760
1761 src1 = gen_load_fpr_D(dc, rs1);
1762 src2 = gen_load_fpr_D(dc, rs2);
1763 src0 = gen_load_fpr_D(dc, rd);
1764 dst = gen_dest_fpr_D();
1765
1766 gen(dst, src0, src1, src2);
1767
1768 gen_store_fpr_D(dc, rd, dst);
1769}
61f17f6e
RH		 1770#endif
1771
1772static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1773 void (*gen)(TCGv_ptr))
1774{
61f17f6e
RH		 1775 gen_op_load_fpr_QT1(QFPREG(rs));
1776
1777 gen(cpu_env);
1778
61f17f6e
RH		 1779 gen_op_store_QT0_fpr(QFPREG(rd));
1780 gen_update_fprs_dirty(QFPREG(rd));
1781}
1782
1783#ifdef TARGET_SPARC64
1784static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1785 void (*gen)(TCGv_ptr))
1786{
1787 gen_op_load_fpr_QT1(QFPREG(rs));
1788
1789 gen(cpu_env);
1790
1791 gen_op_store_QT0_fpr(QFPREG(rd));
1792 gen_update_fprs_dirty(QFPREG(rd));
1793}
1794#endif
1795
1796static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1797 void (*gen)(TCGv_ptr))
1798{
61f17f6e
RH		 1799 gen_op_load_fpr_QT0(QFPREG(rs1));
1800 gen_op_load_fpr_QT1(QFPREG(rs2));
1801
1802 gen(cpu_env);
1803
61f17f6e
RH		 1804 gen_op_store_QT0_fpr(QFPREG(rd));
1805 gen_update_fprs_dirty(QFPREG(rd));
1806}
1807
1808static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1809 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1810{
1811 TCGv_i64 dst;
1812 TCGv_i32 src1, src2;
1813
61f17f6e
RH		 1814 src1 = gen_load_fpr_F(dc, rs1);
1815 src2 = gen_load_fpr_F(dc, rs2);
1816 dst = gen_dest_fpr_D();
1817
1818 gen(dst, cpu_env, src1, src2);
1819
61f17f6e
RH		 1820 gen_store_fpr_D(dc, rd, dst);
1821}
1822
1823static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1824 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1825{
1826 TCGv_i64 src1, src2;
1827
61f17f6e
RH		 1828 src1 = gen_load_fpr_D(dc, rs1);
1829 src2 = gen_load_fpr_D(dc, rs2);
1830
1831 gen(cpu_env, src1, src2);
1832
61f17f6e
RH		 1833 gen_op_store_QT0_fpr(QFPREG(rd));
1834 gen_update_fprs_dirty(QFPREG(rd));
1835}
1836
1837#ifdef TARGET_SPARC64
1838static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1839 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1840{
1841 TCGv_i64 dst;
1842 TCGv_i32 src;
1843
61f17f6e
RH		 1844 src = gen_load_fpr_F(dc, rs);
1845 dst = gen_dest_fpr_D();
1846
1847 gen(dst, cpu_env, src);
1848
61f17f6e
RH		 1849 gen_store_fpr_D(dc, rd, dst);
1850}
1851#endif
1852
1853static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1854 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1855{
1856 TCGv_i64 dst;
1857 TCGv_i32 src;
1858
1859 src = gen_load_fpr_F(dc, rs);
1860 dst = gen_dest_fpr_D();
1861
1862 gen(dst, cpu_env, src);
1863
1864 gen_store_fpr_D(dc, rd, dst);
1865}
1866
1867static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1868 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1869{
1870 TCGv_i32 dst;
1871 TCGv_i64 src;
1872
61f17f6e
RH		 1873 src = gen_load_fpr_D(dc, rs);
1874 dst = gen_dest_fpr_F();
1875
1876 gen(dst, cpu_env, src);
1877
61f17f6e
RH		 1878 gen_store_fpr_F(dc, rd, dst);
1879}
1880
1881static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1882 void (*gen)(TCGv_i32, TCGv_ptr))
1883{
1884 TCGv_i32 dst;
1885
61f17f6e
RH		 1886 gen_op_load_fpr_QT1(QFPREG(rs));
1887 dst = gen_dest_fpr_F();
1888
1889 gen(dst, cpu_env);
1890
61f17f6e
RH		 1891 gen_store_fpr_F(dc, rd, dst);
1892}
1893
1894static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1895 void (*gen)(TCGv_i64, TCGv_ptr))
1896{
1897 TCGv_i64 dst;
1898
61f17f6e
RH		 1899 gen_op_load_fpr_QT1(QFPREG(rs));
1900 dst = gen_dest_fpr_D();
1901
1902 gen(dst, cpu_env);
1903
61f17f6e
RH		 1904 gen_store_fpr_D(dc, rd, dst);
1905}
1906
1907static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1908 void (*gen)(TCGv_ptr, TCGv_i32))
1909{
1910 TCGv_i32 src;
1911
1912 src = gen_load_fpr_F(dc, rs);
1913
1914 gen(cpu_env, src);
1915
1916 gen_op_store_QT0_fpr(QFPREG(rd));
1917 gen_update_fprs_dirty(QFPREG(rd));
1918}
1919
1920static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1921 void (*gen)(TCGv_ptr, TCGv_i64))
1922{
1923 TCGv_i64 src;
1924
1925 src = gen_load_fpr_D(dc, rs);
1926
1927 gen(cpu_env, src);
1928
1929 gen_op_store_QT0_fpr(QFPREG(rd));
1930 gen_update_fprs_dirty(QFPREG(rd));
1931}
1932
1a2fb1c0
BS		 1933/* asi moves */
1934#ifdef TARGET_SPARC64
a7812ae4 1935static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1936{
95f9397c 1937 int asi;
a7812ae4 1938 TCGv_i32 r_asi;
1a2fb1c0 1939
1a2fb1c0 1940 if (IS_IMM) {
a7812ae4 1941 r_asi = tcg_temp_new_i32();
255e1fcb 1942 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1943 } else {
1944 asi = GET_FIELD(insn, 19, 26);
0425bee5 1945 r_asi = tcg_const_i32(asi);
1a2fb1c0 1946 }
0425bee5
BS		 1947 return r_asi;
1948}
1949
77f193da
BS		 1950static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1951 int sign)
0425bee5 1952{
a7812ae4 1953 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1954
4af984a7 1955 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1956 r_size = tcg_const_i32(size);
1957 r_sign = tcg_const_i32(sign);
a7812ae4
PB		 1958 gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign);
1959 tcg_temp_free_i32(r_sign);
1960 tcg_temp_free_i32(r_size);
1961 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1962}
1963
4af984a7 1964static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1965{
a7812ae4 1966 TCGv_i32 r_asi, r_size;
1a2fb1c0 1967
4af984a7 1968 r_asi = gen_get_asi(insn, addr);
2ea815ca 1969 r_size = tcg_const_i32(size);
a7812ae4
PB		 1970 gen_helper_st_asi(addr, src, r_asi, r_size);
1971 tcg_temp_free_i32(r_size);
1972 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1973}
1974
4af984a7 1975static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1976{
a7812ae4 1977 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 1978
4af984a7 1979 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1980 r_size = tcg_const_i32(size);
1981 r_rd = tcg_const_i32(rd);
a7812ae4
PB		 1982 gen_helper_ldf_asi(addr, r_asi, r_size, r_rd);
1983 tcg_temp_free_i32(r_rd);
1984 tcg_temp_free_i32(r_size);
1985 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1986}
1987
4af984a7 1988static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1989{
a7812ae4 1990 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 1991
31741a27 1992 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1993 r_size = tcg_const_i32(size);
1994 r_rd = tcg_const_i32(rd);
a7812ae4
PB		 1995 gen_helper_stf_asi(addr, r_asi, r_size, r_rd);
1996 tcg_temp_free_i32(r_rd);
1997 tcg_temp_free_i32(r_size);
1998 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1999}
2000
4af984a7 2001static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2002{
a7812ae4 2003 TCGv_i32 r_asi, r_size, r_sign;
1a2fb1c0 2004
4af984a7 2005 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2006 r_size = tcg_const_i32(4);
2007 r_sign = tcg_const_i32(0);
a7812ae4
PB		 2008 gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
2009 tcg_temp_free_i32(r_sign);
2010 gen_helper_st_asi(addr, dst, r_asi, r_size);
2011 tcg_temp_free_i32(r_size);
2012 tcg_temp_free_i32(r_asi);
8d96d209 2013 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 2014}
2015
db166940 2016static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1a2fb1c0 2017{
a7812ae4 2018 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2019
4af984a7 2020 r_asi = gen_get_asi(insn, addr);
db166940 2021 r_rd = tcg_const_i32(rd);
a7812ae4
PB		 2022 gen_helper_ldda_asi(addr, r_asi, r_rd);
2023 tcg_temp_free_i32(r_rd);
2024 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2025}
2026
4af984a7 2027static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 2028{
a7812ae4 2029 TCGv_i32 r_asi, r_size;
a7ec4229
BS		 2030
2031 gen_movl_reg_TN(rd + 1, cpu_tmp0);
ab508019 2032 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
4af984a7 2033 r_asi = gen_get_asi(insn, addr);
2ea815ca 2034 r_size = tcg_const_i32(8);
a7812ae4
PB		 2035 gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
2036 tcg_temp_free_i32(r_size);
2037 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2038}
2039
77f193da
BS		 2040static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
2041 int rd)
1a2fb1c0 2042{
a7812ae4
PB		 2043 TCGv r_val1;
2044 TCGv_i32 r_asi;
1a2fb1c0 2045
a7812ae4 2046 r_val1 = tcg_temp_new();
1a2fb1c0 2047 gen_movl_reg_TN(rd, r_val1);
4af984a7 2048 r_asi = gen_get_asi(insn, addr);
a7812ae4
PB		 2049 gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi);
2050 tcg_temp_free_i32(r_asi);
2ea815ca 2051 tcg_temp_free(r_val1);
1a2fb1c0
BS		 2052}
2053
77f193da
BS		 2054static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
2055 int rd)
1a2fb1c0 2056{
a7812ae4 2057 TCGv_i32 r_asi;
1a2fb1c0 2058
8911f501 2059 gen_movl_reg_TN(rd, cpu_tmp64);
4af984a7 2060 r_asi = gen_get_asi(insn, addr);
a7812ae4
PB		 2061 gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi);
2062 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2063}
2064
2065#elif !defined(CONFIG_USER_ONLY)
2066
77f193da
BS		 2067static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2068 int sign)
1a2fb1c0 2069{
a7812ae4 2070 TCGv_i32 r_asi, r_size, r_sign;
1a2fb1c0 2071
2ea815ca
BS		 2072 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2073 r_size = tcg_const_i32(size);
2074 r_sign = tcg_const_i32(sign);
a7812ae4 2075 gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
2ea815ca
BS		 2076 tcg_temp_free(r_sign);
2077 tcg_temp_free(r_size);
2078 tcg_temp_free(r_asi);
4af984a7 2079 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 2080}
2081
4af984a7 2082static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2083{
a7812ae4 2084 TCGv_i32 r_asi, r_size;
1a2fb1c0 2085
4af984a7 2086 tcg_gen_extu_tl_i64(cpu_tmp64, src);
2ea815ca
BS		 2087 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2088 r_size = tcg_const_i32(size);
a7812ae4 2089 gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
2ea815ca
BS		 2090 tcg_temp_free(r_size);
2091 tcg_temp_free(r_asi);
1a2fb1c0
BS		 2092}
2093
4af984a7 2094static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2095{
a7812ae4
PB		 2096 TCGv_i32 r_asi, r_size, r_sign;
2097 TCGv_i64 r_val;
1a2fb1c0 2098
2ea815ca
BS		 2099 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2100 r_size = tcg_const_i32(4);
2101 r_sign = tcg_const_i32(0);
a7812ae4 2102 gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
2ea815ca 2103 tcg_temp_free(r_sign);
a7812ae4
PB		 2104 r_val = tcg_temp_new_i64();
2105 tcg_gen_extu_tl_i64(r_val, dst);
2106 gen_helper_st_asi(addr, r_val, r_asi, r_size);
2107 tcg_temp_free_i64(r_val);
2ea815ca
BS		 2108 tcg_temp_free(r_size);
2109 tcg_temp_free(r_asi);
8d96d209 2110 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 2111}
2112
db166940 2113static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1a2fb1c0 2114{
a7812ae4 2115 TCGv_i32 r_asi, r_size, r_sign;
1a2fb1c0 2116
2ea815ca
BS		 2117 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2118 r_size = tcg_const_i32(8);
2119 r_sign = tcg_const_i32(0);
a7812ae4 2120 gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
2ea815ca
BS		 2121 tcg_temp_free(r_sign);
2122 tcg_temp_free(r_size);
2123 tcg_temp_free(r_asi);
db166940
BS		 2124 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
2125 gen_movl_TN_reg(rd + 1, cpu_tmp0);
8911f501 2126 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 2127 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
db166940 2128 gen_movl_TN_reg(rd, hi);
0425bee5
BS		 2129}
2130
4af984a7 2131static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 2132{
a7812ae4 2133 TCGv_i32 r_asi, r_size;
a7ec4229
BS		 2134
2135 gen_movl_reg_TN(rd + 1, cpu_tmp0);
ab508019 2136 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
2ea815ca
BS		 2137 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2138 r_size = tcg_const_i32(8);
a7812ae4 2139 gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
2ea815ca
BS		 2140 tcg_temp_free(r_size);
2141 tcg_temp_free(r_asi);
1a2fb1c0
BS		 2142}
2143#endif
2144
2145#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4af984a7 2146static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2147{
a7812ae4
PB		 2148 TCGv_i64 r_val;
2149 TCGv_i32 r_asi, r_size;
1a2fb1c0 2150
4af984a7 2151 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2152
2ea815ca
BS		 2153 r_val = tcg_const_i64(0xffULL);
2154 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2155 r_size = tcg_const_i32(1);
a7812ae4
PB		 2156 gen_helper_st_asi(addr, r_val, r_asi, r_size);
2157 tcg_temp_free_i32(r_size);
2158 tcg_temp_free_i32(r_asi);
2159 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2160}
2161#endif
2162
9322a4bf
BS		 2163static inline TCGv get_src1(unsigned int insn, TCGv def)
2164{
2165 TCGv r_rs1 = def;
2166 unsigned int rs1;
2167
2168 rs1 = GET_FIELD(insn, 13, 17);
42a8aa83
RH		 2169 if (rs1 == 0) {
2170 tcg_gen_movi_tl(def, 0);
2171 } else if (rs1 < 8) {
5c6a0628 2172 r_rs1 = cpu_gregs[rs1];
42a8aa83 2173 } else {
9322a4bf 2174 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
42a8aa83 2175 }
9322a4bf
BS		 2176 return r_rs1;
2177}
2178
a49d9390
BS		 2179static inline TCGv get_src2(unsigned int insn, TCGv def)
2180{
2181 TCGv r_rs2 = def;
a49d9390
BS		 2182
2183 if (IS_IMM) { /* immediate */
42a8aa83
RH		 2184 target_long simm = GET_FIELDs(insn, 19, 31);
2185 tcg_gen_movi_tl(def, simm);
a49d9390 2186 } else { /* register */
42a8aa83
RH		 2187 unsigned int rs2 = GET_FIELD(insn, 27, 31);
2188 if (rs2 == 0) {
2189 tcg_gen_movi_tl(def, 0);
2190 } else if (rs2 < 8) {
a49d9390 2191 r_rs2 = cpu_gregs[rs2];
42a8aa83 2192 } else {
a49d9390 2193 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
42a8aa83 2194 }
a49d9390
BS		 2195 }
2196 return r_rs2;
2197}
2198
8194f35a
IK		 2199#ifdef TARGET_SPARC64
2200static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2201{
b551ec04 2202 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2203
2204 /* load env->tl into r_tl */
b551ec04 2205 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2206
2207 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2208 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2209
2210 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2211 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
8194f35a
IK		 2212 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts));
2213
2214 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2215 {
2216 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2217 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2218 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2219 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2220 }
8194f35a 2221
b551ec04 2222 tcg_temp_free_i32(r_tl);
8194f35a 2223}
6c073553
RH		 2224
2225static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2226 int width, bool cc, bool left)
2227{
2228 TCGv lo1, lo2, t1, t2;
2229 uint64_t amask, tabl, tabr;
2230 int shift, imask, omask;
2231
2232 if (cc) {
2233 tcg_gen_mov_tl(cpu_cc_src, s1);
2234 tcg_gen_mov_tl(cpu_cc_src2, s2);
2235 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2236 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2237 dc->cc_op = CC_OP_SUB;
2238 }
2239
2240 /* Theory of operation: there are two tables, left and right (not to
2241 be confused with the left and right versions of the opcode). These
2242 are indexed by the low 3 bits of the inputs. To make things "easy",
2243 these tables are loaded into two constants, TABL and TABR below.
2244 The operation index = (input & imask) << shift calculates the index
2245 into the constant, while val = (table >> index) & omask calculates
2246 the value we're looking for. */
2247 switch (width) {
2248 case 8:
2249 imask = 0x7;
2250 shift = 3;
2251 omask = 0xff;
2252 if (left) {
2253 tabl = 0x80c0e0f0f8fcfeffULL;
2254 tabr = 0xff7f3f1f0f070301ULL;
2255 } else {
2256 tabl = 0x0103070f1f3f7fffULL;
2257 tabr = 0xfffefcf8f0e0c080ULL;
2258 }
2259 break;
2260 case 16:
2261 imask = 0x6;
2262 shift = 1;
2263 omask = 0xf;
2264 if (left) {
2265 tabl = 0x8cef;
2266 tabr = 0xf731;
2267 } else {
2268 tabl = 0x137f;
2269 tabr = 0xfec8;
2270 }
2271 break;
2272 case 32:
2273 imask = 0x4;
2274 shift = 0;
2275 omask = 0x3;
2276 if (left) {
2277 tabl = (2 << 2) | 3;
2278 tabr = (3 << 2) | 1;
2279 } else {
2280 tabl = (1 << 2) | 3;
2281 tabr = (3 << 2) | 2;
2282 }
2283 break;
2284 default:
2285 abort();
2286 }
2287
2288 lo1 = tcg_temp_new();
2289 lo2 = tcg_temp_new();
2290 tcg_gen_andi_tl(lo1, s1, imask);
2291 tcg_gen_andi_tl(lo2, s2, imask);
2292 tcg_gen_shli_tl(lo1, lo1, shift);
2293 tcg_gen_shli_tl(lo2, lo2, shift);
2294
2295 t1 = tcg_const_tl(tabl);
2296 t2 = tcg_const_tl(tabr);
2297 tcg_gen_shr_tl(lo1, t1, lo1);
2298 tcg_gen_shr_tl(lo2, t2, lo2);
2299 tcg_gen_andi_tl(dst, lo1, omask);
2300 tcg_gen_andi_tl(lo2, lo2, omask);
2301
2302 amask = -8;
2303 if (AM_CHECK(dc)) {
2304 amask &= 0xffffffffULL;
2305 }
2306 tcg_gen_andi_tl(s1, s1, amask);
2307 tcg_gen_andi_tl(s2, s2, amask);
2308
2309 /* We want to compute
2310 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2311 We've already done dst = lo1, so this reduces to
2312 dst &= (s1 == s2 ? -1 : lo2)
2313 Which we perform by
2314 lo2 |= -(s1 == s2)
2315 dst &= lo2
2316 */
2317 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2318 tcg_gen_neg_tl(t1, t1);
2319 tcg_gen_or_tl(lo2, lo2, t1);
2320 tcg_gen_and_tl(dst, dst, lo2);
2321
2322 tcg_temp_free(lo1);
2323 tcg_temp_free(lo2);
2324 tcg_temp_free(t1);
2325 tcg_temp_free(t2);
2326}
add545ab
RH		 2327
2328static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2329{
2330 TCGv tmp = tcg_temp_new();
2331
2332 tcg_gen_add_tl(tmp, s1, s2);
2333 tcg_gen_andi_tl(dst, tmp, -8);
2334 if (left) {
2335 tcg_gen_neg_tl(tmp, tmp);
2336 }
2337 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2338
2339 tcg_temp_free(tmp);
2340}
8194f35a
IK		 2341#endif
2342
64a88d5d 2343#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2344 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2345 goto illegal_insn;
2346#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2347 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2348 goto nfpu_insn;
2349
0bee699e 2350/* before an instruction, dc->pc must be static */
cf495bcf
FB		 2351static void disas_sparc_insn(DisasContext * dc)
2352{
2353 unsigned int insn, opc, rs1, rs2, rd;
42a8aa83 2354 TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2;
208ae657 2355 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2356 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2357 target_long simm;
7a3f1944 2358
8fec2b8c 2359 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
a8c768c0 2360 tcg_gen_debug_insn_start(dc->pc);
0fa85d43 2361 insn = ldl_code(dc->pc);
cf495bcf 2362 opc = GET_FIELD(insn, 0, 1);
7a3f1944 2363
cf495bcf 2364 rd = GET_FIELD(insn, 2, 6);
6ae20372 2365
42a8aa83
RH		 2366 cpu_tmp1 = cpu_src1 = tcg_temp_new();
2367 cpu_tmp2 = cpu_src2 = tcg_temp_new();
6ae20372 2368
cf495bcf 2369 switch (opc) {
0f8a249a
BS		 2370 case 0: /* branches/sethi */
2371 {
2372 unsigned int xop = GET_FIELD(insn, 7, 9);
2373 int32_t target;
2374 switch (xop) {
3475187d 2375#ifdef TARGET_SPARC64
0f8a249a
BS		 2376 case 0x1: /* V9 BPcc */
2377 {
2378 int cc;
2379
2380 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2381 target = sign_extend(target, 19);
0f8a249a
BS		 2382 target <<= 2;
2383 cc = GET_FIELD_SP(insn, 20, 21);
2384 if (cc == 0)
6ae20372 2385 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a 2386 else if (cc == 2)
6ae20372 2387 do_branch(dc, target, insn, 1, cpu_cond);
0f8a249a
BS		 2388 else
2389 goto illegal_insn;
2390 goto jmp_insn;
2391 }
2392 case 0x3: /* V9 BPr */
2393 {
2394 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2395 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2396 target = sign_extend(target, 16);
2397 target <<= 2;
9322a4bf 2398 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2399 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
0f8a249a
BS		 2400 goto jmp_insn;
2401 }
2402 case 0x5: /* V9 FBPcc */
2403 {
2404 int cc = GET_FIELD_SP(insn, 20, 21);
6ae20372 2405 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2406 goto jmp_insn;
0f8a249a
BS		 2407 target = GET_FIELD_SP(insn, 0, 18);
2408 target = sign_extend(target, 19);
2409 target <<= 2;
6ae20372 2410 do_fbranch(dc, target, insn, cc, cpu_cond);
0f8a249a
BS		 2411 goto jmp_insn;
2412 }
a4d17f19 2413#else
0f8a249a
BS		 2414 case 0x7: /* CBN+x */
2415 {
2416 goto ncp_insn;
2417 }
2418#endif
2419 case 0x2: /* BN+x */
2420 {
2421 target = GET_FIELD(insn, 10, 31);
2422 target = sign_extend(target, 22);
2423 target <<= 2;
6ae20372 2424 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 2425 goto jmp_insn;
2426 }
2427 case 0x6: /* FBN+x */
2428 {
6ae20372 2429 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2430 goto jmp_insn;
0f8a249a
BS		 2431 target = GET_FIELD(insn, 10, 31);
2432 target = sign_extend(target, 22);
2433 target <<= 2;
6ae20372 2434 do_fbranch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 2435 goto jmp_insn;
2436 }
2437 case 0x4: /* SETHI */
0f8a249a 2438 if (rd) { // nop
0f8a249a 2439 uint32_t value = GET_FIELD(insn, 10, 31);
2ea815ca
BS		 2440 TCGv r_const;
2441
2442 r_const = tcg_const_tl(value << 10);
2443 gen_movl_TN_reg(rd, r_const);
2444 tcg_temp_free(r_const);
0f8a249a 2445 }
0f8a249a
BS		 2446 break;
2447 case 0x0: /* UNIMPL */
2448 default:
3475187d 2449 goto illegal_insn;
0f8a249a
BS		 2450 }
2451 break;
2452 }
2453 break;
dc1a6971
BS		 2454 case 1: /*CALL*/
2455 {
0f8a249a 2456 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2ea815ca 2457 TCGv r_const;
cf495bcf 2458
2ea815ca
BS		 2459 r_const = tcg_const_tl(dc->pc);
2460 gen_movl_TN_reg(15, r_const);
2461 tcg_temp_free(r_const);
0f8a249a 2462 target += dc->pc;
6ae20372 2463 gen_mov_pc_npc(dc, cpu_cond);
0f8a249a
BS		 2464 dc->npc = target;
2465 }
2466 goto jmp_insn;
2467 case 2: /* FPU & Logical Operations */
2468 {
2469 unsigned int xop = GET_FIELD(insn, 7, 12);
2470 if (xop == 0x3a) { /* generate trap */
cf495bcf 2471 int cond;
3475187d 2472
9322a4bf 2473 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 2474 if (IS_IMM) {
2475 rs2 = GET_FIELD(insn, 25, 31);
6ae20372 2476 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
cf495bcf
FB		 2477 } else {
2478 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 2479 if (rs2 != 0) {
6ae20372
BS		 2480 gen_movl_reg_TN(rs2, cpu_src2);
2481 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 2482 } else
2483 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 2484 }
b04d9890 2485
cf495bcf 2486 cond = GET_FIELD(insn, 3, 6);
b04d9890 2487 if (cond == 0x8) { /* Trap Always */
6ae20372 2488 save_state(dc, cpu_cond);
b158a785
BS		 2489 if ((dc->def->features & CPU_FEATURE_HYPV) &&
2490 supervisor(dc))
2491 tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2492 else
2493 tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2494 tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
a7812ae4 2495 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
b04d9890
FC		 2496
2497 if (rs2 == 0 &&
2498 dc->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
2499
2500 gen_helper_shutdown();
2501
2502 } else {
bc265319 2503 gen_helper_raise_exception(cpu_env, cpu_tmp32);
b04d9890 2504 }
af7bf89b 2505 } else if (cond != 0) {
a7812ae4 2506 TCGv r_cond = tcg_temp_new();
b158a785 2507 int l1;
3475187d 2508#ifdef TARGET_SPARC64
0f8a249a
BS		 2509 /* V9 icc/xcc */
2510 int cc = GET_FIELD_SP(insn, 11, 12);
748b9d8e 2511
6ae20372 2512 save_state(dc, cpu_cond);
0f8a249a 2513 if (cc == 0)
8393617c 2514 gen_cond(r_cond, 0, cond, dc);
0f8a249a 2515 else if (cc == 2)
8393617c 2516 gen_cond(r_cond, 1, cond, dc);
0f8a249a
BS		 2517 else
2518 goto illegal_insn;
3475187d 2519#else
6ae20372 2520 save_state(dc, cpu_cond);
8393617c 2521 gen_cond(r_cond, 0, cond, dc);
3475187d 2522#endif
b158a785
BS		 2523 l1 = gen_new_label();
2524 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
2525
2526 if ((dc->def->features & CPU_FEATURE_HYPV) &&
2527 supervisor(dc))
2528 tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2529 else
2530 tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2531 tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
a7812ae4 2532 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
bc265319 2533 gen_helper_raise_exception(cpu_env, cpu_tmp32);
b158a785
BS		 2534
2535 gen_set_label(l1);
2ea815ca 2536 tcg_temp_free(r_cond);
cf495bcf 2537 }
a80dde08 2538 gen_op_next_insn();
57fec1fe 2539 tcg_gen_exit_tb(0);
a80dde08
FB		 2540 dc->is_br = 1;
2541 goto jmp_insn;
cf495bcf
FB		 2542 } else if (xop == 0x28) {
2543 rs1 = GET_FIELD(insn, 13, 17);
2544 switch(rs1) {
2545 case 0: /* rdy */
65fe7b09
BS		 2546#ifndef TARGET_SPARC64
2547 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2548 manual, rdy on the microSPARC
2549 II */
2550 case 0x0f: /* stbar in the SPARCv8 manual,
2551 rdy on the microSPARC II */
2552 case 0x10 ... 0x1f: /* implementation-dependent in the
2553 SPARCv8 manual, rdy on the
2554 microSPARC II */
4a2ba232
FC		 2555 /* Read Asr17 */
2556 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
2557 TCGv r_const;
2558
2559 /* Read Asr17 for a Leon3 monoprocessor */
2560 r_const = tcg_const_tl((1 << 8)
2561 | (dc->def->nwindows - 1));
2562 gen_movl_TN_reg(rd, r_const);
2563 tcg_temp_free(r_const);
2564 break;
2565 }
65fe7b09 2566#endif
255e1fcb 2567 gen_movl_TN_reg(rd, cpu_y);
cf495bcf 2568 break;
3475187d 2569#ifdef TARGET_SPARC64
0f8a249a 2570 case 0x2: /* V9 rdccr */
2ffd9176 2571 gen_helper_compute_psr(cpu_env);
063c3675 2572 gen_helper_rdccr(cpu_dst, cpu_env);
6ae20372 2573 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2574 break;
0f8a249a 2575 case 0x3: /* V9 rdasi */
255e1fcb 2576 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
6ae20372 2577 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2578 break;
0f8a249a 2579 case 0x4: /* V9 rdtick */
ccd4a219 2580 {
a7812ae4 2581 TCGv_ptr r_tickptr;
ccd4a219 2582
a7812ae4 2583 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 2584 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2585 offsetof(CPUState, tick));
a7812ae4
PB		 2586 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2587 tcg_temp_free_ptr(r_tickptr);
6ae20372 2588 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2589 }
3475187d 2590 break;
0f8a249a 2591 case 0x5: /* V9 rdpc */
2ea815ca
BS		 2592 {
2593 TCGv r_const;
2594
2595 r_const = tcg_const_tl(dc->pc);
2596 gen_movl_TN_reg(rd, r_const);
2597 tcg_temp_free(r_const);
2598 }
0f8a249a
BS		 2599 break;
2600 case 0x6: /* V9 rdfprs */
255e1fcb 2601 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
6ae20372 2602 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2603 break;
65fe7b09
BS		 2604 case 0xf: /* V9 membar */
2605 break; /* no effect */
0f8a249a 2606 case 0x13: /* Graphics Status */
6ae20372 2607 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 2608 goto jmp_insn;
255e1fcb 2609 gen_movl_TN_reg(rd, cpu_gsr);
725cb90b 2610 break;
9d926598
BS		 2611 case 0x16: /* Softint */
2612 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
2613 gen_movl_TN_reg(rd, cpu_dst);
2614 break;
0f8a249a 2615 case 0x17: /* Tick compare */
255e1fcb 2616 gen_movl_TN_reg(rd, cpu_tick_cmpr);
83469015 2617 break;
0f8a249a 2618 case 0x18: /* System tick */
ccd4a219 2619 {
a7812ae4 2620 TCGv_ptr r_tickptr;
ccd4a219 2621
a7812ae4 2622 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 2623 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2624 offsetof(CPUState, stick));
a7812ae4
PB		 2625 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2626 tcg_temp_free_ptr(r_tickptr);
6ae20372 2627 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2628 }
83469015 2629 break;
0f8a249a 2630 case 0x19: /* System tick compare */
255e1fcb 2631 gen_movl_TN_reg(rd, cpu_stick_cmpr);
83469015 2632 break;
0f8a249a
BS		 2633 case 0x10: /* Performance Control */
2634 case 0x11: /* Performance Instrumentation Counter */
2635 case 0x12: /* Dispatch Control */
2636 case 0x14: /* Softint set, WO */
2637 case 0x15: /* Softint clear, WO */
3475187d
FB		 2638#endif
2639 default:
cf495bcf
FB		 2640 goto illegal_insn;
2641 }
e8af50a3 2642#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2643 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2644#ifndef TARGET_SPARC64
0f8a249a
BS		 2645 if (!supervisor(dc))
2646 goto priv_insn;
2ffd9176 2647 gen_helper_compute_psr(cpu_env);
8393617c 2648 dc->cc_op = CC_OP_FLAGS;
063c3675 2649 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2650#else
fb79ceb9 2651 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2652 if (!hypervisor(dc))
2653 goto priv_insn;
2654 rs1 = GET_FIELD(insn, 13, 17);
2655 switch (rs1) {
2656 case 0: // hpstate
2657 // gen_op_rdhpstate();
2658 break;
2659 case 1: // htstate
2660 // gen_op_rdhtstate();
2661 break;
2662 case 3: // hintp
255e1fcb 2663 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2664 break;
2665 case 5: // htba
255e1fcb 2666 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2667 break;
2668 case 6: // hver
255e1fcb 2669 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2670 break;
2671 case 31: // hstick_cmpr
255e1fcb 2672 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2673 break;
2674 default:
2675 goto illegal_insn;
2676 }
2677#endif
6ae20372 2678 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2679 break;
3475187d 2680 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2681 if (!supervisor(dc))
2682 goto priv_insn;
3475187d
FB		 2683#ifdef TARGET_SPARC64
2684 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2685 switch (rs1) {
2686 case 0: // tpc
375ee38b 2687 {
a7812ae4 2688 TCGv_ptr r_tsptr;
375ee38b 2689
a7812ae4 2690 r_tsptr = tcg_temp_new_ptr();
8194f35a 2691 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2692 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2693 offsetof(trap_state, tpc));
a7812ae4 2694 tcg_temp_free_ptr(r_tsptr);
375ee38b 2695 }
0f8a249a
BS		 2696 break;
2697 case 1: // tnpc
375ee38b 2698 {
a7812ae4 2699 TCGv_ptr r_tsptr;
375ee38b 2700
a7812ae4 2701 r_tsptr = tcg_temp_new_ptr();
8194f35a 2702 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2703 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2704 offsetof(trap_state, tnpc));
a7812ae4 2705 tcg_temp_free_ptr(r_tsptr);
375ee38b 2706 }
0f8a249a
BS		 2707 break;
2708 case 2: // tstate
375ee38b 2709 {
a7812ae4 2710 TCGv_ptr r_tsptr;
375ee38b 2711
a7812ae4 2712 r_tsptr = tcg_temp_new_ptr();
8194f35a 2713 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2714 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2715 offsetof(trap_state, tstate));
a7812ae4 2716 tcg_temp_free_ptr(r_tsptr);
375ee38b 2717 }
0f8a249a
BS		 2718 break;
2719 case 3: // tt
375ee38b 2720 {
a7812ae4 2721 TCGv_ptr r_tsptr;
375ee38b 2722
a7812ae4 2723 r_tsptr = tcg_temp_new_ptr();
8194f35a 2724 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2725 tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
375ee38b 2726 offsetof(trap_state, tt));
a7812ae4
PB		 2727 tcg_temp_free_ptr(r_tsptr);
2728 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
375ee38b 2729 }
0f8a249a
BS		 2730 break;
2731 case 4: // tick
ccd4a219 2732 {
a7812ae4 2733 TCGv_ptr r_tickptr;
ccd4a219 2734
a7812ae4 2735 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 2736 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2737 offsetof(CPUState, tick));
a7812ae4 2738 gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
ece43b8d 2739 gen_movl_TN_reg(rd, cpu_tmp0);
a7812ae4 2740 tcg_temp_free_ptr(r_tickptr);
ccd4a219 2741 }
0f8a249a
BS		 2742 break;
2743 case 5: // tba
255e1fcb 2744 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2745 break;
2746 case 6: // pstate
77f193da
BS		 2747 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2748 offsetof(CPUSPARCState, pstate));
ece43b8d 2749 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2750 break;
2751 case 7: // tl
77f193da
BS		 2752 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2753 offsetof(CPUSPARCState, tl));
ece43b8d 2754 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2755 break;
2756 case 8: // pil
77f193da
BS		 2757 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2758 offsetof(CPUSPARCState, psrpil));
ece43b8d 2759 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2760 break;
2761 case 9: // cwp
063c3675 2762 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2763 break;
2764 case 10: // cansave
77f193da
BS		 2765 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2766 offsetof(CPUSPARCState, cansave));
ece43b8d 2767 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2768 break;
2769 case 11: // canrestore
77f193da
BS		 2770 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2771 offsetof(CPUSPARCState, canrestore));
ece43b8d 2772 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2773 break;
2774 case 12: // cleanwin
77f193da
BS		 2775 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2776 offsetof(CPUSPARCState, cleanwin));
ece43b8d 2777 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2778 break;
2779 case 13: // otherwin
77f193da
BS		 2780 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2781 offsetof(CPUSPARCState, otherwin));
ece43b8d 2782 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2783 break;
2784 case 14: // wstate
77f193da
BS		 2785 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2786 offsetof(CPUSPARCState, wstate));
ece43b8d 2787 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a 2788 break;
e9ebed4d 2789 case 16: // UA2005 gl
fb79ceb9 2790 CHECK_IU_FEATURE(dc, GL);
77f193da
BS		 2791 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2792 offsetof(CPUSPARCState, gl));
ece43b8d 2793 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
e9ebed4d
BS		 2794 break;
2795 case 26: // UA2005 strand status
fb79ceb9 2796 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2797 if (!hypervisor(dc))
2798 goto priv_insn;
527067d8 2799 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2800 break;
0f8a249a 2801 case 31: // ver
255e1fcb 2802 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2803 break;
2804 case 15: // fq
2805 default:
2806 goto illegal_insn;
2807 }
3475187d 2808#else
255e1fcb 2809 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2810#endif
ece43b8d 2811 gen_movl_TN_reg(rd, cpu_tmp0);
e8af50a3 2812 break;
3475187d
FB		 2813 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2814#ifdef TARGET_SPARC64
c5f2f668 2815 save_state(dc, cpu_cond);
063c3675 2816 gen_helper_flushw(cpu_env);
3475187d 2817#else
0f8a249a
BS		 2818 if (!supervisor(dc))
2819 goto priv_insn;
255e1fcb 2820 gen_movl_TN_reg(rd, cpu_tbr);
3475187d 2821#endif
e8af50a3
FB		 2822 break;
2823#endif
0f8a249a 2824 } else if (xop == 0x34) { /* FPU Operations */
6ae20372 2825 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2826 goto jmp_insn;
0f8a249a 2827 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2828 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2829 rs2 = GET_FIELD(insn, 27, 31);
2830 xop = GET_FIELD(insn, 18, 26);
cca1d527 2831 save_state(dc, cpu_cond);
0f8a249a 2832 switch (xop) {
dc1a6971 2833 case 0x1: /* fmovs */
208ae657
RH		 2834 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2835 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2836 break;
2837 case 0x5: /* fnegs */
61f17f6e 2838 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2839 break;
2840 case 0x9: /* fabss */
61f17f6e 2841 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2842 break;
2843 case 0x29: /* fsqrts */
2844 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2845 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2846 break;
2847 case 0x2a: /* fsqrtd */
2848 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2849 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2850 break;
2851 case 0x2b: /* fsqrtq */
2852 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2853 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2854 break;
2855 case 0x41: /* fadds */
61f17f6e 2856 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2857 break;
2858 case 0x42: /* faddd */
61f17f6e 2859 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2860 break;
2861 case 0x43: /* faddq */
2862 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2863 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2864 break;
2865 case 0x45: /* fsubs */
61f17f6e 2866 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2867 break;
2868 case 0x46: /* fsubd */
61f17f6e 2869 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 2870 break;
2871 case 0x47: /* fsubq */
2872 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2873 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 2874 break;
2875 case 0x49: /* fmuls */
2876 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 2877 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 2878 break;
2879 case 0x4a: /* fmuld */
2880 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 2881 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 2882 break;
2883 case 0x4b: /* fmulq */
2884 CHECK_FPU_FEATURE(dc, FLOAT128);
2885 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 2886 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 2887 break;
2888 case 0x4d: /* fdivs */
61f17f6e 2889 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 2890 break;
2891 case 0x4e: /* fdivd */
61f17f6e 2892 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 2893 break;
2894 case 0x4f: /* fdivq */
2895 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2896 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 2897 break;
2898 case 0x69: /* fsmuld */
2899 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 2900 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 2901 break;
2902 case 0x6e: /* fdmulq */
2903 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2904 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 2905 break;
2906 case 0xc4: /* fitos */
61f17f6e 2907 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 2908 break;
2909 case 0xc6: /* fdtos */
61f17f6e 2910 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 2911 break;
2912 case 0xc7: /* fqtos */
2913 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2914 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 2915 break;
2916 case 0xc8: /* fitod */
61f17f6e 2917 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 2918 break;
2919 case 0xc9: /* fstod */
61f17f6e 2920 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 2921 break;
2922 case 0xcb: /* fqtod */
2923 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2924 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 2925 break;
2926 case 0xcc: /* fitoq */
2927 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2928 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 2929 break;
2930 case 0xcd: /* fstoq */
2931 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2932 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 2933 break;
2934 case 0xce: /* fdtoq */
2935 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2936 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 2937 break;
2938 case 0xd1: /* fstoi */
61f17f6e 2939 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 2940 break;
2941 case 0xd2: /* fdtoi */
61f17f6e 2942 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 2943 break;
2944 case 0xd3: /* fqtoi */
2945 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2946 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 2947 break;
3475187d 2948#ifdef TARGET_SPARC64
dc1a6971 2949 case 0x2: /* V9 fmovd */
96eda024
RH		 2950 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
2951 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 2952 break;
2953 case 0x3: /* V9 fmovq */
2954 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 2955 gen_move_Q(rd, rs2);
dc1a6971
BS		 2956 break;
2957 case 0x6: /* V9 fnegd */
61f17f6e 2958 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 2959 break;
2960 case 0x7: /* V9 fnegq */
2961 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2962 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 2963 break;
2964 case 0xa: /* V9 fabsd */
61f17f6e 2965 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 2966 break;
2967 case 0xb: /* V9 fabsq */
2968 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2969 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 2970 break;
2971 case 0x81: /* V9 fstox */
61f17f6e 2972 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 2973 break;
2974 case 0x82: /* V9 fdtox */
61f17f6e 2975 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 2976 break;
2977 case 0x83: /* V9 fqtox */
2978 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2979 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 2980 break;
2981 case 0x84: /* V9 fxtos */
61f17f6e 2982 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 2983 break;
2984 case 0x88: /* V9 fxtod */
61f17f6e 2985 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 2986 break;
2987 case 0x8c: /* V9 fxtoq */
2988 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2989 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 2990 break;
0f8a249a 2991#endif
dc1a6971
BS		 2992 default:
2993 goto illegal_insn;
0f8a249a
BS		 2994 }
2995 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2996#ifdef TARGET_SPARC64
0f8a249a 2997 int cond;
3475187d 2998#endif
6ae20372 2999 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 3000 goto jmp_insn;
0f8a249a 3001 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3002 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3003 rs2 = GET_FIELD(insn, 27, 31);
3004 xop = GET_FIELD(insn, 18, 26);
cca1d527 3005 save_state(dc, cpu_cond);
3475187d 3006#ifdef TARGET_SPARC64
0f8a249a 3007 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 3008 int l1;
3009
3010 l1 = gen_new_label();
0f8a249a 3011 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 3012 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 3013 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
3014 0, l1);
208ae657
RH		 3015 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3016 gen_store_fpr_F(dc, rd, cpu_src1_32);
dcf24905 3017 gen_set_label(l1);
0f8a249a
BS		 3018 break;
3019 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 3020 int l1;
3021
3022 l1 = gen_new_label();
0f8a249a 3023 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 3024 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 3025 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
3026 0, l1);
96eda024
RH		 3027 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3028 gen_store_fpr_D(dc, rd, cpu_src1_64);
dcf24905 3029 gen_set_label(l1);
0f8a249a
BS		 3030 break;
3031 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
dcf24905
BS		 3032 int l1;
3033
64a88d5d 3034 CHECK_FPU_FEATURE(dc, FLOAT128);
dcf24905 3035 l1 = gen_new_label();
1f587329 3036 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 3037 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 3038 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
3039 0, l1);
ac11f776 3040 gen_move_Q(rd, rs2);
dcf24905 3041 gen_set_label(l1);
1f587329 3042 break;
0f8a249a
BS		 3043 }
3044#endif
3045 switch (xop) {
3475187d 3046#ifdef TARGET_SPARC64
714547bb 3047#define FMOVSCC(fcc) \
19f329ad 3048 { \
0425bee5 3049 TCGv r_cond; \
19f329ad
BS		 3050 int l1; \
3051 \
3052 l1 = gen_new_label(); \
dc1a6971 3053 r_cond = tcg_temp_new(); \
19f329ad
BS		 3054 cond = GET_FIELD_SP(insn, 14, 17); \
3055 gen_fcond(r_cond, fcc, cond); \
cb63669a
PB		 3056 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3057 0, l1); \
208ae657
RH		 3058 cpu_src1_32 = gen_load_fpr_F(dc, rs2); \
3059 gen_store_fpr_F(dc, rd, cpu_src1_32); \
714547bb
BS		 3060 gen_set_label(l1); \
3061 tcg_temp_free(r_cond); \
3062 }
3063#define FMOVDCC(fcc) \
3064 { \
3065 TCGv r_cond; \
3066 int l1; \
3067 \
3068 l1 = gen_new_label(); \
dc1a6971 3069 r_cond = tcg_temp_new(); \
714547bb
BS		 3070 cond = GET_FIELD_SP(insn, 14, 17); \
3071 gen_fcond(r_cond, fcc, cond); \
3072 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3073 0, l1); \
96eda024
RH		 3074 cpu_src1_64 = gen_load_fpr_D(dc, rs2); \
3075 gen_store_fpr_D(dc, rd, cpu_src1_64); \
714547bb
BS		 3076 gen_set_label(l1); \
3077 tcg_temp_free(r_cond); \
3078 }
3079#define FMOVQCC(fcc) \
3080 { \
3081 TCGv r_cond; \
3082 int l1; \
3083 \
3084 l1 = gen_new_label(); \
dc1a6971 3085 r_cond = tcg_temp_new(); \
714547bb
BS		 3086 cond = GET_FIELD_SP(insn, 14, 17); \
3087 gen_fcond(r_cond, fcc, cond); \
3088 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3089 0, l1); \
ac11f776 3090 gen_move_Q(rd, rs2); \
19f329ad 3091 gen_set_label(l1); \
2ea815ca 3092 tcg_temp_free(r_cond); \
19f329ad 3093 }
0f8a249a 3094 case 0x001: /* V9 fmovscc %fcc0 */
714547bb 3095 FMOVSCC(0);
0f8a249a
BS		 3096 break;
3097 case 0x002: /* V9 fmovdcc %fcc0 */
714547bb 3098 FMOVDCC(0);
0f8a249a
BS		 3099 break;
3100 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3101 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3102 FMOVQCC(0);
1f587329 3103 break;
0f8a249a 3104 case 0x041: /* V9 fmovscc %fcc1 */
714547bb 3105 FMOVSCC(1);
0f8a249a
BS		 3106 break;
3107 case 0x042: /* V9 fmovdcc %fcc1 */
714547bb 3108 FMOVDCC(1);
0f8a249a
BS		 3109 break;
3110 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3111 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3112 FMOVQCC(1);
1f587329 3113 break;
0f8a249a 3114 case 0x081: /* V9 fmovscc %fcc2 */
714547bb 3115 FMOVSCC(2);
0f8a249a
BS		 3116 break;
3117 case 0x082: /* V9 fmovdcc %fcc2 */
714547bb 3118 FMOVDCC(2);
0f8a249a
BS		 3119 break;
3120 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3121 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3122 FMOVQCC(2);
1f587329 3123 break;
0f8a249a 3124 case 0x0c1: /* V9 fmovscc %fcc3 */
714547bb 3125 FMOVSCC(3);
0f8a249a
BS		 3126 break;
3127 case 0x0c2: /* V9 fmovdcc %fcc3 */
714547bb 3128 FMOVDCC(3);
0f8a249a
BS		 3129 break;
3130 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3131 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3132 FMOVQCC(3);
1f587329 3133 break;
714547bb
BS		 3134#undef FMOVSCC
3135#undef FMOVDCC
3136#undef FMOVQCC
714547bb
BS		 3137#define FMOVSCC(icc) \
3138 { \
3139 TCGv r_cond; \
3140 int l1; \
3141 \
3142 l1 = gen_new_label(); \
dc1a6971 3143 r_cond = tcg_temp_new(); \
714547bb 3144 cond = GET_FIELD_SP(insn, 14, 17); \
8393617c 3145 gen_cond(r_cond, icc, cond, dc); \
714547bb
BS		 3146 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3147 0, l1); \
208ae657
RH		 3148 cpu_src1_32 = gen_load_fpr_F(dc, rs2); \
3149 gen_store_fpr_F(dc, rd, cpu_src1_32); \
714547bb
BS		 3150 gen_set_label(l1); \
3151 tcg_temp_free(r_cond); \
3152 }
3153#define FMOVDCC(icc) \
3154 { \
3155 TCGv r_cond; \
3156 int l1; \
3157 \
3158 l1 = gen_new_label(); \
dc1a6971 3159 r_cond = tcg_temp_new(); \
714547bb 3160 cond = GET_FIELD_SP(insn, 14, 17); \
8393617c 3161 gen_cond(r_cond, icc, cond, dc); \
714547bb
BS		 3162 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3163 0, l1); \
96eda024
RH		 3164 cpu_src1_64 = gen_load_fpr_D(dc, rs2); \
3165 gen_store_fpr_D(dc, rd, cpu_src1_64); \
638737ad 3166 gen_update_fprs_dirty(DFPREG(rd)); \
714547bb
BS		 3167 gen_set_label(l1); \
3168 tcg_temp_free(r_cond); \
3169 }
3170#define FMOVQCC(icc) \
3171 { \
3172 TCGv r_cond; \
3173 int l1; \
3174 \
3175 l1 = gen_new_label(); \
dc1a6971 3176 r_cond = tcg_temp_new(); \
714547bb 3177 cond = GET_FIELD_SP(insn, 14, 17); \
8393617c 3178 gen_cond(r_cond, icc, cond, dc); \
714547bb
BS		 3179 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
3180 0, l1); \
ac11f776 3181 gen_move_Q(rd, rs2); \
714547bb
BS		 3182 gen_set_label(l1); \
3183 tcg_temp_free(r_cond); \
3184 }
19f329ad 3185
0f8a249a 3186 case 0x101: /* V9 fmovscc %icc */
714547bb 3187 FMOVSCC(0);
0f8a249a
BS		 3188 break;
3189 case 0x102: /* V9 fmovdcc %icc */
714547bb 3190 FMOVDCC(0);
b7d69dc2 3191 break;
0f8a249a 3192 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3193 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3194 FMOVQCC(0);
1f587329 3195 break;
0f8a249a 3196 case 0x181: /* V9 fmovscc %xcc */
714547bb 3197 FMOVSCC(1);
0f8a249a
BS		 3198 break;
3199 case 0x182: /* V9 fmovdcc %xcc */
714547bb 3200 FMOVDCC(1);
0f8a249a
BS		 3201 break;
3202 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3203 CHECK_FPU_FEATURE(dc, FLOAT128);
714547bb 3204 FMOVQCC(1);
1f587329 3205 break;
714547bb
BS		 3206#undef FMOVSCC
3207#undef FMOVDCC
3208#undef FMOVQCC
1f587329
BS		 3209#endif
3210 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3211 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3212 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3213 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3214 break;
1f587329 3215 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3216 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3217 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3218 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3219 break;
1f587329 3220 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3221 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3222 gen_op_load_fpr_QT0(QFPREG(rs1));
3223 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3224 gen_op_fcmpq(rd & 3);
1f587329 3225 break;
0f8a249a 3226 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3227 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3228 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3229 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3230 break;
3231 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3232 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3233 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3234 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3235 break;
1f587329 3236 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3237 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3238 gen_op_load_fpr_QT0(QFPREG(rs1));
3239 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3240 gen_op_fcmpeq(rd & 3);
1f587329 3241 break;
0f8a249a
BS		 3242 default:
3243 goto illegal_insn;
3244 }
0f8a249a
BS		 3245 } else if (xop == 0x2) {
3246 // clr/mov shortcut
e80cfcfc
FB		 3247
3248 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3249 if (rs1 == 0) {
1a2fb1c0 3250 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a 3251 if (IS_IMM) { /* immediate */
2ea815ca
BS		 3252 TCGv r_const;
3253
67526b20
BS		 3254 simm = GET_FIELDs(insn, 19, 31);
3255 r_const = tcg_const_tl(simm);
2ea815ca
BS		 3256 gen_movl_TN_reg(rd, r_const);
3257 tcg_temp_free(r_const);
0f8a249a
BS		 3258 } else { /* register */
3259 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3260 gen_movl_reg_TN(rs2, cpu_dst);
9c6c6662 3261 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3262 }
0f8a249a 3263 } else {
9322a4bf 3264 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 3265 if (IS_IMM) { /* immediate */
67526b20
BS		 3266 simm = GET_FIELDs(insn, 19, 31);
3267 tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
9c6c6662 3268 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3269 } else { /* register */
3270 // or x, %g0, y -> mov T1, x; mov y, T1
3271 rs2 = GET_FIELD(insn, 27, 31);
3272 if (rs2 != 0) {
6ae20372
BS		 3273 gen_movl_reg_TN(rs2, cpu_src2);
3274 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
9c6c6662 3275 gen_movl_TN_reg(rd, cpu_dst);
6f551262 3276 } else
9c6c6662 3277 gen_movl_TN_reg(rd, cpu_src1);
0f8a249a 3278 }
0f8a249a 3279 }
83469015 3280#ifdef TARGET_SPARC64
0f8a249a 3281 } else if (xop == 0x25) { /* sll, V9 sllx */
9322a4bf 3282 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 3283 if (IS_IMM) { /* immediate */
67526b20 3284 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3285 if (insn & (1 << 12)) {
67526b20 3286 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3287 } else {
67526b20 3288 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3289 }
0f8a249a 3290 } else { /* register */
83469015 3291 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3292 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 3293 if (insn & (1 << 12)) {
6ae20372 3294 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3295 } else {
6ae20372 3296 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3297 }
01b1fa6d 3298 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3299 }
6ae20372 3300 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3301 } else if (xop == 0x26) { /* srl, V9 srlx */
9322a4bf 3302 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 3303 if (IS_IMM) { /* immediate */
67526b20 3304 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3305 if (insn & (1 << 12)) {
67526b20 3306 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3307 } else {
6ae20372 3308 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3309 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3310 }
0f8a249a 3311 } else { /* register */
83469015 3312 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3313 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 3314 if (insn & (1 << 12)) {
6ae20372
BS		 3315 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3316 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3317 } else {
6ae20372
BS		 3318 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3319 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3320 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3321 }
83469015 3322 }
6ae20372 3323 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3324 } else if (xop == 0x27) { /* sra, V9 srax */
9322a4bf 3325 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 3326 if (IS_IMM) { /* immediate */
67526b20 3327 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3328 if (insn & (1 << 12)) {
67526b20 3329 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3330 } else {
6ae20372 3331 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
527067d8 3332 tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
67526b20 3333 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3334 }
0f8a249a 3335 } else { /* register */
83469015 3336 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3337 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 3338 if (insn & (1 << 12)) {
6ae20372
BS		 3339 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3340 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3341 } else {
6ae20372
BS		 3342 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3343 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
527067d8 3344 tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
6ae20372 3345 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3346 }
83469015 3347 }
6ae20372 3348 gen_movl_TN_reg(rd, cpu_dst);
e80cfcfc 3349#endif
fcc72045 3350 } else if (xop < 0x36) {
cf495bcf 3351 if (xop < 0x20) {
41d72852
BS		 3352 cpu_src1 = get_src1(insn, cpu_src1);
3353 cpu_src2 = get_src2(insn, cpu_src2);
cf495bcf 3354 switch (xop & ~0x10) {
b89e94af 3355 case 0x0: /* add */
41d72852
BS		 3356 if (IS_IMM) {
3357 simm = GET_FIELDs(insn, 19, 31);
3358 if (xop & 0x10) {
3359 gen_op_addi_cc(cpu_dst, cpu_src1, simm);
bdf9f35d
BS		 3360 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3361 dc->cc_op = CC_OP_ADD;
41d72852
BS		 3362 } else {
3363 tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
3364 }
3365 } else {
3366 if (xop & 0x10) {
3367 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
bdf9f35d
BS		 3368 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3369 dc->cc_op = CC_OP_ADD;
41d72852
BS		 3370 } else {
3371 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3372 }
3373 }
cf495bcf 3374 break;
b89e94af 3375 case 0x1: /* and */
41d72852
BS		 3376 if (IS_IMM) {
3377 simm = GET_FIELDs(insn, 19, 31);
3378 tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
3379 } else {
3380 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3381 }
3382 if (xop & 0x10) {
38482a77
BS		 3383 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3384 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3385 dc->cc_op = CC_OP_LOGIC;
41d72852 3386 }
cf495bcf 3387 break;
b89e94af 3388 case 0x2: /* or */
41d72852
BS		 3389 if (IS_IMM) {
3390 simm = GET_FIELDs(insn, 19, 31);
3391 tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
3392 } else {
3393 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3394 }
8393617c 3395 if (xop & 0x10) {
38482a77
BS		 3396 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3397 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3398 dc->cc_op = CC_OP_LOGIC;
8393617c 3399 }
0f8a249a 3400 break;
b89e94af 3401 case 0x3: /* xor */
41d72852
BS		 3402 if (IS_IMM) {
3403 simm = GET_FIELDs(insn, 19, 31);
3404 tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
3405 } else {
3406 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3407 }
8393617c 3408 if (xop & 0x10) {
38482a77
BS		 3409 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3410 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3411 dc->cc_op = CC_OP_LOGIC;
8393617c 3412 }
cf495bcf 3413 break;
b89e94af 3414 case 0x4: /* sub */
41d72852
BS		 3415 if (IS_IMM) {
3416 simm = GET_FIELDs(insn, 19, 31);
3417 if (xop & 0x10) {
d4b0d468 3418 gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
41d72852
BS		 3419 } else {
3420 tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
3421 }
3422 } else {
3423 if (xop & 0x10) {
3424 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
d4b0d468
BS		 3425 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3426 dc->cc_op = CC_OP_SUB;
41d72852
BS		 3427 } else {
3428 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3429 }
3430 }
cf495bcf 3431 break;
b89e94af 3432 case 0x5: /* andn */
41d72852
BS		 3433 if (IS_IMM) {
3434 simm = GET_FIELDs(insn, 19, 31);
3435 tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
3436 } else {
3437 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
3438 }
8393617c 3439 if (xop & 0x10) {
38482a77
BS		 3440 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3441 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3442 dc->cc_op = CC_OP_LOGIC;
8393617c 3443 }
cf495bcf 3444 break;
b89e94af 3445 case 0x6: /* orn */
41d72852
BS		 3446 if (IS_IMM) {
3447 simm = GET_FIELDs(insn, 19, 31);
3448 tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
3449 } else {
3450 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
3451 }
8393617c 3452 if (xop & 0x10) {
38482a77
BS		 3453 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3454 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3455 dc->cc_op = CC_OP_LOGIC;
8393617c 3456 }
cf495bcf 3457 break;
b89e94af 3458 case 0x7: /* xorn */
41d72852
BS		 3459 if (IS_IMM) {
3460 simm = GET_FIELDs(insn, 19, 31);
3461 tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
3462 } else {
3463 tcg_gen_not_tl(cpu_tmp0, cpu_src2);
3464 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3465 }
8393617c 3466 if (xop & 0x10) {
38482a77
BS		 3467 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3468 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3469 dc->cc_op = CC_OP_LOGIC;
8393617c 3470 }
cf495bcf 3471 break;
b89e94af 3472 case 0x8: /* addx, V9 addc */
70c48285
RH		 3473 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3474 (xop & 0x10));
cf495bcf 3475 break;
ded3ab80 3476#ifdef TARGET_SPARC64
0f8a249a 3477 case 0x9: /* V9 mulx */
41d72852
BS		 3478 if (IS_IMM) {
3479 simm = GET_FIELDs(insn, 19, 31);
3480 tcg_gen_muli_i64(cpu_dst, cpu_src1, simm);
3481 } else {
3482 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3483 }
ded3ab80
PB		 3484 break;
3485#endif
b89e94af 3486 case 0xa: /* umul */
64a88d5d 3487 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3488 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3489 if (xop & 0x10) {
38482a77
BS		 3490 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3491 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3492 dc->cc_op = CC_OP_LOGIC;
8393617c 3493 }
cf495bcf 3494 break;
b89e94af 3495 case 0xb: /* smul */
64a88d5d 3496 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3497 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3498 if (xop & 0x10) {
38482a77
BS		 3499 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3500 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3501 dc->cc_op = CC_OP_LOGIC;
8393617c 3502 }
cf495bcf 3503 break;
b89e94af 3504 case 0xc: /* subx, V9 subc */
70c48285
RH		 3505 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3506 (xop & 0x10));
cf495bcf 3507 break;
ded3ab80 3508#ifdef TARGET_SPARC64
0f8a249a 3509 case 0xd: /* V9 udivx */
8e91ed30
AT		 3510 {
3511 TCGv r_temp1, r_temp2;
3512 r_temp1 = tcg_temp_local_new();
3513 r_temp2 = tcg_temp_local_new();
3514 tcg_gen_mov_tl(r_temp1, cpu_src1);
3515 tcg_gen_mov_tl(r_temp2, cpu_src2);
3516 gen_trap_ifdivzero_tl(r_temp2);
3517 tcg_gen_divu_i64(cpu_dst, r_temp1, r_temp2);
3518 tcg_temp_free(r_temp1);
3519 tcg_temp_free(r_temp2);
3520 }
ded3ab80
PB		 3521 break;
3522#endif
b89e94af 3523 case 0xe: /* udiv */
64a88d5d 3524 CHECK_IU_FEATURE(dc, DIV);
8393617c 3525 if (xop & 0x10) {
7a5e4488
BS		 3526 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3527 cpu_src2);
6c78ea32 3528 dc->cc_op = CC_OP_DIV;
0fcec41e 3529 } else {
7a5e4488
BS		 3530 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3531 cpu_src2);
8393617c 3532 }
cf495bcf 3533 break;
b89e94af 3534 case 0xf: /* sdiv */
64a88d5d 3535 CHECK_IU_FEATURE(dc, DIV);
8393617c 3536 if (xop & 0x10) {
7a5e4488
BS		 3537 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3538 cpu_src2);
6c78ea32 3539 dc->cc_op = CC_OP_DIV;
0fcec41e 3540 } else {
7a5e4488
BS		 3541 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3542 cpu_src2);
8393617c 3543 }
cf495bcf
FB		 3544 break;
3545 default:
3546 goto illegal_insn;
3547 }
6ae20372 3548 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3549 } else {
41d72852
BS		 3550 cpu_src1 = get_src1(insn, cpu_src1);
3551 cpu_src2 = get_src2(insn, cpu_src2);
cf495bcf 3552 switch (xop) {
0f8a249a 3553 case 0x20: /* taddcc */
6ae20372
BS		 3554 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3555 gen_movl_TN_reg(rd, cpu_dst);
3b2d1e92
BS		 3556 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3557 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3558 break;
3559 case 0x21: /* tsubcc */
6ae20372
BS		 3560 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3561 gen_movl_TN_reg(rd, cpu_dst);
3b2d1e92
BS		 3562 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3563 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3564 break;
3565 case 0x22: /* taddcctv */
6ae20372
BS		 3566 save_state(dc, cpu_cond);
3567 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3568 gen_movl_TN_reg(rd, cpu_dst);
3b2d1e92
BS		 3569 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV);
3570 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3571 break;
3572 case 0x23: /* tsubcctv */
6ae20372
BS		 3573 save_state(dc, cpu_cond);
3574 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3575 gen_movl_TN_reg(rd, cpu_dst);
3b2d1e92
BS		 3576 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV);
3577 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3578 break;
cf495bcf 3579 case 0x24: /* mulscc */
2ffd9176 3580 gen_helper_compute_psr(cpu_env);
6ae20372
BS		 3581 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3582 gen_movl_TN_reg(rd, cpu_dst);
d084469c
BS		 3583 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3584 dc->cc_op = CC_OP_ADD;
cf495bcf 3585 break;
83469015 3586#ifndef TARGET_SPARC64
0f8a249a 3587 case 0x25: /* sll */
e35298cd 3588 if (IS_IMM) { /* immediate */
67526b20
BS		 3589 simm = GET_FIELDs(insn, 20, 31);
3590 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd
BS		 3591 } else { /* register */
3592 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3593 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3594 }
6ae20372 3595 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3596 break;
83469015 3597 case 0x26: /* srl */
e35298cd 3598 if (IS_IMM) { /* immediate */
67526b20
BS		 3599 simm = GET_FIELDs(insn, 20, 31);
3600 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd
BS		 3601 } else { /* register */
3602 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3603 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3604 }
6ae20372 3605 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3606 break;
83469015 3607 case 0x27: /* sra */
e35298cd 3608 if (IS_IMM) { /* immediate */
67526b20
BS		 3609 simm = GET_FIELDs(insn, 20, 31);
3610 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd
BS		 3611 } else { /* register */
3612 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3613 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3614 }
6ae20372 3615 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3616 break;
83469015 3617#endif
cf495bcf
FB		 3618 case 0x30:
3619 {
cf495bcf 3620 switch(rd) {
3475187d 3621 case 0: /* wry */
5068cbd9
BS		 3622 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3623 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3624 break;
65fe7b09
BS		 3625#ifndef TARGET_SPARC64
3626 case 0x01 ... 0x0f: /* undefined in the
3627 SPARCv8 manual, nop
3628 on the microSPARC
3629 II */
3630 case 0x10 ... 0x1f: /* implementation-dependent
3631 in the SPARCv8
3632 manual, nop on the
3633 microSPARC II */
3634 break;
3635#else
0f8a249a 3636 case 0x2: /* V9 wrccr */
6ae20372 3637 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
063c3675 3638 gen_helper_wrccr(cpu_env, cpu_dst);
8393617c
BS		 3639 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3640 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3641 break;
3642 case 0x3: /* V9 wrasi */
6ae20372 3643 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
01b5d4e5 3644 tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
255e1fcb 3645 tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
0f8a249a
BS		 3646 break;
3647 case 0x6: /* V9 wrfprs */
6ae20372 3648 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
255e1fcb 3649 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
6ae20372 3650 save_state(dc, cpu_cond);
3299908c 3651 gen_op_next_insn();
57fec1fe 3652 tcg_gen_exit_tb(0);
3299908c 3653 dc->is_br = 1;
0f8a249a
BS		 3654 break;
3655 case 0xf: /* V9 sir, nop if user */
3475187d 3656#if !defined(CONFIG_USER_ONLY)
6ad6135d 3657 if (supervisor(dc)) {
1a2fb1c0 3658 ; // XXX
6ad6135d 3659 }
3475187d 3660#endif
0f8a249a
BS		 3661 break;
3662 case 0x13: /* Graphics Status */
6ae20372 3663 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 3664 goto jmp_insn;
255e1fcb 3665 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3666 break;
9d926598
BS		 3667 case 0x14: /* Softint set */
3668 if (!supervisor(dc))
3669 goto illegal_insn;
3670 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
79227036 3671 gen_helper_set_softint(cpu_env, cpu_tmp64);
9d926598
BS		 3672 break;
3673 case 0x15: /* Softint clear */
3674 if (!supervisor(dc))
3675 goto illegal_insn;
3676 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
79227036 3677 gen_helper_clear_softint(cpu_env, cpu_tmp64);
9d926598
BS		 3678 break;
3679 case 0x16: /* Softint write */
3680 if (!supervisor(dc))
3681 goto illegal_insn;
3682 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
79227036 3683 gen_helper_write_softint(cpu_env, cpu_tmp64);
9d926598 3684 break;
0f8a249a 3685 case 0x17: /* Tick compare */
83469015 3686#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3687 if (!supervisor(dc))
3688 goto illegal_insn;
83469015 3689#endif
ccd4a219 3690 {
a7812ae4 3691 TCGv_ptr r_tickptr;
ccd4a219 3692
255e1fcb 3693 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3694 cpu_src2);
a7812ae4 3695 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 3696 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3697 offsetof(CPUState, tick));
a7812ae4
PB		 3698 gen_helper_tick_set_limit(r_tickptr,
3699 cpu_tick_cmpr);
3700 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3701 }
0f8a249a
BS		 3702 break;
3703 case 0x18: /* System tick */
83469015 3704#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3705 if (!supervisor(dc))
3706 goto illegal_insn;
83469015 3707#endif
ccd4a219 3708 {
a7812ae4 3709 TCGv_ptr r_tickptr;
ccd4a219 3710
6ae20372
BS		 3711 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3712 cpu_src2);
a7812ae4 3713 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 3714 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3715 offsetof(CPUState, stick));
a7812ae4
PB		 3716 gen_helper_tick_set_count(r_tickptr,
3717 cpu_dst);
3718 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3719 }
0f8a249a
BS		 3720 break;
3721 case 0x19: /* System tick compare */
83469015 3722#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3723 if (!supervisor(dc))
3724 goto illegal_insn;
3475187d 3725#endif
ccd4a219 3726 {
a7812ae4 3727 TCGv_ptr r_tickptr;
ccd4a219 3728
255e1fcb 3729 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3730 cpu_src2);
a7812ae4 3731 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 3732 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3733 offsetof(CPUState, stick));
a7812ae4
PB		 3734 gen_helper_tick_set_limit(r_tickptr,
3735 cpu_stick_cmpr);
3736 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3737 }
0f8a249a 3738 break;
83469015 3739
0f8a249a 3740 case 0x10: /* Performance Control */
77f193da
BS		 3741 case 0x11: /* Performance Instrumentation
3742 Counter */
0f8a249a 3743 case 0x12: /* Dispatch Control */
83469015 3744#endif
3475187d 3745 default:
cf495bcf
FB		 3746 goto illegal_insn;
3747 }
3748 }
3749 break;
e8af50a3 3750#if !defined(CONFIG_USER_ONLY)
af7bf89b 3751 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3752 {
0f8a249a
BS		 3753 if (!supervisor(dc))
3754 goto priv_insn;
3475187d 3755#ifdef TARGET_SPARC64
0f8a249a
BS		 3756 switch (rd) {
3757 case 0:
063c3675 3758 gen_helper_saved(cpu_env);
0f8a249a
BS		 3759 break;
3760 case 1:
063c3675 3761 gen_helper_restored(cpu_env);
0f8a249a 3762 break;
e9ebed4d
BS		 3763 case 2: /* UA2005 allclean */
3764 case 3: /* UA2005 otherw */
3765 case 4: /* UA2005 normalw */
3766 case 5: /* UA2005 invalw */
3767 // XXX
0f8a249a 3768 default:
3475187d
FB		 3769 goto illegal_insn;
3770 }
3771#else
6ae20372 3772 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
063c3675 3773 gen_helper_wrpsr(cpu_env, cpu_dst);
8393617c
BS		 3774 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3775 dc->cc_op = CC_OP_FLAGS;
6ae20372 3776 save_state(dc, cpu_cond);
9e61bde5 3777 gen_op_next_insn();
57fec1fe 3778 tcg_gen_exit_tb(0);
0f8a249a 3779 dc->is_br = 1;
3475187d 3780#endif
e8af50a3
FB		 3781 }
3782 break;
af7bf89b 3783 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3784 {
0f8a249a
BS		 3785 if (!supervisor(dc))
3786 goto priv_insn;
ece43b8d 3787 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3788#ifdef TARGET_SPARC64
0f8a249a
BS		 3789 switch (rd) {
3790 case 0: // tpc
375ee38b 3791 {
a7812ae4 3792 TCGv_ptr r_tsptr;
375ee38b 3793
a7812ae4 3794 r_tsptr = tcg_temp_new_ptr();
8194f35a 3795 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3796 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3797 offsetof(trap_state, tpc));
a7812ae4 3798 tcg_temp_free_ptr(r_tsptr);
375ee38b 3799 }
0f8a249a
BS		 3800 break;
3801 case 1: // tnpc
375ee38b 3802 {
a7812ae4 3803 TCGv_ptr r_tsptr;
375ee38b 3804
a7812ae4 3805 r_tsptr = tcg_temp_new_ptr();
8194f35a 3806 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3807 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3808 offsetof(trap_state, tnpc));
a7812ae4 3809 tcg_temp_free_ptr(r_tsptr);
375ee38b 3810 }
0f8a249a
BS		 3811 break;
3812 case 2: // tstate
375ee38b 3813 {
a7812ae4 3814 TCGv_ptr r_tsptr;
375ee38b 3815
a7812ae4 3816 r_tsptr = tcg_temp_new_ptr();
8194f35a 3817 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3818 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3819 offsetof(trap_state,
3820 tstate));
a7812ae4 3821 tcg_temp_free_ptr(r_tsptr);
375ee38b 3822 }
0f8a249a
BS		 3823 break;
3824 case 3: // tt
375ee38b 3825 {
a7812ae4 3826 TCGv_ptr r_tsptr;
375ee38b 3827
a7812ae4 3828 r_tsptr = tcg_temp_new_ptr();
8194f35a 3829 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
527067d8
BS		 3830 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3831 tcg_gen_st_i32(cpu_tmp32, r_tsptr,
375ee38b 3832 offsetof(trap_state, tt));
a7812ae4 3833 tcg_temp_free_ptr(r_tsptr);
375ee38b 3834 }
0f8a249a
BS		 3835 break;
3836 case 4: // tick
ccd4a219 3837 {
a7812ae4 3838 TCGv_ptr r_tickptr;
ccd4a219 3839
a7812ae4 3840 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 3841 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3842 offsetof(CPUState, tick));
a7812ae4
PB		 3843 gen_helper_tick_set_count(r_tickptr,
3844 cpu_tmp0);
3845 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3846 }
0f8a249a
BS		 3847 break;
3848 case 5: // tba
255e1fcb 3849 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3850 break;
3851 case 6: // pstate
a2589e5c
BS		 3852 {
3853 TCGv r_tmp = tcg_temp_local_new();
3854
3855 tcg_gen_mov_tl(r_tmp, cpu_tmp0);
3856 save_state(dc, cpu_cond);
063c3675 3857 gen_helper_wrpstate(cpu_env, r_tmp);
a2589e5c
BS		 3858 tcg_temp_free(r_tmp);
3859 dc->npc = DYNAMIC_PC;
3860 }
0f8a249a
BS		 3861 break;
3862 case 7: // tl
a2589e5c
BS		 3863 {
3864 TCGv r_tmp = tcg_temp_local_new();
3865
3866 tcg_gen_mov_tl(r_tmp, cpu_tmp0);
3867 save_state(dc, cpu_cond);
3868 tcg_gen_trunc_tl_i32(cpu_tmp32, r_tmp);
3869 tcg_temp_free(r_tmp);
3870 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3871 offsetof(CPUSPARCState, tl));
3872 dc->npc = DYNAMIC_PC;
3873 }
0f8a249a
BS		 3874 break;
3875 case 8: // pil
063c3675 3876 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3877 break;
3878 case 9: // cwp
063c3675 3879 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3880 break;
3881 case 10: // cansave
ece43b8d 3882 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3883 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3884 offsetof(CPUSPARCState,
3885 cansave));
0f8a249a
BS		 3886 break;
3887 case 11: // canrestore
ece43b8d 3888 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3889 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3890 offsetof(CPUSPARCState,
3891 canrestore));
0f8a249a
BS		 3892 break;
3893 case 12: // cleanwin
ece43b8d 3894 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3895 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3896 offsetof(CPUSPARCState,
3897 cleanwin));
0f8a249a
BS		 3898 break;
3899 case 13: // otherwin
ece43b8d 3900 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3901 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3902 offsetof(CPUSPARCState,
3903 otherwin));
0f8a249a
BS		 3904 break;
3905 case 14: // wstate
ece43b8d 3906 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3907 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3908 offsetof(CPUSPARCState,
3909 wstate));
0f8a249a 3910 break;
e9ebed4d 3911 case 16: // UA2005 gl
fb79ceb9 3912 CHECK_IU_FEATURE(dc, GL);
ece43b8d 3913 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3914 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3915 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3916 break;
3917 case 26: // UA2005 strand status
fb79ceb9 3918 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3919 if (!hypervisor(dc))
3920 goto priv_insn;
527067d8 3921 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3922 break;
0f8a249a
BS		 3923 default:
3924 goto illegal_insn;
3925 }
3475187d 3926#else
ece43b8d 3927 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
c93e7817
BS		 3928 if (dc->def->nwindows != 32)
3929 tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3930 (1 << dc->def->nwindows) - 1);
255e1fcb 3931 tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
3475187d 3932#endif
e8af50a3
FB		 3933 }
3934 break;
e9ebed4d 3935 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3936 {
e9ebed4d 3937#ifndef TARGET_SPARC64
0f8a249a
BS		 3938 if (!supervisor(dc))
3939 goto priv_insn;
255e1fcb 3940 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3941#else
fb79ceb9 3942 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3943 if (!hypervisor(dc))
3944 goto priv_insn;
ece43b8d 3945 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3946 switch (rd) {
3947 case 0: // hpstate
3948 // XXX gen_op_wrhpstate();
6ae20372 3949 save_state(dc, cpu_cond);
e9ebed4d 3950 gen_op_next_insn();
57fec1fe 3951 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3952 dc->is_br = 1;
3953 break;
3954 case 1: // htstate
3955 // XXX gen_op_wrhtstate();
3956 break;
3957 case 3: // hintp
255e1fcb 3958 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3959 break;
3960 case 5: // htba
255e1fcb 3961 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3962 break;
3963 case 31: // hstick_cmpr
ccd4a219 3964 {
a7812ae4 3965 TCGv_ptr r_tickptr;
ccd4a219 3966
255e1fcb 3967 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3968 r_tickptr = tcg_temp_new_ptr();
ccd4a219
BS		 3969 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3970 offsetof(CPUState, hstick));
a7812ae4
PB		 3971 gen_helper_tick_set_limit(r_tickptr,
3972 cpu_hstick_cmpr);
3973 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3974 }
e9ebed4d
BS		 3975 break;
3976 case 6: // hver readonly
3977 default:
3978 goto illegal_insn;
3979 }
3980#endif
e8af50a3
FB		 3981 }
3982 break;
3983#endif
3475187d 3984#ifdef TARGET_SPARC64
0f8a249a
BS		 3985 case 0x2c: /* V9 movcc */
3986 {
3987 int cc = GET_FIELD_SP(insn, 11, 12);
3988 int cond = GET_FIELD_SP(insn, 14, 17);
748b9d8e 3989 TCGv r_cond;
00f219bf
BS		 3990 int l1;
3991
a7812ae4 3992 r_cond = tcg_temp_new();
0f8a249a
BS		 3993 if (insn & (1 << 18)) {
3994 if (cc == 0)
8393617c 3995 gen_cond(r_cond, 0, cond, dc);
0f8a249a 3996 else if (cc == 2)
8393617c 3997 gen_cond(r_cond, 1, cond, dc);
0f8a249a
BS		 3998 else
3999 goto illegal_insn;
4000 } else {
748b9d8e 4001 gen_fcond(r_cond, cc, cond);
0f8a249a 4002 }
00f219bf
BS		 4003
4004 l1 = gen_new_label();
4005
cb63669a 4006 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
00f219bf 4007 if (IS_IMM) { /* immediate */
2ea815ca
BS		 4008 TCGv r_const;
4009
67526b20
BS		 4010 simm = GET_FIELD_SPs(insn, 0, 10);
4011 r_const = tcg_const_tl(simm);
2ea815ca
BS		 4012 gen_movl_TN_reg(rd, r_const);
4013 tcg_temp_free(r_const);
00f219bf
BS		 4014 } else {
4015 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 4016 gen_movl_reg_TN(rs2, cpu_tmp0);
4017 gen_movl_TN_reg(rd, cpu_tmp0);
00f219bf 4018 }
00f219bf 4019 gen_set_label(l1);
2ea815ca 4020 tcg_temp_free(r_cond);
0f8a249a
BS		 4021 break;
4022 }
4023 case 0x2d: /* V9 sdivx */
6ae20372
BS		 4024 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
4025 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 4026 break;
4027 case 0x2e: /* V9 popc */
4028 {
a49d9390 4029 cpu_src2 = get_src2(insn, cpu_src2);
a7812ae4 4030 gen_helper_popc(cpu_dst, cpu_src2);
6ae20372 4031 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 4032 }
4033 case 0x2f: /* V9 movr */
4034 {
4035 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 4036 int l1;
4037
9322a4bf 4038 cpu_src1 = get_src1(insn, cpu_src1);
00f219bf
BS		 4039
4040 l1 = gen_new_label();
4041
cb63669a
PB		 4042 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
4043 cpu_src1, 0, l1);
0f8a249a 4044 if (IS_IMM) { /* immediate */
2ea815ca
BS		 4045 TCGv r_const;
4046
67526b20
BS		 4047 simm = GET_FIELD_SPs(insn, 0, 9);
4048 r_const = tcg_const_tl(simm);
2ea815ca
BS		 4049 gen_movl_TN_reg(rd, r_const);
4050 tcg_temp_free(r_const);
00f219bf 4051 } else {
0f8a249a 4052 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 4053 gen_movl_reg_TN(rs2, cpu_tmp0);
4054 gen_movl_TN_reg(rd, cpu_tmp0);
0f8a249a 4055 }
00f219bf 4056 gen_set_label(l1);
0f8a249a
BS		 4057 break;
4058 }
4059#endif
4060 default:
4061 goto illegal_insn;
4062 }
4063 }
3299908c
BS		 4064 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4065#ifdef TARGET_SPARC64
4066 int opf = GET_FIELD_SP(insn, 5, 13);
4067 rs1 = GET_FIELD(insn, 13, 17);
4068 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 4069 if (gen_trap_ifnofpu(dc, cpu_cond))
e9ebed4d 4070 goto jmp_insn;
3299908c
BS		 4071
4072 switch (opf) {
e9ebed4d 4073 case 0x000: /* VIS I edge8cc */
6c073553
RH		 4074 CHECK_FPU_FEATURE(dc, VIS1);
4075 gen_movl_reg_TN(rs1, cpu_src1);
4076 gen_movl_reg_TN(rs2, cpu_src2);
4077 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
4078 gen_movl_TN_reg(rd, cpu_dst);
4079 break;
e9ebed4d 4080 case 0x001: /* VIS II edge8n */
6c073553
RH		 4081 CHECK_FPU_FEATURE(dc, VIS2);
4082 gen_movl_reg_TN(rs1, cpu_src1);
4083 gen_movl_reg_TN(rs2, cpu_src2);
4084 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
4085 gen_movl_TN_reg(rd, cpu_dst);
4086 break;
e9ebed4d 4087 case 0x002: /* VIS I edge8lcc */
6c073553
RH		 4088 CHECK_FPU_FEATURE(dc, VIS1);
4089 gen_movl_reg_TN(rs1, cpu_src1);
4090 gen_movl_reg_TN(rs2, cpu_src2);
4091 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
4092 gen_movl_TN_reg(rd, cpu_dst);
4093 break;
e9ebed4d 4094 case 0x003: /* VIS II edge8ln */
6c073553
RH		 4095 CHECK_FPU_FEATURE(dc, VIS2);
4096 gen_movl_reg_TN(rs1, cpu_src1);
4097 gen_movl_reg_TN(rs2, cpu_src2);
4098 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
4099 gen_movl_TN_reg(rd, cpu_dst);
4100 break;
e9ebed4d 4101 case 0x004: /* VIS I edge16cc */
6c073553
RH		 4102 CHECK_FPU_FEATURE(dc, VIS1);
4103 gen_movl_reg_TN(rs1, cpu_src1);
4104 gen_movl_reg_TN(rs2, cpu_src2);
4105 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
4106 gen_movl_TN_reg(rd, cpu_dst);
4107 break;
e9ebed4d 4108 case 0x005: /* VIS II edge16n */
6c073553
RH		 4109 CHECK_FPU_FEATURE(dc, VIS2);
4110 gen_movl_reg_TN(rs1, cpu_src1);
4111 gen_movl_reg_TN(rs2, cpu_src2);
4112 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
4113 gen_movl_TN_reg(rd, cpu_dst);
4114 break;
e9ebed4d 4115 case 0x006: /* VIS I edge16lcc */
6c073553
RH		 4116 CHECK_FPU_FEATURE(dc, VIS1);
4117 gen_movl_reg_TN(rs1, cpu_src1);
4118 gen_movl_reg_TN(rs2, cpu_src2);
4119 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
4120 gen_movl_TN_reg(rd, cpu_dst);
4121 break;
e9ebed4d 4122 case 0x007: /* VIS II edge16ln */
6c073553
RH		 4123 CHECK_FPU_FEATURE(dc, VIS2);
4124 gen_movl_reg_TN(rs1, cpu_src1);
4125 gen_movl_reg_TN(rs2, cpu_src2);
4126 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
4127 gen_movl_TN_reg(rd, cpu_dst);
4128 break;
e9ebed4d 4129 case 0x008: /* VIS I edge32cc */
6c073553
RH		 4130 CHECK_FPU_FEATURE(dc, VIS1);
4131 gen_movl_reg_TN(rs1, cpu_src1);
4132 gen_movl_reg_TN(rs2, cpu_src2);
4133 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
4134 gen_movl_TN_reg(rd, cpu_dst);
4135 break;
e9ebed4d 4136 case 0x009: /* VIS II edge32n */
6c073553
RH		 4137 CHECK_FPU_FEATURE(dc, VIS2);
4138 gen_movl_reg_TN(rs1, cpu_src1);
4139 gen_movl_reg_TN(rs2, cpu_src2);
4140 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
4141 gen_movl_TN_reg(rd, cpu_dst);
4142 break;
e9ebed4d 4143 case 0x00a: /* VIS I edge32lcc */
6c073553
RH		 4144 CHECK_FPU_FEATURE(dc, VIS1);
4145 gen_movl_reg_TN(rs1, cpu_src1);
4146 gen_movl_reg_TN(rs2, cpu_src2);
4147 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
4148 gen_movl_TN_reg(rd, cpu_dst);
4149 break;
e9ebed4d 4150 case 0x00b: /* VIS II edge32ln */
6c073553
RH		 4151 CHECK_FPU_FEATURE(dc, VIS2);
4152 gen_movl_reg_TN(rs1, cpu_src1);
4153 gen_movl_reg_TN(rs2, cpu_src2);
4154 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
4155 gen_movl_TN_reg(rd, cpu_dst);
4156 break;
e9ebed4d 4157 case 0x010: /* VIS I array8 */
64a88d5d 4158 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 4159 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 4160 gen_movl_reg_TN(rs2, cpu_src2);
f027c3b1 4161 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4162 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4163 break;
4164 case 0x012: /* VIS I array16 */
64a88d5d 4165 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 4166 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 4167 gen_movl_reg_TN(rs2, cpu_src2);
f027c3b1 4168 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372
BS		 4169 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
4170 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4171 break;
4172 case 0x014: /* VIS I array32 */
64a88d5d 4173 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 4174 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 4175 gen_movl_reg_TN(rs2, cpu_src2);
f027c3b1 4176 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372
BS		 4177 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
4178 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d 4179 break;
3299908c 4180 case 0x018: /* VIS I alignaddr */
64a88d5d 4181 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 4182 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 4183 gen_movl_reg_TN(rs2, cpu_src2);
add545ab 4184 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
6ae20372 4185 gen_movl_TN_reg(rd, cpu_dst);
3299908c
BS		 4186 break;
4187 case 0x01a: /* VIS I alignaddrl */
add545ab
RH		 4188 CHECK_FPU_FEATURE(dc, VIS1);
4189 cpu_src1 = get_src1(insn, cpu_src1);
4190 gen_movl_reg_TN(rs2, cpu_src2);
4191 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
4192 gen_movl_TN_reg(rd, cpu_dst);
4193 break;
4194 case 0x019: /* VIS II bmask */
3299908c 4195 // XXX
e9ebed4d
BS		 4196 goto illegal_insn;
4197 case 0x020: /* VIS I fcmple16 */
64a88d5d 4198 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4199 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4200 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4201 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4202 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4203 break;
4204 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4205 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4206 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4207 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4208 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4209 gen_movl_TN_reg(rd, cpu_dst);
3299908c 4210 break;
e9ebed4d 4211 case 0x024: /* VIS I fcmple32 */
64a88d5d 4212 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4213 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4214 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4215 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4216 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4217 break;
4218 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4219 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4220 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4221 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4222 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4223 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4224 break;
4225 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4226 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4227 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4228 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4229 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4230 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4231 break;
4232 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4233 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4234 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4235 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4236 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4237 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4238 break;
4239 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4240 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4241 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4242 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4243 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4244 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4245 break;
4246 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4247 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4248 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4249 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4250 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
afcb7375 4251 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 4252 break;
4253 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4254 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4255 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4256 break;
4257 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4258 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4259 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4260 break;
4261 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4262 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4263 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4264 break;
4265 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4266 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4267 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4268 break;
4269 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4270 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4271 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4272 break;
4273 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4274 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4275 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4276 break;
4277 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4278 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4279 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4280 break;
4281 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4282 CHECK_FPU_FEATURE(dc, VIS1);
4283 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4284 break;
e9ebed4d 4285 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4286 CHECK_FPU_FEATURE(dc, VIS1);
4287 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4288 cpu_dst_32 = gen_dest_fpr_F();
4289 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4290 gen_store_fpr_F(dc, rd, cpu_dst_32);
4291 break;
e9ebed4d 4292 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4293 CHECK_FPU_FEATURE(dc, VIS1);
4294 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4295 cpu_dst_32 = gen_dest_fpr_F();
4296 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4297 gen_store_fpr_F(dc, rd, cpu_dst_32);
4298 break;
f888300b
RH		 4299 case 0x03e: /* VIS I pdist */
4300 CHECK_FPU_FEATURE(dc, VIS1);
4301 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4302 break;
3299908c 4303 case 0x048: /* VIS I faligndata */
64a88d5d 4304 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4305 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4306 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4307 cpu_dst_64 = gen_dest_fpr_D();
4308 gen_helper_faligndata(cpu_dst_64, cpu_env,
4309 cpu_src1_64, cpu_src2_64);
4310 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c 4311 break;
e9ebed4d 4312 case 0x04b: /* VIS I fpmerge */
64a88d5d 4313 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4314 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4315 break;
4316 case 0x04c: /* VIS II bshuffle */
4317 // XXX
4318 goto illegal_insn;
4319 case 0x04d: /* VIS I fexpand */
64a88d5d 4320 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4321 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4322 break;
4323 case 0x050: /* VIS I fpadd16 */
64a88d5d 4324 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4325 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4326 break;
4327 case 0x051: /* VIS I fpadd16s */
64a88d5d 4328 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4329 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4330 break;
4331 case 0x052: /* VIS I fpadd32 */
64a88d5d 4332 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4333 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4334 break;
4335 case 0x053: /* VIS I fpadd32s */
64a88d5d 4336 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4337 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4338 break;
4339 case 0x054: /* VIS I fpsub16 */
64a88d5d 4340 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4341 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4342 break;
4343 case 0x055: /* VIS I fpsub16s */
64a88d5d 4344 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4345 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4346 break;
4347 case 0x056: /* VIS I fpsub32 */
64a88d5d 4348 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4349 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4350 break;
4351 case 0x057: /* VIS I fpsub32s */
64a88d5d 4352 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4353 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4354 break;
3299908c 4355 case 0x060: /* VIS I fzero */
64a88d5d 4356 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4357 cpu_dst_64 = gen_dest_fpr_D();
4358 tcg_gen_movi_i64(cpu_dst_64, 0);
4359 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4360 break;
4361 case 0x061: /* VIS I fzeros */
64a88d5d 4362 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4363 cpu_dst_32 = gen_dest_fpr_F();
4364 tcg_gen_movi_i32(cpu_dst_32, 0);
4365 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4366 break;
e9ebed4d 4367 case 0x062: /* VIS I fnor */
64a88d5d 4368 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4369 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4370 break;
4371 case 0x063: /* VIS I fnors */
64a88d5d 4372 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4373 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4374 break;
4375 case 0x064: /* VIS I fandnot2 */
64a88d5d 4376 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4377 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4378 break;
4379 case 0x065: /* VIS I fandnot2s */
64a88d5d 4380 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4381 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4382 break;
4383 case 0x066: /* VIS I fnot2 */
64a88d5d 4384 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4385 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4386 break;
4387 case 0x067: /* VIS I fnot2s */
64a88d5d 4388 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4389 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4390 break;
4391 case 0x068: /* VIS I fandnot1 */
64a88d5d 4392 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4393 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4394 break;
4395 case 0x069: /* VIS I fandnot1s */
64a88d5d 4396 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4397 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4398 break;
4399 case 0x06a: /* VIS I fnot1 */
64a88d5d 4400 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4401 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4402 break;
4403 case 0x06b: /* VIS I fnot1s */
64a88d5d 4404 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4405 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4406 break;
4407 case 0x06c: /* VIS I fxor */
64a88d5d 4408 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4409 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4410 break;
4411 case 0x06d: /* VIS I fxors */
64a88d5d 4412 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4413 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4414 break;
4415 case 0x06e: /* VIS I fnand */
64a88d5d 4416 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4417 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4418 break;
4419 case 0x06f: /* VIS I fnands */
64a88d5d 4420 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4421 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4422 break;
4423 case 0x070: /* VIS I fand */
64a88d5d 4424 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4425 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4426 break;
4427 case 0x071: /* VIS I fands */
64a88d5d 4428 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4429 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4430 break;
4431 case 0x072: /* VIS I fxnor */
64a88d5d 4432 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4433 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4434 break;
4435 case 0x073: /* VIS I fxnors */
64a88d5d 4436 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4437 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4438 break;
3299908c 4439 case 0x074: /* VIS I fsrc1 */
64a88d5d 4440 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4441 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4442 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4443 break;
4444 case 0x075: /* VIS I fsrc1s */
64a88d5d 4445 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4446 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4447 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4448 break;
e9ebed4d 4449 case 0x076: /* VIS I fornot2 */
64a88d5d 4450 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4451 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4452 break;
4453 case 0x077: /* VIS I fornot2s */
64a88d5d 4454 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4455 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4456 break;
3299908c 4457 case 0x078: /* VIS I fsrc2 */
64a88d5d 4458 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4459 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4460 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4461 break;
4462 case 0x079: /* VIS I fsrc2s */
64a88d5d 4463 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4464 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4465 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4466 break;
e9ebed4d 4467 case 0x07a: /* VIS I fornot1 */
64a88d5d 4468 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4469 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4470 break;
4471 case 0x07b: /* VIS I fornot1s */
64a88d5d 4472 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4473 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4474 break;
4475 case 0x07c: /* VIS I for */
64a88d5d 4476 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4477 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4478 break;
4479 case 0x07d: /* VIS I fors */
64a88d5d 4480 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4481 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4482 break;
3299908c 4483 case 0x07e: /* VIS I fone */
64a88d5d 4484 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4485 cpu_dst_64 = gen_dest_fpr_D();
4486 tcg_gen_movi_i64(cpu_dst_64, -1);
4487 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4488 break;
4489 case 0x07f: /* VIS I fones */
64a88d5d 4490 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4491 cpu_dst_32 = gen_dest_fpr_F();
4492 tcg_gen_movi_i32(cpu_dst_32, -1);
4493 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4494 break;
e9ebed4d
BS		 4495 case 0x080: /* VIS I shutdown */
4496 case 0x081: /* VIS II siam */
4497 // XXX
4498 goto illegal_insn;
3299908c
BS		 4499 default:
4500 goto illegal_insn;
4501 }
4502#else
0f8a249a 4503 goto ncp_insn;
3299908c
BS		 4504#endif
4505 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4506#ifdef TARGET_SPARC64
0f8a249a 4507 goto illegal_insn;
fcc72045 4508#else
0f8a249a 4509 goto ncp_insn;
fcc72045 4510#endif
3475187d 4511#ifdef TARGET_SPARC64
0f8a249a 4512 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4513 TCGv_i32 r_const;
2ea815ca 4514
6ae20372 4515 save_state(dc, cpu_cond);
9322a4bf 4516 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 4517 if (IS_IMM) { /* immediate */
67526b20
BS		 4518 simm = GET_FIELDs(insn, 19, 31);
4519 tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
0f8a249a 4520 } else { /* register */
3475187d 4521 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4522 if (rs2) {
6ae20372
BS		 4523 gen_movl_reg_TN(rs2, cpu_src2);
4524 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 4525 } else
4526 tcg_gen_mov_tl(cpu_dst, cpu_src1);
3475187d 4527 }
063c3675 4528 gen_helper_restore(cpu_env);
6ae20372 4529 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca 4530 r_const = tcg_const_i32(3);
a7812ae4
PB		 4531 gen_helper_check_align(cpu_dst, r_const);
4532 tcg_temp_free_i32(r_const);
6ae20372 4533 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 4534 dc->npc = DYNAMIC_PC;
4535 goto jmp_insn;
3475187d 4536#endif
0f8a249a 4537 } else {
9322a4bf 4538 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 4539 if (IS_IMM) { /* immediate */
67526b20
BS		 4540 simm = GET_FIELDs(insn, 19, 31);
4541 tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
0f8a249a 4542 } else { /* register */
e80cfcfc 4543 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4544 if (rs2) {
6ae20372
BS		 4545 gen_movl_reg_TN(rs2, cpu_src2);
4546 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 4547 } else
4548 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 4549 }
0f8a249a
BS		 4550 switch (xop) {
4551 case 0x38: /* jmpl */
4552 {
a7812ae4
PB		 4553 TCGv r_pc;
4554 TCGv_i32 r_const;
2ea815ca 4555
a7812ae4
PB		 4556 r_pc = tcg_const_tl(dc->pc);
4557 gen_movl_TN_reg(rd, r_pc);
4558 tcg_temp_free(r_pc);
6ae20372 4559 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca 4560 r_const = tcg_const_i32(3);
a7812ae4
PB		 4561 gen_helper_check_align(cpu_dst, r_const);
4562 tcg_temp_free_i32(r_const);
6ae20372 4563 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 4564 dc->npc = DYNAMIC_PC;
4565 }
4566 goto jmp_insn;
3475187d 4567#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4568 case 0x39: /* rett, V9 return */
4569 {
a7812ae4 4570 TCGv_i32 r_const;
2ea815ca 4571
0f8a249a
BS		 4572 if (!supervisor(dc))
4573 goto priv_insn;
6ae20372 4574 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca 4575 r_const = tcg_const_i32(3);
a7812ae4
PB		 4576 gen_helper_check_align(cpu_dst, r_const);
4577 tcg_temp_free_i32(r_const);
6ae20372 4578 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a 4579 dc->npc = DYNAMIC_PC;
063c3675 4580 gen_helper_rett(cpu_env);
0f8a249a
BS		 4581 }
4582 goto jmp_insn;
4583#endif
4584 case 0x3b: /* flush */
5578ceab 4585 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4586 goto unimp_flush;
dcfd14b3 4587 /* nop */
0f8a249a
BS		 4588 break;
4589 case 0x3c: /* save */
6ae20372 4590 save_state(dc, cpu_cond);
063c3675 4591 gen_helper_save(cpu_env);
6ae20372 4592 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 4593 break;
4594 case 0x3d: /* restore */
6ae20372 4595 save_state(dc, cpu_cond);
063c3675 4596 gen_helper_restore(cpu_env);
6ae20372 4597 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 4598 break;
3475187d 4599#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4600 case 0x3e: /* V9 done/retry */
4601 {
4602 switch (rd) {
4603 case 0:
4604 if (!supervisor(dc))
4605 goto priv_insn;
4606 dc->npc = DYNAMIC_PC;
4607 dc->pc = DYNAMIC_PC;
063c3675 4608 gen_helper_done(cpu_env);
0f8a249a
BS		 4609 goto jmp_insn;
4610 case 1:
4611 if (!supervisor(dc))
4612 goto priv_insn;
4613 dc->npc = DYNAMIC_PC;
4614 dc->pc = DYNAMIC_PC;
063c3675 4615 gen_helper_retry(cpu_env);
0f8a249a
BS		 4616 goto jmp_insn;
4617 default:
4618 goto illegal_insn;
4619 }
4620 }
4621 break;
4622#endif
4623 default:
4624 goto illegal_insn;
4625 }
cf495bcf 4626 }
0f8a249a
BS		 4627 break;
4628 }
4629 break;
4630 case 3: /* load/store instructions */
4631 {
4632 unsigned int xop = GET_FIELD(insn, 7, 12);
9322a4bf 4633
cfa90513
BS		 4634 /* flush pending conditional evaluations before exposing
4635 cpu state */
4636 if (dc->cc_op != CC_OP_FLAGS) {
4637 dc->cc_op = CC_OP_FLAGS;
2ffd9176 4638 gen_helper_compute_psr(cpu_env);
cfa90513 4639 }
9322a4bf 4640 cpu_src1 = get_src1(insn, cpu_src1);
71817e48 4641 if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
81ad8ba2 4642 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 4643 gen_movl_reg_TN(rs2, cpu_src2);
71817e48
BS		 4644 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4645 } else if (IS_IMM) { /* immediate */
67526b20
BS		 4646 simm = GET_FIELDs(insn, 19, 31);
4647 tcg_gen_addi_tl(cpu_addr, cpu_src1, simm);
0f8a249a
BS		 4648 } else { /* register */
4649 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4650 if (rs2 != 0) {
6ae20372
BS		 4651 gen_movl_reg_TN(rs2, cpu_src2);
4652 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
6f551262
BS		 4653 } else
4654 tcg_gen_mov_tl(cpu_addr, cpu_src1);
0f8a249a 4655 }
2f2ecb83
BS		 4656 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4657 (xop > 0x17 && xop <= 0x1d ) ||
4658 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 4659 switch (xop) {
b89e94af 4660 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4661 gen_address_mask(dc, cpu_addr);
6ae20372 4662 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4663 break;
b89e94af 4664 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4665 gen_address_mask(dc, cpu_addr);
6ae20372 4666 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4667 break;
b89e94af 4668 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4669 gen_address_mask(dc, cpu_addr);
6ae20372 4670 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4671 break;
b89e94af 4672 case 0x3: /* ldd, load double word */
0f8a249a 4673 if (rd & 1)
d4218d99 4674 goto illegal_insn;
1a2fb1c0 4675 else {
a7812ae4 4676 TCGv_i32 r_const;
2ea815ca 4677
c2bc0e38 4678 save_state(dc, cpu_cond);
2ea815ca 4679 r_const = tcg_const_i32(7);
a7812ae4
PB		 4680 gen_helper_check_align(cpu_addr, r_const); // XXX remove
4681 tcg_temp_free_i32(r_const);
2cade6a3 4682 gen_address_mask(dc, cpu_addr);
6ae20372 4683 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
32b6c812
BS		 4684 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4685 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4686 gen_movl_TN_reg(rd + 1, cpu_tmp0);
8911f501 4687 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
6ae20372
BS		 4688 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4689 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
1a2fb1c0 4690 }
0f8a249a 4691 break;
b89e94af 4692 case 0x9: /* ldsb, load signed byte */
2cade6a3 4693 gen_address_mask(dc, cpu_addr);
6ae20372 4694 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4695 break;
b89e94af 4696 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4697 gen_address_mask(dc, cpu_addr);
6ae20372 4698 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4699 break;
4700 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4701 {
4702 TCGv r_const;
4703
2cade6a3 4704 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4705 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4706 r_const = tcg_const_tl(0xff);
4707 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4708 tcg_temp_free(r_const);
4709 }
0f8a249a 4710 break;
b89e94af 4711 case 0x0f: /* swap, swap register with memory. Also
77f193da 4712 atomically */
64a88d5d 4713 CHECK_IU_FEATURE(dc, SWAP);
6ae20372 4714 gen_movl_reg_TN(rd, cpu_val);
2cade6a3 4715 gen_address_mask(dc, cpu_addr);
527067d8 4716 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
6ae20372 4717 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
527067d8 4718 tcg_gen_mov_tl(cpu_val, cpu_tmp0);
0f8a249a 4719 break;
3475187d 4720#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4721 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4722#ifndef TARGET_SPARC64
0f8a249a
BS		 4723 if (IS_IMM)
4724 goto illegal_insn;
4725 if (!supervisor(dc))
4726 goto priv_insn;
6ea4a6c8 4727#endif
c2bc0e38 4728 save_state(dc, cpu_cond);
6ae20372 4729 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4730 break;
b89e94af 4731 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4732#ifndef TARGET_SPARC64
0f8a249a
BS		 4733 if (IS_IMM)
4734 goto illegal_insn;
4735 if (!supervisor(dc))
4736 goto priv_insn;
4737#endif
c2bc0e38 4738 save_state(dc, cpu_cond);
6ae20372 4739 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4740 break;
b89e94af 4741 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4742#ifndef TARGET_SPARC64
0f8a249a
BS		 4743 if (IS_IMM)
4744 goto illegal_insn;
4745 if (!supervisor(dc))
4746 goto priv_insn;
3475187d 4747#endif
c2bc0e38 4748 save_state(dc, cpu_cond);
6ae20372 4749 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4750 break;
b89e94af 4751 case 0x13: /* ldda, load double word alternate */
3475187d 4752#ifndef TARGET_SPARC64
0f8a249a
BS		 4753 if (IS_IMM)
4754 goto illegal_insn;
4755 if (!supervisor(dc))
4756 goto priv_insn;
3475187d 4757#endif
0f8a249a 4758 if (rd & 1)
d4218d99 4759 goto illegal_insn;
c2bc0e38 4760 save_state(dc, cpu_cond);
db166940
BS		 4761 gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4762 goto skip_move;
b89e94af 4763 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4764#ifndef TARGET_SPARC64
0f8a249a
BS		 4765 if (IS_IMM)
4766 goto illegal_insn;
4767 if (!supervisor(dc))
4768 goto priv_insn;
4769#endif
c2bc0e38 4770 save_state(dc, cpu_cond);
6ae20372 4771 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4772 break;
b89e94af 4773 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4774#ifndef TARGET_SPARC64
0f8a249a
BS		 4775 if (IS_IMM)
4776 goto illegal_insn;
4777 if (!supervisor(dc))
4778 goto priv_insn;
3475187d 4779#endif
c2bc0e38 4780 save_state(dc, cpu_cond);
6ae20372 4781 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4782 break;
4783 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4784#ifndef TARGET_SPARC64
0f8a249a
BS		 4785 if (IS_IMM)
4786 goto illegal_insn;
4787 if (!supervisor(dc))
4788 goto priv_insn;
4789#endif
c2bc0e38 4790 save_state(dc, cpu_cond);
6ae20372 4791 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4792 break;
b89e94af 4793 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4794 atomically */
64a88d5d 4795 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4796#ifndef TARGET_SPARC64
0f8a249a
BS		 4797 if (IS_IMM)
4798 goto illegal_insn;
4799 if (!supervisor(dc))
4800 goto priv_insn;
6ea4a6c8 4801#endif
c2bc0e38 4802 save_state(dc, cpu_cond);
6ae20372
BS		 4803 gen_movl_reg_TN(rd, cpu_val);
4804 gen_swap_asi(cpu_val, cpu_addr, insn);
0f8a249a 4805 break;
3475187d
FB		 4806
4807#ifndef TARGET_SPARC64
0f8a249a
BS		 4808 case 0x30: /* ldc */
4809 case 0x31: /* ldcsr */
4810 case 0x33: /* lddc */
4811 goto ncp_insn;
3475187d
FB		 4812#endif
4813#endif
4814#ifdef TARGET_SPARC64
0f8a249a 4815 case 0x08: /* V9 ldsw */
2cade6a3 4816 gen_address_mask(dc, cpu_addr);
6ae20372 4817 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4818 break;
4819 case 0x0b: /* V9 ldx */
2cade6a3 4820 gen_address_mask(dc, cpu_addr);
6ae20372 4821 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4822 break;
4823 case 0x18: /* V9 ldswa */
c2bc0e38 4824 save_state(dc, cpu_cond);
6ae20372 4825 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4826 break;
4827 case 0x1b: /* V9 ldxa */
c2bc0e38 4828 save_state(dc, cpu_cond);
6ae20372 4829 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4830 break;
4831 case 0x2d: /* V9 prefetch, no effect */
4832 goto skip_move;
4833 case 0x30: /* V9 ldfa */
8872eb4f
TS		 4834 if (gen_trap_ifnofpu(dc, cpu_cond)) {
4835 goto jmp_insn;
4836 }
c2bc0e38 4837 save_state(dc, cpu_cond);
6ae20372 4838 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4839 gen_update_fprs_dirty(rd);
81ad8ba2 4840 goto skip_move;
0f8a249a 4841 case 0x33: /* V9 lddfa */
8872eb4f
TS		 4842 if (gen_trap_ifnofpu(dc, cpu_cond)) {
4843 goto jmp_insn;
4844 }
c2bc0e38 4845 save_state(dc, cpu_cond);
6ae20372 4846 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4847 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4848 goto skip_move;
0f8a249a
BS		 4849 case 0x3d: /* V9 prefetcha, no effect */
4850 goto skip_move;
4851 case 0x32: /* V9 ldqfa */
64a88d5d 4852 CHECK_FPU_FEATURE(dc, FLOAT128);
8872eb4f
TS		 4853 if (gen_trap_ifnofpu(dc, cpu_cond)) {
4854 goto jmp_insn;
4855 }
c2bc0e38 4856 save_state(dc, cpu_cond);
6ae20372 4857 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4858 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4859 goto skip_move;
0f8a249a
BS		 4860#endif
4861 default:
4862 goto illegal_insn;
4863 }
6ae20372 4864 gen_movl_TN_reg(rd, cpu_val);
db166940 4865#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4866 skip_move: ;
3475187d 4867#endif
0f8a249a 4868 } else if (xop >= 0x20 && xop < 0x24) {
6ae20372 4869 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4870 goto jmp_insn;
c2bc0e38 4871 save_state(dc, cpu_cond);
0f8a249a 4872 switch (xop) {
b89e94af 4873 case 0x20: /* ldf, load fpreg */
2cade6a3 4874 gen_address_mask(dc, cpu_addr);
527067d8 4875 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
208ae657
RH		 4876 cpu_dst_32 = gen_dest_fpr_F();
4877 tcg_gen_trunc_tl_i32(cpu_dst_32, cpu_tmp0);
4878 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4879 break;
3a3b925d
BS		 4880 case 0x21: /* ldfsr, V9 ldxfsr */
4881#ifdef TARGET_SPARC64
2cade6a3 4882 gen_address_mask(dc, cpu_addr);
3a3b925d
BS		 4883 if (rd == 1) {
4884 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
2e2f4ade 4885 gen_helper_ldxfsr(cpu_env, cpu_tmp64);
fe987e23
IK		 4886 } else {
4887 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4888 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
2e2f4ade 4889 gen_helper_ldfsr(cpu_env, cpu_tmp32);
fe987e23 4890 }
3a3b925d
BS		 4891#else
4892 {
4893 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
2e2f4ade 4894 gen_helper_ldfsr(cpu_env, cpu_tmp32);
3a3b925d
BS		 4895 }
4896#endif
0f8a249a 4897 break;
b89e94af 4898 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4899 {
a7812ae4 4900 TCGv_i32 r_const;
2ea815ca
BS		 4901
4902 CHECK_FPU_FEATURE(dc, FLOAT128);
4903 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4904 gen_address_mask(dc, cpu_addr);
a7812ae4
PB		 4905 gen_helper_ldqf(cpu_addr, r_const);
4906 tcg_temp_free_i32(r_const);
2ea815ca 4907 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4908 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4909 }
1f587329 4910 break;
b89e94af 4911 case 0x23: /* lddf, load double fpreg */
03fb8cfc
RH		 4912 gen_address_mask(dc, cpu_addr);
4913 cpu_dst_64 = gen_dest_fpr_D();
4914 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4915 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4916 break;
4917 default:
4918 goto illegal_insn;
4919 }
dc1a6971 4920 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4921 xop == 0xe || xop == 0x1e) {
6ae20372 4922 gen_movl_reg_TN(rd, cpu_val);
0f8a249a 4923 switch (xop) {
b89e94af 4924 case 0x4: /* st, store word */
2cade6a3 4925 gen_address_mask(dc, cpu_addr);
6ae20372 4926 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4927 break;
b89e94af 4928 case 0x5: /* stb, store byte */
2cade6a3 4929 gen_address_mask(dc, cpu_addr);
6ae20372 4930 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4931 break;
b89e94af 4932 case 0x6: /* sth, store halfword */
2cade6a3 4933 gen_address_mask(dc, cpu_addr);
6ae20372 4934 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4935 break;
b89e94af 4936 case 0x7: /* std, store double word */
0f8a249a 4937 if (rd & 1)
d4218d99 4938 goto illegal_insn;
1a2fb1c0 4939 else {
a7812ae4 4940 TCGv_i32 r_const;
1a2fb1c0 4941
c2bc0e38 4942 save_state(dc, cpu_cond);
2cade6a3 4943 gen_address_mask(dc, cpu_addr);
2ea815ca 4944 r_const = tcg_const_i32(7);
a7812ae4
PB		 4945 gen_helper_check_align(cpu_addr, r_const); // XXX remove
4946 tcg_temp_free_i32(r_const);
a7ec4229 4947 gen_movl_reg_TN(rd + 1, cpu_tmp0);
ab508019 4948 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
6ae20372 4949 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
7fa76c0b 4950 }
0f8a249a 4951 break;
3475187d 4952#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4953 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4954#ifndef TARGET_SPARC64
0f8a249a
BS		 4955 if (IS_IMM)
4956 goto illegal_insn;
4957 if (!supervisor(dc))
4958 goto priv_insn;
6ea4a6c8 4959#endif
c2bc0e38 4960 save_state(dc, cpu_cond);
6ae20372 4961 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4962 dc->npc = DYNAMIC_PC;
d39c0b99 4963 break;
b89e94af 4964 case 0x15: /* stba, store byte alternate */
3475187d 4965#ifndef TARGET_SPARC64
0f8a249a
BS		 4966 if (IS_IMM)
4967 goto illegal_insn;
4968 if (!supervisor(dc))
4969 goto priv_insn;
3475187d 4970#endif
c2bc0e38 4971 save_state(dc, cpu_cond);
6ae20372 4972 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4973 dc->npc = DYNAMIC_PC;
d39c0b99 4974 break;
b89e94af 4975 case 0x16: /* stha, store halfword alternate */
3475187d 4976#ifndef TARGET_SPARC64
0f8a249a
BS		 4977 if (IS_IMM)
4978 goto illegal_insn;
4979 if (!supervisor(dc))
4980 goto priv_insn;
6ea4a6c8 4981#endif
c2bc0e38 4982 save_state(dc, cpu_cond);
6ae20372 4983 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4984 dc->npc = DYNAMIC_PC;
d39c0b99 4985 break;
b89e94af 4986 case 0x17: /* stda, store double word alternate */
3475187d 4987#ifndef TARGET_SPARC64
0f8a249a
BS		 4988 if (IS_IMM)
4989 goto illegal_insn;
4990 if (!supervisor(dc))
4991 goto priv_insn;
3475187d 4992#endif
0f8a249a 4993 if (rd & 1)
d4218d99 4994 goto illegal_insn;
1a2fb1c0 4995 else {
c2bc0e38 4996 save_state(dc, cpu_cond);
6ae20372 4997 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4998 }
d39c0b99 4999 break;
e80cfcfc 5000#endif
3475187d 5001#ifdef TARGET_SPARC64
0f8a249a 5002 case 0x0e: /* V9 stx */
2cade6a3 5003 gen_address_mask(dc, cpu_addr);
6ae20372 5004 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5005 break;
5006 case 0x1e: /* V9 stxa */
c2bc0e38 5007 save_state(dc, cpu_cond);
6ae20372 5008 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 5009 dc->npc = DYNAMIC_PC;
0f8a249a 5010 break;
3475187d 5011#endif
0f8a249a
BS		 5012 default:
5013 goto illegal_insn;
5014 }
5015 } else if (xop > 0x23 && xop < 0x28) {
6ae20372 5016 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 5017 goto jmp_insn;
c2bc0e38 5018 save_state(dc, cpu_cond);
0f8a249a 5019 switch (xop) {
b89e94af 5020 case 0x24: /* stf, store fpreg */
2cade6a3 5021 gen_address_mask(dc, cpu_addr);
208ae657
RH		 5022 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5023 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_src1_32);
527067d8 5024 tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5025 break;
5026 case 0x25: /* stfsr, V9 stxfsr */
3a3b925d 5027#ifdef TARGET_SPARC64
2cade6a3 5028 gen_address_mask(dc, cpu_addr);
3a3b925d
BS		 5029 tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
5030 if (rd == 1)
5031 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
527067d8
BS		 5032 else
5033 tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
3a3b925d
BS		 5034#else
5035 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
6ae20372 5036 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
3a3b925d 5037#endif
0f8a249a 5038 break;
1f587329
BS		 5039 case 0x26:
5040#ifdef TARGET_SPARC64
1f587329 5041 /* V9 stqf, store quad fpreg */
2ea815ca 5042 {
a7812ae4 5043 TCGv_i32 r_const;
2ea815ca
BS		 5044
5045 CHECK_FPU_FEATURE(dc, FLOAT128);
5046 gen_op_load_fpr_QT0(QFPREG(rd));
5047 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5048 gen_address_mask(dc, cpu_addr);
a7812ae4
PB		 5049 gen_helper_stqf(cpu_addr, r_const);
5050 tcg_temp_free_i32(r_const);
2ea815ca 5051 }
1f587329 5052 break;
1f587329
BS		 5053#else /* !TARGET_SPARC64 */
5054 /* stdfq, store floating point queue */
5055#if defined(CONFIG_USER_ONLY)
5056 goto illegal_insn;
5057#else
0f8a249a
BS		 5058 if (!supervisor(dc))
5059 goto priv_insn;
6ae20372 5060 if (gen_trap_ifnofpu(dc, cpu_cond))
0f8a249a
BS		 5061 goto jmp_insn;
5062 goto nfq_insn;
1f587329 5063#endif
0f8a249a 5064#endif
b89e94af 5065 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5066 gen_address_mask(dc, cpu_addr);
5067 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5068 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5069 break;
5070 default:
5071 goto illegal_insn;
5072 }
5073 } else if (xop > 0x33 && xop < 0x3f) {
c2bc0e38 5074 save_state(dc, cpu_cond);
0f8a249a 5075 switch (xop) {
a4d17f19 5076#ifdef TARGET_SPARC64
0f8a249a 5077 case 0x34: /* V9 stfa */
5f06b547
TS		 5078 if (gen_trap_ifnofpu(dc, cpu_cond)) {
5079 goto jmp_insn;
5080 }
6ae20372 5081 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5082 break;
1f587329 5083 case 0x36: /* V9 stqfa */
2ea815ca 5084 {
a7812ae4 5085 TCGv_i32 r_const;
2ea815ca
BS		 5086
5087 CHECK_FPU_FEATURE(dc, FLOAT128);
5f06b547
TS		 5088 if (gen_trap_ifnofpu(dc, cpu_cond)) {
5089 goto jmp_insn;
5090 }
2ea815ca 5091 r_const = tcg_const_i32(7);
a7812ae4
PB		 5092 gen_helper_check_align(cpu_addr, r_const);
5093 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5094 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5095 }
1f587329 5096 break;
0f8a249a 5097 case 0x37: /* V9 stdfa */
5f06b547
TS		 5098 if (gen_trap_ifnofpu(dc, cpu_cond)) {
5099 goto jmp_insn;
5100 }
6ae20372 5101 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a
BS		 5102 break;
5103 case 0x3c: /* V9 casa */
71817e48 5104 gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
6ae20372 5105 gen_movl_TN_reg(rd, cpu_val);
0f8a249a
BS		 5106 break;
5107 case 0x3e: /* V9 casxa */
71817e48 5108 gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
6ae20372 5109 gen_movl_TN_reg(rd, cpu_val);
0f8a249a 5110 break;
a4d17f19 5111#else
0f8a249a
BS		 5112 case 0x34: /* stc */
5113 case 0x35: /* stcsr */
5114 case 0x36: /* stdcq */
5115 case 0x37: /* stdc */
5116 goto ncp_insn;
5117#endif
5118 default:
5119 goto illegal_insn;
5120 }
dc1a6971 5121 } else
0f8a249a
BS		 5122 goto illegal_insn;
5123 }
5124 break;
cf495bcf
FB		 5125 }
5126 /* default case for non jump instructions */
72cbca10 5127 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5128 dc->pc = DYNAMIC_PC;
5129 gen_op_next_insn();
72cbca10
FB		 5130 } else if (dc->npc == JUMP_PC) {
5131 /* we can do a static jump */
6ae20372 5132 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5133 dc->is_br = 1;
5134 } else {
0f8a249a
BS		 5135 dc->pc = dc->npc;
5136 dc->npc = dc->npc + 4;
cf495bcf 5137 }
e80cfcfc 5138 jmp_insn:
42a8aa83 5139 goto egress;
cf495bcf 5140 illegal_insn:
2ea815ca 5141 {
a7812ae4 5142 TCGv_i32 r_const;
2ea815ca
BS		 5143
5144 save_state(dc, cpu_cond);
5145 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5146 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5147 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5148 dc->is_br = 1;
5149 }
42a8aa83 5150 goto egress;
64a88d5d 5151 unimp_flush:
2ea815ca 5152 {
a7812ae4 5153 TCGv_i32 r_const;
2ea815ca
BS		 5154
5155 save_state(dc, cpu_cond);
5156 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5157 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5158 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5159 dc->is_br = 1;
5160 }
42a8aa83 5161 goto egress;
e80cfcfc 5162#if !defined(CONFIG_USER_ONLY)
e8af50a3 5163 priv_insn:
2ea815ca 5164 {
a7812ae4 5165 TCGv_i32 r_const;
2ea815ca
BS		 5166
5167 save_state(dc, cpu_cond);
5168 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5169 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5170 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5171 dc->is_br = 1;
5172 }
42a8aa83 5173 goto egress;
64a88d5d 5174#endif
e80cfcfc 5175 nfpu_insn:
6ae20372 5176 save_state(dc, cpu_cond);
e80cfcfc
FB		 5177 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5178 dc->is_br = 1;
42a8aa83 5179 goto egress;
64a88d5d 5180#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5181 nfq_insn:
6ae20372 5182 save_state(dc, cpu_cond);
9143e598
BS		 5183 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5184 dc->is_br = 1;
42a8aa83 5185 goto egress;
9143e598 5186#endif
fcc72045
BS		 5187#ifndef TARGET_SPARC64
5188 ncp_insn:
2ea815ca
BS		 5189 {
5190 TCGv r_const;
5191
5192 save_state(dc, cpu_cond);
5193 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5194 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5195 tcg_temp_free(r_const);
5196 dc->is_br = 1;
5197 }
42a8aa83 5198 goto egress;
fcc72045 5199#endif
42a8aa83
RH		 5200 egress:
5201 tcg_temp_free(cpu_tmp1);
5202 tcg_temp_free(cpu_tmp2);
30038fd8
RH		 5203 if (dc->n_t32 != 0) {
5204 int i;
5205 for (i = dc->n_t32 - 1; i >= 0; --i) {
5206 tcg_temp_free_i32(dc->t32[i]);
5207 }
5208 dc->n_t32 = 0;
5209 }
7a3f1944
FB		 5210}
5211
2cfc5f17
TS		 5212static inline void gen_intermediate_code_internal(TranslationBlock * tb,
5213 int spc, CPUSPARCState *env)
7a3f1944 5214{
72cbca10 5215 target_ulong pc_start, last_pc;
cf495bcf
FB		 5216 uint16_t *gen_opc_end;
5217 DisasContext dc1, *dc = &dc1;
a1d1bb31 5218 CPUBreakpoint *bp;
e8af50a3 5219 int j, lj = -1;
2e70f6ef
PB		 5220 int num_insns;
5221 int max_insns;
cf495bcf
FB		 5222
5223 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5224 dc->tb = tb;
72cbca10 5225 pc_start = tb->pc;
cf495bcf 5226 dc->pc = pc_start;
e80cfcfc 5227 last_pc = dc->pc;
72cbca10 5228 dc->npc = (target_ulong) tb->cs_base;
8393617c 5229 dc->cc_op = CC_OP_DYNAMIC;
6f27aba6 5230 dc->mem_idx = cpu_mmu_index(env);
5578ceab 5231 dc->def = env->def;
f838e2c5
BS		 5232 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5233 dc->address_mask_32bit = tb_am_enabled(tb->flags);
060718c1 5234 dc->singlestep = (env->singlestep_enabled || singlestep);
cf495bcf 5235 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 5236
a7812ae4
PB		 5237 cpu_tmp0 = tcg_temp_new();
5238 cpu_tmp32 = tcg_temp_new_i32();
5239 cpu_tmp64 = tcg_temp_new_i64();
d987963a 5240
a7812ae4 5241 cpu_dst = tcg_temp_local_new();
d987963a
BS		 5242
5243 // loads and stores
a7812ae4
PB		 5244 cpu_val = tcg_temp_local_new();
5245 cpu_addr = tcg_temp_local_new();
1a2fb1c0 5246
2e70f6ef
PB		 5247 num_insns = 0;
5248 max_insns = tb->cflags & CF_COUNT_MASK;
5249 if (max_insns == 0)
5250 max_insns = CF_COUNT_MASK;
5251 gen_icount_start();
cf495bcf 5252 do {
72cf2d4f
BS		 5253 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
5254 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 5255 if (bp->pc == dc->pc) {
0f8a249a 5256 if (dc->pc != pc_start)
6ae20372 5257 save_state(dc, cpu_cond);
bc265319 5258 gen_helper_debug(cpu_env);
57fec1fe 5259 tcg_gen_exit_tb(0);
0f8a249a 5260 dc->is_br = 1;
e80cfcfc 5261 goto exit_gen_loop;
e8af50a3
FB		 5262 }
5263 }
5264 }
5265 if (spc) {
93fcfe39 5266 qemu_log("Search PC...\n");
e8af50a3
FB		 5267 j = gen_opc_ptr - gen_opc_buf;
5268 if (lj < j) {
5269 lj++;
5270 while (lj < j)
5271 gen_opc_instr_start[lj++] = 0;
5272 gen_opc_pc[lj] = dc->pc;
5273 gen_opc_npc[lj] = dc->npc;
5274 gen_opc_instr_start[lj] = 1;
2e70f6ef 5275 gen_opc_icount[lj] = num_insns;
e8af50a3
FB		 5276 }
5277 }
2e70f6ef
PB		 5278 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
5279 gen_io_start();
0f8a249a
BS		 5280 last_pc = dc->pc;
5281 disas_sparc_insn(dc);
2e70f6ef 5282 num_insns++;
0f8a249a
BS		 5283
5284 if (dc->is_br)
5285 break;
5286 /* if the next PC is different, we abort now */
5287 if (dc->pc != (last_pc + 4))
5288 break;
d39c0b99
FB		 5289 /* if we reach a page boundary, we stop generation so that the
5290 PC of a TT_TFAULT exception is always in the right page */
5291 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5292 break;
e80cfcfc
FB		 5293 /* if single step mode, we generate only one instruction and
5294 generate an exception */
060718c1 5295 if (dc->singlestep) {
e80cfcfc
FB		 5296 break;
5297 }
cf495bcf 5298 } while ((gen_opc_ptr < gen_opc_end) &&
2e70f6ef
PB		 5299 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5300 num_insns < max_insns);
e80cfcfc
FB		 5301
5302 exit_gen_loop:
d987963a 5303 tcg_temp_free(cpu_addr);
3f0436fe 5304 tcg_temp_free(cpu_val);
d987963a 5305 tcg_temp_free(cpu_dst);
a7812ae4
PB		 5306 tcg_temp_free_i64(cpu_tmp64);
5307 tcg_temp_free_i32(cpu_tmp32);
2ea815ca 5308 tcg_temp_free(cpu_tmp0);
96eda024 5309
2e70f6ef
PB		 5310 if (tb->cflags & CF_LAST_IO)
5311 gen_io_end();
72cbca10 5312 if (!dc->is_br) {
5fafdf24 5313 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5314 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5315 /* static PC and NPC: we can use direct chaining */
2f5680ee 5316 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10
FB		 5317 } else {
5318 if (dc->pc != DYNAMIC_PC)
2f5680ee 5319 tcg_gen_movi_tl(cpu_pc, dc->pc);
6ae20372 5320 save_npc(dc, cpu_cond);
57fec1fe 5321 tcg_gen_exit_tb(0);
72cbca10
FB		 5322 }
5323 }
2e70f6ef 5324 gen_icount_end(tb, num_insns);
cf495bcf 5325 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 5326 if (spc) {
5327 j = gen_opc_ptr - gen_opc_buf;
5328 lj++;
5329 while (lj <= j)
5330 gen_opc_instr_start[lj++] = 0;
e8af50a3 5331#if 0
93fcfe39 5332 log_page_dump();
e8af50a3 5333#endif
c3278b7b
FB		 5334 gen_opc_jump_pc[0] = dc->jump_pc[0];
5335 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 5336 } else {
e80cfcfc 5337 tb->size = last_pc + 4 - pc_start;
2e70f6ef 5338 tb->icount = num_insns;
e8af50a3 5339 }
7a3f1944 5340#ifdef DEBUG_DISAS
8fec2b8c 5341 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5342 qemu_log("--------------\n");
5343 qemu_log("IN: %s\n", lookup_symbol(pc_start));
5344 log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
5345 qemu_log("\n");
cf495bcf 5346 }
7a3f1944 5347#endif
7a3f1944
FB		 5348}
5349
2cfc5f17 5350void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5351{
2cfc5f17 5352 gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 5353}
5354
2cfc5f17 5355void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5356{
2cfc5f17 5357 gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 5358}
5359
c48fcb47 5360void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5361{
f5069b26 5362 unsigned int i;
c48fcb47 5363 static int inited;
f5069b26
BS		 5364 static const char * const gregnames[8] = {
5365 NULL, // g0 not used
5366 "g1",
5367 "g2",
5368 "g3",
5369 "g4",
5370 "g5",
5371 "g6",
5372 "g7",
5373 };
30038fd8
RH		 5374 static const char * const fregnames[32] = {
5375 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5376 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5377 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5378 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5379 };
aaed909a 5380
1a2fb1c0
BS		 5381 /* init various static tables */
5382 if (!inited) {
5383 inited = 1;
5384
a7812ae4
PB		 5385 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5386 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
5387 offsetof(CPUState, regwptr),
5388 "regwptr");
1a2fb1c0 5389#ifdef TARGET_SPARC64
a7812ae4
PB		 5390 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc),
5391 "xcc");
5392 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi),
5393 "asi");
5394 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs),
5395 "fprs");
5396 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr),
255e1fcb 5397 "gsr");
a7812ae4 5398 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
255e1fcb
BS		 5399 offsetof(CPUState, tick_cmpr),
5400 "tick_cmpr");
a7812ae4 5401 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
255e1fcb
BS		 5402 offsetof(CPUState, stick_cmpr),
5403 "stick_cmpr");
a7812ae4 5404 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
255e1fcb
BS		 5405 offsetof(CPUState, hstick_cmpr),
5406 "hstick_cmpr");
a7812ae4 5407 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp),
255e1fcb 5408 "hintp");
a7812ae4
PB		 5409 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba),
5410 "htba");
5411 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver),
5412 "hver");
5413 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
255e1fcb 5414 offsetof(CPUState, ssr), "ssr");
a7812ae4 5415 cpu_ver = tcg_global_mem_new(TCG_AREG0,
255e1fcb 5416 offsetof(CPUState, version), "ver");
a7812ae4
PB		 5417 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
5418 offsetof(CPUState, softint),
5419 "softint");
255e1fcb 5420#else
a7812ae4 5421 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim),
255e1fcb 5422 "wim");
1a2fb1c0 5423#endif
a7812ae4 5424 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond),
77f193da 5425 "cond");
a7812ae4 5426 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
dc99a3f2 5427 "cc_src");
a7812ae4 5428 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
d9bdab86
BS		 5429 offsetof(CPUState, cc_src2),
5430 "cc_src2");
a7812ae4 5431 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
dc99a3f2 5432 "cc_dst");
8393617c
BS		 5433 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
5434 "cc_op");
a7812ae4
PB		 5435 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
5436 "psr");
5437 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),
87e92502 5438 "fsr");
a7812ae4 5439 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc),
48d5c82b 5440 "pc");
a7812ae4
PB		 5441 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc),
5442 "npc");
5443 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
255e1fcb 5444#ifndef CONFIG_USER_ONLY
a7812ae4 5445 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr),
255e1fcb
BS		 5446 "tbr");
5447#endif
30038fd8 5448 for (i = 1; i < 8; i++) {
a7812ae4 5449 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
f5069b26
BS		 5450 offsetof(CPUState, gregs[i]),
5451 gregnames[i]);
30038fd8
RH		 5452 }
5453 for (i = 0; i < TARGET_DPREGS; i++) {
5454 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
45c7b743
RH		 5455 offsetof(CPUState, fpr[i]),
5456 fregnames[i]);
30038fd8 5457 }
714547bb 5458
c9e03d8f
BS		 5459 /* register helpers */
5460
a7812ae4 5461#define GEN_HELPER 2
c9e03d8f 5462#include "helper.h"
1a2fb1c0 5463 }
658138bc 5464}
d2856f1a 5465
e87b7cb0 5466void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
d2856f1a
AJ		 5467{
5468 target_ulong npc;
5469 env->pc = gen_opc_pc[pc_pos];
5470 npc = gen_opc_npc[pc_pos];
5471 if (npc == 1) {
5472 /* dynamic NPC: already stored */
5473 } else if (npc == 2) {
d7da2a10
BS		 5474 /* jump PC: use 'cond' and the jump targets of the translation */
5475 if (env->cond) {
d2856f1a 5476 env->npc = gen_opc_jump_pc[0];
d7da2a10 5477 } else {
d2856f1a 5478 env->npc = gen_opc_jump_pc[1];
d7da2a10 5479 }
d2856f1a
AJ		 5480 } else {
5481 env->npc = npc;
5482 }
14ed7adc
IK		 5483
5484 /* flush pending conditional evaluations before exposing cpu state */
5485 if (CC_OP != CC_OP_FLAGS) {
2ffd9176 5486 helper_compute_psr(env);
14ed7adc 5487 }
d2856f1a 5488}
Mirror of https://git.qemu.org/git/qemu.git