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sim: overhaul & unify endian settings management
[thirdparty/binutils-gdb.git] / sim / ft32 / interp.c
CommitLineData
f46e4eb7
JB		 1/* Simulator for the FT32 processor
2
3666a048 3 Copyright (C) 2008-2021 Free Software Foundation, Inc.
f46e4eb7
JB		 4 Contributed by FTDI <support@ftdichip.com>
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
6df01ab8
MF		 21/* This must come before any other includes. */
22#include "defs.h"
23
f46e4eb7
JB		 24#include <fcntl.h>
25#include <signal.h>
26#include <stdlib.h>
27#include <stdint.h>
28
29#include "bfd.h"
df68e12b 30#include "sim/callback.h"
f46e4eb7 31#include "libiberty.h"
df68e12b 32#include "sim/sim.h"
f46e4eb7
JB		 33
34#include "sim-main.h"
35#include "sim-options.h"
36
37#include "opcode/ft32.h"
38
39/*
40 * FT32 is a Harvard architecture: RAM and code occupy
41 * different address spaces.
42 *
43 * sim and gdb model FT32 memory by adding 0x800000 to RAM
44 * addresses. This means that sim/gdb can treat all addresses
45 * similarly.
46 *
47 * The address space looks like:
48 *
49 * 00000 start of code memory
50 * 3ffff end of code memory
51 * 800000 start of RAM
52 * 80ffff end of RAM
53 */
54
55#define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
56
57static unsigned long
58ft32_extract_unsigned_integer (unsigned char *addr, int len)
59{
60 unsigned long retval;
61 unsigned char *p;
62 unsigned char *startaddr = (unsigned char *) addr;
63 unsigned char *endaddr = startaddr + len;
64
65 /* Start at the most significant end of the integer, and work towards
66 the least significant. */
67 retval = 0;
68
69 for (p = endaddr; p > startaddr;)
70 retval = (retval << 8) | * -- p;
71
72 return retval;
73}
74
75static void
76ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
77{
78 unsigned char *p;
79 unsigned char *startaddr = (unsigned char *)addr;
80 unsigned char *endaddr = startaddr + len;
81
82 for (p = startaddr; p < endaddr; p++)
83 {
84 *p = val & 0xff;
85 val >>= 8;
86 }
87}
88
89/*
90 * Align EA according to its size DW.
91 * The FT32 ignores the low bit of a 16-bit addresss,
92 * and the low two bits of a 32-bit address.
93 */
94static uint32_t ft32_align (uint32_t dw, uint32_t ea)
95{
96 switch (dw)
97 {
98 case 1:
99 ea &= ~1;
100 break;
101 case 2:
102 ea &= ~3;
103 break;
104 default:
105 break;
106 }
107 return ea;
108}
109
110/* Read an item from memory address EA, sized DW. */
111static uint32_t
112ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
113{
114 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 115 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 116 uint8_t byte[4];
117 uint32_t r;
118
119 ea = ft32_align (dw, ea);
120
121 switch (dw) {
122 case 0:
123 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
124 case 1:
125 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
126 case 2:
127 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
128 default:
129 abort ();
130 }
131}
132
133/* Write item V to memory address EA, sized DW. */
134static void
135ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
136{
137 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 138 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 139 uint8_t byte[4];
140
141 ea = ft32_align (dw, ea);
142
143 switch (dw) {
144 case 0:
145 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
146 break;
147 case 1:
148 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
149 break;
150 case 2:
151 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
152 break;
153 default:
154 abort ();
155 }
156}
157
158#define ILLEGAL() \
159 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
160
161static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
162{
163 sim_cpu *cpu = STATE_CPU (sd, 0);
164 uint32_t insnpc = cpu->state.pc;
165 uint32_t r;
166 uint8_t byte[4];
167
168 ea &= 0x1ffff;
169 if (ea & ~0xffff)
170 {
171 /* Simulate some IO devices */
172 switch (ea)
173 {
bcd68f9e
JB		 174 case 0x10000:
175 return getchar ();
f46e4eb7
JB		 176 case 0x1fff4:
177 /* Read the simulator cycle timer. */
178 return cpu->state.cycles / 100;
179 default:
180 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
181 ea, insnpc);
182 ILLEGAL ();
183 }
184 }
185 return ft32_read_item (sd, dw, RAM_BIAS + ea);
186}
187
188static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
189{
190 sim_cpu *cpu = STATE_CPU (sd, 0);
191 ea &= 0x1ffff;
192 if (ea & 0x10000)
193 {
194 /* Simulate some IO devices */
195 switch (ea)
196 {
197 case 0x10000:
198 /* Console output */
199 putchar (d & 0xff);
200 break;
201 case 0x1fc80:
202 /* Unlock the PM write port */
203 cpu->state.pm_unlock = (d == 0x1337f7d1);
204 break;
205 case 0x1fc84:
206 /* Set the PM write address register */
207 cpu->state.pm_addr = d;
208 break;
209 case 0x1fc88:
71c34ca7
JB		 210 if (cpu->state.pm_unlock)
211 {
212 /* Write to PM. */
213 ft32_write_item (sd, dw, cpu->state.pm_addr, d);
214 cpu->state.pm_addr += 4;
215 }
f46e4eb7
JB		 216 break;
217 case 0x1fffc:
218 /* Normal exit. */
219 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]);
220 break;
221 case 0x1fff8:
222 sim_io_printf (sd, "Debug write %08x\n", d);
223 break;
224 default:
225 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
226 }
227 }
228 else
229 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
230}
231
232#define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
233#define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
234
235/* LSBS (n) is a mask of the least significant N bits. */
236#define LSBS(n) ((1U << (n)) - 1)
237
238static void ft32_push (SIM_DESC sd, uint32_t v)
239{
240 sim_cpu *cpu = STATE_CPU (sd, 0);
241 cpu->state.regs[FT32_HARD_SP] -= 4;
242 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
243 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v);
244}
245
246static uint32_t ft32_pop (SIM_DESC sd)
247{
248 sim_cpu *cpu = STATE_CPU (sd, 0);
249 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]);
250 cpu->state.regs[FT32_HARD_SP] += 4;
251 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
252 return r;
253}
254
255/* Extract the low SIZ bits of N as an unsigned number. */
256static int nunsigned (int siz, int n)
257{
258 return n & LSBS (siz);
259}
260
261/* Extract the low SIZ bits of N as a signed number. */
262static int nsigned (int siz, int n)
263{
264 int shift = (sizeof (int) * 8) - siz;
265 return (n << shift) >> shift;
266}
267
268/* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
269static uint32_t ft32sdiv (uint32_t n, uint32_t d)
270{
271 if (n == 0x80000000UL && d == 0xffffffffUL)
272 return 0x80000000UL;
273 else
274 return (uint32_t)((int)n / (int)d);
275}
276
277/* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
278static uint32_t ft32smod (uint32_t n, uint32_t d)
279{
280 if (n == 0x80000000UL && d == 0xffffffffUL)
281 return 0;
282 else
283 return (uint32_t)((int)n % (int)d);
284}
285
286/* Circular rotate right N by B bits. */
287static uint32_t ror (uint32_t n, uint32_t b)
288{
289 b &= 31;
290 return (n >> b) | (n << (32 - b));
291}
292
293/* Implement the BINS machine instruction.
294 See FT32 Programmer's Reference for details. */
295static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
296{
297 uint32_t bitmask = LSBS (len) << pos;
298 return (d & ~bitmask) | ((f << pos) & bitmask);
299}
300
301/* Implement the FLIP machine instruction.
302 See FT32 Programmer's Reference for details. */
303static uint32_t flip (uint32_t x, uint32_t b)
304{
305 if (b & 1)
306 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
307 if (b & 2)
308 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
309 if (b & 4)
310 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
311 if (b & 8)
312 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
313 if (b & 16)
314 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
315 return x;
316}
317
318static void
319step_once (SIM_DESC sd)
320{
321 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 322 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 323 uint32_t inst;
324 uint32_t dw;
325 uint32_t cb;
326 uint32_t r_d;
327 uint32_t cr;
328 uint32_t cv;
329 uint32_t bt;
330 uint32_t r_1;
331 uint32_t rimm;
332 uint32_t r_2;
333 uint32_t k20;
334 uint32_t pa;
335 uint32_t aa;
336 uint32_t k16;
3b4b0a62 337 uint32_t k15;
f46e4eb7
JB		 338 uint32_t al;
339 uint32_t r_1v;
340 uint32_t rimmv;
341 uint32_t bit_pos;
342 uint32_t bit_len;
343 uint32_t upper;
344 uint32_t insnpc;
dcc31d28
JB		 345 unsigned int sc[2];
346 int isize;
f46e4eb7 347
f46e4eb7
JB		 348 inst = ft32_read_item (sd, 2, cpu->state.pc);
349 cpu->state.cycles += 1;
350
dcc31d28
JB		 351 if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
352 && ft32_decode_shortcode (cpu->state.pc, inst, sc))
353 {
354 if ((cpu->state.pc & 3) == 0)
355 inst = sc[0];
356 else
357 inst = sc[1];
358 isize = 2;
359 }
360 else
361 isize = 4;
362
f46e4eb7
JB		 363 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
364 if (inst == 0x00340002)
365 {
366 sim_engine_halt (sd, cpu, NULL,
367 cpu->state.pc,
368 sim_stopped, SIM_SIGTRAP);
369 goto escape;
370 }
371
372 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
373 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
374 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
375 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
376 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
377 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
378 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
379 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
380 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
381 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
382 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
383 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
384 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
3b4b0a62
JB		 385 k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ);
386 if (k15 & 0x80)
387 k15 ^= 0x7f00;
388 if (k15 & 0x4000)
389 k15 -= 0x8000;
f46e4eb7
JB		 390 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
391
392 r_1v = cpu->state.regs[r_1];
393 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f];
394
395 bit_pos = rimmv & 31;
396 bit_len = 0xf & (rimmv >> 5);
397 if (bit_len == 0)
398 bit_len = 16;
399
400 upper = (inst >> 27);
401
402 insnpc = cpu->state.pc;
dcc31d28 403 cpu->state.pc += isize;
f46e4eb7
JB		 404 switch (upper)
405 {
406 case FT32_PAT_TOC:
407 case FT32_PAT_TOCI:
408 {
409 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv);
410 if (take)
411 {
412 cpu->state.cycles += 1;
413 if (bt)
414 ft32_push (sd, cpu->state.pc); /* this is a call. */
415 if (upper == FT32_PAT_TOC)
416 cpu->state.pc = pa << 2;
417 else
418 cpu->state.pc = cpu->state.regs[r_2];
419 if (cpu->state.pc == 0x8)
420 goto escape;
421 }
422 }
423 break;
424
425 case FT32_PAT_ALUOP:
426 case FT32_PAT_CMPOP:
427 {
428 uint32_t result;
429 switch (al)
430 {
431 case 0x0: result = r_1v + rimmv; break;
432 case 0x1: result = ror (r_1v, rimmv); break;
433 case 0x2: result = r_1v - rimmv; break;
434 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
435 case 0x4: result = r_1v & rimmv; break;
436 case 0x5: result = r_1v | rimmv; break;
437 case 0x6: result = r_1v ^ rimmv; break;
438 case 0x7: result = ~(r_1v ^ rimmv); break;
439 case 0x8: result = r_1v << rimmv; break;
440 case 0x9: result = r_1v >> rimmv; break;
441 case 0xa: result = (int32_t)r_1v >> rimmv; break;
442 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
443 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
444 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
445 case 0xe: result = flip (r_1v, rimmv); break;
446 default:
447 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
448 ILLEGAL ();
449 }
450 if (upper == FT32_PAT_ALUOP)
451 cpu->state.regs[r_d] = result;
452 else
453 {
454 uint32_t dwmask = 0;
455 int dwsiz = 0;
456 int zero;
457 int sign;
458 int ahi;
459 int bhi;
460 int overflow;
461 int carry;
462 int bit;
463 uint64_t ra;
464 uint64_t rb;
465 int above;
466 int greater;
467 int greatereq;
468
469 switch (dw)
470 {
471 case 0: dwsiz = 7; dwmask = 0xffU; break;
472 case 1: dwsiz = 15; dwmask = 0xffffU; break;
473 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
474 }
475
476 zero = (0 == (result & dwmask));
477 sign = 1 & (result >> dwsiz);
478 ahi = 1 & (r_1v >> dwsiz);
479 bhi = 1 & (rimmv >> dwsiz);
480 overflow = (sign != ahi) & (ahi == !bhi);
481 bit = (dwsiz + 1);
482 ra = r_1v & dwmask;
483 rb = rimmv & dwmask;
484 switch (al)
485 {
486 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
487 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
488 default: carry = 0; break;
489 }
490 above = (!carry & !zero);
491 greater = (sign == overflow) & !zero;
492 greatereq = (sign == overflow);
493
494 cpu->state.regs[r_d] = (
495 (above << 6) |
496 (greater << 5) |
497 (greatereq << 4) |
498 (sign << 3) |
499 (overflow << 2) |
500 (carry << 1) |
501 (zero << 0));
502 }
503 }
504 break;
505
506 case FT32_PAT_LDK:
507 cpu->state.regs[r_d] = k20;
508 break;
509
510 case FT32_PAT_LPM:
511 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2);
512 cpu->state.cycles += 1;
513 break;
514
515 case FT32_PAT_LPMI:
3b4b0a62 516 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15);
f46e4eb7
JB		 517 cpu->state.cycles += 1;
518 break;
519
520 case FT32_PAT_STA:
521 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
522 break;
523
524 case FT32_PAT_STI:
3b4b0a62 525 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]);
f46e4eb7
JB		 526 break;
527
528 case FT32_PAT_LDA:
529 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa);
530 cpu->state.cycles += 1;
531 break;
532
533 case FT32_PAT_LDI:
3b4b0a62 534 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
f46e4eb7
JB		 535 cpu->state.cycles += 1;
536 break;
537
538 case FT32_PAT_EXA:
539 {
540 uint32_t tmp;
541 tmp = cpu_mem_read (sd, dw, aa);
542 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
543 cpu->state.regs[r_d] = tmp;
544 cpu->state.cycles += 1;
545 }
546 break;
547
548 case FT32_PAT_EXI:
549 {
550 uint32_t tmp;
3b4b0a62
JB		 551 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
552 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]);
f46e4eb7
JB		 553 cpu->state.regs[r_d] = tmp;
554 cpu->state.cycles += 1;
555 }
556 break;
557
558 case FT32_PAT_PUSH:
559 ft32_push (sd, r_1v);
560 break;
561
562 case FT32_PAT_LINK:
563 ft32_push (sd, cpu->state.regs[r_d]);
564 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP];
565 cpu->state.regs[FT32_HARD_SP] -= k16;
566 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
567 break;
568
569 case FT32_PAT_UNLINK:
570 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d];
571 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
572 cpu->state.regs[r_d] = ft32_pop (sd);
573 break;
574
575 case FT32_PAT_POP:
576 cpu->state.cycles += 1;
577 cpu->state.regs[r_d] = ft32_pop (sd);
578 break;
579
580 case FT32_PAT_RETURN:
581 cpu->state.pc = ft32_pop (sd);
582 break;
583
584 case FT32_PAT_FFUOP:
585 switch (al)
586 {
587 case 0x0:
588 cpu->state.regs[r_d] = r_1v / rimmv;
589 break;
590 case 0x1:
591 cpu->state.regs[r_d] = r_1v % rimmv;
592 break;
593 case 0x2:
594 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv);
595 break;
596 case 0x3:
597 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv);
598 break;
599
600 case 0x4:
601 {
602 /* strcmp instruction. */
603 uint32_t a = r_1v;
604 uint32_t b = rimmv;
605 uint32_t i = 0;
606 while ((GET_BYTE (a + i) != 0) &&
607 (GET_BYTE (a + i) == GET_BYTE (b + i)))
608 i++;
609 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
610 }
611 break;
612
613 case 0x5:
614 {
615 /* memcpy instruction. */
616 uint32_t src = r_1v;
617 uint32_t dst = cpu->state.regs[r_d];
618 uint32_t i;
395b0d8a 619 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 620 PUT_BYTE (dst + i, GET_BYTE (src + i));
621 }
622 break;
623 case 0x6:
624 {
625 /* strlen instruction. */
626 uint32_t src = r_1v;
627 uint32_t i;
628 for (i = 0; GET_BYTE (src + i) != 0; i++)
629 ;
630 cpu->state.regs[r_d] = i;
631 }
632 break;
633 case 0x7:
634 {
635 /* memset instruction. */
636 uint32_t dst = cpu->state.regs[r_d];
637 uint32_t i;
395b0d8a 638 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 639 PUT_BYTE (dst + i, r_1v);
640 }
641 break;
642 case 0x8:
643 cpu->state.regs[r_d] = r_1v * rimmv;
644 break;
645 case 0x9:
646 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
647 break;
648 case 0xa:
649 {
650 /* stpcpy instruction. */
651 uint32_t src = r_1v;
652 uint32_t dst = cpu->state.regs[r_d];
653 uint32_t i;
654 for (i = 0; GET_BYTE (src + i) != 0; i++)
655 PUT_BYTE (dst + i, GET_BYTE (src + i));
656 PUT_BYTE (dst + i, 0);
657 cpu->state.regs[r_d] = dst + i;
658 }
659 break;
660 case 0xe:
661 {
662 /* streamout instruction. */
663 uint32_t i;
664 uint32_t src = cpu->state.regs[r_1];
665 for (i = 0; i < rimmv; i += (1 << dw))
666 {
667 cpu_mem_write (sd,
668 dw,
669 cpu->state.regs[r_d],
670 cpu_mem_read (sd, dw, src));
671 src += (1 << dw);
672 }
673 }
674 break;
675 default:
676 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
677 ILLEGAL ();
678 }
679 break;
680
681 default:
682 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
683 ILLEGAL ();
684 }
685 cpu->state.num_i++;
686
687escape:
688 ;
689}
690
691void
692sim_engine_run (SIM_DESC sd,
693 int next_cpu_nr, /* ignore */
694 int nr_cpus, /* ignore */
695 int siggnal) /* ignore */
696{
697 sim_cpu *cpu;
698
699 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
700
701 cpu = STATE_CPU (sd, 0);
702
703 while (1)
704 {
705 step_once (sd);
706 if (sim_events_tick (sd))
707 sim_events_process (sd);
708 }
709}
710
f46e4eb7
JB		 711static uint32_t *
712ft32_lookup_register (SIM_CPU *cpu, int nr)
713{
714 /* Handle the register number translation here.
715 * Sim registers are 0-31.
716 * Other tools (gcc, gdb) use:
717 * 0 - fp
718 * 1 - sp
719 * 2 - r0
720 * 31 - cc
721 */
722
723 if ((nr < 0) || (nr > 32))
724 {
725 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
726 abort ();
727 }
728
729 switch (nr)
730 {
731 case FT32_FP_REGNUM:
732 return &cpu->state.regs[FT32_HARD_FP];
733 case FT32_SP_REGNUM:
734 return &cpu->state.regs[FT32_HARD_SP];
735 case FT32_CC_REGNUM:
736 return &cpu->state.regs[FT32_HARD_CC];
737 case FT32_PC_REGNUM:
738 return &cpu->state.pc;
739 default:
740 return &cpu->state.regs[nr - 2];
741 }
742}
743
744static int
745ft32_reg_store (SIM_CPU *cpu,
746 int rn,
747 unsigned char *memory,
748 int length)
749{
750 if (0 <= rn && rn <= 32)
751 {
752 if (length == 4)
753 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
754
755 return 4;
756 }
757 else
758 return 0;
759}
760
761static int
762ft32_reg_fetch (SIM_CPU *cpu,
763 int rn,
764 unsigned char *memory,
765 int length)
766{
767 if (0 <= rn && rn <= 32)
768 {
769 if (length == 4)
770 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
771
772 return 4;
773 }
774 else
775 return 0;
776}
777
778static sim_cia
779ft32_pc_get (SIM_CPU *cpu)
780{
65f90968 781 return cpu->state.pc;
f46e4eb7
JB		 782}
783
784static void
785ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
786{
787 cpu->state.pc = newpc;
788}
789
790/* Cover function of sim_state_free to free the cpu buffers as well. */
791
792static void
793free_state (SIM_DESC sd)
794{
795 if (STATE_MODULES (sd) != NULL)
796 sim_module_uninstall (sd);
797 sim_cpu_free_all (sd);
798 sim_state_free (sd);
799}
800
801SIM_DESC
802sim_open (SIM_OPEN_KIND kind,
803 host_callback *cb,
804 struct bfd *abfd,
2e3d4f4d 805 char * const *argv)
f46e4eb7
JB		 806{
807 char c;
808 size_t i;
809 SIM_DESC sd = sim_state_alloc (kind, cb);
810
ba307cdd
MF		 811 /* Set default options before parsing user options. */
812 current_alignment = STRICT_ALIGNMENT;
f9a4d543 813 current_target_byte_order = BFD_ENDIAN_LITTLE;
ba307cdd 814
f46e4eb7 815 /* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11 816 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
f46e4eb7
JB		 817 {
818 free_state (sd);
819 return 0;
820 }
821
822 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
823 {
824 free_state (sd);
825 return 0;
826 }
827
77cf2ef5 828 /* The parser will print an error message for us, so we silently return. */
f46e4eb7
JB		 829 if (sim_parse_args (sd, argv) != SIM_RC_OK)
830 {
831 free_state (sd);
832 return 0;
833 }
834
835 /* Allocate external memory if none specified by user.
836 Use address 4 here in case the user wanted address 0 unmapped. */
837 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
838 {
839 sim_do_command (sd, "memory region 0x00000000,0x40000");
840 sim_do_command (sd, "memory region 0x800000,0x10000");
841 }
842
843 /* Check for/establish the reference program image. */
844 if (sim_analyze_program (sd,
845 (STATE_PROG_ARGV (sd) != NULL
846 ? *STATE_PROG_ARGV (sd)
847 : NULL), abfd) != SIM_RC_OK)
848 {
849 free_state (sd);
850 return 0;
851 }
852
853 /* Configure/verify the target byte order and other runtime
854 configuration options. */
855 if (sim_config (sd) != SIM_RC_OK)
856 {
857 free_state (sd);
858 return 0;
859 }
860
861 if (sim_post_argv_init (sd) != SIM_RC_OK)
862 {
863 free_state (sd);
864 return 0;
865 }
866
867 /* CPU specific initialization. */
868 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
869 {
870 SIM_CPU *cpu = STATE_CPU (sd, i);
871
872 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
873 CPU_REG_STORE (cpu) = ft32_reg_store;
874 CPU_PC_FETCH (cpu) = ft32_pc_get;
875 CPU_PC_STORE (cpu) = ft32_pc_set;
876 }
877
878 return sd;
879}
880
f46e4eb7
JB		 881SIM_RC
882sim_create_inferior (SIM_DESC sd,
883 struct bfd *abfd,
2e3d4f4d
MF		 884 char * const *argv,
885 char * const *env)
f46e4eb7
JB		 886{
887 uint32_t addr;
888 sim_cpu *cpu = STATE_CPU (sd, 0);
889
890 /* Set the PC. */
891 if (abfd != NULL)
892 addr = bfd_get_start_address (abfd);
893 else
894 addr = 0;
895
0e967299
MF		 896 /* Standalone mode (i.e. `run`) will take care of the argv for us in
897 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
898 with `gdb`), we need to handle it because the user can change the
899 argv on the fly via gdb's 'run'. */
900 if (STATE_PROG_ARGV (sd) != argv)
f46e4eb7
JB		 901 {
902 freeargv (STATE_PROG_ARGV (sd));
903 STATE_PROG_ARGV (sd) = dupargv (argv);
904 }
905 cpu->state.regs[FT32_HARD_SP] = addr;
906 cpu->state.num_i = 0;
907 cpu->state.cycles = 0;
908 cpu->state.next_tick_cycle = 100000;
909
910 return SIM_RC_OK;
911}
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