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[thirdparty/binutils-gdb.git] / sim / h8300 / compile.c
CommitLineData
c906108c 1/*
9f70f8ec 2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
c906108c
SS		 3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
a6ff997c 20#include "config.h"
c906108c
SS		 21#include <signal.h>
22#ifdef HAVE_TIME_H
23#include <time.h>
24#endif
25#ifdef HAVE_STDLIB_H
26#include <stdlib.h>
27#endif
28#ifdef HAVE_SYS_PARAM_H
29#include <sys/param.h>
30#endif
dc5c3759 31
c906108c 32#include "bfd.h"
dc5c3759 33#include "sim-main.h"
a64bfde3 34#include "gdb/sim-h8300.h"
bf174226
V		 35#include "sys/stat.h"
36#include "sys/types.h"
c906108c
SS		 37
38#ifndef SIGTRAP
39# define SIGTRAP 5
40#endif
41
42int debug;
43
44host_callback *sim_callback;
45
46static SIM_OPEN_KIND sim_kind;
47static char *myname;
48
49/* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
52 by gdb. */
dc5c3759 53static void set_simcache_size (SIM_DESC, int);
c906108c 54
dc5c3759 55#define X(op, size) (op * 4 + size)
c906108c 56
59768597 57#define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
dc5c3759 58
c906108c
SS		 59#define h8_opcodes ops
60#define DEFINE_TABLE
61#include "opcode/h8300.h"
62
dc5c3759 63/* CPU data object: */
c906108c 64
dc5c3759
MS		 65static int
66sim_state_initialize (SIM_DESC sd, sim_cpu *cpu)
67{
68 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
69
70 memset (&cpu->regs, 0, sizeof(cpu->regs));
71 cpu->regs[SBR_REGNUM] = 0xFFFFFF00;
72 cpu->pc = 0;
73 cpu->delayed_branch = 0;
74 cpu->memory = NULL;
75 cpu->eightbit = NULL;
76 cpu->mask = 0;
77
78 /* Initialize local simulator state. */
79 sd->sim_cache = NULL;
80 sd->sim_cache_size = 0;
81 sd->cache_idx = NULL;
82 sd->cache_top = 0;
83 sd->memory_size = 0;
84 sd->compiles = 0;
85#ifdef ADEBUG
86 memset (&cpu->stats, 0, sizeof (cpu->stats));
87#endif
88 return 0;
89}
7a292a7a 90
dc5c3759
MS		 91static unsigned int
92h8_get_pc (SIM_DESC sd)
93{
94 return (STATE_CPU (sd, 0)) -> pc;
95}
7a292a7a 96
dc5c3759
MS		 97static void
98h8_set_pc (SIM_DESC sd, unsigned int val)
99{
100 (STATE_CPU (sd, 0)) -> pc = val;
101}
fc974602 102
dc5c3759
MS		 103static unsigned int
104h8_get_ccr (SIM_DESC sd)
105{
106 return (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM];
107}
c906108c 108
dc5c3759
MS		 109static void
110h8_set_ccr (SIM_DESC sd, unsigned int val)
111{
112 (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM] = val;
113}
c906108c 114
dc5c3759
MS		 115static unsigned int
116h8_get_exr (SIM_DESC sd)
117{
118 return (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM];
119}
c906108c 120
dc5c3759
MS		 121static void
122h8_set_exr (SIM_DESC sd, unsigned int val)
123{
124 (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM] = val;
125}
c906108c 126
dc5c3759
MS		 127static int
128h8_get_sbr (SIM_DESC sd)
129{
130 return (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM];
131}
c906108c 132
dc5c3759
MS		 133static void
134h8_set_sbr (SIM_DESC sd, int val)
135{
136 (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM] = val;
137}
c906108c 138
c906108c 139static int
dc5c3759
MS		 140h8_get_vbr (SIM_DESC sd)
141{
142 return (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM];
143}
144
145static void
146h8_set_vbr (SIM_DESC sd, int val)
c906108c 147{
dc5c3759 148 (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM] = val;
c906108c
SS		 149}
150
151static int
dc5c3759 152h8_get_cache_top (SIM_DESC sd)
c906108c 153{
dc5c3759
MS		 154 return sd -> cache_top;
155}
156
157static void
158h8_set_cache_top (SIM_DESC sd, int val)
159{
160 sd -> cache_top = val;
c906108c
SS		 161}
162
c906108c 163static int
dc5c3759 164h8_get_mask (SIM_DESC sd)
c906108c 165{
dc5c3759 166 return (STATE_CPU (sd, 0)) -> mask;
c906108c
SS		 167}
168
dc5c3759
MS		 169static void
170h8_set_mask (SIM_DESC sd, int val)
c906108c 171{
dc5c3759
MS		 172 (STATE_CPU (sd, 0)) -> mask = val;
173}
174#if 0
175static int
176h8_get_exception (SIM_DESC sd)
177{
178 return (STATE_CPU (sd, 0)) -> exception;
179}
c906108c 180
dc5c3759
MS		 181static void
182h8_set_exception (SIM_DESC sd, int val)
183{
184 (STATE_CPU (sd, 0)) -> exception = val;
185}
0ef9643e 186
dc5c3759
MS		 187static enum h8300_sim_state
188h8_get_state (SIM_DESC sd)
189{
190 return sd -> state;
c906108c
SS		 191}
192
dc5c3759
MS		 193static void
194h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
d1360fb0 195{
dc5c3759
MS		 196 sd -> state = val;
197}
198#endif
199static unsigned int
200h8_get_cycles (SIM_DESC sd)
201{
202 return (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM];
203}
204
205static void
206h8_set_cycles (SIM_DESC sd, unsigned int val)
207{
208 (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM] = val;
d1360fb0
V		 209}
210
c906108c 211static unsigned int
dc5c3759 212h8_get_insts (SIM_DESC sd)
c906108c 213{
dc5c3759
MS		 214 return (STATE_CPU (sd, 0)) -> regs[INST_REGNUM];
215}
0ef9643e 216
dc5c3759
MS		 217static void
218h8_set_insts (SIM_DESC sd, unsigned int val)
219{
220 (STATE_CPU (sd, 0)) -> regs[INST_REGNUM] = val;
221}
0ef9643e 222
dc5c3759
MS		 223static unsigned int
224h8_get_ticks (SIM_DESC sd)
225{
226 return (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM];
227}
c906108c 228
dc5c3759
MS		 229static void
230h8_set_ticks (SIM_DESC sd, unsigned int val)
231{
232 (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM] = val;
233}
c906108c 234
dc5c3759
MS		 235static unsigned int
236h8_get_mach (SIM_DESC sd)
237{
238 return (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM];
239}
c906108c 240
dc5c3759
MS		 241static void
242h8_set_mach (SIM_DESC sd, unsigned int val)
243{
244 (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM] = val;
245}
0ef9643e 246
dc5c3759
MS		 247static unsigned int
248h8_get_macl (SIM_DESC sd)
249{
250 return (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM];
251}
0ef9643e 252
dc5c3759
MS		 253static void
254h8_set_macl (SIM_DESC sd, unsigned int val)
255{
256 (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM] = val;
257}
0ef9643e 258
dc5c3759
MS		 259static int
260h8_get_compiles (SIM_DESC sd)
261{
262 return sd -> compiles;
263}
0ef9643e 264
dc5c3759
MS		 265static void
266h8_increment_compiles (SIM_DESC sd)
267{
268 sd -> compiles ++;
269}
0ef9643e 270
dc5c3759
MS		 271static unsigned int *
272h8_get_reg_buf (SIM_DESC sd)
273{
274 return &(((STATE_CPU (sd, 0)) -> regs)[0]);
275}
0ef9643e 276
dc5c3759
MS		 277static unsigned int
278h8_get_reg (SIM_DESC sd, int regnum)
279{
280 return (STATE_CPU (sd, 0)) -> regs[regnum];
281}
c906108c 282
dc5c3759
MS		 283static void
284h8_set_reg (SIM_DESC sd, int regnum, int val)
285{
286 (STATE_CPU (sd, 0)) -> regs[regnum] = val;
287}
0ef9643e 288
dc5c3759
MS		 289#ifdef ADEBUG
290static int
291h8_get_stats (SIM_DESC sd, int idx)
292{
293 return sd -> stats[idx];
294}
c906108c 295
dc5c3759
MS		 296static void
297h8_increment_stats (SIM_DESC sd, int idx)
298{
299 sd -> stats[idx] ++;
300}
301#endif /* ADEBUG */
c906108c 302
dc5c3759
MS		 303static unsigned short *
304h8_get_cache_idx_buf (SIM_DESC sd)
305{
306 return sd -> cache_idx;
307}
c906108c 308
dc5c3759
MS		 309static void
310h8_set_cache_idx_buf (SIM_DESC sd, unsigned short *ptr)
311{
312 sd -> cache_idx = ptr;
313}
c906108c 314
dc5c3759
MS		 315static unsigned short
316h8_get_cache_idx (SIM_DESC sd, unsigned int idx)
317{
318 if (idx > sd->memory_size)
319 return (unsigned short) -1;
320 return sd -> cache_idx[idx];
321}
c906108c 322
dc5c3759
MS		 323static void
324h8_set_cache_idx (SIM_DESC sd, int idx, unsigned int val)
325{
326 sd -> cache_idx[idx] = (unsigned short) val;
327}
c906108c 328
dc5c3759
MS		 329static unsigned char *
330h8_get_memory_buf (SIM_DESC sd)
331{
332 return (STATE_CPU (sd, 0)) -> memory;
333}
c906108c 334
dc5c3759
MS		 335static void
336h8_set_memory_buf (SIM_DESC sd, unsigned char *ptr)
337{
338 (STATE_CPU (sd, 0)) -> memory = ptr;
339}
c906108c 340
dc5c3759
MS		 341static unsigned char
342h8_get_memory (SIM_DESC sd, int idx)
343{
344 return (STATE_CPU (sd, 0)) -> memory[idx];
345}
c906108c 346
dc5c3759
MS		 347static void
348h8_set_memory (SIM_DESC sd, int idx, unsigned int val)
349{
350 (STATE_CPU (sd, 0)) -> memory[idx] = (unsigned char) val;
351}
c906108c 352
dc5c3759
MS		 353static unsigned char *
354h8_get_eightbit_buf (SIM_DESC sd)
355{
356 return (STATE_CPU (sd, 0)) -> eightbit;
357}
c906108c 358
dc5c3759
MS		 359static void
360h8_set_eightbit_buf (SIM_DESC sd, unsigned char *ptr)
361{
362 (STATE_CPU (sd, 0)) -> eightbit = ptr;
363}
c906108c 364
dc5c3759
MS		 365static unsigned char
366h8_get_eightbit (SIM_DESC sd, int idx)
367{
368 return (STATE_CPU (sd, 0)) -> eightbit[idx];
369}
c906108c 370
dc5c3759
MS		 371static void
372h8_set_eightbit (SIM_DESC sd, int idx, unsigned int val)
373{
374 (STATE_CPU (sd, 0)) -> eightbit[idx] = (unsigned char) val;
375}
c906108c 376
dc5c3759
MS		 377static unsigned int
378h8_get_delayed_branch (SIM_DESC sd)
379{
380 return (STATE_CPU (sd, 0)) -> delayed_branch;
c906108c
SS		 381}
382
c906108c 383static void
dc5c3759 384h8_set_delayed_branch (SIM_DESC sd, unsigned int dest)
c906108c 385{
dc5c3759
MS		 386 (STATE_CPU (sd, 0)) -> delayed_branch = dest;
387}
c906108c 388
dc5c3759
MS		 389static char **
390h8_get_command_line (SIM_DESC sd)
391{
392 return (STATE_CPU (sd, 0)) -> command_line;
393}
c906108c 394
dc5c3759
MS		 395static void
396h8_set_command_line (SIM_DESC sd, char ** val)
397{
398 (STATE_CPU (sd, 0)) -> command_line = val;
399}
c906108c 400
dc5c3759
MS		 401static char *
402h8_get_cmdline_arg (SIM_DESC sd, int index)
403{
404 return (STATE_CPU (sd, 0)) -> command_line[index];
405}
c906108c 406
dc5c3759
MS		 407static void
408h8_set_cmdline_arg (SIM_DESC sd, int index, char * val)
409{
410 (STATE_CPU (sd, 0)) -> command_line[index] = val;
411}
c906108c 412
dc5c3759
MS		 413/* MAC Saturation Mode */
414static int
415h8_get_macS (SIM_DESC sd)
416{
417 return (STATE_CPU (sd, 0)) -> macS;
c906108c
SS		 418}
419
dc5c3759
MS		 420static void
421h8_set_macS (SIM_DESC sd, int val)
422{
423 (STATE_CPU (sd, 0)) -> macS = (val != 0);
424}
c906108c 425
dc5c3759
MS		 426/* MAC Zero Flag */
427static int
428h8_get_macZ (SIM_DESC sd)
429{
430 return (STATE_CPU (sd, 0)) -> macZ;
431}
c906108c 432
dc5c3759
MS		 433static void
434h8_set_macZ (SIM_DESC sd, int val)
435{
436 (STATE_CPU (sd, 0)) -> macZ = (val != 0);
437}
c906108c 438
dc5c3759
MS		 439/* MAC Negative Flag */
440static int
441h8_get_macN (SIM_DESC sd)
442{
443 return (STATE_CPU (sd, 0)) -> macN;
444}
c906108c 445
dc5c3759
MS		 446static void
447h8_set_macN (SIM_DESC sd, int val)
448{
449 (STATE_CPU (sd, 0)) -> macN = (val != 0);
450}
c906108c 451
dc5c3759
MS		 452/* MAC Overflow Flag */
453static int
454h8_get_macV (SIM_DESC sd)
455{
456 return (STATE_CPU (sd, 0)) -> macV;
457}
c906108c 458
dc5c3759
MS		 459static void
460h8_set_macV (SIM_DESC sd, int val)
461{
462 (STATE_CPU (sd, 0)) -> macV = (val != 0);
463}
c906108c 464
dc5c3759 465/* End CPU data object. */
c906108c 466
dc5c3759 467/* The rate at which to call the host's poll_quit callback. */
c906108c 468
dc5c3759 469enum { POLL_QUIT_INTERVAL = 0x80000 };
c906108c 470
dc5c3759
MS		 471#define LOW_BYTE(x) ((x) & 0xff)
472#define HIGH_BYTE(x) (((x) >> 8) & 0xff)
473#define P(X, Y) ((X << 8) | Y)
c906108c 474
dc5c3759
MS		 475#define C (c != 0)
476#define Z (nz == 0)
477#define V (v != 0)
478#define N (n != 0)
479#define U (u != 0)
480#define H (h != 0)
481#define UI (ui != 0)
482#define I (intMaskBit != 0)
c906108c 483
dc5c3759
MS		 484#define BUILDSR(SD) \
485 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
486 | (N << 3) | (Z << 2) | (V << 1) | C)
c906108c 487
9f70f8ec
MS		 488#define GETSR(SD) \
489 /* Get Status Register (flags). */ \
490 c = (h8_get_ccr (sd) >> 0) & 1; \
491 v = (h8_get_ccr (sd) >> 1) & 1; \
492 nz = !((h8_get_ccr (sd) >> 2) & 1); \
493 n = (h8_get_ccr (sd) >> 3) & 1; \
494 u = (h8_get_ccr (sd) >> 4) & 1; \
495 h = (h8_get_ccr (sd) >> 5) & 1; \
496 ui = ((h8_get_ccr (sd) >> 6) & 1); \
497 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
498
499
dc5c3759
MS		 500#ifdef __CHAR_IS_SIGNED__
501#define SEXTCHAR(x) ((char) (x))
502#endif
c906108c 503
dc5c3759
MS		 504#ifndef SEXTCHAR
505#define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
506#endif
c906108c 507
dc5c3759
MS		 508#define UEXTCHAR(x) ((x) & 0xff)
509#define UEXTSHORT(x) ((x) & 0xffff)
510#define SEXTSHORT(x) ((short) (x))
c906108c 511
dc5c3759
MS		 512int h8300hmode = 0;
513int h8300smode = 0;
59768597 514int h8300_normal_mode = 0;
dc5c3759 515int h8300sxmode = 0;
c906108c 516
dc5c3759 517static int memory_size;
c906108c 518
dc5c3759
MS		 519static int
520get_now (void)
521{
522 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
523}
c906108c 524
dc5c3759
MS		 525static int
526now_persec (void)
527{
528 return 1;
529}
c906108c 530
dc5c3759
MS		 531static int
532bitfrom (int x)
533{
534 switch (x & SIZE)
535 {
536 case L_8:
537 return SB;
538 case L_16:
539 case L_16U:
540 return SW;
541 case L_32:
542 return SL;
543 case L_P:
59768597 544 return (h8300hmode && !h8300_normal_mode)? SL : SW;
c906108c 545 }
dc5c3759 546 return 0;
c906108c
SS		 547}
548
dc5c3759
MS		 549/* Simulate an indirection / dereference.
550 return 0 for success, -1 for failure.
551*/
c906108c 552
dc5c3759
MS		 553static unsigned int
554lvalue (SIM_DESC sd, int x, int rn, unsigned int *val)
c906108c 555{
dc5c3759
MS		 556 if (val == NULL) /* Paranoia. */
557 return -1;
c906108c 558
dc5c3759 559 switch (x / 4)
c906108c 560 {
dc5c3759
MS		 561 case OP_DISP:
562 if (rn == ZERO_REGNUM)
563 *val = X (OP_IMM, SP);
564 else
565 *val = X (OP_REG, SP);
c906108c 566 break;
dc5c3759
MS		 567 case OP_MEM:
568 *val = X (OP_MEM, SP);
c906108c
SS		 569 break;
570 default:
dc5c3759
MS		 571 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
572 return -1;
c906108c 573 }
dc5c3759 574 return 0;
c906108c
SS		 575}
576
dc5c3759
MS		 577static int
578cmdline_location()
c906108c 579{
59768597 580 if (h8300smode && !h8300_normal_mode)
dc5c3759 581 return 0xffff00L;
59768597 582 else if (h8300hmode && !h8300_normal_mode)
dc5c3759
MS		 583 return 0x2ff00L;
584 else
585 return 0xff00L;
c906108c
SS		 586}
587
de9b1892 588static void
dc5c3759 589decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
c906108c 590{
dc5c3759
MS		 591 int cst[3] = {0, 0, 0};
592 int reg[3] = {0, 0, 0};
593 int rdisp[3] = {0, 0, 0};
594 int opnum;
595 const struct h8_opcode *q;
c906108c 596
dc5c3759
MS		 597 dst->dst.type = -1;
598 dst->src.type = -1;
c906108c 599
dc5c3759
MS		 600 /* Find the exact opcode/arg combo. */
601 for (q = h8_opcodes; q->name; q++)
602 {
c4212d37 603 const op_type *nib = q->data.nib;
dc5c3759 604 unsigned int len = 0;
c906108c 605
dc5c3759 606 if ((q->available == AV_H8SX && !h8300sxmode) ||
9f70f8ec 607 (q->available == AV_H8S && !h8300smode) ||
dc5c3759
MS		 608 (q->available == AV_H8H && !h8300hmode))
609 continue;
c906108c 610
f408565c
MS		 611 cst[0] = cst[1] = cst[2] = 0;
612 reg[0] = reg[1] = reg[2] = 0;
613 rdisp[0] = rdisp[1] = rdisp[2] = 0;
614
dc5c3759 615 while (1)
c906108c 616 {
dc5c3759
MS		 617 op_type looking_for = *nib;
618 int thisnib = data[len / 2];
c906108c 619
dc5c3759
MS		 620 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
621 opnum = ((looking_for & OP3) ? 2 :
622 (looking_for & DST) ? 1 : 0);
623
624 if (looking_for < 16 && looking_for >= 0)
c906108c 625 {
dc5c3759
MS		 626 if (looking_for != thisnib)
627 goto fail;
c906108c 628 }
dc5c3759 629 else
c906108c 630 {
dc5c3759 631 if (looking_for & B31)
c906108c 632 {
dc5c3759
MS		 633 if (!((thisnib & 0x8) != 0))
634 goto fail;
635
636 looking_for = (op_type) (looking_for & ~B31);
637 thisnib &= 0x7;
c906108c 638 }
dc5c3759 639 else if (looking_for & B30)
c906108c 640 {
dc5c3759
MS		 641 if (!((thisnib & 0x8) == 0))
642 goto fail;
643
644 looking_for = (op_type) (looking_for & ~B30);
c906108c 645 }
c906108c 646
dc5c3759
MS		 647 if (looking_for & B21)
648 {
649 if (!((thisnib & 0x4) != 0))
650 goto fail;
c906108c 651
dc5c3759
MS		 652 looking_for = (op_type) (looking_for & ~B21);
653 thisnib &= 0xb;
654 }
655 else if (looking_for & B20)
656 {
657 if (!((thisnib & 0x4) == 0))
658 goto fail;
c906108c 659
dc5c3759
MS		 660 looking_for = (op_type) (looking_for & ~B20);
661 }
c906108c 662
dc5c3759
MS		 663 if (looking_for & B11)
664 {
665 if (!((thisnib & 0x2) != 0))
666 goto fail;
c906108c 667
dc5c3759
MS		 668 looking_for = (op_type) (looking_for & ~B11);
669 thisnib &= 0xd;
670 }
671 else if (looking_for & B10)
672 {
673 if (!((thisnib & 0x2) == 0))
674 goto fail;
c906108c 675
dc5c3759
MS		 676 looking_for = (op_type) (looking_for & ~B10);
677 }
c906108c 678
dc5c3759
MS		 679 if (looking_for & B01)
680 {
681 if (!((thisnib & 0x1) != 0))
682 goto fail;
c906108c 683
dc5c3759
MS		 684 looking_for = (op_type) (looking_for & ~B01);
685 thisnib &= 0xe;
686 }
687 else if (looking_for & B00)
688 {
689 if (!((thisnib & 0x1) == 0))
690 goto fail;
c906108c 691
dc5c3759
MS		 692 looking_for = (op_type) (looking_for & ~B00);
693 }
c906108c 694
dc5c3759
MS		 695 if (looking_for & IGNORE)
696 {
697 /* Hitachi has declared that IGNORE must be zero. */
698 if (thisnib != 0)
699 goto fail;
700 }
701 else if ((looking_for & MODE) == DATA)
702 {
703 ; /* Skip embedded data. */
704 }
705 else if ((looking_for & MODE) == DBIT)
706 {
707 /* Exclude adds/subs by looking at bit 0 and 2, and
708 make sure the operand size, either w or l,
709 matches by looking at bit 1. */
710 if ((looking_for & 7) != (thisnib & 7))
711 goto fail;
c906108c 712
dc5c3759
MS		 713 cst[opnum] = (thisnib & 0x8) ? 2 : 1;
714 }
715 else if ((looking_for & MODE) == REG ||
716 (looking_for & MODE) == LOWREG ||
717 (looking_for & MODE) == IND ||
718 (looking_for & MODE) == PREINC ||
719 (looking_for & MODE) == POSTINC ||
720 (looking_for & MODE) == PREDEC ||
721 (looking_for & MODE) == POSTDEC)
722 {
723 reg[opnum] = thisnib;
724 }
725 else if (looking_for & CTRL)
726 {
727 thisnib &= 7;
728 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
729 ((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
730 ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
731 ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
732 ((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
733 ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
734 goto fail;
735 if (((looking_for & MODE) == CCR_EXR &&
736 (thisnib != C_CCR && thisnib != C_EXR)) ||
737 ((looking_for & MODE) == VBR_SBR &&
738 (thisnib != C_VBR && thisnib != C_SBR)) ||
739 ((looking_for & MODE) == MACREG &&
740 (thisnib != C_MACH && thisnib != C_MACL)))
741 goto fail;
742 if (((looking_for & MODE) == CC_EX_VB_SB &&
743 (thisnib != C_CCR && thisnib != C_EXR &&
744 thisnib != C_VBR && thisnib != C_SBR)))
745 goto fail;
c906108c 746
dc5c3759
MS		 747 reg[opnum] = thisnib;
748 }
749 else if ((looking_for & MODE) == ABS)
750 {
751 /* Absolute addresses are unsigned. */
752 switch (looking_for & SIZE)
753 {
754 case L_8:
755 cst[opnum] = UEXTCHAR (data[len / 2]);
756 break;
757 case L_16:
758 case L_16U:
759 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
760 break;
761 case L_32:
762 cst[opnum] =
763 (data[len / 2 + 0] << 24) +
764 (data[len / 2 + 1] << 16) +
765 (data[len / 2 + 2] << 8) +
766 (data[len / 2 + 3]);
767 break;
768 default:
769 printf ("decode: bad size ABS: %d\n",
770 (looking_for & SIZE));
771 goto end;
772 }
773 }
774 else if ((looking_for & MODE) == DISP ||
775 (looking_for & MODE) == PCREL ||
776 (looking_for & MODE) == INDEXB ||
777 (looking_for & MODE) == INDEXW ||
778 (looking_for & MODE) == INDEXL)
dc5c3759
MS		 779 {
780 switch (looking_for & SIZE)
781 {
782 case L_2:
783 cst[opnum] = thisnib & 3;
dc5c3759
MS		 784 break;
785 case L_8:
786 cst[opnum] = SEXTCHAR (data[len / 2]);
787 break;
788 case L_16:
789 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
790 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
791 break;
792 case L_16U:
793 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
794 break;
795 case L_32:
796 cst[opnum] =
797 (data[len / 2 + 0] << 24) +
798 (data[len / 2 + 1] << 16) +
799 (data[len / 2 + 2] << 8) +
800 (data[len / 2 + 3]);
801 break;
802 default:
803 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
804 (looking_for & SIZE));
805 goto end;
806 }
807 }
808 else if ((looking_for & SIZE) == L_16 ||
809 (looking_for & SIZE) == L_16U)
810 {
811 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
0f42aa71
MS		 812 /* Immediates are always unsigned. */
813 if ((looking_for & SIZE) != L_16U &&
814 (looking_for & MODE) != IMM)
dc5c3759
MS		 815 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
816 }
817 else if (looking_for & ABSJMP)
818 {
819 switch (looking_for & SIZE) {
820 case L_24:
821 cst[opnum] = (data[1] << 16) | (data[2] << 8) | (data[3]);
822 break;
823 case L_32:
824 cst[opnum] =
825 (data[len / 2 + 0] << 24) +
826 (data[len / 2 + 1] << 16) +
827 (data[len / 2 + 2] << 8) +
828 (data[len / 2 + 3]);
829 break;
830 default:
831 printf ("decode: bad size ABSJMP: %d\n",
832 (looking_for & SIZE));
833 goto end;
834 }
835 }
836 else if ((looking_for & MODE) == MEMIND)
837 {
838 cst[opnum] = data[1];
839 }
9f70f8ec
MS		 840 else if ((looking_for & MODE) == VECIND)
841 {
59768597
SA		 842 if(h8300_normal_mode)
843 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 2;
844 else
845 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
9f70f8ec
MS		 846 cst[opnum] += h8_get_vbr (sd); /* Add vector base reg. */
847 }
dc5c3759
MS		 848 else if ((looking_for & SIZE) == L_32)
849 {
850 int i = len / 2;
6147b1f6 851
dc5c3759
MS		 852 cst[opnum] =
853 (data[i + 0] << 24) |
854 (data[i + 1] << 16) |
855 (data[i + 2] << 8) |
856 (data[i + 3]);
857 }
858 else if ((looking_for & SIZE) == L_24)
859 {
860 int i = len / 2;
6147b1f6 861
dc5c3759
MS		 862 cst[opnum] =
863 (data[i + 0] << 16) |
864 (data[i + 1] << 8) |
865 (data[i + 2]);
866 }
867 else if (looking_for & DISPREG)
868 {
869 rdisp[opnum] = thisnib & 0x7;
870 }
871 else if ((looking_for & MODE) == KBIT)
872 {
873 switch (thisnib)
874 {
875 case 9:
876 cst[opnum] = 4;
877 break;
878 case 8:
879 cst[opnum] = 2;
880 break;
881 case 0:
882 cst[opnum] = 1;
883 break;
884 default:
885 goto fail;
886 }
887 }
888 else if ((looking_for & SIZE) == L_8)
889 {
890 if ((looking_for & MODE) == ABS)
891 {
892 /* Will be combined with contents of SBR_REGNUM
893 by fetch (). For all modes except h8sx, this
894 will always contain the value 0xFFFFFF00. */
895 cst[opnum] = data[len / 2] & 0xff;
896 }
897 else
898 {
899 cst[opnum] = data[len / 2] & 0xff;
900 }
901 }
9f70f8ec
MS		 902 else if ((looking_for & SIZE) == L_2)
903 {
904 cst[opnum] = thisnib & 3;
905 }
dc5c3759
MS		 906 else if ((looking_for & SIZE) == L_3 ||
907 (looking_for & SIZE) == L_3NZ)
908 {
909 cst[opnum] = thisnib & 7;
910 if (cst[opnum] == 0 && (looking_for & SIZE) == L_3NZ)
911 goto fail;
912 }
913 else if ((looking_for & SIZE) == L_4)
914 {
915 cst[opnum] = thisnib & 15;
916 }
917 else if ((looking_for & SIZE) == L_5)
918 {
919 cst[opnum] = data[len / 2] & 0x1f;
920 }
921 else if (looking_for == E)
922 {
923#ifdef ADEBUG
924 dst->op = q;
925#endif
926 /* Fill in the args. */
927 {
c4212d37 928 const op_type *args = q->args.nib;
dc5c3759
MS		 929 int hadone = 0;
930 int nargs;
6147b1f6 931
dc5c3759
MS		 932 for (nargs = 0;
933 nargs < 3 && *args != E;
934 nargs++)
935 {
936 int x = *args;
937 ea_type *p;
c906108c 938
dc5c3759
MS		 939 opnum = ((x & OP3) ? 2 :
940 (x & DST) ? 1 : 0);
941 if (x & DST)
942 p = &dst->dst;
943 else if (x & OP3)
944 p = &dst->op3;
945 else
946 p = &dst->src;
c906108c 947
dc5c3759
MS		 948 if ((x & MODE) == IMM ||
949 (x & MODE) == KBIT ||
950 (x & MODE) == DBIT)
951 {
952 /* Use the instruction to determine
953 the operand size. */
954 p->type = X (OP_IMM, OP_SIZE (q->how));
955 p->literal = cst[opnum];
956 }
957 else if ((x & MODE) == CONST_2 ||
958 (x & MODE) == CONST_4 ||
959 (x & MODE) == CONST_8 ||
960 (x & MODE) == CONST_16)
961 {
962 /* Use the instruction to determine
963 the operand size. */
964 p->type = X (OP_IMM, OP_SIZE (q->how));
965 switch (x & MODE) {
966 case CONST_2: p->literal = 2; break;
967 case CONST_4: p->literal = 4; break;
968 case CONST_8: p->literal = 8; break;
969 case CONST_16: p->literal = 16; break;
970 }
971 }
972 else if ((x & MODE) == REG)
973 {
974 p->type = X (OP_REG, bitfrom (x));
975 p->reg = reg[opnum];
976 }
977 else if ((x & MODE) == LOWREG)
978 {
979 p->type = X (OP_LOWREG, bitfrom (x));
980 p->reg = reg[opnum];
981 }
982 else if ((x & MODE) == PREINC)
983 {
984 /* Use the instruction to determine
985 the operand size. */
986 p->type = X (OP_PREINC, OP_SIZE (q->how));
987 p->reg = reg[opnum] & 0x7;
988 }
989 else if ((x & MODE) == POSTINC)
990 {
991 /* Use the instruction to determine
992 the operand size. */
993 p->type = X (OP_POSTINC, OP_SIZE (q->how));
994 p->reg = reg[opnum] & 0x7;
995 }
996 else if ((x & MODE) == PREDEC)
997 {
998 /* Use the instruction to determine
999 the operand size. */
1000 p->type = X (OP_PREDEC, OP_SIZE (q->how));
1001 p->reg = reg[opnum] & 0x7;
1002 }
1003 else if ((x & MODE) == POSTDEC)
1004 {
1005 /* Use the instruction to determine
1006 the operand size. */
1007 p->type = X (OP_POSTDEC, OP_SIZE (q->how));
1008 p->reg = reg[opnum] & 0x7;
1009 }
1010 else if ((x & MODE) == IND)
1011 {
1012 /* Note: an indirect is transformed into
1013 a displacement of zero.
1014 */
1015 /* Use the instruction to determine
1016 the operand size. */
1017 p->type = X (OP_DISP, OP_SIZE (q->how));
1018 p->reg = reg[opnum] & 0x7;
1019 p->literal = 0;
1020 if (OP_KIND (q->how) == O_JSR ||
1021 OP_KIND (q->how) == O_JMP)
b86015ea 1022 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
dc5c3759
MS		 1023 goto end;
1024 }
1025 else if ((x & MODE) == ABS)
1026 {
1027 /* Note: a 16 or 32 bit ABS is transformed into a
1028 displacement from pseudo-register ZERO_REGNUM,
1029 which is always zero. An 8 bit ABS becomes
1030 a displacement from SBR_REGNUM.
1031 */
1032 /* Use the instruction to determine
1033 the operand size. */
1034 p->type = X (OP_DISP, OP_SIZE (q->how));
1035 p->literal = cst[opnum];
1036
1037 /* 8-bit ABS is displacement from SBR.
1038 16 and 32-bit ABS are displacement from ZERO.
1039 (SBR will always be zero except for h8/sx)
1040 */
1041 if ((x & SIZE) == L_8)
1042 p->reg = SBR_REGNUM;
1043 else
1044 p->reg = ZERO_REGNUM;;
1045 }
9f70f8ec
MS		 1046 else if ((x & MODE) == MEMIND ||
1047 (x & MODE) == VECIND)
dc5c3759
MS		 1048 {
1049 /* Size doesn't matter. */
1050 p->type = X (OP_MEM, SB);
1051 p->literal = cst[opnum];
1052 if (OP_KIND (q->how) == O_JSR ||
1053 OP_KIND (q->how) == O_JMP)
b86015ea 1054 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
dc5c3759
MS		 1055 goto end;
1056 }
1057 else if ((x & MODE) == PCREL)
1058 {
1059 /* Size doesn't matter. */
1060 p->type = X (OP_PCREL, SB);
1061 p->literal = cst[opnum];
1062 }
1063 else if (x & ABSJMP)
1064 {
1065 p->type = X (OP_IMM, SP);
1066 p->literal = cst[opnum];
1067 }
f408565c 1068 else if ((x & MODE) == INDEXB)
dc5c3759 1069 {
f408565c
MS		 1070 p->type = X (OP_INDEXB, OP_SIZE (q->how));
1071 p->literal = cst[opnum];
1072 p->reg = rdisp[opnum];
1073 }
1074 else if ((x & MODE) == INDEXW)
1075 {
1076 p->type = X (OP_INDEXW, OP_SIZE (q->how));
dc5c3759
MS		 1077 p->literal = cst[opnum];
1078 p->reg = rdisp[opnum];
1079 }
f408565c
MS		 1080 else if ((x & MODE) == INDEXL)
1081 {
1082 p->type = X (OP_INDEXL, OP_SIZE (q->how));
1083 p->literal = cst[opnum];
1084 p->reg = rdisp[opnum];
1085 }
1086 else if ((x & MODE) == DISP)
1087 {
1088 /* Yuck -- special for mova args. */
1089 if (strncmp (q->name, "mova", 4) == 0 &&
1090 (x & SIZE) == L_2)
1091 {
1092 /* Mova can have a DISP2 dest, with an
1093 INDEXB or INDEXW src. The multiplier
1094 for the displacement value is determined
1095 by the src operand, not by the insn. */
1096
1097 switch (OP_KIND (dst->src.type))
1098 {
1099 case OP_INDEXB:
1100 p->type = X (OP_DISP, SB);
1101 p->literal = cst[opnum];
1102 break;
1103 case OP_INDEXW:
1104 p->type = X (OP_DISP, SW);
1105 p->literal = cst[opnum] * 2;
1106 break;
1107 default:
1108 goto fail;
1109 }
1110 }
1111 else
1112 {
1113 p->type = X (OP_DISP, OP_SIZE (q->how));
1114 p->literal = cst[opnum];
1115 /* DISP2 is special. */
1116 if ((x & SIZE) == L_2)
1117 switch (OP_SIZE (q->how))
1118 {
1119 case SB: break;
1120 case SW: p->literal *= 2; break;
1121 case SL: p->literal *= 4; break;
1122 }
1123 }
1124 p->reg = rdisp[opnum];
1125 }
dc5c3759
MS		 1126 else if (x & CTRL)
1127 {
1128 switch (reg[opnum])
1129 {
1130 case C_CCR:
1131 p->type = X (OP_CCR, SB);
1132 break;
1133 case C_EXR:
1134 p->type = X (OP_EXR, SB);
1135 break;
1136 case C_MACH:
1137 p->type = X (OP_MACH, SL);
1138 break;
1139 case C_MACL:
1140 p->type = X (OP_MACL, SL);
1141 break;
1142 case C_VBR:
1143 p->type = X (OP_VBR, SL);
1144 break;
1145 case C_SBR:
1146 p->type = X (OP_SBR, SL);
1147 break;
1148 }
1149 }
1150 else if ((x & MODE) == CCR)
1151 {
1152 p->type = OP_CCR;
1153 }
1154 else if ((x & MODE) == EXR)
1155 {
1156 p->type = OP_EXR;
1157 }
1158 else
9f70f8ec 1159 printf ("Hmmmm 0x%x...\n", x);
c906108c 1160
dc5c3759
MS		 1161 args++;
1162 }
1163 }
c906108c 1164
dc5c3759
MS		 1165 /* Unary operators: treat src and dst as equivalent. */
1166 if (dst->dst.type == -1)
1167 dst->dst = dst->src;
1168 if (dst->src.type == -1)
1169 dst->src = dst->dst;
1170
1171 dst->opcode = q->how;
1172 dst->cycles = q->time;
c906108c 1173
dc5c3759
MS		 1174 /* And jsr's to these locations are turned into
1175 magic traps. */
fc974602 1176
dc5c3759
MS		 1177 if (OP_KIND (dst->opcode) == O_JSR)
1178 {
1179 switch (dst->src.literal)
1180 {
1181 case 0xc5:
1182 dst->opcode = O (O_SYS_OPEN, SB);
1183 break;
1184 case 0xc6:
1185 dst->opcode = O (O_SYS_READ, SB);
1186 break;
1187 case 0xc7:
1188 dst->opcode = O (O_SYS_WRITE, SB);
1189 break;
1190 case 0xc8:
1191 dst->opcode = O (O_SYS_LSEEK, SB);
1192 break;
1193 case 0xc9:
1194 dst->opcode = O (O_SYS_CLOSE, SB);
1195 break;
1196 case 0xca:
1197 dst->opcode = O (O_SYS_STAT, SB);
1198 break;
1199 case 0xcb:
1200 dst->opcode = O (O_SYS_FSTAT, SB);
1201 break;
1202 case 0xcc:
1203 dst->opcode = O (O_SYS_CMDLINE, SB);
1204 break;
1205 }
1206 /* End of Processing for system calls. */
1207 }
1208
1209 dst->next_pc = addr + len / 2;
1210 return;
1211 }
1212 else
9f70f8ec 1213 printf ("Don't understand 0x%x \n", looking_for);
dc5c3759
MS		 1214 }
1215
1216 len++;
1217 nib++;
1218 }
1219
1220 fail:
1221 ;
1222 }
1223 end:
1224 /* Fell off the end. */
1225 dst->opcode = O (O_ILL, SB);
1226}
1227
1228static void
1229compile (SIM_DESC sd, int pc)
1230{
1231 int idx;
1232
1233 /* Find the next cache entry to use. */
1234 idx = h8_get_cache_top (sd) + 1;
1235 h8_increment_compiles (sd);
1236 if (idx >= sd->sim_cache_size)
c906108c 1237 {
dc5c3759
MS		 1238 idx = 1;
1239 }
1240 h8_set_cache_top (sd, idx);
c906108c 1241
dc5c3759
MS		 1242 /* Throw away its old meaning. */
1243 h8_set_cache_idx (sd, sd->sim_cache[idx].oldpc, 0);
1244
1245 /* Set to new address. */
1246 sd->sim_cache[idx].oldpc = pc;
c906108c 1247
dc5c3759
MS		 1248 /* Fill in instruction info. */
1249 decode (sd, pc, h8_get_memory_buf (sd) + pc, sd->sim_cache + idx);
c906108c 1250
dc5c3759
MS		 1251 /* Point to new cache entry. */
1252 h8_set_cache_idx (sd, pc, idx);
1253}
c906108c
SS		 1254
1255
dc5c3759
MS		 1256static unsigned char *breg[32];
1257static unsigned short *wreg[16];
1258static unsigned int *lreg[18];
1259
1260#define GET_B_REG(X) *(breg[X])
1261#define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1262#define GET_W_REG(X) *(wreg[X])
1263#define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1264#define GET_L_REG(X) h8_get_reg (sd, X)
1265#define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1266
1267#define GET_MEMORY_L(X) \
1268 ((X) < memory_size \
1269 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1270 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1271 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1272 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1273 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1274 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1275
1276#define GET_MEMORY_W(X) \
1277 ((X) < memory_size \
1278 ? ((h8_get_memory (sd, (X)+0) << 8) \
1279 | (h8_get_memory (sd, (X)+1) << 0)) \
1280 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1281 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1282
1283
1284#define GET_MEMORY_B(X) \
1285 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1286 : (h8_get_eightbit (sd, (X) & 0xff)))
1287
1288#define SET_MEMORY_L(X, Y) \
1289{ register unsigned char *_p; register int __y = (Y); \
1290 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1291 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1292 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1293 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1294}
c906108c 1295
dc5c3759
MS		 1296#define SET_MEMORY_W(X, Y) \
1297{ register unsigned char *_p; register int __y = (Y); \
1298 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1299 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1300 _p[0] = __y >> 8; _p[1] = __y; \
1301}
c906108c 1302
dc5c3759
MS		 1303#define SET_MEMORY_B(X, Y) \
1304 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1305 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
c906108c 1306
dc5c3759
MS		 1307/* Simulate a memory fetch.
1308 Return 0 for success, -1 for failure.
1309*/
c906108c 1310
dc5c3759
MS		 1311static int
1312fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
1313{
1314 int rn = arg->reg;
1315 int abs = arg->literal;
1316 int r;
1317 int t;
1318
1319 if (val == NULL)
1320 return -1; /* Paranoia. */
1321
1322 switch (arg->type)
1323 {
1324 /* Indexed register plus displacement mode:
1325
1326 This new family of addressing modes are similar to OP_DISP
1327 (register plus displacement), with two differences:
1328 1) INDEXB uses only the least significant byte of the register,
1329 INDEXW uses only the least significant word, and
1330 INDEXL uses the entire register (just like OP_DISP).
1331 and
1332 2) The displacement value in abs is multiplied by two
1333 for SW-sized operations, and by four for SL-size.
1334
1335 This gives nine possible variations.
1336 */
1337
1338 case X (OP_INDEXB, SB):
1339 case X (OP_INDEXB, SW):
1340 case X (OP_INDEXB, SL):
1341 case X (OP_INDEXW, SB):
1342 case X (OP_INDEXW, SW):
1343 case X (OP_INDEXW, SL):
1344 case X (OP_INDEXL, SB):
1345 case X (OP_INDEXL, SW):
1346 case X (OP_INDEXL, SL):
1347 t = GET_L_REG (rn);
1348 switch (OP_KIND (arg->type)) {
1349 case OP_INDEXB: t &= 0xff; break;
1350 case OP_INDEXW: t &= 0xffff; break;
1351 case OP_INDEXL:
1352 default: break;
1353 }
1354 switch (OP_SIZE (arg->type)) {
1355 case SB:
1356 *val = GET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd));
1357 break;
1358 case SW:
1359 *val = GET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd));
1360 break;
1361 case SL:
1362 *val = GET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd));
1363 break;
1364 }
1365 break;
1366
1367 case X (OP_LOWREG, SB):
1368 *val = GET_L_REG (rn) & 0xff;
1369 break;
1370 case X (OP_LOWREG, SW):
1371 *val = GET_L_REG (rn) & 0xffff;
1372 break;
1373
1374 case X (OP_REG, SB): /* Register direct, byte. */
1375 *val = GET_B_REG (rn);
1376 break;
1377 case X (OP_REG, SW): /* Register direct, word. */
1378 *val = GET_W_REG (rn);
1379 break;
1380 case X (OP_REG, SL): /* Register direct, long. */
1381 *val = GET_L_REG (rn);
1382 break;
1383 case X (OP_IMM, SB): /* Immediate, byte. */
1384 case X (OP_IMM, SW): /* Immediate, word. */
1385 case X (OP_IMM, SL): /* Immediate, long. */
1386 *val = abs;
1387 break;
1388 case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
1389 t = GET_L_REG (rn);
3a6c31f9 1390 r = GET_MEMORY_B (t & h8_get_mask (sd));
dc5c3759
MS		 1391 if (!twice)
1392 t += 1;
dc5c3759
MS		 1393 SET_L_REG (rn, t);
1394 *val = r;
1395 break;
1396 case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
1397 t = GET_L_REG (rn);
3a6c31f9 1398 r = GET_MEMORY_W (t & h8_get_mask (sd));
dc5c3759
MS		 1399 if (!twice)
1400 t += 2;
dc5c3759
MS		 1401 SET_L_REG (rn, t);
1402 *val = r;
1403 break;
1404 case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
1405 t = GET_L_REG (rn);
3a6c31f9 1406 r = GET_MEMORY_L (t & h8_get_mask (sd));
dc5c3759
MS		 1407 if (!twice)
1408 t += 4;
dc5c3759
MS		 1409 SET_L_REG (rn, t);
1410 *val = r;
1411 break;
1412
1413 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
1414 t = GET_L_REG (rn);
3a6c31f9 1415 r = GET_MEMORY_B (t & h8_get_mask (sd));
dc5c3759
MS		 1416 if (!twice)
1417 t -= 1;
dc5c3759
MS		 1418 SET_L_REG (rn, t);
1419 *val = r;
1420 break;
1421 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
1422 t = GET_L_REG (rn);
3a6c31f9 1423 r = GET_MEMORY_W (t & h8_get_mask (sd));
dc5c3759
MS		 1424 if (!twice)
1425 t -= 2;
dc5c3759
MS		 1426 SET_L_REG (rn, t);
1427 *val = r;
1428 break;
1429 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
1430 t = GET_L_REG (rn);
3a6c31f9 1431 r = GET_MEMORY_L (t & h8_get_mask (sd));
dc5c3759
MS		 1432 if (!twice)
1433 t -= 4;
dc5c3759
MS		 1434 SET_L_REG (rn, t);
1435 *val = r;
1436 break;
1437
1438 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
1439 t = GET_L_REG (rn) - 1;
dc5c3759 1440 SET_L_REG (rn, t);
3a6c31f9 1441 t &= h8_get_mask (sd);
dc5c3759
MS		 1442 *val = GET_MEMORY_B (t);
1443 break;
1444
1445 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
1446 t = GET_L_REG (rn) - 2;
dc5c3759 1447 SET_L_REG (rn, t);
3a6c31f9 1448 t &= h8_get_mask (sd);
dc5c3759
MS		 1449 *val = GET_MEMORY_W (t);
1450 break;
1451
1452 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
1453 t = GET_L_REG (rn) - 4;
dc5c3759 1454 SET_L_REG (rn, t);
3a6c31f9 1455 t &= h8_get_mask (sd);
dc5c3759
MS		 1456 *val = GET_MEMORY_L (t);
1457 break;
1458
1459 case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
1460 t = GET_L_REG (rn) + 1;
dc5c3759 1461 SET_L_REG (rn, t);
3a6c31f9 1462 t &= h8_get_mask (sd);
dc5c3759
MS		 1463 *val = GET_MEMORY_B (t);
1464 break;
1465
1466 case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
1467 t = GET_L_REG (rn) + 2;
dc5c3759 1468 SET_L_REG (rn, t);
3a6c31f9 1469 t &= h8_get_mask (sd);
dc5c3759
MS		 1470 *val = GET_MEMORY_W (t);
1471 break;
1472
1473 case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
1474 t = GET_L_REG (rn) + 4;
dc5c3759 1475 SET_L_REG (rn, t);
3a6c31f9 1476 t &= h8_get_mask (sd);
dc5c3759
MS		 1477 *val = GET_MEMORY_L (t);
1478 break;
1479
1480 case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
1481 t = GET_L_REG (rn) + abs;
1482 t &= h8_get_mask (sd);
1483 *val = GET_MEMORY_B (t);
1484 break;
1485
1486 case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
1487 t = GET_L_REG (rn) + abs;
1488 t &= h8_get_mask (sd);
1489 *val = GET_MEMORY_W (t);
1490 break;
1491
1492 case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
1493 t = GET_L_REG (rn) + abs;
1494 t &= h8_get_mask (sd);
1495 *val =GET_MEMORY_L (t);
1496 break;
1497
1498 case X (OP_MEM, SL): /* Absolute memory address, long. */
1499 t = GET_MEMORY_L (abs);
1500 t &= h8_get_mask (sd);
1501 *val = t;
1502 break;
1503
1504 case X (OP_MEM, SW): /* Absolute memory address, word. */
1505 t = GET_MEMORY_W (abs);
1506 t &= h8_get_mask (sd);
1507 *val = t;
1508 break;
1509
1510 case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
1511 case X (OP_PCREL, SW):
1512 case X (OP_PCREL, SL):
1513 case X (OP_PCREL, SN):
1514 *val = abs;
1515 break;
1516
1517 case X (OP_MEM, SB): /* Why isn't this implemented? */
1518 default:
1519 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1520 return -1;
1521 }
1522 return 0; /* Success. */
1523}
1524
1525/* Normal fetch. */
1526
1527static int
1528fetch (SIM_DESC sd, ea_type *arg, int *val)
1529{
1530 return fetch_1 (sd, arg, val, 0);
1531}
1532
1533/* Fetch which will be followed by a store to the same location.
1534 The difference being that we don't want to do a post-increment
1535 or post-decrement at this time: we'll do it when we store. */
1536
1537static int
1538fetch2 (SIM_DESC sd, ea_type *arg, int *val)
1539{
1540 return fetch_1 (sd, arg, val, 1);
1541}
1542
1543/* Simulate a memory store.
1544 Return 0 for success, -1 for failure.
1545*/
1546
1547static int
1548store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
1549{
1550 int rn = arg->reg;
1551 int abs = arg->literal;
1552 int t;
1553
1554 switch (arg->type)
1555 {
1556 /* Indexed register plus displacement mode:
1557
1558 This new family of addressing modes are similar to OP_DISP
1559 (register plus displacement), with two differences:
1560 1) INDEXB uses only the least significant byte of the register,
1561 INDEXW uses only the least significant word, and
1562 INDEXL uses the entire register (just like OP_DISP).
1563 and
1564 2) The displacement value in abs is multiplied by two
1565 for SW-sized operations, and by four for SL-size.
1566
1567 This gives nine possible variations.
1568 */
1569
1570 case X (OP_INDEXB, SB):
1571 case X (OP_INDEXB, SW):
1572 case X (OP_INDEXB, SL):
1573 case X (OP_INDEXW, SB):
1574 case X (OP_INDEXW, SW):
1575 case X (OP_INDEXW, SL):
1576 case X (OP_INDEXL, SB):
1577 case X (OP_INDEXL, SW):
1578 case X (OP_INDEXL, SL):
1579 t = GET_L_REG (rn);
1580 switch (OP_KIND (arg->type)) {
1581 case OP_INDEXB: t &= 0xff; break;
1582 case OP_INDEXW: t &= 0xffff; break;
1583 case OP_INDEXL:
1584 default: break;
1585 }
1586 switch (OP_SIZE (arg->type)) {
1587 case SB:
1588 SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
1589 break;
1590 case SW:
1591 SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
1592 break;
1593 case SL:
1594 SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
1595 break;
1596 }
1597 break;
1598
1599 case X (OP_REG, SB): /* Register direct, byte. */
1600 SET_B_REG (rn, n);
1601 break;
1602 case X (OP_REG, SW): /* Register direct, word. */
1603 SET_W_REG (rn, n);
1604 break;
1605 case X (OP_REG, SL): /* Register direct, long. */
1606 SET_L_REG (rn, n);
1607 break;
1608
1609 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
1610 t = GET_L_REG (rn);
1611 if (!twice)
1612 t -= 1;
dc5c3759 1613 SET_L_REG (rn, t);
3a6c31f9 1614 t &= h8_get_mask (sd);
dc5c3759
MS		 1615 SET_MEMORY_B (t, n);
1616
1617 break;
1618 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
1619 t = GET_L_REG (rn);
1620 if (!twice)
1621 t -= 2;
dc5c3759 1622 SET_L_REG (rn, t);
3a6c31f9 1623 t &= h8_get_mask (sd);
dc5c3759
MS		 1624 SET_MEMORY_W (t, n);
1625 break;
1626
1627 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
1628 t = GET_L_REG (rn);
1629 if (!twice)
1630 t -= 4;
dc5c3759 1631 SET_L_REG (rn, t);
3a6c31f9 1632 t &= h8_get_mask (sd);
dc5c3759
MS		 1633 SET_MEMORY_L (t, n);
1634 break;
1635
1636 case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
1637 t = GET_L_REG (rn);
1638 if (!twice)
1639 t += 1;
dc5c3759 1640 SET_L_REG (rn, t);
3a6c31f9 1641 t &= h8_get_mask (sd);
dc5c3759
MS		 1642 SET_MEMORY_B (t, n);
1643
1644 break;
1645 case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
1646 t = GET_L_REG (rn);
1647 if (!twice)
1648 t += 2;
dc5c3759 1649 SET_L_REG (rn, t);
3a6c31f9 1650 t &= h8_get_mask (sd);
dc5c3759
MS		 1651 SET_MEMORY_W (t, n);
1652 break;
1653
1654 case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
1655 t = GET_L_REG (rn);
1656 if (!twice)
1657 t += 4;
dc5c3759 1658 SET_L_REG (rn, t);
3a6c31f9 1659 t &= h8_get_mask (sd);
dc5c3759
MS		 1660 SET_MEMORY_L (t, n);
1661 break;
1662
1663 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
3a6c31f9 1664 t = GET_L_REG (rn);
dc5c3759 1665 SET_L_REG (rn, t - 1);
3a6c31f9
YS		 1666 t &= h8_get_mask (sd);
1667 SET_MEMORY_B (t, n);
dc5c3759
MS		 1668 break;
1669
1670 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
3a6c31f9 1671 t = GET_L_REG (rn);
dc5c3759 1672 SET_L_REG (rn, t - 2);
3a6c31f9
YS		 1673 t &= h8_get_mask (sd);
1674 SET_MEMORY_W (t, n);
dc5c3759
MS		 1675 break;
1676
1677 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
3a6c31f9 1678 t = GET_L_REG (rn);
dc5c3759 1679 SET_L_REG (rn, t - 4);
3a6c31f9
YS		 1680 t &= h8_get_mask (sd);
1681 SET_MEMORY_L (t, n);
dc5c3759
MS		 1682 break;
1683
1684 case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
3a6c31f9 1685 t = GET_L_REG (rn);
dc5c3759 1686 SET_L_REG (rn, t + 1);
3a6c31f9
YS		 1687 t &= h8_get_mask (sd);
1688 SET_MEMORY_B (t, n);
dc5c3759
MS		 1689 break;
1690
1691 case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
3a6c31f9 1692 t = GET_L_REG (rn);
dc5c3759 1693 SET_L_REG (rn, t + 2);
3a6c31f9
YS		 1694 t &= h8_get_mask (sd);
1695 SET_MEMORY_W (t, n);
dc5c3759
MS		 1696 break;
1697
1698 case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
3a6c31f9 1699 t = GET_L_REG (rn);
dc5c3759 1700 SET_L_REG (rn, t + 4);
3a6c31f9
YS		 1701 t &= h8_get_mask (sd);
1702 SET_MEMORY_L (t, n);
dc5c3759
MS		 1703 break;
1704
1705 case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
1706 t = GET_L_REG (rn) + abs;
1707 t &= h8_get_mask (sd);
1708 SET_MEMORY_B (t, n);
1709 break;
1710
1711 case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
1712 t = GET_L_REG (rn) + abs;
1713 t &= h8_get_mask (sd);
1714 SET_MEMORY_W (t, n);
1715 break;
1716
1717 case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
1718 t = GET_L_REG (rn) + abs;
1719 t &= h8_get_mask (sd);
1720 SET_MEMORY_L (t, n);
1721 break;
1722
1723
1724 case X (OP_MEM, SB): /* Why isn't this implemented? */
1725 case X (OP_MEM, SW): /* Why isn't this implemented? */
1726 case X (OP_MEM, SL): /* Why isn't this implemented? */
1727 default:
1728 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1729 return -1;
1730 }
1731 return 0;
1732}
1733
1734/* Normal store. */
1735
1736static int
1737store (SIM_DESC sd, ea_type *arg, int n)
1738{
1739 return store_1 (sd, arg, n, 0);
1740}
1741
1742/* Store which follows a fetch from the same location.
1743 The difference being that we don't want to do a pre-increment
1744 or pre-decrement at this time: it was already done when we fetched. */
1745
1746static int
1747store2 (SIM_DESC sd, ea_type *arg, int n)
1748{
1749 return store_1 (sd, arg, n, 1);
1750}
1751
1752static union
1753{
1754 short int i;
1755 struct
1756 {
1757 char low;
1758 char high;
1759 }
1760 u;
1761} littleendian;
1762
1763/* Flag to be set whenever a new SIM_DESC object is created. */
1764static int init_pointers_needed = 1;
1765
1766static void
1767init_pointers (SIM_DESC sd)
1768{
1769 if (init_pointers_needed)
1770 {
1771 int i;
1772
1773 littleendian.i = 1;
1774
59768597 1775 if (h8300smode && !h8300_normal_mode)
dc5c3759 1776 memory_size = H8300S_MSIZE;
59768597 1777 else if (h8300hmode && !h8300_normal_mode)
dc5c3759
MS		 1778 memory_size = H8300H_MSIZE;
1779 else
1780 memory_size = H8300_MSIZE;
1781 /* `msize' must be a power of two. */
1782 if ((memory_size & (memory_size - 1)) != 0)
1783 {
1784 (*sim_callback->printf_filtered)
1785 (sim_callback,
1786 "init_pointers: bad memory size %d, defaulting to %d.\n",
1787 memory_size, memory_size = H8300S_MSIZE);
1788 }
1789
1790 if (h8_get_memory_buf (sd))
1791 free (h8_get_memory_buf (sd));
1792 if (h8_get_cache_idx_buf (sd))
1793 free (h8_get_cache_idx_buf (sd));
1794 if (h8_get_eightbit_buf (sd))
1795 free (h8_get_eightbit_buf (sd));
1796
1797 h8_set_memory_buf (sd, (unsigned char *)
1798 calloc (sizeof (char), memory_size));
1799 h8_set_cache_idx_buf (sd, (unsigned short *)
1800 calloc (sizeof (short), memory_size));
1801 sd->memory_size = memory_size;
1802 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
1803
1804 h8_set_mask (sd, memory_size - 1);
1805
1806 memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
1807
1808 for (i = 0; i < 8; i++)
1809 {
1810 /* FIXME: rewrite using local buffer. */
1811 unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
1812 unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
1813 unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
1814 unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
1815 h8_set_reg (sd, i, 0x00112233);
1816
1817 while (p < e)
1818 {
1819 if (*p == 0x22)
1820 breg[i] = p;
1821 if (*p == 0x33)
1822 breg[i + 8] = p;
1823 if (*p == 0x11)
1824 breg[i + 16] = p;
1825 if (*p == 0x00)
1826 breg[i + 24] = p;
1827 p++;
1828 }
1829
1830 wreg[i] = wreg[i + 8] = 0;
1831 while (q < u)
1832 {
1833 if (*q == 0x2233)
1834 {
1835 wreg[i] = q;
1836 }
1837 if (*q == 0x0011)
1838 {
1839 wreg[i + 8] = q;
1840 }
1841 q++;
1842 }
1843
1844 if (wreg[i] == 0 || wreg[i + 8] == 0)
1845 (*sim_callback->printf_filtered) (sim_callback,
1846 "init_pointers: internal error.\n");
1847
1848 h8_set_reg (sd, i, 0);
1849 lreg[i] = h8_get_reg_buf (sd) + i;
1850 }
1851
1852 /* Note: sim uses pseudo-register ZERO as a zero register. */
1853 lreg[ZERO_REGNUM] = h8_get_reg_buf (sd) + ZERO_REGNUM;
1854 init_pointers_needed = 0;
1855
1856 /* Initialize the seg registers. */
1857 if (!sd->sim_cache)
1858 set_simcache_size (sd, CSIZE);
1859 }
1860}
1861
dc5c3759
MS		 1862int
1863sim_stop (SIM_DESC sd)
1864{
1865 /* FIXME: use a real signal value. */
1866 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
1867 return 1;
1868}
1869
1870#define OBITOP(name, f, s, op) \
1871case O (name, SB): \
1872{ \
1873 int m, tmp; \
1874 \
1875 if (f) \
1876 if (fetch (sd, &code->dst, &ea)) \
1877 goto end; \
1878 if (fetch (sd, &code->src, &tmp)) \
1879 goto end; \
b86015ea 1880 m = 1 << (tmp & 7); \
dc5c3759
MS		 1881 op; \
1882 if (s) \
1883 if (store (sd, &code->dst,ea)) \
1884 goto end; \
1885 goto next; \
1886}
1887
1888void
1889sim_resume (SIM_DESC sd, int step, int siggnal)
1890{
1891 static int init1;
1892 int cycles = 0;
1893 int insts = 0;
1894 int tick_start = get_now ();
dc5c3759
MS		 1895 int poll_count = 0;
1896 int res;
1897 int tmp;
1898 int rd;
1899 int ea;
1900 int bit;
1901 int pc;
1902 int c, nz, v, n, u, h, ui, intMaskBit;
1903 int trace, intMask;
1904 int oldmask;
1905 enum sim_stop reason;
1906 int sigrc;
1907
1908 init_pointers (sd);
1909
dc5c3759
MS		 1910 if (step)
1911 {
1912 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
1913 }
1914 else
1915 {
1916 sim_engine_set_run_state (sd, sim_running, 0);
1917 }
1918
1919 pc = h8_get_pc (sd);
1920
1921 /* The PC should never be odd. */
1922 if (pc & 0x1)
1923 {
1924 sim_engine_set_run_state (sd, sim_stopped, SIGBUS);
1925 return;
1926 }
1927
1928 /* Get Status Register (flags). */
9f70f8ec 1929 GETSR (sd);
dc5c3759
MS		 1930
1931 if (h8300smode) /* Get exr. */
1932 {
1933 trace = (h8_get_exr (sd) >> 7) & 1;
1934 intMask = h8_get_exr (sd) & 7;
1935 }
1936
1937 oldmask = h8_get_mask (sd);
59768597 1938 if (!h8300hmode || h8300_normal_mode)
dc5c3759
MS		 1939 h8_set_mask (sd, 0xffff);
1940 do
1941 {
1942 unsigned short cidx;
1943 decoded_inst *code;
1944
1945 top:
1946 cidx = h8_get_cache_idx (sd, pc);
1947 if (cidx == (unsigned short) -1 ||
1948 cidx >= sd->sim_cache_size)
1949 goto illegal;
1950
1951 code = sd->sim_cache + cidx;
1952
1953#if ADEBUG
1954 if (debug)
1955 {
1956 printf ("%x %d %s\n", pc, code->opcode,
1957 code->op ? code->op->name : "**");
1958 }
1959 h8_increment_stats (sd, code->opcode);
1960#endif
1961
1962 if (code->opcode)
1963 {
1964 cycles += code->cycles;
1965 insts++;
1966 }
1967
1968 switch (code->opcode)
1969 {
1970 case 0:
1971 /*
1972 * This opcode is a fake for when we get to an
1973 * instruction which hasnt been compiled
1974 */
1975 compile (sd, pc);
1976 goto top;
1977 break;
1978
1979 case O (O_MOVAB, SL):
1980 case O (O_MOVAW, SL):
1981 case O (O_MOVAL, SL):
1982 /* 1) Evaluate 2nd argument (dst).
1983 2) Mask / zero extend according to whether 1st argument (src)
1984 is INDEXB, INDEXW, or INDEXL.
1985 3) Left-shift the result by 0, 1 or 2, according to size of mova
1986 (mova/b, mova/w, mova/l).
1987 4) Add literal value of 1st argument (src).
1988 5) Store result in 3rd argument (op3).
f408565c
MS		 1989 */
1990
1991 /* Alas, since this is the only instruction with 3 arguments,
1992 decode doesn't handle them very well. Some fix-up is required.
1993
1994 a) The size of dst is determined by whether src is
1995 INDEXB or INDEXW. */
dc5c3759 1996
f408565c
MS		 1997 if (OP_KIND (code->src.type) == OP_INDEXB)
1998 code->dst.type = X (OP_KIND (code->dst.type), SB);
1999 else if (OP_KIND (code->src.type) == OP_INDEXW)
2000 code->dst.type = X (OP_KIND (code->dst.type), SW);
2001
2002 /* b) If op3 == null, then this is the short form of the insn.
2003 Dst is the dispreg of src, and op3 is the 32-bit form
2004 of the same register.
dc5c3759 2005 */
f408565c
MS		 2006
2007 if (code->op3.type == 0)
2008 {
2009 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
2010 We get to compose dst and op3 as follows:
2011
2012 op3 is a 32-bit register, ID == src.reg.
2013 dst is the same register, but 8 or 16 bits
2014 depending on whether src is INDEXB or INDEXW.
2015 */
2016
2017 code->op3.type = X (OP_REG, SL);
2018 code->op3.reg = code->src.reg;
2019 code->op3.literal = 0;
2020
2021 if (OP_KIND (code->src.type) == OP_INDEXB)
e073c474
AO		 2022 {
2023 code->dst.type = X (OP_REG, SB);
2024 code->dst.reg = code->op3.reg + 8;
2025 }
f408565c
MS		 2026 else
2027 code->dst.type = X (OP_REG, SW);
2028 }
2029
dc5c3759
MS		 2030 if (fetch (sd, &code->dst, &ea))
2031 goto end;
2032
2033 switch (OP_KIND (code->src.type)) {
2034 case OP_INDEXB: ea = ea & 0xff; break;
2035 case OP_INDEXW: ea = ea & 0xffff; break;
2036 case OP_INDEXL: break;
2037 default: goto illegal;
2038 }
2039
2040 switch (code->opcode) {
2041 case O (O_MOVAB, SL): break;
2042 case O (O_MOVAW, SL): ea = ea << 1; break;
2043 case O (O_MOVAL, SL): ea = ea << 2; break;
2044 default: goto illegal;
2045 }
2046
2047 ea = ea + code->src.literal;
2048
2049 if (store (sd, &code->op3, ea))
2050 goto end;
2051
2052 goto next;
2053
2054 case O (O_SUBX, SB): /* subx, extended sub */
2055 if (fetch2 (sd, &code->dst, &rd))
2056 goto end;
2057 if (fetch (sd, &code->src, &ea))
2058 goto end;
2059 ea = -(ea + C);
2060 res = rd + ea;
2061 goto alu8;
2062
2063 case O (O_SUBX, SW): /* subx, extended sub */
2064 if (fetch2 (sd, &code->dst, &rd))
2065 goto end;
2066 if (fetch (sd, &code->src, &ea))
2067 goto end;
2068 ea = -(ea + C);
2069 res = rd + ea;
2070 goto alu16;
2071
2072 case O (O_SUBX, SL): /* subx, extended sub */
2073 if (fetch2 (sd, &code->dst, &rd))
2074 goto end;
2075 if (fetch (sd, &code->src, &ea))
2076 goto end;
2077 ea = -(ea + C);
2078 res = rd + ea;
2079 goto alu32;
2080
2081 case O (O_ADDX, SB): /* addx, extended add */
2082 if (fetch2 (sd, &code->dst, &rd))
2083 goto end;
2084 if (fetch (sd, &code->src, &ea))
2085 goto end;
2086 ea = ea + C;
2087 res = rd + ea;
2088 goto alu8;
2089
2090 case O (O_ADDX, SW): /* addx, extended add */
2091 if (fetch2 (sd, &code->dst, &rd))
2092 goto end;
2093 if (fetch (sd, &code->src, &ea))
2094 goto end;
2095 ea = ea + C;
2096 res = rd + ea;
2097 goto alu16;
2098
2099 case O (O_ADDX, SL): /* addx, extended add */
2100 if (fetch2 (sd, &code->dst, &rd))
2101 goto end;
2102 if (fetch (sd, &code->src, &ea))
2103 goto end;
2104 ea = ea + C;
2105 res = rd + ea;
2106 goto alu32;
2107
2108 case O (O_SUB, SB): /* sub.b */
2109 /* Fetch rd and ea. */
2110 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2111 goto end;
2112 ea = -ea;
2113 res = rd + ea;
2114 goto alu8;
2115
2116 case O (O_SUB, SW): /* sub.w */
2117 /* Fetch rd and ea. */
2118 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2119 goto end;
2120 ea = -ea;
2121 res = rd + ea;
2122 goto alu16;
2123
2124 case O (O_SUB, SL): /* sub.l */
2125 /* Fetch rd and ea. */
2126 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2127 goto end;
2128 ea = -ea;
2129 res = rd + ea;
2130 goto alu32;
2131
2132 case O (O_NEG, SB): /* neg.b */
2133 /* Fetch ea. */
2134 if (fetch2 (sd, &code->src, &ea))
2135 goto end;
2136 ea = -ea;
2137 rd = 0;
2138 res = rd + ea;
2139 goto alu8;
2140
2141 case O (O_NEG, SW): /* neg.w */
2142 /* Fetch ea. */
2143 if (fetch2 (sd, &code->src, &ea))
2144 goto end;
2145 ea = -ea;
2146 rd = 0;
2147 res = rd + ea;
2148 goto alu16;
2149
2150 case O (O_NEG, SL): /* neg.l */
2151 /* Fetch ea. */
2152 if (fetch2 (sd, &code->src, &ea))
2153 goto end;
2154 ea = -ea;
2155 rd = 0;
2156 res = rd + ea;
2157 goto alu32;
2158
2159 case O (O_ADD, SB): /* add.b */
2160 if (fetch2 (sd, &code->dst, &rd))
2161 goto end;
2162 if (fetch (sd, &code->src, &ea))
2163 goto end;
2164 res = rd + ea;
2165 goto alu8;
2166
2167 case O (O_ADD, SW): /* add.w */
2168 if (fetch2 (sd, &code->dst, &rd))
2169 goto end;
2170 if (fetch (sd, &code->src, &ea))
2171 goto end;
2172 res = rd + ea;
2173 goto alu16;
2174
2175 case O (O_ADD, SL): /* add.l */
2176 if (fetch2 (sd, &code->dst, &rd))
2177 goto end;
2178 if (fetch (sd, &code->src, &ea))
2179 goto end;
2180 res = rd + ea;
2181 goto alu32;
2182
2183 case O (O_AND, SB): /* and.b */
2184 /* Fetch rd and ea. */
2185 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2186 goto end;
2187 res = rd & ea;
2188 goto log8;
2189
2190 case O (O_AND, SW): /* and.w */
2191 /* Fetch rd and ea. */
2192 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2193 goto end;
2194 res = rd & ea;
2195 goto log16;
2196
2197 case O (O_AND, SL): /* and.l */
2198 /* Fetch rd and ea. */
2199 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2200 goto end;
2201 res = rd & ea;
2202 goto log32;
2203
2204 case O (O_OR, SB): /* or.b */
2205 /* Fetch rd and ea. */
2206 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2207 goto end;
2208 res = rd | ea;
2209 goto log8;
2210
2211 case O (O_OR, SW): /* or.w */
2212 /* Fetch rd and ea. */
2213 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2214 goto end;
2215 res = rd | ea;
2216 goto log16;
2217
2218 case O (O_OR, SL): /* or.l */
2219 /* Fetch rd and ea. */
2220 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2221 goto end;
2222 res = rd | ea;
2223 goto log32;
2224
2225 case O (O_XOR, SB): /* xor.b */
2226 /* Fetch rd and ea. */
2227 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2228 goto end;
2229 res = rd ^ ea;
2230 goto log8;
2231
2232 case O (O_XOR, SW): /* xor.w */
2233 /* Fetch rd and ea. */
2234 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2235 goto end;
2236 res = rd ^ ea;
2237 goto log16;
2238
2239 case O (O_XOR, SL): /* xor.l */
2240 /* Fetch rd and ea. */
2241 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2242 goto end;
2243 res = rd ^ ea;
2244 goto log32;
2245
2246 case O (O_MOV, SB):
2247 if (fetch (sd, &code->src, &res))
2248 goto end;
2249 if (store (sd, &code->dst, res))
2250 goto end;
2251 goto just_flags_log8;
2252 case O (O_MOV, SW):
2253 if (fetch (sd, &code->src, &res))
2254 goto end;
2255 if (store (sd, &code->dst, res))
2256 goto end;
2257 goto just_flags_log16;
2258 case O (O_MOV, SL):
2259 if (fetch (sd, &code->src, &res))
2260 goto end;
2261 if (store (sd, &code->dst, res))
2262 goto end;
2263 goto just_flags_log32;
2264
9f70f8ec 2265 case O (O_MOVMD, SB): /* movmd.b */
dc5c3759
MS		 2266 ea = GET_W_REG (4);
2267 if (ea == 0)
2268 ea = 0x10000;
2269
2270 while (ea--)
2271 {
2272 rd = GET_MEMORY_B (GET_L_REG (5));
2273 SET_MEMORY_B (GET_L_REG (6), rd);
2274 SET_L_REG (5, GET_L_REG (5) + 1);
2275 SET_L_REG (6, GET_L_REG (6) + 1);
2276 SET_W_REG (4, ea);
2277 }
2278 goto next;
2279
9f70f8ec 2280 case O (O_MOVMD, SW): /* movmd.w */
dc5c3759
MS		 2281 ea = GET_W_REG (4);
2282 if (ea == 0)
2283 ea = 0x10000;
2284
2285 while (ea--)
2286 {
2287 rd = GET_MEMORY_W (GET_L_REG (5));
2288 SET_MEMORY_W (GET_L_REG (6), rd);
2289 SET_L_REG (5, GET_L_REG (5) + 2);
2290 SET_L_REG (6, GET_L_REG (6) + 2);
2291 SET_W_REG (4, ea);
2292 }
2293 goto next;
2294
9f70f8ec 2295 case O (O_MOVMD, SL): /* movmd.l */
dc5c3759
MS		 2296 ea = GET_W_REG (4);
2297 if (ea == 0)
2298 ea = 0x10000;
2299
2300 while (ea--)
2301 {
2302 rd = GET_MEMORY_L (GET_L_REG (5));
2303 SET_MEMORY_L (GET_L_REG (6), rd);
2304 SET_L_REG (5, GET_L_REG (5) + 4);
2305 SET_L_REG (6, GET_L_REG (6) + 4);
2306 SET_W_REG (4, ea);
2307 }
2308 goto next;
2309
2310 case O (O_MOVSD, SB): /* movsd.b */
2311 /* This instruction implements strncpy, with a conditional branch.
2312 r4 contains n, r5 contains src, and r6 contains dst.
2313 The 16-bit displacement operand is added to the pc
2314 if and only if the end of string is reached before
2315 n bytes are transferred. */
2316
2317 ea = GET_L_REG (4) & 0xffff;
2318 if (ea == 0)
2319 ea = 0x10000;
2320
2321 while (ea--)
2322 {
2323 rd = GET_MEMORY_B (GET_L_REG (5));
2324 SET_MEMORY_B (GET_L_REG (6), rd);
2325 SET_L_REG (5, GET_L_REG (5) + 1);
2326 SET_L_REG (6, GET_L_REG (6) + 1);
2327 SET_W_REG (4, ea);
2328 if (rd == 0)
2329 goto condtrue;
2330 }
2331 goto next;
2332
2333 case O (O_EEPMOV, SB): /* eepmov.b */
2334 case O (O_EEPMOV, SW): /* eepmov.w */
2335 if (h8300hmode || h8300smode)
2336 {
2337 register unsigned char *_src, *_dst;
2338 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
2339 ? h8_get_reg (sd, R4_REGNUM) & 0xffff
2340 : h8_get_reg (sd, R4_REGNUM) & 0xff);
2341
2342 _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
2343 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
2344 : h8_get_eightbit_buf (sd) +
2345 (h8_get_reg (sd, R5_REGNUM) & 0xff));
2346 if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
2347 {
2348 if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2349 goto illegal;
2350 }
2351 _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
2352 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
2353 : h8_get_eightbit_buf (sd) +
2354 (h8_get_reg (sd, R6_REGNUM) & 0xff));
2355
2356 if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
2357 {
2358 if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2359 goto illegal;
2360 }
2361 memcpy (_dst, _src, count);
2362
2363 h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
2364 h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
2365 h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
2366 ((code->opcode == O (O_EEPMOV, SW))
2367 ? (~0xffff) : (~0xff)));
2368 cycles += 2 * count;
2369 goto next;
2370 }
2371 goto illegal;
2372
2373 case O (O_ADDS, SL): /* adds (.l) */
2374 /* FIXME fetch.
2375 * This insn only uses register operands, but still
2376 * it would be cleaner to use fetch and store... */
2377 SET_L_REG (code->dst.reg,
2378 GET_L_REG (code->dst.reg)
2379 + code->src.literal);
2380
2381 goto next;
2382
2383 case O (O_SUBS, SL): /* subs (.l) */
2384 /* FIXME fetch.
2385 * This insn only uses register operands, but still
2386 * it would be cleaner to use fetch and store... */
2387 SET_L_REG (code->dst.reg,
2388 GET_L_REG (code->dst.reg)
2389 - code->src.literal);
2390 goto next;
2391
2392 case O (O_CMP, SB): /* cmp.b */
2393 if (fetch (sd, &code->dst, &rd))
2394 goto end;
2395 if (fetch (sd, &code->src, &ea))
2396 goto end;
2397 ea = -ea;
2398 res = rd + ea;
2399 goto just_flags_alu8;
2400
2401 case O (O_CMP, SW): /* cmp.w */
2402 if (fetch (sd, &code->dst, &rd))
2403 goto end;
2404 if (fetch (sd, &code->src, &ea))
2405 goto end;
2406 ea = -ea;
2407 res = rd + ea;
2408 goto just_flags_alu16;
2409
2410 case O (O_CMP, SL): /* cmp.l */
2411 if (fetch (sd, &code->dst, &rd))
2412 goto end;
2413 if (fetch (sd, &code->src, &ea))
2414 goto end;
2415 ea = -ea;
2416 res = rd + ea;
2417 goto just_flags_alu32;
2418
2419 case O (O_DEC, SB): /* dec.b */
2420 /* FIXME fetch.
2421 * This insn only uses register operands, but still
2422 * it would be cleaner to use fetch and store... */
2423 rd = GET_B_REG (code->src.reg);
2424 ea = -1;
2425 res = rd + ea;
2426 SET_B_REG (code->src.reg, res);
2427 goto just_flags_inc8;
2428
2429 case O (O_DEC, SW): /* dec.w */
2430 /* FIXME fetch.
2431 * This insn only uses register operands, but still
2432 * it would be cleaner to use fetch and store... */
2433 rd = GET_W_REG (code->dst.reg);
2434 ea = -code->src.literal;
2435 res = rd + ea;
2436 SET_W_REG (code->dst.reg, res);
2437 goto just_flags_inc16;
2438
2439 case O (O_DEC, SL): /* dec.l */
2440 /* FIXME fetch.
2441 * This insn only uses register operands, but still
2442 * it would be cleaner to use fetch and store... */
2443 rd = GET_L_REG (code->dst.reg);
2444 ea = -code->src.literal;
2445 res = rd + ea;
2446 SET_L_REG (code->dst.reg, res);
2447 goto just_flags_inc32;
2448
2449 case O (O_INC, SB): /* inc.b */
2450 /* FIXME fetch.
2451 * This insn only uses register operands, but still
2452 * it would be cleaner to use fetch and store... */
2453 rd = GET_B_REG (code->src.reg);
2454 ea = 1;
2455 res = rd + ea;
2456 SET_B_REG (code->src.reg, res);
2457 goto just_flags_inc8;
2458
2459 case O (O_INC, SW): /* inc.w */
2460 /* FIXME fetch.
2461 * This insn only uses register operands, but still
2462 * it would be cleaner to use fetch and store... */
2463 rd = GET_W_REG (code->dst.reg);
2464 ea = code->src.literal;
2465 res = rd + ea;
2466 SET_W_REG (code->dst.reg, res);
2467 goto just_flags_inc16;
2468
2469 case O (O_INC, SL): /* inc.l */
2470 /* FIXME fetch.
2471 * This insn only uses register operands, but still
2472 * it would be cleaner to use fetch and store... */
2473 rd = GET_L_REG (code->dst.reg);
2474 ea = code->src.literal;
2475 res = rd + ea;
2476 SET_L_REG (code->dst.reg, res);
2477 goto just_flags_inc32;
2478
2479 case O (O_LDC, SB): /* ldc.b */
2480 if (fetch (sd, &code->src, &res))
2481 goto end;
2482 goto setc;
2483
2484 case O (O_LDC, SW): /* ldc.w */
2485 if (fetch (sd, &code->src, &res))
2486 goto end;
2487
2488 /* Word operand, value from MSB, must be shifted. */
2489 res >>= 8;
2490 goto setc;
2491
2492 case O (O_LDC, SL): /* ldc.l */
2493 if (fetch (sd, &code->src, &res))
2494 goto end;
2495 switch (code->dst.type) {
2496 case X (OP_SBR, SL):
2497 h8_set_sbr (sd, res);
2498 break;
2499 case X (OP_VBR, SL):
2500 h8_set_vbr (sd, res);
2501 break;
2502 default:
2503 goto illegal;
2504 }
2505 goto next;
2506
2507 case O (O_STC, SW): /* stc.w */
2508 case O (O_STC, SB): /* stc.b */
2509 if (code->src.type == X (OP_CCR, SB))
2510 {
2511 BUILDSR (sd);
2512 res = h8_get_ccr (sd);
2513 }
2514 else if (code->src.type == X (OP_EXR, SB) && h8300smode)
2515 {
2516 if (h8300smode)
2517 h8_set_exr (sd, (trace << 7) | intMask);
2518 res = h8_get_exr (sd);
2519 }
2520 else
2521 goto illegal;
2522
2523 /* Word operand, value to MSB, must be shifted. */
2524 if (code->opcode == X (O_STC, SW))
2525 res <<= 8;
2526 if (store (sd, &code->dst, res))
2527 goto end;
2528 goto next;
2529 case O (O_STC, SL): /* stc.l */
2530 switch (code->src.type) {
2531 case X (OP_SBR, SL):
2532 res = h8_get_sbr (sd);
2533 break;
2534 case X (OP_VBR, SL):
2535 res = h8_get_vbr (sd);
2536 break;
2537 default:
2538 goto illegal;
2539 }
2540 if (store (sd, &code->dst, res))
2541 goto end;
2542 goto next;
2543
2544 case O (O_ANDC, SB): /* andc.b */
2545 if (code->dst.type == X (OP_CCR, SB))
2546 {
2547 BUILDSR (sd);
2548 rd = h8_get_ccr (sd);
2549 }
2550 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2551 {
2552 if (h8300smode)
2553 h8_set_exr (sd, (trace << 7) | intMask);
d6fd015d 2554 rd = h8_get_exr (sd);
dc5c3759
MS		 2555 }
2556 else
2557 goto illegal;
2558 ea = code->src.literal;
2559 res = rd & ea;
2560 goto setc;
2561
2562 case O (O_ORC, SB): /* orc.b */
2563 if (code->dst.type == X (OP_CCR, SB))
2564 {
2565 BUILDSR (sd);
2566 rd = h8_get_ccr (sd);
2567 }
2568 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2569 {
2570 if (h8300smode)
2571 h8_set_exr (sd, (trace << 7) | intMask);
2572 rd = h8_get_exr (sd);
2573 }
2574 else
2575 goto illegal;
2576 ea = code->src.literal;
2577 res = rd | ea;
2578 goto setc;
2579
2580 case O (O_XORC, SB): /* xorc.b */
2581 if (code->dst.type == X (OP_CCR, SB))
2582 {
2583 BUILDSR (sd);
2584 rd = h8_get_ccr (sd);
2585 }
2586 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2587 {
2588 if (h8300smode)
2589 h8_set_exr (sd, (trace << 7) | intMask);
2590 rd = h8_get_exr (sd);
2591 }
2592 else
2593 goto illegal;
2594 ea = code->src.literal;
2595 res = rd ^ ea;
2596 goto setc;
2597
2598 case O (O_BRAS, SB): /* bra/s */
2599 /* This is basically an ordinary branch, with a delay slot. */
2600 if (fetch (sd, &code->src, &res))
2601 goto end;
2602
2603 if ((res & 1) == 0)
2604 goto illegal;
2605
2606 res -= 1;
2607
2608 /* Execution continues at next instruction, but
2609 delayed_branch is set up for next cycle. */
2610 h8_set_delayed_branch (sd, code->next_pc + res);
2611 pc = code->next_pc;
2612 goto end;
2613
2614 case O (O_BRAB, SB): /* bra rd.b */
2615 case O (O_BRAW, SW): /* bra rd.w */
2616 case O (O_BRAL, SL): /* bra erd.l */
2617 if (fetch (sd, &code->src, &rd))
2618 goto end;
2619 switch (OP_SIZE (code->opcode)) {
2620 case SB: rd &= 0xff; break;
2621 case SW: rd &= 0xffff; break;
2622 case SL: rd &= 0xffffffff; break;
2623 }
2624 pc = code->next_pc + rd;
2625 goto end;
2626
2627 case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
2628 case O (O_BRABS, SB): /* bra/bs, branch if bit set */
2629 case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
2630 case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
2631 if (fetch (sd, &code->dst, &rd) ||
2632 fetch (sd, &code->src, &bit))
2633 goto end;
2634
2635 if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
2636 code->opcode == O (O_BSRBC, SB)) /* call if clear */
2637 {
2638 if ((rd & (1 << bit))) /* no branch */
2639 goto next;
2640 }
2641 else /* branch/call if set */
2642 {
2643 if (!(rd & (1 << bit))) /* no branch */
2644 goto next;
2645 }
2646
2647 if (fetch (sd, &code->op3, &res)) /* branch */
2648 goto end;
2649 pc = code->next_pc + res;
2650
2651 if (code->opcode == O (O_BRABC, SB) ||
2652 code->opcode == O (O_BRABS, SB)) /* branch */
2653 goto end;
2654 else /* call */
2655 goto call;
2656
2657 case O (O_BRA, SN):
2658 case O (O_BRA, SL):
2659 case O (O_BRA, SW):
2660 case O (O_BRA, SB): /* bra, branch always */
2661 if (1)
2662 goto condtrue;
2663 goto next;
2664
2665 case O (O_BRN, SB): /* brn, ;-/ branch never? */
2666 if (0)
2667 goto condtrue;
2668 goto next;
2669
2670 case O (O_BHI, SB): /* bhi */
2671 if ((C || Z) == 0)
2672 goto condtrue;
2673 goto next;
2674
2675
2676 case O (O_BLS, SB): /* bls */
2677 if ((C || Z))
2678 goto condtrue;
2679 goto next;
2680
2681 case O (O_BCS, SB): /* bcs, branch if carry set */
2682 if ((C == 1))
2683 goto condtrue;
2684 goto next;
2685
2686 case O (O_BCC, SB): /* bcc, branch if carry clear */
2687 if ((C == 0))
2688 goto condtrue;
2689 goto next;
2690
2691 case O (O_BEQ, SB): /* beq, branch if zero set */
2692 if (Z)
2693 goto condtrue;
2694 goto next;
2695 case O (O_BGT, SB): /* bgt */
2696 if (((Z || (N ^ V)) == 0))
2697 goto condtrue;
2698 goto next;
2699
2700 case O (O_BLE, SB): /* ble */
2701 if (((Z || (N ^ V)) == 1))
2702 goto condtrue;
2703 goto next;
2704
2705 case O (O_BGE, SB): /* bge */
2706 if ((N ^ V) == 0)
2707 goto condtrue;
2708 goto next;
2709 case O (O_BLT, SB): /* blt */
2710 if ((N ^ V))
2711 goto condtrue;
2712 goto next;
2713 case O (O_BMI, SB): /* bmi */
2714 if ((N))
2715 goto condtrue;
2716 goto next;
2717 case O (O_BNE, SB): /* bne, branch if zero clear */
2718 if ((Z == 0))
2719 goto condtrue;
2720 goto next;
2721
2722 case O (O_BPL, SB): /* bpl */
2723 if (N == 0)
2724 goto condtrue;
2725 goto next;
2726 case O (O_BVC, SB): /* bvc */
2727 if ((V == 0))
2728 goto condtrue;
2729 goto next;
2730 case O (O_BVS, SB): /* bvs */
2731 if ((V == 1))
2732 goto condtrue;
2733 goto next;
2734
2735 /* Trap for Command Line setup. */
2736 case O (O_SYS_CMDLINE, SB):
2737 {
2738 int i = 0; /* Loop counter. */
2739 int j = 0; /* Loop counter. */
2740 int ind_arg_len = 0; /* Length of each argument. */
2741 int no_of_args = 0; /* The no. or cmdline args. */
2742 int current_location = 0; /* Location of string. */
2743 int old_sp = 0; /* The Initial Stack Pointer. */
2744 int no_of_slots = 0; /* No. of slots required on the stack
2745 for storing cmdline args. */
2746 int sp_move = 0; /* No. of locations by which the stack needs
2747 to grow. */
2748 int new_sp = 0; /* The final stack pointer location passed
2749 back. */
2750 int *argv_ptrs; /* Pointers of argv strings to be stored. */
2751 int argv_ptrs_location = 0; /* Location of pointers to cmdline
2752 args on the stack. */
2753 int char_ptr_size = 0; /* Size of a character pointer on
2754 target machine. */
2755 int addr_cmdline = 0; /* Memory location where cmdline has
2756 to be stored. */
2757 int size_cmdline = 0; /* Size of cmdline. */
2758
2759 /* Set the address of 256 free locations where command line is
2760 stored. */
2761 addr_cmdline = cmdline_location();
2762 h8_set_reg (sd, 0, addr_cmdline);
2763
2764 /* Counting the no. of commandline arguments. */
2765 for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
2766 continue;
2767
2768 /* No. of arguments in the command line. */
2769 no_of_args = i;
2770
2771 /* Current location is just a temporary variable,which we are
2772 setting to the point to the start of our commandline string. */
2773 current_location = addr_cmdline;
2774
2775 /* Allocating space for storing pointers of the command line
2776 arguments. */
2777 argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
2778
2779 /* Setting char_ptr_size to the sizeof (char *) on the different
2780 architectures. */
59768597 2781 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
dc5c3759
MS		 2782 {
2783 char_ptr_size = 4;
2784 }
2785 else
2786 {
2787 char_ptr_size = 2;
2788 }
2789
2790 for (i = 0; i < no_of_args; i++)
2791 {
2792 ind_arg_len = 0;
2793
2794 /* The size of the commandline argument. */
917c78f9 2795 ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
dc5c3759
MS		 2796
2797 /* The total size of the command line string. */
2798 size_cmdline += ind_arg_len;
2799
2800 /* As we have only 256 bytes, we need to provide a graceful
2801 exit. Anyways, a program using command line arguments
2802 where we cannot store all the command line arguments
2803 given may behave unpredictably. */
2804 if (size_cmdline >= 256)
2805 {
2806 h8_set_reg (sd, 0, 0);
2807 goto next;
2808 }
2809 else
2810 {
2811 /* current_location points to the memory where the next
2812 commandline argument is stored. */
2813 argv_ptrs[i] = current_location;
2814 for (j = 0; j < ind_arg_len; j++)
2815 {
2816 SET_MEMORY_B ((current_location +
2817 (sizeof (char) * j)),
2818 *(h8_get_cmdline_arg (sd, i) +
2819 sizeof (char) * j));
2820 }
2821
2822 /* Setting current_location to the starting of next
2823 argument. */
2824 current_location += ind_arg_len;
2825 }
2826 }
2827
2828 /* This is the original position of the stack pointer. */
2829 old_sp = h8_get_reg (sd, SP_REGNUM);
2830
2831 /* We need space from the stack to store the pointers to argvs. */
2832 /* As we will infringe on the stack, we need to shift the stack
2833 pointer so that the data is not overwritten. We calculate how
2834 much space is required. */
2835 sp_move = (no_of_args) * (char_ptr_size);
2836
2837 /* The final position of stack pointer, we have thus taken some
2838 space from the stack. */
2839 new_sp = old_sp - sp_move;
2840
2841 /* Temporary variable holding value where the argv pointers need
2842 to be stored. */
2843 argv_ptrs_location = new_sp;
2844
2845 /* The argv pointers are stored at sequential locations. As per
2846 the H8300 ABI. */
2847 for (i = 0; i < no_of_args; i++)
2848 {
2849 /* Saving the argv pointer. */
59768597 2850 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
dc5c3759
MS		 2851 {
2852 SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
2853 }
2854 else
2855 {
2856 SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
2857 }
2858
2859 /* The next location where the pointer to the next argv
2860 string has to be stored. */
2861 argv_ptrs_location += char_ptr_size;
2862 }
2863
2864 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2865 pointers. */
59768597 2866 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
dc5c3759
MS		 2867 {
2868 SET_MEMORY_L (old_sp, 0x0);
2869 }
2870 else
2871 {
2872 SET_MEMORY_W (old_sp, 0x0);
2873 }
2874
2875 /* Freeing allocated memory. */
2876 free (argv_ptrs);
2877 for (i = 0; i <= no_of_args; i++)
2878 {
2879 free (h8_get_cmdline_arg (sd, i));
2880 }
2881 free (h8_get_command_line (sd));
2882
2883 /* The no. of argv arguments are returned in Reg 0. */
2884 h8_set_reg (sd, 0, no_of_args);
2885 /* The Pointer to argv in Register 1. */
2886 h8_set_reg (sd, 1, new_sp);
2887 /* Setting the stack pointer to the new value. */
2888 h8_set_reg (sd, SP_REGNUM, new_sp);
2889 }
2890 goto next;
2891
2892 /* System call processing starts. */
2893 case O (O_SYS_OPEN, SB):
2894 {
2895 int len = 0; /* Length of filename. */
2896 char *filename; /* Filename would go here. */
2897 char temp_char; /* Temporary character */
2898 int mode = 0; /* Mode bits for the file. */
2899 int open_return; /* Return value of open, file descriptor. */
2900 int i; /* Loop counter */
2901 int filename_ptr; /* Pointer to filename in cpu memory. */
2902
2903 /* Setting filename_ptr to first argument of open, */
2904 /* and trying to get mode. */
59768597 2905 if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
dc5c3759
MS		 2906 {
2907 filename_ptr = GET_L_REG (0);
2908 mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
2909 }
2910 else
2911 {
2912 filename_ptr = GET_W_REG (0);
2913 mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
2914 }
2915
2916 /* Trying to find the length of the filename. */
2917 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2918
2919 len = 1;
2920 while (temp_char != '\0')
2921 {
2922 temp_char = GET_MEMORY_B (filename_ptr + len);
2923 len++;
2924 }
2925
2926 /* Allocating space for the filename. */
2927 filename = (char *) malloc (sizeof (char) * len);
2928
2929 /* String copying the filename from memory. */
2930 for (i = 0; i < len; i++)
2931 {
2932 temp_char = GET_MEMORY_B (filename_ptr + i);
2933 filename[i] = temp_char;
2934 }
2935
2936 /* Callback to open and return the file descriptor. */
2937 open_return = sim_callback->open (sim_callback, filename, mode);
2938
2939 /* Return value in register 0. */
2940 h8_set_reg (sd, 0, open_return);
2941
2942 /* Freeing memory used for filename. */
2943 free (filename);
2944 }
2945 goto next;
2946
2947 case O (O_SYS_READ, SB):
2948 {
2949 char *char_ptr; /* Where characters read would be stored. */
2950 int fd; /* File descriptor */
2951 int buf_size; /* BUF_SIZE parameter in read. */
2952 int i = 0; /* Temporary Loop counter */
2953 int read_return = 0; /* Return value from callback to
2954 read. */
2955
59768597
SA		 2956 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2957 buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
dc5c3759
MS		 2958
2959 char_ptr = (char *) malloc (sizeof (char) * buf_size);
2960
2961 /* Callback to read and return the no. of characters read. */
2962 read_return =
2963 sim_callback->read (sim_callback, fd, char_ptr, buf_size);
2964
2965 /* The characters read are stored in cpu memory. */
2966 for (i = 0; i < buf_size; i++)
2967 {
2968 SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
2969 *(char_ptr + (sizeof (char) * i)));
2970 }
2971
2972 /* Return value in Register 0. */
2973 h8_set_reg (sd, 0, read_return);
2974
2975 /* Freeing memory used as buffer. */
2976 free (char_ptr);
2977 }
2978 goto next;
2979
2980 case O (O_SYS_WRITE, SB):
2981 {
2982 int fd; /* File descriptor */
2983 char temp_char; /* Temporary character */
2984 int len; /* Length of write, Parameter II to write. */
2985 int char_ptr; /* Character Pointer, Parameter I of write. */
2986 char *ptr; /* Where characters to be written are stored.
2987 */
2988 int write_return; /* Return value from callback to write. */
2989 int i = 0; /* Loop counter */
2990
59768597
SA		 2991 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2992 char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2993 len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
dc5c3759
MS		 2994
2995 /* Allocating space for the characters to be written. */
2996 ptr = (char *) malloc (sizeof (char) * len);
2997
2998 /* Fetching the characters from cpu memory. */
2999 for (i = 0; i < len; i++)
3000 {
3001 temp_char = GET_MEMORY_B (char_ptr + i);
3002 ptr[i] = temp_char;
3003 }
3004
3005 /* Callback write and return the no. of characters written. */
3006 write_return = sim_callback->write (sim_callback, fd, ptr, len);
3007
3008 /* Return value in Register 0. */
3009 h8_set_reg (sd, 0, write_return);
3010
3011 /* Freeing memory used as buffer. */
3012 free (ptr);
3013 }
3014 goto next;
3015
3016 case O (O_SYS_LSEEK, SB):
3017 {
3018 int fd; /* File descriptor */
3019 int offset; /* Offset */
3020 int origin; /* Origin */
3021 int lseek_return; /* Return value from callback to lseek. */
3022
59768597
SA		 3023 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3024 offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3025 origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
c906108c 3026
dc5c3759
MS		 3027 /* Callback lseek and return offset. */
3028 lseek_return =
3029 sim_callback->lseek (sim_callback, fd, offset, origin);
3b02cf92 3030
dc5c3759
MS		 3031 /* Return value in register 0. */
3032 h8_set_reg (sd, 0, lseek_return);
3033 }
3034 goto next;
c906108c 3035
dc5c3759
MS		 3036 case O (O_SYS_CLOSE, SB):
3037 {
3038 int fd; /* File descriptor */
3039 int close_return; /* Return value from callback to close. */
c906108c 3040
59768597 3041 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
c906108c 3042
dc5c3759
MS		 3043 /* Callback close and return. */
3044 close_return = sim_callback->close (sim_callback, fd);
c906108c 3045
dc5c3759
MS		 3046 /* Return value in register 0. */
3047 h8_set_reg (sd, 0, close_return);
3048 }
3049 goto next;
c906108c 3050
dc5c3759
MS		 3051 case O (O_SYS_FSTAT, SB):
3052 {
3053 int fd; /* File descriptor */
3054 struct stat stat_rec; /* Stat record */
3055 int fstat_return; /* Return value from callback to stat. */
3056 int stat_ptr; /* Pointer to stat record. */
3057 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
c906108c 3058
59768597 3059 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
c906108c 3060
dc5c3759 3061 /* Setting stat_ptr to second argument of stat. */
59768597 3062 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
c906108c 3063
dc5c3759 3064 /* Callback stat and return. */
2d7bb758
JB		 3065 fstat_return = sim_callback->to_fstat (sim_callback, fd,
3066 &stat_rec);
c906108c 3067
dc5c3759
MS		 3068 /* Have stat_ptr point to starting of stat_rec. */
3069 temp_stat_ptr = (char *) (&stat_rec);
c906108c 3070
dc5c3759
MS		 3071 /* Setting up the stat structure returned. */
3072 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3073 stat_ptr += 2;
3074 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3075 stat_ptr += 2;
3076 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3077 stat_ptr += 4;
3078 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3079 stat_ptr += 2;
3080 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3081 stat_ptr += 2;
3082 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3083 stat_ptr += 2;
3084 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3085 stat_ptr += 2;
3086 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3087 stat_ptr += 4;
3088 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3089 stat_ptr += 8;
3090 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3091 stat_ptr += 8;
3092 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
c906108c 3093
dc5c3759
MS		 3094 /* Return value in register 0. */
3095 h8_set_reg (sd, 0, fstat_return);
3096 }
3097 goto next;
c906108c 3098
dc5c3759
MS		 3099 case O (O_SYS_STAT, SB):
3100 {
3101 int len = 0; /* Length of filename. */
3102 char *filename; /* Filename would go here. */
3103 char temp_char; /* Temporary character */
3104 int filename_ptr; /* Pointer to filename in cpu memory. */
3105 struct stat stat_rec; /* Stat record */
3106 int stat_return; /* Return value from callback to stat */
3107 int stat_ptr; /* Pointer to stat record. */
3108 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3109 int i = 0; /* Loop Counter */
c906108c 3110
dc5c3759 3111 /* Setting filename_ptr to first argument of open. */
59768597 3112 filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
c906108c 3113
dc5c3759
MS		 3114 /* Trying to find the length of the filename. */
3115 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
c906108c 3116
dc5c3759
MS		 3117 len = 1;
3118 while (temp_char != '\0')
3119 {
3120 temp_char = GET_MEMORY_B (filename_ptr + len);
3121 len++;
3122 }
d0fe2f7e 3123
dc5c3759
MS		 3124 /* Allocating space for the filename. */
3125 filename = (char *) malloc (sizeof (char) * len);
c3f4437e 3126
dc5c3759
MS		 3127 /* String copying the filename from memory. */
3128 for (i = 0; i < len; i++)
3129 {
3130 temp_char = GET_MEMORY_B (filename_ptr + i);
3131 filename[i] = temp_char;
3132 }
c906108c 3133
dc5c3759
MS		 3134 /* Setting stat_ptr to second argument of stat. */
3135 /* stat_ptr = h8_get_reg (sd, 1); */
59768597 3136 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
c906108c 3137
dc5c3759
MS		 3138 /* Callback stat and return. */
3139 stat_return =
2d7bb758 3140 sim_callback->to_stat (sim_callback, filename, &stat_rec);
c906108c 3141
dc5c3759
MS		 3142 /* Have stat_ptr point to starting of stat_rec. */
3143 temp_stat_ptr = (char *) (&stat_rec);
3144
3145 /* Freeing memory used for filename. */
3146 free (filename);
3147
3148 /* Setting up the stat structure returned. */
3149 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3150 stat_ptr += 2;
3151 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3152 stat_ptr += 2;
3153 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3154 stat_ptr += 4;
3155 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3156 stat_ptr += 2;
3157 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3158 stat_ptr += 2;
3159 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3160 stat_ptr += 2;
3161 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3162 stat_ptr += 2;
3163 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3164 stat_ptr += 4;
3165 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3166 stat_ptr += 8;
3167 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3168 stat_ptr += 8;
3169 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3170
3171 /* Return value in register 0. */
3172 h8_set_reg (sd, 0, stat_return);
3173 }
c906108c 3174 goto next;
dc5c3759 3175 /* End of system call processing. */
c906108c 3176
dc5c3759
MS		 3177 case O (O_NOT, SB): /* not.b */
3178 if (fetch2 (sd, &code->src, &rd))
3179 goto end;
3180 rd = ~rd;
3181 v = 0;
3182 goto shift8;
c906108c 3183
dc5c3759
MS		 3184 case O (O_NOT, SW): /* not.w */
3185 if (fetch2 (sd, &code->src, &rd))
3186 goto end;
3187 rd = ~rd;
3188 v = 0;
3189 goto shift16;
c906108c 3190
dc5c3759
MS		 3191 case O (O_NOT, SL): /* not.l */
3192 if (fetch2 (sd, &code->src, &rd))
3193 goto end;
3194 rd = ~rd;
3195 v = 0;
3196 goto shift32;
c906108c 3197
dc5c3759
MS		 3198 case O (O_SHLL, SB): /* shll.b */
3199 case O (O_SHLR, SB): /* shlr.b */
3200 if (fetch2 (sd, &code->dst, &rd))
3201 goto end;
c906108c 3202
55acb21b
MS		 3203 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3204 ea = 1; /* unary op */
3205 else /* binary op */
dc5c3759 3206 fetch (sd, &code->src, &ea);
c906108c 3207
dc5c3759
MS		 3208 if (code->opcode == O (O_SHLL, SB))
3209 {
3210 v = (ea > 8);
3211 c = rd & (0x80 >> (ea - 1));
3212 rd <<= ea;
3213 }
3214 else
3215 {
3216 v = 0;
3217 c = rd & (1 << (ea - 1));
3218 rd = (unsigned char) rd >> ea;
3219 }
3220 goto shift8;
c906108c 3221
dc5c3759
MS		 3222 case O (O_SHLL, SW): /* shll.w */
3223 case O (O_SHLR, SW): /* shlr.w */
3224 if (fetch2 (sd, &code->dst, &rd))
3225 goto end;
c906108c 3226
55acb21b
MS		 3227 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3228 ea = 1; /* unary op */
dc5c3759 3229 else
55acb21b 3230 fetch (sd, &code->src, &ea);
c906108c 3231
dc5c3759
MS		 3232 if (code->opcode == O (O_SHLL, SW))
3233 {
3234 v = (ea > 16);
3235 c = rd & (0x8000 >> (ea - 1));
3236 rd <<= ea;
3237 }
3238 else
3239 {
3240 v = 0;
3241 c = rd & (1 << (ea - 1));
3242 rd = (unsigned short) rd >> ea;
3243 }
3244 goto shift16;
c906108c 3245
dc5c3759
MS		 3246 case O (O_SHLL, SL): /* shll.l */
3247 case O (O_SHLR, SL): /* shlr.l */
3248 if (fetch2 (sd, &code->dst, &rd))
3249 goto end;
c906108c 3250
55acb21b
MS		 3251 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3252 ea = 1; /* unary op */
dc5c3759 3253 else
55acb21b 3254 fetch (sd, &code->src, &ea);
c906108c 3255
dc5c3759 3256 if (code->opcode == O (O_SHLL, SL))
c3f4437e 3257 {
dc5c3759
MS		 3258 v = (ea > 32);
3259 c = rd & (0x80000000 >> (ea - 1));
3260 rd <<= ea;
c3f4437e 3261 }
dc5c3759 3262 else
c3f4437e 3263 {
dc5c3759
MS		 3264 v = 0;
3265 c = rd & (1 << (ea - 1));
3266 rd = (unsigned int) rd >> ea;
c3f4437e 3267 }
dc5c3759
MS		 3268 goto shift32;
3269
3270 case O (O_SHAL, SB):
3271 case O (O_SHAR, SB):
3272 if (fetch2 (sd, &code->dst, &rd))
3273 goto end;
3274
3275 if (code->src.type == X (OP_IMM, SB))
3276 fetch (sd, &code->src, &ea);
c3f4437e 3277 else
dc5c3759 3278 ea = 1;
6147b1f6 3279
dc5c3759 3280 if (code->opcode == O (O_SHAL, SB))
c3f4437e 3281 {
dc5c3759
MS		 3282 c = rd & (0x80 >> (ea - 1));
3283 res = rd >> (7 - ea);
3284 v = ((res & 1) && !(res & 2))
3285 || (!(res & 1) && (res & 2));
3286 rd <<= ea;
c3f4437e 3287 }
dc5c3759 3288 else
c3f4437e 3289 {
dc5c3759
MS		 3290 c = rd & (1 << (ea - 1));
3291 v = 0;
3292 rd = ((signed char) rd) >> ea;
c3f4437e 3293 }
dc5c3759
MS		 3294 goto shift8;
3295
3296 case O (O_SHAL, SW):
3297 case O (O_SHAR, SW):
3298 if (fetch2 (sd, &code->dst, &rd))
3299 goto end;
3300
3301 if (code->src.type == X (OP_IMM, SW))
3302 fetch (sd, &code->src, &ea);
c3f4437e 3303 else
dc5c3759 3304 ea = 1;
c906108c 3305
dc5c3759 3306 if (code->opcode == O (O_SHAL, SW))
c3f4437e 3307 {
dc5c3759
MS		 3308 c = rd & (0x8000 >> (ea - 1));
3309 res = rd >> (15 - ea);
3310 v = ((res & 1) && !(res & 2))
3311 || (!(res & 1) && (res & 2));
3312 rd <<= ea;
c3f4437e 3313 }
dc5c3759 3314 else
c3f4437e 3315 {
dc5c3759
MS		 3316 c = rd & (1 << (ea - 1));
3317 v = 0;
3318 rd = ((signed short) rd) >> ea;
c3f4437e 3319 }
dc5c3759
MS		 3320 goto shift16;
3321
3322 case O (O_SHAL, SL):
3323 case O (O_SHAR, SL):
3324 if (fetch2 (sd, &code->dst, &rd))
3325 goto end;
3326
3327 if (code->src.type == X (OP_IMM, SL))
3328 fetch (sd, &code->src, &ea);
3329 else
3330 ea = 1;
c906108c 3331
dc5c3759 3332 if (code->opcode == O (O_SHAL, SL))
c3f4437e 3333 {
dc5c3759
MS		 3334 c = rd & (0x80000000 >> (ea - 1));
3335 res = rd >> (31 - ea);
3336 v = ((res & 1) && !(res & 2))
3337 || (!(res & 1) && (res & 2));
3338 rd <<= ea;
c3f4437e 3339 }
dc5c3759 3340 else
c3f4437e 3341 {
dc5c3759
MS		 3342 c = rd & (1 << (ea - 1));
3343 v = 0;
3344 rd = ((signed int) rd) >> ea;
c3f4437e 3345 }
dc5c3759 3346 goto shift32;
c906108c 3347
dc5c3759
MS		 3348 case O (O_ROTL, SB):
3349 case O (O_ROTR, SB):
3350 if (fetch2 (sd, &code->dst, &rd))
3351 goto end;
c906108c 3352
dc5c3759
MS		 3353 if (code->src.type == X (OP_IMM, SB))
3354 fetch (sd, &code->src, &ea);
3355 else
3356 ea = 1;
c906108c 3357
dc5c3759
MS		 3358 while (ea--)
3359 if (code->opcode == O (O_ROTL, SB))
3360 {
3361 c = rd & 0x80;
3362 rd <<= 1;
3363 if (c)
3364 rd |= 1;
3365 }
3366 else
3367 {
3368 c = rd & 1;
3369 rd = ((unsigned char) rd) >> 1;
3370 if (c)
3371 rd |= 0x80;
3372 }
c906108c 3373
dc5c3759
MS		 3374 v = 0;
3375 goto shift8;
c906108c 3376
dc5c3759
MS		 3377 case O (O_ROTL, SW):
3378 case O (O_ROTR, SW):
3379 if (fetch2 (sd, &code->dst, &rd))
3380 goto end;
c906108c 3381
dc5c3759
MS		 3382 if (code->src.type == X (OP_IMM, SW))
3383 fetch (sd, &code->src, &ea);
3384 else
3385 ea = 1;
c906108c 3386
dc5c3759
MS		 3387 while (ea--)
3388 if (code->opcode == O (O_ROTL, SW))
3389 {
3390 c = rd & 0x8000;
3391 rd <<= 1;
3392 if (c)
3393 rd |= 1;
3394 }
3395 else
3396 {
3397 c = rd & 1;
3398 rd = ((unsigned short) rd) >> 1;
3399 if (c)
3400 rd |= 0x8000;
3401 }
c906108c 3402
dc5c3759
MS		 3403 v = 0;
3404 goto shift16;
c906108c 3405
dc5c3759
MS		 3406 case O (O_ROTL, SL):
3407 case O (O_ROTR, SL):
3408 if (fetch2 (sd, &code->dst, &rd))
3409 goto end;
c906108c 3410
dc5c3759
MS		 3411 if (code->src.type == X (OP_IMM, SL))
3412 fetch (sd, &code->src, &ea);
3413 else
3414 ea = 1;
c906108c 3415
dc5c3759
MS		 3416 while (ea--)
3417 if (code->opcode == O (O_ROTL, SL))
3418 {
3419 c = rd & 0x80000000;
3420 rd <<= 1;
3421 if (c)
3422 rd |= 1;
3423 }
3424 else
3425 {
3426 c = rd & 1;
3427 rd = ((unsigned int) rd) >> 1;
3428 if (c)
3429 rd |= 0x80000000;
3430 }
c906108c 3431
dc5c3759
MS		 3432 v = 0;
3433 goto shift32;
c906108c 3434
dc5c3759
MS		 3435 case O (O_ROTXL, SB):
3436 case O (O_ROTXR, SB):
3437 if (fetch2 (sd, &code->dst, &rd))
3438 goto end;
d1360fb0 3439
dc5c3759
MS		 3440 if (code->src.type == X (OP_IMM, SB))
3441 fetch (sd, &code->src, &ea);
3442 else
3443 ea = 1;
d1360fb0 3444
dc5c3759
MS		 3445 while (ea--)
3446 if (code->opcode == O (O_ROTXL, SB))
3447 {
3448 res = rd & 0x80;
3449 rd <<= 1;
3450 if (C)
3451 rd |= 1;
3452 c = res;
3453 }
3454 else
3455 {
3456 res = rd & 1;
3457 rd = ((unsigned char) rd) >> 1;
3458 if (C)
3459 rd |= 0x80;
3460 c = res;
3461 }
d1360fb0 3462
dc5c3759
MS		 3463 v = 0;
3464 goto shift8;
d1360fb0 3465
dc5c3759
MS		 3466 case O (O_ROTXL, SW):
3467 case O (O_ROTXR, SW):
3468 if (fetch2 (sd, &code->dst, &rd))
3469 goto end;
d1360fb0 3470
dc5c3759
MS		 3471 if (code->src.type == X (OP_IMM, SW))
3472 fetch (sd, &code->src, &ea);
3473 else
3474 ea = 1;
d1360fb0 3475
dc5c3759
MS		 3476 while (ea--)
3477 if (code->opcode == O (O_ROTXL, SW))
d1360fb0 3478 {
dc5c3759
MS		 3479 res = rd & 0x8000;
3480 rd <<= 1;
3481 if (C)
3482 rd |= 1;
3483 c = res;
d1360fb0
V		 3484 }
3485 else
3486 {
dc5c3759
MS		 3487 res = rd & 1;
3488 rd = ((unsigned short) rd) >> 1;
3489 if (C)
3490 rd |= 0x8000;
3491 c = res;
d1360fb0
V		 3492 }
3493
dc5c3759
MS		 3494 v = 0;
3495 goto shift16;
d1360fb0 3496
dc5c3759
MS		 3497 case O (O_ROTXL, SL):
3498 case O (O_ROTXR, SL):
3499 if (fetch2 (sd, &code->dst, &rd))
3500 goto end;
d1360fb0 3501
dc5c3759
MS		 3502 if (code->src.type == X (OP_IMM, SL))
3503 fetch (sd, &code->src, &ea);
3504 else
3505 ea = 1;
d1360fb0 3506
dc5c3759
MS		 3507 while (ea--)
3508 if (code->opcode == O (O_ROTXL, SL))
3509 {
3510 res = rd & 0x80000000;
3511 rd <<= 1;
3512 if (C)
3513 rd |= 1;
3514 c = res;
3515 }
3516 else
3517 {
3518 res = rd & 1;
3519 rd = ((unsigned int) rd) >> 1;
3520 if (C)
3521 rd |= 0x80000000;
3522 c = res;
d1360fb0
V		 3523 }
3524
dc5c3759
MS		 3525 v = 0;
3526 goto shift32;
d1360fb0 3527
dc5c3759
MS		 3528 case O (O_JMP, SN):
3529 case O (O_JMP, SL):
3530 case O (O_JMP, SB): /* jmp */
3531 case O (O_JMP, SW):
9f70f8ec
MS		 3532 fetch (sd, &code->src, &pc);
3533 goto end;
d1360fb0 3534
dc5c3759
MS		 3535 case O (O_JSR, SN):
3536 case O (O_JSR, SL):
3537 case O (O_JSR, SB): /* jsr, jump to subroutine */
3538 case O (O_JSR, SW):
9f70f8ec
MS		 3539 if (fetch (sd, &code->src, &pc))
3540 goto end;
3541 call:
3542 tmp = h8_get_reg (sd, SP_REGNUM);
d1360fb0 3543
59768597 3544 if (h8300hmode && !h8300_normal_mode)
9f70f8ec
MS		 3545 {
3546 tmp -= 4;
3547 SET_MEMORY_L (tmp, code->next_pc);
3548 }
3549 else
3550 {
3551 tmp -= 2;
3552 SET_MEMORY_W (tmp, code->next_pc);
3553 }
3554 h8_set_reg (sd, SP_REGNUM, tmp);
d1360fb0 3555
9f70f8ec 3556 goto end;
dc5c3759
MS		 3557
3558 case O (O_BSR, SW):
3559 case O (O_BSR, SL):
3560 case O (O_BSR, SB): /* bsr, branch to subroutine */
3561 if (fetch (sd, &code->src, &res))
3562 goto end;
3563 pc = code->next_pc + res;
3564 goto call;
3565
9f70f8ec
MS		 3566 case O (O_RTE, SN): /* rte, return from exception */
3567 rte:
3568 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3569 tmp = h8_get_reg (sd, SP_REGNUM);
dc5c3759 3570
9f70f8ec
MS		 3571 if (h8300smode) /* pop exr */
3572 {
3573 h8_set_exr (sd, GET_MEMORY_L (tmp));
3574 tmp += 4;
3575 }
59768597 3576 if (h8300hmode && !h8300_normal_mode)
9f70f8ec
MS		 3577 {
3578 h8_set_ccr (sd, GET_MEMORY_L (tmp));
3579 tmp += 4;
3580 pc = GET_MEMORY_L (tmp);
3581 tmp += 4;
3582 }
3583 else
3584 {
3585 h8_set_ccr (sd, GET_MEMORY_W (tmp));
3586 tmp += 2;
3587 pc = GET_MEMORY_W (tmp);
3588 tmp += 2;
3589 }
dc5c3759 3590
9f70f8ec
MS		 3591 GETSR (sd);
3592 h8_set_reg (sd, SP_REGNUM, tmp);
3593 goto end;
d1360fb0 3594
9f70f8ec
MS		 3595 case O (O_RTS, SN): /* rts, return from subroutine */
3596 rts:
3597 tmp = h8_get_reg (sd, SP_REGNUM);
3598
59768597 3599 if (h8300hmode && !h8300_normal_mode)
9f70f8ec
MS		 3600 {
3601 pc = GET_MEMORY_L (tmp);
3602 tmp += 4;
3603 }
3604 else
3605 {
3606 pc = GET_MEMORY_W (tmp);
3607 tmp += 2;
3608 }
3609
3610 h8_set_reg (sd, SP_REGNUM, tmp);
3611 goto end;
d1360fb0 3612
dc5c3759
MS		 3613 case O (O_ILL, SB): /* illegal */
3614 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
3615 goto end;
3616
3617 case O (O_SLEEP, SN): /* sleep */
3618 /* Check for magic numbers in r1 and r2. */
3619 if ((h8_get_reg (sd, R1_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC1 &&
3620 (h8_get_reg (sd, R2_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC2 &&
3621 SIM_WIFEXITED (h8_get_reg (sd, 0)))
3622 {
3623 /* This trap comes from _exit, not from gdb. */
3624 sim_engine_set_run_state (sd, sim_exited,
3625 SIM_WEXITSTATUS (h8_get_reg (sd, 0)));
3626 }
e22fef83 3627#if 0
f408565c
MS		 3628 /* Unfortunately this won't really work, because
3629 when we take a breakpoint trap, R0 has a "random",
3630 user-defined value. Don't see any immediate solution. */
f0861129
MS		 3631 else if (SIM_WIFSTOPPED (h8_get_reg (sd, 0)))
3632 {
3633 /* Pass the stop signal up to gdb. */
3634 sim_engine_set_run_state (sd, sim_stopped,
3635 SIM_WSTOPSIG (h8_get_reg (sd, 0)));
3636 }
e22fef83 3637#endif
dc5c3759
MS		 3638 else
3639 {
3640 /* Treat it as a sigtrap. */
3641 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3642 }
3643 goto end;
bf174226 3644
9f70f8ec
MS		 3645 case O (O_TRAPA, SB): /* trapa */
3646 if (fetch (sd, &code->src, &res))
59768597
SA		 3647 goto end; /* res is vector number. */
3648
3649 tmp = h8_get_reg (sd, SP_REGNUM);
3650 if(h8300_normal_mode)
3651 {
3652 tmp -= 2;
3653 SET_MEMORY_W (tmp, code->next_pc);
3654 tmp -= 2;
3655 SET_MEMORY_W (tmp, h8_get_ccr (sd));
3656 }
3657 else
3658 {
3659 tmp -= 4;
3660 SET_MEMORY_L (tmp, code->next_pc);
3661 tmp -= 4;
3662 SET_MEMORY_L (tmp, h8_get_ccr (sd));
3663 }
3664 intMaskBit = 1;
3665 BUILDSR (sd);
3666
9f70f8ec
MS		 3667 if (h8300smode)
3668 {
3669 tmp -= 4;
3670 SET_MEMORY_L (tmp, h8_get_exr (sd));
3671 }
3672
3673 h8_set_reg (sd, SP_REGNUM, tmp);
3674
59768597
SA		 3675 if(h8300_normal_mode)
3676 pc = GET_MEMORY_L (0x10 + res * 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3677 else
3678 pc = GET_MEMORY_L (0x20 + res * 4);
9f70f8ec
MS		 3679 goto end;
3680
dc5c3759
MS		 3681 case O (O_BPT, SN):
3682 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3683 goto end;
bf174226 3684
dc5c3759
MS		 3685 case O (O_BSETEQ, SB):
3686 if (Z)
3687 goto bset;
3688 goto next;
bf174226 3689
dc5c3759
MS		 3690 case O (O_BSETNE, SB):
3691 if (!Z)
3692 goto bset;
3693 goto next;
bf174226 3694
dc5c3759
MS		 3695 case O (O_BCLREQ, SB):
3696 if (Z)
3697 goto bclr;
3698 goto next;
bf174226 3699
dc5c3759
MS		 3700 case O (O_BCLRNE, SB):
3701 if (!Z)
3702 goto bclr;
3703 goto next;
bf174226 3704
dc5c3759
MS		 3705 OBITOP (O_BNOT, 1, 1, ea ^= m); /* bnot */
3706 OBITOP (O_BTST, 1, 0, nz = ea & m); /* btst */
3707 bset:
3708 OBITOP (O_BSET, 1, 1, ea |= m); /* bset */
3709 bclr:
3710 OBITOP (O_BCLR, 1, 1, ea &= ~m); /* bclr */
3711 OBITOP (O_BLD, 1, 0, c = ea & m); /* bld */
3712 OBITOP (O_BILD, 1, 0, c = !(ea & m)); /* bild */
3713 OBITOP (O_BST, 1, 1, ea &= ~m;
3714 if (C) ea |= m); /* bst */
3715 OBITOP (O_BIST, 1, 1, ea &= ~m;
3716 if (!C) ea |= m); /* bist */
3717 OBITOP (O_BSTZ, 1, 1, ea &= ~m;
3718 if (Z) ea |= m); /* bstz */
3719 OBITOP (O_BISTZ, 1, 1, ea &= ~m;
3720 if (!Z) ea |= m); /* bistz */
3721 OBITOP (O_BAND, 1, 0, c = (ea & m) && C); /* band */
3722 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); /* biand */
3723 OBITOP (O_BOR, 1, 0, c = (ea & m) || C); /* bor */
3724 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); /* bior */
3725 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0)!= C); /* bxor */
3726 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); /* bixor */
3727
3728 case O (O_BFLD, SB): /* bfld */
3729 /* bitfield load */
3730 ea = 0;
3731 if (fetch (sd, &code->src, &bit))
3732 goto end;
bf174226 3733
dc5c3759
MS		 3734 if (bit != 0)
3735 {
3736 if (fetch (sd, &code->dst, &ea))
3737 goto end;
bf174226 3738
dc5c3759
MS		 3739 ea &= bit;
3740 while (!(bit & 1))
3741 {
3742 ea >>= 1;
3743 bit >>= 1;
3744 }
3745 }
3746 if (store (sd, &code->op3, ea))
3747 goto end;
bf174226 3748
c906108c
SS		 3749 goto next;
3750
dc5c3759
MS		 3751 case O(O_BFST, SB): /* bfst */
3752 /* bitfield store */
3753 /* NOTE: the imm8 value is in dst, and the ea value
3754 (which is actually the destination) is in op3.
3755 It has to be that way, to avoid breaking the assembler. */
bf174226 3756
dc5c3759
MS		 3757 if (fetch (sd, &code->dst, &bit)) /* imm8 */
3758 goto end;
3759 if (bit == 0) /* noop -- nothing to do. */
3760 goto next;
bf174226 3761
dc5c3759
MS		 3762 if (fetch (sd, &code->src, &rd)) /* reg8 src */
3763 goto end;
bf174226 3764
dc5c3759
MS		 3765 if (fetch2 (sd, &code->op3, &ea)) /* ea dst */
3766 goto end;
bf174226 3767
dc5c3759
MS		 3768 /* Left-shift the register data into position. */
3769 for (tmp = bit; !(tmp & 1); tmp >>= 1)
3770 rd <<= 1;
bf174226 3771
dc5c3759
MS		 3772 /* Combine it with the neighboring bits. */
3773 ea = (ea & ~bit) | (rd & bit);
bf174226 3774
dc5c3759
MS		 3775 /* Put it back. */
3776 if (store2 (sd, &code->op3, ea))
3777 goto end;
3778 goto next;
3779
3780 case O (O_CLRMAC, SN): /* clrmac */
3781 h8_set_mach (sd, 0);
3782 h8_set_macl (sd, 0);
3783 h8_set_macZ (sd, 1);
3784 h8_set_macV (sd, 0);
3785 h8_set_macN (sd, 0);
3786 goto next;
3787
3788 case O (O_STMAC, SL): /* stmac, 260 */
3789 switch (code->src.type) {
3790 case X (OP_MACH, SL):
3791 res = h8_get_mach (sd);
3792 if (res & 0x200) /* sign extend */
3793 res |= 0xfffffc00;
3794 break;
3795 case X (OP_MACL, SL):
3796 res = h8_get_macl (sd);
3797 break;
3798 default: goto illegal;
bf174226 3799 }
dc5c3759
MS		 3800 nz = !h8_get_macZ (sd);
3801 n = h8_get_macN (sd);
3802 v = h8_get_macV (sd);
3803
3804 if (store (sd, &code->dst, res))
3805 goto end;
3806
bf174226
V		 3807 goto next;
3808
dc5c3759
MS		 3809 case O (O_LDMAC, SL): /* ldmac, 179 */
3810 if (fetch (sd, &code->src, &rd))
3811 goto end;
bf174226 3812
dc5c3759
MS		 3813 switch (code->dst.type) {
3814 case X (OP_MACH, SL):
3815 rd &= 0x3ff; /* Truncate to 10 bits */
3816 h8_set_mach (sd, rd);
3817 break;
3818 case X (OP_MACL, SL):
3819 h8_set_macl (sd, rd);
3820 break;
3821 default: goto illegal;
3822 }
3823 h8_set_macV (sd, 0);
3824 goto next;
bf174226 3825
dc5c3759
MS		 3826 case O (O_MAC, SW):
3827 if (fetch (sd, &code->src, &rd) ||
3828 fetch (sd, &code->dst, &res))
3829 goto end;
bf174226 3830
dc5c3759
MS		 3831 /* Ye gods, this is non-portable!
3832 However, the existing mul/div code is similar. */
3833 res = SEXTSHORT (res) * SEXTSHORT (rd);
bf174226 3834
dc5c3759
MS		 3835 if (h8_get_macS (sd)) /* Saturating mode */
3836 {
3837 long long mac = h8_get_macl (sd);
bf174226 3838
dc5c3759
MS		 3839 if (mac & 0x80000000) /* sign extend */
3840 mac |= 0xffffffff00000000LL;
bf174226 3841
dc5c3759
MS		 3842 mac += res;
3843 if (mac > 0x7fffffff || mac < 0xffffffff80000000LL)
3844 h8_set_macV (sd, 1);
3845 h8_set_macZ (sd, (mac == 0));
3846 h8_set_macN (sd, (mac < 0));
3847 h8_set_macl (sd, (int) mac);
3848 }
3849 else /* "Less Saturating" mode */
3850 {
3851 long long mac = h8_get_mach (sd);
3852 mac <<= 32;
3853 mac += h8_get_macl (sd);
3854
3855 if (mac & 0x20000000000LL) /* sign extend */
3856 mac |= 0xfffffc0000000000LL;
3857
3858 mac += res;
3859 if (mac > 0x1ffffffffffLL ||
3860 mac < (long long) 0xfffffe0000000000LL)
3861 h8_set_macV (sd, 1);
3862 h8_set_macZ (sd, (mac == 0));
3863 h8_set_macN (sd, (mac < 0));
3864 h8_set_macl (sd, (int) mac);
3865 mac >>= 32;
3866 h8_set_mach (sd, (int) (mac & 0x3ff));
3867 }
bf174226
V		 3868 goto next;
3869
dc5c3759
MS		 3870 case O (O_MULS, SW): /* muls.w */
3871 if (fetch (sd, &code->src, &ea) ||
3872 fetch (sd, &code->dst, &rd))
3873 goto end;
bf174226 3874
e073c474 3875 ea = SEXTSHORT (ea);
dc5c3759
MS		 3876 res = SEXTSHORT (ea * SEXTSHORT (rd));
3877
3878 n = res & 0x8000;
3879 nz = res & 0xffff;
3880 if (store (sd, &code->dst, res))
3881 goto end;
bf174226 3882
bf174226
V		 3883 goto next;
3884
dc5c3759
MS		 3885 case O (O_MULS, SL): /* muls.l */
3886 if (fetch (sd, &code->src, &ea) ||
3887 fetch (sd, &code->dst, &rd))
3888 goto end;
bf174226 3889
dc5c3759 3890 res = ea * rd;
bf174226 3891
dc5c3759
MS		 3892 n = res & 0x80000000;
3893 nz = res & 0xffffffff;
3894 if (store (sd, &code->dst, res))
3895 goto end;
bf174226
V		 3896 goto next;
3897
dc5c3759
MS		 3898 case O (O_MULSU, SL): /* muls/u.l */
3899 if (fetch (sd, &code->src, &ea) ||
3900 fetch (sd, &code->dst, &rd))
3901 goto end;
bf174226 3902
dc5c3759
MS		 3903 /* Compute upper 32 bits of the 64-bit result. */
3904 res = (((long long) ea) * ((long long) rd)) >> 32;
bf174226 3905
dc5c3759
MS		 3906 n = res & 0x80000000;
3907 nz = res & 0xffffffff;
3908 if (store (sd, &code->dst, res))
3909 goto end;
3910 goto next;
bf174226 3911
dc5c3759
MS		 3912 case O (O_MULU, SW): /* mulu.w */
3913 if (fetch (sd, &code->src, &ea) ||
3914 fetch (sd, &code->dst, &rd))
3915 goto end;
bf174226 3916
dc5c3759
MS		 3917 res = UEXTSHORT ((UEXTSHORT (ea) * UEXTSHORT (rd)));
3918
3919 /* Don't set Z or N. */
3920 if (store (sd, &code->dst, res))
3921 goto end;
bf174226 3922
bf174226
V		 3923 goto next;
3924
dc5c3759
MS		 3925 case O (O_MULU, SL): /* mulu.l */
3926 if (fetch (sd, &code->src, &ea) ||
3927 fetch (sd, &code->dst, &rd))
3928 goto end;
bf174226 3929
dc5c3759 3930 res = ea * rd;
bf174226 3931
dc5c3759
MS		 3932 /* Don't set Z or N. */
3933 if (store (sd, &code->dst, res))
3934 goto end;
bf174226 3935
dc5c3759 3936 goto next;
bf174226 3937
dc5c3759
MS		 3938 case O (O_MULUU, SL): /* mulu/u.l */
3939 if (fetch (sd, &code->src, &ea) ||
3940 fetch (sd, &code->dst, &rd))
3941 goto end;
bf174226 3942
dc5c3759
MS		 3943 /* Compute upper 32 bits of the 64-bit result. */
3944 res = (((unsigned long long) (unsigned) ea) *
3945 ((unsigned long long) (unsigned) rd)) >> 32;
bf174226 3946
dc5c3759
MS		 3947 /* Don't set Z or N. */
3948 if (store (sd, &code->dst, res))
3949 goto end;
bf174226 3950
dc5c3759 3951 goto next;
bf174226 3952
dc5c3759
MS		 3953 case O (O_MULXS, SB): /* mulxs.b */
3954 if (fetch (sd, &code->src, &ea) ||
3955 fetch (sd, &code->dst, &rd))
3956 goto end;
bf174226 3957
e073c474 3958 ea = SEXTCHAR (ea);
dc5c3759
MS		 3959 res = ea * SEXTCHAR (rd);
3960
3961 n = res & 0x8000;
3962 nz = res & 0xffff;
3963 if (store (sd, &code->dst, res))
3964 goto end;
bf174226 3965
bf174226 3966 goto next;
bf174226 3967
dc5c3759
MS		 3968 case O (O_MULXS, SW): /* mulxs.w */
3969 if (fetch (sd, &code->src, &ea) ||
3970 fetch (sd, &code->dst, &rd))
c906108c
SS		 3971 goto end;
3972
e073c474 3973 ea = SEXTSHORT (ea);
dc5c3759 3974 res = ea * SEXTSHORT (rd & 0xffff);
c906108c 3975
dc5c3759
MS		 3976 n = res & 0x80000000;
3977 nz = res & 0xffffffff;
3978 if (store (sd, &code->dst, res))
3979 goto end;
3980
3981 goto next;
c906108c 3982
dc5c3759
MS		 3983 case O (O_MULXU, SB): /* mulxu.b */
3984 if (fetch (sd, &code->src, &ea) ||
3985 fetch (sd, &code->dst, &rd))
c906108c 3986 goto end;
c906108c 3987
dc5c3759 3988 res = UEXTCHAR (ea) * UEXTCHAR (rd);
c906108c 3989
dc5c3759
MS		 3990 if (store (sd, &code->dst, res))
3991 goto end;
c906108c 3992
dc5c3759 3993 goto next;
c906108c 3994
dc5c3759
MS		 3995 case O (O_MULXU, SW): /* mulxu.w */
3996 if (fetch (sd, &code->src, &ea) ||
3997 fetch (sd, &code->dst, &rd))
c906108c 3998 goto end;
c906108c 3999
dc5c3759 4000 res = UEXTSHORT (ea) * UEXTSHORT (rd);
c906108c 4001
dc5c3759
MS		 4002 if (store (sd, &code->dst, res))
4003 goto end;
4004
4005 goto next;
c906108c 4006
9f70f8ec
MS		 4007 case O (O_TAS, SB): /* tas (test and set) */
4008 if (!h8300sxmode) /* h8sx can use any register. */
4009 switch (code->src.reg)
4010 {
4011 case R0_REGNUM:
4012 case R1_REGNUM:
4013 case R4_REGNUM:
4014 case R5_REGNUM:
4015 break;
4016 default:
4017 goto illegal;
4018 }
4019
dc5c3759
MS		 4020 if (fetch (sd, &code->src, &res))
4021 goto end;
4022 if (store (sd, &code->src, res | 0x80))
4023 goto end;
4024
6147b1f6 4025 goto just_flags_log8;
c906108c 4026
dc5c3759
MS		 4027 case O (O_DIVU, SW): /* divu.w */
4028 if (fetch (sd, &code->src, &ea) ||
4029 fetch (sd, &code->dst, &rd))
4030 goto end;
c906108c 4031
dc5c3759
MS		 4032 n = ea & 0x8000;
4033 nz = ea & 0xffff;
4034 if (ea)
4035 res = (unsigned) (UEXTSHORT (rd) / UEXTSHORT (ea));
4036 else
4037 res = 0;
c906108c 4038
dc5c3759
MS		 4039 if (store (sd, &code->dst, res))
4040 goto end;
4041 goto next;
c906108c 4042
dc5c3759
MS		 4043 case O (O_DIVU, SL): /* divu.l */
4044 if (fetch (sd, &code->src, &ea) ||
4045 fetch (sd, &code->dst, &rd))
4046 goto end;
4047
4048 n = ea & 0x80000000;
4049 nz = ea & 0xffffffff;
4050 if (ea)
4051 res = (unsigned) rd / ea;
4052 else
4053 res = 0;
4054
4055 if (store (sd, &code->dst, res))
4056 goto end;
4057 goto next;
4058
4059 case O (O_DIVS, SW): /* divs.w */
4060 if (fetch (sd, &code->src, &ea) ||
4061 fetch (sd, &code->dst, &rd))
4062 goto end;
4063
dc5c3759
MS		 4064 if (ea)
4065 {
4066 res = SEXTSHORT (rd) / SEXTSHORT (ea);
4067 nz = 1;
4068 }
4069 else
4070 {
4071 res = 0;
4072 nz = 0;
4073 }
4074
4075 n = res & 0x8000;
4076 if (store (sd, &code->dst, res))
4077 goto end;
4078 goto next;
4079
4080 case O (O_DIVS, SL): /* divs.l */
4081 if (fetch (sd, &code->src, &ea) ||
4082 fetch (sd, &code->dst, &rd))
4083 goto end;
4084
dc5c3759
MS		 4085 if (ea)
4086 {
4087 res = rd / ea;
4088 nz = 1;
4089 }
4090 else
4091 {
4092 res = 0;
4093 nz = 0;
4094 }
4095
4096 n = res & 0x80000000;
4097 if (store (sd, &code->dst, res))
4098 goto end;
4099 goto next;
4100
4101 case O (O_DIVXU, SB): /* divxu.b */
4102 if (fetch (sd, &code->src, &ea) ||
4103 fetch (sd, &code->dst, &rd))
4104 goto end;
4105
4106 rd = UEXTSHORT (rd);
4107 ea = UEXTCHAR (ea);
4108
4109 n = ea & 0x80;
4110 nz = ea & 0xff;
4111 if (ea)
4112 {
4113 tmp = (unsigned) rd % ea;
4114 res = (unsigned) rd / ea;
4115 }
4116 else
4117 {
4118 tmp = 0;
4119 res = 0;
4120 }
4121
9f70f8ec 4122 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
dc5c3759
MS		 4123 goto end;
4124 goto next;
4125
4126 case O (O_DIVXU, SW): /* divxu.w */
4127 if (fetch (sd, &code->src, &ea) ||
4128 fetch (sd, &code->dst, &rd))
4129 goto end;
4130
4131 ea = UEXTSHORT (ea);
4132
4133 n = ea & 0x8000;
4134 nz = ea & 0xffff;
4135 if (ea)
4136 {
4137 tmp = (unsigned) rd % ea;
4138 res = (unsigned) rd / ea;
4139 }
4140 else
4141 {
4142 tmp = 0;
4143 res = 0;
4144 }
4145
4146 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4147 goto end;
4148 goto next;
4149
4150 case O (O_DIVXS, SB): /* divxs.b */
4151 if (fetch (sd, &code->src, &ea) ||
4152 fetch (sd, &code->dst, &rd))
4153 goto end;
4154
4155 rd = SEXTSHORT (rd);
e073c474 4156 ea = SEXTCHAR (ea);
dc5c3759
MS		 4157
4158 if (ea)
4159 {
4160 tmp = (int) rd % (int) ea;
4161 res = (int) rd / (int) ea;
4162 nz = 1;
4163 }
4164 else
4165 {
4166 tmp = 0;
4167 res = 0;
4168 nz = 0;
4169 }
4170
4171 n = res & 0x8000;
4172 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4173 goto end;
4174 goto next;
4175
4176 case O (O_DIVXS, SW): /* divxs.w */
4177 if (fetch (sd, &code->src, &ea) ||
4178 fetch (sd, &code->dst, &rd))
4179 goto end;
4180
e073c474 4181 ea = SEXTSHORT (ea);
dc5c3759
MS		 4182
4183 if (ea)
4184 {
4185 tmp = (int) rd % (int) ea;
4186 res = (int) rd / (int) ea;
4187 nz = 1;
4188 }
4189 else
4190 {
4191 tmp = 0;
4192 res = 0;
4193 nz = 0;
4194 }
4195
4196 n = res & 0x80000000;
4197 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4198 goto end;
4199 goto next;
4200
4201 case O (O_EXTS, SW): /* exts.w, signed extend */
4202 if (fetch2 (sd, &code->dst, &rd))
4203 goto end;
c906108c 4204 ea = rd & 0x80 ? -256 : 0;
dc5c3759 4205 res = (rd & 0xff) + ea;
c906108c 4206 goto log16;
dc5c3759
MS		 4207
4208 case O (O_EXTS, SL): /* exts.l, signed extend */
4209 if (fetch2 (sd, &code->dst, &rd))
4210 goto end;
4211 if (code->src.type == X (OP_IMM, SL))
4212 {
4213 if (fetch (sd, &code->src, &ea))
4214 goto end;
4215
4216 if (ea == 2) /* exts.l #2, nn */
4217 {
4218 /* Sign-extend from 8-bit to 32-bit. */
4219 ea = rd & 0x80 ? -256 : 0;
4220 res = (rd & 0xff) + ea;
4221 goto log32;
4222 }
4223 }
4224 /* Sign-extend from 16-bit to 32-bit. */
c906108c 4225 ea = rd & 0x8000 ? -65536 : 0;
dc5c3759 4226 res = (rd & 0xffff) + ea;
c906108c 4227 goto log32;
dc5c3759
MS		 4228
4229 case O (O_EXTU, SW): /* extu.w, unsigned extend */
4230 if (fetch2 (sd, &code->dst, &rd))
4231 goto end;
c906108c 4232 ea = 0;
dc5c3759 4233 res = (rd & 0xff) + ea;
c906108c 4234 goto log16;
dc5c3759
MS		 4235
4236 case O (O_EXTU, SL): /* extu.l, unsigned extend */
4237 if (fetch2 (sd, &code->dst, &rd))
4238 goto end;
4239 if (code->src.type == X (OP_IMM, SL))
4240 {
4241 if (fetch (sd, &code->src, &ea))
4242 goto end;
4243
4244 if (ea == 2) /* extu.l #2, nn */
4245 {
4246 /* Zero-extend from 8-bit to 32-bit. */
4247 ea = 0;
4248 res = (rd & 0xff) + ea;
4249 goto log32;
4250 }
4251 }
4252 /* Zero-extend from 16-bit to 32-bit. */
c906108c 4253 ea = 0;
dc5c3759 4254 res = (rd & 0xffff) + ea;
c906108c
SS		 4255 goto log32;
4256
dc5c3759 4257 case O (O_NOP, SN): /* nop */
c906108c
SS		 4258 goto next;
4259
dc5c3759 4260 case O (O_STM, SL): /* stm, store to memory */
c906108c
SS		 4261 {
4262 int nregs, firstreg, i;
4263
4264 nregs = GET_MEMORY_B (pc + 1);
4265 nregs >>= 4;
4266 nregs &= 0xf;
dc5c3759 4267 firstreg = code->src.reg;
c906108c
SS		 4268 firstreg &= 0xf;
4269 for (i = firstreg; i <= firstreg + nregs; i++)
4270 {
dc5c3759
MS		 4271 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) - 4);
4272 SET_MEMORY_L (h8_get_reg (sd, SP_REGNUM), h8_get_reg (sd, i));
c906108c
SS		 4273 }
4274 }
4275 goto next;
4276
dc5c3759 4277 case O (O_LDM, SL): /* ldm, load from memory */
9f70f8ec
MS		 4278 case O (O_RTEL, SN): /* rte/l, ldm plus rte */
4279 case O (O_RTSL, SN): /* rts/l, ldm plus rts */
c906108c
SS		 4280 {
4281 int nregs, firstreg, i;
4282
9f70f8ec
MS		 4283 nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
4284 firstreg = code->dst.reg & 0xf;
c906108c
SS		 4285 for (i = firstreg; i >= firstreg - nregs; i--)
4286 {
dc5c3759
MS		 4287 h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
4288 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
c906108c
SS		 4289 }
4290 }
9f70f8ec
MS		 4291 switch (code->opcode) {
4292 case O (O_RTEL, SN):
4293 goto rte;
4294 case O (O_RTSL, SN):
4295 goto rts;
4296 case O (O_LDM, SL):
4297 goto next;
4298 default:
4299 goto illegal;
4300 }
c906108c 4301
b7f97e9c
MS		 4302 case O (O_DAA, SB):
4303 /* Decimal Adjust Addition. This is for BCD arithmetic. */
9f70f8ec 4304 res = GET_B_REG (code->src.reg); /* FIXME fetch? */
dc5c3759
MS		 4305 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4306 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
b7f97e9c 4307 res = res; /* Value added == 0. */
dc5c3759
MS		 4308 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4309 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
b7f97e9c 4310 res = res + 0x6; /* Value added == 6. */
dc5c3759
MS		 4311 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4312 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
b7f97e9c 4313 res = res + 0x6; /* Value added == 6. */
dc5c3759
MS		 4314 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4315 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4316 res = res + 0x60; /* Value added == 60. */
4317 else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15) &&
4318 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4319 res = res + 0x66; /* Value added == 66. */
4320 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4321 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4322 res = res + 0x66; /* Value added == 66. */
4323 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4324 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
b7f97e9c 4325 res = res + 0x60; /* Value added == 60. */
dc5c3759
MS		 4326 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4327 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
b7f97e9c 4328 res = res + 0x66; /* Value added == 66. */
dc5c3759
MS		 4329 else if (c && (1 <= (res >> 4) && (res >> 4) <= 3) &&
4330 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
b7f97e9c 4331 res = res + 0x66; /* Value added == 66. */
b7f97e9c
MS		 4332
4333 goto alu8;
4334
4335 case O (O_DAS, SB):
4336 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4337 res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
dc5c3759
MS		 4338 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4339 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
b7f97e9c 4340 res = res; /* Value added == 0. */
dc5c3759
MS		 4341 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4342 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
b7f97e9c 4343 res = res + 0xfa; /* Value added == 0xfa. */
dc5c3759
MS		 4344 else if ( c && (7 <= (res >> 4) && (res >> 4) <= 15) &&
4345 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
b7f97e9c 4346 res = res + 0xa0; /* Value added == 0xa0. */
dc5c3759
MS		 4347 else if (c && (6 <= (res >> 4) && (res >> 4) <= 15) &&
4348 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
b7f97e9c
MS		 4349 res = res + 0x9a; /* Value added == 0x9a. */
4350
4351 goto alu8;
4352
c906108c 4353 default:
d0fe2f7e 4354 illegal:
dc5c3759 4355 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
c906108c
SS		 4356 goto end;
4357
4358 }
dc5c3759
MS		 4359
4360 (*sim_callback->printf_filtered) (sim_callback,
4361 "sim_resume: internal error.\n");
4362 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4363 goto end;
c906108c
SS		 4364
4365 setc:
dc5c3759
MS		 4366 if (code->dst.type == X (OP_CCR, SB) ||
4367 code->dst.type == X (OP_CCR, SW))
c3f4437e 4368 {
dc5c3759 4369 h8_set_ccr (sd, res);
9f70f8ec 4370 GETSR (sd);
c3f4437e 4371 }
dc5c3759
MS		 4372 else if (h8300smode &&
4373 (code->dst.type == X (OP_EXR, SB) ||
4374 code->dst.type == X (OP_EXR, SW)))
c3f4437e 4375 {
dc5c3759
MS		 4376 h8_set_exr (sd, res);
4377 if (h8300smode) /* Get exr. */
4378 {
4379 trace = (h8_get_exr (sd) >> 7) & 1;
4380 intMask = h8_get_exr (sd) & 7;
4381 }
c3f4437e 4382 }
fc974602 4383 else
c3f4437e 4384 goto illegal;
fc974602 4385
c906108c
SS		 4386 goto next;
4387
4388 condtrue:
4389 /* When a branch works */
dc5c3759
MS		 4390 if (fetch (sd, &code->src, &res))
4391 goto end;
4392 if (res & 1) /* bad address */
4393 goto illegal;
4394 pc = code->next_pc + res;
c906108c
SS		 4395 goto end;
4396
4397 /* Set the cond codes from res */
4398 bitop:
4399
4400 /* Set the flags after an 8 bit inc/dec operation */
4401 just_flags_inc8:
4402 n = res & 0x80;
4403 nz = res & 0xff;
4404 v = (rd & 0x7f) == 0x7f;
4405 goto next;
4406
c906108c
SS		 4407 /* Set the flags after an 16 bit inc/dec operation */
4408 just_flags_inc16:
4409 n = res & 0x8000;
4410 nz = res & 0xffff;
4411 v = (rd & 0x7fff) == 0x7fff;
4412 goto next;
4413
c906108c
SS		 4414 /* Set the flags after an 32 bit inc/dec operation */
4415 just_flags_inc32:
4416 n = res & 0x80000000;
4417 nz = res & 0xffffffff;
4418 v = (rd & 0x7fffffff) == 0x7fffffff;
4419 goto next;
4420
c906108c
SS		 4421 shift8:
4422 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4423 n = (rd & 0x80);
4424 nz = rd & 0xff;
dc5c3759
MS		 4425 if (store2 (sd, &code->dst, rd))
4426 goto end;
c906108c
SS		 4427 goto next;
4428
4429 shift16:
4430 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4431 n = (rd & 0x8000);
4432 nz = rd & 0xffff;
dc5c3759
MS		 4433 if (store2 (sd, &code->dst, rd))
4434 goto end;
c906108c
SS		 4435 goto next;
4436
4437 shift32:
4438 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4439 n = (rd & 0x80000000);
4440 nz = rd & 0xffffffff;
dc5c3759
MS		 4441 if (store2 (sd, &code->dst, rd))
4442 goto end;
c906108c
SS		 4443 goto next;
4444
4445 log32:
dc5c3759
MS		 4446 if (store2 (sd, &code->dst, res))
4447 goto end;
4448
c906108c
SS		 4449 just_flags_log32:
4450 /* flags after a 32bit logical operation */
4451 n = res & 0x80000000;
4452 nz = res & 0xffffffff;
4453 v = 0;
4454 goto next;
4455
4456 log16:
dc5c3759
MS		 4457 if (store2 (sd, &code->dst, res))
4458 goto end;
4459
c906108c
SS		 4460 just_flags_log16:
4461 /* flags after a 16bit logical operation */
4462 n = res & 0x8000;
4463 nz = res & 0xffff;
4464 v = 0;
4465 goto next;
4466
c906108c 4467 log8:
dc5c3759
MS		 4468 if (store2 (sd, &code->dst, res))
4469 goto end;
4470
c906108c
SS		 4471 just_flags_log8:
4472 n = res & 0x80;
4473 nz = res & 0xff;
4474 v = 0;
4475 goto next;
4476
4477 alu8:
dc5c3759
MS		 4478 if (store2 (sd, &code->dst, res))
4479 goto end;
4480
c906108c
SS		 4481 just_flags_alu8:
4482 n = res & 0x80;
4483 nz = res & 0xff;
4484 c = (res & 0x100);
4485 switch (code->opcode / 4)
4486 {
4487 case O_ADD:
dc5c3759 4488 case O_ADDX:
c906108c
SS		 4489 v = ((rd & 0x80) == (ea & 0x80)
4490 && (rd & 0x80) != (res & 0x80));
4491 break;
4492 case O_SUB:
dc5c3759 4493 case O_SUBX:
c906108c
SS		 4494 case O_CMP:
4495 v = ((rd & 0x80) != (-ea & 0x80)
4496 && (rd & 0x80) != (res & 0x80));
4497 break;
4498 case O_NEG:
4499 v = (rd == 0x80);
4500 break;
dc5c3759
MS		 4501 case O_DAA:
4502 case O_DAS:
4503 break; /* No effect on v flag. */
c906108c
SS		 4504 }
4505 goto next;
4506
4507 alu16:
dc5c3759
MS		 4508 if (store2 (sd, &code->dst, res))
4509 goto end;
4510
c906108c
SS		 4511 just_flags_alu16:
4512 n = res & 0x8000;
4513 nz = res & 0xffff;
4514 c = (res & 0x10000);
4515 switch (code->opcode / 4)
4516 {
4517 case O_ADD:
dc5c3759 4518 case O_ADDX:
c906108c
SS		 4519 v = ((rd & 0x8000) == (ea & 0x8000)
4520 && (rd & 0x8000) != (res & 0x8000));
4521 break;
4522 case O_SUB:
dc5c3759 4523 case O_SUBX:
c906108c
SS		 4524 case O_CMP:
4525 v = ((rd & 0x8000) != (-ea & 0x8000)
4526 && (rd & 0x8000) != (res & 0x8000));
4527 break;
4528 case O_NEG:
4529 v = (rd == 0x8000);
4530 break;
4531 }
4532 goto next;
4533
4534 alu32:
dc5c3759
MS		 4535 if (store2 (sd, &code->dst, res))
4536 goto end;
4537
c906108c
SS		 4538 just_flags_alu32:
4539 n = res & 0x80000000;
4540 nz = res & 0xffffffff;
4541 switch (code->opcode / 4)
4542 {
4543 case O_ADD:
dc5c3759 4544 case O_ADDX:
c906108c
SS		 4545 v = ((rd & 0x80000000) == (ea & 0x80000000)
4546 && (rd & 0x80000000) != (res & 0x80000000));
dc5c3759
MS		 4547 c = ((unsigned) res < (unsigned) rd) ||
4548 ((unsigned) res < (unsigned) ea);
c906108c
SS		 4549 break;
4550 case O_SUB:
dc5c3759 4551 case O_SUBX:
c906108c
SS		 4552 case O_CMP:
4553 v = ((rd & 0x80000000) != (-ea & 0x80000000)
4554 && (rd & 0x80000000) != (res & 0x80000000));
4555 c = (unsigned) rd < (unsigned) -ea;
4556 break;
4557 case O_NEG:
4558 v = (rd == 0x80000000);
4559 c = res != 0;
4560 break;
4561 }
4562 goto next;
4563
dc5c3759
MS		 4564 next:
4565 if ((res = h8_get_delayed_branch (sd)) != 0)
4566 {
4567 pc = res;
4568 h8_set_delayed_branch (sd, 0);
4569 }
4570 else
4571 pc = code->next_pc;
c906108c
SS		 4572
4573 end:
dc5c3759 4574
c906108c
SS		 4575 if (--poll_count < 0)
4576 {
7a292a7a 4577 poll_count = POLL_QUIT_INTERVAL;
c906108c
SS		 4578 if ((*sim_callback->poll_quit) != NULL
4579 && (*sim_callback->poll_quit) (sim_callback))
dc5c3759 4580 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
c906108c 4581 }
dc5c3759
MS		 4582 sim_engine_get_run_state (sd, &reason, &sigrc);
4583 } while (reason == sim_running);
c906108c 4584
dc5c3759
MS		 4585 h8_set_ticks (sd, h8_get_ticks (sd) + get_now () - tick_start);
4586 h8_set_cycles (sd, h8_get_cycles (sd) + cycles);
4587 h8_set_insts (sd, h8_get_insts (sd) + insts);
4588 h8_set_pc (sd, pc);
4589 BUILDSR (sd);
4590
4591 if (h8300smode)
4592 h8_set_exr (sd, (trace<<7) | intMask);
4593
4594 h8_set_mask (sd, oldmask);
c906108c
SS		 4595}
4596
c906108c 4597int
5558e7e6 4598sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
c906108c
SS		 4599{
4600 int i;
4601
dc5c3759 4602 init_pointers (sd);
c906108c
SS		 4603 if (addr < 0)
4604 return 0;
4605 for (i = 0; i < size; i++)
4606 {
4607 if (addr < memory_size)
4608 {
dc5c3759
MS		 4609 h8_set_memory (sd, addr + i, buffer[i]);
4610 h8_set_cache_idx (sd, addr + i, 0);
c906108c
SS		 4611 }
4612 else
dc5c3759
MS		 4613 {
4614 h8_set_eightbit (sd, (addr + i) & 0xff, buffer[i]);
4615 }
c906108c
SS		 4616 }
4617 return size;
4618}
4619
4620int
a4f27e3e 4621sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
c906108c 4622{
dc5c3759 4623 init_pointers (sd);
c906108c
SS		 4624 if (addr < 0)
4625 return 0;
4626 if (addr < memory_size)
dc5c3759 4627 memcpy (buffer, h8_get_memory_buf (sd) + addr, size);
c906108c 4628 else
dc5c3759 4629 memcpy (buffer, h8_get_eightbit_buf (sd) + (addr & 0xff), size);
c906108c
SS		 4630 return size;
4631}
4632
4633
c906108c 4634int
a4f27e3e 4635sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
c906108c
SS		 4636{
4637 int longval;
4638 int shortval;
4639 int intval;
4640 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
4641 shortval = (value[0] << 8) | (value[1]);
4642 intval = h8300hmode ? longval : shortval;
4643
dc5c3759 4644 init_pointers (sd);
c906108c
SS		 4645 switch (rn)
4646 {
9f70f8ec 4647 case PC_REGNUM:
59768597
SA		 4648 if(h8300_normal_mode)
4649 h8_set_pc (sd, shortval); /* PC for Normal mode is 2 bytes */
4650 else
4651 h8_set_pc (sd, intval);
9f70f8ec 4652 break;
c906108c 4653 default:
dc5c3759
MS		 4654 (*sim_callback->printf_filtered) (sim_callback,
4655 "sim_store_register: bad regnum %d.\n",
4656 rn);
c906108c
SS		 4657 case R0_REGNUM:
4658 case R1_REGNUM:
4659 case R2_REGNUM:
4660 case R3_REGNUM:
4661 case R4_REGNUM:
4662 case R5_REGNUM:
4663 case R6_REGNUM:
4664 case R7_REGNUM:
dc5c3759 4665 h8_set_reg (sd, rn, intval);
c906108c
SS		 4666 break;
4667 case CCR_REGNUM:
dc5c3759 4668 h8_set_ccr (sd, intval);
c906108c 4669 break;
fc974602 4670 case EXR_REGNUM:
dc5c3759 4671 h8_set_exr (sd, intval);
fc974602 4672 break;
173b1c98
MS		 4673 case SBR_REGNUM:
4674 h8_set_sbr (sd, intval);
4675 break;
4676 case VBR_REGNUM:
4677 h8_set_vbr (sd, intval);
4678 break;
4679 case MACH_REGNUM:
4680 h8_set_mach (sd, intval);
4681 break;
4682 case MACL_REGNUM:
4683 h8_set_macl (sd, intval);
4684 break;
c906108c 4685 case CYCLE_REGNUM:
dc5c3759 4686 h8_set_cycles (sd, longval);
c906108c 4687 break;
9f70f8ec 4688
c906108c 4689 case INST_REGNUM:
dc5c3759 4690 h8_set_insts (sd, longval);
c906108c 4691 break;
9f70f8ec 4692
c906108c 4693 case TICK_REGNUM:
dc5c3759 4694 h8_set_ticks (sd, longval);
c906108c
SS		 4695 break;
4696 }
dae477fe 4697 return length;
c906108c
SS		 4698}
4699
4700int
a4f27e3e 4701sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
c906108c
SS		 4702{
4703 int v;
4704 int longreg = 0;
4705
dc5c3759 4706 init_pointers (sd);
c906108c 4707
d0fe2f7e 4708 if (!h8300smode && rn >= EXR_REGNUM)
c3f4437e 4709 rn++;
c906108c
SS		 4710 switch (rn)
4711 {
4712 default:
dc5c3759
MS		 4713 (*sim_callback->printf_filtered) (sim_callback,
4714 "sim_fetch_register: bad regnum %d.\n",
4715 rn);
4716 v = 0;
4717 break;
3b02cf92 4718 case CCR_REGNUM:
dc5c3759 4719 v = h8_get_ccr (sd);
c906108c 4720 break;
fc974602 4721 case EXR_REGNUM:
dc5c3759 4722 v = h8_get_exr (sd);
fc974602 4723 break;
3b02cf92 4724 case PC_REGNUM:
dc5c3759 4725 v = h8_get_pc (sd);
c906108c 4726 break;
173b1c98
MS		 4727 case SBR_REGNUM:
4728 v = h8_get_sbr (sd);
4729 break;
4730 case VBR_REGNUM:
4731 v = h8_get_vbr (sd);
4732 break;
4733 case MACH_REGNUM:
4734 v = h8_get_mach (sd);
4735 break;
4736 case MACL_REGNUM:
4737 v = h8_get_macl (sd);
4738 break;
c906108c
SS		 4739 case R0_REGNUM:
4740 case R1_REGNUM:
4741 case R2_REGNUM:
4742 case R3_REGNUM:
4743 case R4_REGNUM:
4744 case R5_REGNUM:
4745 case R6_REGNUM:
4746 case R7_REGNUM:
dc5c3759 4747 v = h8_get_reg (sd, rn);
c906108c 4748 break;
3b02cf92 4749 case CYCLE_REGNUM:
dc5c3759 4750 v = h8_get_cycles (sd);
c906108c
SS		 4751 longreg = 1;
4752 break;
3b02cf92 4753 case TICK_REGNUM:
dc5c3759 4754 v = h8_get_ticks (sd);
c906108c
SS		 4755 longreg = 1;
4756 break;
3b02cf92 4757 case INST_REGNUM:
dc5c3759 4758 v = h8_get_insts (sd);
c906108c
SS		 4759 longreg = 1;
4760 break;
4761 }
59768597
SA		 4762 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4763 if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode))
c906108c
SS		 4764 {
4765 buf[0] = v >> 24;
4766 buf[1] = v >> 16;
4767 buf[2] = v >> 8;
4768 buf[3] = v >> 0;
4769 }
4770 else
4771 {
4772 buf[0] = v >> 8;
4773 buf[1] = v;
4774 }
4775 return -1;
4776}
4777
4778void
a4f27e3e 4779sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
c906108c 4780{
dc5c3759 4781 sim_engine_get_run_state (sd, reason, sigrc);
c906108c
SS		 4782}
4783
dc5c3759
MS		 4784static void
4785set_simcache_size (SIM_DESC sd, int n)
c906108c 4786{
dc5c3759
MS		 4787 if (sd->sim_cache)
4788 free (sd->sim_cache);
c906108c
SS		 4789 if (n < 2)
4790 n = 2;
dc5c3759
MS		 4791 sd->sim_cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
4792 memset (sd->sim_cache, 0, sizeof (decoded_inst) * n);
4793 sd->sim_cache_size = n;
c906108c
SS		 4794}
4795
4796
4797void
a4f27e3e 4798sim_info (SIM_DESC sd, int verbose)
c906108c 4799{
dc5c3759
MS		 4800 double timetaken = (double) h8_get_ticks (sd) / (double) now_persec ();
4801 double virttime = h8_get_cycles (sd) / 10.0e6;
c906108c
SS		 4802
4803 (*sim_callback->printf_filtered) (sim_callback,
4804 "\n\n#instructions executed %10d\n",
dc5c3759 4805 h8_get_insts (sd));
c906108c
SS		 4806 (*sim_callback->printf_filtered) (sim_callback,
4807 "#cycles (v approximate) %10d\n",
dc5c3759 4808 h8_get_cycles (sd));
c906108c
SS		 4809 (*sim_callback->printf_filtered) (sim_callback,
4810 "#real time taken %10.4f\n",
4811 timetaken);
4812 (*sim_callback->printf_filtered) (sim_callback,
e8c1a4e7 4813 "#virtual time taken %10.4f\n",
c906108c
SS		 4814 virttime);
4815 if (timetaken != 0.0)
4816 (*sim_callback->printf_filtered) (sim_callback,
4817 "#simulation ratio %10.4f\n",
4818 virttime / timetaken);
4819 (*sim_callback->printf_filtered) (sim_callback,
4820 "#compiles %10d\n",
dc5c3759 4821 h8_get_compiles (sd));
c906108c
SS		 4822 (*sim_callback->printf_filtered) (sim_callback,
4823 "#cache size %10d\n",
dc5c3759 4824 sd->sim_cache_size);
c906108c
SS		 4825
4826#ifdef ADEBUG
4827 /* This to be conditional on `what' (aka `verbose'),
4828 however it was never passed as non-zero. */
4829 if (1)
4830 {
4831 int i;
4832 for (i = 0; i < O_LAST; i++)
4833 {
dc5c3759
MS		 4834 if (h8_get_stats (sd, i))
4835 (*sim_callback->printf_filtered) (sim_callback, "%d: %d\n",
4836 i, h8_get_stats (sd, i));
c906108c
SS		 4837 }
4838 }
4839#endif
4840}
4841
2ea716f6
KH		 4842/* Indicate whether the cpu is an H8/300 or H8/300H.
4843 FLAG is non-zero for the H8/300H. */
c906108c
SS		 4844
4845void
27ebfdf4 4846set_h8300h (unsigned long machine)
c906108c
SS		 4847{
4848 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4849 This function being replaced by a sim_open:ARGV configuration
2ea716f6 4850 option. */
dc5c3759 4851
454d0511
DD		 4852 h8300hmode = h8300smode = h8300sxmode = h8300_normal_mode = 0;
4853
9f70f8ec 4854 if (machine == bfd_mach_h8300sx || machine == bfd_mach_h8300sxn)
27ebfdf4
MS		 4855 h8300sxmode = 1;
4856
4857 if (machine == bfd_mach_h8300s || machine == bfd_mach_h8300sn || h8300sxmode)
4858 h8300smode = 1;
4859
4860 if (machine == bfd_mach_h8300h || machine == bfd_mach_h8300hn || h8300smode)
4861 h8300hmode = 1;
59768597
SA		 4862
4863 if(machine == bfd_mach_h8300hn || machine == bfd_mach_h8300sn || machine == bfd_mach_h8300sxn)
4864 h8300_normal_mode = 1;
dc5c3759
MS		 4865}
4866
4867/* Cover function of sim_state_free to free the cpu buffers as well. */
4868
4869static void
4870free_state (SIM_DESC sd)
4871{
4872 if (STATE_MODULES (sd) != NULL)
4873 sim_module_uninstall (sd);
4874
4875 /* Fixme: free buffers in _sim_cpu. */
4876 sim_state_free (sd);
c906108c
SS		 4877}
4878
4879SIM_DESC
a4f27e3e 4880sim_open (SIM_OPEN_KIND kind,
dc5c3759 4881 struct host_callback_struct *callback,
6b4a8935 4882 struct bfd *abfd,
a4f27e3e 4883 char **argv)
c906108c 4884{
dc5c3759
MS		 4885 SIM_DESC sd;
4886 sim_cpu *cpu;
4887
4888 sd = sim_state_alloc (kind, callback);
4889 sd->cpu = sim_cpu_alloc (sd, 0);
4890 cpu = STATE_CPU (sd, 0);
4891 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4892 sim_state_initialize (sd, cpu);
4893 /* sim_cpu object is new, so some initialization is needed. */
4894 init_pointers_needed = 1;
4895
4896 /* For compatibility (FIXME: is this right?). */
4897 current_alignment = NONSTRICT_ALIGNMENT;
4898 current_target_byte_order = BIG_ENDIAN;
4899
4900 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
4901 {
4902 free_state (sd);
4903 return 0;
4904 }
4905
4906 /* getopt will print the error message so we just have to exit if
4907 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4908 to call print_filtered. */
4909 if (sim_parse_args (sd, argv) != SIM_RC_OK)
4910 {
4911 /* Uninstall the modules to avoid memory leaks,
4912 file descriptor leaks, etc. */
4913 free_state (sd);
4914 return 0;
4915 }
4916
4917 /* Check for/establish the a reference program image. */
4918 if (sim_analyze_program (sd,
4919 (STATE_PROG_ARGV (sd) != NULL
4920 ? *STATE_PROG_ARGV (sd)
4921 : NULL), abfd) != SIM_RC_OK)
4922 {
4923 free_state (sd);
4924 return 0;
4925 }
4926
4927 /* Establish any remaining configuration options. */
4928 if (sim_config (sd) != SIM_RC_OK)
4929 {
4930 free_state (sd);
4931 return 0;
4932 }
4933
4934 if (sim_post_argv_init (sd) != SIM_RC_OK)
4935 {
4936 /* Uninstall the modules to avoid memory leaks,
4937 file descriptor leaks, etc. */
4938 free_state (sd);
4939 return 0;
4940 }
4941
4942 /* sim_hw_configure (sd); */
4943
2ea716f6 4944 /* FIXME: Much of the code in sim_load can be moved here. */
c906108c
SS		 4945
4946 sim_kind = kind;
4947 myname = argv[0];
dc5c3759
MS		 4948 sim_callback = callback;
4949 return sd;
c906108c
SS		 4950}
4951
4952void
a4f27e3e 4953sim_close (SIM_DESC sd, int quitting)
c906108c 4954{
2ea716f6 4955 /* Nothing to do. */
c906108c
SS		 4956}
4957
4958/* Called by gdb to load a program into memory. */
4959
4960SIM_RC
b2b255bd 4961sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
c906108c
SS		 4962{
4963 bfd *prog_bfd;
4964
2ea716f6
KH		 4965 /* FIXME: The code below that sets a specific variant of the H8/300
4966 being simulated should be moved to sim_open(). */
c906108c 4967
2ea716f6 4968 /* See if the file is for the H8/300 or H8/300H. */
c906108c
SS		 4969 /* ??? This may not be the most efficient way. The z8k simulator
4970 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4971 if (abfd != NULL)
4972 prog_bfd = abfd;
4973 else
3d29fdb4 4974 prog_bfd = bfd_openr (prog, NULL);
c906108c
SS		 4975 if (prog_bfd != NULL)
4976 {
4977 /* Set the cpu type. We ignore failure from bfd_check_format
4978 and bfd_openr as sim_load_file checks too. */
de9b1892 4979 if (bfd_check_format (prog_bfd, bfd_object))
c906108c 4980 {
27ebfdf4 4981 set_h8300h (bfd_get_mach (prog_bfd));
c906108c
SS		 4982 }
4983 }
4984
4985 /* If we're using gdb attached to the simulator, then we have to
4986 reallocate memory for the simulator.
4987
4988 When gdb first starts, it calls fetch_registers (among other
4989 functions), which in turn calls init_pointers, which allocates
4990 simulator memory.
4991
4992 The problem is when we do that, we don't know whether we're
2ea716f6 4993 debugging an H8/300 or H8/300H program.
c906108c
SS		 4994
4995 This is the first point at which we can make that determination,
4996 so we just reallocate memory now; this will also allow us to handle
2ea716f6 4997 switching between H8/300 and H8/300H programs without exiting
c906108c 4998 gdb. */
a8cdafbd 4999
59768597 5000 if (h8300smode && !h8300_normal_mode)
a8cdafbd 5001 memory_size = H8300S_MSIZE;
59768597 5002 else if (h8300hmode && !h8300_normal_mode)
c906108c
SS		 5003 memory_size = H8300H_MSIZE;
5004 else
5005 memory_size = H8300_MSIZE;
5006
dc5c3759
MS		 5007 if (h8_get_memory_buf (sd))
5008 free (h8_get_memory_buf (sd));
5009 if (h8_get_cache_idx_buf (sd))
5010 free (h8_get_cache_idx_buf (sd));
5011 if (h8_get_eightbit_buf (sd))
5012 free (h8_get_eightbit_buf (sd));
c906108c 5013
dc5c3759
MS		 5014 h8_set_memory_buf (sd, (unsigned char *)
5015 calloc (sizeof (char), memory_size));
5016 h8_set_cache_idx_buf (sd, (unsigned short *)
5017 calloc (sizeof (short), memory_size));
e4d3c499 5018 sd->memory_size = memory_size;
dc5c3759 5019 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
c906108c 5020
2ea716f6 5021 /* `msize' must be a power of two. */
c906108c 5022 if ((memory_size & (memory_size - 1)) != 0)
dc5c3759
MS		 5023 {
5024 (*sim_callback->printf_filtered) (sim_callback,
5025 "sim_load: bad memory size.\n");
5026 return SIM_RC_FAIL;
5027 }
5028 h8_set_mask (sd, memory_size - 1);
c906108c
SS		 5029
5030 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
5031 sim_kind == SIM_OPEN_DEBUG,
5032 0, sim_write)
5033 == NULL)
5034 {
5035 /* Close the bfd if we opened it. */
5036 if (abfd == NULL && prog_bfd != NULL)
5037 bfd_close (prog_bfd);
5038 return SIM_RC_FAIL;
5039 }
5040
5041 /* Close the bfd if we opened it. */
5042 if (abfd == NULL && prog_bfd != NULL)
5043 bfd_close (prog_bfd);
5044 return SIM_RC_OK;
5045}
5046
5047SIM_RC
6b4a8935 5048sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
c906108c 5049{
d1360fb0
V		 5050 int i = 0;
5051 int len_arg = 0;
5052 int no_of_args = 0;
dc5c3759 5053
c906108c 5054 if (abfd != NULL)
dc5c3759 5055 h8_set_pc (sd, bfd_get_start_address (abfd));
c906108c 5056 else
dc5c3759 5057 h8_set_pc (sd, 0);
d1360fb0
V		 5058
5059 /* Command Line support. */
5060 if (argv != NULL)
5061 {
5062 /* Counting the no. of commandline arguments. */
5063 for (no_of_args = 0; argv[no_of_args] != NULL; no_of_args++)
5064 continue;
5065
5066 /* Allocating memory for the argv pointers. */
dc5c3759
MS		 5067 h8_set_command_line (sd, (char **) malloc ((sizeof (char *))
5068 * (no_of_args + 1)));
d1360fb0
V		 5069
5070 for (i = 0; i < no_of_args; i++)
5071 {
d1360fb0 5072 /* Copying the argument string. */
dc5c3759 5073 h8_set_cmdline_arg (sd, i, (char *) strdup (argv[i]));
d1360fb0 5074 }
dc5c3759 5075 h8_set_cmdline_arg (sd, i, NULL);
d1360fb0
V		 5076 }
5077
c906108c
SS		 5078 return SIM_RC_OK;
5079}
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