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Commit | Line | Data |
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c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
3c25f8c7 AC |
35 | #include "gdb/callback.h" |
36 | #include "gdb/remote-sim.h" | |
a64bfde3 | 37 | #include "gdb/sim-h8300.h" |
bf174226 V |
38 | #include "sys/stat.h" |
39 | #include "sys/types.h" | |
c906108c SS |
40 | |
41 | #ifndef SIGTRAP | |
42 | # define SIGTRAP 5 | |
43 | #endif | |
44 | ||
45 | int debug; | |
46 | ||
47 | host_callback *sim_callback; | |
48 | ||
49 | static SIM_OPEN_KIND sim_kind; | |
50 | static char *myname; | |
51 | ||
52 | /* FIXME: Needs to live in header file. | |
53 | This header should also include the things in remote-sim.h. | |
54 | One could move this to remote-sim.h but this function isn't needed | |
55 | by gdb. */ | |
56 | void sim_set_simcache_size PARAMS ((int)); | |
57 | ||
de9b1892 | 58 | #define X(op, size) op * 4 + size |
c906108c | 59 | |
de9b1892 | 60 | #define SP (h8300hmode ? SL : SW) |
c906108c SS |
61 | #define SB 0 |
62 | #define SW 1 | |
63 | #define SL 2 | |
64 | #define OP_REG 1 | |
65 | #define OP_DEC 2 | |
66 | #define OP_DISP 3 | |
67 | #define OP_INC 4 | |
68 | #define OP_PCREL 5 | |
69 | #define OP_MEM 6 | |
70 | #define OP_CCR 7 | |
71 | #define OP_IMM 8 | |
72 | #define OP_ABS 10 | |
fc974602 | 73 | #define OP_EXR 11 |
c906108c SS |
74 | #define h8_opcodes ops |
75 | #define DEFINE_TABLE | |
76 | #include "opcode/h8300.h" | |
77 | ||
78 | #include "inst.h" | |
79 | ||
0ef9643e | 80 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
81 | |
82 | #define POLL_QUIT_INTERVAL 0x80000 | |
83 | ||
c906108c | 84 | #define LOW_BYTE(x) ((x) & 0xff) |
de9b1892 KH |
85 | #define HIGH_BYTE(x) (((x) >> 8) & 0xff) |
86 | #define P(X,Y) ((X << 8) | Y) | |
c906108c | 87 | |
d0fe2f7e KH |
88 | #define BUILDSR() \ |
89 | cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \ | |
90 | | (N << 3) | (Z << 2) | (V << 1) | C); | |
c906108c | 91 | |
fc974602 | 92 | #define BUILDEXR() \ |
d1335144 | 93 | if (h8300smode) cpu.exr = (trace<<7) | intMask; |
fc974602 | 94 | |
c906108c SS |
95 | #define GETSR() \ |
96 | c = (cpu.ccr >> 0) & 1;\ | |
97 | v = (cpu.ccr >> 1) & 1;\ | |
98 | nz = !((cpu.ccr >> 2) & 1);\ | |
f6225c96 AV |
99 | n = (cpu.ccr >> 3) & 1;\ |
100 | u = (cpu.ccr >> 4) & 1;\ | |
101 | h = (cpu.ccr >> 5) & 1;\ | |
102 | ui = ((cpu.ccr >> 6) & 1);\ | |
103 | intMaskBit = (cpu.ccr >> 7) & 1; | |
c906108c | 104 | |
d0fe2f7e KH |
105 | #define GETEXR() \ |
106 | if (h8300smode) \ | |
107 | { \ | |
108 | trace = (cpu.exr >> 7) & 1; \ | |
109 | intMask = cpu.exr & 7; \ | |
110 | } | |
fc974602 | 111 | |
c906108c | 112 | #ifdef __CHAR_IS_SIGNED__ |
de9b1892 | 113 | #define SEXTCHAR(x) ((char) (x)) |
c906108c SS |
114 | #endif |
115 | ||
116 | #ifndef SEXTCHAR | |
d0fe2f7e | 117 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff) |
c906108c SS |
118 | #endif |
119 | ||
120 | #define UEXTCHAR(x) ((x) & 0xff) | |
121 | #define UEXTSHORT(x) ((x) & 0xffff) | |
de9b1892 | 122 | #define SEXTSHORT(x) ((short) (x)) |
c906108c SS |
123 | |
124 | static cpu_state_type cpu; | |
125 | ||
126 | int h8300hmode = 0; | |
127 | int h8300smode = 0; | |
128 | ||
129 | static int memory_size; | |
130 | ||
c906108c | 131 | static int |
a4f27e3e | 132 | get_now (void) |
c906108c | 133 | { |
3b02cf92 | 134 | return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */ |
c906108c SS |
135 | } |
136 | ||
137 | static int | |
a4f27e3e | 138 | now_persec (void) |
c906108c SS |
139 | { |
140 | return 1; | |
141 | } | |
142 | ||
c906108c | 143 | static int |
a4f27e3e | 144 | bitfrom (int x) |
c906108c SS |
145 | { |
146 | switch (x & SIZE) | |
147 | { | |
148 | case L_8: | |
149 | return SB; | |
150 | case L_16: | |
151 | return SW; | |
152 | case L_32: | |
153 | return SL; | |
154 | case L_P: | |
155 | return h8300hmode ? SL : SW; | |
156 | } | |
157 | } | |
158 | ||
0ef9643e | 159 | static unsigned int |
a4f27e3e | 160 | lvalue (int x, int rn) |
c906108c SS |
161 | { |
162 | switch (x / 4) | |
163 | { | |
164 | case OP_DISP: | |
165 | if (rn == 8) | |
166 | { | |
167 | return X (OP_IMM, SP); | |
168 | } | |
169 | return X (OP_REG, SP); | |
170 | ||
171 | case OP_MEM: | |
c906108c | 172 | return X (OP_MEM, SP); |
0ef9643e | 173 | |
c906108c | 174 | default: |
3b02cf92 | 175 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
176 | } |
177 | } | |
178 | ||
179 | static unsigned int | |
a4f27e3e | 180 | decode (int addr, unsigned char *data, decoded_inst *dst) |
c906108c SS |
181 | { |
182 | int rs = 0; | |
183 | int rd = 0; | |
184 | int rdisp = 0; | |
185 | int abs = 0; | |
c906108c | 186 | int bit = 0; |
0ef9643e | 187 | int plen = 0; |
6d028502 | 188 | struct h8_opcode *q; |
c906108c | 189 | int size = 0; |
0ef9643e | 190 | |
c906108c SS |
191 | dst->dst.type = -1; |
192 | dst->src.type = -1; | |
0ef9643e JL |
193 | |
194 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 195 | for (q = h8_opcodes; q->name; q++) |
c906108c | 196 | { |
6d028502 | 197 | op_type *nib = q->data.nib; |
c906108c SS |
198 | unsigned int len = 0; |
199 | ||
c906108c SS |
200 | while (1) |
201 | { | |
202 | op_type looking_for = *nib; | |
203 | int thisnib = data[len >> 1]; | |
204 | ||
205 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
206 | ||
207 | if (looking_for < 16 && looking_for >= 0) | |
208 | { | |
209 | if (looking_for != thisnib) | |
210 | goto fail; | |
211 | } | |
212 | else | |
213 | { | |
214 | if ((int) looking_for & (int) B31) | |
215 | { | |
216 | if (!(((int) thisnib & 0x8) != 0)) | |
217 | goto fail; | |
0ef9643e JL |
218 | |
219 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
220 | thisnib &= 0x7; |
221 | } | |
0ef9643e | 222 | |
c906108c SS |
223 | if ((int) looking_for & (int) B30) |
224 | { | |
225 | if (!(((int) thisnib & 0x8) == 0)) | |
226 | goto fail; | |
0ef9643e | 227 | |
c906108c SS |
228 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
229 | } | |
0ef9643e | 230 | |
c906108c SS |
231 | if (looking_for & DBIT) |
232 | { | |
0a17cd59 AC |
233 | /* Exclude adds/subs by looking at bit 0 and 2, and |
234 | make sure the operand size, either w or l, | |
235 | matches by looking at bit 1. */ | |
236 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 237 | goto fail; |
0ef9643e | 238 | |
c906108c SS |
239 | abs = (thisnib & 0x8) ? 2 : 1; |
240 | } | |
241 | else if (looking_for & (REG | IND | INC | DEC)) | |
242 | { | |
243 | if (looking_for & REG) | |
244 | { | |
0ef9643e | 245 | /* Can work out size from the register. */ |
c906108c SS |
246 | size = bitfrom (looking_for); |
247 | } | |
248 | if (looking_for & SRC) | |
0ef9643e | 249 | rs = thisnib; |
c906108c | 250 | else |
0ef9643e | 251 | rd = thisnib; |
c906108c SS |
252 | } |
253 | else if (looking_for & L_16) | |
254 | { | |
255 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
256 | plen = 16; | |
257 | if (looking_for & (PCREL | DISP)) | |
258 | { | |
259 | abs = (short) (abs); | |
260 | } | |
261 | } | |
262 | else if (looking_for & ABSJMP) | |
263 | { | |
0ef9643e | 264 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
265 | } |
266 | else if (looking_for & MEMIND) | |
267 | { | |
268 | abs = data[1]; | |
269 | } | |
270 | else if (looking_for & L_32) | |
271 | { | |
272 | int i = len >> 1; | |
0ef9643e | 273 | |
c906108c SS |
274 | abs = (data[i] << 24) |
275 | | (data[i + 1] << 16) | |
276 | | (data[i + 2] << 8) | |
277 | | (data[i + 3]); | |
278 | ||
279 | plen = 32; | |
280 | } | |
281 | else if (looking_for & L_24) | |
282 | { | |
283 | int i = len >> 1; | |
0ef9643e | 284 | |
c906108c SS |
285 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
286 | plen = 24; | |
287 | } | |
288 | else if (looking_for & IGNORE) | |
289 | { | |
0ef9643e | 290 | ; |
c906108c SS |
291 | } |
292 | else if (looking_for & DISPREG) | |
293 | { | |
294 | rdisp = thisnib & 0x7; | |
295 | } | |
296 | else if (looking_for & KBIT) | |
297 | { | |
298 | switch (thisnib) | |
299 | { | |
300 | case 9: | |
301 | abs = 4; | |
302 | break; | |
303 | case 8: | |
304 | abs = 2; | |
305 | break; | |
306 | case 0: | |
307 | abs = 1; | |
308 | break; | |
0a17cd59 AC |
309 | default: |
310 | goto fail; | |
c906108c SS |
311 | } |
312 | } | |
313 | else if (looking_for & L_8) | |
314 | { | |
315 | plen = 8; | |
316 | ||
317 | if (looking_for & PCREL) | |
318 | { | |
319 | abs = SEXTCHAR (data[len >> 1]); | |
320 | } | |
321 | else if (looking_for & ABS8MEM) | |
322 | { | |
323 | plen = 8; | |
324 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 325 | abs |= data[len >> 1] & 0xff; |
c906108c | 326 | } |
0ef9643e | 327 | else |
c906108c SS |
328 | { |
329 | abs = data[len >> 1] & 0xff; | |
330 | } | |
331 | } | |
332 | else if (looking_for & L_3) | |
333 | { | |
334 | plen = 3; | |
335 | ||
336 | bit = thisnib; | |
337 | } | |
338 | else if (looking_for == E) | |
339 | { | |
340 | dst->op = q; | |
341 | ||
0ef9643e | 342 | /* Fill in the args. */ |
c906108c SS |
343 | { |
344 | op_type *args = q->args.nib; | |
345 | int hadone = 0; | |
346 | ||
347 | while (*args != E) | |
348 | { | |
349 | int x = *args; | |
350 | int rn = (x & DST) ? rd : rs; | |
351 | ea_type *p; | |
352 | ||
353 | if (x & DST) | |
0ef9643e | 354 | p = &(dst->dst); |
c906108c | 355 | else |
0ef9643e | 356 | p = &(dst->src); |
c906108c | 357 | |
0ef9643e | 358 | if (x & L_3) |
c906108c SS |
359 | { |
360 | p->type = X (OP_IMM, size); | |
361 | p->literal = bit; | |
362 | } | |
363 | else if (x & (IMM | KBIT | DBIT)) | |
364 | { | |
365 | p->type = X (OP_IMM, size); | |
366 | p->literal = abs; | |
367 | } | |
368 | else if (x & REG) | |
369 | { | |
6d028502 KH |
370 | /* Reset the size. |
371 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
372 | |
373 | size = bitfrom (x); | |
374 | p->type = X (OP_REG, size); | |
375 | p->reg = rn; | |
376 | } | |
377 | else if (x & INC) | |
378 | { | |
379 | p->type = X (OP_INC, size); | |
380 | p->reg = rn & 0x7; | |
381 | } | |
382 | else if (x & DEC) | |
383 | { | |
384 | p->type = X (OP_DEC, size); | |
385 | p->reg = rn & 0x7; | |
386 | } | |
387 | else if (x & IND) | |
388 | { | |
389 | p->type = X (OP_DISP, size); | |
390 | p->reg = rn & 0x7; | |
391 | p->literal = 0; | |
392 | } | |
393 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
394 | { | |
395 | p->type = X (OP_DISP, size); | |
396 | p->literal = abs; | |
397 | p->reg = 8; | |
398 | } | |
399 | else if (x & MEMIND) | |
400 | { | |
401 | p->type = X (OP_MEM, size); | |
402 | p->literal = abs; | |
403 | } | |
404 | else if (x & PCREL) | |
405 | { | |
406 | p->type = X (OP_PCREL, size); | |
407 | p->literal = abs + addr + 2; | |
408 | if (x & L_16) | |
409 | p->literal += 2; | |
410 | } | |
411 | else if (x & ABSJMP) | |
412 | { | |
413 | p->type = X (OP_IMM, SP); | |
414 | p->literal = abs; | |
415 | } | |
416 | else if (x & DISP) | |
417 | { | |
418 | p->type = X (OP_DISP, size); | |
419 | p->literal = abs; | |
420 | p->reg = rdisp & 0x7; | |
421 | } | |
422 | else if (x & CCR) | |
423 | { | |
424 | p->type = OP_CCR; | |
425 | } | |
fc974602 AV |
426 | else if (x & EXR) |
427 | { | |
428 | p->type = OP_EXR; | |
429 | } | |
c906108c SS |
430 | else |
431 | printf ("Hmmmm %x", x); | |
432 | ||
433 | args++; | |
434 | } | |
435 | } | |
436 | ||
0ef9643e JL |
437 | /* But a jmp or a jsr gets automagically lvalued, |
438 | since we branch to their address not their | |
439 | contents. */ | |
c906108c SS |
440 | if (q->how == O (O_JSR, SB) |
441 | || q->how == O (O_JMP, SB)) | |
442 | { | |
443 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
444 | } | |
445 | ||
446 | if (dst->dst.type == -1) | |
447 | dst->dst = dst->src; | |
448 | ||
449 | dst->opcode = q->how; | |
450 | dst->cycles = q->time; | |
451 | ||
bf174226 V |
452 | /* And a jsr to these locations are turned into magic |
453 | traps. */ | |
c906108c SS |
454 | |
455 | if (dst->opcode == O (O_JSR, SB)) | |
456 | { | |
bf174226 | 457 | switch (dst->src.literal) |
c906108c | 458 | { |
bf174226 V |
459 | case 0xc5: |
460 | dst->opcode = O (O_SYS_OPEN, SB); | |
461 | break; | |
462 | case 0xc6: | |
463 | dst->opcode = O (O_SYS_READ, SB); | |
464 | break; | |
465 | case 0xc7: | |
466 | dst->opcode = O (O_SYS_WRITE, SB); | |
467 | break; | |
468 | case 0xc8: | |
469 | dst->opcode = O (O_SYS_LSEEK, SB); | |
470 | break; | |
471 | case 0xc9: | |
472 | dst->opcode = O (O_SYS_CLOSE, SB); | |
473 | break; | |
474 | case 0xca: | |
475 | dst->opcode = O (O_SYS_STAT, SB); | |
476 | break; | |
477 | case 0xcb: | |
478 | dst->opcode = O (O_SYS_FSTAT, SB); | |
479 | break; | |
c906108c | 480 | } |
bf174226 | 481 | /* End of Processing for system calls. */ |
c906108c SS |
482 | } |
483 | ||
484 | dst->next_pc = addr + len / 2; | |
485 | return; | |
486 | } | |
487 | else | |
98ecb0a7 | 488 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
489 | } |
490 | ||
491 | len++; | |
492 | nib++; | |
493 | } | |
494 | ||
495 | fail: | |
6d028502 | 496 | ; |
c906108c SS |
497 | } |
498 | ||
0ef9643e | 499 | /* Fell off the end. */ |
c906108c SS |
500 | dst->opcode = O (O_ILL, SB); |
501 | } | |
502 | ||
c906108c | 503 | static void |
a4f27e3e | 504 | compile (int pc) |
c906108c SS |
505 | { |
506 | int idx; | |
507 | ||
2ea716f6 | 508 | /* Find the next cache entry to use. */ |
c906108c SS |
509 | idx = cpu.cache_top + 1; |
510 | cpu.compiles++; | |
511 | if (idx >= cpu.csize) | |
512 | { | |
513 | idx = 1; | |
514 | } | |
515 | cpu.cache_top = idx; | |
516 | ||
2ea716f6 | 517 | /* Throw away its old meaning. */ |
c906108c SS |
518 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; |
519 | ||
2ea716f6 | 520 | /* Set to new address. */ |
c906108c SS |
521 | cpu.cache[idx].oldpc = pc; |
522 | ||
2ea716f6 | 523 | /* Fill in instruction info. */ |
c906108c SS |
524 | decode (pc, cpu.memory + pc, cpu.cache + idx); |
525 | ||
2ea716f6 | 526 | /* Point to new cache entry. */ |
c906108c SS |
527 | cpu.cache_idx[pc] = idx; |
528 | } | |
529 | ||
530 | ||
531 | static unsigned char *breg[18]; | |
532 | static unsigned short *wreg[18]; | |
533 | static unsigned int *lreg[18]; | |
534 | ||
535 | #define GET_B_REG(x) *(breg[x]) | |
536 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
537 | #define GET_W_REG(x) *(wreg[x]) | |
538 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
539 | ||
540 | #define GET_L_REG(x) *(lreg[x]) | |
541 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
542 | ||
543 | #define GET_MEMORY_L(x) \ | |
544 | (x < memory_size \ | |
545 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
546 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
547 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
548 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
549 | ||
550 | #define GET_MEMORY_W(x) \ | |
551 | (x < memory_size \ | |
552 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
553 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
554 | ||
555 | ||
556 | #define GET_MEMORY_B(x) \ | |
557 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
558 | ||
559 | #define SET_MEMORY_L(x,y) \ | |
560 | { register unsigned char *_p; register int __y = y; \ | |
561 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
562 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
563 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
564 | ||
565 | #define SET_MEMORY_W(x,y) \ | |
566 | { register unsigned char *_p; register int __y = y; \ | |
567 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
568 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
569 | ||
570 | #define SET_MEMORY_B(x,y) \ | |
571 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
572 | ||
a4f27e3e MS |
573 | static int |
574 | fetch (ea_type *arg) | |
c906108c SS |
575 | { |
576 | int rn = arg->reg; | |
577 | int abs = arg->literal; | |
578 | int r; | |
579 | int t; | |
580 | ||
581 | switch (arg->type) | |
582 | { | |
583 | case X (OP_REG, SB): | |
584 | return GET_B_REG (rn); | |
585 | case X (OP_REG, SW): | |
586 | return GET_W_REG (rn); | |
587 | case X (OP_REG, SL): | |
588 | return GET_L_REG (rn); | |
589 | case X (OP_IMM, SB): | |
590 | case X (OP_IMM, SW): | |
591 | case X (OP_IMM, SL): | |
592 | return abs; | |
593 | case X (OP_DEC, SB): | |
594 | abort (); | |
595 | ||
596 | case X (OP_INC, SB): | |
597 | t = GET_L_REG (rn); | |
598 | t &= cpu.mask; | |
599 | r = GET_MEMORY_B (t); | |
600 | t++; | |
601 | t = t & cpu.mask; | |
602 | SET_L_REG (rn, t); | |
603 | return r; | |
604 | break; | |
605 | case X (OP_INC, SW): | |
606 | t = GET_L_REG (rn); | |
607 | t &= cpu.mask; | |
608 | r = GET_MEMORY_W (t); | |
609 | t += 2; | |
610 | t = t & cpu.mask; | |
611 | SET_L_REG (rn, t); | |
612 | return r; | |
613 | case X (OP_INC, SL): | |
614 | t = GET_L_REG (rn); | |
615 | t &= cpu.mask; | |
616 | r = GET_MEMORY_L (t); | |
617 | ||
618 | t += 4; | |
619 | t = t & cpu.mask; | |
620 | SET_L_REG (rn, t); | |
621 | return r; | |
622 | ||
623 | case X (OP_DISP, SB): | |
624 | t = GET_L_REG (rn) + abs; | |
625 | t &= cpu.mask; | |
626 | return GET_MEMORY_B (t); | |
627 | ||
628 | case X (OP_DISP, SW): | |
629 | t = GET_L_REG (rn) + abs; | |
630 | t &= cpu.mask; | |
631 | return GET_MEMORY_W (t); | |
632 | ||
633 | case X (OP_DISP, SL): | |
634 | t = GET_L_REG (rn) + abs; | |
635 | t &= cpu.mask; | |
636 | return GET_MEMORY_L (t); | |
637 | ||
638 | case X (OP_MEM, SL): | |
639 | t = GET_MEMORY_L (abs); | |
640 | t &= cpu.mask; | |
641 | return t; | |
642 | ||
643 | case X (OP_MEM, SW): | |
644 | t = GET_MEMORY_W (abs); | |
645 | t &= cpu.mask; | |
646 | return t; | |
647 | ||
648 | default: | |
3b02cf92 | 649 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
650 | |
651 | } | |
652 | } | |
653 | ||
654 | ||
de9b1892 | 655 | static void |
a4f27e3e | 656 | store (ea_type *arg, int n) |
c906108c SS |
657 | { |
658 | int rn = arg->reg; | |
659 | int abs = arg->literal; | |
660 | int t; | |
661 | ||
662 | switch (arg->type) | |
663 | { | |
664 | case X (OP_REG, SB): | |
665 | SET_B_REG (rn, n); | |
666 | break; | |
667 | case X (OP_REG, SW): | |
668 | SET_W_REG (rn, n); | |
669 | break; | |
670 | case X (OP_REG, SL): | |
671 | SET_L_REG (rn, n); | |
672 | break; | |
673 | ||
674 | case X (OP_DEC, SB): | |
675 | t = GET_L_REG (rn) - 1; | |
676 | t &= cpu.mask; | |
677 | SET_L_REG (rn, t); | |
678 | SET_MEMORY_B (t, n); | |
679 | ||
680 | break; | |
681 | case X (OP_DEC, SW): | |
682 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
683 | SET_L_REG (rn, t); | |
684 | SET_MEMORY_W (t, n); | |
685 | break; | |
686 | ||
687 | case X (OP_DEC, SL): | |
688 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
689 | SET_L_REG (rn, t); | |
690 | SET_MEMORY_L (t, n); | |
691 | break; | |
692 | ||
693 | case X (OP_DISP, SB): | |
694 | t = GET_L_REG (rn) + abs; | |
695 | t &= cpu.mask; | |
696 | SET_MEMORY_B (t, n); | |
697 | break; | |
698 | ||
699 | case X (OP_DISP, SW): | |
700 | t = GET_L_REG (rn) + abs; | |
701 | t &= cpu.mask; | |
702 | SET_MEMORY_W (t, n); | |
703 | break; | |
704 | ||
705 | case X (OP_DISP, SL): | |
706 | t = GET_L_REG (rn) + abs; | |
707 | t &= cpu.mask; | |
708 | SET_MEMORY_L (t, n); | |
709 | break; | |
710 | default: | |
711 | abort (); | |
712 | } | |
713 | } | |
714 | ||
715 | ||
716 | static union | |
717 | { | |
718 | short int i; | |
719 | struct | |
720 | { | |
721 | char low; | |
722 | char high; | |
723 | } | |
724 | u; | |
725 | } | |
726 | ||
727 | littleendian; | |
728 | ||
de9b1892 | 729 | static void |
a4f27e3e | 730 | init_pointers (void) |
c906108c SS |
731 | { |
732 | static int init; | |
733 | ||
734 | if (!init) | |
735 | { | |
736 | int i; | |
737 | ||
738 | init = 1; | |
739 | littleendian.i = 1; | |
740 | ||
a8cdafbd AV |
741 | if (h8300smode) |
742 | memory_size = H8300S_MSIZE; | |
743 | else if (h8300hmode) | |
c906108c SS |
744 | memory_size = H8300H_MSIZE; |
745 | else | |
746 | memory_size = H8300_MSIZE; | |
747 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
748 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
749 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
750 | ||
2ea716f6 | 751 | /* `msize' must be a power of two. */ |
c906108c SS |
752 | if ((memory_size & (memory_size - 1)) != 0) |
753 | abort (); | |
754 | cpu.mask = memory_size - 1; | |
755 | ||
756 | for (i = 0; i < 9; i++) | |
757 | { | |
758 | cpu.regs[i] = 0; | |
759 | } | |
760 | ||
761 | for (i = 0; i < 8; i++) | |
762 | { | |
763 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
764 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
765 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
766 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
767 | cpu.regs[i] = 0x00112233; | |
768 | while (p < e) | |
769 | { | |
770 | if (*p == 0x22) | |
771 | { | |
772 | breg[i] = p; | |
773 | } | |
774 | if (*p == 0x33) | |
775 | { | |
776 | breg[i + 8] = p; | |
777 | } | |
778 | p++; | |
779 | } | |
ec38ce99 | 780 | wreg[i] = wreg[i + 8] = 0; |
c906108c SS |
781 | while (q < u) |
782 | { | |
783 | if (*q == 0x2233) | |
784 | { | |
785 | wreg[i] = q; | |
786 | } | |
787 | if (*q == 0x0011) | |
788 | { | |
789 | wreg[i + 8] = q; | |
790 | } | |
791 | q++; | |
792 | } | |
ec38ce99 KH |
793 | if (wreg[i] == 0 || wreg[i + 8] == 0) |
794 | abort (); | |
c906108c SS |
795 | cpu.regs[i] = 0; |
796 | lreg[i] = &cpu.regs[i]; | |
797 | } | |
798 | ||
799 | lreg[8] = &cpu.regs[8]; | |
800 | ||
2ea716f6 | 801 | /* Initialize the seg registers. */ |
c906108c SS |
802 | if (!cpu.cache) |
803 | sim_set_simcache_size (CSIZE); | |
804 | } | |
805 | } | |
806 | ||
807 | static void | |
a4f27e3e | 808 | control_c (int sig) |
c906108c SS |
809 | { |
810 | cpu.state = SIM_STATE_STOPPED; | |
811 | cpu.exception = SIGINT; | |
812 | } | |
813 | ||
814 | #define C (c != 0) | |
815 | #define Z (nz == 0) | |
816 | #define V (v != 0) | |
817 | #define N (n != 0) | |
f6225c96 AV |
818 | #define U (u != 0) |
819 | #define H (h != 0) | |
820 | #define UI (ui != 0) | |
821 | #define I (intMaskBit != 0) | |
c906108c SS |
822 | |
823 | static int | |
a4f27e3e | 824 | mop (decoded_inst *code, int bsize, int sign) |
c906108c SS |
825 | { |
826 | int multiplier; | |
827 | int multiplicand; | |
828 | int result; | |
829 | int n, nz; | |
830 | ||
831 | if (sign) | |
832 | { | |
833 | multiplicand = | |
834 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
835 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
836 | multiplier = | |
837 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
838 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
839 | } | |
840 | else | |
841 | { | |
842 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
843 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
844 | multiplier = | |
845 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
846 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
847 | ||
848 | } | |
849 | result = multiplier * multiplicand; | |
850 | ||
851 | if (sign) | |
852 | { | |
853 | n = result & (bsize ? 0x8000 : 0x80000000); | |
854 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
855 | } | |
856 | if (bsize) | |
857 | { | |
858 | SET_W_REG (code->dst.reg, result); | |
859 | } | |
860 | else | |
861 | { | |
862 | SET_L_REG (code->dst.reg, result); | |
863 | } | |
de9b1892 KH |
864 | #if 0 |
865 | return ((n == 1) << 1) | (nz == 1); | |
866 | #endif | |
c906108c SS |
867 | } |
868 | ||
869 | #define ONOT(name, how) \ | |
d1335144 | 870 | case O (name, SB): \ |
c906108c SS |
871 | { \ |
872 | int t; \ | |
873 | int hm = 0x80; \ | |
874 | rd = GET_B_REG (code->src.reg); \ | |
875 | how; \ | |
876 | goto shift8; \ | |
877 | } \ | |
d1335144 | 878 | case O (name, SW): \ |
c906108c SS |
879 | { \ |
880 | int t; \ | |
881 | int hm = 0x8000; \ | |
882 | rd = GET_W_REG (code->src.reg); \ | |
883 | how; \ | |
884 | goto shift16; \ | |
885 | } \ | |
d1335144 | 886 | case O (name, SL): \ |
c906108c SS |
887 | { \ |
888 | int t; \ | |
889 | int hm = 0x80000000; \ | |
890 | rd = GET_L_REG (code->src.reg); \ | |
891 | how; \ | |
892 | goto shift32; \ | |
893 | } | |
894 | ||
895 | #define OSHIFTS(name, how1, how2) \ | |
d1335144 | 896 | case O (name, SB): \ |
c906108c SS |
897 | { \ |
898 | int t; \ | |
899 | int hm = 0x80; \ | |
900 | rd = GET_B_REG (code->src.reg); \ | |
901 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
902 | { \ | |
903 | how1; \ | |
904 | } \ | |
905 | else \ | |
906 | { \ | |
907 | how2; \ | |
908 | } \ | |
909 | goto shift8; \ | |
910 | } \ | |
d1335144 | 911 | case O (name, SW): \ |
c906108c SS |
912 | { \ |
913 | int t; \ | |
914 | int hm = 0x8000; \ | |
915 | rd = GET_W_REG (code->src.reg); \ | |
916 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
917 | { \ | |
918 | how1; \ | |
919 | } \ | |
920 | else \ | |
921 | { \ | |
922 | how2; \ | |
923 | } \ | |
924 | goto shift16; \ | |
925 | } \ | |
d1335144 | 926 | case O (name, SL): \ |
c906108c SS |
927 | { \ |
928 | int t; \ | |
929 | int hm = 0x80000000; \ | |
930 | rd = GET_L_REG (code->src.reg); \ | |
931 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
932 | { \ | |
933 | how1; \ | |
934 | } \ | |
935 | else \ | |
936 | { \ | |
937 | how2; \ | |
938 | } \ | |
939 | goto shift32; \ | |
940 | } | |
941 | ||
942 | #define OBITOP(name,f, s, op) \ | |
d1335144 | 943 | case O (name, SB): \ |
c906108c SS |
944 | { \ |
945 | int m; \ | |
946 | int b; \ | |
947 | if (f) ea = fetch (&code->dst); \ | |
d1335144 | 948 | m=1<< fetch (&code->src); \ |
c906108c | 949 | op; \ |
d1335144 | 950 | if (s) store (&code->dst,ea); goto next; \ |
c906108c SS |
951 | } |
952 | ||
953 | int | |
837fd61c | 954 | sim_stop (SIM_DESC sd) |
c906108c SS |
955 | { |
956 | cpu.state = SIM_STATE_STOPPED; | |
957 | cpu.exception = SIGINT; | |
958 | return 1; | |
959 | } | |
960 | ||
6147b1f6 AV |
961 | #define R0_REGNUM 0 |
962 | #define R1_REGNUM 1 | |
963 | #define R2_REGNUM 2 | |
964 | #define R3_REGNUM 3 | |
965 | #define R4_REGNUM 4 | |
966 | #define R5_REGNUM 5 | |
967 | #define R6_REGNUM 6 | |
968 | #define R7_REGNUM 7 | |
969 | ||
970 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
971 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
972 | * stack frame */ | |
973 | ||
974 | #define CCR_REGNUM 8 /* Contains processor status */ | |
975 | #define PC_REGNUM 9 /* Contains program counter */ | |
976 | ||
977 | #define CYCLE_REGNUM 10 | |
978 | ||
979 | #define EXR_REGNUM 11 | |
980 | #define INST_REGNUM 12 | |
981 | #define TICK_REGNUM 13 | |
982 | ||
c906108c | 983 | void |
a4f27e3e | 984 | sim_resume (SIM_DESC sd, int step, int siggnal) |
c906108c SS |
985 | { |
986 | static int init1; | |
987 | int cycles = 0; | |
988 | int insts = 0; | |
989 | int tick_start = get_now (); | |
990 | void (*prev) (); | |
991 | int poll_count = 0; | |
992 | int res; | |
993 | int tmp; | |
994 | int rd; | |
995 | int ea; | |
996 | int bit; | |
997 | int pc; | |
f6225c96 | 998 | int c, nz, v, n, u, h, ui, intMaskBit; |
fc974602 | 999 | int trace, intMask; |
c906108c SS |
1000 | int oldmask; |
1001 | init_pointers (); | |
1002 | ||
1003 | prev = signal (SIGINT, control_c); | |
1004 | ||
1005 | if (step) | |
1006 | { | |
1007 | cpu.state = SIM_STATE_STOPPED; | |
1008 | cpu.exception = SIGTRAP; | |
1009 | } | |
1010 | else | |
1011 | { | |
1012 | cpu.state = SIM_STATE_RUNNING; | |
1013 | cpu.exception = 0; | |
1014 | } | |
1015 | ||
1016 | pc = cpu.pc; | |
1017 | ||
1018 | /* The PC should never be odd. */ | |
1019 | if (pc & 0x1) | |
1020 | abort (); | |
1021 | ||
1022 | GETSR (); | |
fc974602 AV |
1023 | GETEXR (); |
1024 | ||
c906108c SS |
1025 | oldmask = cpu.mask; |
1026 | if (!h8300hmode) | |
1027 | cpu.mask = 0xffff; | |
1028 | do | |
1029 | { | |
1030 | int cidx; | |
1031 | decoded_inst *code; | |
1032 | ||
1033 | top: | |
1034 | cidx = cpu.cache_idx[pc]; | |
1035 | code = cpu.cache + cidx; | |
1036 | ||
1037 | ||
1038 | #define ALUOP(STORE, NAME, HOW) \ | |
d0fe2f7e KH |
1039 | case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \ |
1040 | case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \ | |
1041 | case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32; | |
c906108c SS |
1042 | |
1043 | ||
d0fe2f7e KH |
1044 | #define LOGOP(NAME, HOW) \ |
1045 | case O (NAME, SB): HOW; goto log8; \ | |
1046 | case O (NAME, SW): HOW; goto log16; \ | |
1047 | case O (NAME, SL): HOW; goto log32; | |
c906108c SS |
1048 | |
1049 | ||
1050 | ||
1051 | #if ADEBUG | |
1052 | if (debug) | |
1053 | { | |
1054 | printf ("%x %d %s\n", pc, code->opcode, | |
1055 | code->op ? code->op->name : "**"); | |
1056 | } | |
1057 | cpu.stats[code->opcode]++; | |
1058 | ||
1059 | #endif | |
1060 | ||
3b02cf92 | 1061 | if (code->opcode) |
c3f4437e KH |
1062 | { |
1063 | cycles += code->cycles; | |
1064 | insts++; | |
1065 | } | |
3b02cf92 | 1066 | |
c906108c SS |
1067 | switch (code->opcode) |
1068 | { | |
1069 | case 0: | |
1070 | /* | |
1071 | * This opcode is a fake for when we get to an | |
1072 | * instruction which hasnt been compiled | |
1073 | */ | |
1074 | compile (pc); | |
1075 | goto top; | |
1076 | break; | |
1077 | ||
1078 | ||
1079 | case O (O_SUBX, SB): | |
1080 | rd = fetch (&code->dst); | |
1081 | ea = fetch (&code->src); | |
1082 | ea = -(ea + C); | |
1083 | res = rd + ea; | |
1084 | goto alu8; | |
1085 | ||
1086 | case O (O_ADDX, SB): | |
1087 | rd = fetch (&code->dst); | |
1088 | ea = fetch (&code->src); | |
1089 | ea = C + ea; | |
1090 | res = rd + ea; | |
1091 | goto alu8; | |
1092 | ||
d1335144 KH |
1093 | #define EA ea = fetch (&code->src); |
1094 | #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst); | |
c906108c SS |
1095 | |
1096 | ALUOP (1, O_SUB, RD_EA; | |
1097 | ea = -ea; | |
1098 | res = rd + ea); | |
1099 | ALUOP (1, O_NEG, EA; | |
1100 | ea = -ea; | |
1101 | rd = 0; | |
1102 | res = rd + ea); | |
1103 | ||
1104 | case O (O_ADD, SB): | |
1105 | rd = GET_B_REG (code->dst.reg); | |
1106 | ea = fetch (&code->src); | |
1107 | res = rd + ea; | |
1108 | goto alu8; | |
1109 | case O (O_ADD, SW): | |
1110 | rd = GET_W_REG (code->dst.reg); | |
1111 | ea = fetch (&code->src); | |
1112 | res = rd + ea; | |
1113 | goto alu16; | |
1114 | case O (O_ADD, SL): | |
1115 | rd = GET_L_REG (code->dst.reg); | |
1116 | ea = fetch (&code->src); | |
1117 | res = rd + ea; | |
1118 | goto alu32; | |
1119 | ||
1120 | ||
1121 | LOGOP (O_AND, RD_EA; | |
1122 | res = rd & ea); | |
1123 | ||
1124 | LOGOP (O_OR, RD_EA; | |
1125 | res = rd | ea); | |
1126 | ||
1127 | LOGOP (O_XOR, RD_EA; | |
1128 | res = rd ^ ea); | |
1129 | ||
1130 | ||
1131 | case O (O_MOV_TO_MEM, SB): | |
1132 | res = GET_B_REG (code->src.reg); | |
1133 | goto log8; | |
1134 | case O (O_MOV_TO_MEM, SW): | |
1135 | res = GET_W_REG (code->src.reg); | |
1136 | goto log16; | |
1137 | case O (O_MOV_TO_MEM, SL): | |
1138 | res = GET_L_REG (code->src.reg); | |
1139 | goto log32; | |
1140 | ||
1141 | ||
1142 | case O (O_MOV_TO_REG, SB): | |
1143 | res = fetch (&code->src); | |
1144 | SET_B_REG (code->dst.reg, res); | |
1145 | goto just_flags_log8; | |
1146 | case O (O_MOV_TO_REG, SW): | |
1147 | res = fetch (&code->src); | |
1148 | SET_W_REG (code->dst.reg, res); | |
1149 | goto just_flags_log16; | |
1150 | case O (O_MOV_TO_REG, SL): | |
1151 | res = fetch (&code->src); | |
1152 | SET_L_REG (code->dst.reg, res); | |
1153 | goto just_flags_log32; | |
1154 | ||
6147b1f6 AV |
1155 | case O (O_EEPMOV, SB): |
1156 | case O (O_EEPMOV, SW): | |
d0fe2f7e | 1157 | if (h8300hmode || h8300smode) |
c3f4437e | 1158 | { |
d0fe2f7e KH |
1159 | register unsigned char *_src, *_dst; |
1160 | unsigned int count = ((code->opcode == O (O_EEPMOV, SW)) | |
1161 | ? cpu.regs[R4_REGNUM] & 0xffff | |
1162 | : cpu.regs[R4_REGNUM] & 0xff); | |
1163 | ||
1164 | _src = (cpu.regs[R5_REGNUM] < memory_size | |
1165 | ? cpu.memory + cpu.regs[R5_REGNUM] | |
1166 | : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff)); | |
1167 | if ((_src + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1168 | { |
d0fe2f7e | 1169 | if ((_src + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1170 | goto illegal; |
1171 | } | |
d0fe2f7e KH |
1172 | _dst = (cpu.regs[R6_REGNUM] < memory_size |
1173 | ? cpu.memory + cpu.regs[R6_REGNUM] | |
1174 | : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff)); | |
1175 | if ((_dst + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1176 | { |
d0fe2f7e | 1177 | if ((_dst + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1178 | goto illegal; |
1179 | } | |
d0fe2f7e | 1180 | memcpy (_dst, _src, count); |
c3f4437e | 1181 | |
d0fe2f7e KH |
1182 | cpu.regs[R5_REGNUM] += count; |
1183 | cpu.regs[R6_REGNUM] += count; | |
1184 | cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW)) | |
1185 | ? (~0xffff) : (~0xff)); | |
1186 | cycles += 2 * count; | |
c3f4437e KH |
1187 | goto next; |
1188 | } | |
1189 | goto illegal; | |
c906108c SS |
1190 | |
1191 | case O (O_ADDS, SL): | |
1192 | SET_L_REG (code->dst.reg, | |
1193 | GET_L_REG (code->dst.reg) | |
1194 | + code->src.literal); | |
1195 | ||
1196 | goto next; | |
1197 | ||
1198 | case O (O_SUBS, SL): | |
1199 | SET_L_REG (code->dst.reg, | |
1200 | GET_L_REG (code->dst.reg) | |
1201 | - code->src.literal); | |
1202 | goto next; | |
1203 | ||
1204 | case O (O_CMP, SB): | |
1205 | rd = fetch (&code->dst); | |
1206 | ea = fetch (&code->src); | |
1207 | ea = -ea; | |
1208 | res = rd + ea; | |
1209 | goto just_flags_alu8; | |
1210 | ||
1211 | case O (O_CMP, SW): | |
1212 | rd = fetch (&code->dst); | |
1213 | ea = fetch (&code->src); | |
1214 | ea = -ea; | |
1215 | res = rd + ea; | |
1216 | goto just_flags_alu16; | |
1217 | ||
1218 | case O (O_CMP, SL): | |
1219 | rd = fetch (&code->dst); | |
1220 | ea = fetch (&code->src); | |
1221 | ea = -ea; | |
1222 | res = rd + ea; | |
1223 | goto just_flags_alu32; | |
1224 | ||
1225 | ||
1226 | case O (O_DEC, SB): | |
1227 | rd = GET_B_REG (code->src.reg); | |
1228 | ea = -1; | |
1229 | res = rd + ea; | |
1230 | SET_B_REG (code->src.reg, res); | |
1231 | goto just_flags_inc8; | |
1232 | ||
1233 | case O (O_DEC, SW): | |
1234 | rd = GET_W_REG (code->dst.reg); | |
1235 | ea = -code->src.literal; | |
1236 | res = rd + ea; | |
1237 | SET_W_REG (code->dst.reg, res); | |
1238 | goto just_flags_inc16; | |
1239 | ||
1240 | case O (O_DEC, SL): | |
1241 | rd = GET_L_REG (code->dst.reg); | |
1242 | ea = -code->src.literal; | |
1243 | res = rd + ea; | |
1244 | SET_L_REG (code->dst.reg, res); | |
1245 | goto just_flags_inc32; | |
1246 | ||
1247 | ||
1248 | case O (O_INC, SB): | |
1249 | rd = GET_B_REG (code->src.reg); | |
1250 | ea = 1; | |
1251 | res = rd + ea; | |
1252 | SET_B_REG (code->src.reg, res); | |
1253 | goto just_flags_inc8; | |
1254 | ||
1255 | case O (O_INC, SW): | |
1256 | rd = GET_W_REG (code->dst.reg); | |
1257 | ea = code->src.literal; | |
1258 | res = rd + ea; | |
1259 | SET_W_REG (code->dst.reg, res); | |
1260 | goto just_flags_inc16; | |
1261 | ||
1262 | case O (O_INC, SL): | |
1263 | rd = GET_L_REG (code->dst.reg); | |
1264 | ea = code->src.literal; | |
1265 | res = rd + ea; | |
1266 | SET_L_REG (code->dst.reg, res); | |
1267 | goto just_flags_inc32; | |
1268 | ||
c906108c | 1269 | #define GET_CCR(x) BUILDSR();x = cpu.ccr |
d1335144 | 1270 | #define GET_EXR(x) BUILDEXR ();x = cpu.exr |
c906108c | 1271 | |
6147b1f6 AV |
1272 | case O (O_LDC, SB): |
1273 | case O (O_LDC, SW): | |
d1335144 | 1274 | res = fetch (&code->src); |
6147b1f6 AV |
1275 | goto setc; |
1276 | case O (O_STC, SB): | |
1277 | case O (O_STC, SW): | |
d1335144 | 1278 | if (code->src.type == OP_CCR) |
c3f4437e | 1279 | { |
d1335144 | 1280 | GET_CCR (res); |
c3f4437e | 1281 | } |
d1335144 | 1282 | else if (code->src.type == OP_EXR && h8300smode) |
c3f4437e | 1283 | { |
d1335144 | 1284 | GET_EXR (res); |
c3f4437e KH |
1285 | } |
1286 | else | |
6147b1f6 AV |
1287 | goto illegal; |
1288 | store (&code->dst, res); | |
1289 | goto next; | |
1290 | ||
c906108c | 1291 | case O (O_ANDC, SB): |
d1335144 | 1292 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1293 | { |
1294 | GET_CCR (rd); | |
1295 | } | |
d1335144 | 1296 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1297 | { |
1298 | GET_EXR (rd); | |
1299 | } | |
1300 | else | |
fc974602 | 1301 | goto illegal; |
c906108c SS |
1302 | ea = code->src.literal; |
1303 | res = rd & ea; | |
1304 | goto setc; | |
1305 | ||
1306 | case O (O_ORC, SB): | |
d1335144 | 1307 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1308 | { |
1309 | GET_CCR (rd); | |
1310 | } | |
d1335144 | 1311 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1312 | { |
1313 | GET_EXR (rd); | |
1314 | } | |
1315 | else | |
fc974602 | 1316 | goto illegal; |
c906108c SS |
1317 | ea = code->src.literal; |
1318 | res = rd | ea; | |
1319 | goto setc; | |
1320 | ||
1321 | case O (O_XORC, SB): | |
d1335144 | 1322 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1323 | { |
1324 | GET_CCR (rd); | |
1325 | } | |
d1335144 | 1326 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1327 | { |
1328 | GET_EXR (rd); | |
1329 | } | |
1330 | else | |
fc974602 | 1331 | goto illegal; |
c906108c SS |
1332 | ea = code->src.literal; |
1333 | res = rd ^ ea; | |
1334 | goto setc; | |
1335 | ||
1336 | ||
1337 | case O (O_BRA, SB): | |
1338 | if (1) | |
1339 | goto condtrue; | |
1340 | goto next; | |
1341 | ||
1342 | case O (O_BRN, SB): | |
1343 | if (0) | |
1344 | goto condtrue; | |
1345 | goto next; | |
1346 | ||
1347 | case O (O_BHI, SB): | |
1348 | if ((C || Z) == 0) | |
1349 | goto condtrue; | |
1350 | goto next; | |
1351 | ||
1352 | ||
1353 | case O (O_BLS, SB): | |
1354 | if ((C || Z)) | |
1355 | goto condtrue; | |
1356 | goto next; | |
1357 | ||
1358 | case O (O_BCS, SB): | |
1359 | if ((C == 1)) | |
1360 | goto condtrue; | |
1361 | goto next; | |
1362 | ||
1363 | case O (O_BCC, SB): | |
1364 | if ((C == 0)) | |
1365 | goto condtrue; | |
1366 | goto next; | |
1367 | ||
1368 | case O (O_BEQ, SB): | |
1369 | if (Z) | |
1370 | goto condtrue; | |
1371 | goto next; | |
1372 | case O (O_BGT, SB): | |
1373 | if (((Z || (N ^ V)) == 0)) | |
1374 | goto condtrue; | |
1375 | goto next; | |
1376 | ||
1377 | ||
1378 | case O (O_BLE, SB): | |
1379 | if (((Z || (N ^ V)) == 1)) | |
1380 | goto condtrue; | |
1381 | goto next; | |
1382 | ||
1383 | case O (O_BGE, SB): | |
1384 | if ((N ^ V) == 0) | |
1385 | goto condtrue; | |
1386 | goto next; | |
1387 | case O (O_BLT, SB): | |
1388 | if ((N ^ V)) | |
1389 | goto condtrue; | |
1390 | goto next; | |
1391 | case O (O_BMI, SB): | |
1392 | if ((N)) | |
1393 | goto condtrue; | |
1394 | goto next; | |
1395 | case O (O_BNE, SB): | |
1396 | if ((Z == 0)) | |
1397 | goto condtrue; | |
1398 | goto next; | |
1399 | ||
1400 | case O (O_BPL, SB): | |
1401 | if (N == 0) | |
1402 | goto condtrue; | |
1403 | goto next; | |
1404 | case O (O_BVC, SB): | |
1405 | if ((V == 0)) | |
1406 | goto condtrue; | |
1407 | goto next; | |
1408 | case O (O_BVS, SB): | |
1409 | if ((V == 1)) | |
1410 | goto condtrue; | |
1411 | goto next; | |
1412 | ||
bf174226 V |
1413 | /* System call processing starts. */ |
1414 | case O (O_SYS_OPEN, SB): | |
c906108c | 1415 | { |
bf174226 V |
1416 | int len = 0; /* Length of filename. */ |
1417 | char *filename; /* Filename would go here. */ | |
1418 | char temp_char; /* Temporary character */ | |
1419 | int mode = 0; /* Mode bits for the file. */ | |
1420 | int open_return; /* Return value of open, file descriptor. */ | |
1421 | int i; /* Loop counter */ | |
1422 | int filename_ptr; /* Pointer to filename in cpu memory. */ | |
1423 | ||
1424 | /* Setting filename_ptr to first argument of open. */ | |
1425 | filename_ptr = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1426 | ||
1427 | /* Trying to get mode. */ | |
1428 | if (h8300hmode || h8300smode) | |
1429 | { | |
1430 | mode = GET_MEMORY_L (cpu.regs[7] + 4); | |
1431 | } | |
1432 | else | |
1433 | { | |
1434 | mode = GET_MEMORY_W (cpu.regs[7] + 2); | |
1435 | } | |
1436 | ||
1437 | /* Trying to find the length of the filename. */ | |
1438 | temp_char = GET_MEMORY_B (cpu.regs[0]); | |
1439 | ||
1440 | len = 1; | |
1441 | while (temp_char != '\0') | |
1442 | { | |
1443 | temp_char = GET_MEMORY_B (filename_ptr + len); | |
1444 | len++; | |
1445 | } | |
1446 | ||
1447 | /* Allocating space for the filename. */ | |
1448 | filename = (char *) malloc (sizeof (char) * len); | |
1449 | ||
1450 | /* String copying the filename from memory. */ | |
1451 | for (i = 0; i < len; i++) | |
1452 | { | |
1453 | temp_char = GET_MEMORY_B (filename_ptr + i); | |
1454 | filename[i] = temp_char; | |
1455 | } | |
1456 | ||
1457 | /* Callback to open and return the file descriptor. */ | |
1458 | open_return = sim_callback->open (sim_callback, filename, mode); | |
1459 | ||
1460 | /* Return value in register 0. */ | |
1461 | cpu.regs[0] = open_return; | |
1462 | ||
1463 | /* Freeing memory used for filename. */ | |
1464 | free (filename); | |
c906108c SS |
1465 | } |
1466 | goto next; | |
1467 | ||
bf174226 V |
1468 | case O (O_SYS_READ, SB): |
1469 | { | |
1470 | char *char_ptr; /* Where characters read would be stored. */ | |
1471 | int fd; /* File descriptor */ | |
1472 | int buf_size; /* BUF_SIZE parameter in read. */ | |
1473 | int i = 0; /* Temporary Loop counter */ | |
1474 | int read_return = 0; /* Return value from callback to | |
1475 | read. */ | |
1476 | ||
1477 | fd = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1478 | buf_size = h8300hmode ? GET_L_REG (2) : GET_W_REG (2); | |
1479 | ||
1480 | char_ptr = (char *) malloc (sizeof (char) * buf_size); | |
1481 | ||
1482 | /* Callback to read and return the no. of characters read. */ | |
1483 | read_return = | |
1484 | sim_callback->read (sim_callback, fd, char_ptr, buf_size); | |
1485 | ||
1486 | /* The characters read are stored in cpu memory. */ | |
1487 | for (i = 0; i < buf_size; i++) | |
1488 | { | |
1489 | SET_MEMORY_B ((cpu.regs[1] + (sizeof (char) * i)), | |
1490 | *(char_ptr + (sizeof (char) * i))); | |
1491 | } | |
1492 | ||
1493 | /* Return value in Register 0. */ | |
1494 | cpu.regs[0] = read_return; | |
1495 | ||
1496 | /* Freeing memory used as buffer. */ | |
1497 | free (char_ptr); | |
1498 | } | |
1499 | goto next; | |
1500 | ||
1501 | case O (O_SYS_WRITE, SB): | |
1502 | { | |
1503 | int fd; /* File descriptor */ | |
1504 | char temp_char; /* Temporary character */ | |
1505 | int len; /* Length of write, Parameter II to write. */ | |
1506 | int char_ptr; /* Character Pointer, Parameter I of write. */ | |
1507 | char *ptr; /* Where characters to be written are stored. | |
1508 | */ | |
1509 | int write_return; /* Return value from callback to write. */ | |
1510 | int i = 0; /* Loop counter */ | |
1511 | ||
1512 | fd = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1513 | char_ptr = h8300hmode ? GET_L_REG (1) : GET_W_REG (1); | |
1514 | len = h8300hmode ? GET_L_REG (2) : GET_W_REG (2); | |
1515 | ||
1516 | /* Allocating space for the characters to be written. */ | |
1517 | ptr = (char *) malloc (sizeof (char) * len); | |
1518 | ||
1519 | /* Fetching the characters from cpu memory. */ | |
1520 | for (i = 0; i < len; i++) | |
1521 | { | |
1522 | temp_char = GET_MEMORY_B (char_ptr + i); | |
1523 | ptr[i] = temp_char; | |
1524 | } | |
1525 | ||
1526 | /* Callback write and return the no. of characters written. */ | |
1527 | write_return = sim_callback->write (sim_callback, fd, ptr, len); | |
1528 | ||
1529 | /* Return value in Register 0. */ | |
1530 | cpu.regs[0] = write_return; | |
1531 | ||
1532 | /* Freeing memory used as buffer. */ | |
1533 | free (ptr); | |
1534 | } | |
1535 | goto next; | |
1536 | ||
1537 | case O (O_SYS_LSEEK, SB): | |
1538 | { | |
1539 | int fd; /* File descriptor */ | |
1540 | int offset; /* Offset */ | |
1541 | int origin; /* Origin */ | |
1542 | int lseek_return; /* Return value from callback to lseek. */ | |
1543 | ||
1544 | fd = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1545 | offset = h8300hmode ? GET_L_REG (1) : GET_W_REG (1); | |
1546 | origin = h8300hmode ? GET_L_REG (2) : GET_W_REG (2); | |
1547 | ||
1548 | /* Callback lseek and return offset. */ | |
1549 | lseek_return = | |
1550 | sim_callback->lseek (sim_callback, fd, offset, origin); | |
1551 | ||
1552 | /* Return value in register 0. */ | |
1553 | cpu.regs[0] = lseek_return; | |
1554 | } | |
1555 | goto next; | |
1556 | ||
1557 | case O (O_SYS_CLOSE, SB): | |
1558 | { | |
1559 | int fd; /* File descriptor */ | |
1560 | int close_return; /* Return value from callback to close. */ | |
1561 | ||
1562 | fd = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1563 | ||
1564 | /* Callback close and return. */ | |
1565 | close_return = sim_callback->close (sim_callback, fd); | |
1566 | ||
1567 | /* Return value in register 0. */ | |
1568 | cpu.regs[0] = close_return; | |
1569 | } | |
1570 | goto next; | |
1571 | ||
1572 | case O (O_SYS_FSTAT, SB): | |
1573 | { | |
1574 | int fd; /* File descriptor */ | |
1575 | struct stat stat_rec; /* Stat record */ | |
1576 | int fstat_return; /* Return value from callback to stat. */ | |
1577 | int stat_ptr; /* Pointer to stat record. */ | |
1578 | char *temp_stat_ptr; /* Temporary stat_rec pointer. */ | |
1579 | ||
1580 | fd = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1581 | ||
1582 | /* Setting stat_ptr to second argument of stat. */ | |
1583 | stat_ptr = h8300hmode ? GET_L_REG (1) : GET_W_REG (1); | |
1584 | ||
1585 | /* Callback stat and return. */ | |
1586 | fstat_return = sim_callback->fstat (sim_callback, fd, &stat_rec); | |
1587 | ||
1588 | /* Have stat_ptr point to starting of stat_rec. */ | |
1589 | temp_stat_ptr = (char *) (&stat_rec); | |
1590 | ||
1591 | /* Setting up the stat structure returned. */ | |
1592 | SET_MEMORY_W (stat_ptr, stat_rec.st_dev); | |
1593 | stat_ptr += 2; | |
1594 | SET_MEMORY_W (stat_ptr, stat_rec.st_ino); | |
1595 | stat_ptr += 2; | |
1596 | SET_MEMORY_L (stat_ptr, stat_rec.st_mode); | |
1597 | stat_ptr += 4; | |
1598 | SET_MEMORY_W (stat_ptr, stat_rec.st_nlink); | |
1599 | stat_ptr += 2; | |
1600 | SET_MEMORY_W (stat_ptr, stat_rec.st_uid); | |
1601 | stat_ptr += 2; | |
1602 | SET_MEMORY_W (stat_ptr, stat_rec.st_gid); | |
1603 | stat_ptr += 2; | |
1604 | SET_MEMORY_W (stat_ptr, stat_rec.st_rdev); | |
1605 | stat_ptr += 2; | |
1606 | SET_MEMORY_L (stat_ptr, stat_rec.st_size); | |
1607 | stat_ptr += 4; | |
1608 | SET_MEMORY_L (stat_ptr, stat_rec.st_atime); | |
1609 | stat_ptr += 8; | |
1610 | SET_MEMORY_L (stat_ptr, stat_rec.st_mtime); | |
1611 | stat_ptr += 8; | |
1612 | SET_MEMORY_L (stat_ptr, stat_rec.st_ctime); | |
1613 | ||
1614 | /* Return value in register 0. */ | |
1615 | cpu.regs[0] = fstat_return; | |
1616 | } | |
1617 | goto next; | |
1618 | ||
1619 | case O (O_SYS_STAT, SB): | |
1620 | { | |
1621 | int len = 0; /* Length of filename. */ | |
1622 | char *filename; /* Filename would go here. */ | |
1623 | char temp_char; /* Temporary character */ | |
1624 | int filename_ptr; /* Pointer to filename in cpu memory. */ | |
1625 | struct stat stat_rec; /* Stat record */ | |
1626 | int stat_return; /* Return value from callback to stat */ | |
1627 | int stat_ptr; /* Pointer to stat record. */ | |
1628 | char *temp_stat_ptr; /* Temporary stat_rec pointer. */ | |
1629 | int i = 0; /* Loop Counter */ | |
1630 | ||
1631 | /* Setting filename_ptr to first argument of open. */ | |
1632 | filename_ptr = h8300hmode ? GET_L_REG (0) : GET_W_REG (0); | |
1633 | ||
1634 | /* Trying to find the length of the filename. */ | |
1635 | temp_char = GET_MEMORY_B (cpu.regs[0]); | |
1636 | ||
1637 | len = 1; | |
1638 | while (temp_char != '\0') | |
1639 | { | |
1640 | temp_char = GET_MEMORY_B (filename_ptr + len); | |
1641 | len++; | |
1642 | } | |
1643 | ||
1644 | /* Allocating space for the filename. */ | |
1645 | filename = (char *) malloc (sizeof (char) * len); | |
1646 | ||
1647 | /* String copying the filename from memory. */ | |
1648 | for (i = 0; i < len; i++) | |
1649 | { | |
1650 | temp_char = GET_MEMORY_B (filename_ptr + i); | |
1651 | filename[i] = temp_char; | |
1652 | } | |
1653 | ||
1654 | /* Setting stat_ptr to second argument of stat. */ | |
1655 | /* stat_ptr = cpu.regs[1]; */ | |
1656 | stat_ptr = h8300hmode ? GET_L_REG (1) : GET_W_REG (1); | |
1657 | ||
1658 | /* Callback stat and return. */ | |
1659 | stat_return = | |
1660 | sim_callback->stat (sim_callback, filename, &stat_rec); | |
1661 | ||
1662 | /* Have stat_ptr point to starting of stat_rec. */ | |
1663 | temp_stat_ptr = (char *) (&stat_rec); | |
1664 | ||
1665 | /* Freeing memory used for filename. */ | |
1666 | free (filename); | |
1667 | ||
1668 | /* Setting up the stat structure returned. */ | |
1669 | SET_MEMORY_W (stat_ptr, stat_rec.st_dev); | |
1670 | stat_ptr += 2; | |
1671 | SET_MEMORY_W (stat_ptr, stat_rec.st_ino); | |
1672 | stat_ptr += 2; | |
1673 | SET_MEMORY_L (stat_ptr, stat_rec.st_mode); | |
1674 | stat_ptr += 4; | |
1675 | SET_MEMORY_W (stat_ptr, stat_rec.st_nlink); | |
1676 | stat_ptr += 2; | |
1677 | SET_MEMORY_W (stat_ptr, stat_rec.st_uid); | |
1678 | stat_ptr += 2; | |
1679 | SET_MEMORY_W (stat_ptr, stat_rec.st_gid); | |
1680 | stat_ptr += 2; | |
1681 | SET_MEMORY_W (stat_ptr, stat_rec.st_rdev); | |
1682 | stat_ptr += 2; | |
1683 | SET_MEMORY_L (stat_ptr, stat_rec.st_size); | |
1684 | stat_ptr += 4; | |
1685 | SET_MEMORY_L (stat_ptr, stat_rec.st_atime); | |
1686 | stat_ptr += 8; | |
1687 | SET_MEMORY_L (stat_ptr, stat_rec.st_mtime); | |
1688 | stat_ptr += 8; | |
1689 | SET_MEMORY_L (stat_ptr, stat_rec.st_ctime); | |
1690 | ||
1691 | /* Return value in register 0. */ | |
1692 | cpu.regs[0] = stat_return; | |
1693 | } | |
1694 | goto next; | |
1695 | /* End of system call processing. */ | |
1696 | ||
c906108c SS |
1697 | ONOT (O_NOT, rd = ~rd; v = 0;); |
1698 | OSHIFTS (O_SHLL, | |
1699 | c = rd & hm; v = 0; rd <<= 1, | |
1700 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1701 | OSHIFTS (O_SHLR, | |
1702 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1703 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1704 | OSHIFTS (O_SHAL, | |
1705 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1706 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1707 | OSHIFTS (O_SHAR, | |
1708 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
d1335144 | 1709 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1); |
c906108c SS |
1710 | OSHIFTS (O_ROTL, |
1711 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1712 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1713 | OSHIFTS (O_ROTR, | |
1714 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1715 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1716 | OSHIFTS (O_ROTXL, | |
1717 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1718 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1719 | OSHIFTS (O_ROTXR, | |
1720 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1721 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1722 | ||
1723 | case O (O_JMP, SB): | |
1724 | { | |
1725 | pc = fetch (&code->src); | |
1726 | goto end; | |
1727 | ||
1728 | } | |
1729 | ||
1730 | case O (O_JSR, SB): | |
1731 | { | |
1732 | int tmp; | |
1733 | pc = fetch (&code->src); | |
1734 | call: | |
1735 | tmp = cpu.regs[7]; | |
1736 | ||
1737 | if (h8300hmode) | |
1738 | { | |
1739 | tmp -= 4; | |
1740 | SET_MEMORY_L (tmp, code->next_pc); | |
1741 | } | |
1742 | else | |
1743 | { | |
1744 | tmp -= 2; | |
1745 | SET_MEMORY_W (tmp, code->next_pc); | |
1746 | } | |
1747 | cpu.regs[7] = tmp; | |
1748 | ||
1749 | goto end; | |
1750 | } | |
1751 | case O (O_BSR, SB): | |
1752 | pc = code->src.literal; | |
1753 | goto call; | |
1754 | ||
1755 | case O (O_RTS, SN): | |
1756 | { | |
1757 | int tmp; | |
1758 | ||
1759 | tmp = cpu.regs[7]; | |
1760 | ||
1761 | if (h8300hmode) | |
1762 | { | |
1763 | pc = GET_MEMORY_L (tmp); | |
1764 | tmp += 4; | |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | pc = GET_MEMORY_W (tmp); | |
1769 | tmp += 2; | |
1770 | } | |
1771 | ||
1772 | cpu.regs[7] = tmp; | |
1773 | goto end; | |
1774 | } | |
1775 | ||
1776 | case O (O_ILL, SB): | |
1777 | cpu.state = SIM_STATE_STOPPED; | |
1778 | cpu.exception = SIGILL; | |
1779 | goto end; | |
1780 | case O (O_SLEEP, SN): | |
c906108c SS |
1781 | /* FIXME: Doesn't this break for breakpoints when r0 |
1782 | contains just the right (er, wrong) value? */ | |
1783 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1784 | /* The format of r0 is defined by target newlib. Expand |
1785 | the macros here instead of looking for .../sys/wait.h. */ | |
1786 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1787 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
c3f4437e | 1788 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) |
c906108c SS |
1789 | cpu.exception = SIGILL; |
1790 | else | |
1791 | cpu.exception = SIGTRAP; | |
c906108c SS |
1792 | goto end; |
1793 | case O (O_BPT, SN): | |
1794 | cpu.state = SIM_STATE_STOPPED; | |
1795 | cpu.exception = SIGTRAP; | |
1796 | goto end; | |
1797 | ||
1798 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1799 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1800 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
c3f4437e | 1801 | OBITOP (O_BSET, 1, 1, ea |= m); |
c906108c SS |
1802 | OBITOP (O_BLD, 1, 0, c = ea & m); |
1803 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1804 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1805 | if (C) ea |= m); | |
1806 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1807 | if (!C) ea |= m); | |
1808 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1809 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1810 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1811 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
ad4cda16 | 1812 | OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0) != C); |
c906108c SS |
1813 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); |
1814 | ||
de9b1892 KH |
1815 | #define MOP(bsize, signed) \ |
1816 | mop (code, bsize, signed); \ | |
1817 | goto next; | |
c906108c SS |
1818 | |
1819 | case O (O_MULS, SB): | |
1820 | MOP (1, 1); | |
1821 | break; | |
1822 | case O (O_MULS, SW): | |
1823 | MOP (0, 1); | |
1824 | break; | |
1825 | case O (O_MULU, SB): | |
1826 | MOP (1, 0); | |
1827 | break; | |
1828 | case O (O_MULU, SW): | |
1829 | MOP (0, 0); | |
1830 | break; | |
1831 | ||
6147b1f6 | 1832 | case O (O_TAS, SB): |
d1335144 | 1833 | if (!h8300smode || code->src.type != X (OP_REG, SL)) |
c3f4437e | 1834 | goto illegal; |
d1335144 | 1835 | switch (code->src.reg) |
c3f4437e KH |
1836 | { |
1837 | case R0_REGNUM: | |
1838 | case R1_REGNUM: | |
1839 | case R4_REGNUM: | |
1840 | case R5_REGNUM: | |
1841 | break; | |
1842 | default: | |
1843 | goto illegal; | |
1844 | } | |
1845 | res = fetch (&code->src); | |
d0fe2f7e | 1846 | store (&code->src, res | 0x80); |
6147b1f6 | 1847 | goto just_flags_log8; |
c906108c SS |
1848 | |
1849 | case O (O_DIVU, SB): | |
1850 | { | |
1851 | rd = GET_W_REG (code->dst.reg); | |
1852 | ea = GET_B_REG (code->src.reg); | |
1853 | if (ea) | |
1854 | { | |
de9b1892 KH |
1855 | tmp = (unsigned) rd % ea; |
1856 | rd = (unsigned) rd / ea; | |
c906108c SS |
1857 | } |
1858 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1859 | n = ea & 0x80; | |
1860 | nz = ea & 0xff; | |
1861 | ||
1862 | goto next; | |
1863 | } | |
1864 | case O (O_DIVU, SW): | |
1865 | { | |
1866 | rd = GET_L_REG (code->dst.reg); | |
1867 | ea = GET_W_REG (code->src.reg); | |
1868 | n = ea & 0x8000; | |
1869 | nz = ea & 0xffff; | |
1870 | if (ea) | |
1871 | { | |
de9b1892 KH |
1872 | tmp = (unsigned) rd % ea; |
1873 | rd = (unsigned) rd / ea; | |
c906108c SS |
1874 | } |
1875 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1876 | goto next; | |
1877 | } | |
1878 | ||
1879 | case O (O_DIVS, SB): | |
1880 | { | |
1881 | ||
1882 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1883 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1884 | if (ea) | |
1885 | { | |
1886 | tmp = (int) rd % (int) ea; | |
1887 | rd = (int) rd / (int) ea; | |
1888 | n = rd & 0x8000; | |
1889 | nz = 1; | |
1890 | } | |
1891 | else | |
1892 | nz = 0; | |
1893 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1894 | goto next; | |
1895 | } | |
1896 | case O (O_DIVS, SW): | |
1897 | { | |
1898 | rd = GET_L_REG (code->dst.reg); | |
1899 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1900 | if (ea) | |
1901 | { | |
1902 | tmp = (int) rd % (int) ea; | |
1903 | rd = (int) rd / (int) ea; | |
1904 | n = rd & 0x80000000; | |
1905 | nz = 1; | |
1906 | } | |
1907 | else | |
1908 | nz = 0; | |
1909 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1910 | goto next; | |
1911 | } | |
1912 | case O (O_EXTS, SW): | |
ec38ce99 | 1913 | rd = GET_W_REG (code->src.reg) & 0xff; /* Yes, src, not dst. */ |
c906108c SS |
1914 | ea = rd & 0x80 ? -256 : 0; |
1915 | res = rd + ea; | |
1916 | goto log16; | |
1917 | case O (O_EXTS, SL): | |
1918 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1919 | ea = rd & 0x8000 ? -65536 : 0; | |
1920 | res = rd + ea; | |
1921 | goto log32; | |
1922 | case O (O_EXTU, SW): | |
ec38ce99 | 1923 | rd = GET_W_REG (code->src.reg) & 0xff; |
c906108c SS |
1924 | ea = 0; |
1925 | res = rd + ea; | |
1926 | goto log16; | |
1927 | case O (O_EXTU, SL): | |
1928 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1929 | ea = 0; | |
1930 | res = rd + ea; | |
1931 | goto log32; | |
1932 | ||
1933 | case O (O_NOP, SN): | |
1934 | goto next; | |
1935 | ||
1936 | case O (O_STM, SL): | |
1937 | { | |
1938 | int nregs, firstreg, i; | |
1939 | ||
1940 | nregs = GET_MEMORY_B (pc + 1); | |
1941 | nregs >>= 4; | |
1942 | nregs &= 0xf; | |
1943 | firstreg = GET_MEMORY_B (pc + 3); | |
1944 | firstreg &= 0xf; | |
1945 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1946 | { | |
1947 | cpu.regs[7] -= 4; | |
1948 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1949 | } | |
1950 | } | |
1951 | goto next; | |
1952 | ||
1953 | case O (O_LDM, SL): | |
1954 | { | |
1955 | int nregs, firstreg, i; | |
1956 | ||
1957 | nregs = GET_MEMORY_B (pc + 1); | |
1958 | nregs >>= 4; | |
1959 | nregs &= 0xf; | |
1960 | firstreg = GET_MEMORY_B (pc + 3); | |
1961 | firstreg &= 0xf; | |
1962 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1963 | { | |
1964 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1965 | cpu.regs[7] += 4; | |
1966 | } | |
1967 | } | |
1968 | goto next; | |
1969 | ||
1970 | default: | |
d0fe2f7e | 1971 | illegal: |
c906108c SS |
1972 | cpu.state = SIM_STATE_STOPPED; |
1973 | cpu.exception = SIGILL; | |
1974 | goto end; | |
1975 | ||
1976 | } | |
1977 | abort (); | |
1978 | ||
1979 | setc: | |
d1335144 | 1980 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1981 | { |
1982 | cpu.ccr = res; | |
1983 | GETSR (); | |
1984 | } | |
d1335144 | 1985 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1986 | { |
1987 | cpu.exr = res; | |
1988 | GETEXR (); | |
1989 | } | |
fc974602 | 1990 | else |
c3f4437e | 1991 | goto illegal; |
fc974602 | 1992 | |
c906108c SS |
1993 | goto next; |
1994 | ||
1995 | condtrue: | |
1996 | /* When a branch works */ | |
1997 | pc = code->src.literal; | |
1998 | goto end; | |
1999 | ||
2000 | /* Set the cond codes from res */ | |
2001 | bitop: | |
2002 | ||
2003 | /* Set the flags after an 8 bit inc/dec operation */ | |
2004 | just_flags_inc8: | |
2005 | n = res & 0x80; | |
2006 | nz = res & 0xff; | |
2007 | v = (rd & 0x7f) == 0x7f; | |
2008 | goto next; | |
2009 | ||
2010 | ||
2011 | /* Set the flags after an 16 bit inc/dec operation */ | |
2012 | just_flags_inc16: | |
2013 | n = res & 0x8000; | |
2014 | nz = res & 0xffff; | |
2015 | v = (rd & 0x7fff) == 0x7fff; | |
2016 | goto next; | |
2017 | ||
2018 | ||
2019 | /* Set the flags after an 32 bit inc/dec operation */ | |
2020 | just_flags_inc32: | |
2021 | n = res & 0x80000000; | |
2022 | nz = res & 0xffffffff; | |
2023 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
2024 | goto next; | |
2025 | ||
2026 | ||
2027 | shift8: | |
2028 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
2029 | n = (rd & 0x80); | |
2030 | nz = rd & 0xff; | |
2031 | SET_B_REG (code->src.reg, rd); | |
2032 | goto next; | |
2033 | ||
2034 | shift16: | |
2035 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
2036 | n = (rd & 0x8000); | |
2037 | nz = rd & 0xffff; | |
2038 | SET_W_REG (code->src.reg, rd); | |
2039 | goto next; | |
2040 | ||
2041 | shift32: | |
2042 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
2043 | n = (rd & 0x80000000); | |
2044 | nz = rd & 0xffffffff; | |
2045 | SET_L_REG (code->src.reg, rd); | |
2046 | goto next; | |
2047 | ||
2048 | log32: | |
2049 | store (&code->dst, res); | |
2050 | just_flags_log32: | |
2051 | /* flags after a 32bit logical operation */ | |
2052 | n = res & 0x80000000; | |
2053 | nz = res & 0xffffffff; | |
2054 | v = 0; | |
2055 | goto next; | |
2056 | ||
2057 | log16: | |
2058 | store (&code->dst, res); | |
2059 | just_flags_log16: | |
2060 | /* flags after a 16bit logical operation */ | |
2061 | n = res & 0x8000; | |
2062 | nz = res & 0xffff; | |
2063 | v = 0; | |
2064 | goto next; | |
2065 | ||
2066 | ||
2067 | log8: | |
2068 | store (&code->dst, res); | |
2069 | just_flags_log8: | |
2070 | n = res & 0x80; | |
2071 | nz = res & 0xff; | |
2072 | v = 0; | |
2073 | goto next; | |
2074 | ||
2075 | alu8: | |
2076 | SET_B_REG (code->dst.reg, res); | |
2077 | just_flags_alu8: | |
2078 | n = res & 0x80; | |
2079 | nz = res & 0xff; | |
2080 | c = (res & 0x100); | |
2081 | switch (code->opcode / 4) | |
2082 | { | |
2083 | case O_ADD: | |
2084 | v = ((rd & 0x80) == (ea & 0x80) | |
2085 | && (rd & 0x80) != (res & 0x80)); | |
2086 | break; | |
2087 | case O_SUB: | |
2088 | case O_CMP: | |
2089 | v = ((rd & 0x80) != (-ea & 0x80) | |
2090 | && (rd & 0x80) != (res & 0x80)); | |
2091 | break; | |
2092 | case O_NEG: | |
2093 | v = (rd == 0x80); | |
2094 | break; | |
2095 | } | |
2096 | goto next; | |
2097 | ||
2098 | alu16: | |
2099 | SET_W_REG (code->dst.reg, res); | |
2100 | just_flags_alu16: | |
2101 | n = res & 0x8000; | |
2102 | nz = res & 0xffff; | |
2103 | c = (res & 0x10000); | |
2104 | switch (code->opcode / 4) | |
2105 | { | |
2106 | case O_ADD: | |
2107 | v = ((rd & 0x8000) == (ea & 0x8000) | |
2108 | && (rd & 0x8000) != (res & 0x8000)); | |
2109 | break; | |
2110 | case O_SUB: | |
2111 | case O_CMP: | |
2112 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
2113 | && (rd & 0x8000) != (res & 0x8000)); | |
2114 | break; | |
2115 | case O_NEG: | |
2116 | v = (rd == 0x8000); | |
2117 | break; | |
2118 | } | |
2119 | goto next; | |
2120 | ||
2121 | alu32: | |
2122 | SET_L_REG (code->dst.reg, res); | |
2123 | just_flags_alu32: | |
2124 | n = res & 0x80000000; | |
2125 | nz = res & 0xffffffff; | |
2126 | switch (code->opcode / 4) | |
2127 | { | |
2128 | case O_ADD: | |
2129 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
2130 | && (rd & 0x80000000) != (res & 0x80000000)); | |
2131 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
2132 | break; | |
2133 | case O_SUB: | |
2134 | case O_CMP: | |
2135 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
2136 | && (rd & 0x80000000) != (res & 0x80000000)); | |
2137 | c = (unsigned) rd < (unsigned) -ea; | |
2138 | break; | |
2139 | case O_NEG: | |
2140 | v = (rd == 0x80000000); | |
2141 | c = res != 0; | |
2142 | break; | |
2143 | } | |
2144 | goto next; | |
2145 | ||
2146 | next:; | |
2147 | pc = code->next_pc; | |
2148 | ||
2149 | end: | |
2150 | ; | |
de9b1892 KH |
2151 | #if 0 |
2152 | if (cpu.regs[8]) | |
2153 | abort (); | |
2154 | #endif | |
c906108c SS |
2155 | |
2156 | if (--poll_count < 0) | |
2157 | { | |
7a292a7a | 2158 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
2159 | if ((*sim_callback->poll_quit) != NULL |
2160 | && (*sim_callback->poll_quit) (sim_callback)) | |
2161 | sim_stop (sd); | |
2162 | } | |
2163 | ||
2164 | } | |
2165 | while (cpu.state == SIM_STATE_RUNNING); | |
2166 | cpu.ticks += get_now () - tick_start; | |
2167 | cpu.cycles += cycles; | |
2168 | cpu.insts += insts; | |
de9b1892 | 2169 | |
c906108c SS |
2170 | cpu.pc = pc; |
2171 | BUILDSR (); | |
d1335144 | 2172 | BUILDEXR (); |
c906108c SS |
2173 | cpu.mask = oldmask; |
2174 | signal (SIGINT, prev); | |
2175 | } | |
2176 | ||
2177 | int | |
a4f27e3e | 2178 | sim_trace (SIM_DESC sd) |
c906108c | 2179 | { |
2ea716f6 | 2180 | /* FIXME: Unfinished. */ |
c906108c SS |
2181 | abort (); |
2182 | } | |
2183 | ||
2184 | int | |
a4f27e3e | 2185 | sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
2186 | { |
2187 | int i; | |
2188 | ||
2189 | init_pointers (); | |
2190 | if (addr < 0) | |
2191 | return 0; | |
2192 | for (i = 0; i < size; i++) | |
2193 | { | |
2194 | if (addr < memory_size) | |
2195 | { | |
2196 | cpu.memory[addr + i] = buffer[i]; | |
2197 | cpu.cache_idx[addr + i] = 0; | |
2198 | } | |
2199 | else | |
2200 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
2201 | } | |
2202 | return size; | |
2203 | } | |
2204 | ||
2205 | int | |
a4f27e3e | 2206 | sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
2207 | { |
2208 | init_pointers (); | |
2209 | if (addr < 0) | |
2210 | return 0; | |
2211 | if (addr < memory_size) | |
2212 | memcpy (buffer, cpu.memory + addr, size); | |
2213 | else | |
2214 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
2215 | return size; | |
2216 | } | |
2217 | ||
2218 | ||
c906108c | 2219 | int |
a4f27e3e | 2220 | sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length) |
c906108c SS |
2221 | { |
2222 | int longval; | |
2223 | int shortval; | |
2224 | int intval; | |
2225 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
2226 | shortval = (value[0] << 8) | (value[1]); | |
2227 | intval = h8300hmode ? longval : shortval; | |
2228 | ||
2229 | init_pointers (); | |
2230 | switch (rn) | |
2231 | { | |
2232 | case PC_REGNUM: | |
2233 | cpu.pc = intval; | |
2234 | break; | |
2235 | default: | |
2236 | abort (); | |
2237 | case R0_REGNUM: | |
2238 | case R1_REGNUM: | |
2239 | case R2_REGNUM: | |
2240 | case R3_REGNUM: | |
2241 | case R4_REGNUM: | |
2242 | case R5_REGNUM: | |
2243 | case R6_REGNUM: | |
2244 | case R7_REGNUM: | |
2245 | cpu.regs[rn] = intval; | |
2246 | break; | |
2247 | case CCR_REGNUM: | |
2248 | cpu.ccr = intval; | |
2249 | break; | |
fc974602 AV |
2250 | case EXR_REGNUM: |
2251 | cpu.exr = intval; | |
2252 | break; | |
c906108c SS |
2253 | case CYCLE_REGNUM: |
2254 | cpu.cycles = longval; | |
2255 | break; | |
2256 | ||
2257 | case INST_REGNUM: | |
2258 | cpu.insts = longval; | |
2259 | break; | |
2260 | ||
2261 | case TICK_REGNUM: | |
2262 | cpu.ticks = longval; | |
2263 | break; | |
2264 | } | |
2265 | return -1; | |
2266 | } | |
2267 | ||
2268 | int | |
a4f27e3e | 2269 | sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length) |
c906108c SS |
2270 | { |
2271 | int v; | |
2272 | int longreg = 0; | |
2273 | ||
2274 | init_pointers (); | |
2275 | ||
d0fe2f7e | 2276 | if (!h8300smode && rn >= EXR_REGNUM) |
c3f4437e | 2277 | rn++; |
c906108c SS |
2278 | switch (rn) |
2279 | { | |
2280 | default: | |
2281 | abort (); | |
3b02cf92 | 2282 | case CCR_REGNUM: |
c906108c SS |
2283 | v = cpu.ccr; |
2284 | break; | |
fc974602 AV |
2285 | case EXR_REGNUM: |
2286 | v = cpu.exr; | |
2287 | break; | |
3b02cf92 | 2288 | case PC_REGNUM: |
c906108c SS |
2289 | v = cpu.pc; |
2290 | break; | |
2291 | case R0_REGNUM: | |
2292 | case R1_REGNUM: | |
2293 | case R2_REGNUM: | |
2294 | case R3_REGNUM: | |
2295 | case R4_REGNUM: | |
2296 | case R5_REGNUM: | |
2297 | case R6_REGNUM: | |
2298 | case R7_REGNUM: | |
2299 | v = cpu.regs[rn]; | |
2300 | break; | |
3b02cf92 | 2301 | case CYCLE_REGNUM: |
c906108c SS |
2302 | v = cpu.cycles; |
2303 | longreg = 1; | |
2304 | break; | |
3b02cf92 | 2305 | case TICK_REGNUM: |
c906108c SS |
2306 | v = cpu.ticks; |
2307 | longreg = 1; | |
2308 | break; | |
3b02cf92 | 2309 | case INST_REGNUM: |
c906108c SS |
2310 | v = cpu.insts; |
2311 | longreg = 1; | |
2312 | break; | |
2313 | } | |
2314 | if (h8300hmode || longreg) | |
2315 | { | |
2316 | buf[0] = v >> 24; | |
2317 | buf[1] = v >> 16; | |
2318 | buf[2] = v >> 8; | |
2319 | buf[3] = v >> 0; | |
2320 | } | |
2321 | else | |
2322 | { | |
2323 | buf[0] = v >> 8; | |
2324 | buf[1] = v; | |
2325 | } | |
2326 | return -1; | |
2327 | } | |
2328 | ||
2329 | void | |
a4f27e3e | 2330 | sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc) |
c906108c SS |
2331 | { |
2332 | #if 0 /* FIXME: This should work but we can't use it. | |
2333 | grep for SLEEP above. */ | |
2334 | switch (cpu.state) | |
2335 | { | |
2336 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
2337 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
2338 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
2339 | default : abort (); | |
2340 | } | |
2341 | #else | |
2342 | *reason = sim_stopped; | |
2343 | #endif | |
2344 | *sigrc = cpu.exception; | |
2345 | } | |
2346 | ||
2347 | /* FIXME: Rename to sim_set_mem_size. */ | |
2348 | ||
2349 | void | |
a4f27e3e | 2350 | sim_size (int n) |
c906108c SS |
2351 | { |
2352 | /* Memory size is fixed. */ | |
2353 | } | |
2354 | ||
2355 | void | |
a4f27e3e | 2356 | sim_set_simcache_size (int n) |
c906108c SS |
2357 | { |
2358 | if (cpu.cache) | |
2359 | free (cpu.cache); | |
2360 | if (n < 2) | |
2361 | n = 2; | |
2362 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
2363 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
2364 | cpu.csize = n; | |
2365 | } | |
2366 | ||
2367 | ||
2368 | void | |
a4f27e3e | 2369 | sim_info (SIM_DESC sd, int verbose) |
c906108c SS |
2370 | { |
2371 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
2372 | double virttime = cpu.cycles / 10.0e6; | |
2373 | ||
2374 | (*sim_callback->printf_filtered) (sim_callback, | |
2375 | "\n\n#instructions executed %10d\n", | |
2376 | cpu.insts); | |
2377 | (*sim_callback->printf_filtered) (sim_callback, | |
2378 | "#cycles (v approximate) %10d\n", | |
2379 | cpu.cycles); | |
2380 | (*sim_callback->printf_filtered) (sim_callback, | |
2381 | "#real time taken %10.4f\n", | |
2382 | timetaken); | |
2383 | (*sim_callback->printf_filtered) (sim_callback, | |
2384 | "#virtual time taked %10.4f\n", | |
2385 | virttime); | |
2386 | if (timetaken != 0.0) | |
2387 | (*sim_callback->printf_filtered) (sim_callback, | |
2388 | "#simulation ratio %10.4f\n", | |
2389 | virttime / timetaken); | |
2390 | (*sim_callback->printf_filtered) (sim_callback, | |
2391 | "#compiles %10d\n", | |
2392 | cpu.compiles); | |
2393 | (*sim_callback->printf_filtered) (sim_callback, | |
2394 | "#cache size %10d\n", | |
2395 | cpu.csize); | |
2396 | ||
2397 | #ifdef ADEBUG | |
2398 | /* This to be conditional on `what' (aka `verbose'), | |
2399 | however it was never passed as non-zero. */ | |
2400 | if (1) | |
2401 | { | |
2402 | int i; | |
2403 | for (i = 0; i < O_LAST; i++) | |
2404 | { | |
2405 | if (cpu.stats[i]) | |
2406 | (*sim_callback->printf_filtered) (sim_callback, | |
2407 | "%d: %d\n", i, cpu.stats[i]); | |
2408 | } | |
2409 | } | |
2410 | #endif | |
2411 | } | |
2412 | ||
2ea716f6 KH |
2413 | /* Indicate whether the cpu is an H8/300 or H8/300H. |
2414 | FLAG is non-zero for the H8/300H. */ | |
c906108c SS |
2415 | |
2416 | void | |
a4f27e3e | 2417 | set_h8300h (int h_flag, int s_flag) |
c906108c SS |
2418 | { |
2419 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2420 | This function being replaced by a sim_open:ARGV configuration | |
2ea716f6 | 2421 | option. */ |
a8cdafbd AV |
2422 | h8300hmode = h_flag; |
2423 | h8300smode = s_flag; | |
c906108c SS |
2424 | } |
2425 | ||
2426 | SIM_DESC | |
a4f27e3e MS |
2427 | sim_open (SIM_OPEN_KIND kind, |
2428 | struct host_callback_struct *ptr, | |
6b4a8935 | 2429 | struct bfd *abfd, |
a4f27e3e | 2430 | char **argv) |
c906108c | 2431 | { |
2ea716f6 | 2432 | /* FIXME: Much of the code in sim_load can be moved here. */ |
c906108c SS |
2433 | |
2434 | sim_kind = kind; | |
2435 | myname = argv[0]; | |
2436 | sim_callback = ptr; | |
2ea716f6 | 2437 | /* Fudge our descriptor. */ |
c906108c SS |
2438 | return (SIM_DESC) 1; |
2439 | } | |
2440 | ||
2441 | void | |
a4f27e3e | 2442 | sim_close (SIM_DESC sd, int quitting) |
c906108c | 2443 | { |
2ea716f6 | 2444 | /* Nothing to do. */ |
c906108c SS |
2445 | } |
2446 | ||
2447 | /* Called by gdb to load a program into memory. */ | |
2448 | ||
2449 | SIM_RC | |
a4f27e3e | 2450 | sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty) |
c906108c SS |
2451 | { |
2452 | bfd *prog_bfd; | |
2453 | ||
2ea716f6 KH |
2454 | /* FIXME: The code below that sets a specific variant of the H8/300 |
2455 | being simulated should be moved to sim_open(). */ | |
c906108c | 2456 | |
2ea716f6 | 2457 | /* See if the file is for the H8/300 or H8/300H. */ |
c906108c SS |
2458 | /* ??? This may not be the most efficient way. The z8k simulator |
2459 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2460 | if (abfd != NULL) | |
2461 | prog_bfd = abfd; | |
2462 | else | |
2463 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2464 | if (prog_bfd != NULL) | |
2465 | { | |
2466 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2467 | and bfd_openr as sim_load_file checks too. */ | |
de9b1892 | 2468 | if (bfd_check_format (prog_bfd, bfd_object)) |
c906108c SS |
2469 | { |
2470 | unsigned long mach = bfd_get_mach (prog_bfd); | |
a8cdafbd AV |
2471 | set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s, |
2472 | mach == bfd_mach_h8300s); | |
c906108c SS |
2473 | } |
2474 | } | |
2475 | ||
2476 | /* If we're using gdb attached to the simulator, then we have to | |
2477 | reallocate memory for the simulator. | |
2478 | ||
2479 | When gdb first starts, it calls fetch_registers (among other | |
2480 | functions), which in turn calls init_pointers, which allocates | |
2481 | simulator memory. | |
2482 | ||
2483 | The problem is when we do that, we don't know whether we're | |
2ea716f6 | 2484 | debugging an H8/300 or H8/300H program. |
c906108c SS |
2485 | |
2486 | This is the first point at which we can make that determination, | |
2487 | so we just reallocate memory now; this will also allow us to handle | |
2ea716f6 | 2488 | switching between H8/300 and H8/300H programs without exiting |
c906108c | 2489 | gdb. */ |
a8cdafbd AV |
2490 | |
2491 | if (h8300smode) | |
2492 | memory_size = H8300S_MSIZE; | |
2493 | else if (h8300hmode) | |
c906108c SS |
2494 | memory_size = H8300H_MSIZE; |
2495 | else | |
2496 | memory_size = H8300_MSIZE; | |
2497 | ||
2498 | if (cpu.memory) | |
2499 | free (cpu.memory); | |
2500 | if (cpu.cache_idx) | |
2501 | free (cpu.cache_idx); | |
2502 | if (cpu.eightbit) | |
2503 | free (cpu.eightbit); | |
2504 | ||
2505 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2506 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2507 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2508 | ||
2ea716f6 | 2509 | /* `msize' must be a power of two. */ |
c906108c SS |
2510 | if ((memory_size & (memory_size - 1)) != 0) |
2511 | abort (); | |
2512 | cpu.mask = memory_size - 1; | |
2513 | ||
2514 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2515 | sim_kind == SIM_OPEN_DEBUG, | |
2516 | 0, sim_write) | |
2517 | == NULL) | |
2518 | { | |
2519 | /* Close the bfd if we opened it. */ | |
2520 | if (abfd == NULL && prog_bfd != NULL) | |
2521 | bfd_close (prog_bfd); | |
2522 | return SIM_RC_FAIL; | |
2523 | } | |
2524 | ||
2525 | /* Close the bfd if we opened it. */ | |
2526 | if (abfd == NULL && prog_bfd != NULL) | |
2527 | bfd_close (prog_bfd); | |
2528 | return SIM_RC_OK; | |
2529 | } | |
2530 | ||
2531 | SIM_RC | |
6b4a8935 | 2532 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) |
c906108c SS |
2533 | { |
2534 | if (abfd != NULL) | |
2535 | cpu.pc = bfd_get_start_address (abfd); | |
2536 | else | |
2537 | cpu.pc = 0; | |
2538 | return SIM_RC_OK; | |
2539 | } | |
2540 | ||
2541 | void | |
a4f27e3e | 2542 | sim_do_command (SIM_DESC sd, char *cmd) |
c906108c SS |
2543 | { |
2544 | (*sim_callback->printf_filtered) (sim_callback, | |
2545 | "This simulator does not accept any commands.\n"); | |
2546 | } | |
2547 | ||
2548 | void | |
a4f27e3e | 2549 | sim_set_callbacks (struct host_callback_struct *ptr) |
c906108c SS |
2550 | { |
2551 | sim_callback = ptr; | |
2552 | } |