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Fix typo in ALIGN_N usage.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
c2d11a7d
JM		 11999-11-29 Mark Salter <msalter@cygnus.com>
2
3 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
4 to clear status bits in sdisr register. This is how the hardware works.
5
6 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
7 being used by cygmon.
8
4ce44c66
JM		 91999-11-11 Andrew Haley <aph@cygnus.com>
10
11 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
12 instructions.
13
cff3e48b
JM		 14Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
15
16 * mips.igen (MULT): Correct previous mis-applied patch.
17
d4f3574e
SS		 18Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
19
20 * mips.igen (delayslot32): Handle sequence like
21 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
22 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
23 (MULT): Actually pass the third register...
24
251999-09-03 Mark Salter <msalter@cygnus.com>
26
27 * interp.c (sim_open): Added more memory aliases for additional
28 hardware being touched by cygmon on jmr3904 board.
29
30Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
31
32 * configure: Regenerated to track ../common/aclocal.m4 changes.
33
a0b3c4fd
JM		 34Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
35
36 * interp.c (sim_store_register): Handle case where client - GDB -
37 specifies that a 4 byte register is 8 bytes in size.
38 (sim_fetch_register): Ditto.
39
adf40b2e
JM		 401999-07-14 Frank Ch. Eigler <fche@cygnus.com>
41
42 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
43 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
44 (idt_monitor_base): Base address for IDT monitor traps.
45 (pmon_monitor_base): Ditto for PMON.
46 (lsipmon_monitor_base): Ditto for LSI PMON.
47 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
48 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
49 (sim_firmware_command): New function.
50 (mips_option_handler): Call it for OPTION_FIRMWARE.
51 (sim_open): Allocate memory for idt_monitor region. If "--board"
52 option was given, add no monitor by default. Add BREAK hooks only if
53 monitors are also there.
54
43e526b9
JM		 55Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
56
57 * interp.c (sim_monitor): Flush output before reading input.
58
59Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
60
61 * tconfig.in (SIM_HANDLES_LMA): Always define.
62
63Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
64
65 From Mark Salter <msalter@cygnus.com>:
66 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
67 (sim_open): Add setup for BSP board.
68
9846de1b
JM		 69Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
70
71 * mips.igen (MULT, MULTU): Add syntax for two operand version.
72 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
73 them as unimplemented.
74
cd0fc7c3
SS		 751999-05-08 Felix Lee <flee@cygnus.com>
76
77 * configure: Regenerated to track ../common/aclocal.m4 changes.
78
7a292a7a
SS		 791999-04-21 Frank Ch. Eigler <fche@cygnus.com>
80
81 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
82
83Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
84
85 * configure.in: Any mips64vr5*-*-* target should have
86 -DTARGET_ENABLE_FR=1.
87 (default_endian): Any mips64vr*el-*-* target should default to
88 LITTLE_ENDIAN.
89 * configure: Re-generate.
90
911999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
92
93 * mips.igen (ldl): Extend from _16_, not 32.
94
95Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
96
97 * interp.c (sim_store_register): Force registers written to by GDB
98 into an un-interpreted state.
99
c906108c
SS		 1001999-02-05 Frank Ch. Eigler <fche@cygnus.com>
101
102 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
103 CPU, start periodic background I/O polls.
104 (tx3904sio_poll): New function: periodic I/O poller.
105
1061998-12-30 Frank Ch. Eigler <fche@cygnus.com>
107
108 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
109
110Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
111
112 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
113 case statement.
114
1151998-12-29 Frank Ch. Eigler <fche@cygnus.com>
116
117 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
118 (load_word): Call SIM_CORE_SIGNAL hook on error.
119 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
120 starting. For exception dispatching, pass PC instead of NULL_CIA.
121 (decode_coproc): Use COP0_BADVADDR to store faulting address.
122 * sim-main.h (COP0_BADVADDR): Define.
123 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
124 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
125 (_sim_cpu): Add exc_* fields to store register value snapshots.
126 * mips.igen (*): Replace memory-related SignalException* calls
127 with references to SIM_CORE_SIGNAL hook.
128
129 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
130 fix.
131 * sim-main.c (*): Minor warning cleanups.
132
1331998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
134
135 * m16.igen (DADDIU5): Correct type-o.
136
137Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
138
139 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
140 variables.
141
142Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
143
144 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
145 to include path.
146 (interp.o): Add dependency on itable.h
147 (oengine.c, gencode): Delete remaining references.
148 (BUILT_SRC_FROM_GEN): Clean up.
149
1501998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
151
152 * vr4run.c: New.
153 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
154 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
155 tmp-run-hack) : New.
156 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
157 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
158 Drop the "64" qualifier to get the HACK generator working.
159 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
160 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
161 qualifier to get the hack generator working.
162 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
163 (DSLL): Use do_dsll.
164 (DSLLV): Use do_dsllv.
165 (DSRA): Use do_dsra.
166 (DSRL): Use do_dsrl.
167 (DSRLV): Use do_dsrlv.
168 (BC1): Move *vr4100 to get the HACK generator working.
169 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
170 get the HACK generator working.
171 (MACC) Rename to get the HACK generator working.
172 (DMACC,MACCS,DMACCS): Add the 64.
173
1741998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
175
176 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
177 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
178
1791998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
180
181 * mips/interp.c (DEBUG): Cleanups.
182
1831998-12-10 Frank Ch. Eigler <fche@cygnus.com>
184
185 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
186 (tx3904sio_tickle): fflush after a stdout character output.
187
1881998-12-03 Frank Ch. Eigler <fche@cygnus.com>
189
190 * interp.c (sim_close): Uninstall modules.
191
192Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
193
194 * sim-main.h, interp.c (sim_monitor): Change to global
195 function.
196
197Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
198
199 * configure.in (vr4100): Only include vr4100 instructions in
200 simulator.
201 * configure: Re-generate.
202 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
203
204Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
205
206 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
207 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
208 true alternative.
209
210 * configure.in (sim_default_gen, sim_use_gen): Replace with
211 sim_gen.
212 (--enable-sim-igen): Delete config option. Always using IGEN.
213 * configure: Re-generate.
214
215 * Makefile.in (gencode): Kill, kill, kill.
216 * gencode.c: Ditto.
217
218Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
219
220 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
221 bit mips16 igen simulator.
222 * configure: Re-generate.
223
224 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
225 as part of vr4100 ISA.
226 * vr.igen: Mark all instructions as 64 bit only.
227
228Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
229
230 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
231 Pacify GCC.
232
233Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
234
235 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
236 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
237 * configure: Re-generate.
238
239 * m16.igen (BREAK): Define breakpoint instruction.
240 (JALX32): Mark instruction as mips16 and not r3900.
241 * mips.igen (C.cond.fmt): Fix typo in instruction format.
242
243 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
244
245Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
246
247 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
248 insn as a debug breakpoint.
249
250 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
251 pending.slot_size.
252 (PENDING_SCHED): Clean up trace statement.
253 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
254 (PENDING_FILL): Delay write by only one cycle.
255 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
256
257 * sim-main.c (pending_tick): Clean up trace statements. Add trace
258 of pending writes.
259 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
260 32 & 64.
261 (pending_tick): Move incrementing of index to FOR statement.
262 (pending_tick): Only update PENDING_OUT after a write has occured.
263
264 * configure.in: Add explicit mips-lsi-* target. Use gencode to
265 build simulator.
266 * configure: Re-generate.
267
268 * interp.c (sim_engine_run OLD): Delete explicit call to
269 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
270
271Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
272
273 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
274 interrupt level number to match changed SignalExceptionInterrupt
275 macro.
276
277Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
278
279 * interp.c: #include "itable.h" if WITH_IGEN.
280 (get_insn_name): New function.
281 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
282 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
283
284Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
285
286 * configure: Rebuilt to inhale new common/aclocal.m4.
287
288Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
289
290 * dv-tx3904sio.c: Include sim-assert.h.
291
292Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
293
294 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
295 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
296 Reorganize target-specific sim-hardware checks.
297 * configure: rebuilt.
298 * interp.c (sim_open): For tx39 target boards, set
299 OPERATING_ENVIRONMENT, add tx3904sio devices.
300 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
301 ROM executables. Install dv-sockser into sim-modules list.
302
303 * dv-tx3904irc.c: Compiler warning clean-up.
304 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
305 frequent hw-trace messages.
306
307Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
308
309 * vr.igen (MulAcc): Identify as a vr4100 specific function.
310
311Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
312
313 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
314
315 * vr.igen: New file.
316 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
317 * mips.igen: Define vr4100 model. Include vr.igen.
318Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
319
320 * mips.igen (check_mf_hilo): Correct check.
321
322Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
323
324 * sim-main.h (interrupt_event): Add prototype.
325
326 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
327 register_ptr, register_value.
328 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
329
330 * sim-main.h (tracefh): Make extern.
331
332Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
333
334 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
335 Reduce unnecessarily high timer event frequency.
336 * dv-tx3904cpu.c: Ditto for interrupt event.
337
338Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
339
340 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
341 to allay warnings.
342 (interrupt_event): Made non-static.
343
344 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
345 interchange of configuration values for external vs. internal
346 clock dividers.
347
348Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
349
350 * mips.igen (BREAK): Moved code to here for
351 simulator-reserved break instructions.
352 * gencode.c (build_instruction): Ditto.
353 * interp.c (signal_exception): Code moved from here. Non-
354 reserved instructions now use exception vector, rather
355 than halting sim.
356 * sim-main.h: Moved magic constants to here.
357
358Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
359
360 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
361 register upon non-zero interrupt event level, clear upon zero
362 event value.
363 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
364 by passing zero event value.
365 (*_io_{read,write}_buffer): Endianness fixes.
366 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
367 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
368
369 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
370 serial I/O and timer module at base address 0xFFFF0000.
371
372Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
373
374 * mips.igen (SWC1) : Correct the handling of ReverseEndian
375 and BigEndianCPU.
376
377Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
378
379 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
380 parts.
381 * configure: Update.
382
383Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
384
385 * dv-tx3904tmr.c: New file - implements tx3904 timer.
386 * dv-tx3904{irc,cpu}.c: Mild reformatting.
387 * configure.in: Include tx3904tmr in hw_device list.
388 * configure: Rebuilt.
389 * interp.c (sim_open): Instantiate three timer instances.
390 Fix address typo of tx3904irc instance.
391
392Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
393
394 * interp.c (signal_exception): SystemCall exception now uses
395 the exception vector.
396
397Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
398
399 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
400 to allay warnings.
401
402Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
403
404 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
405
406Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
407
408 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
409
410 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
411 sim-main.h. Declare a struct hw_descriptor instead of struct
412 hw_device_descriptor.
413
414Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
415
416 * mips.igen (do_store_left, do_load_left): Compute nr of left and
417 right bits and then re-align left hand bytes to correct byte
418 lanes. Fix incorrect computation in do_store_left when loading
419 bytes from second word.
420
421Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
422
423 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
424 * interp.c (sim_open): Only create a device tree when HW is
425 enabled.
426
427 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
428 * interp.c (signal_exception): Ditto.
429
430Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
431
432 * gencode.c: Mark BEGEZALL as LIKELY.
433
434Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
435
436 * sim-main.h (ALU32_END): Sign extend 32 bit results.
437 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
438
439Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
440
441 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
442 modules. Recognize TX39 target with "mips*tx39" pattern.
443 * configure: Rebuilt.
444 * sim-main.h (*): Added many macros defining bits in
445 TX39 control registers.
446 (SignalInterrupt): Send actual PC instead of NULL.
447 (SignalNMIReset): New exception type.
448 * interp.c (board): New variable for future use to identify
449 a particular board being simulated.
450 (mips_option_handler,mips_options): Added "--board" option.
451 (interrupt_event): Send actual PC.
452 (sim_open): Make memory layout conditional on board setting.
453 (signal_exception): Initial implementation of hardware interrupt
454 handling. Accept another break instruction variant for simulator
455 exit.
456 (decode_coproc): Implement RFE instruction for TX39.
457 (mips.igen): Decode RFE instruction as such.
458 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
459 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
460 bbegin to implement memory map.
461 * dv-tx3904cpu.c: New file.
462 * dv-tx3904irc.c: New file.
463
464Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
465
466 * mips.igen (check_mt_hilo): Create a separate r3900 version.
467
468Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
469
470 * tx.igen (madd,maddu): Replace calls to check_op_hilo
471 with calls to check_div_hilo.
472
473Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
474
475 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
476 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
477 Add special r3900 version of do_mult_hilo.
478 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
479 with calls to check_mult_hilo.
480 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
481 with calls to check_div_hilo.
482
483Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
484
485 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
486 Document a replacement.
487
488Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
489
490 * interp.c (sim_monitor): Make mon_printf work.
491
492Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
493
494 * sim-main.h (INSN_NAME): New arg `cpu'.
495
496Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
497
498 * configure: Regenerated to track ../common/aclocal.m4 changes.
499
500Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
501
502 * configure: Regenerated to track ../common/aclocal.m4 changes.
503 * config.in: Ditto.
504
505Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
506
507 * acconfig.h: New file.
508 * configure.in: Reverted change of Apr 24; use sinclude again.
509
510Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
511
512 * configure: Regenerated to track ../common/aclocal.m4 changes.
513 * config.in: Ditto.
514
515Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
516
517 * configure.in: Don't call sinclude.
518
519Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
520
521 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
522
523Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
524
525 * mips.igen (ERET): Implement.
526
527 * interp.c (decode_coproc): Return sign-extended EPC.
528
529 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
530
531 * interp.c (signal_exception): Do not ignore Trap.
532 (signal_exception): On TRAP, restart at exception address.
533 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
534 (signal_exception): Update.
535 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
536 so that TRAP instructions are caught.
537
538Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
539
540 * sim-main.h (struct hilo_access, struct hilo_history): Define,
541 contains HI/LO access history.
542 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
543 (HIACCESS, LOACCESS): Delete, replace with
544 (HIHISTORY, LOHISTORY): New macros.
545 (CHECKHILO): Delete all, moved to mips.igen
546
547 * gencode.c (build_instruction): Do not generate checks for
548 correct HI/LO register usage.
549
550 * interp.c (old_engine_run): Delete checks for correct HI/LO
551 register usage.
552
553 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
554 check_mf_cycles): New functions.
555 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
556 do_divu, domultx, do_mult, do_multu): Use.
557
558 * tx.igen ("madd", "maddu"): Use.
559
560Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
561
562 * mips.igen (DSRAV): Use function do_dsrav.
563 (SRAV): Use new function do_srav.
564
565 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
566 (B): Sign extend 11 bit immediate.
567 (EXT-B*): Shift 16 bit immediate left by 1.
568 (ADDIU*): Don't sign extend immediate value.
569
570Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
571
572 * m16run.c (sim_engine_run): Restore CIA after handling an event.
573
574 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
575 functions.
576
577 * mips.igen (delayslot32, nullify_next_insn): New functions.
578 (m16.igen): Always include.
579 (do_*): Add more tracing.
580
581 * m16.igen (delayslot16): Add NIA argument, could be called by a
582 32 bit MIPS16 instruction.
583
584 * interp.c (ifetch16): Move function from here.
585 * sim-main.c (ifetch16): To here.
586
587 * sim-main.c (ifetch16, ifetch32): Update to match current
588 implementations of LH, LW.
589 (signal_exception): Don't print out incorrect hex value of illegal
590 instruction.
591
592Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
593
594 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
595 instruction.
596
597 * m16.igen: Implement MIPS16 instructions.
598
599 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
600 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
601 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
602 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
603 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
604 bodies of corresponding code from 32 bit insn to these. Also used
605 by MIPS16 versions of functions.
606
607 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
608 (IMEM16): Drop NR argument from macro.
609
610Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
611
612 * Makefile.in (SIM_OBJS): Add sim-main.o.
613
614 * sim-main.h (address_translation, load_memory, store_memory,
615 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
616 as INLINE_SIM_MAIN.
617 (pr_addr, pr_uword64): Declare.
618 (sim-main.c): Include when H_REVEALS_MODULE_P.
619
620 * interp.c (address_translation, load_memory, store_memory,
621 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
622 from here.
623 * sim-main.c: To here. Fix compilation problems.
624
625 * configure.in: Enable inlining.
626 * configure: Re-config.
627
628Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
629
630 * configure: Regenerated to track ../common/aclocal.m4 changes.
631
632Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
633
634 * mips.igen: Include tx.igen.
635 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
636 * tx.igen: New file, contains MADD and MADDU.
637
638 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
639 the hardwired constant `7'.
640 (store_memory): Ditto.
641 (LOADDRMASK): Move definition to sim-main.h.
642
643 mips.igen (MTC0): Enable for r3900.
644 (ADDU): Add trace.
645
646 mips.igen (do_load_byte): Delete.
647 (do_load, do_store, do_load_left, do_load_write, do_store_left,
648 do_store_right): New functions.
649 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
650
651 configure.in: Let the tx39 use igen again.
652 configure: Update.
653
654Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
655
656 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
657 not an address sized quantity. Return zero for cache sizes.
658
659Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
660
661 * mips.igen (r3900): r3900 does not support 64 bit integer
662 operations.
663
664Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
665
666 * configure.in (mipstx39*-*-*): Use gencode simulator rather
667 than igen one.
668 * configure : Rebuild.
669
670Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
671
672 * configure: Regenerated to track ../common/aclocal.m4 changes.
673
674Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
675
676 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
677
678Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
679
680 * configure: Regenerated to track ../common/aclocal.m4 changes.
681 * config.in: Regenerated to track ../common/aclocal.m4 changes.
682
683Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
684
685 * configure: Regenerated to track ../common/aclocal.m4 changes.
686
687Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
688
689 * interp.c (Max, Min): Comment out functions. Not yet used.
690
691Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
692
693 * configure: Regenerated to track ../common/aclocal.m4 changes.
694
695Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
696
697 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
698 configurable settings for stand-alone simulator.
699
700 * configure.in: Added X11 search, just in case.
701
702 * configure: Regenerated.
703
704Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
705
706 * interp.c (sim_write, sim_read, load_memory, store_memory):
707 Replace sim_core_*_map with read_map, write_map, exec_map resp.
708
709Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
710
711 * sim-main.h (GETFCC): Return an unsigned value.
712
713Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * mips.igen (DIV): Fix check for -1 / MIN_INT.
716 (DADD): Result destination is RD not RT.
717
718Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
719
720 * sim-main.h (HIACCESS, LOACCESS): Always define.
721
722 * mdmx.igen (Maxi, Mini): Rename Max, Min.
723
724 * interp.c (sim_info): Delete.
725
726Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
727
728 * interp.c (DECLARE_OPTION_HANDLER): Use it.
729 (mips_option_handler): New argument `cpu'.
730 (sim_open): Update call to sim_add_option_table.
731
732Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
733
734 * mips.igen (CxC1): Add tracing.
735
736Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
737
738 * sim-main.h (Max, Min): Declare.
739
740 * interp.c (Max, Min): New functions.
741
742 * mips.igen (BC1): Add tracing.
743
744Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
745
746 * interp.c Added memory map for stack in vr4100
747
748Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
749
750 * interp.c (load_memory): Add missing "break"'s.
751
752Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * interp.c (sim_store_register, sim_fetch_register): Pass in
755 length parameter. Return -1.
756
757Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
758
759 * interp.c: Added hardware init hook, fixed warnings.
760
761Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
764
765Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
766
767 * interp.c (ifetch16): New function.
768
769 * sim-main.h (IMEM32): Rename IMEM.
770 (IMEM16_IMMED): Define.
771 (IMEM16): Define.
772 (DELAY_SLOT): Update.
773
774 * m16run.c (sim_engine_run): New file.
775
776 * m16.igen: All instructions except LB.
777 (LB): Call do_load_byte.
778 * mips.igen (do_load_byte): New function.
779 (LB): Call do_load_byte.
780
781 * mips.igen: Move spec for insn bit size and high bit from here.
782 * Makefile.in (tmp-igen, tmp-m16): To here.
783
784 * m16.dc: New file, decode mips16 instructions.
785
786 * Makefile.in (SIM_NO_ALL): Define.
787 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
788
789Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
790
791 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
792 point unit to 32 bit registers.
793 * configure: Re-generate.
794
795Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
796
797 * configure.in (sim_use_gen): Make IGEN the default simulator
798 generator for generic 32 and 64 bit mips targets.
799 * configure: Re-generate.
800
801Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
804 bitsize.
805
806 * interp.c (sim_fetch_register, sim_store_register): Read/write
807 FGR from correct location.
808 (sim_open): Set size of FGR's according to
809 WITH_TARGET_FLOATING_POINT_BITSIZE.
810
811 * sim-main.h (FGR): Store floating point registers in a separate
812 array.
813
814Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
815
816 * configure: Regenerated to track ../common/aclocal.m4 changes.
817
818Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
819
820 * interp.c (ColdReset): Call PENDING_INVALIDATE.
821
822 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
823
824 * interp.c (pending_tick): New function. Deliver pending writes.
825
826 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
827 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
828 it can handle mixed sized quantites and single bits.
829
830Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
831
832 * interp.c (oengine.h): Do not include when building with IGEN.
833 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
834 (sim_info): Ditto for PROCESSOR_64BIT.
835 (sim_monitor): Replace ut_reg with unsigned_word.
836 (*): Ditto for t_reg.
837 (LOADDRMASK): Define.
838 (sim_open): Remove defunct check that host FP is IEEE compliant,
839 using software to emulate floating point.
840 (value_fpr, ...): Always compile, was conditional on HASFPU.
841
842Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
843
844 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
845 size.
846
847 * interp.c (SD, CPU): Define.
848 (mips_option_handler): Set flags in each CPU.
849 (interrupt_event): Assume CPU 0 is the one being iterrupted.
850 (sim_close): Do not clear STATE, deleted anyway.
851 (sim_write, sim_read): Assume CPU zero's vm should be used for
852 data transfers.
853 (sim_create_inferior): Set the PC for all processors.
854 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
855 argument.
856 (mips16_entry): Pass correct nr of args to store_word, load_word.
857 (ColdReset): Cold reset all cpu's.
858 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
859 (sim_monitor, load_memory, store_memory, signal_exception): Use
860 `CPU' instead of STATE_CPU.
861
862
863 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
864 SD or CPU_.
865
866 * sim-main.h (signal_exception): Add sim_cpu arg.
867 (SignalException*): Pass both SD and CPU to signal_exception.
868 * interp.c (signal_exception): Update.
869
870 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
871 Ditto
872 (sync_operation, prefetch, cache_op, store_memory, load_memory,
873 address_translation): Ditto
874 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
875
876Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
877
878 * configure: Regenerated to track ../common/aclocal.m4 changes.
879
880Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
881
882 * interp.c (sim_engine_run): Add `nr_cpus' argument.
883
884 * mips.igen (model): Map processor names onto BFD name.
885
886 * sim-main.h (CPU_CIA): Delete.
887 (SET_CIA, GET_CIA): Define
888
889Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
892 regiser.
893
894 * configure.in (default_endian): Configure a big-endian simulator
895 by default.
896 * configure: Re-generate.
897
898Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
899
900 * configure: Regenerated to track ../common/aclocal.m4 changes.
901
902Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
903
904 * interp.c (sim_monitor): Handle Densan monitor outbyte
905 and inbyte functions.
906
9071997-12-29 Felix Lee <flee@cygnus.com>
908
909 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
910
911Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
912
913 * Makefile.in (tmp-igen): Arrange for $zero to always be
914 reset to zero after every instruction.
915
916Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
917
918 * configure: Regenerated to track ../common/aclocal.m4 changes.
919 * config.in: Ditto.
920
921Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
922
923 * mips.igen (MSUB): Fix to work like MADD.
924 * gencode.c (MSUB): Similarly.
925
926Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
927
928 * configure: Regenerated to track ../common/aclocal.m4 changes.
929
930Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
933
934Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * sim-main.h (sim-fpu.h): Include.
937
938 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
939 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
940 using host independant sim_fpu module.
941
942Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * interp.c (signal_exception): Report internal errors with SIGABRT
945 not SIGQUIT.
946
947 * sim-main.h (C0_CONFIG): New register.
948 (signal.h): No longer include.
949
950 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
951
952Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
953
954 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
955
956Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
957
958 * mips.igen: Tag vr5000 instructions.
959 (ANDI): Was missing mipsIV model, fix assembler syntax.
960 (do_c_cond_fmt): New function.
961 (C.cond.fmt): Handle mips I-III which do not support CC field
962 separatly.
963 (bc1): Handle mips IV which do not have a delaed FCC separatly.
964 (SDR): Mask paddr when BigEndianMem, not the converse as specified
965 in IV3.2 spec.
966 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
967 vr5000 which saves LO in a GPR separatly.
968
969 * configure.in (enable-sim-igen): For vr5000, select vr5000
970 specific instructions.
971 * configure: Re-generate.
972
973Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * Makefile.in (SIM_OBJS): Add sim-fpu module.
976
977 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
978 fmt_uninterpreted_64 bit cases to switch. Convert to
979 fmt_formatted,
980
981 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
982
983 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
984 as specified in IV3.2 spec.
985 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
986
987Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
988
989 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
990 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
991 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
992 PENDING_FILL versions of instructions. Simplify.
993 (X): New function.
994 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
995 instructions.
996 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
997 a signed value.
998 (MTHI, MFHI): Disable code checking HI-LO.
999
1000 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1001 global.
1002 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1003
1004Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1005
1006 * gencode.c (build_mips16_operands): Replace IPC with cia.
1007
1008 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1009 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1010 IPC to `cia'.
1011 (UndefinedResult): Replace function with macro/function
1012 combination.
1013 (sim_engine_run): Don't save PC in IPC.
1014
1015 * sim-main.h (IPC): Delete.
1016
1017
1018 * interp.c (signal_exception, store_word, load_word,
1019 address_translation, load_memory, store_memory, cache_op,
1020 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1021 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1022 current instruction address - cia - argument.
1023 (sim_read, sim_write): Call address_translation directly.
1024 (sim_engine_run): Rename variable vaddr to cia.
1025 (signal_exception): Pass cia to sim_monitor
1026
1027 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1028 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1029 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1030
1031 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1032 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1033 SIM_ASSERT.
1034
1035 * interp.c (signal_exception): Pass restart address to
1036 sim_engine_restart.
1037
1038 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1039 idecode.o): Add dependency.
1040
1041 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1042 Delete definitions
1043 (DELAY_SLOT): Update NIA not PC with branch address.
1044 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1045
1046 * mips.igen: Use CIA not PC in branch calculations.
1047 (illegal): Call SignalException.
1048 (BEQ, ADDIU): Fix assembler.
1049
1050Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1051
1052 * m16.igen (JALX): Was missing.
1053
1054 * configure.in (enable-sim-igen): New configuration option.
1055 * configure: Re-generate.
1056
1057 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1058
1059 * interp.c (load_memory, store_memory): Delete parameter RAW.
1060 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1061 bypassing {load,store}_memory.
1062
1063 * sim-main.h (ByteSwapMem): Delete definition.
1064
1065 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1066
1067 * interp.c (sim_do_command, sim_commands): Delete mips specific
1068 commands. Handled by module sim-options.
1069
1070 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1071 (WITH_MODULO_MEMORY): Define.
1072
1073 * interp.c (sim_info): Delete code printing memory size.
1074
1075 * interp.c (mips_size): Nee sim_size, delete function.
1076 (power2): Delete.
1077 (monitor, monitor_base, monitor_size): Delete global variables.
1078 (sim_open, sim_close): Delete code creating monitor and other
1079 memory regions. Use sim-memopts module, via sim_do_commandf, to
1080 manage memory regions.
1081 (load_memory, store_memory): Use sim-core for memory model.
1082
1083 * interp.c (address_translation): Delete all memory map code
1084 except line forcing 32 bit addresses.
1085
1086Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1089 trace options.
1090
1091 * interp.c (logfh, logfile): Delete globals.
1092 (sim_open, sim_close): Delete code opening & closing log file.
1093 (mips_option_handler): Delete -l and -n options.
1094 (OPTION mips_options): Ditto.
1095
1096 * interp.c (OPTION mips_options): Rename option trace to dinero.
1097 (mips_option_handler): Update.
1098
1099Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1100
1101 * interp.c (fetch_str): New function.
1102 (sim_monitor): Rewrite using sim_read & sim_write.
1103 (sim_open): Check magic number.
1104 (sim_open): Write monitor vectors into memory using sim_write.
1105 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1106 (sim_read, sim_write): Simplify - transfer data one byte at a
1107 time.
1108 (load_memory, store_memory): Clarify meaning of parameter RAW.
1109
1110 * sim-main.h (isHOST): Defete definition.
1111 (isTARGET): Mark as depreciated.
1112 (address_translation): Delete parameter HOST.
1113
1114 * interp.c (address_translation): Delete parameter HOST.
1115
1116Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * mips.igen:
1119
1120 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1121 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1122
1123Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1124
1125 * mips.igen: Add model filter field to records.
1126
1127Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1128
1129 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1130
1131 interp.c (sim_engine_run): Do not compile function sim_engine_run
1132 when WITH_IGEN == 1.
1133
1134 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1135 target architecture.
1136
1137 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1138 igen. Replace with configuration variables sim_igen_flags /
1139 sim_m16_flags.
1140
1141 * m16.igen: New file. Copy mips16 insns here.
1142 * mips.igen: From here.
1143
1144Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1147 to top.
1148 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1149
1150Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1151
1152 * gencode.c (build_instruction): Follow sim_write's lead in using
1153 BigEndianMem instead of !ByteSwapMem.
1154
1155Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1156
1157 * configure.in (sim_gen): Dependent on target, select type of
1158 generator. Always select old style generator.
1159
1160 configure: Re-generate.
1161
1162 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1163 targets.
1164 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1165 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1166 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1167 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1168 SIM_@sim_gen@_*, set by autoconf.
1169
1170Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1171
1172 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1173
1174 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1175 CURRENT_FLOATING_POINT instead.
1176
1177 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1178 (address_translation): Raise exception InstructionFetch when
1179 translation fails and isINSTRUCTION.
1180
1181 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1182 sim_engine_run): Change type of of vaddr and paddr to
1183 address_word.
1184 (address_translation, prefetch, load_memory, store_memory,
1185 cache_op): Change type of vAddr and pAddr to address_word.
1186
1187 * gencode.c (build_instruction): Change type of vaddr and paddr to
1188 address_word.
1189
1190Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1193 macro to obtain result of ALU op.
1194
1195Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1196
1197 * interp.c (sim_info): Call profile_print.
1198
1199Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1202
1203 * sim-main.h (WITH_PROFILE): Do not define, defined in
1204 common/sim-config.h. Use sim-profile module.
1205 (simPROFILE): Delete defintion.
1206
1207 * interp.c (PROFILE): Delete definition.
1208 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1209 (sim_close): Delete code writing profile histogram.
1210 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1211 Delete.
1212 (sim_engine_run): Delete code profiling the PC.
1213
1214Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1215
1216 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1217
1218 * interp.c (sim_monitor): Make register pointers of type
1219 unsigned_word*.
1220
1221 * sim-main.h: Make registers of type unsigned_word not
1222 signed_word.
1223
1224Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * interp.c (sync_operation): Rename from SyncOperation, make
1227 global, add SD argument.
1228 (prefetch): Rename from Prefetch, make global, add SD argument.
1229 (decode_coproc): Make global.
1230
1231 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1232
1233 * gencode.c (build_instruction): Generate DecodeCoproc not
1234 decode_coproc calls.
1235
1236 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1237 (SizeFGR): Move to sim-main.h
1238 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1239 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1240 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1241 sim-main.h.
1242 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1243 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1244 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1245 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1246 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1247 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1248
1249 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1250 exception.
1251 (sim-alu.h): Include.
1252 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1253 (sim_cia): Typedef to instruction_address.
1254
1255Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1256
1257 * Makefile.in (interp.o): Rename generated file engine.c to
1258 oengine.c.
1259
1260 * interp.c: Update.
1261
1262Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1265
1266Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267
1268 * gencode.c (build_instruction): For "FPSQRT", output correct
1269 number of arguments to Recip.
1270
1271Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * Makefile.in (interp.o): Depends on sim-main.h
1274
1275 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1276
1277 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1278 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1279 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1280 STATE, DSSTATE): Define
1281 (GPR, FGRIDX, ..): Define.
1282
1283 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1284 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1285 (GPR, FGRIDX, ...): Delete macros.
1286
1287 * interp.c: Update names to match defines from sim-main.h
1288
1289Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 * interp.c (sim_monitor): Add SD argument.
1292 (sim_warning): Delete. Replace calls with calls to
1293 sim_io_eprintf.
1294 (sim_error): Delete. Replace calls with sim_io_error.
1295 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1296 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1297 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1298 argument.
1299 (mips_size): Rename from sim_size. Add SD argument.
1300
1301 * interp.c (simulator): Delete global variable.
1302 (callback): Delete global variable.
1303 (mips_option_handler, sim_open, sim_write, sim_read,
1304 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1305 sim_size,sim_monitor): Use sim_io_* not callback->*.
1306 (sim_open): ZALLOC simulator struct.
1307 (PROFILE): Do not define.
1308
1309Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1312 support.h with corresponding code.
1313
1314 * sim-main.h (word64, uword64), support.h: Move definition to
1315 sim-main.h.
1316 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1317
1318 * support.h: Delete
1319 * Makefile.in: Update dependencies
1320 * interp.c: Do not include.
1321
1322Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323
1324 * interp.c (address_translation, load_memory, store_memory,
1325 cache_op): Rename to from AddressTranslation et.al., make global,
1326 add SD argument
1327
1328 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1329 CacheOp): Define.
1330
1331 * interp.c (SignalException): Rename to signal_exception, make
1332 global.
1333
1334 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1335
1336 * sim-main.h (SignalException, SignalExceptionInterrupt,
1337 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1338 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1339 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1340 Define.
1341
1342 * interp.c, support.h: Use.
1343
1344Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1345
1346 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1347 to value_fpr / store_fpr. Add SD argument.
1348 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1349 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1350
1351 * sim-main.h (ValueFPR, StoreFPR): Define.
1352
1353Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1354
1355 * interp.c (sim_engine_run): Check consistency between configure
1356 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1357 and HASFPU.
1358
1359 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1360 (mips_fpu): Configure WITH_FLOATING_POINT.
1361 (mips_endian): Configure WITH_TARGET_ENDIAN.
1362 * configure: Update.
1363
1364Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * configure: Regenerated to track ../common/aclocal.m4 changes.
1367
1368Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1369
1370 * configure: Regenerated.
1371
1372Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1373
1374 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1375
1376Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1377
1378 * gencode.c (print_igen_insn_models): Assume certain architectures
1379 include all mips* instructions.
1380 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1381 instruction.
1382
1383 * Makefile.in (tmp.igen): Add target. Generate igen input from
1384 gencode file.
1385
1386 * gencode.c (FEATURE_IGEN): Define.
1387 (main): Add --igen option. Generate output in igen format.
1388 (process_instructions): Format output according to igen option.
1389 (print_igen_insn_format): New function.
1390 (print_igen_insn_models): New function.
1391 (process_instructions): Only issue warnings and ignore
1392 instructions when no FEATURE_IGEN.
1393
1394Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1395
1396 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1397 MIPS targets.
1398
1399Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400
1401 * configure: Regenerated to track ../common/aclocal.m4 changes.
1402
1403Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404
1405 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1406 SIM_RESERVED_BITS): Delete, moved to common.
1407 (SIM_EXTRA_CFLAGS): Update.
1408
1409Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * configure.in: Configure non-strict memory alignment.
1412 * configure: Regenerated to track ../common/aclocal.m4 changes.
1413
1414Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * configure: Regenerated to track ../common/aclocal.m4 changes.
1417
1418Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1419
1420 * gencode.c (SDBBP,DERET): Added (3900) insns.
1421 (RFE): Turn on for 3900.
1422 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1423 (dsstate): Made global.
1424 (SUBTARGET_R3900): Added.
1425 (CANCELDELAYSLOT): New.
1426 (SignalException): Ignore SystemCall rather than ignore and
1427 terminate. Add DebugBreakPoint handling.
1428 (decode_coproc): New insns RFE, DERET; and new registers Debug
1429 and DEPC protected by SUBTARGET_R3900.
1430 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1431 bits explicitly.
1432 * Makefile.in,configure.in: Add mips subtarget option.
1433 * configure: Update.
1434
1435Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1436
1437 * gencode.c: Add r3900 (tx39).
1438
1439
1440Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1441
1442 * gencode.c (build_instruction): Don't need to subtract 4 for
1443 JALR, just 2.
1444
1445Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1446
1447 * interp.c: Correct some HASFPU problems.
1448
1449Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450
1451 * configure: Regenerated to track ../common/aclocal.m4 changes.
1452
1453Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * interp.c (mips_options): Fix samples option short form, should
1456 be `x'.
1457
1458Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * interp.c (sim_info): Enable info code. Was just returning.
1461
1462Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1465 MFC0.
1466
1467Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1470 constants.
1471 (build_instruction): Ditto for LL.
1472
1473Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1474
1475 * configure: Regenerated to track ../common/aclocal.m4 changes.
1476
1477Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1478
1479 * configure: Regenerated to track ../common/aclocal.m4 changes.
1480 * config.in: Ditto.
1481
1482Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 * interp.c (sim_open): Add call to sim_analyze_program, update
1485 call to sim_config.
1486
1487Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * interp.c (sim_kill): Delete.
1490 (sim_create_inferior): Add ABFD argument. Set PC from same.
1491 (sim_load): Move code initializing trap handlers from here.
1492 (sim_open): To here.
1493 (sim_load): Delete, use sim-hload.c.
1494
1495 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1496
1497Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * configure: Regenerated to track ../common/aclocal.m4 changes.
1500 * config.in: Ditto.
1501
1502Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * interp.c (sim_open): Add ABFD argument.
1505 (sim_load): Move call to sim_config from here.
1506 (sim_open): To here. Check return status.
1507
1508Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1509
1510 * gencode.c (build_instruction): Two arg MADD should
1511 not assign result to $0.
1512
1513Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1514
1515 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1516 * sim/mips/configure.in: Regenerate.
1517
1518Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1519
1520 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1521 signed8, unsigned8 et.al. types.
1522
1523 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1524 hosts when selecting subreg.
1525
1526Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1527
1528 * interp.c (sim_engine_run): Reset the ZERO register to zero
1529 regardless of FEATURE_WARN_ZERO.
1530 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1531
1532Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1535 (SignalException): For BreakPoints ignore any mode bits and just
1536 save the PC.
1537 (SignalException): Always set the CAUSE register.
1538
1539Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1542 exception has been taken.
1543
1544 * interp.c: Implement the ERET and mt/f sr instructions.
1545
1546Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * interp.c (SignalException): Don't bother restarting an
1549 interrupt.
1550
1551Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * interp.c (SignalException): Really take an interrupt.
1554 (interrupt_event): Only deliver interrupts when enabled.
1555
1556Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * interp.c (sim_info): Only print info when verbose.
1559 (sim_info) Use sim_io_printf for output.
1560
1561Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1562
1563 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1564 mips architectures.
1565
1566Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * interp.c (sim_do_command): Check for common commands if a
1569 simulator specific command fails.
1570
1571Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1572
1573 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1574 and simBE when DEBUG is defined.
1575
1576Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * interp.c (interrupt_event): New function. Pass exception event
1579 onto exception handler.
1580
1581 * configure.in: Check for stdlib.h.
1582 * configure: Regenerate.
1583
1584 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1585 variable declaration.
1586 (build_instruction): Initialize memval1.
1587 (build_instruction): Add UNUSED attribute to byte, bigend,
1588 reverse.
1589 (build_operands): Ditto.
1590
1591 * interp.c: Fix GCC warnings.
1592 (sim_get_quit_code): Delete.
1593
1594 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1595 * Makefile.in: Ditto.
1596 * configure: Re-generate.
1597
1598 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1599
1600Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (mips_option_handler): New function parse argumes using
1603 sim-options.
1604 (myname): Replace with STATE_MY_NAME.
1605 (sim_open): Delete check for host endianness - performed by
1606 sim_config.
1607 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1608 (sim_open): Move much of the initialization from here.
1609 (sim_load): To here. After the image has been loaded and
1610 endianness set.
1611 (sim_open): Move ColdReset from here.
1612 (sim_create_inferior): To here.
1613 (sim_open): Make FP check less dependant on host endianness.
1614
1615 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1616 run.
1617 * interp.c (sim_set_callbacks): Delete.
1618
1619 * interp.c (membank, membank_base, membank_size): Replace with
1620 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1621 (sim_open): Remove call to callback->init. gdb/run do this.
1622
1623 * interp.c: Update
1624
1625 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1626
1627 * interp.c (big_endian_p): Delete, replaced by
1628 current_target_byte_order.
1629
1630Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1631
1632 * interp.c (host_read_long, host_read_word, host_swap_word,
1633 host_swap_long): Delete. Using common sim-endian.
1634 (sim_fetch_register, sim_store_register): Use H2T.
1635 (pipeline_ticks): Delete. Handled by sim-events.
1636 (sim_info): Update.
1637 (sim_engine_run): Update.
1638
1639Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1642 reason from here.
1643 (SignalException): To here. Signal using sim_engine_halt.
1644 (sim_stop_reason): Delete, moved to common.
1645
1646Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1647
1648 * interp.c (sim_open): Add callback argument.
1649 (sim_set_callbacks): Delete SIM_DESC argument.
1650 (sim_size): Ditto.
1651
1652Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * Makefile.in (SIM_OBJS): Add common modules.
1655
1656 * interp.c (sim_set_callbacks): Also set SD callback.
1657 (set_endianness, xfer_*, swap_*): Delete.
1658 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1659 Change to functions using sim-endian macros.
1660 (control_c, sim_stop): Delete, use common version.
1661 (simulate): Convert into.
1662 (sim_engine_run): This function.
1663 (sim_resume): Delete.
1664
1665 * interp.c (simulation): New variable - the simulator object.
1666 (sim_kind): Delete global - merged into simulation.
1667 (sim_load): Cleanup. Move PC assignment from here.
1668 (sim_create_inferior): To here.
1669
1670 * sim-main.h: New file.
1671 * interp.c (sim-main.h): Include.
1672
1673Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1674
1675 * configure: Regenerated to track ../common/aclocal.m4 changes.
1676
1677Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1678
1679 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1680
1681Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1682
1683 * gencode.c (build_instruction): DIV instructions: check
1684 for division by zero and integer overflow before using
1685 host's division operation.
1686
1687Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1688
1689 * Makefile.in (SIM_OBJS): Add sim-load.o.
1690 * interp.c: #include bfd.h.
1691 (target_byte_order): Delete.
1692 (sim_kind, myname, big_endian_p): New static locals.
1693 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1694 after argument parsing. Recognize -E arg, set endianness accordingly.
1695 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1696 load file into simulator. Set PC from bfd.
1697 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1698 (set_endianness): Use big_endian_p instead of target_byte_order.
1699
1700Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1701
1702 * interp.c (sim_size): Delete prototype - conflicts with
1703 definition in remote-sim.h. Correct definition.
1704
1705Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1706
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1708 * config.in: Ditto.
1709
1710Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1711
1712 * interp.c (sim_open): New arg `kind'.
1713
1714 * configure: Regenerated to track ../common/aclocal.m4 changes.
1715
1716Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1717
1718 * configure: Regenerated to track ../common/aclocal.m4 changes.
1719
1720Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1721
1722 * interp.c (sim_open): Set optind to 0 before calling getopt.
1723
1724Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1725
1726 * configure: Regenerated to track ../common/aclocal.m4 changes.
1727
1728Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1729
1730 * interp.c : Replace uses of pr_addr with pr_uword64
1731 where the bit length is always 64 independent of SIM_ADDR.
1732 (pr_uword64) : added.
1733
1734Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1735
1736 * configure: Re-generate.
1737
1738Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1739
1740 * configure: Regenerate to track ../common/aclocal.m4 changes.
1741
1742Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1743
1744 * interp.c (sim_open): New SIM_DESC result. Argument is now
1745 in argv form.
1746 (other sim_*): New SIM_DESC argument.
1747
1748Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1749
1750 * interp.c: Fix printing of addresses for non-64-bit targets.
1751 (pr_addr): Add function to print address based on size.
1752
1753Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1754
1755 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1756
1757Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1758
1759 * gencode.c (build_mips16_operands): Correct computation of base
1760 address for extended PC relative instruction.
1761
1762Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1763
1764 * interp.c (mips16_entry): Add support for floating point cases.
1765 (SignalException): Pass floating point cases to mips16_entry.
1766 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1767 registers.
1768 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1769 or fmt_word.
1770 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1771 and then set the state to fmt_uninterpreted.
1772 (COP_SW): Temporarily set the state to fmt_word while calling
1773 ValueFPR.
1774
1775Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1776
1777 * gencode.c (build_instruction): The high order may be set in the
1778 comparison flags at any ISA level, not just ISA 4.
1779
1780Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1781
1782 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1783 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1784 * configure.in: sinclude ../common/aclocal.m4.
1785 * configure: Regenerated.
1786
1787Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1788
1789 * configure: Rebuild after change to aclocal.m4.
1790
1791Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1792
1793 * configure configure.in Makefile.in: Update to new configure
1794 scheme which is more compatible with WinGDB builds.
1795 * configure.in: Improve comment on how to run autoconf.
1796 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1797 * Makefile.in: Use autoconf substitution to install common
1798 makefile fragment.
1799
1800Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1801
1802 * gencode.c (build_instruction): Use BigEndianCPU instead of
1803 ByteSwapMem.
1804
1805Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1806
1807 * interp.c (sim_monitor): Make output to stdout visible in
1808 wingdb's I/O log window.
1809
1810Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1811
1812 * support.h: Undo previous change to SIGTRAP
1813 and SIGQUIT values.
1814
1815Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1816
1817 * interp.c (store_word, load_word): New static functions.
1818 (mips16_entry): New static function.
1819 (SignalException): Look for mips16 entry and exit instructions.
1820 (simulate): Use the correct index when setting fpr_state after
1821 doing a pending move.
1822
1823Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1824
1825 * interp.c: Fix byte-swapping code throughout to work on
1826 both little- and big-endian hosts.
1827
1828Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1829
1830 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1831 with gdb/config/i386/xm-windows.h.
1832
1833Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1834
1835 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1836 that messes up arithmetic shifts.
1837
1838Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1839
1840 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1841 SIGTRAP and SIGQUIT for _WIN32.
1842
1843Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1844
1845 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1846 force a 64 bit multiplication.
1847 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1848 destination register is 0, since that is the default mips16 nop
1849 instruction.
1850
1851Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1852
1853 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1854 (build_endian_shift): Don't check proc64.
1855 (build_instruction): Always set memval to uword64. Cast op2 to
1856 uword64 when shifting it left in memory instructions. Always use
1857 the same code for stores--don't special case proc64.
1858
1859 * gencode.c (build_mips16_operands): Fix base PC value for PC
1860 relative operands.
1861 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1862 jal instruction.
1863 * interp.c (simJALDELAYSLOT): Define.
1864 (JALDELAYSLOT): Define.
1865 (INDELAYSLOT, INJALDELAYSLOT): Define.
1866 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1867
1868Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1869
1870 * interp.c (sim_open): add flush_cache as a PMON routine
1871 (sim_monitor): handle flush_cache by ignoring it
1872
1873Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1874
1875 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1876 BigEndianMem.
1877 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1878 (BigEndianMem): Rename to ByteSwapMem and change sense.
1879 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1880 BigEndianMem references to !ByteSwapMem.
1881 (set_endianness): New function, with prototype.
1882 (sim_open): Call set_endianness.
1883 (sim_info): Use simBE instead of BigEndianMem.
1884 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1885 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1886 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1887 ifdefs, keeping the prototype declaration.
1888 (swap_word): Rewrite correctly.
1889 (ColdReset): Delete references to CONFIG. Delete endianness related
1890 code; moved to set_endianness.
1891
1892Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1893
1894 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1895 * interp.c (CHECKHILO): Define away.
1896 (simSIGINT): New macro.
1897 (membank_size): Increase from 1MB to 2MB.
1898 (control_c): New function.
1899 (sim_resume): Rename parameter signal to signal_number. Add local
1900 variable prev. Call signal before and after simulate.
1901 (sim_stop_reason): Add simSIGINT support.
1902 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1903 functions always.
1904 (sim_warning): Delete call to SignalException. Do call printf_filtered
1905 if logfh is NULL.
1906 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1907 a call to sim_warning.
1908
1909Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1910
1911 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1912 16 bit instructions.
1913
1914Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1915
1916 Add support for mips16 (16 bit MIPS implementation):
1917 * gencode.c (inst_type): Add mips16 instruction encoding types.
1918 (GETDATASIZEINSN): Define.
1919 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1920 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1921 mtlo.
1922 (MIPS16_DECODE): New table, for mips16 instructions.
1923 (bitmap_val): New static function.
1924 (struct mips16_op): Define.
1925 (mips16_op_table): New table, for mips16 operands.
1926 (build_mips16_operands): New static function.
1927 (process_instructions): If PC is odd, decode a mips16
1928 instruction. Break out instruction handling into new
1929 build_instruction function.
1930 (build_instruction): New static function, broken out of
1931 process_instructions. Check modifiers rather than flags for SHIFT
1932 bit count and m[ft]{hi,lo} direction.
1933 (usage): Pass program name to fprintf.
1934 (main): Remove unused variable this_option_optind. Change
1935 ``*loptarg++'' to ``loptarg++''.
1936 (my_strtoul): Parenthesize && within ||.
1937 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1938 (simulate): If PC is odd, fetch a 16 bit instruction, and
1939 increment PC by 2 rather than 4.
1940 * configure.in: Add case for mips16*-*-*.
1941 * configure: Rebuild.
1942
1943Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1944
1945 * interp.c: Allow -t to enable tracing in standalone simulator.
1946 Fix garbage output in trace file and error messages.
1947
1948Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1949
1950 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1951 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1952 * configure.in: Simplify using macros in ../common/aclocal.m4.
1953 * configure: Regenerated.
1954 * tconfig.in: New file.
1955
1956Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1957
1958 * interp.c: Fix bugs in 64-bit port.
1959 Use ansi function declarations for msvc compiler.
1960 Initialize and test file pointer in trace code.
1961 Prevent duplicate definition of LAST_EMED_REGNUM.
1962
1963Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1964
1965 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1966
1967Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1968
1969 * interp.c (SignalException): Check for explicit terminating
1970 breakpoint value.
1971 * gencode.c: Pass instruction value through SignalException()
1972 calls for Trap, Breakpoint and Syscall.
1973
1974Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1975
1976 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1977 only used on those hosts that provide it.
1978 * configure.in: Add sqrt() to list of functions to be checked for.
1979 * config.in: Re-generated.
1980 * configure: Re-generated.
1981
1982Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1983
1984 * gencode.c (process_instructions): Call build_endian_shift when
1985 expanding STORE RIGHT, to fix swr.
1986 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1987 clear the high bits.
1988 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1989 Fix float to int conversions to produce signed values.
1990
1991Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1992
1993 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1994 (process_instructions): Correct handling of nor instruction.
1995 Correct shift count for 32 bit shift instructions. Correct sign
1996 extension for arithmetic shifts to not shift the number of bits in
1997 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1998 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1999 Fix madd.
2000 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2001 It's OK to have a mult follow a mult. What's not OK is to have a
2002 mult follow an mfhi.
2003 (Convert): Comment out incorrect rounding code.
2004
2005Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2006
2007 * interp.c (sim_monitor): Improved monitor printf
2008 simulation. Tidied up simulator warnings, and added "--log" option
2009 for directing warning message output.
2010 * gencode.c: Use sim_warning() rather than WARNING macro.
2011
2012Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2013
2014 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2015 getopt1.o, rather than on gencode.c. Link objects together.
2016 Don't link against -liberty.
2017 (gencode.o, getopt.o, getopt1.o): New targets.
2018 * gencode.c: Include <ctype.h> and "ansidecl.h".
2019 (AND): Undefine after including "ansidecl.h".
2020 (ULONG_MAX): Define if not defined.
2021 (OP_*): Don't define macros; now defined in opcode/mips.h.
2022 (main): Call my_strtoul rather than strtoul.
2023 (my_strtoul): New static function.
2024
2025Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2026
2027 * gencode.c (process_instructions): Generate word64 and uword64
2028 instead of `long long' and `unsigned long long' data types.
2029 * interp.c: #include sysdep.h to get signals, and define default
2030 for SIGBUS.
2031 * (Convert): Work around for Visual-C++ compiler bug with type
2032 conversion.
2033 * support.h: Make things compile under Visual-C++ by using
2034 __int64 instead of `long long'. Change many refs to long long
2035 into word64/uword64 typedefs.
2036
2037Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2038
2039 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2040 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2041 (docdir): Removed.
2042 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2043 (AC_PROG_INSTALL): Added.
2044 (AC_PROG_CC): Moved to before configure.host call.
2045 * configure: Rebuilt.
2046
2047Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2048
2049 * configure.in: Define @SIMCONF@ depending on mips target.
2050 * configure: Rebuild.
2051 * Makefile.in (run): Add @SIMCONF@ to control simulator
2052 construction.
2053 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2054 * interp.c: Remove some debugging, provide more detailed error
2055 messages, update memory accesses to use LOADDRMASK.
2056
2057Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2058
2059 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2060 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2061 stamp-h.
2062 * configure: Rebuild.
2063 * config.in: New file, generated by autoheader.
2064 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2065 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2066 HAVE_ANINT and HAVE_AINT, as appropriate.
2067 * Makefile.in (run): Use @LIBS@ rather than -lm.
2068 (interp.o): Depend upon config.h.
2069 (Makefile): Just rebuild Makefile.
2070 (clean): Remove stamp-h.
2071 (mostlyclean): Make the same as clean, not as distclean.
2072 (config.h, stamp-h): New targets.
2073
2074Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2075
2076 * interp.c (ColdReset): Fix boolean test. Make all simulator
2077 globals static.
2078
2079Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2080
2081 * interp.c (xfer_direct_word, xfer_direct_long,
2082 swap_direct_word, swap_direct_long, xfer_big_word,
2083 xfer_big_long, xfer_little_word, xfer_little_long,
2084 swap_word,swap_long): Added.
2085 * interp.c (ColdReset): Provide function indirection to
2086 host<->simulated_target transfer routines.
2087 * interp.c (sim_store_register, sim_fetch_register): Updated to
2088 make use of indirected transfer routines.
2089
2090Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2091
2092 * gencode.c (process_instructions): Ensure FP ABS instruction
2093 recognised.
2094 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2095 system call support.
2096
2097Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2098
2099 * interp.c (sim_do_command): Complain if callback structure not
2100 initialised.
2101
2102Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2103
2104 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2105 support for Sun hosts.
2106 * Makefile.in (gencode): Ensure the host compiler and libraries
2107 used for cross-hosted build.
2108
2109Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2110
2111 * interp.c, gencode.c: Some more (TODO) tidying.
2112
2113Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2114
2115 * gencode.c, interp.c: Replaced explicit long long references with
2116 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2117 * support.h (SET64LO, SET64HI): Macros added.
2118
2119Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2120
2121 * configure: Regenerate with autoconf 2.7.
2122
2123Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2124
2125 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2126 * support.h: Remove superfluous "1" from #if.
2127 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2128
2129Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2130
2131 * interp.c (StoreFPR): Control UndefinedResult() call on
2132 WARN_RESULT manifest.
2133
2134Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2135
2136 * gencode.c: Tidied instruction decoding, and added FP instruction
2137 support.
2138
2139 * interp.c: Added dineroIII, and BSD profiling support. Also
2140 run-time FP handling.
2141
2142Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2143
2144 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2145 gencode.c, interp.c, support.h: created.
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