bpf: opcodes, gas: support for signed register move V4 instructions

This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
	(BPF_OFFSET16_MOVS16): Likewise.
	(BPF_OFFSET16_MOVS32): Likewise.
	(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R instructions.  and MOVS32I instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.s: Test movs instructions.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu.d: Add expected results.
	* testsuite/gas/bpf/alu32.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3d22461266a30a456e2b5f4bee9fdf7f713fc90a..66c95a1b9a5bdbd3e54c860b7d7f02323f31b1cc 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * testsuite/gas/bpf/alu.s: Test movs instructions.
+       * testsuite/gas/bpf/alu-pseudoc.s: Likewise.
+       * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
+       * testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
+       * testsuite/gas/bpf/alu.d: Add expected results.
+       * testsuite/gas/bpf/alu32.d: Likewise.
+       * testsuite/gas/bpf/alu-be.d: Likewise.
+       * testsuite/gas/bpf/alu32-be.d: Likewise.
+       * testsuite/gas/bpf/alu-pseudoc.d: Likewise.
+       * testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
+       * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
+       * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
+
 2023-07-03  Nick Clifton  <nickc@redhat.com>
 
        * configure: Regenerate.

diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
index 4742f89ea170ce3a4848df93bb7a28cd7bf79a41..a3814e95c3a9eca5af417ec2307f773a5e8e0371 100644 (file)
--- a/gas/doc/c-bpf.texi
+++ b/gas/doc/c-bpf.texi
@@ -259,6 +259,18 @@ ambiguity in the pseudoc syntax.
 @itemx rd = imm32
 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
 in @code{rd}.
+
+@item movs rd, rs, 8
+@itemx rd s= (i8) rs
+Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
+
+@item movs rd, rs, 16
+@itemx rd s= (i16) rs
+Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
+
+@item movs rd, rs, 32
+@itemx rd s= (i32) rs
+Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
 @end table
 
 @subsection 32-bit arithmetic instructions
@@ -354,6 +366,18 @@ ambiguity in the pseudoc syntax.
 @itemx rd = imm32
 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
 in @code{rd}.
+
+@item mov32s rd, rs, 8
+@itemx rd s= (i8) rs
+Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
+
+@item mov32s rd, rs, 16
+@itemx rd s= (i16) rs
+Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
+
+@item mov32s rd, rs, 32
+@itemx rd s= (i32) rs
+Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
 @end table
 
 @subsection Endianness conversion instructions

diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
index 8d8c29e91c759693a96b68b7a2dc8a188a3b48cd..486d7923478bb3b6b91128dbd6509917af74b34f 100644 (file)
--- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
@@ -63,3 +63,6 @@ Disassembly of section .text:
  1a0:  dc 60 00 00 00 00 00 10         r6=be16 r6
  1a8:  dc 50 00 00 00 00 00 20         r5=be32 r5
  1b0:  dc 40 00 00 00 00 00 40         r4=be64 r4
+ 1b8:  bf 12 00 08 00 00 00 00         r1 s= \(i8\) r2
+ 1c0:  bf 12 00 10 00 00 00 00         r1 s= \(i16\) r2
+ 1c8:  bf 12 00 20 00 00 00 00         r1 s= \(i32\) r2

diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d
index 170db4b853d9cae12592ea8da82fcb2a2bd79628..a082c46af1cc3f9604781a82ebdfa66b9218b837 100644 (file)
--- a/gas/testsuite/gas/bpf/alu-be.d
+++ b/gas/testsuite/gas/bpf/alu-be.d
@@ -63,3 +63,6 @@ Disassembly of section .text:
  1a0:  dc 60 00 00 00 00 00 10         endbe %r6,16
  1a8:  dc 50 00 00 00 00 00 20         endbe %r5,32
  1b0:  dc 40 00 00 00 00 00 40         endbe %r4,64
+ 1b8:  bf 12 00 08 00 00 00 00         movs %r1,%r2,8
+ 1c0:  bf 12 00 10 00 00 00 00         movs %r1,%r2,16
+ 1c8:  bf 12 00 20 00 00 00 00         movs %r1,%r2,32

diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d
index 5d69e68a4f0cf7ca980ae2d31b18e5adfc93d670..cf1ef2ac0295ffbce8094bc12001f21b8e323f7b 100644 (file)
--- a/gas/testsuite/gas/bpf/alu-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.d
@@ -63,3 +63,6 @@ Disassembly of section .text:
  1a0:  dc 06 00 00 10 00 00 00         r6=be16 r6
  1a8:  dc 05 00 00 20 00 00 00         r5=be32 r5
  1b0:  dc 04 00 00 40 00 00 00         r4=be64 r4
+ 1b8:  bf 21 08 00 00 00 00 00         r1 s= \(i8\) r2
+ 1c0:  bf 21 10 00 00 00 00 00         r1 s= \(i16\) r2
+ 1c8:  bf 21 20 00 00 00 00 00         r1 s= \(i32\) r2

diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s
index a271bef977d55b4ff9114061b462ab4b9ed3ddee..513c8b8f4f9b48d95165e6f8db41a1014134b747 100644 (file)
--- a/gas/testsuite/gas/bpf/alu-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.s
@@ -55,3 +55,6 @@
        r6 = be16 r6
        r5 = be32 r5
        r4 = be64 r4
+        r1 s= (i8) r2
+        r1 s= (i16) r2
+        r1 s= (i32) r2

diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d
index 476891b9afd4fbe342819148104a4191cf5a31a2..409018ddf5577e7eb2f7a70265bbeebf4f46b451 100644 (file)
--- a/gas/testsuite/gas/bpf/alu.d
+++ b/gas/testsuite/gas/bpf/alu.d
@@ -63,3 +63,6 @@ Disassembly of section .text:
  1a0:  dc 06 00 00 10 00 00 00         endbe %r6,16
  1a8:  dc 05 00 00 20 00 00 00         endbe %r5,32
  1b0:  dc 04 00 00 40 00 00 00         endbe %r4,64
+ 1b8:  bf 21 08 00 00 00 00 00         movs %r1,%r2,8
+ 1c0:  bf 21 10 00 00 00 00 00         movs %r1,%r2,16
+ 1c8:  bf 21 20 00 00 00 00 00         movs %r1,%r2,32

diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s
index bb3f926520076c6baa19122242708f744ca31de7..6f8c30fff6803266830b60c4c04bfbb8de2ed8cd 100644 (file)
--- a/gas/testsuite/gas/bpf/alu.s
+++ b/gas/testsuite/gas/bpf/alu.s
@@ -55,3 +55,6 @@
         endbe  %r6,16
         endbe  %r5,32
         endbe  %r4,64
+        movs    %r1,%r2,8
+        movs    %r1,%r2,16
+        movs    %r1,%r2,32

diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
index 6daad3b6926387d727d54793c38648200239c423..79a638fb37ef1d2b5f3426fac7ff55b2e5905f73 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
@@ -57,3 +57,6 @@ Disassembly of section .text:
  170:  c4 40 00 00 7e ad be ef         w4 s>>=0x7eadbeef
  178:  cc 56 00 00 00 00 00 00         w5 s>>=w6
  180:  8c 23 00 00 00 00 00 00         w2=-w3
+ 188:  bc 12 00 08 00 00 00 00         w1 s= \(i8\) w2
+ 190:  bc 12 00 10 00 00 00 00         w1 s= \(i16\) w2
+ 198:  bc 12 00 20 00 00 00 00         w1 s= \(i32\) w2

diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d
index 6de8f0660d83f95d341b112311abf884ccc598be..0549bf2313115a27e37c08a32f013b311eb97a74 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32-be.d
+++ b/gas/testsuite/gas/bpf/alu32-be.d
@@ -57,3 +57,6 @@ Disassembly of section .text:
  170:  c4 40 00 00 7e ad be ef         arsh32 %r4,0x7eadbeef
  178:  cc 56 00 00 00 00 00 00         arsh32 %r5,%r6
  180:  8c 23 00 00 00 00 00 00         neg32 %r2,%r3
+ 188:  bc 12 00 08 00 00 00 00         movs32 %r1,%r2,8
+ 190:  bc 12 00 10 00 00 00 00         movs32 %r1,%r2,16
+ 198:  bc 12 00 20 00 00 00 00         movs32 %r1,%r2,32

diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d
index f339c808d260ea48f99822d284de85a6ef3936cd..175dd1f1cd611f01d54d6db004e80f97397bb63d 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d
@@ -57,3 +57,6 @@ Disassembly of section .text:
  170:  c4 04 00 00 ef be ad 7e         w4 s>>=0x7eadbeef
  178:  cc 65 00 00 00 00 00 00         w5 s>>=w6
  180:  8c 32 00 00 00 00 00 00         w2=-w3
+ 188:  bc 21 08 00 00 00 00 00         w1 s= \(i8\) w2
+ 190:  bc 21 10 00 00 00 00 00         w1 s= \(i16\) w2
+ 198:  bc 21 20 00 00 00 00 00         w1 s= \(i32\) w2

diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s
index 0a0d41fdf46d1cb8cf52d24fc66454385960a243..5a0e442154f832a4964e520e4a612b59287a8bad 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s
@@ -49,3 +49,6 @@
        w4 s>>= 2125315823
        w5 s>>= w6
        w2 = - w3
+        w1 s= (i8) w2
+        w1 s= (i16) w2
+        w1 s= (i32) w2

diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d
index 712d1c7328ed8b7729851740c7f9b099c0c3ab73..68aa86fce0911aab586b7c2d4a3f4b075d64c167 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32.d
+++ b/gas/testsuite/gas/bpf/alu32.d
@@ -57,3 +57,6 @@ Disassembly of section .text:
  170:  c4 04 00 00 ef be ad 7e         arsh32 %r4,0x7eadbeef
  178:  cc 65 00 00 00 00 00 00         arsh32 %r5,%r6
  180:  8c 32 00 00 00 00 00 00         neg32 %r2,%r3
+ 188:  bc 21 08 00 00 00 00 00         movs32 %r1,%r2,8
+ 190:  bc 21 10 00 00 00 00 00         movs32 %r1,%r2,16
+ 198:  bc 21 20 00 00 00 00 00         movs32 %r1,%r2,32

diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s
index f43ea4a4d236afa63441f704ac020dc18bbc7bb3..14f0a12de2c0c896eaf6f3d616ceda01ec2f0ffe 100644 (file)
--- a/gas/testsuite/gas/bpf/alu32.s
+++ b/gas/testsuite/gas/bpf/alu32.s
@@ -49,3 +49,6 @@
         arsh32 %r4, 0x7eadbeef
         arsh32 %r5, %r6
         neg32  %r2, %r3
+        movs32  %r1,%r2,8
+        movs32  %r1,%r2,16
+        movs32  %r1,%r2,32

diff --git a/include/ChangeLog b/include/ChangeLog
index f0c8fe875ea6fbd3f5b4f0cd481dc0a8b7d8e1f9..5872f284533aca351a626348f64631e34a021334 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,11 @@
+2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
+       (BPF_OFFSET16_MOVS16): Likewise.
+       (BPF_OFFSET16_MOVS32): Likewise.
+       (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
+       MOVS32{8,16,32}R.
+
 2023-07-03  Nick Clifton  <nickc@redhat.com>
 
        2.41 Branch Point.

diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
index f928979f86f570f2a4c15d7a0894d1f4fb6137de..48f06c264ba2aef2ce75a60f80300b816a54f2b5 100644 (file)
--- a/include/opcode/bpf.h
+++ b/include/opcode/bpf.h
@@ -131,6 +131,9 @@ typedef uint64_t bpf_insn_word;
    even if these are multi-byte or infra-byte.  Bleh.  */
 
 #define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32)
+#define BPF_OFFSET16_MOVS8 ((uint64_t)8 << 32)
+#define BPF_OFFSET16_MOVS16 ((uint64_t)16 << 32)
+#define BPF_OFFSET16_MOVS32 ((uint64_t)32 << 32)
 
 #define BPF_IMM32_END16 ((uint64_t)0x00000010)
 #define BPF_IMM32_END32 ((uint64_t)0x00000020)
@@ -162,6 +165,7 @@ enum bpf_insn_id
   BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,
   BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,
   BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,
+  BPF_INSN_MOVS8R, BPF_INSN_MOVS16R, BPF_INSN_MOVS32R,
   BPF_INSN_MOVR, BPF_INSN_MOVI,
   /* ALU32 instructions.  */
   BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I,
@@ -171,6 +175,7 @@ enum bpf_insn_id
   BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,
   BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
   BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
+  BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R,
   BPF_INSN_MOV32R, BPF_INSN_MOV32I,
   /* Endianness conversion instructions.  */
   BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f202d1941bcf65706b366dfe453efdf19dedd2a2..55d4e7d657fc236eddf620b423b88f034bee0fbe 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
+       MOVS32{8,16,32}R instructions.  and MOVS32I instructions.
+
 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
        * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c

diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index f89d93a5c78b3af92bcc332462f77ab97ad05bfa..72be1d956d56582bf4874bee013dfde66fe8c63c 100644 (file)
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -89,6 +89,12 @@ const struct bpf_opcode bpf_opcodes[] =
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
   {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
+  {BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=%w( i8 )%w%sr",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
+  {BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=%w( i16 )%w%sr",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
+  {BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=%w( i32 )%w%sr",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
   {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
   {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32",
@@ -151,6 +157,12 @@ const struct bpf_opcode bpf_opcodes[] =
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
   {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
+  {BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=%w( i8 )%w%sw",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
+  {BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=%w( i16 )%w%sw",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
+  {BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=%w( i32 )%w%sw",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
   {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
   {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",