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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
0430891c | 13 | #include "qemu/osdep.h" |
0d09e41a | 14 | #include "hw/isa/vt82c686.h" |
83c9f4ca | 15 | #include "hw/pci/pci.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
0d09e41a | 17 | #include "hw/isa/isa.h" |
98cf824b | 18 | #include "hw/isa/superio.h" |
d6454270 | 19 | #include "migration/vmstate.h" |
0d09e41a PB |
20 | #include "hw/isa/apm.h" |
21 | #include "hw/acpi/acpi.h" | |
22 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 23 | #include "qapi/error.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
911629e6 | 25 | #include "qemu/range.h" |
1de7afc9 | 26 | #include "qemu/timer.h" |
022c62cb | 27 | #include "exec/address-spaces.h" |
ff413a1f | 28 | #include "trace.h" |
edf79e66 | 29 | |
94349bff | 30 | OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM) |
edf79e66 | 31 | |
db1015e9 | 32 | struct VT686PMState { |
edf79e66 | 33 | PCIDevice dev; |
a2902821 | 34 | MemoryRegion io; |
355bf2e5 | 35 | ACPIREGS ar; |
edf79e66 | 36 | APMState apm; |
edf79e66 | 37 | PMSMBus smb; |
db1015e9 | 38 | }; |
edf79e66 | 39 | |
edf79e66 HC |
40 | static void pm_io_space_update(VT686PMState *s) |
41 | { | |
42 | uint32_t pm_io_base; | |
43 | ||
a2902821 GH |
44 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
45 | pm_io_base &= 0xffc0; | |
edf79e66 | 46 | |
a2902821 GH |
47 | memory_region_transaction_begin(); |
48 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
49 | memory_region_set_address(&s->io, pm_io_base); | |
50 | memory_region_transaction_commit(); | |
edf79e66 HC |
51 | } |
52 | ||
911629e6 BZ |
53 | static void smb_io_space_update(VT686PMState *s) |
54 | { | |
55 | uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; | |
56 | ||
57 | memory_region_transaction_begin(); | |
58 | memory_region_set_address(&s->smb.io, smbase); | |
59 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); | |
60 | memory_region_transaction_commit(); | |
61 | } | |
62 | ||
edf79e66 HC |
63 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
64 | { | |
65 | VT686PMState *s = opaque; | |
66 | ||
67 | pm_io_space_update(s); | |
911629e6 | 68 | smb_io_space_update(s); |
edf79e66 HC |
69 | return 0; |
70 | } | |
71 | ||
72 | static const VMStateDescription vmstate_acpi = { | |
73 | .name = "vt82c686b_pm", | |
74 | .version_id = 1, | |
75 | .minimum_version_id = 1, | |
edf79e66 | 76 | .post_load = vmstate_acpi_post_load, |
d49805ae | 77 | .fields = (VMStateField[]) { |
edf79e66 | 78 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
355bf2e5 GH |
79 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
80 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
81 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 82 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
e720677e | 83 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
355bf2e5 | 84 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
edf79e66 HC |
85 | VMSTATE_END_OF_LIST() |
86 | } | |
87 | }; | |
88 | ||
94349bff BZ |
89 | static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) |
90 | { | |
911629e6 BZ |
91 | VT686PMState *s = VT82C686B_PM(d); |
92 | ||
94349bff BZ |
93 | trace_via_pm_write(addr, val, len); |
94 | pci_default_write_config(d, addr, val, len); | |
911629e6 BZ |
95 | if (ranges_overlap(addr, len, 0x90, 4)) { |
96 | uint32_t v = pci_get_long(s->dev.config + 0x90); | |
97 | pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); | |
98 | } | |
99 | if (range_covers_byte(addr, len, 0xd2)) { | |
100 | s->dev.config[0xd2] &= 0xf; | |
101 | smb_io_space_update(s); | |
102 | } | |
94349bff BZ |
103 | } |
104 | ||
35e360ed BZ |
105 | static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) |
106 | { | |
107 | trace_via_pm_io_write(addr, data, size); | |
108 | } | |
109 | ||
110 | static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) | |
111 | { | |
112 | trace_via_pm_io_read(addr, 0, size); | |
113 | return 0; | |
114 | } | |
115 | ||
116 | static const MemoryRegionOps pm_io_ops = { | |
117 | .read = pm_io_read, | |
118 | .write = pm_io_write, | |
119 | .endianness = DEVICE_NATIVE_ENDIAN, | |
120 | .impl = { | |
121 | .min_access_size = 1, | |
122 | .max_access_size = 1, | |
123 | }, | |
124 | }; | |
125 | ||
94349bff BZ |
126 | static void pm_update_sci(VT686PMState *s) |
127 | { | |
128 | int sci_level, pmsts; | |
129 | ||
130 | pmsts = acpi_pm1_evt_get_sts(&s->ar); | |
131 | sci_level = (((pmsts & s->ar.pm1.evt.en) & | |
132 | (ACPI_BITMASK_RT_CLOCK_ENABLE | | |
133 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
134 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
135 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
136 | pci_set_irq(&s->dev, sci_level); | |
137 | /* schedule a timer interruption if needed */ | |
138 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && | |
139 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); | |
140 | } | |
141 | ||
142 | static void pm_tmr_timer(ACPIREGS *ar) | |
143 | { | |
144 | VT686PMState *s = container_of(ar, VT686PMState, ar); | |
145 | pm_update_sci(s); | |
146 | } | |
147 | ||
911629e6 BZ |
148 | static void vt82c686b_pm_reset(DeviceState *d) |
149 | { | |
150 | VT686PMState *s = VT82C686B_PM(d); | |
151 | ||
9af8e529 BZ |
152 | memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, |
153 | PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); | |
154 | /* Power Management IO base */ | |
155 | pci_set_long(s->dev.config + 0x48, 1); | |
911629e6 BZ |
156 | /* SMBus IO base */ |
157 | pci_set_long(s->dev.config + 0x90, 1); | |
911629e6 BZ |
158 | |
159 | smb_io_space_update(s); | |
160 | } | |
161 | ||
9af21dbe | 162 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 163 | { |
e6340505 | 164 | VT686PMState *s = VT82C686B_PM(dev); |
edf79e66 HC |
165 | uint8_t *pci_conf; |
166 | ||
167 | pci_conf = s->dev.config; | |
edf79e66 HC |
168 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
169 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
170 | PCI_STATUS_DEVSEL_MEDIUM); | |
171 | ||
a30c34d2 | 172 | pm_smbus_init(DEVICE(s), &s->smb, false); |
911629e6 BZ |
173 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); |
174 | memory_region_set_enabled(&s->smb.io, false); | |
edf79e66 | 175 | |
42d8a3cf | 176 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 177 | |
35e360ed | 178 | memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, |
40a0bba1 | 179 | "vt82c686-pm", 128); |
35e360ed | 180 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); |
a2902821 | 181 | memory_region_set_enabled(&s->io, false); |
edf79e66 | 182 | |
77d58b1e | 183 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 184 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 185 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
edf79e66 HC |
186 | } |
187 | ||
40021f08 AL |
188 | static void via_pm_class_init(ObjectClass *klass, void *data) |
189 | { | |
39bffca2 | 190 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
191 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
192 | ||
9af21dbe | 193 | k->realize = vt82c686b_pm_realize; |
40021f08 AL |
194 | k->config_write = pm_write_config; |
195 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
196 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
197 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
198 | k->revision = 0x40; | |
911629e6 | 199 | dc->reset = vt82c686b_pm_reset; |
39bffca2 AL |
200 | dc->desc = "PM"; |
201 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 202 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
40021f08 AL |
203 | } |
204 | ||
8c43a6f0 | 205 | static const TypeInfo via_pm_info = { |
e6340505 | 206 | .name = TYPE_VT82C686B_PM, |
39bffca2 AL |
207 | .parent = TYPE_PCI_DEVICE, |
208 | .instance_size = sizeof(VT686PMState), | |
209 | .class_init = via_pm_class_init, | |
fd3b02c8 EH |
210 | .interfaces = (InterfaceInfo[]) { |
211 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
212 | { }, | |
213 | }, | |
edf79e66 HC |
214 | }; |
215 | ||
94349bff BZ |
216 | |
217 | typedef struct SuperIOConfig { | |
218 | uint8_t regs[0x100]; | |
219 | uint8_t index; | |
220 | MemoryRegion io; | |
221 | } SuperIOConfig; | |
222 | ||
223 | static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, | |
224 | unsigned size) | |
225 | { | |
226 | SuperIOConfig *sc = opaque; | |
227 | ||
228 | if (addr == 0x3f0) { /* config index register */ | |
229 | sc->index = data & 0xff; | |
230 | } else { | |
231 | bool can_write = true; | |
232 | /* 0x3f1, config data register */ | |
233 | trace_via_superio_write(sc->index, data & 0xff); | |
234 | switch (sc->index) { | |
235 | case 0x00 ... 0xdf: | |
236 | case 0xe4: | |
237 | case 0xe5: | |
238 | case 0xe9 ... 0xed: | |
239 | case 0xf3: | |
240 | case 0xf5: | |
241 | case 0xf7: | |
242 | case 0xf9 ... 0xfb: | |
243 | case 0xfd ... 0xff: | |
244 | can_write = false; | |
245 | break; | |
246 | /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ | |
247 | default: | |
248 | break; | |
249 | ||
250 | } | |
251 | if (can_write) { | |
252 | sc->regs[sc->index] = data & 0xff; | |
253 | } | |
254 | } | |
255 | } | |
256 | ||
257 | static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) | |
258 | { | |
259 | SuperIOConfig *sc = opaque; | |
260 | uint8_t val = sc->regs[sc->index]; | |
261 | ||
262 | trace_via_superio_read(sc->index, val); | |
263 | return val; | |
264 | } | |
265 | ||
266 | static const MemoryRegionOps superio_cfg_ops = { | |
267 | .read = superio_cfg_read, | |
268 | .write = superio_cfg_write, | |
269 | .endianness = DEVICE_NATIVE_ENDIAN, | |
270 | .impl = { | |
271 | .min_access_size = 1, | |
272 | .max_access_size = 1, | |
273 | }, | |
274 | }; | |
275 | ||
276 | ||
277 | OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) | |
278 | ||
279 | struct VT82C686BISAState { | |
280 | PCIDevice dev; | |
281 | SuperIOConfig superio_cfg; | |
282 | }; | |
283 | ||
284 | static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, | |
285 | uint32_t val, int len) | |
286 | { | |
287 | VT82C686BISAState *s = VT82C686B_ISA(d); | |
288 | ||
289 | trace_via_isa_write(addr, val, len); | |
290 | pci_default_write_config(d, addr, val, len); | |
291 | if (addr == 0x85) { | |
292 | /* BIT(1): enable or disable superio config io ports */ | |
293 | memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); | |
294 | } | |
295 | } | |
296 | ||
edf79e66 HC |
297 | static const VMStateDescription vmstate_via = { |
298 | .name = "vt82c686b", | |
299 | .version_id = 1, | |
300 | .minimum_version_id = 1, | |
d49805ae | 301 | .fields = (VMStateField[]) { |
0f798461 | 302 | VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), |
edf79e66 HC |
303 | VMSTATE_END_OF_LIST() |
304 | } | |
305 | }; | |
306 | ||
94349bff BZ |
307 | static void vt82c686b_isa_reset(DeviceState *dev) |
308 | { | |
309 | VT82C686BISAState *s = VT82C686B_ISA(dev); | |
310 | uint8_t *pci_conf = s->dev.config; | |
311 | ||
312 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
313 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
314 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
315 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
316 | ||
317 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
318 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
319 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
320 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
321 | pci_conf[0x59] = 0x04; | |
322 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
323 | pci_conf[0x5f] = 0x04; | |
324 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
325 | ||
326 | s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ | |
327 | s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ | |
328 | s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ | |
329 | s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ | |
330 | s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ | |
331 | s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ | |
332 | } | |
333 | ||
9af21dbe | 334 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
edf79e66 | 335 | { |
007b3103 | 336 | VT82C686BISAState *s = VT82C686B_ISA(d); |
edf79e66 | 337 | uint8_t *pci_conf; |
bcc37e24 | 338 | ISABus *isa_bus; |
edf79e66 HC |
339 | uint8_t *wmask; |
340 | int i; | |
341 | ||
bb2ed009 | 342 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
d10e5432 MA |
343 | pci_address_space_io(d), errp); |
344 | if (!isa_bus) { | |
345 | return; | |
346 | } | |
edf79e66 HC |
347 | |
348 | pci_conf = d->config; | |
edf79e66 | 349 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
350 | |
351 | wmask = d->wmask; | |
352 | for (i = 0x00; i < 0xff; i++) { | |
f3db354c FB |
353 | if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { |
354 | wmask[i] = 0x00; | |
355 | } | |
edf79e66 HC |
356 | } |
357 | ||
6be6e4bc BZ |
358 | memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, |
359 | &s->superio_cfg, "superio_cfg", 2); | |
360 | memory_region_set_enabled(&s->superio_cfg.io, false); | |
f3db354c FB |
361 | /* |
362 | * The floppy also uses 0x3f0 and 0x3f1. | |
363 | * But we do not emulate a floppy, so just set it here. | |
364 | */ | |
bcc37e24 | 365 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
6be6e4bc | 366 | &s->superio_cfg.io); |
edf79e66 HC |
367 | } |
368 | ||
40021f08 AL |
369 | static void via_class_init(ObjectClass *klass, void *data) |
370 | { | |
39bffca2 | 371 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
372 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
373 | ||
9af21dbe | 374 | k->realize = vt82c686b_realize; |
40021f08 AL |
375 | k->config_write = vt82c686b_write_config; |
376 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
377 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
378 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
379 | k->revision = 0x40; | |
9dc1a769 | 380 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 381 | dc->desc = "ISA bridge"; |
39bffca2 | 382 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
383 | /* |
384 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
c3a09ff6 | 385 | * e.g. by mips_fuloong2e_init() |
04916ee9 | 386 | */ |
e90f2a8c | 387 | dc->user_creatable = false; |
40021f08 AL |
388 | } |
389 | ||
8c43a6f0 | 390 | static const TypeInfo via_info = { |
0f798461 | 391 | .name = TYPE_VT82C686B_ISA, |
39bffca2 | 392 | .parent = TYPE_PCI_DEVICE, |
0f798461 | 393 | .instance_size = sizeof(VT82C686BISAState), |
39bffca2 | 394 | .class_init = via_class_init, |
fd3b02c8 EH |
395 | .interfaces = (InterfaceInfo[]) { |
396 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
397 | { }, | |
398 | }, | |
edf79e66 HC |
399 | }; |
400 | ||
94349bff | 401 | |
98cf824b PMD |
402 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
403 | { | |
404 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
405 | ||
406 | sc->serial.count = 2; | |
407 | sc->parallel.count = 1; | |
408 | sc->ide.count = 0; | |
409 | sc->floppy.count = 1; | |
410 | } | |
411 | ||
412 | static const TypeInfo via_superio_info = { | |
413 | .name = TYPE_VT82C686B_SUPERIO, | |
414 | .parent = TYPE_ISA_SUPERIO, | |
415 | .instance_size = sizeof(ISASuperIODevice), | |
416 | .class_size = sizeof(ISASuperIOClass), | |
417 | .class_init = vt82c686b_superio_class_init, | |
418 | }; | |
419 | ||
94349bff | 420 | |
83f7d43a | 421 | static void vt82c686b_register_types(void) |
edf79e66 | 422 | { |
83f7d43a | 423 | type_register_static(&via_pm_info); |
39bffca2 | 424 | type_register_static(&via_info); |
94349bff | 425 | type_register_static(&via_superio_info); |
edf79e66 | 426 | } |
83f7d43a AF |
427 | |
428 | type_init(vt82c686b_register_types) |