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hw/net/imx_fec: Convert debug fprintf() to trace events
[thirdparty/qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
0430891c 25#include "qemu/osdep.h"
4c8f9735 26#include "qemu/units.h"
6ff37c3d 27#include "qemu/error-report.h"
b635d98c 28#include "qapi/error.h"
64552b6b 29#include "hw/irq.h"
a27bd6c7 30#include "hw/qdev-properties.h"
d7dfca08
IM		 31#include "sysemu/dma.h"
32#include "qemu/timer.h"
d7dfca08 33#include "qemu/bitops.h"
f82a0f44 34#include "hw/sd/sdhci.h"
d6454270 35#include "migration/vmstate.h"
637d23be 36#include "sdhci-internal.h"
03dd024f 37#include "qemu/log.h"
0b8fa32f 38#include "qemu/module.h"
8be487d8 39#include "trace.h"
d7dfca08 40
40bbc194
PM		 41#define TYPE_SDHCI_BUS "sdhci-bus"
42#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
43
aa164fbf
PMD		 44#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
45
09b738ff
PMD		 46static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
47{
48 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
49}
50
6ff37c3d
PMD		 51/* return true on error */
52static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
53 uint8_t freq, Error **errp)
54{
4d67852d
PMD		 55 if (s->sd_spec_version >= 3) {
56 return false;
57 }
6ff37c3d
PMD		 58 switch (freq) {
59 case 0:
60 case 10 ... 63:
61 break;
62 default:
63 error_setg(errp, "SD %s clock frequency can have value"
64 "in range 0-63 only", desc);
65 return true;
66 }
67 return false;
68}
69
70static void sdhci_check_capareg(SDHCIState *s, Error **errp)
71{
72 uint64_t msk = s->capareg;
73 uint32_t val;
74 bool y;
75
76 switch (s->sd_spec_version) {
1e23b63f
PMD		 77 case 4:
78 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
79 trace_sdhci_capareg("64-bit system bus (v4)", val);
80 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
81
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
83 trace_sdhci_capareg("UHS-II", val);
84 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
85
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
87 trace_sdhci_capareg("ADMA3", val);
88 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
89
90 /* fallthrough */
4d67852d
PMD		 91 case 3:
92 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
93 trace_sdhci_capareg("async interrupt", val);
94 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
95
96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
97 if (val) {
98 error_setg(errp, "slot-type not supported");
99 return;
100 }
101 trace_sdhci_capareg("slot type", val);
102 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
103
104 if (val != 2) {
105 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
106 trace_sdhci_capareg("8-bit bus", val);
107 }
108 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
109
110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
111 trace_sdhci_capareg("bus speed mask", val);
112 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
113
114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
115 trace_sdhci_capareg("driver strength mask", val);
116 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
117
118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
119 trace_sdhci_capareg("timer re-tuning", val);
120 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
121
122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
123 trace_sdhci_capareg("use SDR50 tuning", val);
124 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
125
126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
127 trace_sdhci_capareg("re-tuning mode", val);
128 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
129
130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
131 trace_sdhci_capareg("clock multiplier", val);
132 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
133
134 /* fallthrough */
6ff37c3d 135 case 2: /* default version */
0540fba9
PMD		 136 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
137 trace_sdhci_capareg("ADMA2", val);
138 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
139
140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
141 trace_sdhci_capareg("ADMA1", val);
142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
143
144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
1e23b63f 145 trace_sdhci_capareg("64-bit system bus (v3)", val);
0540fba9 146 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
6ff37c3d
PMD		 147
148 /* fallthrough */
149 case 1:
150 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
151 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
152
153 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
154 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
155 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
156 return;
157 }
158 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
159
160 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
161 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
162 if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
163 return;
164 }
165 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
166
167 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
168 if (val >= 3) {
169 error_setg(errp, "block size can be 512, 1024 or 2048 only");
170 return;
171 }
172 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
173 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
174
175 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
176 trace_sdhci_capareg("high speed", val);
177 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
178
179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
180 trace_sdhci_capareg("SDMA", val);
181 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
182
183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
184 trace_sdhci_capareg("suspend/resume", val);
185 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
186
187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
188 trace_sdhci_capareg("3.3v", val);
189 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
190
191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
192 trace_sdhci_capareg("3.0v", val);
193 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
194
195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
196 trace_sdhci_capareg("1.8v", val);
197 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
198 break;
199
200 default:
201 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
202 }
203 if (msk) {
204 qemu_log_mask(LOG_UNIMP,
205 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
206 }
207}
208
d7dfca08
IM		 209static uint8_t sdhci_slotint(SDHCIState *s)
210{
211 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
212 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
213 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
214}
215
216static inline void sdhci_update_irq(SDHCIState *s)
217{
218 qemu_set_irq(s->irq, sdhci_slotint(s));
219}
220
221static void sdhci_raise_insertion_irq(void *opaque)
222{
223 SDHCIState *s = (SDHCIState *)opaque;
224
225 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 226 timer_mod(s->insert_timer,
227 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 228 } else {
229 s->prnsts = 0x1ff0000;
230 if (s->norintstsen & SDHC_NISEN_INSERT) {
231 s->norintsts |= SDHC_NIS_INSERT;
232 }
233 sdhci_update_irq(s);
234 }
235}
236
40bbc194 237static void sdhci_set_inserted(DeviceState *dev, bool level)
d7dfca08 238{
40bbc194 239 SDHCIState *s = (SDHCIState *)dev;
d7dfca08 240
8be487d8 241 trace_sdhci_set_inserted(level ? "insert" : "eject");
d7dfca08
IM		 242 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
243 /* Give target some time to notice card ejection */
bc72ad67
AB		 244 timer_mod(s->insert_timer,
245 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 246 } else {
247 if (level) {
248 s->prnsts = 0x1ff0000;
249 if (s->norintstsen & SDHC_NISEN_INSERT) {
250 s->norintsts |= SDHC_NIS_INSERT;
251 }
252 } else {
253 s->prnsts = 0x1fa0000;
254 s->pwrcon &= ~SDHC_POWER_ON;
255 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
256 if (s->norintstsen & SDHC_NISEN_REMOVE) {
257 s->norintsts |= SDHC_NIS_REMOVE;
258 }
259 }
260 sdhci_update_irq(s);
261 }
262}
263
40bbc194 264static void sdhci_set_readonly(DeviceState *dev, bool level)
d7dfca08 265{
40bbc194 266 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 267
268 if (level) {
269 s->prnsts &= ~SDHC_WRITE_PROTECT;
270 } else {
271 /* Write enabled */
272 s->prnsts |= SDHC_WRITE_PROTECT;
273 }
274}
275
276static void sdhci_reset(SDHCIState *s)
277{
40bbc194
PM		 278 DeviceState *dev = DEVICE(s);
279
bc72ad67
AB		 280 timer_del(s->insert_timer);
281 timer_del(s->transfer_timer);
aceb5b06
PMD		 282
283 /* Set all registers to 0. Capabilities/Version registers are not cleared
d7dfca08
IM		 284 * and assumed to always preserve their value, given to them during
285 * initialization */
286 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
287
5c1bc9a2
AB		 288 /* Reset other state based on current card insertion/readonly status */
289 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
290 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
40bbc194 291
d7dfca08
IM		 292 s->data_count = 0;
293 s->stopped_state = sdhc_not_stopped;
0a7ac9f9 294 s->pending_insert_state = false;
d7dfca08
IM		 295}
296
8b41c305
PM		 297static void sdhci_poweron_reset(DeviceState *dev)
298{
299 /* QOM (ie power-on) reset. This is identical to reset
300 * commanded via device register apart from handling of the
301 * 'pending insert on powerup' quirk.
302 */
303 SDHCIState *s = (SDHCIState *)dev;
304
305 sdhci_reset(s);
306
307 if (s->pending_insert_quirk) {
308 s->pending_insert_state = true;
309 }
310}
311
d368ba43 312static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 313
314static void sdhci_send_command(SDHCIState *s)
315{
316 SDRequest request;
317 uint8_t response[16];
318 int rlen;
319
320 s->errintsts = 0;
321 s->acmd12errsts = 0;
322 request.cmd = s->cmdreg >> 8;
323 request.arg = s->argument;
8be487d8
PMD		 324
325 trace_sdhci_send_command(request.cmd, request.arg);
40bbc194 326 rlen = sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 327
328 if (s->cmdreg & SDHC_CMD_RESPONSE) {
329 if (rlen == 4) {
b3141c06 330 s->rspreg[0] = ldl_be_p(response);
d7dfca08 331 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
8be487d8 332 trace_sdhci_response4(s->rspreg[0]);
d7dfca08 333 } else if (rlen == 16) {
b3141c06
PMD		 334 s->rspreg[0] = ldl_be_p(&response[11]);
335 s->rspreg[1] = ldl_be_p(&response[7]);
336 s->rspreg[2] = ldl_be_p(&response[3]);
d7dfca08
IM		 337 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
338 response[2];
8be487d8
PMD		 339 trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
340 s->rspreg[1], s->rspreg[0]);
d7dfca08 341 } else {
8be487d8 342 trace_sdhci_error("timeout waiting for command response");
d7dfca08
IM		 343 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
344 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
345 s->norintsts |= SDHC_NIS_ERR;
346 }
347 }
348
fd1e5c81
AS		 349 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
350 (s->norintstsen & SDHC_NISEN_TRSCMP) &&
d7dfca08
IM		 351 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
352 s->norintsts |= SDHC_NIS_TRSCMP;
353 }
d7dfca08
IM		 354 }
355
356 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
357 s->norintsts |= SDHC_NIS_CMDCMP;
358 }
359
360 sdhci_update_irq(s);
361
362 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 363 s->data_count = 0;
d368ba43 364 sdhci_data_transfer(s);
d7dfca08
IM		 365 }
366}
367
368static void sdhci_end_transfer(SDHCIState *s)
369{
370 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
371 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
372 SDRequest request;
373 uint8_t response[16];
374
375 request.cmd = 0x0C;
376 request.arg = 0;
8be487d8 377 trace_sdhci_end_transfer(request.cmd, request.arg);
40bbc194 378 sdbus_do_command(&s->sdbus, &request, response);
d7dfca08 379 /* Auto CMD12 response goes to the upper Response register */
b3141c06 380 s->rspreg[3] = ldl_be_p(response);
d7dfca08
IM		 381 }
382
383 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
384 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
385 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
386
387 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
388 s->norintsts |= SDHC_NIS_TRSCMP;
389 }
390
391 sdhci_update_irq(s);
392}
393
394/*
395 * Programmed i/o data transfer
396 */
d23b6caa 397#define BLOCK_SIZE_MASK (4 * KiB - 1)
d7dfca08
IM		 398
399/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
400static void sdhci_read_block_from_card(SDHCIState *s)
401{
402 int index = 0;
ea55a221
PMD		 403 uint8_t data;
404 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 405
406 if ((s->trnmod & SDHC_TRNS_MULTI) &&
407 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
408 return;
409 }
410
ea55a221
PMD		 411 for (index = 0; index < blk_size; index++) {
412 data = sdbus_read_data(&s->sdbus);
413 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
08022a91 414 /* Device is not in tuning */
ea55a221
PMD		 415 s->fifo_buffer[index] = data;
416 }
417 }
418
419 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
08022a91 420 /* Device is in tuning */
ea55a221
PMD		 421 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
422 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
423 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
424 SDHC_DATA_INHIBIT);
425 goto read_done;
d7dfca08
IM		 426 }
427
428 /* New data now available for READ through Buffer Port Register */
429 s->prnsts |= SDHC_DATA_AVAILABLE;
430 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
431 s->norintsts |= SDHC_NIS_RBUFRDY;
432 }
433
434 /* Clear DAT line active status if that was the last block */
435 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
436 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
437 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
438 }
439
440 /* If stop at block gap request was set and it's not the last block of
441 * data - generate Block Event interrupt */
442 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
443 s->blkcnt != 1) {
444 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
445 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
446 s->norintsts |= SDHC_EIS_BLKGAP;
447 }
448 }
449
ea55a221 450read_done:
d7dfca08
IM		 451 sdhci_update_irq(s);
452}
453
454/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
455static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
456{
457 uint32_t value = 0;
458 int i;
459
460 /* first check that a valid data exists in host controller input buffer */
461 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
8be487d8 462 trace_sdhci_error("read from empty buffer");
d7dfca08
IM		 463 return 0;
464 }
465
466 for (i = 0; i < size; i++) {
467 value |= s->fifo_buffer[s->data_count] << i * 8;
468 s->data_count++;
469 /* check if we've read all valid data (blksize bytes) from buffer */
bf8ec38e 470 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 471 trace_sdhci_read_dataport(s->data_count);
d7dfca08
IM		 472 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
473 s->data_count = 0; /* next buff read must start at position [0] */
474
475 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
476 s->blkcnt--;
477 }
478
479 /* if that was the last block of data */
480 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
481 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
482 /* stop at gap request */
483 (s->stopped_state == sdhc_gap_read &&
484 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 485 sdhci_end_transfer(s);
d7dfca08 486 } else { /* if there are more data, read next block from card */
d368ba43 487 sdhci_read_block_from_card(s);
d7dfca08
IM		 488 }
489 break;
490 }
491 }
492
493 return value;
494}
495
496/* Write data from host controller FIFO to card */
497static void sdhci_write_block_to_card(SDHCIState *s)
498{
499 int index = 0;
500
501 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
502 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
503 s->norintsts |= SDHC_NIS_WBUFRDY;
504 }
505 sdhci_update_irq(s);
506 return;
507 }
508
509 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
510 if (s->blkcnt == 0) {
511 return;
512 } else {
513 s->blkcnt--;
514 }
515 }
516
bf8ec38e 517 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
40bbc194 518 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
d7dfca08
IM		 519 }
520
521 /* Next data can be written through BUFFER DATORT register */
522 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 523
524 /* Finish transfer if that was the last block of data */
525 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
526 ((s->trnmod & SDHC_TRNS_MULTI) &&
527 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 528 sdhci_end_transfer(s);
dcdb4cd8
PC		 529 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
530 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 531 }
532
533 /* Generate Block Gap Event if requested and if not the last block */
534 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
535 s->blkcnt > 0) {
536 s->prnsts &= ~SDHC_DOING_WRITE;
537 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
538 s->norintsts |= SDHC_EIS_BLKGAP;
539 }
d368ba43 540 sdhci_end_transfer(s);
d7dfca08
IM		 541 }
542
543 sdhci_update_irq(s);
544}
545
546/* Write @size bytes of @value data to host controller @s Buffer Data Port
547 * register */
548static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
549{
550 unsigned i;
551
552 /* Check that there is free space left in a buffer */
553 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
8be487d8 554 trace_sdhci_error("Can't write to data buffer: buffer full");
d7dfca08
IM		 555 return;
556 }
557
558 for (i = 0; i < size; i++) {
559 s->fifo_buffer[s->data_count] = value & 0xFF;
560 s->data_count++;
561 value >>= 8;
bf8ec38e 562 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
8be487d8 563 trace_sdhci_write_dataport(s->data_count);
d7dfca08
IM		 564 s->data_count = 0;
565 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
566 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 567 sdhci_write_block_to_card(s);
d7dfca08
IM		 568 }
569 }
570 }
571}
572
573/*
574 * Single DMA data transfer
575 */
576
577/* Multi block SDMA transfer */
578static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
579{
580 bool page_aligned = false;
581 unsigned int n, begin;
bf8ec38e
PMD		 582 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
583 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
d7dfca08
IM		 584 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
585
6e86d903
PP		 586 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
587 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
588 return;
589 }
590
d7dfca08
IM		 591 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
592 * possible stop at page boundary if initial address is not page aligned,
593 * allow them to work properly */
594 if ((s->sdmasysad % boundary_chk) == 0) {
595 page_aligned = true;
596 }
597
598 if (s->trnmod & SDHC_TRNS_READ) {
599 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
600 SDHC_DAT_LINE_ACTIVE;
601 while (s->blkcnt) {
602 if (s->data_count == 0) {
603 for (n = 0; n < block_size; n++) {
40bbc194 604 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 605 }
606 }
607 begin = s->data_count;
608 if (((boundary_count + begin) < block_size) && page_aligned) {
609 s->data_count = boundary_count + begin;
610 boundary_count = 0;
611 } else {
612 s->data_count = block_size;
613 boundary_count -= block_size - begin;
614 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
615 s->blkcnt--;
616 }
617 }
dd55c485 618 dma_memory_write(s->dma_as, s->sdmasysad,
d7dfca08
IM		 619 &s->fifo_buffer[begin], s->data_count - begin);
620 s->sdmasysad += s->data_count - begin;
621 if (s->data_count == block_size) {
622 s->data_count = 0;
623 }
624 if (page_aligned && boundary_count == 0) {
625 break;
626 }
627 }
628 } else {
629 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
630 SDHC_DAT_LINE_ACTIVE;
631 while (s->blkcnt) {
632 begin = s->data_count;
633 if (((boundary_count + begin) < block_size) && page_aligned) {
634 s->data_count = boundary_count + begin;
635 boundary_count = 0;
636 } else {
637 s->data_count = block_size;
638 boundary_count -= block_size - begin;
639 }
dd55c485 640 dma_memory_read(s->dma_as, s->sdmasysad,
42922105 641 &s->fifo_buffer[begin], s->data_count - begin);
d7dfca08
IM		 642 s->sdmasysad += s->data_count - begin;
643 if (s->data_count == block_size) {
644 for (n = 0; n < block_size; n++) {
40bbc194 645 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 646 }
647 s->data_count = 0;
648 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
649 s->blkcnt--;
650 }
651 }
652 if (page_aligned && boundary_count == 0) {
653 break;
654 }
655 }
656 }
657
658 if (s->blkcnt == 0) {
d368ba43 659 sdhci_end_transfer(s);
d7dfca08
IM		 660 } else {
661 if (s->norintstsen & SDHC_NISEN_DMA) {
662 s->norintsts |= SDHC_NIS_DMA;
663 }
664 sdhci_update_irq(s);
665 }
666}
667
668/* single block SDMA transfer */
d7dfca08
IM		 669static void sdhci_sdma_transfer_single_block(SDHCIState *s)
670{
671 int n;
bf8ec38e 672 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
d7dfca08
IM		 673
674 if (s->trnmod & SDHC_TRNS_READ) {
675 for (n = 0; n < datacnt; n++) {
40bbc194 676 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08 677 }
dd55c485 678 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
d7dfca08 679 } else {
dd55c485 680 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
d7dfca08 681 for (n = 0; n < datacnt; n++) {
40bbc194 682 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 683 }
684 }
241999bf 685 s->blkcnt--;
d7dfca08 686
d368ba43 687 sdhci_end_transfer(s);
d7dfca08
IM		 688}
689
690typedef struct ADMADescr {
691 hwaddr addr;
692 uint16_t length;
693 uint8_t attr;
694 uint8_t incr;
695} ADMADescr;
696
697static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
698{
699 uint32_t adma1 = 0;
700 uint64_t adma2 = 0;
701 hwaddr entry_addr = (hwaddr)s->admasysaddr;
06c5120b 702 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 703 case SDHC_CTRL_ADMA2_32:
18610bfd 704 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2));
d7dfca08
IM		 705 adma2 = le64_to_cpu(adma2);
706 /* The spec does not specify endianness of descriptor table.
707 * We currently assume that it is LE.
708 */
709 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
710 dscr->length = (uint16_t)extract64(adma2, 16, 16);
711 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
712 dscr->incr = 8;
713 break;
714 case SDHC_CTRL_ADMA1_32:
18610bfd 715 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1));
d7dfca08
IM		 716 adma1 = le32_to_cpu(adma1);
717 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
718 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
719 dscr->incr = 4;
720 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
721 dscr->length = (uint16_t)extract32(adma1, 12, 16);
722 } else {
4c8f9735 723 dscr->length = 4 * KiB;
d7dfca08
IM		 724 }
725 break;
726 case SDHC_CTRL_ADMA2_64:
18610bfd
PMD		 727 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1);
728 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2);
d7dfca08 729 dscr->length = le16_to_cpu(dscr->length);
18610bfd 730 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8);
04654b5a
SPB		 731 dscr->addr = le64_to_cpu(dscr->addr);
732 dscr->attr &= (uint8_t) ~0xC0;
d7dfca08
IM		 733 dscr->incr = 12;
734 break;
735 }
736}
737
738/* Advanced DMA data transfer */
739
740static void sdhci_do_adma(SDHCIState *s)
741{
742 unsigned int n, begin, length;
bf8ec38e 743 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
8be487d8 744 ADMADescr dscr = {};
d7dfca08
IM		 745 int i;
746
747 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
748 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
749
750 get_adma_description(s, &dscr);
8be487d8 751 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
d7dfca08
IM		 752
753 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
754 /* Indicate that error occurred in ST_FDS state */
755 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
756 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
757
758 /* Generate ADMA error interrupt */
759 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
760 s->errintsts |= SDHC_EIS_ADMAERR;
761 s->norintsts |= SDHC_NIS_ERR;
762 }
763
764 sdhci_update_irq(s);
765 return;
766 }
767
4c8f9735 768 length = dscr.length ? dscr.length : 64 * KiB;
d7dfca08
IM		 769
770 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
771 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
772
773 if (s->trnmod & SDHC_TRNS_READ) {
774 while (length) {
775 if (s->data_count == 0) {
776 for (n = 0; n < block_size; n++) {
40bbc194 777 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 778 }
779 }
780 begin = s->data_count;
781 if ((length + begin) < block_size) {
782 s->data_count = length + begin;
783 length = 0;
784 } else {
785 s->data_count = block_size;
786 length -= block_size - begin;
787 }
dd55c485 788 dma_memory_write(s->dma_as, dscr.addr,
d7dfca08
IM		 789 &s->fifo_buffer[begin],
790 s->data_count - begin);
791 dscr.addr += s->data_count - begin;
792 if (s->data_count == block_size) {
793 s->data_count = 0;
794 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
795 s->blkcnt--;
796 if (s->blkcnt == 0) {
797 break;
798 }
799 }
800 }
801 }
802 } else {
803 while (length) {
804 begin = s->data_count;
805 if ((length + begin) < block_size) {
806 s->data_count = length + begin;
807 length = 0;
808 } else {
809 s->data_count = block_size;
810 length -= block_size - begin;
811 }
dd55c485 812 dma_memory_read(s->dma_as, dscr.addr,
9db11cef
PC		 813 &s->fifo_buffer[begin],
814 s->data_count - begin);
d7dfca08
IM		 815 dscr.addr += s->data_count - begin;
816 if (s->data_count == block_size) {
817 for (n = 0; n < block_size; n++) {
40bbc194 818 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 819 }
820 s->data_count = 0;
821 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
822 s->blkcnt--;
823 if (s->blkcnt == 0) {
824 break;
825 }
826 }
827 }
828 }
829 }
830 s->admasysaddr += dscr.incr;
831 break;
832 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
833 s->admasysaddr = dscr.addr;
8be487d8 834 trace_sdhci_adma("link", s->admasysaddr);
d7dfca08
IM		 835 break;
836 default:
837 s->admasysaddr += dscr.incr;
838 break;
839 }
840
1d32c26f 841 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
8be487d8 842 trace_sdhci_adma("interrupt", s->admasysaddr);
1d32c26f
PC		 843 if (s->norintstsen & SDHC_NISEN_DMA) {
844 s->norintsts |= SDHC_NIS_DMA;
845 }
846
847 sdhci_update_irq(s);
848 }
849
d7dfca08
IM		 850 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
851 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
852 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
8be487d8 853 trace_sdhci_adma_transfer_completed();
d7dfca08
IM		 854 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
855 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
856 s->blkcnt != 0)) {
8be487d8 857 trace_sdhci_error("SD/MMC host ADMA length mismatch");
d7dfca08
IM		 858 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
859 SDHC_ADMAERR_STATE_ST_TFR;
860 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
8be487d8 861 trace_sdhci_error("Set ADMA error flag");
d7dfca08
IM		 862 s->errintsts |= SDHC_EIS_ADMAERR;
863 s->norintsts |= SDHC_NIS_ERR;
864 }
865
866 sdhci_update_irq(s);
867 }
d368ba43 868 sdhci_end_transfer(s);
d7dfca08
IM		 869 return;
870 }
871
d7dfca08
IM		 872 }
873
085d8134 874 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 875 timer_mod(s->transfer_timer,
876 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 877}
878
879/* Perform data transfer according to controller configuration */
880
d368ba43 881static void sdhci_data_transfer(void *opaque)
d7dfca08 882{
d368ba43 883 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 884
885 if (s->trnmod & SDHC_TRNS_DMA) {
06c5120b 886 switch (SDHC_DMA_TYPE(s->hostctl1)) {
d7dfca08 887 case SDHC_CTRL_SDMA:
d7dfca08 888 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 889 sdhci_sdma_transfer_single_block(s);
d7dfca08 890 } else {
d368ba43 891 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 892 }
893
894 break;
895 case SDHC_CTRL_ADMA1_32:
0540fba9 896 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
8be487d8 897 trace_sdhci_error("ADMA1 not supported");
d7dfca08
IM		 898 break;
899 }
900
d368ba43 901 sdhci_do_adma(s);
d7dfca08
IM		 902 break;
903 case SDHC_CTRL_ADMA2_32:
0540fba9 904 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
8be487d8 905 trace_sdhci_error("ADMA2 not supported");
d7dfca08
IM		 906 break;
907 }
908
d368ba43 909 sdhci_do_adma(s);
d7dfca08
IM		 910 break;
911 case SDHC_CTRL_ADMA2_64:
0540fba9
PMD		 912 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
913 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
8be487d8 914 trace_sdhci_error("64 bit ADMA not supported");
d7dfca08
IM		 915 break;
916 }
917
d368ba43 918 sdhci_do_adma(s);
d7dfca08
IM		 919 break;
920 default:
8be487d8 921 trace_sdhci_error("Unsupported DMA type");
d7dfca08
IM		 922 break;
923 }
924 } else {
40bbc194 925 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
d7dfca08
IM		 926 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
927 SDHC_DAT_LINE_ACTIVE;
d368ba43 928 sdhci_read_block_from_card(s);
d7dfca08
IM		 929 } else {
930 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
931 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 932 sdhci_write_block_to_card(s);
d7dfca08
IM		 933 }
934 }
935}
936
937static bool sdhci_can_issue_command(SDHCIState *s)
938{
6890a695 939 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
d7dfca08
IM		 940 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
941 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
942 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
943 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
944 return false;
945 }
946
947 return true;
948}
949
950/* The Buffer Data Port register must be accessed in sequential and
951 * continuous manner */
952static inline bool
953sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
954{
955 if ((s->data_count & 0x3) != byte_num) {
8be487d8
PMD		 956 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
957 "is prohibited\n");
d7dfca08
IM		 958 return false;
959 }
960 return true;
961}
962
d368ba43 963static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 964{
d368ba43 965 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 966 uint32_t ret = 0;
967
968 switch (offset & ~0x3) {
969 case SDHC_SYSAD:
970 ret = s->sdmasysad;
971 break;
972 case SDHC_BLKSIZE:
973 ret = s->blksize | (s->blkcnt << 16);
974 break;
975 case SDHC_ARGUMENT:
976 ret = s->argument;
977 break;
978 case SDHC_TRNMOD:
979 ret = s->trnmod | (s->cmdreg << 16);
980 break;
981 case SDHC_RSPREG0 ... SDHC_RSPREG3:
982 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
983 break;
984 case SDHC_BDATA:
985 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 986 ret = sdhci_read_dataport(s, size);
8be487d8 987 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 988 return ret;
989 }
990 break;
991 case SDHC_PRNSTS:
992 ret = s->prnsts;
da346922
PMD		 993 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
994 sdbus_get_dat_lines(&s->sdbus));
995 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
996 sdbus_get_cmd_line(&s->sdbus));
d7dfca08
IM		 997 break;
998 case SDHC_HOSTCTL:
06c5120b 999 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
d7dfca08
IM		 1000 (s->wakcon << 24);
1001 break;
1002 case SDHC_CLKCON:
1003 ret = s->clkcon | (s->timeoutcon << 16);
1004 break;
1005 case SDHC_NORINTSTS:
1006 ret = s->norintsts | (s->errintsts << 16);
1007 break;
1008 case SDHC_NORINTSTSEN:
1009 ret = s->norintstsen | (s->errintstsen << 16);
1010 break;
1011 case SDHC_NORINTSIGEN:
1012 ret = s->norintsigen | (s->errintsigen << 16);
1013 break;
1014 case SDHC_ACMD12ERRSTS:
ea55a221 1015 ret = s->acmd12errsts | (s->hostctl2 << 16);
d7dfca08 1016 break;
cd209421 1017 case SDHC_CAPAB:
5efc9016
PMD		 1018 ret = (uint32_t)s->capareg;
1019 break;
1020 case SDHC_CAPAB + 4:
1021 ret = (uint32_t)(s->capareg >> 32);
d7dfca08
IM		 1022 break;
1023 case SDHC_MAXCURR:
5efc9016
PMD		 1024 ret = (uint32_t)s->maxcurr;
1025 break;
1026 case SDHC_MAXCURR + 4:
1027 ret = (uint32_t)(s->maxcurr >> 32);
d7dfca08
IM		 1028 break;
1029 case SDHC_ADMAERR:
1030 ret = s->admaerr;
1031 break;
1032 case SDHC_ADMASYSADDR:
1033 ret = (uint32_t)s->admasysaddr;
1034 break;
1035 case SDHC_ADMASYSADDR + 4:
1036 ret = (uint32_t)(s->admasysaddr >> 32);
1037 break;
1038 case SDHC_SLOT_INT_STATUS:
aceb5b06 1039 ret = (s->version << 16) | sdhci_slotint(s);
d7dfca08
IM		 1040 break;
1041 default:
00b004b3
PMD		 1042 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1043 "not implemented\n", size, offset);
d7dfca08
IM		 1044 break;
1045 }
1046
1047 ret >>= (offset & 0x3) * 8;
1048 ret &= (1ULL << (size * 8)) - 1;
8be487d8 1049 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
d7dfca08
IM		 1050 return ret;
1051}
1052
1053static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1054{
1055 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1056 return;
1057 }
1058 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1059
1060 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1061 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1062 if (s->stopped_state == sdhc_gap_read) {
1063 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 1064 sdhci_read_block_from_card(s);
d7dfca08
IM		 1065 } else {
1066 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 1067 sdhci_write_block_to_card(s);
d7dfca08
IM		 1068 }
1069 s->stopped_state = sdhc_not_stopped;
1070 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1071 if (s->prnsts & SDHC_DOING_READ) {
1072 s->stopped_state = sdhc_gap_read;
1073 } else if (s->prnsts & SDHC_DOING_WRITE) {
1074 s->stopped_state = sdhc_gap_write;
1075 }
1076 }
1077}
1078
1079static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1080{
1081 switch (value) {
1082 case SDHC_RESET_ALL:
d368ba43 1083 sdhci_reset(s);
d7dfca08
IM		 1084 break;
1085 case SDHC_RESET_CMD:
1086 s->prnsts &= ~SDHC_CMD_INHIBIT;
1087 s->norintsts &= ~SDHC_NIS_CMDCMP;
1088 break;
1089 case SDHC_RESET_DATA:
1090 s->data_count = 0;
1091 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
1092 SDHC_DOING_READ | SDHC_DOING_WRITE |
1093 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
1094 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
1095 s->stopped_state = sdhc_not_stopped;
1096 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
1097 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
1098 break;
1099 }
1100}
1101
1102static void
d368ba43 1103sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 1104{
d368ba43 1105 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 1106 unsigned shift = 8 * (offset & 0x3);
1107 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 1108 uint32_t value = val;
d7dfca08
IM		 1109 value <<= shift;
1110
1111 switch (offset & ~0x3) {
1112 case SDHC_SYSAD:
1113 s->sdmasysad = (s->sdmasysad & mask) | value;
1114 MASKED_WRITE(s->sdmasysad, mask, value);
1115 /* Writing to last byte of sdmasysad might trigger transfer */
1116 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
06c5120b 1117 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
45ba9f76
PP		 1118 if (s->trnmod & SDHC_TRNS_MULTI) {
1119 sdhci_sdma_transfer_multi_blocks(s);
1120 } else {
1121 sdhci_sdma_transfer_single_block(s);
1122 }
d7dfca08
IM		 1123 }
1124 break;
1125 case SDHC_BLKSIZE:
1126 if (!TRANSFERRING_DATA(s->prnsts)) {
1127 MASKED_WRITE(s->blksize, mask, value);
1128 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1129 }
9201bb9a
AF		 1130
1131 /* Limit block size to the maximum buffer size */
1132 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
78ee6bd0 1133 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than "
9201bb9a
AF		 1134 "the maximum buffer 0x%x", __func__, s->blksize,
1135 s->buf_maxsz);
1136
1137 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1138 }
1139
d7dfca08
IM		 1140 break;
1141 case SDHC_ARGUMENT:
1142 MASKED_WRITE(s->argument, mask, value);
1143 break;
1144 case SDHC_TRNMOD:
1145 /* DMA can be enabled only if it is supported as indicated by
1146 * capabilities register */
6ff37c3d 1147 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
d7dfca08
IM		 1148 value &= ~SDHC_TRNS_DMA;
1149 }
24bddf9d 1150 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
d7dfca08
IM		 1151 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1152
1153 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1154 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1155 break;
1156 }
1157
d368ba43 1158 sdhci_send_command(s);
d7dfca08
IM		 1159 break;
1160 case SDHC_BDATA:
1161 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1162 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1163 }
1164 break;
1165 case SDHC_HOSTCTL:
1166 if (!(mask & 0xFF0000)) {
1167 sdhci_blkgap_write(s, value >> 16);
1168 }
06c5120b 1169 MASKED_WRITE(s->hostctl1, mask, value);
d7dfca08
IM		 1170 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1171 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1172 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1173 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1174 s->pwrcon &= ~SDHC_POWER_ON;
1175 }
1176 break;
1177 case SDHC_CLKCON:
1178 if (!(mask & 0xFF000000)) {
1179 sdhci_reset_write(s, value >> 24);
1180 }
1181 MASKED_WRITE(s->clkcon, mask, value);
1182 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1183 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1184 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1185 } else {
1186 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1187 }
1188 break;
1189 case SDHC_NORINTSTS:
1190 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1191 value &= ~SDHC_NIS_CARDINT;
1192 }
1193 s->norintsts &= mask | ~value;
1194 s->errintsts &= (mask >> 16) | ~(value >> 16);
1195 if (s->errintsts) {
1196 s->norintsts |= SDHC_NIS_ERR;
1197 } else {
1198 s->norintsts &= ~SDHC_NIS_ERR;
1199 }
1200 sdhci_update_irq(s);
1201 break;
1202 case SDHC_NORINTSTSEN:
1203 MASKED_WRITE(s->norintstsen, mask, value);
1204 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1205 s->norintsts &= s->norintstsen;
1206 s->errintsts &= s->errintstsen;
1207 if (s->errintsts) {
1208 s->norintsts |= SDHC_NIS_ERR;
1209 } else {
1210 s->norintsts &= ~SDHC_NIS_ERR;
1211 }
0a7ac9f9
AB		 1212 /* Quirk for Raspberry Pi: pending card insert interrupt
1213 * appears when first enabled after power on */
1214 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1215 assert(s->pending_insert_quirk);
1216 s->norintsts |= SDHC_NIS_INSERT;
1217 s->pending_insert_state = false;
1218 }
d7dfca08
IM		 1219 sdhci_update_irq(s);
1220 break;
1221 case SDHC_NORINTSIGEN:
1222 MASKED_WRITE(s->norintsigen, mask, value);
1223 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1224 sdhci_update_irq(s);
1225 break;
1226 case SDHC_ADMAERR:
1227 MASKED_WRITE(s->admaerr, mask, value);
1228 break;
1229 case SDHC_ADMASYSADDR:
1230 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1231 (uint64_t)mask)) | (uint64_t)value;
1232 break;
1233 case SDHC_ADMASYSADDR + 4:
1234 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1235 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1236 break;
1237 case SDHC_FEAER:
1238 s->acmd12errsts |= value;
1239 s->errintsts |= (value >> 16) & s->errintstsen;
1240 if (s->acmd12errsts) {
1241 s->errintsts |= SDHC_EIS_CMD12ERR;
1242 }
1243 if (s->errintsts) {
1244 s->norintsts |= SDHC_NIS_ERR;
1245 }
1246 sdhci_update_irq(s);
1247 break;
5d2c0464 1248 case SDHC_ACMD12ERRSTS:
0034ebe6
PMD		 1249 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1250 if (s->uhs_mode >= UHS_I) {
1251 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1252
1253 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1254 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1255 } else {
1256 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1257 }
1258 }
5d2c0464 1259 break;
5efc9016
PMD		 1260
1261 case SDHC_CAPAB:
1262 case SDHC_CAPAB + 4:
1263 case SDHC_MAXCURR:
1264 case SDHC_MAXCURR + 4:
1265 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1266 " <- 0x%08x read-only\n", size, offset, value >> shift);
1267 break;
1268
d7dfca08 1269 default:
00b004b3
PMD		 1270 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1271 "not implemented\n", size, offset, value >> shift);
d7dfca08
IM		 1272 break;
1273 }
8be487d8
PMD		 1274 trace_sdhci_access("wr", size << 3, offset, "<-",
1275 value >> shift, value >> shift);
d7dfca08
IM		 1276}
1277
1278static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1279 .read = sdhci_read,
1280 .write = sdhci_write,
d7dfca08
IM		 1281 .valid = {
1282 .min_access_size = 1,
1283 .max_access_size = 4,
1284 .unaligned = false
1285 },
1286 .endianness = DEVICE_LITTLE_ENDIAN,
1287};
1288
aceb5b06
PMD		 1289static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
1290{
6ff37c3d
PMD		 1291 Error *local_err = NULL;
1292
4d67852d
PMD		 1293 switch (s->sd_spec_version) {
1294 case 2 ... 3:
1295 break;
1296 default:
1297 error_setg(errp, "Only Spec v2/v3 are supported");
aceb5b06
PMD		 1298 return;
1299 }
1300 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
6ff37c3d
PMD		 1301
1302 sdhci_check_capareg(s, &local_err);
1303 if (local_err) {
1304 error_propagate(errp, local_err);
1305 return;
1306 }
aceb5b06
PMD		 1307}
1308
b635d98c
PMD		 1309/* --- qdev common --- */
1310
ce864603 1311void sdhci_initfn(SDHCIState *s)
d7dfca08 1312{
40bbc194
PM		 1313 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1314 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
d7dfca08 1315
bc72ad67 1316 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1317 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
fd1e5c81
AS		 1318
1319 s->io_ops = &sdhci_mmio_ops;
d7dfca08
IM		 1320}
1321
ce864603 1322void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1323{
bc72ad67
AB		 1324 timer_del(s->insert_timer);
1325 timer_free(s->insert_timer);
1326 timer_del(s->transfer_timer);
1327 timer_free(s->transfer_timer);
d7dfca08 1328
012aef07
MA		 1329 g_free(s->fifo_buffer);
1330 s->fifo_buffer = NULL;
d7dfca08
IM		 1331}
1332
ce864603 1333void sdhci_common_realize(SDHCIState *s, Error **errp)
25367498 1334{
aceb5b06
PMD		 1335 Error *local_err = NULL;
1336
1337 sdhci_init_readonly_registers(s, &local_err);
1338 if (local_err) {
1339 error_propagate(errp, local_err);
1340 return;
1341 }
25367498
PMD		 1342 s->buf_maxsz = sdhci_get_fifolen(s);
1343 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1344
c0983085 1345 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
25367498
PMD		 1346 SDHC_REGISTERS_MAP_SIZE);
1347}
1348
b69c3c21 1349void sdhci_common_unrealize(SDHCIState *s)
8b7455c7
PMD		 1350{
1351 /* This function is expected to be called only once for each class:
1352 * - SysBus: via DeviceClass->unrealize(),
1353 * - PCI: via PCIDeviceClass->exit().
1354 * However to avoid double-free and/or use-after-free we still nullify
1355 * this variable (better safe than sorry!). */
1356 g_free(s->fifo_buffer);
1357 s->fifo_buffer = NULL;
1358}
1359
0a7ac9f9
AB		 1360static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1361{
1362 SDHCIState *s = opaque;
1363
1364 return s->pending_insert_state;
1365}
1366
1367static const VMStateDescription sdhci_pending_insert_vmstate = {
1368 .name = "sdhci/pending-insert",
1369 .version_id = 1,
1370 .minimum_version_id = 1,
1371 .needed = sdhci_pending_insert_vmstate_needed,
1372 .fields = (VMStateField[]) {
1373 VMSTATE_BOOL(pending_insert_state, SDHCIState),
1374 VMSTATE_END_OF_LIST()
1375 },
1376};
1377
d7dfca08
IM		 1378const VMStateDescription sdhci_vmstate = {
1379 .name = "sdhci",
1380 .version_id = 1,
1381 .minimum_version_id = 1,
35d08458 1382 .fields = (VMStateField[]) {
d7dfca08
IM		 1383 VMSTATE_UINT32(sdmasysad, SDHCIState),
1384 VMSTATE_UINT16(blksize, SDHCIState),
1385 VMSTATE_UINT16(blkcnt, SDHCIState),
1386 VMSTATE_UINT32(argument, SDHCIState),
1387 VMSTATE_UINT16(trnmod, SDHCIState),
1388 VMSTATE_UINT16(cmdreg, SDHCIState),
1389 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1390 VMSTATE_UINT32(prnsts, SDHCIState),
06c5120b 1391 VMSTATE_UINT8(hostctl1, SDHCIState),
d7dfca08
IM		 1392 VMSTATE_UINT8(pwrcon, SDHCIState),
1393 VMSTATE_UINT8(blkgap, SDHCIState),
1394 VMSTATE_UINT8(wakcon, SDHCIState),
1395 VMSTATE_UINT16(clkcon, SDHCIState),
1396 VMSTATE_UINT8(timeoutcon, SDHCIState),
1397 VMSTATE_UINT8(admaerr, SDHCIState),
1398 VMSTATE_UINT16(norintsts, SDHCIState),
1399 VMSTATE_UINT16(errintsts, SDHCIState),
1400 VMSTATE_UINT16(norintstsen, SDHCIState),
1401 VMSTATE_UINT16(errintstsen, SDHCIState),
1402 VMSTATE_UINT16(norintsigen, SDHCIState),
1403 VMSTATE_UINT16(errintsigen, SDHCIState),
1404 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1405 VMSTATE_UINT16(data_count, SDHCIState),
1406 VMSTATE_UINT64(admasysaddr, SDHCIState),
1407 VMSTATE_UINT8(stopped_state, SDHCIState),
59046ec2 1408 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
e720677e
PB		 1409 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1410 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08 1411 VMSTATE_END_OF_LIST()
0a7ac9f9
AB		 1412 },
1413 .subsections = (const VMStateDescription*[]) {
1414 &sdhci_pending_insert_vmstate,
1415 NULL
1416 },
d7dfca08
IM		 1417};
1418
ce864603 1419void sdhci_common_class_init(ObjectClass *klass, void *data)
1c92c505
PMD		 1420{
1421 DeviceClass *dc = DEVICE_CLASS(klass);
1422
1423 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1424 dc->vmsd = &sdhci_vmstate;
1425 dc->reset = sdhci_poweron_reset;
1426}
1427
b635d98c
PMD		 1428/* --- qdev SysBus --- */
1429
5ec911c3 1430static Property sdhci_sysbus_properties[] = {
b635d98c 1431 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
0a7ac9f9
AB		 1432 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1433 false),
60765b6c
PMD		 1434 DEFINE_PROP_LINK("dma", SDHCIState,
1435 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
5ec911c3
KC		 1436 DEFINE_PROP_END_OF_LIST(),
1437};
1438
7302dcd6
KC		 1439static void sdhci_sysbus_init(Object *obj)
1440{
1441 SDHCIState *s = SYSBUS_SDHCI(obj);
5ec911c3 1442
40bbc194 1443 sdhci_initfn(s);
7302dcd6
KC		 1444}
1445
1446static void sdhci_sysbus_finalize(Object *obj)
1447{
1448 SDHCIState *s = SYSBUS_SDHCI(obj);
60765b6c
PMD		 1449
1450 if (s->dma_mr) {
1451 object_unparent(OBJECT(s->dma_mr));
1452 }
1453
7302dcd6
KC		 1454 sdhci_uninitfn(s);
1455}
1456
1019388c 1457static void sdhci_sysbus_realize(DeviceState *dev, Error **errp)
d7dfca08 1458{
7302dcd6 1459 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08 1460 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ab958e38 1461 Error *local_err = NULL;
d7dfca08 1462
544156ef 1463 sdhci_common_realize(s, &local_err);
ab958e38
PMD		 1464 if (local_err) {
1465 error_propagate(errp, local_err);
25367498
PMD		 1466 return;
1467 }
1468
60765b6c 1469 if (s->dma_mr) {
02e57e1c 1470 s->dma_as = &s->sysbus_dma_as;
60765b6c
PMD		 1471 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1472 } else {
1473 /* use system_memory() if property "dma" not set */
1474 s->dma_as = &address_space_memory;
1475 }
dd55c485 1476
d7dfca08 1477 sysbus_init_irq(sbd, &s->irq);
fd1e5c81 1478
d7dfca08
IM		 1479 sysbus_init_mmio(sbd, &s->iomem);
1480}
1481
b69c3c21 1482static void sdhci_sysbus_unrealize(DeviceState *dev)
8b7455c7
PMD		 1483{
1484 SDHCIState *s = SYSBUS_SDHCI(dev);
1485
b69c3c21 1486 sdhci_common_unrealize(s);
60765b6c
PMD		 1487
1488 if (s->dma_mr) {
1489 address_space_destroy(s->dma_as);
1490 }
8b7455c7
PMD		 1491}
1492
7302dcd6 1493static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1494{
1495 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08 1496
4f67d30b 1497 device_class_set_props(dc, sdhci_sysbus_properties);
7302dcd6 1498 dc->realize = sdhci_sysbus_realize;
8b7455c7 1499 dc->unrealize = sdhci_sysbus_unrealize;
1c92c505
PMD		 1500
1501 sdhci_common_class_init(klass, data);
d7dfca08
IM		 1502}
1503
7302dcd6
KC		 1504static const TypeInfo sdhci_sysbus_info = {
1505 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1506 .parent = TYPE_SYS_BUS_DEVICE,
1507 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1508 .instance_init = sdhci_sysbus_init,
1509 .instance_finalize = sdhci_sysbus_finalize,
1510 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1511};
1512
b635d98c
PMD		 1513/* --- qdev bus master --- */
1514
40bbc194
PM		 1515static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1516{
1517 SDBusClass *sbc = SD_BUS_CLASS(klass);
1518
1519 sbc->set_inserted = sdhci_set_inserted;
1520 sbc->set_readonly = sdhci_set_readonly;
1521}
1522
1523static const TypeInfo sdhci_bus_info = {
1524 .name = TYPE_SDHCI_BUS,
1525 .parent = TYPE_SD_BUS,
1526 .instance_size = sizeof(SDBus),
1527 .class_init = sdhci_bus_class_init,
1528};
1529
efadc818
PMD		 1530/* --- qdev i.MX eSDHC --- */
1531
fd1e5c81
AS		 1532static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
1533{
1534 SDHCIState *s = SYSBUS_SDHCI(opaque);
1535 uint32_t ret;
06c5120b 1536 uint16_t hostctl1;
fd1e5c81
AS		 1537
1538 switch (offset) {
1539 default:
1540 return sdhci_read(opaque, offset, size);
1541
1542 case SDHC_HOSTCTL:
1543 /*
1544 * For a detailed explanation on the following bit
1545 * manipulation code see comments in a similar part of
1546 * usdhc_write()
1547 */
06c5120b 1548 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
fd1e5c81 1549
06c5120b
PMD		 1550 if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1551 hostctl1 |= ESDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1552 }
1553
06c5120b
PMD		 1554 if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1555 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1556 }
1557
06c5120b 1558 ret = hostctl1;
fd1e5c81
AS		 1559 ret |= (uint32_t)s->blkgap << 16;
1560 ret |= (uint32_t)s->wakcon << 24;
1561
1562 break;
1563
6bfd06da
HEF		 1564 case SDHC_PRNSTS:
1565 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1566 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1567 if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1568 ret |= ESDHC_PRNSTS_SDSTB;
1569 }
1570 break;
1571
fd1e5c81
AS		 1572 case ESDHC_DLL_CTRL:
1573 case ESDHC_TUNE_CTRL_STATUS:
1574 case ESDHC_UNDOCUMENTED_REG27:
1575 case ESDHC_TUNING_CTRL:
1576 case ESDHC_VENDOR_SPEC:
1577 case ESDHC_MIX_CTRL:
1578 case ESDHC_WTMK_LVL:
1579 ret = 0;
1580 break;
1581 }
1582
1583 return ret;
1584}
1585
1586static void
1587usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1588{
1589 SDHCIState *s = SYSBUS_SDHCI(opaque);
06c5120b 1590 uint8_t hostctl1;
fd1e5c81
AS		 1591 uint32_t value = (uint32_t)val;
1592
1593 switch (offset) {
1594 case ESDHC_DLL_CTRL:
1595 case ESDHC_TUNE_CTRL_STATUS:
1596 case ESDHC_UNDOCUMENTED_REG27:
1597 case ESDHC_TUNING_CTRL:
1598 case ESDHC_WTMK_LVL:
1599 case ESDHC_VENDOR_SPEC:
1600 break;
1601
1602 case SDHC_HOSTCTL:
1603 /*
1604 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1605 *
1606 * 7 6 5 4 3 2 1 0
1607 * |-----------+--------+--------+-----------+----------+---------|
1608 * | Card | Card | Endian | DATA3 | Data | Led |
1609 * | Detect | Detect | Mode | as Card | Transfer | Control |
1610 * | Signal | Test | | Detection | Width | |
1611 * | Selection | Level | | Pin | | |
1612 * |-----------+--------+--------+-----------+----------+---------|
1613 *
1614 * and 0x29
1615 *
1616 * 15 10 9 8
1617 * |----------+------|
1618 * | Reserved | DMA |
1619 * | | Sel. |
1620 * | | |
1621 * |----------+------|
1622 *
1623 * and here's what SDCHI spec expects those offsets to be:
1624 *
1625 * 0x28 (Host Control Register)
1626 *
1627 * 7 6 5 4 3 2 1 0
1628 * |--------+--------+----------+------+--------+----------+---------|
1629 * | Card | Card | Extended | DMA | High | Data | LED |
1630 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1631 * | Signal | Test | Transfer | | Enable | Width | |
1632 * | Sel. | Level | Width | | | | |
1633 * |--------+--------+----------+------+--------+----------+---------|
1634 *
1635 * and 0x29 (Power Control Register)
1636 *
1637 * |----------------------------------|
1638 * | Power Control Register |
1639 * | |
1640 * | Description omitted, |
1641 * | since it has no analog in ESDHCI |
1642 * | |
1643 * |----------------------------------|
1644 *
1645 * Since offsets 0x2A and 0x2B should be compatible between
1646 * both IP specs we only need to reconcile least 16-bit of the
1647 * word we've been given.
1648 */
1649
1650 /*
1651 * First, save bits 7 6 and 0 since they are identical
1652 */
06c5120b
PMD		 1653 hostctl1 = value & (SDHC_CTRL_LED |
1654 SDHC_CTRL_CDTEST_INS |
1655 SDHC_CTRL_CDTEST_EN);
fd1e5c81
AS		 1656 /*
1657 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1658 * bits 5 and 1
1659 */
1660 if (value & ESDHC_CTRL_8BITBUS) {
06c5120b 1661 hostctl1 |= SDHC_CTRL_8BITBUS;
fd1e5c81
AS		 1662 }
1663
1664 if (value & ESDHC_CTRL_4BITBUS) {
06c5120b 1665 hostctl1 |= ESDHC_CTRL_4BITBUS;
fd1e5c81
AS		 1666 }
1667
1668 /*
1669 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1670 */
06c5120b 1671 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
fd1e5c81
AS		 1672
1673 /*
1674 * Now place the corrected value into low 16-bit of the value
1675 * we are going to give standard SDHCI write function
1676 *
1677 * NOTE: This transformation should be the inverse of what can
1678 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1679 * kernel
1680 */
1681 value &= ~UINT16_MAX;
06c5120b 1682 value |= hostctl1;
fd1e5c81
AS		 1683 value |= (uint16_t)s->pwrcon << 8;
1684
1685 sdhci_write(opaque, offset, value, size);
1686 break;
1687
1688 case ESDHC_MIX_CTRL:
1689 /*
1690 * So, when SD/MMC stack in Linux tries to write to "Transfer
1691 * Mode Register", ESDHC i.MX quirk code will translate it
1692 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1693 * order to get where we started
1694 *
1695 * Note that Auto CMD23 Enable bit is located in a wrong place
1696 * on i.MX, but since it is not used by QEMU we do not care.
1697 *
1698 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1699 * here becuase it will result in a call to
1700 * sdhci_send_command(s) which we don't want.
1701 *
1702 */
1703 s->trnmod = value & UINT16_MAX;
1704 break;
1705 case SDHC_TRNMOD:
1706 /*
1707 * Similar to above, but this time a write to "Command
1708 * Register" will be translated into a 4-byte write to
1709 * "Transfer Mode register" where lower 16-bit of value would
1710 * be set to zero. So what we do is fill those bits with
1711 * cached value from s->trnmod and let the SDHCI
1712 * infrastructure handle the rest
1713 */
1714 sdhci_write(opaque, offset, val | s->trnmod, size);
1715 break;
1716 case SDHC_BLKSIZE:
1717 /*
1718 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1719 * Linux driver will try to zero this field out which will
1720 * break the rest of SDHCI emulation.
1721 *
1722 * Linux defaults to maximum possible setting (512K boundary)
1723 * and it seems to be the only option that i.MX IP implements,
1724 * so we artificially set it to that value.
1725 */
1726 val |= 0x7 << 12;
1727 /* FALLTHROUGH */
1728 default:
1729 sdhci_write(opaque, offset, val, size);
1730 break;
1731 }
1732}
1733
fd1e5c81
AS		 1734static const MemoryRegionOps usdhc_mmio_ops = {
1735 .read = usdhc_read,
1736 .write = usdhc_write,
1737 .valid = {
1738 .min_access_size = 1,
1739 .max_access_size = 4,
1740 .unaligned = false
1741 },
1742 .endianness = DEVICE_LITTLE_ENDIAN,
1743};
1744
1745static void imx_usdhc_init(Object *obj)
1746{
1747 SDHCIState *s = SYSBUS_SDHCI(obj);
1748
1749 s->io_ops = &usdhc_mmio_ops;
1750 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1751}
1752
1753static const TypeInfo imx_usdhc_info = {
1754 .name = TYPE_IMX_USDHC,
1755 .parent = TYPE_SYSBUS_SDHCI,
1756 .instance_init = imx_usdhc_init,
1757};
1758
c85fba50
PMD		 1759/* --- qdev Samsung s3c --- */
1760
1761#define S3C_SDHCI_CONTROL2 0x80
1762#define S3C_SDHCI_CONTROL3 0x84
1763#define S3C_SDHCI_CONTROL4 0x8c
1764
1765static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
1766{
1767 uint64_t ret;
1768
1769 switch (offset) {
1770 case S3C_SDHCI_CONTROL2:
1771 case S3C_SDHCI_CONTROL3:
1772 case S3C_SDHCI_CONTROL4:
1773 /* ignore */
1774 ret = 0;
1775 break;
1776 default:
1777 ret = sdhci_read(opaque, offset, size);
1778 break;
1779 }
1780
1781 return ret;
1782}
1783
1784static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
1785 unsigned size)
1786{
1787 switch (offset) {
1788 case S3C_SDHCI_CONTROL2:
1789 case S3C_SDHCI_CONTROL3:
1790 case S3C_SDHCI_CONTROL4:
1791 /* ignore */
1792 break;
1793 default:
1794 sdhci_write(opaque, offset, val, size);
1795 break;
1796 }
1797}
1798
1799static const MemoryRegionOps sdhci_s3c_mmio_ops = {
1800 .read = sdhci_s3c_read,
1801 .write = sdhci_s3c_write,
1802 .valid = {
1803 .min_access_size = 1,
1804 .max_access_size = 4,
1805 .unaligned = false
1806 },
1807 .endianness = DEVICE_LITTLE_ENDIAN,
1808};
1809
1810static void sdhci_s3c_init(Object *obj)
1811{
1812 SDHCIState *s = SYSBUS_SDHCI(obj);
1813
1814 s->io_ops = &sdhci_s3c_mmio_ops;
1815}
1816
1817static const TypeInfo sdhci_s3c_info = {
1818 .name = TYPE_S3C_SDHCI ,
1819 .parent = TYPE_SYSBUS_SDHCI,
1820 .instance_init = sdhci_s3c_init,
1821};
1822
d7dfca08
IM		 1823static void sdhci_register_types(void)
1824{
7302dcd6 1825 type_register_static(&sdhci_sysbus_info);
40bbc194 1826 type_register_static(&sdhci_bus_info);
fd1e5c81 1827 type_register_static(&imx_usdhc_info);
c85fba50 1828 type_register_static(&sdhci_s3c_info);
d7dfca08
IM		 1829}
1830
1831type_init(sdhci_register_types)
Mirror of https://git.qemu.org/git/qemu.git