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target-*: Increment num_insns immediately after tcg_gen_insn_start
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
7a3f1944
FB		 21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
76cad711 28#include "disas/disas.h"
2ef6175a 29#include "exec/helper-proto.h"
57fec1fe 30#include "tcg-op.h"
f08b6170 31#include "exec/cpu_ldst.h"
7a3f1944 32
2ef6175a 33#include "exec/helper-gen.h"
a7812ae4 34
a7e30d84
LV		 35#include "trace-tcg.h"
36
37
7a3f1944
FB		 38#define DEBUG_DISAS
39
72cbca10
FB		 40#define DYNAMIC_PC 1 /* dynamic pc value */
41#define JUMP_PC 2 /* dynamic pc value which takes only two values
42 according to jump_pc[T2] */
43
1a2fb1c0 44/* global register indexes */
a7812ae4 45static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 48static TCGv_i32 cpu_psr;
49static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a7812ae4
PB		 56static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
60static TCGv_i32 cpu_softint;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
1a7ff922
PB		 67static target_ulong gen_opc_npc[OPC_BUF_SIZE];
68static target_ulong gen_opc_jump_pc[2];
69
022c62cb 70#include "exec/gen-icount.h"
2e70f6ef 71
7a3f1944 72typedef struct DisasContext {
0f8a249a
BS		 73 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
74 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 75 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 76 int is_br;
e8af50a3 77 int mem_idx;
a80dde08 78 int fpu_enabled;
2cade6a3 79 int address_mask_32bit;
060718c1 80 int singlestep;
8393617c 81 uint32_t cc_op; /* current CC operation */
cf495bcf 82 struct TranslationBlock *tb;
5578ceab 83 sparc_def_t *def;
30038fd8 84 TCGv_i32 t32[3];
88023616 85 TCGv ttl[5];
30038fd8 86 int n_t32;
88023616 87 int n_ttl;
7a3f1944
FB		 88} DisasContext;
89
416fcaea
RH		 90typedef struct {
91 TCGCond cond;
92 bool is_bool;
93 bool g1, g2;
94 TCGv c1, c2;
95} DisasCompare;
96
3475187d 97// This function uses non-native bit order
dc1a6971
BS		 98#define GET_FIELD(X, FROM, TO) \
99 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 100
3475187d 101// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 102#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 103 GET_FIELD(X, 31 - (TO), 31 - (FROM))
104
105#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 106#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 107
108#ifdef TARGET_SPARC64
0387d928 109#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 110#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 111#else
c185970a 112#define DFPREG(r) (r & 0x1e)
1f587329 113#define QFPREG(r) (r & 0x1c)
3475187d
FB		 114#endif
115
b158a785
BS		 116#define UA2005_HTRAP_MASK 0xff
117#define V8_TRAP_MASK 0x7f
118
3475187d
FB		 119static int sign_extend(int x, int len)
120{
121 len = 32 - len;
122 return (x << len) >> len;
123}
124
7a3f1944
FB		 125#define IS_IMM (insn & (1<<13))
126
2ae23e17
RH		 127static inline TCGv_i32 get_temp_i32(DisasContext *dc)
128{
129 TCGv_i32 t;
130 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
131 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
132 return t;
133}
134
135static inline TCGv get_temp_tl(DisasContext *dc)
136{
137 TCGv t;
138 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
139 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
140 return t;
141}
142
141ae5c1
RH		 143static inline void gen_update_fprs_dirty(int rd)
144{
145#if defined(TARGET_SPARC64)
146 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
147#endif
148}
149
ff07ec83 150/* floating point registers moves */
208ae657
RH		 151static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
152{
30038fd8
RH		 153#if TCG_TARGET_REG_BITS == 32
154 if (src & 1) {
155 return TCGV_LOW(cpu_fpr[src / 2]);
156 } else {
157 return TCGV_HIGH(cpu_fpr[src / 2]);
158 }
159#else
160 if (src & 1) {
161 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
162 } else {
2ae23e17 163 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 164 TCGv_i64 t = tcg_temp_new_i64();
165
166 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 167 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 168 tcg_temp_free_i64(t);
169
30038fd8
RH		 170 return ret;
171 }
172#endif
208ae657
RH		 173}
174
175static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
176{
30038fd8
RH		 177#if TCG_TARGET_REG_BITS == 32
178 if (dst & 1) {
179 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
180 } else {
181 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
182 }
183#else
184 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
185 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
186 (dst & 1 ? 0 : 32), 32);
187#endif
141ae5c1 188 gen_update_fprs_dirty(dst);
208ae657
RH		 189}
190
ba5f5179 191static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 192{
ba5f5179 193 return get_temp_i32(dc);
208ae657
RH		 194}
195
96eda024
RH		 196static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
197{
96eda024 198 src = DFPREG(src);
30038fd8 199 return cpu_fpr[src / 2];
96eda024
RH		 200}
201
202static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
203{
204 dst = DFPREG(dst);
30038fd8 205 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 206 gen_update_fprs_dirty(dst);
207}
208
3886b8a3 209static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 210{
3886b8a3 211 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 212}
213
ff07ec83
BS		 214static void gen_op_load_fpr_QT0(unsigned int src)
215{
30038fd8
RH		 216 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
217 offsetof(CPU_QuadU, ll.upper));
218 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
219 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 220}
221
222static void gen_op_load_fpr_QT1(unsigned int src)
223{
30038fd8
RH		 224 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
225 offsetof(CPU_QuadU, ll.upper));
226 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
227 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 228}
229
230static void gen_op_store_QT0_fpr(unsigned int dst)
231{
30038fd8
RH		 232 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
233 offsetof(CPU_QuadU, ll.upper));
234 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
235 offsetof(CPU_QuadU, ll.lower));
ff07ec83 236}
1f587329 237
ac11f776 238#ifdef TARGET_SPARC64
30038fd8 239static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 240{
241 rd = QFPREG(rd);
242 rs = QFPREG(rs);
243
30038fd8
RH		 244 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
245 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 246 gen_update_fprs_dirty(rd);
247}
248#endif
249
81ad8ba2
BS		 250/* moves */
251#ifdef CONFIG_USER_ONLY
3475187d 252#define supervisor(dc) 0
81ad8ba2 253#ifdef TARGET_SPARC64
e9ebed4d 254#define hypervisor(dc) 0
81ad8ba2 255#endif
3475187d 256#else
2aae2b8e 257#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 258#ifdef TARGET_SPARC64
2aae2b8e 259#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 260#else
3475187d 261#endif
81ad8ba2
BS		 262#endif
263
2cade6a3
BS		 264#ifdef TARGET_SPARC64
265#ifndef TARGET_ABI32
266#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 267#else
2cade6a3
BS		 268#define AM_CHECK(dc) (1)
269#endif
1a2fb1c0 270#endif
3391c818 271
2cade6a3
BS		 272static inline void gen_address_mask(DisasContext *dc, TCGv addr)
273{
274#ifdef TARGET_SPARC64
275 if (AM_CHECK(dc))
276 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
277#endif
278}
279
88023616
RH		 280static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
281{
282 if (reg == 0 || reg >= 8) {
283 TCGv t = get_temp_tl(dc);
284 if (reg == 0) {
285 tcg_gen_movi_tl(t, 0);
286 } else {
287 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
288 }
289 return t;
290 } else {
291 return cpu_gregs[reg];
292 }
293}
294
295static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
296{
297 if (reg > 0) {
298 if (reg < 8) {
299 tcg_gen_mov_tl(cpu_gregs[reg], v);
300 } else {
301 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
302 }
303 }
304}
305
306static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
307{
308 if (reg == 0 || reg >= 8) {
309 return get_temp_tl(dc);
310 } else {
311 return cpu_gregs[reg];
312 }
313}
314
5fafdf24 315static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 316 target_ulong pc, target_ulong npc)
317{
318 TranslationBlock *tb;
319
320 tb = s->tb;
321 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 322 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
323 !s->singlestep) {
6e256c93 324 /* jump to same page: we can use a direct jump */
57fec1fe 325 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 326 tcg_gen_movi_tl(cpu_pc, pc);
327 tcg_gen_movi_tl(cpu_npc, npc);
8cfd0495 328 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
6e256c93
FB		 329 } else {
330 /* jump to another page: currently not optimized */
2f5680ee
BS		 331 tcg_gen_movi_tl(cpu_pc, pc);
332 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 333 tcg_gen_exit_tb(0);
6e256c93
FB		 334 }
335}
336
19f329ad 337// XXX suboptimal
a7812ae4 338static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 339{
8911f501 340 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 341 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 342 tcg_gen_andi_tl(reg, reg, 0x1);
343}
344
a7812ae4 345static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 346{
8911f501 347 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 348 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 349 tcg_gen_andi_tl(reg, reg, 0x1);
350}
351
a7812ae4 352static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 353{
8911f501 354 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 355 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 356 tcg_gen_andi_tl(reg, reg, 0x1);
357}
358
a7812ae4 359static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 360{
8911f501 361 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 362 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 363 tcg_gen_andi_tl(reg, reg, 0x1);
364}
365
4af984a7 366static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 367{
4af984a7 368 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 369 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 370 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 371 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 372}
373
70c48285 374static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 375{
70c48285
RH		 376 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
377
378 /* Carry is computed from a previous add: (dst < src) */
379#if TARGET_LONG_BITS == 64
380 cc_src1_32 = tcg_temp_new_i32();
381 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 382 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
383 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 384#else
385 cc_src1_32 = cpu_cc_dst;
386 cc_src2_32 = cpu_cc_src;
387#endif
388
389 carry_32 = tcg_temp_new_i32();
390 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
391
392#if TARGET_LONG_BITS == 64
393 tcg_temp_free_i32(cc_src1_32);
394 tcg_temp_free_i32(cc_src2_32);
395#endif
396
397 return carry_32;
41d72852
BS		 398}
399
70c48285 400static TCGv_i32 gen_sub32_carry32(void)
41d72852 401{
70c48285
RH		 402 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
403
404 /* Carry is computed from a previous borrow: (src1 < src2) */
405#if TARGET_LONG_BITS == 64
406 cc_src1_32 = tcg_temp_new_i32();
407 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 408 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
409 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 410#else
411 cc_src1_32 = cpu_cc_src;
412 cc_src2_32 = cpu_cc_src2;
413#endif
414
415 carry_32 = tcg_temp_new_i32();
416 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
417
418#if TARGET_LONG_BITS == 64
419 tcg_temp_free_i32(cc_src1_32);
420 tcg_temp_free_i32(cc_src2_32);
421#endif
422
423 return carry_32;
424}
425
426static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
427 TCGv src2, int update_cc)
428{
429 TCGv_i32 carry_32;
430 TCGv carry;
431
432 switch (dc->cc_op) {
433 case CC_OP_DIV:
434 case CC_OP_LOGIC:
435 /* Carry is known to be zero. Fall back to plain ADD. */
436 if (update_cc) {
437 gen_op_add_cc(dst, src1, src2);
438 } else {
439 tcg_gen_add_tl(dst, src1, src2);
440 }
441 return;
442
443 case CC_OP_ADD:
444 case CC_OP_TADD:
445 case CC_OP_TADDTV:
15fe216f
RH		 446 if (TARGET_LONG_BITS == 32) {
447 /* We can re-use the host's hardware carry generation by using
448 an ADD2 opcode. We discard the low part of the output.
449 Ideally we'd combine this operation with the add that
450 generated the carry in the first place. */
451 carry = tcg_temp_new();
452 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
453 tcg_temp_free(carry);
70c48285
RH		 454 goto add_done;
455 }
70c48285
RH		 456 carry_32 = gen_add32_carry32();
457 break;
458
459 case CC_OP_SUB:
460 case CC_OP_TSUB:
461 case CC_OP_TSUBTV:
462 carry_32 = gen_sub32_carry32();
463 break;
464
465 default:
466 /* We need external help to produce the carry. */
467 carry_32 = tcg_temp_new_i32();
2ffd9176 468 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 469 break;
470 }
471
472#if TARGET_LONG_BITS == 64
473 carry = tcg_temp_new();
474 tcg_gen_extu_i32_i64(carry, carry_32);
475#else
476 carry = carry_32;
477#endif
478
479 tcg_gen_add_tl(dst, src1, src2);
480 tcg_gen_add_tl(dst, dst, carry);
481
482 tcg_temp_free_i32(carry_32);
483#if TARGET_LONG_BITS == 64
484 tcg_temp_free(carry);
485#endif
486
70c48285 487 add_done:
70c48285
RH		 488 if (update_cc) {
489 tcg_gen_mov_tl(cpu_cc_src, src1);
490 tcg_gen_mov_tl(cpu_cc_src2, src2);
491 tcg_gen_mov_tl(cpu_cc_dst, dst);
492 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
493 dc->cc_op = CC_OP_ADDX;
494 }
dc99a3f2
BS		 495}
496
41d72852 497static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 498{
4af984a7 499 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 500 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 501 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 502 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 503}
504
70c48285
RH		 505static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
506 TCGv src2, int update_cc)
41d72852 507{
70c48285
RH		 508 TCGv_i32 carry_32;
509 TCGv carry;
41d72852 510
70c48285
RH		 511 switch (dc->cc_op) {
512 case CC_OP_DIV:
513 case CC_OP_LOGIC:
514 /* Carry is known to be zero. Fall back to plain SUB. */
515 if (update_cc) {
516 gen_op_sub_cc(dst, src1, src2);
517 } else {
518 tcg_gen_sub_tl(dst, src1, src2);
519 }
520 return;
521
522 case CC_OP_ADD:
523 case CC_OP_TADD:
524 case CC_OP_TADDTV:
525 carry_32 = gen_add32_carry32();
526 break;
527
528 case CC_OP_SUB:
529 case CC_OP_TSUB:
530 case CC_OP_TSUBTV:
15fe216f
RH		 531 if (TARGET_LONG_BITS == 32) {
532 /* We can re-use the host's hardware carry generation by using
533 a SUB2 opcode. We discard the low part of the output.
534 Ideally we'd combine this operation with the add that
535 generated the carry in the first place. */
536 carry = tcg_temp_new();
537 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
538 tcg_temp_free(carry);
70c48285
RH		 539 goto sub_done;
540 }
70c48285
RH		 541 carry_32 = gen_sub32_carry32();
542 break;
543
544 default:
545 /* We need external help to produce the carry. */
546 carry_32 = tcg_temp_new_i32();
2ffd9176 547 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 548 break;
549 }
550
551#if TARGET_LONG_BITS == 64
552 carry = tcg_temp_new();
553 tcg_gen_extu_i32_i64(carry, carry_32);
554#else
555 carry = carry_32;
556#endif
557
558 tcg_gen_sub_tl(dst, src1, src2);
559 tcg_gen_sub_tl(dst, dst, carry);
560
561 tcg_temp_free_i32(carry_32);
562#if TARGET_LONG_BITS == 64
563 tcg_temp_free(carry);
564#endif
565
70c48285 566 sub_done:
70c48285
RH		 567 if (update_cc) {
568 tcg_gen_mov_tl(cpu_cc_src, src1);
569 tcg_gen_mov_tl(cpu_cc_src2, src2);
570 tcg_gen_mov_tl(cpu_cc_dst, dst);
571 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
572 dc->cc_op = CC_OP_SUBX;
573 }
dc99a3f2
BS		 574}
575
4af984a7 576static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 577{
de9e9d9f 578 TCGv r_temp, zero, t0;
d9bdab86 579
a7812ae4 580 r_temp = tcg_temp_new();
de9e9d9f 581 t0 = tcg_temp_new();
d9bdab86
BS		 582
583 /* old op:
584 if (!(env->y & 1))
585 T1 = 0;
586 */
6cb675b0 587 zero = tcg_const_tl(0);
72ccba79 588 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 589 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 590 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 591 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
592 zero, cpu_cc_src2);
593 tcg_temp_free(zero);
d9bdab86
BS		 594
595 // b2 = T0 & 1;
596 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 597 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
598 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 599 tcg_gen_shri_tl(t0, cpu_y, 1);
600 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
601 tcg_gen_or_tl(t0, t0, r_temp);
602 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 603
604 // b1 = N ^ V;
de9e9d9f 605 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 606 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 607 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 608 tcg_temp_free(r_temp);
d9bdab86
BS		 609
610 // T0 = (b1 << 31) | (T0 >> 1);
611 // src1 = T0;
de9e9d9f 612 tcg_gen_shli_tl(t0, t0, 31);
6f551262 613 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 614 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
615 tcg_temp_free(t0);
d9bdab86 616
5c6a0628 617 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 618
5c6a0628 619 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 620}
621
fb170183 622static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 623{
528692a8 624#if TARGET_LONG_BITS == 32
fb170183 625 if (sign_ext) {
528692a8 626 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 627 } else {
528692a8 628 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 629 }
528692a8
RH		 630#else
631 TCGv t0 = tcg_temp_new_i64();
632 TCGv t1 = tcg_temp_new_i64();
fb170183 633
528692a8
RH		 634 if (sign_ext) {
635 tcg_gen_ext32s_i64(t0, src1);
636 tcg_gen_ext32s_i64(t1, src2);
637 } else {
638 tcg_gen_ext32u_i64(t0, src1);
639 tcg_gen_ext32u_i64(t1, src2);
640 }
fb170183 641
528692a8
RH		 642 tcg_gen_mul_i64(dst, t0, t1);
643 tcg_temp_free(t0);
644 tcg_temp_free(t1);
fb170183 645
528692a8
RH		 646 tcg_gen_shri_i64(cpu_y, dst, 32);
647#endif
8879d139
BS		 648}
649
fb170183 650static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 651{
fb170183
IK		 652 /* zero-extend truncated operands before multiplication */
653 gen_op_multiply(dst, src1, src2, 0);
654}
8879d139 655
fb170183
IK		 656static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
657{
658 /* sign-extend truncated operands before multiplication */
659 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 660}
661
19f329ad
BS		 662// 1
663static inline void gen_op_eval_ba(TCGv dst)
664{
665 tcg_gen_movi_tl(dst, 1);
666}
667
668// Z
a7812ae4 669static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 670{
671 gen_mov_reg_Z(dst, src);
672}
673
674// Z | (N ^ V)
a7812ae4 675static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 676{
de9e9d9f
RH		 677 TCGv t0 = tcg_temp_new();
678 gen_mov_reg_N(t0, src);
19f329ad 679 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 680 tcg_gen_xor_tl(dst, dst, t0);
681 gen_mov_reg_Z(t0, src);
682 tcg_gen_or_tl(dst, dst, t0);
683 tcg_temp_free(t0);
19f329ad
BS		 684}
685
686// N ^ V
a7812ae4 687static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 688{
de9e9d9f
RH		 689 TCGv t0 = tcg_temp_new();
690 gen_mov_reg_V(t0, src);
19f329ad 691 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 692 tcg_gen_xor_tl(dst, dst, t0);
693 tcg_temp_free(t0);
19f329ad
BS		 694}
695
696// C | Z
a7812ae4 697static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 698{
de9e9d9f
RH		 699 TCGv t0 = tcg_temp_new();
700 gen_mov_reg_Z(t0, src);
19f329ad 701 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 702 tcg_gen_or_tl(dst, dst, t0);
703 tcg_temp_free(t0);
19f329ad
BS		 704}
705
706// C
a7812ae4 707static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 708{
709 gen_mov_reg_C(dst, src);
710}
711
712// V
a7812ae4 713static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 714{
715 gen_mov_reg_V(dst, src);
716}
717
718// 0
719static inline void gen_op_eval_bn(TCGv dst)
720{
721 tcg_gen_movi_tl(dst, 0);
722}
723
724// N
a7812ae4 725static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 726{
727 gen_mov_reg_N(dst, src);
728}
729
730// !Z
a7812ae4 731static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 732{
733 gen_mov_reg_Z(dst, src);
734 tcg_gen_xori_tl(dst, dst, 0x1);
735}
736
737// !(Z | (N ^ V))
a7812ae4 738static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 739{
de9e9d9f 740 gen_op_eval_ble(dst, src);
19f329ad
BS		 741 tcg_gen_xori_tl(dst, dst, 0x1);
742}
743
744// !(N ^ V)
a7812ae4 745static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 746{
de9e9d9f 747 gen_op_eval_bl(dst, src);
19f329ad
BS		 748 tcg_gen_xori_tl(dst, dst, 0x1);
749}
750
751// !(C | Z)
a7812ae4 752static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 753{
de9e9d9f 754 gen_op_eval_bleu(dst, src);
19f329ad
BS		 755 tcg_gen_xori_tl(dst, dst, 0x1);
756}
757
758// !C
a7812ae4 759static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 760{
761 gen_mov_reg_C(dst, src);
762 tcg_gen_xori_tl(dst, dst, 0x1);
763}
764
765// !N
a7812ae4 766static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 767{
768 gen_mov_reg_N(dst, src);
769 tcg_gen_xori_tl(dst, dst, 0x1);
770}
771
772// !V
a7812ae4 773static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 774{
775 gen_mov_reg_V(dst, src);
776 tcg_gen_xori_tl(dst, dst, 0x1);
777}
778
779/*
780 FPSR bit field FCC1 | FCC0:
781 0 =
782 1 <
783 2 >
784 3 unordered
785*/
786static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
787 unsigned int fcc_offset)
788{
ba6a9d8c 789 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 790 tcg_gen_andi_tl(reg, reg, 0x1);
791}
792
793static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
794 unsigned int fcc_offset)
795{
ba6a9d8c 796 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 797 tcg_gen_andi_tl(reg, reg, 0x1);
798}
799
800// !0: FCC0 | FCC1
801static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
802 unsigned int fcc_offset)
803{
de9e9d9f 804 TCGv t0 = tcg_temp_new();
19f329ad 805 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 806 gen_mov_reg_FCC1(t0, src, fcc_offset);
807 tcg_gen_or_tl(dst, dst, t0);
808 tcg_temp_free(t0);
19f329ad
BS		 809}
810
811// 1 or 2: FCC0 ^ FCC1
812static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
813 unsigned int fcc_offset)
814{
de9e9d9f 815 TCGv t0 = tcg_temp_new();
19f329ad 816 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 817 gen_mov_reg_FCC1(t0, src, fcc_offset);
818 tcg_gen_xor_tl(dst, dst, t0);
819 tcg_temp_free(t0);
19f329ad
BS		 820}
821
822// 1 or 3: FCC0
823static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
824 unsigned int fcc_offset)
825{
826 gen_mov_reg_FCC0(dst, src, fcc_offset);
827}
828
829// 1: FCC0 & !FCC1
830static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
831 unsigned int fcc_offset)
832{
de9e9d9f 833 TCGv t0 = tcg_temp_new();
19f329ad 834 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 835 gen_mov_reg_FCC1(t0, src, fcc_offset);
836 tcg_gen_andc_tl(dst, dst, t0);
837 tcg_temp_free(t0);
19f329ad
BS		 838}
839
840// 2 or 3: FCC1
841static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
842 unsigned int fcc_offset)
843{
844 gen_mov_reg_FCC1(dst, src, fcc_offset);
845}
846
847// 2: !FCC0 & FCC1
848static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
849 unsigned int fcc_offset)
850{
de9e9d9f 851 TCGv t0 = tcg_temp_new();
19f329ad 852 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 853 gen_mov_reg_FCC1(t0, src, fcc_offset);
854 tcg_gen_andc_tl(dst, t0, dst);
855 tcg_temp_free(t0);
19f329ad
BS		 856}
857
858// 3: FCC0 & FCC1
859static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
860 unsigned int fcc_offset)
861{
de9e9d9f 862 TCGv t0 = tcg_temp_new();
19f329ad 863 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 864 gen_mov_reg_FCC1(t0, src, fcc_offset);
865 tcg_gen_and_tl(dst, dst, t0);
866 tcg_temp_free(t0);
19f329ad
BS		 867}
868
869// 0: !(FCC0 | FCC1)
870static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
871 unsigned int fcc_offset)
872{
de9e9d9f 873 TCGv t0 = tcg_temp_new();
19f329ad 874 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 875 gen_mov_reg_FCC1(t0, src, fcc_offset);
876 tcg_gen_or_tl(dst, dst, t0);
19f329ad 877 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 878 tcg_temp_free(t0);
19f329ad
BS		 879}
880
881// 0 or 3: !(FCC0 ^ FCC1)
882static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
883 unsigned int fcc_offset)
884{
de9e9d9f 885 TCGv t0 = tcg_temp_new();
19f329ad 886 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 887 gen_mov_reg_FCC1(t0, src, fcc_offset);
888 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 889 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 890 tcg_temp_free(t0);
19f329ad
BS		 891}
892
893// 0 or 2: !FCC0
894static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
895 unsigned int fcc_offset)
896{
897 gen_mov_reg_FCC0(dst, src, fcc_offset);
898 tcg_gen_xori_tl(dst, dst, 0x1);
899}
900
901// !1: !(FCC0 & !FCC1)
902static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
903 unsigned int fcc_offset)
904{
de9e9d9f 905 TCGv t0 = tcg_temp_new();
19f329ad 906 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 907 gen_mov_reg_FCC1(t0, src, fcc_offset);
908 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 909 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 910 tcg_temp_free(t0);
19f329ad
BS		 911}
912
913// 0 or 1: !FCC1
914static inline void gen_op_eval_fble(TCGv dst, TCGv src,
915 unsigned int fcc_offset)
916{
917 gen_mov_reg_FCC1(dst, src, fcc_offset);
918 tcg_gen_xori_tl(dst, dst, 0x1);
919}
920
921// !2: !(!FCC0 & FCC1)
922static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
923 unsigned int fcc_offset)
924{
de9e9d9f 925 TCGv t0 = tcg_temp_new();
19f329ad 926 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 927 gen_mov_reg_FCC1(t0, src, fcc_offset);
928 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 929 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 930 tcg_temp_free(t0);
19f329ad
BS		 931}
932
933// !3: !(FCC0 & FCC1)
934static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
935 unsigned int fcc_offset)
936{
de9e9d9f 937 TCGv t0 = tcg_temp_new();
19f329ad 938 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 939 gen_mov_reg_FCC1(t0, src, fcc_offset);
940 tcg_gen_and_tl(dst, dst, t0);
19f329ad 941 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 942 tcg_temp_free(t0);
19f329ad
BS		 943}
944
46525e1f 945static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 946 target_ulong pc2, TCGv r_cond)
83469015 947{
42a268c2 948 TCGLabel *l1 = gen_new_label();
83469015 949
cb63669a 950 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 951
6e256c93 952 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 953
954 gen_set_label(l1);
6e256c93 955 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 956}
957
46525e1f 958static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 959 target_ulong pc2, TCGv r_cond)
83469015 960{
42a268c2 961 TCGLabel *l1 = gen_new_label();
83469015 962
cb63669a 963 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 964
6e256c93 965 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 966
967 gen_set_label(l1);
6e256c93 968 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 969}
970
2e655fe7 971static inline void gen_generic_branch(DisasContext *dc)
83469015 972{
61316742
RH		 973 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
974 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
975 TCGv zero = tcg_const_tl(0);
19f329ad 976
61316742 977 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 978
61316742
RH		 979 tcg_temp_free(npc0);
980 tcg_temp_free(npc1);
981 tcg_temp_free(zero);
83469015
FB		 982}
983
4af984a7
BS		 984/* call this function before using the condition register as it may
985 have been set for a jump */
dee8913c 986static inline void flush_cond(DisasContext *dc)
83469015
FB		 987{
988 if (dc->npc == JUMP_PC) {
2e655fe7 989 gen_generic_branch(dc);
83469015
FB		 990 dc->npc = DYNAMIC_PC;
991 }
992}
993
934da7ee 994static inline void save_npc(DisasContext *dc)
72cbca10
FB		 995{
996 if (dc->npc == JUMP_PC) {
2e655fe7 997 gen_generic_branch(dc);
72cbca10
FB		 998 dc->npc = DYNAMIC_PC;
999 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1000 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1001 }
1002}
1003
20132b96 1004static inline void update_psr(DisasContext *dc)
72cbca10 1005{
cfa90513
BS		 1006 if (dc->cc_op != CC_OP_FLAGS) {
1007 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1008 gen_helper_compute_psr(cpu_env);
cfa90513 1009 }
20132b96
RH		 1010}
1011
1012static inline void save_state(DisasContext *dc)
1013{
1014 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1015 save_npc(dc);
72cbca10
FB		 1016}
1017
13a6dd00 1018static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1019{
1020 if (dc->npc == JUMP_PC) {
2e655fe7 1021 gen_generic_branch(dc);
48d5c82b 1022 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1023 dc->pc = DYNAMIC_PC;
1024 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1025 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1026 dc->pc = DYNAMIC_PC;
1027 } else {
1028 dc->pc = dc->npc;
1029 }
1030}
1031
38bc628b
BS		 1032static inline void gen_op_next_insn(void)
1033{
48d5c82b
BS		 1034 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1035 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1036}
1037
416fcaea
RH		 1038static void free_compare(DisasCompare *cmp)
1039{
1040 if (!cmp->g1) {
1041 tcg_temp_free(cmp->c1);
1042 }
1043 if (!cmp->g2) {
1044 tcg_temp_free(cmp->c2);
1045 }
1046}
1047
2a484ecf 1048static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1049 DisasContext *dc)
19f329ad 1050{
2a484ecf 1051 static int subcc_cond[16] = {
96b5a3d3 1052 TCG_COND_NEVER,
2a484ecf
RH		 1053 TCG_COND_EQ,
1054 TCG_COND_LE,
1055 TCG_COND_LT,
1056 TCG_COND_LEU,
1057 TCG_COND_LTU,
1058 -1, /* neg */
1059 -1, /* overflow */
96b5a3d3 1060 TCG_COND_ALWAYS,
2a484ecf
RH		 1061 TCG_COND_NE,
1062 TCG_COND_GT,
1063 TCG_COND_GE,
1064 TCG_COND_GTU,
1065 TCG_COND_GEU,
1066 -1, /* pos */
1067 -1, /* no overflow */
1068 };
1069
96b5a3d3
RH		 1070 static int logic_cond[16] = {
1071 TCG_COND_NEVER,
1072 TCG_COND_EQ, /* eq: Z */
1073 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1074 TCG_COND_LT, /* lt: N ^ V -> N */
1075 TCG_COND_EQ, /* leu: C | Z -> Z */
1076 TCG_COND_NEVER, /* ltu: C -> 0 */
1077 TCG_COND_LT, /* neg: N */
1078 TCG_COND_NEVER, /* vs: V -> 0 */
1079 TCG_COND_ALWAYS,
1080 TCG_COND_NE, /* ne: !Z */
1081 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1082 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1083 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1084 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1085 TCG_COND_GE, /* pos: !N */
1086 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1087 };
1088
a7812ae4 1089 TCGv_i32 r_src;
416fcaea
RH		 1090 TCGv r_dst;
1091
3475187d 1092#ifdef TARGET_SPARC64
2a484ecf 1093 if (xcc) {
dc99a3f2 1094 r_src = cpu_xcc;
2a484ecf 1095 } else {
dc99a3f2 1096 r_src = cpu_psr;
2a484ecf 1097 }
3475187d 1098#else
dc99a3f2 1099 r_src = cpu_psr;
3475187d 1100#endif
2a484ecf 1101
8393617c 1102 switch (dc->cc_op) {
96b5a3d3
RH		 1103 case CC_OP_LOGIC:
1104 cmp->cond = logic_cond[cond];
1105 do_compare_dst_0:
1106 cmp->is_bool = false;
1107 cmp->g2 = false;
1108 cmp->c2 = tcg_const_tl(0);
1109#ifdef TARGET_SPARC64
1110 if (!xcc) {
1111 cmp->g1 = false;
1112 cmp->c1 = tcg_temp_new();
1113 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1114 break;
1115 }
1116#endif
1117 cmp->g1 = true;
1118 cmp->c1 = cpu_cc_dst;
1119 break;
1120
2a484ecf
RH		 1121 case CC_OP_SUB:
1122 switch (cond) {
1123 case 6: /* neg */
1124 case 14: /* pos */
1125 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1126 goto do_compare_dst_0;
2a484ecf 1127
2a484ecf
RH		 1128 case 7: /* overflow */
1129 case 15: /* !overflow */
1130 goto do_dynamic;
1131
1132 default:
1133 cmp->cond = subcc_cond[cond];
1134 cmp->is_bool = false;
1135#ifdef TARGET_SPARC64
1136 if (!xcc) {
1137 /* Note that sign-extension works for unsigned compares as
1138 long as both operands are sign-extended. */
1139 cmp->g1 = cmp->g2 = false;
1140 cmp->c1 = tcg_temp_new();
1141 cmp->c2 = tcg_temp_new();
1142 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1143 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1144 break;
2a484ecf
RH		 1145 }
1146#endif
1147 cmp->g1 = cmp->g2 = true;
1148 cmp->c1 = cpu_cc_src;
1149 cmp->c2 = cpu_cc_src2;
1150 break;
1151 }
8393617c 1152 break;
2a484ecf 1153
8393617c 1154 default:
2a484ecf 1155 do_dynamic:
2ffd9176 1156 gen_helper_compute_psr(cpu_env);
8393617c 1157 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1158 /* FALLTHRU */
1159
1160 case CC_OP_FLAGS:
1161 /* We're going to generate a boolean result. */
1162 cmp->cond = TCG_COND_NE;
1163 cmp->is_bool = true;
1164 cmp->g1 = cmp->g2 = false;
1165 cmp->c1 = r_dst = tcg_temp_new();
1166 cmp->c2 = tcg_const_tl(0);
1167
1168 switch (cond) {
1169 case 0x0:
1170 gen_op_eval_bn(r_dst);
1171 break;
1172 case 0x1:
1173 gen_op_eval_be(r_dst, r_src);
1174 break;
1175 case 0x2:
1176 gen_op_eval_ble(r_dst, r_src);
1177 break;
1178 case 0x3:
1179 gen_op_eval_bl(r_dst, r_src);
1180 break;
1181 case 0x4:
1182 gen_op_eval_bleu(r_dst, r_src);
1183 break;
1184 case 0x5:
1185 gen_op_eval_bcs(r_dst, r_src);
1186 break;
1187 case 0x6:
1188 gen_op_eval_bneg(r_dst, r_src);
1189 break;
1190 case 0x7:
1191 gen_op_eval_bvs(r_dst, r_src);
1192 break;
1193 case 0x8:
1194 gen_op_eval_ba(r_dst);
1195 break;
1196 case 0x9:
1197 gen_op_eval_bne(r_dst, r_src);
1198 break;
1199 case 0xa:
1200 gen_op_eval_bg(r_dst, r_src);
1201 break;
1202 case 0xb:
1203 gen_op_eval_bge(r_dst, r_src);
1204 break;
1205 case 0xc:
1206 gen_op_eval_bgu(r_dst, r_src);
1207 break;
1208 case 0xd:
1209 gen_op_eval_bcc(r_dst, r_src);
1210 break;
1211 case 0xe:
1212 gen_op_eval_bpos(r_dst, r_src);
1213 break;
1214 case 0xf:
1215 gen_op_eval_bvc(r_dst, r_src);
1216 break;
1217 }
19f329ad
BS		 1218 break;
1219 }
1220}
7a3f1944 1221
416fcaea 1222static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1223{
19f329ad 1224 unsigned int offset;
416fcaea
RH		 1225 TCGv r_dst;
1226
1227 /* For now we still generate a straight boolean result. */
1228 cmp->cond = TCG_COND_NE;
1229 cmp->is_bool = true;
1230 cmp->g1 = cmp->g2 = false;
1231 cmp->c1 = r_dst = tcg_temp_new();
1232 cmp->c2 = tcg_const_tl(0);
19f329ad 1233
19f329ad
BS		 1234 switch (cc) {
1235 default:
1236 case 0x0:
1237 offset = 0;
1238 break;
1239 case 0x1:
1240 offset = 32 - 10;
1241 break;
1242 case 0x2:
1243 offset = 34 - 10;
1244 break;
1245 case 0x3:
1246 offset = 36 - 10;
1247 break;
1248 }
1249
1250 switch (cond) {
1251 case 0x0:
1252 gen_op_eval_bn(r_dst);
1253 break;
1254 case 0x1:
87e92502 1255 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1256 break;
1257 case 0x2:
87e92502 1258 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1259 break;
1260 case 0x3:
87e92502 1261 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1262 break;
1263 case 0x4:
87e92502 1264 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1265 break;
1266 case 0x5:
87e92502 1267 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1268 break;
1269 case 0x6:
87e92502 1270 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1271 break;
1272 case 0x7:
87e92502 1273 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1274 break;
1275 case 0x8:
1276 gen_op_eval_ba(r_dst);
1277 break;
1278 case 0x9:
87e92502 1279 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1280 break;
1281 case 0xa:
87e92502 1282 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1283 break;
1284 case 0xb:
87e92502 1285 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1286 break;
1287 case 0xc:
87e92502 1288 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1289 break;
1290 case 0xd:
87e92502 1291 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1292 break;
1293 case 0xe:
87e92502 1294 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1295 break;
1296 case 0xf:
87e92502 1297 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 }
e8af50a3 1300}
00f219bf 1301
416fcaea
RH		 1302static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1303 DisasContext *dc)
1304{
1305 DisasCompare cmp;
1306 gen_compare(&cmp, cc, cond, dc);
1307
1308 /* The interface is to return a boolean in r_dst. */
1309 if (cmp.is_bool) {
1310 tcg_gen_mov_tl(r_dst, cmp.c1);
1311 } else {
1312 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1313 }
1314
1315 free_compare(&cmp);
1316}
1317
1318static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1319{
1320 DisasCompare cmp;
1321 gen_fcompare(&cmp, cc, cond);
1322
1323 /* The interface is to return a boolean in r_dst. */
1324 if (cmp.is_bool) {
1325 tcg_gen_mov_tl(r_dst, cmp.c1);
1326 } else {
1327 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1328 }
1329
1330 free_compare(&cmp);
1331}
1332
19f329ad 1333#ifdef TARGET_SPARC64
00f219bf
BS		 1334// Inverted logic
1335static const int gen_tcg_cond_reg[8] = {
1336 -1,
1337 TCG_COND_NE,
1338 TCG_COND_GT,
1339 TCG_COND_GE,
1340 -1,
1341 TCG_COND_EQ,
1342 TCG_COND_LE,
1343 TCG_COND_LT,
1344};
19f329ad 1345
416fcaea
RH		 1346static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1347{
1348 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1349 cmp->is_bool = false;
1350 cmp->g1 = true;
1351 cmp->g2 = false;
1352 cmp->c1 = r_src;
1353 cmp->c2 = tcg_const_tl(0);
1354}
1355
4af984a7 1356static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1357{
416fcaea
RH		 1358 DisasCompare cmp;
1359 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1360
416fcaea
RH		 1361 /* The interface is to return a boolean in r_dst. */
1362 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1363
1364 free_compare(&cmp);
19f329ad 1365}
3475187d 1366#endif
cf495bcf 1367
d4a288ef 1368static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1369{
cf495bcf 1370 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1371 target_ulong target = dc->pc + offset;
5fafdf24 1372
22036a49
AT		 1373#ifdef TARGET_SPARC64
1374 if (unlikely(AM_CHECK(dc))) {
1375 target &= 0xffffffffULL;
1376 }
1377#endif
cf495bcf 1378 if (cond == 0x0) {
0f8a249a
BS		 1379 /* unconditional not taken */
1380 if (a) {
1381 dc->pc = dc->npc + 4;
1382 dc->npc = dc->pc + 4;
1383 } else {
1384 dc->pc = dc->npc;
1385 dc->npc = dc->pc + 4;
1386 }
cf495bcf 1387 } else if (cond == 0x8) {
0f8a249a
BS		 1388 /* unconditional taken */
1389 if (a) {
1390 dc->pc = target;
1391 dc->npc = dc->pc + 4;
1392 } else {
1393 dc->pc = dc->npc;
1394 dc->npc = target;
c27e2752 1395 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1396 }
cf495bcf 1397 } else {
dee8913c 1398 flush_cond(dc);
d4a288ef 1399 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1400 if (a) {
d4a288ef 1401 gen_branch_a(dc, target, dc->npc, cpu_cond);
cf495bcf 1402 dc->is_br = 1;
0f8a249a 1403 } else {
cf495bcf 1404 dc->pc = dc->npc;
72cbca10 1405 dc->jump_pc[0] = target;
548f66db
AT		 1406 if (unlikely(dc->npc == DYNAMIC_PC)) {
1407 dc->jump_pc[1] = DYNAMIC_PC;
1408 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1409 } else {
1410 dc->jump_pc[1] = dc->npc + 4;
1411 dc->npc = JUMP_PC;
1412 }
0f8a249a 1413 }
cf495bcf 1414 }
7a3f1944
FB		 1415}
1416
d4a288ef 1417static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1418{
1419 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1420 target_ulong target = dc->pc + offset;
1421
22036a49
AT		 1422#ifdef TARGET_SPARC64
1423 if (unlikely(AM_CHECK(dc))) {
1424 target &= 0xffffffffULL;
1425 }
1426#endif
e8af50a3 1427 if (cond == 0x0) {
0f8a249a
BS		 1428 /* unconditional not taken */
1429 if (a) {
1430 dc->pc = dc->npc + 4;
1431 dc->npc = dc->pc + 4;
1432 } else {
1433 dc->pc = dc->npc;
1434 dc->npc = dc->pc + 4;
1435 }
e8af50a3 1436 } else if (cond == 0x8) {
0f8a249a
BS		 1437 /* unconditional taken */
1438 if (a) {
1439 dc->pc = target;
1440 dc->npc = dc->pc + 4;
1441 } else {
1442 dc->pc = dc->npc;
1443 dc->npc = target;
c27e2752 1444 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1445 }
e8af50a3 1446 } else {
dee8913c 1447 flush_cond(dc);
d4a288ef 1448 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1449 if (a) {
d4a288ef 1450 gen_branch_a(dc, target, dc->npc, cpu_cond);
e8af50a3 1451 dc->is_br = 1;
0f8a249a 1452 } else {
e8af50a3
FB		 1453 dc->pc = dc->npc;
1454 dc->jump_pc[0] = target;
548f66db
AT		 1455 if (unlikely(dc->npc == DYNAMIC_PC)) {
1456 dc->jump_pc[1] = DYNAMIC_PC;
1457 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1458 } else {
1459 dc->jump_pc[1] = dc->npc + 4;
1460 dc->npc = JUMP_PC;
1461 }
0f8a249a 1462 }
e8af50a3
FB		 1463 }
1464}
1465
3475187d 1466#ifdef TARGET_SPARC64
4af984a7 1467static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1468 TCGv r_reg)
7a3f1944 1469{
3475187d
FB		 1470 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1471 target_ulong target = dc->pc + offset;
1472
22036a49
AT		 1473 if (unlikely(AM_CHECK(dc))) {
1474 target &= 0xffffffffULL;
1475 }
dee8913c 1476 flush_cond(dc);
d4a288ef 1477 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1478 if (a) {
d4a288ef 1479 gen_branch_a(dc, target, dc->npc, cpu_cond);
0f8a249a 1480 dc->is_br = 1;
3475187d 1481 } else {
0f8a249a
BS		 1482 dc->pc = dc->npc;
1483 dc->jump_pc[0] = target;
548f66db
AT		 1484 if (unlikely(dc->npc == DYNAMIC_PC)) {
1485 dc->jump_pc[1] = DYNAMIC_PC;
1486 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1487 } else {
1488 dc->jump_pc[1] = dc->npc + 4;
1489 dc->npc = JUMP_PC;
1490 }
3475187d 1491 }
7a3f1944
FB		 1492}
1493
a7812ae4 1494static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1495{
714547bb
BS		 1496 switch (fccno) {
1497 case 0:
2e2f4ade 1498 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1499 break;
1500 case 1:
2e2f4ade 1501 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1502 break;
1503 case 2:
2e2f4ade 1504 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1505 break;
1506 case 3:
2e2f4ade 1507 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1508 break;
1509 }
7e8c2b6c
BS		 1510}
1511
03fb8cfc 1512static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1513{
a7812ae4
PB		 1514 switch (fccno) {
1515 case 0:
03fb8cfc 1516 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1517 break;
1518 case 1:
03fb8cfc 1519 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1520 break;
1521 case 2:
03fb8cfc 1522 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1523 break;
1524 case 3:
03fb8cfc 1525 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1526 break;
1527 }
7e8c2b6c
BS		 1528}
1529
7e8c2b6c
BS		 1530static inline void gen_op_fcmpq(int fccno)
1531{
a7812ae4
PB		 1532 switch (fccno) {
1533 case 0:
2e2f4ade 1534 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1535 break;
1536 case 1:
2e2f4ade 1537 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1538 break;
1539 case 2:
2e2f4ade 1540 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1541 break;
1542 case 3:
2e2f4ade 1543 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1544 break;
1545 }
7e8c2b6c 1546}
7e8c2b6c 1547
a7812ae4 1548static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1549{
714547bb
BS		 1550 switch (fccno) {
1551 case 0:
2e2f4ade 1552 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1553 break;
1554 case 1:
2e2f4ade 1555 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1556 break;
1557 case 2:
2e2f4ade 1558 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1559 break;
1560 case 3:
2e2f4ade 1561 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1562 break;
1563 }
7e8c2b6c
BS		 1564}
1565
03fb8cfc 1566static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1567{
a7812ae4
PB		 1568 switch (fccno) {
1569 case 0:
03fb8cfc 1570 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1571 break;
1572 case 1:
03fb8cfc 1573 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1574 break;
1575 case 2:
03fb8cfc 1576 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1577 break;
1578 case 3:
03fb8cfc 1579 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1580 break;
1581 }
7e8c2b6c
BS		 1582}
1583
7e8c2b6c
BS		 1584static inline void gen_op_fcmpeq(int fccno)
1585{
a7812ae4
PB		 1586 switch (fccno) {
1587 case 0:
2e2f4ade 1588 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1589 break;
1590 case 1:
2e2f4ade 1591 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1592 break;
1593 case 2:
2e2f4ade 1594 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1595 break;
1596 case 3:
2e2f4ade 1597 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1598 break;
1599 }
7e8c2b6c 1600}
7e8c2b6c
BS		 1601
1602#else
1603
714547bb 1604static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1605{
2e2f4ade 1606 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1607}
1608
03fb8cfc 1609static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1610{
03fb8cfc 1611 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1612}
1613
7e8c2b6c
BS		 1614static inline void gen_op_fcmpq(int fccno)
1615{
2e2f4ade 1616 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1617}
7e8c2b6c 1618
714547bb 1619static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1620{
2e2f4ade 1621 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1622}
1623
03fb8cfc 1624static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1625{
03fb8cfc 1626 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1627}
1628
7e8c2b6c
BS		 1629static inline void gen_op_fcmpeq(int fccno)
1630{
2e2f4ade 1631 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1632}
1633#endif
1634
134d77a1
BS		 1635static inline void gen_op_fpexception_im(int fsr_flags)
1636{
a7812ae4 1637 TCGv_i32 r_const;
2ea815ca 1638
47ad35f1 1639 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1640 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1641 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1642 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1643 tcg_temp_free_i32(r_const);
134d77a1
BS		 1644}
1645
5b12f1e8 1646static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1647{
1648#if !defined(CONFIG_USER_ONLY)
1649 if (!dc->fpu_enabled) {
a7812ae4 1650 TCGv_i32 r_const;
2ea815ca 1651
66442b07 1652 save_state(dc);
2ea815ca 1653 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1654 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1655 tcg_temp_free_i32(r_const);
a80dde08
FB		 1656 dc->is_br = 1;
1657 return 1;
1658 }
1659#endif
1660 return 0;
1661}
1662
7e8c2b6c
BS		 1663static inline void gen_op_clear_ieee_excp_and_FTT(void)
1664{
47ad35f1 1665 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1666}
1667
61f17f6e
RH		 1668static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1669 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1670{
1671 TCGv_i32 dst, src;
1672
61f17f6e 1673 src = gen_load_fpr_F(dc, rs);
ba5f5179 1674 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1675
1676 gen(dst, cpu_env, src);
1677
61f17f6e
RH		 1678 gen_store_fpr_F(dc, rd, dst);
1679}
1680
1681static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1682 void (*gen)(TCGv_i32, TCGv_i32))
1683{
1684 TCGv_i32 dst, src;
1685
1686 src = gen_load_fpr_F(dc, rs);
ba5f5179 1687 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1688
1689 gen(dst, src);
1690
1691 gen_store_fpr_F(dc, rd, dst);
1692}
1693
1694static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1695 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1696{
1697 TCGv_i32 dst, src1, src2;
1698
61f17f6e
RH		 1699 src1 = gen_load_fpr_F(dc, rs1);
1700 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1701 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1702
1703 gen(dst, cpu_env, src1, src2);
1704
61f17f6e
RH		 1705 gen_store_fpr_F(dc, rd, dst);
1706}
1707
1708#ifdef TARGET_SPARC64
1709static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1710 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1711{
1712 TCGv_i32 dst, src1, src2;
1713
1714 src1 = gen_load_fpr_F(dc, rs1);
1715 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1716 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1717
1718 gen(dst, src1, src2);
1719
1720 gen_store_fpr_F(dc, rd, dst);
1721}
1722#endif
1723
1724static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1725 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1726{
1727 TCGv_i64 dst, src;
1728
61f17f6e 1729 src = gen_load_fpr_D(dc, rs);
3886b8a3 1730 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1731
1732 gen(dst, cpu_env, src);
1733
61f17f6e
RH		 1734 gen_store_fpr_D(dc, rd, dst);
1735}
1736
1737#ifdef TARGET_SPARC64
1738static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1739 void (*gen)(TCGv_i64, TCGv_i64))
1740{
1741 TCGv_i64 dst, src;
1742
1743 src = gen_load_fpr_D(dc, rs);
3886b8a3 1744 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1745
1746 gen(dst, src);
1747
1748 gen_store_fpr_D(dc, rd, dst);
1749}
1750#endif
1751
1752static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1753 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1754{
1755 TCGv_i64 dst, src1, src2;
1756
61f17f6e
RH		 1757 src1 = gen_load_fpr_D(dc, rs1);
1758 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1759 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1760
1761 gen(dst, cpu_env, src1, src2);
1762
61f17f6e
RH		 1763 gen_store_fpr_D(dc, rd, dst);
1764}
1765
1766#ifdef TARGET_SPARC64
1767static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1768 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1769{
1770 TCGv_i64 dst, src1, src2;
1771
1772 src1 = gen_load_fpr_D(dc, rs1);
1773 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1774 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1775
1776 gen(dst, src1, src2);
1777
1778 gen_store_fpr_D(dc, rd, dst);
1779}
f888300b 1780
2dedf314
RH		 1781static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1782 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1783{
1784 TCGv_i64 dst, src1, src2;
1785
1786 src1 = gen_load_fpr_D(dc, rs1);
1787 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1788 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1789
1790 gen(dst, cpu_gsr, src1, src2);
1791
1792 gen_store_fpr_D(dc, rd, dst);
1793}
1794
f888300b
RH		 1795static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1796 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1797{
1798 TCGv_i64 dst, src0, src1, src2;
1799
1800 src1 = gen_load_fpr_D(dc, rs1);
1801 src2 = gen_load_fpr_D(dc, rs2);
1802 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1803 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1804
1805 gen(dst, src0, src1, src2);
1806
1807 gen_store_fpr_D(dc, rd, dst);
1808}
61f17f6e
RH		 1809#endif
1810
1811static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1812 void (*gen)(TCGv_ptr))
1813{
61f17f6e
RH		 1814 gen_op_load_fpr_QT1(QFPREG(rs));
1815
1816 gen(cpu_env);
1817
61f17f6e
RH		 1818 gen_op_store_QT0_fpr(QFPREG(rd));
1819 gen_update_fprs_dirty(QFPREG(rd));
1820}
1821
1822#ifdef TARGET_SPARC64
1823static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1824 void (*gen)(TCGv_ptr))
1825{
1826 gen_op_load_fpr_QT1(QFPREG(rs));
1827
1828 gen(cpu_env);
1829
1830 gen_op_store_QT0_fpr(QFPREG(rd));
1831 gen_update_fprs_dirty(QFPREG(rd));
1832}
1833#endif
1834
1835static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1836 void (*gen)(TCGv_ptr))
1837{
61f17f6e
RH		 1838 gen_op_load_fpr_QT0(QFPREG(rs1));
1839 gen_op_load_fpr_QT1(QFPREG(rs2));
1840
1841 gen(cpu_env);
1842
61f17f6e
RH		 1843 gen_op_store_QT0_fpr(QFPREG(rd));
1844 gen_update_fprs_dirty(QFPREG(rd));
1845}
1846
1847static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1848 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1849{
1850 TCGv_i64 dst;
1851 TCGv_i32 src1, src2;
1852
61f17f6e
RH		 1853 src1 = gen_load_fpr_F(dc, rs1);
1854 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1855 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1856
1857 gen(dst, cpu_env, src1, src2);
1858
61f17f6e
RH		 1859 gen_store_fpr_D(dc, rd, dst);
1860}
1861
1862static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1863 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1864{
1865 TCGv_i64 src1, src2;
1866
61f17f6e
RH		 1867 src1 = gen_load_fpr_D(dc, rs1);
1868 src2 = gen_load_fpr_D(dc, rs2);
1869
1870 gen(cpu_env, src1, src2);
1871
61f17f6e
RH		 1872 gen_op_store_QT0_fpr(QFPREG(rd));
1873 gen_update_fprs_dirty(QFPREG(rd));
1874}
1875
1876#ifdef TARGET_SPARC64
1877static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1878 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1879{
1880 TCGv_i64 dst;
1881 TCGv_i32 src;
1882
61f17f6e 1883 src = gen_load_fpr_F(dc, rs);
3886b8a3 1884 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1885
1886 gen(dst, cpu_env, src);
1887
61f17f6e
RH		 1888 gen_store_fpr_D(dc, rd, dst);
1889}
1890#endif
1891
1892static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1893 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1894{
1895 TCGv_i64 dst;
1896 TCGv_i32 src;
1897
1898 src = gen_load_fpr_F(dc, rs);
3886b8a3 1899 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1900
1901 gen(dst, cpu_env, src);
1902
1903 gen_store_fpr_D(dc, rd, dst);
1904}
1905
1906static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1907 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1908{
1909 TCGv_i32 dst;
1910 TCGv_i64 src;
1911
61f17f6e 1912 src = gen_load_fpr_D(dc, rs);
ba5f5179 1913 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1914
1915 gen(dst, cpu_env, src);
1916
61f17f6e
RH		 1917 gen_store_fpr_F(dc, rd, dst);
1918}
1919
1920static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1921 void (*gen)(TCGv_i32, TCGv_ptr))
1922{
1923 TCGv_i32 dst;
1924
61f17f6e 1925 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1926 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1927
1928 gen(dst, cpu_env);
1929
61f17f6e
RH		 1930 gen_store_fpr_F(dc, rd, dst);
1931}
1932
1933static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1934 void (*gen)(TCGv_i64, TCGv_ptr))
1935{
1936 TCGv_i64 dst;
1937
61f17f6e 1938 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1939 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1940
1941 gen(dst, cpu_env);
1942
61f17f6e
RH		 1943 gen_store_fpr_D(dc, rd, dst);
1944}
1945
1946static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1947 void (*gen)(TCGv_ptr, TCGv_i32))
1948{
1949 TCGv_i32 src;
1950
1951 src = gen_load_fpr_F(dc, rs);
1952
1953 gen(cpu_env, src);
1954
1955 gen_op_store_QT0_fpr(QFPREG(rd));
1956 gen_update_fprs_dirty(QFPREG(rd));
1957}
1958
1959static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1960 void (*gen)(TCGv_ptr, TCGv_i64))
1961{
1962 TCGv_i64 src;
1963
1964 src = gen_load_fpr_D(dc, rs);
1965
1966 gen(cpu_env, src);
1967
1968 gen_op_store_QT0_fpr(QFPREG(rd));
1969 gen_update_fprs_dirty(QFPREG(rd));
1970}
1971
1a2fb1c0
BS		 1972/* asi moves */
1973#ifdef TARGET_SPARC64
a7812ae4 1974static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1975{
95f9397c 1976 int asi;
a7812ae4 1977 TCGv_i32 r_asi;
1a2fb1c0 1978
1a2fb1c0 1979 if (IS_IMM) {
a7812ae4 1980 r_asi = tcg_temp_new_i32();
255e1fcb 1981 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1982 } else {
1983 asi = GET_FIELD(insn, 19, 26);
0425bee5 1984 r_asi = tcg_const_i32(asi);
1a2fb1c0 1985 }
0425bee5
BS		 1986 return r_asi;
1987}
1988
77f193da
BS		 1989static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1990 int sign)
0425bee5 1991{
a7812ae4 1992 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1993
4af984a7 1994 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1995 r_size = tcg_const_i32(size);
1996 r_sign = tcg_const_i32(sign);
fe8d8f0f 1997 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4
PB		 1998 tcg_temp_free_i32(r_sign);
1999 tcg_temp_free_i32(r_size);
2000 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2001}
2002
4af984a7 2003static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2004{
a7812ae4 2005 TCGv_i32 r_asi, r_size;
1a2fb1c0 2006
4af984a7 2007 r_asi = gen_get_asi(insn, addr);
2ea815ca 2008 r_size = tcg_const_i32(size);
fe8d8f0f 2009 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2010 tcg_temp_free_i32(r_size);
2011 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2012}
2013
4af984a7 2014static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2015{
a7812ae4 2016 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2017
4af984a7 2018 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2019 r_size = tcg_const_i32(size);
2020 r_rd = tcg_const_i32(rd);
fe8d8f0f 2021 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2022 tcg_temp_free_i32(r_rd);
2023 tcg_temp_free_i32(r_size);
2024 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2025}
2026
4af984a7 2027static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2028{
a7812ae4 2029 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2030
31741a27 2031 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2032 r_size = tcg_const_i32(size);
2033 r_rd = tcg_const_i32(rd);
fe8d8f0f 2034 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2035 tcg_temp_free_i32(r_rd);
2036 tcg_temp_free_i32(r_size);
2037 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2038}
2039
06828032 2040static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2041{
a7812ae4 2042 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2043 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2044
4af984a7 2045 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2046 r_size = tcg_const_i32(4);
2047 r_sign = tcg_const_i32(0);
1ec789ab 2048 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4 2049 tcg_temp_free_i32(r_sign);
06828032 2050 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2051 tcg_temp_free_i32(r_size);
2052 tcg_temp_free_i32(r_asi);
1ec789ab
RH		 2053 tcg_gen_trunc_i64_tl(dst, t64);
2054 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2055}
2056
c7785e16
RH		 2057static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2058 int insn, int rd)
1a2fb1c0 2059{
a7812ae4 2060 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2061
4af984a7 2062 r_asi = gen_get_asi(insn, addr);
db166940 2063 r_rd = tcg_const_i32(rd);
fe8d8f0f 2064 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2065 tcg_temp_free_i32(r_rd);
2066 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2067}
2068
c7785e16
RH		 2069static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2070 int insn, int rd)
0425bee5 2071{
a7812ae4 2072 TCGv_i32 r_asi, r_size;
c7785e16 2073 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2074 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2075
1ec789ab 2076 tcg_gen_concat_tl_i64(t64, lo, hi);
4af984a7 2077 r_asi = gen_get_asi(insn, addr);
2ea815ca 2078 r_size = tcg_const_i32(8);
1ec789ab 2079 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2080 tcg_temp_free_i32(r_size);
2081 tcg_temp_free_i32(r_asi);
1ec789ab 2082 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2083}
2084
81634eea 2085static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
c7785e16 2086 TCGv val2, int insn, int rd)
1a2fb1c0 2087{
81634eea
RH		 2088 TCGv val1 = gen_load_gpr(dc, rd);
2089 TCGv dst = gen_dest_gpr(dc, rd);
c7785e16 2090 TCGv_i32 r_asi = gen_get_asi(insn, addr);
1a2fb1c0 2091
81634eea 2092 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2093 tcg_temp_free_i32(r_asi);
81634eea 2094 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2095}
2096
2097#elif !defined(CONFIG_USER_ONLY)
2098
77f193da
BS		 2099static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2100 int sign)
1a2fb1c0 2101{
a7812ae4 2102 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2103 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2104
2ea815ca
BS		 2105 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2106 r_size = tcg_const_i32(size);
2107 r_sign = tcg_const_i32(sign);
1ec789ab
RH		 2108 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2109 tcg_temp_free_i32(r_sign);
2110 tcg_temp_free_i32(r_size);
2111 tcg_temp_free_i32(r_asi);
2112 tcg_gen_trunc_i64_tl(dst, t64);
2113 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2114}
2115
4af984a7 2116static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2117{
a7812ae4 2118 TCGv_i32 r_asi, r_size;
1ec789ab 2119 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2120
1ec789ab 2121 tcg_gen_extu_tl_i64(t64, src);
2ea815ca
BS		 2122 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2123 r_size = tcg_const_i32(size);
1ec789ab
RH		 2124 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2125 tcg_temp_free_i32(r_size);
2126 tcg_temp_free_i32(r_asi);
2127 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2128}
2129
06828032 2130static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2131{
a7812ae4 2132 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2133 TCGv_i64 r_val, t64;
1a2fb1c0 2134
2ea815ca
BS		 2135 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2136 r_size = tcg_const_i32(4);
2137 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2138 t64 = tcg_temp_new_i64();
2139 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2ea815ca 2140 tcg_temp_free(r_sign);
a7812ae4 2141 r_val = tcg_temp_new_i64();
06828032 2142 tcg_gen_extu_tl_i64(r_val, src);
fe8d8f0f 2143 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4 2144 tcg_temp_free_i64(r_val);
1ec789ab
RH		 2145 tcg_temp_free_i32(r_size);
2146 tcg_temp_free_i32(r_asi);
2147 tcg_gen_trunc_i64_tl(dst, t64);
2148 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2149}
2150
c7785e16
RH		 2151static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2152 int insn, int rd)
1a2fb1c0 2153{
a7812ae4 2154 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2155 TCGv t;
1ec789ab 2156 TCGv_i64 t64;
1a2fb1c0 2157
2ea815ca
BS		 2158 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2159 r_size = tcg_const_i32(8);
2160 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2161 t64 = tcg_temp_new_i64();
2162 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2163 tcg_temp_free_i32(r_sign);
2164 tcg_temp_free_i32(r_size);
2165 tcg_temp_free_i32(r_asi);
c7785e16
RH		 2166
2167 t = gen_dest_gpr(dc, rd + 1);
1ec789ab 2168 tcg_gen_trunc_i64_tl(t, t64);
c7785e16
RH		 2169 gen_store_gpr(dc, rd + 1, t);
2170
1ec789ab
RH		 2171 tcg_gen_shri_i64(t64, t64, 32);
2172 tcg_gen_trunc_i64_tl(hi, t64);
2173 tcg_temp_free_i64(t64);
c7785e16 2174 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2175}
2176
c7785e16
RH		 2177static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2178 int insn, int rd)
0425bee5 2179{
a7812ae4 2180 TCGv_i32 r_asi, r_size;
c7785e16 2181 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2182 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2183
1ec789ab 2184 tcg_gen_concat_tl_i64(t64, lo, hi);
2ea815ca
BS		 2185 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2186 r_size = tcg_const_i32(8);
1ec789ab
RH		 2187 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2188 tcg_temp_free_i32(r_size);
2189 tcg_temp_free_i32(r_asi);
2190 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2191}
2192#endif
2193
2194#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
16c358e9
SH		 2195static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2196 TCGv val2, int insn, int rd)
2197{
2198 TCGv val1 = gen_load_gpr(dc, rd);
2199 TCGv dst = gen_dest_gpr(dc, rd);
2200#ifdef TARGET_SPARC64
2201 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2202#else
2203 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2204#endif
2205
2206 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2207 tcg_temp_free_i32(r_asi);
2208 gen_store_gpr(dc, rd, dst);
2209}
2210
4af984a7 2211static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2212{
a7812ae4
PB		 2213 TCGv_i64 r_val;
2214 TCGv_i32 r_asi, r_size;
1a2fb1c0 2215
4af984a7 2216 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2217
2ea815ca
BS		 2218 r_val = tcg_const_i64(0xffULL);
2219 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2220 r_size = tcg_const_i32(1);
fe8d8f0f 2221 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4
PB		 2222 tcg_temp_free_i32(r_size);
2223 tcg_temp_free_i32(r_asi);
2224 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2225}
2226#endif
2227
9d1d4e34 2228static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2229{
9d1d4e34
RH		 2230 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2231 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2232}
2233
9d1d4e34 2234static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2235{
a49d9390 2236 if (IS_IMM) { /* immediate */
42a8aa83 2237 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2238 TCGv t = get_temp_tl(dc);
2239 tcg_gen_movi_tl(t, simm);
2240 return t;
2241 } else { /* register */
42a8aa83 2242 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2243 return gen_load_gpr(dc, rs2);
a49d9390 2244 }
a49d9390
BS		 2245}
2246
8194f35a 2247#ifdef TARGET_SPARC64
7e480893
RH		 2248static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2249{
2250 TCGv_i32 c32, zero, dst, s1, s2;
2251
2252 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2253 or fold the comparison down to 32 bits and use movcond_i32. Choose
2254 the later. */
2255 c32 = tcg_temp_new_i32();
2256 if (cmp->is_bool) {
ecc7b3aa 2257 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2258 } else {
2259 TCGv_i64 c64 = tcg_temp_new_i64();
2260 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2261 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2262 tcg_temp_free_i64(c64);
2263 }
2264
2265 s1 = gen_load_fpr_F(dc, rs);
2266 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2267 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2268 zero = tcg_const_i32(0);
2269
2270 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2271
2272 tcg_temp_free_i32(c32);
2273 tcg_temp_free_i32(zero);
2274 gen_store_fpr_F(dc, rd, dst);
2275}
2276
2277static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2278{
3886b8a3 2279 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2280 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2281 gen_load_fpr_D(dc, rs),
2282 gen_load_fpr_D(dc, rd));
2283 gen_store_fpr_D(dc, rd, dst);
2284}
2285
2286static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2287{
2288 int qd = QFPREG(rd);
2289 int qs = QFPREG(rs);
2290
2291 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2292 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2293 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2294 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2295
2296 gen_update_fprs_dirty(qd);
2297}
2298
a2035e83 2299#ifndef CONFIG_USER_ONLY
8194f35a
IK		 2300static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2301{
b551ec04 2302 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2303
2304 /* load env->tl into r_tl */
b551ec04 2305 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2306
2307 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2308 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2309
2310 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2311 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2312 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2313
2314 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2315 {
2316 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2317 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2318 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2319 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2320 }
8194f35a 2321
b551ec04 2322 tcg_temp_free_i32(r_tl);
8194f35a 2323}
a2035e83 2324#endif
6c073553
RH		 2325
2326static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2327 int width, bool cc, bool left)
2328{
2329 TCGv lo1, lo2, t1, t2;
2330 uint64_t amask, tabl, tabr;
2331 int shift, imask, omask;
2332
2333 if (cc) {
2334 tcg_gen_mov_tl(cpu_cc_src, s1);
2335 tcg_gen_mov_tl(cpu_cc_src2, s2);
2336 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2337 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2338 dc->cc_op = CC_OP_SUB;
2339 }
2340
2341 /* Theory of operation: there are two tables, left and right (not to
2342 be confused with the left and right versions of the opcode). These
2343 are indexed by the low 3 bits of the inputs. To make things "easy",
2344 these tables are loaded into two constants, TABL and TABR below.
2345 The operation index = (input & imask) << shift calculates the index
2346 into the constant, while val = (table >> index) & omask calculates
2347 the value we're looking for. */
2348 switch (width) {
2349 case 8:
2350 imask = 0x7;
2351 shift = 3;
2352 omask = 0xff;
2353 if (left) {
2354 tabl = 0x80c0e0f0f8fcfeffULL;
2355 tabr = 0xff7f3f1f0f070301ULL;
2356 } else {
2357 tabl = 0x0103070f1f3f7fffULL;
2358 tabr = 0xfffefcf8f0e0c080ULL;
2359 }
2360 break;
2361 case 16:
2362 imask = 0x6;
2363 shift = 1;
2364 omask = 0xf;
2365 if (left) {
2366 tabl = 0x8cef;
2367 tabr = 0xf731;
2368 } else {
2369 tabl = 0x137f;
2370 tabr = 0xfec8;
2371 }
2372 break;
2373 case 32:
2374 imask = 0x4;
2375 shift = 0;
2376 omask = 0x3;
2377 if (left) {
2378 tabl = (2 << 2) | 3;
2379 tabr = (3 << 2) | 1;
2380 } else {
2381 tabl = (1 << 2) | 3;
2382 tabr = (3 << 2) | 2;
2383 }
2384 break;
2385 default:
2386 abort();
2387 }
2388
2389 lo1 = tcg_temp_new();
2390 lo2 = tcg_temp_new();
2391 tcg_gen_andi_tl(lo1, s1, imask);
2392 tcg_gen_andi_tl(lo2, s2, imask);
2393 tcg_gen_shli_tl(lo1, lo1, shift);
2394 tcg_gen_shli_tl(lo2, lo2, shift);
2395
2396 t1 = tcg_const_tl(tabl);
2397 t2 = tcg_const_tl(tabr);
2398 tcg_gen_shr_tl(lo1, t1, lo1);
2399 tcg_gen_shr_tl(lo2, t2, lo2);
2400 tcg_gen_andi_tl(dst, lo1, omask);
2401 tcg_gen_andi_tl(lo2, lo2, omask);
2402
2403 amask = -8;
2404 if (AM_CHECK(dc)) {
2405 amask &= 0xffffffffULL;
2406 }
2407 tcg_gen_andi_tl(s1, s1, amask);
2408 tcg_gen_andi_tl(s2, s2, amask);
2409
2410 /* We want to compute
2411 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2412 We've already done dst = lo1, so this reduces to
2413 dst &= (s1 == s2 ? -1 : lo2)
2414 Which we perform by
2415 lo2 |= -(s1 == s2)
2416 dst &= lo2
2417 */
2418 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2419 tcg_gen_neg_tl(t1, t1);
2420 tcg_gen_or_tl(lo2, lo2, t1);
2421 tcg_gen_and_tl(dst, dst, lo2);
2422
2423 tcg_temp_free(lo1);
2424 tcg_temp_free(lo2);
2425 tcg_temp_free(t1);
2426 tcg_temp_free(t2);
2427}
add545ab
RH		 2428
2429static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2430{
2431 TCGv tmp = tcg_temp_new();
2432
2433 tcg_gen_add_tl(tmp, s1, s2);
2434 tcg_gen_andi_tl(dst, tmp, -8);
2435 if (left) {
2436 tcg_gen_neg_tl(tmp, tmp);
2437 }
2438 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2439
2440 tcg_temp_free(tmp);
2441}
50c796f9
RH		 2442
2443static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2444{
2445 TCGv t1, t2, shift;
2446
2447 t1 = tcg_temp_new();
2448 t2 = tcg_temp_new();
2449 shift = tcg_temp_new();
2450
2451 tcg_gen_andi_tl(shift, gsr, 7);
2452 tcg_gen_shli_tl(shift, shift, 3);
2453 tcg_gen_shl_tl(t1, s1, shift);
2454
2455 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2456 shift of (up to 63) followed by a constant shift of 1. */
2457 tcg_gen_xori_tl(shift, shift, 63);
2458 tcg_gen_shr_tl(t2, s2, shift);
2459 tcg_gen_shri_tl(t2, t2, 1);
2460
2461 tcg_gen_or_tl(dst, t1, t2);
2462
2463 tcg_temp_free(t1);
2464 tcg_temp_free(t2);
2465 tcg_temp_free(shift);
2466}
8194f35a
IK		 2467#endif
2468
64a88d5d 2469#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2470 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2471 goto illegal_insn;
2472#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2473 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2474 goto nfpu_insn;
2475
0bee699e 2476/* before an instruction, dc->pc must be static */
0184e266 2477static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2478{
0184e266 2479 unsigned int opc, rs1, rs2, rd;
a4273524 2480 TCGv cpu_src1, cpu_src2;
208ae657 2481 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2482 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2483 target_long simm;
7a3f1944 2484
cf495bcf 2485 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2486 rd = GET_FIELD(insn, 2, 6);
6ae20372 2487
cf495bcf 2488 switch (opc) {
0f8a249a
BS		 2489 case 0: /* branches/sethi */
2490 {
2491 unsigned int xop = GET_FIELD(insn, 7, 9);
2492 int32_t target;
2493 switch (xop) {
3475187d 2494#ifdef TARGET_SPARC64
0f8a249a
BS		 2495 case 0x1: /* V9 BPcc */
2496 {
2497 int cc;
2498
2499 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2500 target = sign_extend(target, 19);
0f8a249a
BS		 2501 target <<= 2;
2502 cc = GET_FIELD_SP(insn, 20, 21);
2503 if (cc == 0)
d4a288ef 2504 do_branch(dc, target, insn, 0);
0f8a249a 2505 else if (cc == 2)
d4a288ef 2506 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2507 else
2508 goto illegal_insn;
2509 goto jmp_insn;
2510 }
2511 case 0x3: /* V9 BPr */
2512 {
2513 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2514 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2515 target = sign_extend(target, 16);
2516 target <<= 2;
9d1d4e34 2517 cpu_src1 = get_src1(dc, insn);
d4a288ef 2518 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2519 goto jmp_insn;
2520 }
2521 case 0x5: /* V9 FBPcc */
2522 {
2523 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2524 if (gen_trap_ifnofpu(dc)) {
a80dde08 2525 goto jmp_insn;
5b12f1e8 2526 }
0f8a249a
BS		 2527 target = GET_FIELD_SP(insn, 0, 18);
2528 target = sign_extend(target, 19);
2529 target <<= 2;
d4a288ef 2530 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2531 goto jmp_insn;
2532 }
a4d17f19 2533#else
0f8a249a
BS		 2534 case 0x7: /* CBN+x */
2535 {
2536 goto ncp_insn;
2537 }
2538#endif
2539 case 0x2: /* BN+x */
2540 {
2541 target = GET_FIELD(insn, 10, 31);
2542 target = sign_extend(target, 22);
2543 target <<= 2;
d4a288ef 2544 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2545 goto jmp_insn;
2546 }
2547 case 0x6: /* FBN+x */
2548 {
5b12f1e8 2549 if (gen_trap_ifnofpu(dc)) {
a80dde08 2550 goto jmp_insn;
5b12f1e8 2551 }
0f8a249a
BS		 2552 target = GET_FIELD(insn, 10, 31);
2553 target = sign_extend(target, 22);
2554 target <<= 2;
d4a288ef 2555 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2556 goto jmp_insn;
2557 }
2558 case 0x4: /* SETHI */
97ea2859
RH		 2559 /* Special-case %g0 because that's the canonical nop. */
2560 if (rd) {
0f8a249a 2561 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2562 TCGv t = gen_dest_gpr(dc, rd);
2563 tcg_gen_movi_tl(t, value << 10);
2564 gen_store_gpr(dc, rd, t);
0f8a249a 2565 }
0f8a249a
BS		 2566 break;
2567 case 0x0: /* UNIMPL */
2568 default:
3475187d 2569 goto illegal_insn;
0f8a249a
BS		 2570 }
2571 break;
2572 }
2573 break;
dc1a6971
BS		 2574 case 1: /*CALL*/
2575 {
0f8a249a 2576 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2577 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2578
97ea2859
RH		 2579 tcg_gen_movi_tl(o7, dc->pc);
2580 gen_store_gpr(dc, 15, o7);
0f8a249a 2581 target += dc->pc;
13a6dd00 2582 gen_mov_pc_npc(dc);
22036a49
AT		 2583#ifdef TARGET_SPARC64
2584 if (unlikely(AM_CHECK(dc))) {
2585 target &= 0xffffffffULL;
2586 }
2587#endif
0f8a249a
BS		 2588 dc->npc = target;
2589 }
2590 goto jmp_insn;
2591 case 2: /* FPU & Logical Operations */
2592 {
2593 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2594 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2595 TCGv cpu_tmp0;
5793f2a4 2596
0f8a249a 2597 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2598 int cond = GET_FIELD(insn, 3, 6);
2599 TCGv_i32 trap;
42a268c2
RH		 2600 TCGLabel *l1 = NULL;
2601 int mask;
3475187d 2602
bd49ed41
RH		 2603 if (cond == 0) {
2604 /* Trap never. */
2605 break;
cf495bcf 2606 }
b04d9890 2607
bd49ed41 2608 save_state(dc);
b04d9890 2609
bd49ed41
RH		 2610 if (cond != 8) {
2611 /* Conditional trap. */
3a49e759 2612 DisasCompare cmp;
3475187d 2613#ifdef TARGET_SPARC64
0f8a249a
BS		 2614 /* V9 icc/xcc */
2615 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2616 if (cc == 0) {
2617 gen_compare(&cmp, 0, cond, dc);
2618 } else if (cc == 2) {
2619 gen_compare(&cmp, 1, cond, dc);
2620 } else {
0f8a249a 2621 goto illegal_insn;
3a49e759 2622 }
3475187d 2623#else
3a49e759 2624 gen_compare(&cmp, 0, cond, dc);
3475187d 2625#endif
b158a785 2626 l1 = gen_new_label();
3a49e759
RH		 2627 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2628 cmp.c1, cmp.c2, l1);
2629 free_compare(&cmp);
bd49ed41 2630 }
b158a785 2631
bd49ed41
RH		 2632 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2633 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2634
2635 /* Don't use the normal temporaries, as they may well have
2636 gone out of scope with the branch above. While we're
2637 doing that we might as well pre-truncate to 32-bit. */
2638 trap = tcg_temp_new_i32();
2639
2640 rs1 = GET_FIELD_SP(insn, 14, 18);
2641 if (IS_IMM) {
2642 rs2 = GET_FIELD_SP(insn, 0, 6);
2643 if (rs1 == 0) {
2644 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2645 /* Signal that the trap value is fully constant. */
2646 mask = 0;
2647 } else {
97ea2859 2648 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2649 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2650 tcg_gen_addi_i32(trap, trap, rs2);
2651 }
2652 } else {
97ea2859 2653 TCGv t1, t2;
bd49ed41 2654 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2655 t1 = gen_load_gpr(dc, rs1);
2656 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2657 tcg_gen_add_tl(t1, t1, t2);
2658 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2659 }
2660 if (mask != 0) {
2661 tcg_gen_andi_i32(trap, trap, mask);
2662 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2663 }
2664
2665 gen_helper_raise_exception(cpu_env, trap);
2666 tcg_temp_free_i32(trap);
b158a785 2667
fe1755cb
RH		 2668 if (cond == 8) {
2669 /* An unconditional trap ends the TB. */
2670 dc->is_br = 1;
2671 goto jmp_insn;
2672 } else {
2673 /* A conditional trap falls through to the next insn. */
b158a785 2674 gen_set_label(l1);
fe1755cb 2675 break;
cf495bcf
FB		 2676 }
2677 } else if (xop == 0x28) {
2678 rs1 = GET_FIELD(insn, 13, 17);
2679 switch(rs1) {
2680 case 0: /* rdy */
65fe7b09
BS		 2681#ifndef TARGET_SPARC64
2682 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2683 manual, rdy on the microSPARC
2684 II */
2685 case 0x0f: /* stbar in the SPARCv8 manual,
2686 rdy on the microSPARC II */
2687 case 0x10 ... 0x1f: /* implementation-dependent in the
2688 SPARCv8 manual, rdy on the
2689 microSPARC II */
4a2ba232
FC		 2690 /* Read Asr17 */
2691 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2692 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2693 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2694 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2695 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2696 break;
2697 }
65fe7b09 2698#endif
97ea2859 2699 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2700 break;
3475187d 2701#ifdef TARGET_SPARC64
0f8a249a 2702 case 0x2: /* V9 rdccr */
20132b96 2703 update_psr(dc);
063c3675 2704 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2705 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2706 break;
0f8a249a 2707 case 0x3: /* V9 rdasi */
255e1fcb 2708 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
97ea2859 2709 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2710 break;
0f8a249a 2711 case 0x4: /* V9 rdtick */
ccd4a219 2712 {
a7812ae4 2713 TCGv_ptr r_tickptr;
ccd4a219 2714
a7812ae4 2715 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2716 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2717 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 2718 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2719 tcg_temp_free_ptr(r_tickptr);
97ea2859 2720 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2721 }
3475187d 2722 break;
0f8a249a 2723 case 0x5: /* V9 rdpc */
2ea815ca 2724 {
97ea2859 2725 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2726 if (unlikely(AM_CHECK(dc))) {
97ea2859 2727 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2728 } else {
97ea2859 2729 tcg_gen_movi_tl(t, dc->pc);
22036a49 2730 }
97ea2859 2731 gen_store_gpr(dc, rd, t);
2ea815ca 2732 }
0f8a249a
BS		 2733 break;
2734 case 0x6: /* V9 rdfprs */
255e1fcb 2735 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2736 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2737 break;
65fe7b09
BS		 2738 case 0xf: /* V9 membar */
2739 break; /* no effect */
0f8a249a 2740 case 0x13: /* Graphics Status */
5b12f1e8 2741 if (gen_trap_ifnofpu(dc)) {
725cb90b 2742 goto jmp_insn;
5b12f1e8 2743 }
97ea2859 2744 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2745 break;
9d926598
BS		 2746 case 0x16: /* Softint */
2747 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
97ea2859 2748 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2749 break;
0f8a249a 2750 case 0x17: /* Tick compare */
97ea2859 2751 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2752 break;
0f8a249a 2753 case 0x18: /* System tick */
ccd4a219 2754 {
a7812ae4 2755 TCGv_ptr r_tickptr;
ccd4a219 2756
a7812ae4 2757 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2758 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2759 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 2760 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2761 tcg_temp_free_ptr(r_tickptr);
97ea2859 2762 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2763 }
83469015 2764 break;
0f8a249a 2765 case 0x19: /* System tick compare */
97ea2859 2766 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2767 break;
0f8a249a
BS		 2768 case 0x10: /* Performance Control */
2769 case 0x11: /* Performance Instrumentation Counter */
2770 case 0x12: /* Dispatch Control */
2771 case 0x14: /* Softint set, WO */
2772 case 0x15: /* Softint clear, WO */
3475187d
FB		 2773#endif
2774 default:
cf495bcf
FB		 2775 goto illegal_insn;
2776 }
e8af50a3 2777#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2778 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2779#ifndef TARGET_SPARC64
20132b96 2780 if (!supervisor(dc)) {
0f8a249a 2781 goto priv_insn;
20132b96
RH		 2782 }
2783 update_psr(dc);
063c3675 2784 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2785#else
fb79ceb9 2786 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2787 if (!hypervisor(dc))
2788 goto priv_insn;
2789 rs1 = GET_FIELD(insn, 13, 17);
2790 switch (rs1) {
2791 case 0: // hpstate
2792 // gen_op_rdhpstate();
2793 break;
2794 case 1: // htstate
2795 // gen_op_rdhtstate();
2796 break;
2797 case 3: // hintp
255e1fcb 2798 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2799 break;
2800 case 5: // htba
255e1fcb 2801 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2802 break;
2803 case 6: // hver
255e1fcb 2804 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2805 break;
2806 case 31: // hstick_cmpr
255e1fcb 2807 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2808 break;
2809 default:
2810 goto illegal_insn;
2811 }
2812#endif
97ea2859 2813 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2814 break;
3475187d 2815 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2816 if (!supervisor(dc)) {
0f8a249a 2817 goto priv_insn;
de9e9d9f
RH		 2818 }
2819 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2820#ifdef TARGET_SPARC64
2821 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2822 switch (rs1) {
2823 case 0: // tpc
375ee38b 2824 {
a7812ae4 2825 TCGv_ptr r_tsptr;
375ee38b 2826
a7812ae4 2827 r_tsptr = tcg_temp_new_ptr();
8194f35a 2828 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2829 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2830 offsetof(trap_state, tpc));
a7812ae4 2831 tcg_temp_free_ptr(r_tsptr);
375ee38b 2832 }
0f8a249a
BS		 2833 break;
2834 case 1: // tnpc
375ee38b 2835 {
a7812ae4 2836 TCGv_ptr r_tsptr;
375ee38b 2837
a7812ae4 2838 r_tsptr = tcg_temp_new_ptr();
8194f35a 2839 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2840 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2841 offsetof(trap_state, tnpc));
a7812ae4 2842 tcg_temp_free_ptr(r_tsptr);
375ee38b 2843 }
0f8a249a
BS		 2844 break;
2845 case 2: // tstate
375ee38b 2846 {
a7812ae4 2847 TCGv_ptr r_tsptr;
375ee38b 2848
a7812ae4 2849 r_tsptr = tcg_temp_new_ptr();
8194f35a 2850 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2851 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2852 offsetof(trap_state, tstate));
a7812ae4 2853 tcg_temp_free_ptr(r_tsptr);
375ee38b 2854 }
0f8a249a
BS		 2855 break;
2856 case 3: // tt
375ee38b 2857 {
45778f99 2858 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2859
8194f35a 2860 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2861 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2862 offsetof(trap_state, tt));
a7812ae4 2863 tcg_temp_free_ptr(r_tsptr);
375ee38b 2864 }
0f8a249a
BS		 2865 break;
2866 case 4: // tick
ccd4a219 2867 {
a7812ae4 2868 TCGv_ptr r_tickptr;
ccd4a219 2869
a7812ae4 2870 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2871 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2872 offsetof(CPUSPARCState, tick));
a7812ae4 2873 gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
a7812ae4 2874 tcg_temp_free_ptr(r_tickptr);
ccd4a219 2875 }
0f8a249a
BS		 2876 break;
2877 case 5: // tba
255e1fcb 2878 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2879 break;
2880 case 6: // pstate
45778f99
RH		 2881 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2882 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2883 break;
2884 case 7: // tl
45778f99
RH		 2885 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2886 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2887 break;
2888 case 8: // pil
45778f99
RH		 2889 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2890 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2891 break;
2892 case 9: // cwp
063c3675 2893 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2894 break;
2895 case 10: // cansave
45778f99
RH		 2896 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2897 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2898 break;
2899 case 11: // canrestore
45778f99
RH		 2900 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2901 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2902 break;
2903 case 12: // cleanwin
45778f99
RH		 2904 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2905 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2906 break;
2907 case 13: // otherwin
45778f99
RH		 2908 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2909 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2910 break;
2911 case 14: // wstate
45778f99
RH		 2912 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2913 offsetof(CPUSPARCState, wstate));
0f8a249a 2914 break;
e9ebed4d 2915 case 16: // UA2005 gl
fb79ceb9 2916 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2917 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2918 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2919 break;
2920 case 26: // UA2005 strand status
fb79ceb9 2921 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2922 if (!hypervisor(dc))
2923 goto priv_insn;
527067d8 2924 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2925 break;
0f8a249a 2926 case 31: // ver
255e1fcb 2927 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2928 break;
2929 case 15: // fq
2930 default:
2931 goto illegal_insn;
2932 }
3475187d 2933#else
255e1fcb 2934 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2935#endif
97ea2859 2936 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2937 break;
3475187d
FB		 2938 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2939#ifdef TARGET_SPARC64
66442b07 2940 save_state(dc);
063c3675 2941 gen_helper_flushw(cpu_env);
3475187d 2942#else
0f8a249a
BS		 2943 if (!supervisor(dc))
2944 goto priv_insn;
97ea2859 2945 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2946#endif
e8af50a3
FB		 2947 break;
2948#endif
0f8a249a 2949 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2950 if (gen_trap_ifnofpu(dc)) {
a80dde08 2951 goto jmp_insn;
5b12f1e8 2952 }
0f8a249a 2953 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2954 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2955 rs2 = GET_FIELD(insn, 27, 31);
2956 xop = GET_FIELD(insn, 18, 26);
66442b07 2957 save_state(dc);
0f8a249a 2958 switch (xop) {
dc1a6971 2959 case 0x1: /* fmovs */
208ae657
RH		 2960 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2961 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2962 break;
2963 case 0x5: /* fnegs */
61f17f6e 2964 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2965 break;
2966 case 0x9: /* fabss */
61f17f6e 2967 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2968 break;
2969 case 0x29: /* fsqrts */
2970 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2971 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2972 break;
2973 case 0x2a: /* fsqrtd */
2974 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2975 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2976 break;
2977 case 0x2b: /* fsqrtq */
2978 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2979 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2980 break;
2981 case 0x41: /* fadds */
61f17f6e 2982 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2983 break;
2984 case 0x42: /* faddd */
61f17f6e 2985 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2986 break;
2987 case 0x43: /* faddq */
2988 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2989 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2990 break;
2991 case 0x45: /* fsubs */
61f17f6e 2992 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2993 break;
2994 case 0x46: /* fsubd */
61f17f6e 2995 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 2996 break;
2997 case 0x47: /* fsubq */
2998 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2999 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3000 break;
3001 case 0x49: /* fmuls */
3002 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3003 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3004 break;
3005 case 0x4a: /* fmuld */
3006 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3007 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3008 break;
3009 case 0x4b: /* fmulq */
3010 CHECK_FPU_FEATURE(dc, FLOAT128);
3011 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3012 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3013 break;
3014 case 0x4d: /* fdivs */
61f17f6e 3015 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3016 break;
3017 case 0x4e: /* fdivd */
61f17f6e 3018 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3019 break;
3020 case 0x4f: /* fdivq */
3021 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3022 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3023 break;
3024 case 0x69: /* fsmuld */
3025 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3026 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3027 break;
3028 case 0x6e: /* fdmulq */
3029 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3030 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3031 break;
3032 case 0xc4: /* fitos */
61f17f6e 3033 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3034 break;
3035 case 0xc6: /* fdtos */
61f17f6e 3036 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3037 break;
3038 case 0xc7: /* fqtos */
3039 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3040 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3041 break;
3042 case 0xc8: /* fitod */
61f17f6e 3043 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3044 break;
3045 case 0xc9: /* fstod */
61f17f6e 3046 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3047 break;
3048 case 0xcb: /* fqtod */
3049 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3050 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3051 break;
3052 case 0xcc: /* fitoq */
3053 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3054 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3055 break;
3056 case 0xcd: /* fstoq */
3057 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3058 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3059 break;
3060 case 0xce: /* fdtoq */
3061 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3062 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3063 break;
3064 case 0xd1: /* fstoi */
61f17f6e 3065 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3066 break;
3067 case 0xd2: /* fdtoi */
61f17f6e 3068 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3069 break;
3070 case 0xd3: /* fqtoi */
3071 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3072 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3073 break;
3475187d 3074#ifdef TARGET_SPARC64
dc1a6971 3075 case 0x2: /* V9 fmovd */
96eda024
RH		 3076 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3077 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3078 break;
3079 case 0x3: /* V9 fmovq */
3080 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3081 gen_move_Q(rd, rs2);
dc1a6971
BS		 3082 break;
3083 case 0x6: /* V9 fnegd */
61f17f6e 3084 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3085 break;
3086 case 0x7: /* V9 fnegq */
3087 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3088 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3089 break;
3090 case 0xa: /* V9 fabsd */
61f17f6e 3091 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3092 break;
3093 case 0xb: /* V9 fabsq */
3094 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3095 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3096 break;
3097 case 0x81: /* V9 fstox */
61f17f6e 3098 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3099 break;
3100 case 0x82: /* V9 fdtox */
61f17f6e 3101 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3102 break;
3103 case 0x83: /* V9 fqtox */
3104 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3105 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3106 break;
3107 case 0x84: /* V9 fxtos */
61f17f6e 3108 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3109 break;
3110 case 0x88: /* V9 fxtod */
61f17f6e 3111 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3112 break;
3113 case 0x8c: /* V9 fxtoq */
3114 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3115 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3116 break;
0f8a249a 3117#endif
dc1a6971
BS		 3118 default:
3119 goto illegal_insn;
0f8a249a
BS		 3120 }
3121 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3122#ifdef TARGET_SPARC64
0f8a249a 3123 int cond;
3475187d 3124#endif
5b12f1e8 3125 if (gen_trap_ifnofpu(dc)) {
a80dde08 3126 goto jmp_insn;
5b12f1e8 3127 }
0f8a249a 3128 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3129 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3130 rs2 = GET_FIELD(insn, 27, 31);
3131 xop = GET_FIELD(insn, 18, 26);
66442b07 3132 save_state(dc);
dcf24905 3133
690995a6
RH		 3134#ifdef TARGET_SPARC64
3135#define FMOVR(sz) \
3136 do { \
3137 DisasCompare cmp; \
e7c8afb9 3138 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3139 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3140 gen_compare_reg(&cmp, cond, cpu_src1); \
3141 gen_fmov##sz(dc, &cmp, rd, rs2); \
3142 free_compare(&cmp); \
3143 } while (0)
3144
3145 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3146 FMOVR(s);
0f8a249a
BS		 3147 break;
3148 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3149 FMOVR(d);
0f8a249a
BS		 3150 break;
3151 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3152 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3153 FMOVR(q);
1f587329 3154 break;
0f8a249a 3155 }
690995a6 3156#undef FMOVR
0f8a249a
BS		 3157#endif
3158 switch (xop) {
3475187d 3159#ifdef TARGET_SPARC64
7e480893
RH		 3160#define FMOVCC(fcc, sz) \
3161 do { \
3162 DisasCompare cmp; \
714547bb 3163 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3164 gen_fcompare(&cmp, fcc, cond); \
3165 gen_fmov##sz(dc, &cmp, rd, rs2); \
3166 free_compare(&cmp); \
3167 } while (0)
3168
0f8a249a 3169 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3170 FMOVCC(0, s);
0f8a249a
BS		 3171 break;
3172 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3173 FMOVCC(0, d);
0f8a249a
BS		 3174 break;
3175 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3176 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3177 FMOVCC(0, q);
1f587329 3178 break;
0f8a249a 3179 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3180 FMOVCC(1, s);
0f8a249a
BS		 3181 break;
3182 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3183 FMOVCC(1, d);
0f8a249a
BS		 3184 break;
3185 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3186 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3187 FMOVCC(1, q);
1f587329 3188 break;
0f8a249a 3189 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3190 FMOVCC(2, s);
0f8a249a
BS		 3191 break;
3192 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3193 FMOVCC(2, d);
0f8a249a
BS		 3194 break;
3195 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3196 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3197 FMOVCC(2, q);
1f587329 3198 break;
0f8a249a 3199 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3200 FMOVCC(3, s);
0f8a249a
BS		 3201 break;
3202 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3203 FMOVCC(3, d);
0f8a249a
BS		 3204 break;
3205 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3206 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3207 FMOVCC(3, q);
1f587329 3208 break;
7e480893
RH		 3209#undef FMOVCC
3210#define FMOVCC(xcc, sz) \
3211 do { \
3212 DisasCompare cmp; \
714547bb 3213 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3214 gen_compare(&cmp, xcc, cond, dc); \
3215 gen_fmov##sz(dc, &cmp, rd, rs2); \
3216 free_compare(&cmp); \
3217 } while (0)
19f329ad 3218
0f8a249a 3219 case 0x101: /* V9 fmovscc %icc */
7e480893 3220 FMOVCC(0, s);
0f8a249a
BS		 3221 break;
3222 case 0x102: /* V9 fmovdcc %icc */
7e480893 3223 FMOVCC(0, d);
b7d69dc2 3224 break;
0f8a249a 3225 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3226 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3227 FMOVCC(0, q);
1f587329 3228 break;
0f8a249a 3229 case 0x181: /* V9 fmovscc %xcc */
7e480893 3230 FMOVCC(1, s);
0f8a249a
BS		 3231 break;
3232 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3233 FMOVCC(1, d);
0f8a249a
BS		 3234 break;
3235 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3236 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3237 FMOVCC(1, q);
1f587329 3238 break;
7e480893 3239#undef FMOVCC
1f587329
BS		 3240#endif
3241 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3242 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3243 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3244 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3245 break;
1f587329 3246 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3247 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3248 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3249 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3250 break;
1f587329 3251 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3252 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3253 gen_op_load_fpr_QT0(QFPREG(rs1));
3254 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3255 gen_op_fcmpq(rd & 3);
1f587329 3256 break;
0f8a249a 3257 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3258 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3259 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3260 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3261 break;
3262 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3263 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3264 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3265 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3266 break;
1f587329 3267 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3268 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3269 gen_op_load_fpr_QT0(QFPREG(rs1));
3270 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3271 gen_op_fcmpeq(rd & 3);
1f587329 3272 break;
0f8a249a
BS		 3273 default:
3274 goto illegal_insn;
3275 }
0f8a249a 3276 } else if (xop == 0x2) {
97ea2859 3277 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3278 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3279 if (rs1 == 0) {
97ea2859 3280 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3281 if (IS_IMM) { /* immediate */
67526b20 3282 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3283 tcg_gen_movi_tl(dst, simm);
3284 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3285 } else { /* register */
3286 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3287 if (rs2 == 0) {
3288 tcg_gen_movi_tl(dst, 0);
3289 gen_store_gpr(dc, rd, dst);
3290 } else {
3291 cpu_src2 = gen_load_gpr(dc, rs2);
3292 gen_store_gpr(dc, rd, cpu_src2);
3293 }
0f8a249a 3294 }
0f8a249a 3295 } else {
9d1d4e34 3296 cpu_src1 = get_src1(dc, insn);
0f8a249a 3297 if (IS_IMM) { /* immediate */
67526b20 3298 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3299 tcg_gen_ori_tl(dst, cpu_src1, simm);
3300 gen_store_gpr(dc, rd, dst);
0f8a249a 3301 } else { /* register */
0f8a249a 3302 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3303 if (rs2 == 0) {
3304 /* mov shortcut: or x, %g0, y -> mov x, y */
3305 gen_store_gpr(dc, rd, cpu_src1);
3306 } else {
3307 cpu_src2 = gen_load_gpr(dc, rs2);
3308 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3309 gen_store_gpr(dc, rd, dst);
3310 }
0f8a249a 3311 }
0f8a249a 3312 }
83469015 3313#ifdef TARGET_SPARC64
0f8a249a 3314 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3315 cpu_src1 = get_src1(dc, insn);
0f8a249a 3316 if (IS_IMM) { /* immediate */
67526b20 3317 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3318 if (insn & (1 << 12)) {
67526b20 3319 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3320 } else {
67526b20 3321 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3322 }
0f8a249a 3323 } else { /* register */
83469015 3324 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3325 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3326 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3327 if (insn & (1 << 12)) {
6ae20372 3328 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3329 } else {
6ae20372 3330 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3331 }
01b1fa6d 3332 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3333 }
97ea2859 3334 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3335 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3336 cpu_src1 = get_src1(dc, insn);
0f8a249a 3337 if (IS_IMM) { /* immediate */
67526b20 3338 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3339 if (insn & (1 << 12)) {
67526b20 3340 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3341 } else {
6ae20372 3342 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3343 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3344 }
0f8a249a 3345 } else { /* register */
83469015 3346 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3347 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3348 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3349 if (insn & (1 << 12)) {
6ae20372
BS		 3350 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3351 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3352 } else {
6ae20372
BS		 3353 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3354 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3355 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3356 }
83469015 3357 }
97ea2859 3358 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3359 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3360 cpu_src1 = get_src1(dc, insn);
0f8a249a 3361 if (IS_IMM) { /* immediate */
67526b20 3362 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3363 if (insn & (1 << 12)) {
67526b20 3364 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3365 } else {
97ea2859 3366 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3367 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3368 }
0f8a249a 3369 } else { /* register */
83469015 3370 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3371 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3372 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3373 if (insn & (1 << 12)) {
6ae20372
BS		 3374 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3375 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3376 } else {
6ae20372 3377 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3378 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3379 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3380 }
83469015 3381 }
97ea2859 3382 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3383#endif
fcc72045 3384 } else if (xop < 0x36) {
cf495bcf 3385 if (xop < 0x20) {
9d1d4e34
RH		 3386 cpu_src1 = get_src1(dc, insn);
3387 cpu_src2 = get_src2(dc, insn);
cf495bcf 3388 switch (xop & ~0x10) {
b89e94af 3389 case 0x0: /* add */
97ea2859
RH		 3390 if (xop & 0x10) {
3391 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3392 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3393 dc->cc_op = CC_OP_ADD;
41d72852 3394 } else {
97ea2859 3395 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3396 }
cf495bcf 3397 break;
b89e94af 3398 case 0x1: /* and */
97ea2859 3399 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3400 if (xop & 0x10) {
38482a77
BS		 3401 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3402 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3403 dc->cc_op = CC_OP_LOGIC;
41d72852 3404 }
cf495bcf 3405 break;
b89e94af 3406 case 0x2: /* or */
97ea2859 3407 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3408 if (xop & 0x10) {
38482a77
BS		 3409 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3410 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3411 dc->cc_op = CC_OP_LOGIC;
8393617c 3412 }
0f8a249a 3413 break;
b89e94af 3414 case 0x3: /* xor */
97ea2859 3415 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3416 if (xop & 0x10) {
38482a77
BS		 3417 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3418 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3419 dc->cc_op = CC_OP_LOGIC;
8393617c 3420 }
cf495bcf 3421 break;
b89e94af 3422 case 0x4: /* sub */
97ea2859
RH		 3423 if (xop & 0x10) {
3424 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3425 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3426 dc->cc_op = CC_OP_SUB;
41d72852 3427 } else {
97ea2859 3428 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3429 }
cf495bcf 3430 break;
b89e94af 3431 case 0x5: /* andn */
97ea2859 3432 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3433 if (xop & 0x10) {
38482a77
BS		 3434 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3435 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3436 dc->cc_op = CC_OP_LOGIC;
8393617c 3437 }
cf495bcf 3438 break;
b89e94af 3439 case 0x6: /* orn */
97ea2859 3440 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3441 if (xop & 0x10) {
38482a77
BS		 3442 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3443 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3444 dc->cc_op = CC_OP_LOGIC;
8393617c 3445 }
cf495bcf 3446 break;
b89e94af 3447 case 0x7: /* xorn */
97ea2859 3448 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3449 if (xop & 0x10) {
38482a77
BS		 3450 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3451 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3452 dc->cc_op = CC_OP_LOGIC;
8393617c 3453 }
cf495bcf 3454 break;
b89e94af 3455 case 0x8: /* addx, V9 addc */
70c48285
RH		 3456 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3457 (xop & 0x10));
cf495bcf 3458 break;
ded3ab80 3459#ifdef TARGET_SPARC64
0f8a249a 3460 case 0x9: /* V9 mulx */
97ea2859 3461 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3462 break;
3463#endif
b89e94af 3464 case 0xa: /* umul */
64a88d5d 3465 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3466 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3467 if (xop & 0x10) {
38482a77
BS		 3468 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3469 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3470 dc->cc_op = CC_OP_LOGIC;
8393617c 3471 }
cf495bcf 3472 break;
b89e94af 3473 case 0xb: /* smul */
64a88d5d 3474 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3475 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3476 if (xop & 0x10) {
38482a77
BS		 3477 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3478 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3479 dc->cc_op = CC_OP_LOGIC;
8393617c 3480 }
cf495bcf 3481 break;
b89e94af 3482 case 0xc: /* subx, V9 subc */
70c48285
RH		 3483 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3484 (xop & 0x10));
cf495bcf 3485 break;
ded3ab80 3486#ifdef TARGET_SPARC64
0f8a249a 3487 case 0xd: /* V9 udivx */
c28ae41e 3488 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3489 break;
3490#endif
b89e94af 3491 case 0xe: /* udiv */
64a88d5d 3492 CHECK_IU_FEATURE(dc, DIV);
8393617c 3493 if (xop & 0x10) {
7a5e4488
BS		 3494 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3495 cpu_src2);
6c78ea32 3496 dc->cc_op = CC_OP_DIV;
0fcec41e 3497 } else {
7a5e4488
BS		 3498 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3499 cpu_src2);
8393617c 3500 }
cf495bcf 3501 break;
b89e94af 3502 case 0xf: /* sdiv */
64a88d5d 3503 CHECK_IU_FEATURE(dc, DIV);
8393617c 3504 if (xop & 0x10) {
7a5e4488
BS		 3505 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3506 cpu_src2);
6c78ea32 3507 dc->cc_op = CC_OP_DIV;
0fcec41e 3508 } else {
7a5e4488
BS		 3509 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3510 cpu_src2);
8393617c 3511 }
cf495bcf
FB		 3512 break;
3513 default:
3514 goto illegal_insn;
3515 }
97ea2859 3516 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3517 } else {
9d1d4e34
RH		 3518 cpu_src1 = get_src1(dc, insn);
3519 cpu_src2 = get_src2(dc, insn);
cf495bcf 3520 switch (xop) {
0f8a249a 3521 case 0x20: /* taddcc */
a2ea4aa9 3522 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3523 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3524 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3525 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3526 break;
3527 case 0x21: /* tsubcc */
a2ea4aa9 3528 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3529 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3530 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3531 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3532 break;
3533 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3534 gen_helper_taddcctv(cpu_dst, cpu_env,
3535 cpu_src1, cpu_src2);
97ea2859 3536 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3537 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3538 break;
3539 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3540 gen_helper_tsubcctv(cpu_dst, cpu_env,
3541 cpu_src1, cpu_src2);
97ea2859 3542 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3543 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3544 break;
cf495bcf 3545 case 0x24: /* mulscc */
20132b96 3546 update_psr(dc);
6ae20372 3547 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3548 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3549 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3550 dc->cc_op = CC_OP_ADD;
cf495bcf 3551 break;
83469015 3552#ifndef TARGET_SPARC64
0f8a249a 3553 case 0x25: /* sll */
e35298cd 3554 if (IS_IMM) { /* immediate */
67526b20
BS		 3555 simm = GET_FIELDs(insn, 20, 31);
3556 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3557 } else { /* register */
de9e9d9f 3558 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3559 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3560 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3561 }
97ea2859 3562 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3563 break;
83469015 3564 case 0x26: /* srl */
e35298cd 3565 if (IS_IMM) { /* immediate */
67526b20
BS		 3566 simm = GET_FIELDs(insn, 20, 31);
3567 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3568 } else { /* register */
de9e9d9f 3569 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3570 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3571 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3572 }
97ea2859 3573 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3574 break;
83469015 3575 case 0x27: /* sra */
e35298cd 3576 if (IS_IMM) { /* immediate */
67526b20
BS		 3577 simm = GET_FIELDs(insn, 20, 31);
3578 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3579 } else { /* register */
de9e9d9f 3580 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3581 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3582 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3583 }
97ea2859 3584 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3585 break;
83469015 3586#endif
cf495bcf
FB		 3587 case 0x30:
3588 {
de9e9d9f 3589 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3590 switch(rd) {
3475187d 3591 case 0: /* wry */
5068cbd9
BS		 3592 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3593 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3594 break;
65fe7b09
BS		 3595#ifndef TARGET_SPARC64
3596 case 0x01 ... 0x0f: /* undefined in the
3597 SPARCv8 manual, nop
3598 on the microSPARC
3599 II */
3600 case 0x10 ... 0x1f: /* implementation-dependent
3601 in the SPARCv8
3602 manual, nop on the
3603 microSPARC II */
d1c36ba7
RH		 3604 if ((rd == 0x13) && (dc->def->features &
3605 CPU_FEATURE_POWERDOWN)) {
3606 /* LEON3 power-down */
1cf892ca 3607 save_state(dc);
d1c36ba7
RH		 3608 gen_helper_power_down(cpu_env);
3609 }
65fe7b09
BS		 3610 break;
3611#else
0f8a249a 3612 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3613 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3614 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3615 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3616 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3617 break;
3618 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3619 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3620 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3621 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
0f8a249a
BS		 3622 break;
3623 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3624 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3625 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3626 save_state(dc);
3299908c 3627 gen_op_next_insn();
57fec1fe 3628 tcg_gen_exit_tb(0);
3299908c 3629 dc->is_br = 1;
0f8a249a
BS		 3630 break;
3631 case 0xf: /* V9 sir, nop if user */
3475187d 3632#if !defined(CONFIG_USER_ONLY)
6ad6135d 3633 if (supervisor(dc)) {
1a2fb1c0 3634 ; // XXX
6ad6135d 3635 }
3475187d 3636#endif
0f8a249a
BS		 3637 break;
3638 case 0x13: /* Graphics Status */
5b12f1e8 3639 if (gen_trap_ifnofpu(dc)) {
725cb90b 3640 goto jmp_insn;
5b12f1e8 3641 }
255e1fcb 3642 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3643 break;
9d926598
BS		 3644 case 0x14: /* Softint set */
3645 if (!supervisor(dc))
3646 goto illegal_insn;
aeff993c
RH		 3647 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3648 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3649 break;
3650 case 0x15: /* Softint clear */
3651 if (!supervisor(dc))
3652 goto illegal_insn;
aeff993c
RH		 3653 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3654 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3655 break;
3656 case 0x16: /* Softint write */
3657 if (!supervisor(dc))
3658 goto illegal_insn;
aeff993c
RH		 3659 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3660 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3661 break;
0f8a249a 3662 case 0x17: /* Tick compare */
83469015 3663#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3664 if (!supervisor(dc))
3665 goto illegal_insn;
83469015 3666#endif
ccd4a219 3667 {
a7812ae4 3668 TCGv_ptr r_tickptr;
ccd4a219 3669
255e1fcb 3670 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3671 cpu_src2);
a7812ae4 3672 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3673 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3674 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3675 gen_helper_tick_set_limit(r_tickptr,
3676 cpu_tick_cmpr);
3677 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3678 }
0f8a249a
BS		 3679 break;
3680 case 0x18: /* System tick */
83469015 3681#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3682 if (!supervisor(dc))
3683 goto illegal_insn;
83469015 3684#endif
ccd4a219 3685 {
a7812ae4 3686 TCGv_ptr r_tickptr;
ccd4a219 3687
7b04bd5c 3688 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3689 cpu_src2);
a7812ae4 3690 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3691 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3692 offsetof(CPUSPARCState, stick));
a7812ae4 3693 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3694 cpu_tmp0);
a7812ae4 3695 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3696 }
0f8a249a
BS		 3697 break;
3698 case 0x19: /* System tick compare */
83469015 3699#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3700 if (!supervisor(dc))
3701 goto illegal_insn;
3475187d 3702#endif
ccd4a219 3703 {
a7812ae4 3704 TCGv_ptr r_tickptr;
ccd4a219 3705
255e1fcb 3706 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3707 cpu_src2);
a7812ae4 3708 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3709 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3710 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3711 gen_helper_tick_set_limit(r_tickptr,
3712 cpu_stick_cmpr);
3713 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3714 }
0f8a249a 3715 break;
83469015 3716
0f8a249a 3717 case 0x10: /* Performance Control */
77f193da
BS		 3718 case 0x11: /* Performance Instrumentation
3719 Counter */
0f8a249a 3720 case 0x12: /* Dispatch Control */
83469015 3721#endif
3475187d 3722 default:
cf495bcf
FB		 3723 goto illegal_insn;
3724 }
3725 }
3726 break;
e8af50a3 3727#if !defined(CONFIG_USER_ONLY)
af7bf89b 3728 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3729 {
0f8a249a
BS		 3730 if (!supervisor(dc))
3731 goto priv_insn;
3475187d 3732#ifdef TARGET_SPARC64
0f8a249a
BS		 3733 switch (rd) {
3734 case 0:
063c3675 3735 gen_helper_saved(cpu_env);
0f8a249a
BS		 3736 break;
3737 case 1:
063c3675 3738 gen_helper_restored(cpu_env);
0f8a249a 3739 break;
e9ebed4d
BS		 3740 case 2: /* UA2005 allclean */
3741 case 3: /* UA2005 otherw */
3742 case 4: /* UA2005 normalw */
3743 case 5: /* UA2005 invalw */
3744 // XXX
0f8a249a 3745 default:
3475187d
FB		 3746 goto illegal_insn;
3747 }
3748#else
de9e9d9f 3749 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3750 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3751 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3752 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3753 dc->cc_op = CC_OP_FLAGS;
66442b07 3754 save_state(dc);
9e61bde5 3755 gen_op_next_insn();
57fec1fe 3756 tcg_gen_exit_tb(0);
0f8a249a 3757 dc->is_br = 1;
3475187d 3758#endif
e8af50a3
FB		 3759 }
3760 break;
af7bf89b 3761 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3762 {
0f8a249a
BS		 3763 if (!supervisor(dc))
3764 goto priv_insn;
de9e9d9f 3765 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3766 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3767#ifdef TARGET_SPARC64
0f8a249a
BS		 3768 switch (rd) {
3769 case 0: // tpc
375ee38b 3770 {
a7812ae4 3771 TCGv_ptr r_tsptr;
375ee38b 3772
a7812ae4 3773 r_tsptr = tcg_temp_new_ptr();
8194f35a 3774 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3775 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3776 offsetof(trap_state, tpc));
a7812ae4 3777 tcg_temp_free_ptr(r_tsptr);
375ee38b 3778 }
0f8a249a
BS		 3779 break;
3780 case 1: // tnpc
375ee38b 3781 {
a7812ae4 3782 TCGv_ptr r_tsptr;
375ee38b 3783
a7812ae4 3784 r_tsptr = tcg_temp_new_ptr();
8194f35a 3785 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3786 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3787 offsetof(trap_state, tnpc));
a7812ae4 3788 tcg_temp_free_ptr(r_tsptr);
375ee38b 3789 }
0f8a249a
BS		 3790 break;
3791 case 2: // tstate
375ee38b 3792 {
a7812ae4 3793 TCGv_ptr r_tsptr;
375ee38b 3794
a7812ae4 3795 r_tsptr = tcg_temp_new_ptr();
8194f35a 3796 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3797 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3798 offsetof(trap_state,
3799 tstate));
a7812ae4 3800 tcg_temp_free_ptr(r_tsptr);
375ee38b 3801 }
0f8a249a
BS		 3802 break;
3803 case 3: // tt
375ee38b 3804 {
a7812ae4 3805 TCGv_ptr r_tsptr;
375ee38b 3806
a7812ae4 3807 r_tsptr = tcg_temp_new_ptr();
8194f35a 3808 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3809 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3810 offsetof(trap_state, tt));
a7812ae4 3811 tcg_temp_free_ptr(r_tsptr);
375ee38b 3812 }
0f8a249a
BS		 3813 break;
3814 case 4: // tick
ccd4a219 3815 {
a7812ae4 3816 TCGv_ptr r_tickptr;
ccd4a219 3817
a7812ae4 3818 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3819 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3820 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3821 gen_helper_tick_set_count(r_tickptr,
3822 cpu_tmp0);
3823 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3824 }
0f8a249a
BS		 3825 break;
3826 case 5: // tba
255e1fcb 3827 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3828 break;
3829 case 6: // pstate
6234ac09
RH		 3830 save_state(dc);
3831 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3832 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3833 break;
3834 case 7: // tl
6234ac09 3835 save_state(dc);
7b9e066b 3836 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3837 offsetof(CPUSPARCState, tl));
3838 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3839 break;
3840 case 8: // pil
063c3675 3841 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3842 break;
3843 case 9: // cwp
063c3675 3844 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3845 break;
3846 case 10: // cansave
7b9e066b
RH		 3847 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3848 offsetof(CPUSPARCState,
3849 cansave));
0f8a249a
BS		 3850 break;
3851 case 11: // canrestore
7b9e066b
RH		 3852 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3853 offsetof(CPUSPARCState,
3854 canrestore));
0f8a249a
BS		 3855 break;
3856 case 12: // cleanwin
7b9e066b
RH		 3857 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3858 offsetof(CPUSPARCState,
3859 cleanwin));
0f8a249a
BS		 3860 break;
3861 case 13: // otherwin
7b9e066b
RH		 3862 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3863 offsetof(CPUSPARCState,
3864 otherwin));
0f8a249a
BS		 3865 break;
3866 case 14: // wstate
7b9e066b
RH		 3867 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3868 offsetof(CPUSPARCState,
3869 wstate));
0f8a249a 3870 break;
e9ebed4d 3871 case 16: // UA2005 gl
fb79ceb9 3872 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3873 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3874 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3875 break;
3876 case 26: // UA2005 strand status
fb79ceb9 3877 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3878 if (!hypervisor(dc))
3879 goto priv_insn;
527067d8 3880 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3881 break;
0f8a249a
BS		 3882 default:
3883 goto illegal_insn;
3884 }
3475187d 3885#else
7b9e066b
RH		 3886 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3887 if (dc->def->nwindows != 32) {
3888 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3889 (1 << dc->def->nwindows) - 1);
7b9e066b 3890 }
3475187d 3891#endif
e8af50a3
FB		 3892 }
3893 break;
e9ebed4d 3894 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3895 {
e9ebed4d 3896#ifndef TARGET_SPARC64
0f8a249a
BS		 3897 if (!supervisor(dc))
3898 goto priv_insn;
255e1fcb 3899 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3900#else
fb79ceb9 3901 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3902 if (!hypervisor(dc))
3903 goto priv_insn;
de9e9d9f 3904 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3905 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3906 switch (rd) {
3907 case 0: // hpstate
3908 // XXX gen_op_wrhpstate();
66442b07 3909 save_state(dc);
e9ebed4d 3910 gen_op_next_insn();
57fec1fe 3911 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3912 dc->is_br = 1;
3913 break;
3914 case 1: // htstate
3915 // XXX gen_op_wrhtstate();
3916 break;
3917 case 3: // hintp
255e1fcb 3918 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3919 break;
3920 case 5: // htba
255e1fcb 3921 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3922 break;
3923 case 31: // hstick_cmpr
ccd4a219 3924 {
a7812ae4 3925 TCGv_ptr r_tickptr;
ccd4a219 3926
255e1fcb 3927 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3928 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3929 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3930 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3931 gen_helper_tick_set_limit(r_tickptr,
3932 cpu_hstick_cmpr);
3933 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3934 }
e9ebed4d
BS		 3935 break;
3936 case 6: // hver readonly
3937 default:
3938 goto illegal_insn;
3939 }
3940#endif
e8af50a3
FB		 3941 }
3942 break;
3943#endif
3475187d 3944#ifdef TARGET_SPARC64
0f8a249a
BS		 3945 case 0x2c: /* V9 movcc */
3946 {
3947 int cc = GET_FIELD_SP(insn, 11, 12);
3948 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3949 DisasCompare cmp;
97ea2859 3950 TCGv dst;
00f219bf 3951
0f8a249a 3952 if (insn & (1 << 18)) {
f52879b4
RH		 3953 if (cc == 0) {
3954 gen_compare(&cmp, 0, cond, dc);
3955 } else if (cc == 2) {
3956 gen_compare(&cmp, 1, cond, dc);
3957 } else {
0f8a249a 3958 goto illegal_insn;
f52879b4 3959 }
0f8a249a 3960 } else {
f52879b4 3961 gen_fcompare(&cmp, cc, cond);
0f8a249a 3962 }
00f219bf 3963
f52879b4
RH		 3964 /* The get_src2 above loaded the normal 13-bit
3965 immediate field, not the 11-bit field we have
3966 in movcc. But it did handle the reg case. */
3967 if (IS_IMM) {
67526b20 3968 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3969 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3970 }
f52879b4 3971
97ea2859
RH		 3972 dst = gen_load_gpr(dc, rd);
3973 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3974 cmp.c1, cmp.c2,
97ea2859 3975 cpu_src2, dst);
f52879b4 3976 free_compare(&cmp);
97ea2859 3977 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3978 break;
3979 }
3980 case 0x2d: /* V9 sdivx */
c28ae41e 3981 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3982 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3983 break;
3984 case 0x2e: /* V9 popc */
97ea2859
RH		 3985 gen_helper_popc(cpu_dst, cpu_src2);
3986 gen_store_gpr(dc, rd, cpu_dst);
3987 break;
0f8a249a
BS		 3988 case 0x2f: /* V9 movr */
3989 {
3990 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3991 DisasCompare cmp;
97ea2859 3992 TCGv dst;
00f219bf 3993
c33f80f5 3994 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 3995
c33f80f5
RH		 3996 /* The get_src2 above loaded the normal 13-bit
3997 immediate field, not the 10-bit field we have
3998 in movr. But it did handle the reg case. */
3999 if (IS_IMM) {
67526b20 4000 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4001 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4002 }
c33f80f5 4003
97ea2859
RH		 4004 dst = gen_load_gpr(dc, rd);
4005 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4006 cmp.c1, cmp.c2,
97ea2859 4007 cpu_src2, dst);
c33f80f5 4008 free_compare(&cmp);
97ea2859 4009 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4010 break;
4011 }
4012#endif
4013 default:
4014 goto illegal_insn;
4015 }
4016 }
3299908c
BS		 4017 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4018#ifdef TARGET_SPARC64
4019 int opf = GET_FIELD_SP(insn, 5, 13);
4020 rs1 = GET_FIELD(insn, 13, 17);
4021 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4022 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4023 goto jmp_insn;
5b12f1e8 4024 }
3299908c
BS		 4025
4026 switch (opf) {
e9ebed4d 4027 case 0x000: /* VIS I edge8cc */
6c073553 4028 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4029 cpu_src1 = gen_load_gpr(dc, rs1);
4030 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4031 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4032 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4033 break;
e9ebed4d 4034 case 0x001: /* VIS II edge8n */
6c073553 4035 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4036 cpu_src1 = gen_load_gpr(dc, rs1);
4037 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4038 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4039 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4040 break;
e9ebed4d 4041 case 0x002: /* VIS I edge8lcc */
6c073553 4042 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4043 cpu_src1 = gen_load_gpr(dc, rs1);
4044 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4045 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4046 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4047 break;
e9ebed4d 4048 case 0x003: /* VIS II edge8ln */
6c073553 4049 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4050 cpu_src1 = gen_load_gpr(dc, rs1);
4051 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4052 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4053 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4054 break;
e9ebed4d 4055 case 0x004: /* VIS I edge16cc */
6c073553 4056 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4057 cpu_src1 = gen_load_gpr(dc, rs1);
4058 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4059 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4060 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4061 break;
e9ebed4d 4062 case 0x005: /* VIS II edge16n */
6c073553 4063 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4064 cpu_src1 = gen_load_gpr(dc, rs1);
4065 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4066 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4067 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4068 break;
e9ebed4d 4069 case 0x006: /* VIS I edge16lcc */
6c073553 4070 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4071 cpu_src1 = gen_load_gpr(dc, rs1);
4072 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4073 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4074 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4075 break;
e9ebed4d 4076 case 0x007: /* VIS II edge16ln */
6c073553 4077 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4078 cpu_src1 = gen_load_gpr(dc, rs1);
4079 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4080 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4081 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4082 break;
e9ebed4d 4083 case 0x008: /* VIS I edge32cc */
6c073553 4084 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4085 cpu_src1 = gen_load_gpr(dc, rs1);
4086 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4087 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4088 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4089 break;
e9ebed4d 4090 case 0x009: /* VIS II edge32n */
6c073553 4091 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4092 cpu_src1 = gen_load_gpr(dc, rs1);
4093 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4094 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4095 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4096 break;
e9ebed4d 4097 case 0x00a: /* VIS I edge32lcc */
6c073553 4098 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4099 cpu_src1 = gen_load_gpr(dc, rs1);
4100 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4101 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4102 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4103 break;
e9ebed4d 4104 case 0x00b: /* VIS II edge32ln */
6c073553 4105 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4106 cpu_src1 = gen_load_gpr(dc, rs1);
4107 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4108 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4109 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4110 break;
e9ebed4d 4111 case 0x010: /* VIS I array8 */
64a88d5d 4112 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4113 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4114 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4115 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4116 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4117 break;
4118 case 0x012: /* VIS I array16 */
64a88d5d 4119 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4120 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4121 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4122 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4123 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4124 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4125 break;
4126 case 0x014: /* VIS I array32 */
64a88d5d 4127 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4128 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4129 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4130 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4131 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4132 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4133 break;
3299908c 4134 case 0x018: /* VIS I alignaddr */
64a88d5d 4135 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4136 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4137 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4138 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4139 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4140 break;
4141 case 0x01a: /* VIS I alignaddrl */
add545ab 4142 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4143 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4144 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4145 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4146 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4147 break;
4148 case 0x019: /* VIS II bmask */
793a137a 4149 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4150 cpu_src1 = gen_load_gpr(dc, rs1);
4151 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4152 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4153 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4154 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4155 break;
e9ebed4d 4156 case 0x020: /* VIS I fcmple16 */
64a88d5d 4157 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4158 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4159 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4160 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4161 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4162 break;
4163 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4164 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4165 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4166 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4167 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4168 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4169 break;
e9ebed4d 4170 case 0x024: /* VIS I fcmple32 */
64a88d5d 4171 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4172 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4173 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4174 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4175 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4176 break;
4177 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4178 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4179 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4180 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4181 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4182 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4183 break;
4184 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4185 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4186 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4187 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4188 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4189 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4190 break;
4191 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4192 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4193 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4194 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4195 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4196 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4197 break;
4198 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4199 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4200 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4201 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4202 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4203 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4204 break;
4205 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4206 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4207 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4208 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4209 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4210 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4211 break;
4212 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4213 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4214 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4215 break;
4216 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4217 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4218 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4219 break;
4220 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4221 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4222 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4223 break;
4224 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4225 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4226 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4227 break;
4228 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4229 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4230 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4231 break;
4232 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4233 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4234 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4235 break;
4236 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4237 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4238 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4239 break;
4240 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4241 CHECK_FPU_FEATURE(dc, VIS1);
4242 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4243 break;
e9ebed4d 4244 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4245 CHECK_FPU_FEATURE(dc, VIS1);
4246 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4247 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4248 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4249 gen_store_fpr_F(dc, rd, cpu_dst_32);
4250 break;
e9ebed4d 4251 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4252 CHECK_FPU_FEATURE(dc, VIS1);
4253 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4254 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4255 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4256 gen_store_fpr_F(dc, rd, cpu_dst_32);
4257 break;
f888300b
RH		 4258 case 0x03e: /* VIS I pdist */
4259 CHECK_FPU_FEATURE(dc, VIS1);
4260 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4261 break;
3299908c 4262 case 0x048: /* VIS I faligndata */
64a88d5d 4263 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4264 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4265 break;
e9ebed4d 4266 case 0x04b: /* VIS I fpmerge */
64a88d5d 4267 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4268 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4269 break;
4270 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4271 CHECK_FPU_FEATURE(dc, VIS2);
4272 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4273 break;
e9ebed4d 4274 case 0x04d: /* VIS I fexpand */
64a88d5d 4275 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4276 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4277 break;
4278 case 0x050: /* VIS I fpadd16 */
64a88d5d 4279 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4280 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4281 break;
4282 case 0x051: /* VIS I fpadd16s */
64a88d5d 4283 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4284 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4285 break;
4286 case 0x052: /* VIS I fpadd32 */
64a88d5d 4287 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4288 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4289 break;
4290 case 0x053: /* VIS I fpadd32s */
64a88d5d 4291 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4292 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4293 break;
4294 case 0x054: /* VIS I fpsub16 */
64a88d5d 4295 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4296 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4297 break;
4298 case 0x055: /* VIS I fpsub16s */
64a88d5d 4299 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4300 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4301 break;
4302 case 0x056: /* VIS I fpsub32 */
64a88d5d 4303 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4304 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4305 break;
4306 case 0x057: /* VIS I fpsub32s */
64a88d5d 4307 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4308 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4309 break;
3299908c 4310 case 0x060: /* VIS I fzero */
64a88d5d 4311 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4312 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4313 tcg_gen_movi_i64(cpu_dst_64, 0);
4314 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4315 break;
4316 case 0x061: /* VIS I fzeros */
64a88d5d 4317 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4318 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4319 tcg_gen_movi_i32(cpu_dst_32, 0);
4320 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4321 break;
e9ebed4d 4322 case 0x062: /* VIS I fnor */
64a88d5d 4323 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4324 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4325 break;
4326 case 0x063: /* VIS I fnors */
64a88d5d 4327 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4328 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4329 break;
4330 case 0x064: /* VIS I fandnot2 */
64a88d5d 4331 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4332 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4333 break;
4334 case 0x065: /* VIS I fandnot2s */
64a88d5d 4335 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4336 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4337 break;
4338 case 0x066: /* VIS I fnot2 */
64a88d5d 4339 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4340 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4341 break;
4342 case 0x067: /* VIS I fnot2s */
64a88d5d 4343 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4344 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4345 break;
4346 case 0x068: /* VIS I fandnot1 */
64a88d5d 4347 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4348 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4349 break;
4350 case 0x069: /* VIS I fandnot1s */
64a88d5d 4351 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4352 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4353 break;
4354 case 0x06a: /* VIS I fnot1 */
64a88d5d 4355 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4356 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4357 break;
4358 case 0x06b: /* VIS I fnot1s */
64a88d5d 4359 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4360 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4361 break;
4362 case 0x06c: /* VIS I fxor */
64a88d5d 4363 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4364 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4365 break;
4366 case 0x06d: /* VIS I fxors */
64a88d5d 4367 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4368 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4369 break;
4370 case 0x06e: /* VIS I fnand */
64a88d5d 4371 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4372 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4373 break;
4374 case 0x06f: /* VIS I fnands */
64a88d5d 4375 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4376 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4377 break;
4378 case 0x070: /* VIS I fand */
64a88d5d 4379 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4380 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4381 break;
4382 case 0x071: /* VIS I fands */
64a88d5d 4383 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4384 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4385 break;
4386 case 0x072: /* VIS I fxnor */
64a88d5d 4387 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4388 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4389 break;
4390 case 0x073: /* VIS I fxnors */
64a88d5d 4391 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4392 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4393 break;
3299908c 4394 case 0x074: /* VIS I fsrc1 */
64a88d5d 4395 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4396 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4397 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4398 break;
4399 case 0x075: /* VIS I fsrc1s */
64a88d5d 4400 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4401 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4402 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4403 break;
e9ebed4d 4404 case 0x076: /* VIS I fornot2 */
64a88d5d 4405 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4406 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4407 break;
4408 case 0x077: /* VIS I fornot2s */
64a88d5d 4409 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4410 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4411 break;
3299908c 4412 case 0x078: /* VIS I fsrc2 */
64a88d5d 4413 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4414 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4415 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4416 break;
4417 case 0x079: /* VIS I fsrc2s */
64a88d5d 4418 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4419 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4420 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4421 break;
e9ebed4d 4422 case 0x07a: /* VIS I fornot1 */
64a88d5d 4423 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4424 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4425 break;
4426 case 0x07b: /* VIS I fornot1s */
64a88d5d 4427 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4428 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4429 break;
4430 case 0x07c: /* VIS I for */
64a88d5d 4431 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4432 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4433 break;
4434 case 0x07d: /* VIS I fors */
64a88d5d 4435 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4436 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4437 break;
3299908c 4438 case 0x07e: /* VIS I fone */
64a88d5d 4439 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4440 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4441 tcg_gen_movi_i64(cpu_dst_64, -1);
4442 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4443 break;
4444 case 0x07f: /* VIS I fones */
64a88d5d 4445 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4446 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4447 tcg_gen_movi_i32(cpu_dst_32, -1);
4448 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4449 break;
e9ebed4d
BS		 4450 case 0x080: /* VIS I shutdown */
4451 case 0x081: /* VIS II siam */
4452 // XXX
4453 goto illegal_insn;
3299908c
BS		 4454 default:
4455 goto illegal_insn;
4456 }
4457#else
0f8a249a 4458 goto ncp_insn;
3299908c
BS		 4459#endif
4460 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4461#ifdef TARGET_SPARC64
0f8a249a 4462 goto illegal_insn;
fcc72045 4463#else
0f8a249a 4464 goto ncp_insn;
fcc72045 4465#endif
3475187d 4466#ifdef TARGET_SPARC64
0f8a249a 4467 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4468 TCGv_i32 r_const;
2ea815ca 4469
66442b07 4470 save_state(dc);
9d1d4e34 4471 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4472 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4473 if (IS_IMM) { /* immediate */
67526b20 4474 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4475 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4476 } else { /* register */
3475187d 4477 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4478 if (rs2) {
97ea2859 4479 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4480 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4481 } else {
7b04bd5c 4482 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4483 }
3475187d 4484 }
063c3675 4485 gen_helper_restore(cpu_env);
13a6dd00 4486 gen_mov_pc_npc(dc);
2ea815ca 4487 r_const = tcg_const_i32(3);
7b04bd5c 4488 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4489 tcg_temp_free_i32(r_const);
7b04bd5c 4490 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4491 dc->npc = DYNAMIC_PC;
4492 goto jmp_insn;
3475187d 4493#endif
0f8a249a 4494 } else {
9d1d4e34 4495 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4496 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4497 if (IS_IMM) { /* immediate */
67526b20 4498 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4499 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4500 } else { /* register */
e80cfcfc 4501 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4502 if (rs2) {
97ea2859 4503 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4504 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4505 } else {
7b04bd5c 4506 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4507 }
cf495bcf 4508 }
0f8a249a
BS		 4509 switch (xop) {
4510 case 0x38: /* jmpl */
4511 {
97ea2859 4512 TCGv t;
a7812ae4 4513 TCGv_i32 r_const;
2ea815ca 4514
97ea2859
RH		 4515 t = gen_dest_gpr(dc, rd);
4516 tcg_gen_movi_tl(t, dc->pc);
4517 gen_store_gpr(dc, rd, t);
13a6dd00 4518 gen_mov_pc_npc(dc);
2ea815ca 4519 r_const = tcg_const_i32(3);
7b04bd5c 4520 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4521 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4522 gen_address_mask(dc, cpu_tmp0);
4523 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4524 dc->npc = DYNAMIC_PC;
4525 }
4526 goto jmp_insn;
3475187d 4527#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4528 case 0x39: /* rett, V9 return */
4529 {
a7812ae4 4530 TCGv_i32 r_const;
2ea815ca 4531
0f8a249a
BS		 4532 if (!supervisor(dc))
4533 goto priv_insn;
13a6dd00 4534 gen_mov_pc_npc(dc);
2ea815ca 4535 r_const = tcg_const_i32(3);
7b04bd5c 4536 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4537 tcg_temp_free_i32(r_const);
7b04bd5c 4538 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4539 dc->npc = DYNAMIC_PC;
063c3675 4540 gen_helper_rett(cpu_env);
0f8a249a
BS		 4541 }
4542 goto jmp_insn;
4543#endif
4544 case 0x3b: /* flush */
5578ceab 4545 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4546 goto unimp_flush;
dcfd14b3 4547 /* nop */
0f8a249a
BS		 4548 break;
4549 case 0x3c: /* save */
66442b07 4550 save_state(dc);
063c3675 4551 gen_helper_save(cpu_env);
7b04bd5c 4552 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4553 break;
4554 case 0x3d: /* restore */
66442b07 4555 save_state(dc);
063c3675 4556 gen_helper_restore(cpu_env);
7b04bd5c 4557 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4558 break;
3475187d 4559#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4560 case 0x3e: /* V9 done/retry */
4561 {
4562 switch (rd) {
4563 case 0:
4564 if (!supervisor(dc))
4565 goto priv_insn;
4566 dc->npc = DYNAMIC_PC;
4567 dc->pc = DYNAMIC_PC;
063c3675 4568 gen_helper_done(cpu_env);
0f8a249a
BS		 4569 goto jmp_insn;
4570 case 1:
4571 if (!supervisor(dc))
4572 goto priv_insn;
4573 dc->npc = DYNAMIC_PC;
4574 dc->pc = DYNAMIC_PC;
063c3675 4575 gen_helper_retry(cpu_env);
0f8a249a
BS		 4576 goto jmp_insn;
4577 default:
4578 goto illegal_insn;
4579 }
4580 }
4581 break;
4582#endif
4583 default:
4584 goto illegal_insn;
4585 }
cf495bcf 4586 }
0f8a249a
BS		 4587 break;
4588 }
4589 break;
4590 case 3: /* load/store instructions */
4591 {
4592 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4593 /* ??? gen_address_mask prevents us from using a source
4594 register directly. Always generate a temporary. */
4595 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4596
5e6ed439
RH		 4597 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4598 if (xop == 0x3c || xop == 0x3e) {
4599 /* V9 casa/casxa : no offset */
71817e48 4600 } else if (IS_IMM) { /* immediate */
67526b20 4601 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4602 if (simm != 0) {
4603 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4604 }
0f8a249a
BS		 4605 } else { /* register */
4606 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4607 if (rs2 != 0) {
5e6ed439 4608 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4609 }
0f8a249a 4610 }
2f2ecb83
BS		 4611 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4612 (xop > 0x17 && xop <= 0x1d ) ||
4613 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4614 TCGv cpu_val = gen_dest_gpr(dc, rd);
4615
0f8a249a 4616 switch (xop) {
b89e94af 4617 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4618 gen_address_mask(dc, cpu_addr);
6ae20372 4619 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4620 break;
b89e94af 4621 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4622 gen_address_mask(dc, cpu_addr);
6ae20372 4623 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4624 break;
b89e94af 4625 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4626 gen_address_mask(dc, cpu_addr);
6ae20372 4627 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4628 break;
b89e94af 4629 case 0x3: /* ldd, load double word */
0f8a249a 4630 if (rd & 1)
d4218d99 4631 goto illegal_insn;
1a2fb1c0 4632 else {
a7812ae4 4633 TCGv_i32 r_const;
abcc7191 4634 TCGv_i64 t64;
2ea815ca 4635
66442b07 4636 save_state(dc);
2ea815ca 4637 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4638 /* XXX remove alignment check */
4639 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4640 tcg_temp_free_i32(r_const);
2cade6a3 4641 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4642 t64 = tcg_temp_new_i64();
4643 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4644 tcg_gen_trunc_i64_tl(cpu_val, t64);
4645 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4646 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4647 tcg_gen_shri_i64(t64, t64, 32);
4648 tcg_gen_trunc_i64_tl(cpu_val, t64);
4649 tcg_temp_free_i64(t64);
de9e9d9f 4650 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4651 }
0f8a249a 4652 break;
b89e94af 4653 case 0x9: /* ldsb, load signed byte */
2cade6a3 4654 gen_address_mask(dc, cpu_addr);
6ae20372 4655 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4656 break;
b89e94af 4657 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4658 gen_address_mask(dc, cpu_addr);
6ae20372 4659 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4660 break;
4661 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4662 {
4663 TCGv r_const;
4664
2cade6a3 4665 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4666 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4667 r_const = tcg_const_tl(0xff);
4668 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4669 tcg_temp_free(r_const);
4670 }
0f8a249a 4671 break;
de9e9d9f
RH		 4672 case 0x0f:
4673 /* swap, swap register with memory. Also atomically */
4674 {
4675 TCGv t0 = get_temp_tl(dc);
4676 CHECK_IU_FEATURE(dc, SWAP);
4677 cpu_src1 = gen_load_gpr(dc, rd);
4678 gen_address_mask(dc, cpu_addr);
4679 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4680 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4681 tcg_gen_mov_tl(cpu_val, t0);
4682 }
0f8a249a 4683 break;
3475187d 4684#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4685 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4686#ifndef TARGET_SPARC64
0f8a249a
BS		 4687 if (IS_IMM)
4688 goto illegal_insn;
4689 if (!supervisor(dc))
4690 goto priv_insn;
6ea4a6c8 4691#endif
66442b07 4692 save_state(dc);
6ae20372 4693 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4694 break;
b89e94af 4695 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4696#ifndef TARGET_SPARC64
0f8a249a
BS		 4697 if (IS_IMM)
4698 goto illegal_insn;
4699 if (!supervisor(dc))
4700 goto priv_insn;
4701#endif
66442b07 4702 save_state(dc);
6ae20372 4703 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4704 break;
b89e94af 4705 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4706#ifndef TARGET_SPARC64
0f8a249a
BS		 4707 if (IS_IMM)
4708 goto illegal_insn;
4709 if (!supervisor(dc))
4710 goto priv_insn;
3475187d 4711#endif
66442b07 4712 save_state(dc);
6ae20372 4713 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4714 break;
b89e94af 4715 case 0x13: /* ldda, load double word alternate */
3475187d 4716#ifndef TARGET_SPARC64
0f8a249a
BS		 4717 if (IS_IMM)
4718 goto illegal_insn;
4719 if (!supervisor(dc))
4720 goto priv_insn;
3475187d 4721#endif
0f8a249a 4722 if (rd & 1)
d4218d99 4723 goto illegal_insn;
66442b07 4724 save_state(dc);
c7785e16 4725 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4726 goto skip_move;
b89e94af 4727 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4728#ifndef TARGET_SPARC64
0f8a249a
BS		 4729 if (IS_IMM)
4730 goto illegal_insn;
4731 if (!supervisor(dc))
4732 goto priv_insn;
4733#endif
66442b07 4734 save_state(dc);
6ae20372 4735 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4736 break;
b89e94af 4737 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4738#ifndef TARGET_SPARC64
0f8a249a
BS		 4739 if (IS_IMM)
4740 goto illegal_insn;
4741 if (!supervisor(dc))
4742 goto priv_insn;
3475187d 4743#endif
66442b07 4744 save_state(dc);
6ae20372 4745 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4746 break;
4747 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4748#ifndef TARGET_SPARC64
0f8a249a
BS		 4749 if (IS_IMM)
4750 goto illegal_insn;
4751 if (!supervisor(dc))
4752 goto priv_insn;
4753#endif
66442b07 4754 save_state(dc);
6ae20372 4755 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4756 break;
b89e94af 4757 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4758 atomically */
64a88d5d 4759 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4760#ifndef TARGET_SPARC64
0f8a249a
BS		 4761 if (IS_IMM)
4762 goto illegal_insn;
4763 if (!supervisor(dc))
4764 goto priv_insn;
6ea4a6c8 4765#endif
66442b07 4766 save_state(dc);
06828032
RH		 4767 cpu_src1 = gen_load_gpr(dc, rd);
4768 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4769 break;
3475187d
FB		 4770
4771#ifndef TARGET_SPARC64
0f8a249a
BS		 4772 case 0x30: /* ldc */
4773 case 0x31: /* ldcsr */
4774 case 0x33: /* lddc */
4775 goto ncp_insn;
3475187d
FB		 4776#endif
4777#endif
4778#ifdef TARGET_SPARC64
0f8a249a 4779 case 0x08: /* V9 ldsw */
2cade6a3 4780 gen_address_mask(dc, cpu_addr);
6ae20372 4781 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4782 break;
4783 case 0x0b: /* V9 ldx */
2cade6a3 4784 gen_address_mask(dc, cpu_addr);
6ae20372 4785 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4786 break;
4787 case 0x18: /* V9 ldswa */
66442b07 4788 save_state(dc);
6ae20372 4789 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4790 break;
4791 case 0x1b: /* V9 ldxa */
66442b07 4792 save_state(dc);
6ae20372 4793 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4794 break;
4795 case 0x2d: /* V9 prefetch, no effect */
4796 goto skip_move;
4797 case 0x30: /* V9 ldfa */
5b12f1e8 4798 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4799 goto jmp_insn;
4800 }
66442b07 4801 save_state(dc);
6ae20372 4802 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4803 gen_update_fprs_dirty(rd);
81ad8ba2 4804 goto skip_move;
0f8a249a 4805 case 0x33: /* V9 lddfa */
5b12f1e8 4806 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4807 goto jmp_insn;
4808 }
66442b07 4809 save_state(dc);
6ae20372 4810 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4811 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4812 goto skip_move;
0f8a249a
BS		 4813 case 0x3d: /* V9 prefetcha, no effect */
4814 goto skip_move;
4815 case 0x32: /* V9 ldqfa */
64a88d5d 4816 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4817 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4818 goto jmp_insn;
4819 }
66442b07 4820 save_state(dc);
6ae20372 4821 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4822 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4823 goto skip_move;
0f8a249a
BS		 4824#endif
4825 default:
4826 goto illegal_insn;
4827 }
97ea2859 4828 gen_store_gpr(dc, rd, cpu_val);
db166940 4829#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4830 skip_move: ;
3475187d 4831#endif
0f8a249a 4832 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4833 TCGv t0;
4834
5b12f1e8 4835 if (gen_trap_ifnofpu(dc)) {
a80dde08 4836 goto jmp_insn;
5b12f1e8 4837 }
66442b07 4838 save_state(dc);
0f8a249a 4839 switch (xop) {
b89e94af 4840 case 0x20: /* ldf, load fpreg */
2cade6a3 4841 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4842 t0 = get_temp_tl(dc);
4843 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4844 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4845 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4846 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4847 break;
3a3b925d
BS		 4848 case 0x21: /* ldfsr, V9 ldxfsr */
4849#ifdef TARGET_SPARC64
2cade6a3 4850 gen_address_mask(dc, cpu_addr);
3a3b925d 4851 if (rd == 1) {
abcc7191
RH		 4852 TCGv_i64 t64 = tcg_temp_new_i64();
4853 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4854 gen_helper_ldxfsr(cpu_env, t64);
4855 tcg_temp_free_i64(t64);
f8641947 4856 break;
fe987e23 4857 }
f8641947 4858#endif
de9e9d9f
RH		 4859 cpu_dst_32 = get_temp_i32(dc);
4860 t0 = get_temp_tl(dc);
4861 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4862 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4863 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4864 break;
b89e94af 4865 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4866 {
a7812ae4 4867 TCGv_i32 r_const;
2ea815ca
BS		 4868
4869 CHECK_FPU_FEATURE(dc, FLOAT128);
4870 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4871 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4872 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4873 tcg_temp_free_i32(r_const);
2ea815ca 4874 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4875 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4876 }
1f587329 4877 break;
b89e94af 4878 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4879 gen_address_mask(dc, cpu_addr);
3886b8a3 4880 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4881 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4882 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4883 break;
4884 default:
4885 goto illegal_insn;
4886 }
dc1a6971 4887 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4888 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4889 TCGv cpu_val = gen_load_gpr(dc, rd);
4890
0f8a249a 4891 switch (xop) {
b89e94af 4892 case 0x4: /* st, store word */
2cade6a3 4893 gen_address_mask(dc, cpu_addr);
6ae20372 4894 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4895 break;
b89e94af 4896 case 0x5: /* stb, store byte */
2cade6a3 4897 gen_address_mask(dc, cpu_addr);
6ae20372 4898 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4899 break;
b89e94af 4900 case 0x6: /* sth, store halfword */
2cade6a3 4901 gen_address_mask(dc, cpu_addr);
6ae20372 4902 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4903 break;
b89e94af 4904 case 0x7: /* std, store double word */
0f8a249a 4905 if (rd & 1)
d4218d99 4906 goto illegal_insn;
1a2fb1c0 4907 else {
a7812ae4 4908 TCGv_i32 r_const;
abcc7191 4909 TCGv_i64 t64;
81634eea 4910 TCGv lo;
1a2fb1c0 4911
66442b07 4912 save_state(dc);
2cade6a3 4913 gen_address_mask(dc, cpu_addr);
2ea815ca 4914 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4915 /* XXX remove alignment check */
4916 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4917 tcg_temp_free_i32(r_const);
81634eea 4918 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4919
4920 t64 = tcg_temp_new_i64();
4921 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4922 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4923 tcg_temp_free_i64(t64);
7fa76c0b 4924 }
0f8a249a 4925 break;
3475187d 4926#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4927 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4928#ifndef TARGET_SPARC64
0f8a249a
BS		 4929 if (IS_IMM)
4930 goto illegal_insn;
4931 if (!supervisor(dc))
4932 goto priv_insn;
6ea4a6c8 4933#endif
66442b07 4934 save_state(dc);
6ae20372 4935 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4936 dc->npc = DYNAMIC_PC;
d39c0b99 4937 break;
b89e94af 4938 case 0x15: /* stba, store byte alternate */
3475187d 4939#ifndef TARGET_SPARC64
0f8a249a
BS		 4940 if (IS_IMM)
4941 goto illegal_insn;
4942 if (!supervisor(dc))
4943 goto priv_insn;
3475187d 4944#endif
66442b07 4945 save_state(dc);
6ae20372 4946 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4947 dc->npc = DYNAMIC_PC;
d39c0b99 4948 break;
b89e94af 4949 case 0x16: /* stha, store halfword alternate */
3475187d 4950#ifndef TARGET_SPARC64
0f8a249a
BS		 4951 if (IS_IMM)
4952 goto illegal_insn;
4953 if (!supervisor(dc))
4954 goto priv_insn;
6ea4a6c8 4955#endif
66442b07 4956 save_state(dc);
6ae20372 4957 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4958 dc->npc = DYNAMIC_PC;
d39c0b99 4959 break;
b89e94af 4960 case 0x17: /* stda, store double word alternate */
3475187d 4961#ifndef TARGET_SPARC64
0f8a249a
BS		 4962 if (IS_IMM)
4963 goto illegal_insn;
4964 if (!supervisor(dc))
4965 goto priv_insn;
3475187d 4966#endif
0f8a249a 4967 if (rd & 1)
d4218d99 4968 goto illegal_insn;
1a2fb1c0 4969 else {
66442b07 4970 save_state(dc);
c7785e16 4971 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4972 }
d39c0b99 4973 break;
e80cfcfc 4974#endif
3475187d 4975#ifdef TARGET_SPARC64
0f8a249a 4976 case 0x0e: /* V9 stx */
2cade6a3 4977 gen_address_mask(dc, cpu_addr);
6ae20372 4978 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4979 break;
4980 case 0x1e: /* V9 stxa */
66442b07 4981 save_state(dc);
6ae20372 4982 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4983 dc->npc = DYNAMIC_PC;
0f8a249a 4984 break;
3475187d 4985#endif
0f8a249a
BS		 4986 default:
4987 goto illegal_insn;
4988 }
4989 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4990 if (gen_trap_ifnofpu(dc)) {
a80dde08 4991 goto jmp_insn;
5b12f1e8 4992 }
66442b07 4993 save_state(dc);
0f8a249a 4994 switch (xop) {
b89e94af 4995 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 4996 {
4997 TCGv t = get_temp_tl(dc);
4998 gen_address_mask(dc, cpu_addr);
4999 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5000 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5001 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5002 }
0f8a249a
BS		 5003 break;
5004 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5005 {
5006 TCGv t = get_temp_tl(dc);
5007
5008 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5009#ifdef TARGET_SPARC64
f8641947
RH		 5010 gen_address_mask(dc, cpu_addr);
5011 if (rd == 1) {
5012 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5013 break;
5014 }
3a3b925d 5015#endif
f8641947
RH		 5016 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5017 }
0f8a249a 5018 break;
1f587329
BS		 5019 case 0x26:
5020#ifdef TARGET_SPARC64
1f587329 5021 /* V9 stqf, store quad fpreg */
2ea815ca 5022 {
a7812ae4 5023 TCGv_i32 r_const;
2ea815ca
BS		 5024
5025 CHECK_FPU_FEATURE(dc, FLOAT128);
5026 gen_op_load_fpr_QT0(QFPREG(rd));
5027 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5028 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5029 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5030 tcg_temp_free_i32(r_const);
2ea815ca 5031 }
1f587329 5032 break;
1f587329
BS		 5033#else /* !TARGET_SPARC64 */
5034 /* stdfq, store floating point queue */
5035#if defined(CONFIG_USER_ONLY)
5036 goto illegal_insn;
5037#else
0f8a249a
BS		 5038 if (!supervisor(dc))
5039 goto priv_insn;
5b12f1e8 5040 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5041 goto jmp_insn;
5b12f1e8 5042 }
0f8a249a 5043 goto nfq_insn;
1f587329 5044#endif
0f8a249a 5045#endif
b89e94af 5046 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5047 gen_address_mask(dc, cpu_addr);
5048 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5049 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5050 break;
5051 default:
5052 goto illegal_insn;
5053 }
5054 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5055 save_state(dc);
0f8a249a 5056 switch (xop) {
a4d17f19 5057#ifdef TARGET_SPARC64
0f8a249a 5058 case 0x34: /* V9 stfa */
5b12f1e8 5059 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5060 goto jmp_insn;
5061 }
6ae20372 5062 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5063 break;
1f587329 5064 case 0x36: /* V9 stqfa */
2ea815ca 5065 {
a7812ae4 5066 TCGv_i32 r_const;
2ea815ca
BS		 5067
5068 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5069 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5070 goto jmp_insn;
5071 }
2ea815ca 5072 r_const = tcg_const_i32(7);
fe8d8f0f 5073 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5074 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5075 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5076 }
1f587329 5077 break;
0f8a249a 5078 case 0x37: /* V9 stdfa */
5b12f1e8 5079 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5080 goto jmp_insn;
5081 }
6ae20372 5082 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5083 break;
0f8a249a 5084 case 0x3e: /* V9 casxa */
a4273524
RH		 5085 rs2 = GET_FIELD(insn, 27, 31);
5086 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5087 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5088 break;
a4d17f19 5089#else
0f8a249a
BS		 5090 case 0x34: /* stc */
5091 case 0x35: /* stcsr */
5092 case 0x36: /* stdcq */
5093 case 0x37: /* stdc */
5094 goto ncp_insn;
16c358e9
SH		 5095#endif
5096#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5097 case 0x3c: /* V9 or LEON3 casa */
5098#ifndef TARGET_SPARC64
5099 CHECK_IU_FEATURE(dc, CASA);
5100 if (IS_IMM) {
5101 goto illegal_insn;
5102 }
5103 if (!supervisor(dc)) {
5104 goto priv_insn;
5105 }
5106#endif
5107 rs2 = GET_FIELD(insn, 27, 31);
5108 cpu_src2 = gen_load_gpr(dc, rs2);
5109 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5110 break;
0f8a249a
BS		 5111#endif
5112 default:
5113 goto illegal_insn;
5114 }
a4273524 5115 } else {
0f8a249a 5116 goto illegal_insn;
a4273524 5117 }
0f8a249a
BS		 5118 }
5119 break;
cf495bcf
FB		 5120 }
5121 /* default case for non jump instructions */
72cbca10 5122 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5123 dc->pc = DYNAMIC_PC;
5124 gen_op_next_insn();
72cbca10
FB		 5125 } else if (dc->npc == JUMP_PC) {
5126 /* we can do a static jump */
6ae20372 5127 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5128 dc->is_br = 1;
5129 } else {
0f8a249a
BS		 5130 dc->pc = dc->npc;
5131 dc->npc = dc->npc + 4;
cf495bcf 5132 }
e80cfcfc 5133 jmp_insn:
42a8aa83 5134 goto egress;
cf495bcf 5135 illegal_insn:
2ea815ca 5136 {
a7812ae4 5137 TCGv_i32 r_const;
2ea815ca 5138
66442b07 5139 save_state(dc);
2ea815ca 5140 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5141 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5142 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5143 dc->is_br = 1;
5144 }
42a8aa83 5145 goto egress;
64a88d5d 5146 unimp_flush:
2ea815ca 5147 {
a7812ae4 5148 TCGv_i32 r_const;
2ea815ca 5149
66442b07 5150 save_state(dc);
2ea815ca 5151 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5152 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5153 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5154 dc->is_br = 1;
5155 }
42a8aa83 5156 goto egress;
e80cfcfc 5157#if !defined(CONFIG_USER_ONLY)
e8af50a3 5158 priv_insn:
2ea815ca 5159 {
a7812ae4 5160 TCGv_i32 r_const;
2ea815ca 5161
66442b07 5162 save_state(dc);
2ea815ca 5163 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5164 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5165 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5166 dc->is_br = 1;
5167 }
42a8aa83 5168 goto egress;
64a88d5d 5169#endif
e80cfcfc 5170 nfpu_insn:
66442b07 5171 save_state(dc);
e80cfcfc
FB		 5172 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5173 dc->is_br = 1;
42a8aa83 5174 goto egress;
64a88d5d 5175#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5176 nfq_insn:
66442b07 5177 save_state(dc);
9143e598
BS		 5178 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5179 dc->is_br = 1;
42a8aa83 5180 goto egress;
9143e598 5181#endif
fcc72045
BS		 5182#ifndef TARGET_SPARC64
5183 ncp_insn:
2ea815ca
BS		 5184 {
5185 TCGv r_const;
5186
66442b07 5187 save_state(dc);
2ea815ca 5188 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5189 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5190 tcg_temp_free(r_const);
5191 dc->is_br = 1;
5192 }
42a8aa83 5193 goto egress;
fcc72045 5194#endif
42a8aa83 5195 egress:
30038fd8
RH		 5196 if (dc->n_t32 != 0) {
5197 int i;
5198 for (i = dc->n_t32 - 1; i >= 0; --i) {
5199 tcg_temp_free_i32(dc->t32[i]);
5200 }
5201 dc->n_t32 = 0;
5202 }
88023616
RH		 5203 if (dc->n_ttl != 0) {
5204 int i;
5205 for (i = dc->n_ttl - 1; i >= 0; --i) {
5206 tcg_temp_free(dc->ttl[i]);
5207 }
5208 dc->n_ttl = 0;
5209 }
7a3f1944
FB		 5210}
5211
68a47155
AF		 5212static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
5213 TranslationBlock *tb,
5214 bool spc)
7a3f1944 5215{
ed2803da 5216 CPUState *cs = CPU(cpu);
68a47155 5217 CPUSPARCState *env = &cpu->env;
72cbca10 5218 target_ulong pc_start, last_pc;
cf495bcf 5219 DisasContext dc1, *dc = &dc1;
a1d1bb31 5220 CPUBreakpoint *bp;
e8af50a3 5221 int j, lj = -1;
2e70f6ef
PB		 5222 int num_insns;
5223 int max_insns;
0184e266 5224 unsigned int insn;
cf495bcf
FB		 5225
5226 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5227 dc->tb = tb;
72cbca10 5228 pc_start = tb->pc;
cf495bcf 5229 dc->pc = pc_start;
e80cfcfc 5230 last_pc = dc->pc;
72cbca10 5231 dc->npc = (target_ulong) tb->cs_base;
8393617c 5232 dc->cc_op = CC_OP_DYNAMIC;
97ed5ccd 5233 dc->mem_idx = cpu_mmu_index(env, false);
5578ceab 5234 dc->def = env->def;
f838e2c5
BS		 5235 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5236 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5237 dc->singlestep = (cs->singlestep_enabled || singlestep);
cf495bcf 5238
2e70f6ef
PB		 5239 num_insns = 0;
5240 max_insns = tb->cflags & CF_COUNT_MASK;
5241 if (max_insns == 0)
5242 max_insns = CF_COUNT_MASK;
cd42d5b2 5243 gen_tb_start(tb);
cf495bcf 5244 do {
f0c3c505
AF		 5245 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
5246 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
a1d1bb31 5247 if (bp->pc == dc->pc) {
0f8a249a 5248 if (dc->pc != pc_start)
66442b07 5249 save_state(dc);
bc265319 5250 gen_helper_debug(cpu_env);
57fec1fe 5251 tcg_gen_exit_tb(0);
0f8a249a 5252 dc->is_br = 1;
e80cfcfc 5253 goto exit_gen_loop;
e8af50a3
FB		 5254 }
5255 }
5256 }
5257 if (spc) {
93fcfe39 5258 qemu_log("Search PC...\n");
fe700adb 5259 j = tcg_op_buf_count();
e8af50a3
FB		 5260 if (lj < j) {
5261 lj++;
5262 while (lj < j)
ab1103de 5263 tcg_ctx.gen_opc_instr_start[lj++] = 0;
25983cad 5264 tcg_ctx.gen_opc_pc[lj] = dc->pc;
e8af50a3 5265 gen_opc_npc[lj] = dc->npc;
ab1103de 5266 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 5267 tcg_ctx.gen_opc_icount[lj] = num_insns;
e8af50a3
FB		 5268 }
5269 }
667b8e29 5270 tcg_gen_insn_start(dc->pc);
959082fc 5271 num_insns++;
667b8e29 5272
959082fc 5273 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5274 gen_io_start();
667b8e29
RH		 5275 }
5276
0f8a249a 5277 last_pc = dc->pc;
0184e266 5278 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5279
0184e266 5280 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5281
5282 if (dc->is_br)
5283 break;
5284 /* if the next PC is different, we abort now */
5285 if (dc->pc != (last_pc + 4))
5286 break;
d39c0b99
FB		 5287 /* if we reach a page boundary, we stop generation so that the
5288 PC of a TT_TFAULT exception is always in the right page */
5289 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5290 break;
e80cfcfc
FB		 5291 /* if single step mode, we generate only one instruction and
5292 generate an exception */
060718c1 5293 if (dc->singlestep) {
e80cfcfc
FB		 5294 break;
5295 }
fe700adb 5296 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5297 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5298 num_insns < max_insns);
e80cfcfc
FB		 5299
5300 exit_gen_loop:
b09b2fd3 5301 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5302 gen_io_end();
b09b2fd3 5303 }
72cbca10 5304 if (!dc->is_br) {
5fafdf24 5305 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5306 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5307 /* static PC and NPC: we can use direct chaining */
2f5680ee 5308 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5309 } else {
b09b2fd3 5310 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5311 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5312 }
934da7ee 5313 save_npc(dc);
57fec1fe 5314 tcg_gen_exit_tb(0);
72cbca10
FB		 5315 }
5316 }
806f352d 5317 gen_tb_end(tb, num_insns);
0a7df5da 5318
e8af50a3 5319 if (spc) {
fe700adb 5320 j = tcg_op_buf_count();
e8af50a3
FB		 5321 lj++;
5322 while (lj <= j)
ab1103de 5323 tcg_ctx.gen_opc_instr_start[lj++] = 0;
e8af50a3 5324#if 0
93fcfe39 5325 log_page_dump();
e8af50a3 5326#endif
c3278b7b
FB		 5327 gen_opc_jump_pc[0] = dc->jump_pc[0];
5328 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 5329 } else {
e80cfcfc 5330 tb->size = last_pc + 4 - pc_start;
2e70f6ef 5331 tb->icount = num_insns;
e8af50a3 5332 }
7a3f1944 5333#ifdef DEBUG_DISAS
8fec2b8c 5334 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5335 qemu_log("--------------\n");
5336 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5337 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5338 qemu_log("\n");
cf495bcf 5339 }
7a3f1944 5340#endif
7a3f1944
FB		 5341}
5342
2cfc5f17 5343void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5344{
68a47155 5345 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, false);
7a3f1944
FB		 5346}
5347
2cfc5f17 5348void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5349{
68a47155 5350 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, true);
7a3f1944
FB		 5351}
5352
c48fcb47 5353void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5354{
f5069b26 5355 unsigned int i;
c48fcb47 5356 static int inited;
f5069b26
BS		 5357 static const char * const gregnames[8] = {
5358 NULL, // g0 not used
5359 "g1",
5360 "g2",
5361 "g3",
5362 "g4",
5363 "g5",
5364 "g6",
5365 "g7",
5366 };
30038fd8
RH		 5367 static const char * const fregnames[32] = {
5368 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5369 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5370 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5371 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5372 };
aaed909a 5373
1a2fb1c0
BS		 5374 /* init various static tables */
5375 if (!inited) {
5376 inited = 1;
5377
a7812ae4
PB		 5378 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5379 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
c5f9864e 5380 offsetof(CPUSPARCState, regwptr),
a7812ae4 5381 "regwptr");
1a2fb1c0 5382#ifdef TARGET_SPARC64
c5f9864e 5383 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
a7812ae4 5384 "xcc");
c5f9864e 5385 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
a7812ae4 5386 "asi");
c5f9864e 5387 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
a7812ae4 5388 "fprs");
c5f9864e 5389 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
255e1fcb 5390 "gsr");
a7812ae4 5391 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5392 offsetof(CPUSPARCState, tick_cmpr),
255e1fcb 5393 "tick_cmpr");
a7812ae4 5394 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5395 offsetof(CPUSPARCState, stick_cmpr),
255e1fcb 5396 "stick_cmpr");
a7812ae4 5397 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5398 offsetof(CPUSPARCState, hstick_cmpr),
255e1fcb 5399 "hstick_cmpr");
c5f9864e 5400 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
255e1fcb 5401 "hintp");
c5f9864e 5402 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
a7812ae4 5403 "htba");
c5f9864e 5404 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
a7812ae4
PB		 5405 "hver");
5406 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5407 offsetof(CPUSPARCState, ssr), "ssr");
a7812ae4 5408 cpu_ver = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5409 offsetof(CPUSPARCState, version), "ver");
a7812ae4 5410 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
c5f9864e 5411 offsetof(CPUSPARCState, softint),
a7812ae4 5412 "softint");
255e1fcb 5413#else
c5f9864e 5414 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
255e1fcb 5415 "wim");
1a2fb1c0 5416#endif
c5f9864e 5417 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
77f193da 5418 "cond");
c5f9864e 5419 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
dc99a3f2 5420 "cc_src");
a7812ae4 5421 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5422 offsetof(CPUSPARCState, cc_src2),
d9bdab86 5423 "cc_src2");
c5f9864e 5424 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
dc99a3f2 5425 "cc_dst");
c5f9864e 5426 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
8393617c 5427 "cc_op");
c5f9864e 5428 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
a7812ae4 5429 "psr");
c5f9864e 5430 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
87e92502 5431 "fsr");
c5f9864e 5432 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
48d5c82b 5433 "pc");
c5f9864e 5434 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
a7812ae4 5435 "npc");
c5f9864e 5436 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
255e1fcb 5437#ifndef CONFIG_USER_ONLY
c5f9864e 5438 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
255e1fcb
BS		 5439 "tbr");
5440#endif
30038fd8 5441 for (i = 1; i < 8; i++) {
a7812ae4 5442 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5443 offsetof(CPUSPARCState, gregs[i]),
f5069b26 5444 gregnames[i]);
30038fd8
RH		 5445 }
5446 for (i = 0; i < TARGET_DPREGS; i++) {
5447 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
c5f9864e 5448 offsetof(CPUSPARCState, fpr[i]),
45c7b743 5449 fregnames[i]);
30038fd8 5450 }
1a2fb1c0 5451 }
658138bc 5452}
d2856f1a 5453
c5f9864e 5454void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos)
d2856f1a
AJ		 5455{
5456 target_ulong npc;
25983cad 5457 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a
AJ		 5458 npc = gen_opc_npc[pc_pos];
5459 if (npc == 1) {
5460 /* dynamic NPC: already stored */
5461 } else if (npc == 2) {
d7da2a10
BS		 5462 /* jump PC: use 'cond' and the jump targets of the translation */
5463 if (env->cond) {
d2856f1a 5464 env->npc = gen_opc_jump_pc[0];
d7da2a10 5465 } else {
d2856f1a 5466 env->npc = gen_opc_jump_pc[1];
d7da2a10 5467 }
d2856f1a
AJ		 5468 } else {
5469 env->npc = npc;
5470 }
5471}
Mirror of https://git.qemu.org/git/qemu.git