[people/ms/u-boot.git] / arch / arm / mach-sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <i2c.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

#ifdef CONFIG_MACH_SUN50I
#include <asm/armv8/mmu.h>

static struct mm_region sunxi_mem_map[] = {
	{
		/* SRAM, MMIO regions */
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE
	}, {
		/* RAM */
		.virt = 0x40000000UL,
		.phys = 0x40000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};
struct mm_region *mem_map = sunxi_mem_map;
#endif

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

#ifdef CONFIG_SPL_BUILD
static int spl_board_load_image(struct spl_boot_device *bootdev)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);

	return 0;
}
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
#endif

void s_init(void)
{
	/*
	 * Undocumented magic taken from boot0, without this DRAM
	 * access gets messed up (seems cache related).
	 * The boot0 sources describe this as: "config ema for cache sram"
	 */
#if defined CONFIG_MACH_SUN6I
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#elif defined CONFIG_MACH_SUN8I
	__maybe_unused uint version;

	/* Unlock sram version info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	/*
	 * Ideally this would be a switch case, but we do not know exactly
	 * which versions there are and which version needs which settings,
	 * so reproduce the per SoC code from the BSP.
	 */
#if defined CONFIG_MACH_SUN8I_A23
	if (version == 0x1650)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	else /* 0x1661 ? */
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#elif defined CONFIG_MACH_SUN8I_A33
	if (version != 0x1667)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif

#if defined CONFIG_MACH_SUN6I || \
    defined CONFIG_MACH_SUN7I || \
    defined CONFIG_MACH_SUN8I
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
	tzpc_init();
#endif

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();
	eth_init_board();
}

#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
u32 spl_boot_device(void)
{
	int boot_source;

	/*
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
	 */
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
		return BOOT_DEVICE_BOARD;

	boot_source = readb(SPL_ADDR + 0x28);
	switch (boot_source) {
	case SUNXI_BOOTED_FROM_MMC0:
		return BOOT_DEVICE_MMC1;
	case SUNXI_BOOTED_FROM_NAND:
		return BOOT_DEVICE_NAND;
	case SUNXI_BOOTED_FROM_MMC2:
		return BOOT_DEVICE_MMC2;
	case SUNXI_BOOTED_FROM_SPI:
		return BOOT_DEVICE_SPI;
	}

	panic("Unknown boot source %d\n", boot_source);
	return -1;		/* Never reached */
}

/*
 * Properly announce BOOT_DEVICE_BOARD as "FEL".
 * Overrides weak function from common/spl/spl.c
 */
void spl_board_announce_boot_device(void)
{
	printf("FEL");
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(const u32 boot_device)
{
	return MMCSD_MODE_RAW;
}

void board_init_f(ulong dummy)
{
	spl_init();
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

void reset_cpu(ulong addr)
{
#ifdef CONFIG_SUNXI_GEN_SUN4I
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
a151403f	14	#include <mmc.h>
6620377e	15	#include <i2c.h>
cba69eee IC	16	#include <serial.h>
	17	#ifdef CONFIG_SPL_BUILD
	18	#include <spl.h>
	19	#endif
	20	#include <asm/gpio.h>
	21	#include <asm/io.h>
	22	#include <asm/arch/clock.h>
	23	#include <asm/arch/gpio.h>
af654d14	24	#include <asm/arch/spl.h>
cba69eee IC	25	#include <asm/arch/sys_proto.h>
cba69eee IC	26	#include <asm/arch/timer.h>
92369844	27	#include <asm/arch/tzpc.h>
a151403f	28	#include <asm/arch/mmc.h>
cba69eee	29
799aff38 IC	30	#include <linux/compiler.h>
799aff38 IC	31
942cb0b6 SG	32	struct fel_stash {
	33	uint32_t sp;
	34	uint32_t lr;
840fe95c SS	35	uint32_t cpsr;
	36	uint32_t sctlr;
	37	uint32_t vbar;
	38	uint32_t cr;
942cb0b6 SG	39	};
	40
	41	struct fel_stash fel_stash __attribute__((section(".data")));
	42
d96ebc46 SS	43	#ifdef CONFIG_MACH_SUN50I
	44	#include <asm/armv8/mmu.h>
	45
	46	static struct mm_region sunxi_mem_map[] = {
	47	{
	48	/* SRAM, MMIO regions */
cd4b0c5f YS	49	.virt = 0x0UL,
cd4b0c5f YS	50	.phys = 0x0UL,
d96ebc46 SS	51	.size = 0x40000000UL,
	52	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	53	PTE_BLOCK_NON_SHARE
	54	}, {
	55	/* RAM */
cd4b0c5f YS	56	.virt = 0x40000000UL,
cd4b0c5f YS	57	.phys = 0x40000000UL,
d96ebc46 SS	58	.size = 0x80000000UL,
	59	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	60	PTE_BLOCK_INNER_SHARE
	61	}, {
	62	/* List terminator */
	63	0,
	64	}
	65	};
	66	struct mm_region *mem_map = sunxi_mem_map;
	67	#endif
	68
f630974c	69	static int gpio_init(void)
cba69eee	70	{
ff2b47f6	71	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
ed41e62f	72	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
ff2b47f6 CYT	73	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	74	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	75	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	76	#endif
487b3277	77	#if defined(CONFIG_MACH_SUN8I)
6ad8c743 CYT	78	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
6ad8c743 CYT	79	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
487b3277	80	#else
6ad8c743 CYT	81	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
6ad8c743 CYT	82	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
487b3277	83	#endif
ff2b47f6	84	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
ed41e62f	85	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I))
487b3277 PK	86	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	87	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	88	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	89	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	90	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	91	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	92	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	93	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	94	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	95	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	96	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
e506889c CYT	97	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	98	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	99	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	100	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
1c27b7dc JK	101	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	102	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	103	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	104	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
d96ebc46 SS	105	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	106	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	107	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	108	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
d5a3357f	109	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	110	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	111	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	112	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
1871a8ca HG	113	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	114	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	115	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	116	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	117	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	118	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	119	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	120	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	121	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	122	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	123	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	124	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	125	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	126	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	127	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	128	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	129	#else
	130	#error Unsupported console port number. Please fix pin mux settings in board.c
	131	#endif
cba69eee IC	132
	133	return 0;
	134	}
	135
97d9df0a SG	136	#ifdef CONFIG_SPL_BUILD
97d9df0a SG	137	static int spl_board_load_image(struct spl_boot_device *bootdev)
942cb0b6 SG	138	{
	139	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	140	return_to_fel(fel_stash.sp, fel_stash.lr);
36afd451 NK	141
36afd451 NK	142	return 0;
942cb0b6	143	}
97d9df0a SG	144	SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
97d9df0a SG	145	#endif
942cb0b6	146
b56f6e2b	147	void s_init(void)
f630974c	148	{
583fede8 HG	149	/*
	150	* Undocumented magic taken from boot0, without this DRAM
	151	* access gets messed up (seems cache related).
	152	* The boot0 sources describe this as: "config ema for cache sram"
	153	*/
	154	#if defined CONFIG_MACH_SUN6I
f630974c	155	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
5f8afd70 HG	156	#elif defined CONFIG_MACH_SUN8I
5f8afd70 HG	157	__maybe_unused uint version;
583fede8 HG	158
	159	/* Unlock sram version info reg, read it, relock */
	160	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
5f8afd70	161	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
583fede8 HG	162	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
583fede8 HG	163
5f8afd70 HG	164	/*
	165	* Ideally this would be a switch case, but we do not know exactly
	166	* which versions there are and which version needs which settings,
	167	* so reproduce the per SoC code from the BSP.
	168	*/
	169	#if defined CONFIG_MACH_SUN8I_A23
	170	if (version == 0x1650)
583fede8 HG	171	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	172	else /* 0x1661 ? */
	173	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
5f8afd70 HG	174	#elif defined CONFIG_MACH_SUN8I_A33
	175	if (version != 0x1667)
	176	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
	177	#endif
	178	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	179	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
f630974c	180	#endif
583fede8	181
92bcc6cb HG	182	#if defined CONFIG_MACH_SUN6I \|\| \
	183	defined CONFIG_MACH_SUN7I \|\| \
	184	defined CONFIG_MACH_SUN8I
f630974c SG	185	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	186	asm volatile(
	187	"mrc p15, 0, r0, c1, c0, 1\n"
	188	"orr r0, r0, #1 << 6\n"
	189	"mcr p15, 0, r0, c1, c0, 1\n");
	190	#endif
5823664f CYT	191	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_H3
5823664f CYT	192	/* Enable non-secure access to some peripherals */
92369844 CYT	193	tzpc_init();
92369844 CYT	194	#endif
f630974c SG	195
	196	clock_init();
	197	timer_init();
	198	gpio_init();
	199	i2c_init_board();
fc8991c6	200	eth_init_board();
b56f6e2b	201	}
f630974c	202
b56f6e2b	203	#ifdef CONFIG_SPL_BUILD
a151403f DK	204	DECLARE_GLOBAL_DATA_PTR;
a151403f DK	205
b56f6e2b HG	206	/* The sunxi internal brom will try to loader external bootloader
b56f6e2b HG	207	* from mmc0, nand flash, mmc2.
b56f6e2b HG	208	*/
	209	u32 spl_boot_device(void)
	210	{
ef36d9ae HG	211	int boot_source;
ef36d9ae HG	212
840fe95c	213	/*
a151403f DK	214	* When booting from the SD card or NAND memory, the "eGON.BT0"
	215	* signature is expected to be found in memory at the address 0x0004
	216	* (see the "mksunxiboot" tool, which generates this header).
840fe95c SS	217	*
	218	* When booting in the FEL mode over USB, this signature is patched in
	219	* memory and replaced with something else by the 'fel' tool. This other
	220	* signature is selected in such a way, that it can't be present in a
	221	* valid bootable SD card image (because the BROM would refuse to
	222	* execute the SPL in this case).
	223	*
a151403f DK	224	* This checks for the signature and if it is not found returns to
	225	* the FEL code in the BROM to wait and receive the main u-boot
	226	* binary over USB. If it is found, it determines where SPL was
	227	* read from.
840fe95c	228	*/
af654d14	229	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
942cb0b6	230	return BOOT_DEVICE_BOARD;
a151403f	231
ef36d9ae HG	232	boot_source = readb(SPL_ADDR + 0x28);
	233	switch (boot_source) {
	234	case SUNXI_BOOTED_FROM_MMC0:
a151403f	235	return BOOT_DEVICE_MMC1;
ef36d9ae	236	case SUNXI_BOOTED_FROM_NAND:
a151403f	237	return BOOT_DEVICE_NAND;
ef36d9ae HG	238	case SUNXI_BOOTED_FROM_MMC2:
	239	return BOOT_DEVICE_MMC2;
	240	case SUNXI_BOOTED_FROM_SPI:
	241	return BOOT_DEVICE_SPI;
a151403f DK	242	}
a151403f DK	243
ef36d9ae	244	panic("Unknown boot source %d\n", boot_source);
a151403f	245	return -1; /* Never reached */
b56f6e2b HG	246	}
b56f6e2b HG	247
28d68045 BN	248	/*
	249	* Properly announce BOOT_DEVICE_BOARD as "FEL".
	250	* Overrides weak function from common/spl/spl.c
	251	*/
	252	void spl_board_announce_boot_device(void)
	253	{
	254	printf("FEL");
	255	}
	256
b56f6e2b	257	/* No confirmation data available in SPL yet. Hardcode bootmode */
2b1cdafa	258	u32 spl_boot_mode(const u32 boot_device)
b56f6e2b HG	259	{
	260	return MMCSD_MODE_RAW;
	261	}
	262
	263	void board_init_f(ulong dummy)
	264	{
6d0bdfdd	265	spl_init();
f630974c SG	266	preloader_console_init();
	267
	268	#ifdef CONFIG_SPL_I2C_SUPPORT
	269	/* Needed early by sunxi_board_init if PMU is enabled */
	270	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	271	#endif
	272	sunxi_board_init();
f630974c SG	273	}
	274	#endif
	275
cba69eee IC	276	void reset_cpu(ulong addr)
cba69eee IC	277	{
44d8ae5b	278	#ifdef CONFIG_SUNXI_GEN_SUN4I
c7e79dec HG	279	static const struct sunxi_wdog *wdog =
	280	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	281
	282	/* Set the watchdog for its shortest interval (.5s) and wait */
	283	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	284	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	285
	286	while (1) {
	287	/* sun5i sometimes gets stuck without this */
	288	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	289	}
44d8ae5b HG	290	#endif
44d8ae5b HG	291	#ifdef CONFIG_SUNXI_GEN_SUN6I
78c396a1 CYT	292	static const struct sunxi_wdog *wdog =
	293	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	294
	295	/* Set the watchdog for its shortest interval (.5s) and wait */
	296	writel(WDT_CFG_RESET, &wdog->cfg);
	297	writel(WDT_MODE_EN, &wdog->mode);
	298	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	299	while (1) { }
78c396a1	300	#endif
cba69eee IC	301	}
cba69eee IC	302
d96ebc46	303	#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
cba69eee IC	304	void enable_caches(void)
	305	{
	306	/* Enable D-cache. I-cache is already enabled in start.S */
	307	dcache_enable();
	308	}
	309	#endif