[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <i2c.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

int spl_board_load_image(void)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);

	return 0;
}

void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
	/* Magic (undocmented) value taken from boot0, without this DRAM
	 * access gets messed up (seems cache related) */
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if defined CONFIG_MACH_SUN6I || \
    defined CONFIG_MACH_SUN7I || \
    defined CONFIG_MACH_SUN8I
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
	tzpc_init();
#endif

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();
}

#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
u32 spl_boot_device(void)
{
	__maybe_unused struct mmc *mmc0, *mmc1;
	/*
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
	 */
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
		return BOOT_DEVICE_BOARD;

	/* The BROM will try to boot from mmc0 first, so try that first. */
#ifdef CONFIG_MMC
	mmc_initialize(gd->bd);
	mmc0 = find_mmc_device(0);
	if (sunxi_mmc_has_egon_boot_signature(mmc0))
		return BOOT_DEVICE_MMC1;
#endif

	/* Fallback to booting NAND if enabled. */
	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
		return BOOT_DEVICE_NAND;

#ifdef CONFIG_MMC
	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
		mmc1 = find_mmc_device(1);
		if (sunxi_mmc_has_egon_boot_signature(mmc1))
			return BOOT_DEVICE_MMC2;
	}
#endif

	panic("Could not determine boot source\n");
	return -1;		/* Never reached */
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
	return MMCSD_MODE_RAW;
}

void board_init_f(ulong dummy)
{
	spl_init();
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

void reset_cpu(ulong addr)
{
#ifdef CONFIG_SUNXI_GEN_SUN4I
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#ifdef CONFIG_CMD_NET
/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
	__maybe_unused int rc;

#ifdef CONFIG_MACPWR
	gpio_request(CONFIG_MACPWR, "macpwr");
	gpio_direction_output(CONFIG_MACPWR, 1);
	mdelay(200);
#endif

#ifdef CONFIG_SUNXI_GMAC
	rc = sunxi_gmac_initialize(bis);
	if (rc < 0) {
		printf("sunxi: failed to initialize gmac\n");
		return rc;
	}
#endif

	return 0;
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
a151403f	14	#include <mmc.h>
6620377e	15	#include <i2c.h>
cba69eee IC	16	#include <serial.h>
	17	#ifdef CONFIG_SPL_BUILD
	18	#include <spl.h>
	19	#endif
	20	#include <asm/gpio.h>
	21	#include <asm/io.h>
	22	#include <asm/arch/clock.h>
	23	#include <asm/arch/gpio.h>
af654d14	24	#include <asm/arch/spl.h>
cba69eee IC	25	#include <asm/arch/sys_proto.h>
cba69eee IC	26	#include <asm/arch/timer.h>
92369844	27	#include <asm/arch/tzpc.h>
a151403f	28	#include <asm/arch/mmc.h>
cba69eee	29
799aff38 IC	30	#include <linux/compiler.h>
799aff38 IC	31
942cb0b6 SG	32	struct fel_stash {
	33	uint32_t sp;
	34	uint32_t lr;
840fe95c SS	35	uint32_t cpsr;
	36	uint32_t sctlr;
	37	uint32_t vbar;
	38	uint32_t cr;
942cb0b6 SG	39	};
	40
	41	struct fel_stash fel_stash __attribute__((section(".data")));
	42
f630974c	43	static int gpio_init(void)
cba69eee	44	{
ff2b47f6	45	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
ed41e62f	46	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
ff2b47f6 CYT	47	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	48	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	49	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	50	#endif
487b3277	51	#if defined(CONFIG_MACH_SUN8I)
6ad8c743 CYT	52	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
6ad8c743 CYT	53	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
487b3277	54	#else
6ad8c743 CYT	55	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
6ad8c743 CYT	56	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
487b3277	57	#endif
ff2b47f6	58	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
ed41e62f	59	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I))
487b3277 PK	60	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	61	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	62	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	63	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	64	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	65	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	66	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	67	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	68	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	69	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	70	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
e506889c CYT	71	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	72	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	73	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	74	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
1c27b7dc JK	75	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	76	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	77	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	78	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
d5a3357f	79	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	80	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	81	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	82	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
1871a8ca HG	83	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	84	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	85	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	86	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	87	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	88	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	89	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	90	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	91	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	92	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	93	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	94	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	95	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	96	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	97	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	98	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	99	#else
	100	#error Unsupported console port number. Please fix pin mux settings in board.c
	101	#endif
cba69eee IC	102
	103	return 0;
	104	}
	105
36afd451	106	int spl_board_load_image(void)
942cb0b6 SG	107	{
	108	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	109	return_to_fel(fel_stash.sp, fel_stash.lr);
36afd451 NK	110
36afd451 NK	111	return 0;
942cb0b6 SG	112	}
942cb0b6 SG	113
b56f6e2b	114	void s_init(void)
f630974c	115	{
5e6bacdb	116	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_A23
f630974c SG	117	/* Magic (undocmented) value taken from boot0, without this DRAM
	118	* access gets messed up (seems cache related) */
	119	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	120	#endif
92bcc6cb HG	121	#if defined CONFIG_MACH_SUN6I \|\| \
	122	defined CONFIG_MACH_SUN7I \|\| \
	123	defined CONFIG_MACH_SUN8I
f630974c SG	124	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	125	asm volatile(
	126	"mrc p15, 0, r0, c1, c0, 1\n"
	127	"orr r0, r0, #1 << 6\n"
	128	"mcr p15, 0, r0, c1, c0, 1\n");
	129	#endif
5823664f CYT	130	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_H3
5823664f CYT	131	/* Enable non-secure access to some peripherals */
92369844 CYT	132	tzpc_init();
92369844 CYT	133	#endif
f630974c SG	134
	135	clock_init();
	136	timer_init();
	137	gpio_init();
	138	i2c_init_board();
b56f6e2b	139	}
f630974c	140
b56f6e2b	141	#ifdef CONFIG_SPL_BUILD
a151403f DK	142	DECLARE_GLOBAL_DATA_PTR;
a151403f DK	143
b56f6e2b HG	144	/* The sunxi internal brom will try to loader external bootloader
b56f6e2b HG	145	* from mmc0, nand flash, mmc2.
b56f6e2b HG	146	*/
	147	u32 spl_boot_device(void)
	148	{
f7d6b3cc	149	__maybe_unused struct mmc mmc0, mmc1;
840fe95c	150	/*
a151403f DK	151	* When booting from the SD card or NAND memory, the "eGON.BT0"
	152	* signature is expected to be found in memory at the address 0x0004
	153	* (see the "mksunxiboot" tool, which generates this header).
840fe95c SS	154	*
	155	* When booting in the FEL mode over USB, this signature is patched in
	156	* memory and replaced with something else by the 'fel' tool. This other
	157	* signature is selected in such a way, that it can't be present in a
	158	* valid bootable SD card image (because the BROM would refuse to
	159	* execute the SPL in this case).
	160	*
a151403f DK	161	* This checks for the signature and if it is not found returns to
	162	* the FEL code in the BROM to wait and receive the main u-boot
	163	* binary over USB. If it is found, it determines where SPL was
	164	* read from.
840fe95c	165	*/
af654d14	166	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
942cb0b6	167	return BOOT_DEVICE_BOARD;
a151403f DK	168
a151403f DK	169	/* The BROM will try to boot from mmc0 first, so try that first. */
f7d6b3cc	170	#ifdef CONFIG_MMC
a151403f DK	171	mmc_initialize(gd->bd);
	172	mmc0 = find_mmc_device(0);
	173	if (sunxi_mmc_has_egon_boot_signature(mmc0))
	174	return BOOT_DEVICE_MMC1;
f7d6b3cc	175	#endif
a151403f DK	176
	177	/* Fallback to booting NAND if enabled. */
	178	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
	179	return BOOT_DEVICE_NAND;
	180
f7d6b3cc	181	#ifdef CONFIG_MMC
a151403f DK	182	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
a151403f DK	183	mmc1 = find_mmc_device(1);
a1e56cf6	184	if (sunxi_mmc_has_egon_boot_signature(mmc1))
a151403f	185	return BOOT_DEVICE_MMC2;
a151403f	186	}
f7d6b3cc	187	#endif
a151403f DK	188
	189	panic("Could not determine boot source\n");
	190	return -1; /* Never reached */
b56f6e2b HG	191	}
	192
	193	/* No confirmation data available in SPL yet. Hardcode bootmode */
	194	u32 spl_boot_mode(void)
	195	{
	196	return MMCSD_MODE_RAW;
	197	}
	198
	199	void board_init_f(ulong dummy)
	200	{
6d0bdfdd	201	spl_init();
f630974c SG	202	preloader_console_init();
	203
	204	#ifdef CONFIG_SPL_I2C_SUPPORT
	205	/* Needed early by sunxi_board_init if PMU is enabled */
	206	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	207	#endif
	208	sunxi_board_init();
f630974c SG	209	}
	210	#endif
	211
cba69eee IC	212	void reset_cpu(ulong addr)
cba69eee IC	213	{
44d8ae5b	214	#ifdef CONFIG_SUNXI_GEN_SUN4I
c7e79dec HG	215	static const struct sunxi_wdog *wdog =
	216	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	217
	218	/* Set the watchdog for its shortest interval (.5s) and wait */
	219	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	220	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	221
	222	while (1) {
	223	/* sun5i sometimes gets stuck without this */
	224	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	225	}
44d8ae5b HG	226	#endif
44d8ae5b HG	227	#ifdef CONFIG_SUNXI_GEN_SUN6I
78c396a1 CYT	228	static const struct sunxi_wdog *wdog =
	229	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	230
	231	/* Set the watchdog for its shortest interval (.5s) and wait */
	232	writel(WDT_CFG_RESET, &wdog->cfg);
	233	writel(WDT_MODE_EN, &wdog->mode);
	234	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	235	while (1) { }
78c396a1	236	#endif
cba69eee IC	237	}
cba69eee IC	238
cba69eee IC	239	#ifndef CONFIG_SYS_DCACHE_OFF
	240	void enable_caches(void)
	241	{
	242	/* Enable D-cache. I-cache is already enabled in start.S */
	243	dcache_enable();
	244	}
	245	#endif
5835823d IC	246
	247	#ifdef CONFIG_CMD_NET
	248	/*
	249	* Initializes on-chip ethernet controllers.
	250	* to override, implement board_eth_init()
	251	*/
	252	int cpu_eth_init(bd_t *bis)
	253	{
799aff38	254	__maybe_unused int rc;
5835823d	255
fc703001	256	#ifdef CONFIG_MACPWR
8aeed956	257	gpio_request(CONFIG_MACPWR, "macpwr");
fc703001 HG	258	gpio_direction_output(CONFIG_MACPWR, 1);
	259	mdelay(200);
	260	#endif
	261
5835823d IC	262	#ifdef CONFIG_SUNXI_GMAC
	263	rc = sunxi_gmac_initialize(bis);
	264	if (rc < 0) {
	265	printf("sunxi: failed to initialize gmac\n");
	266	return rc;
	267	}
	268	#endif
	269
	270	return 0;
	271	}
	272	#endif