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KVM: x86: return all bits from get_interrupt_shadow
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
16a96021
MT		 109static bool backwards_tsc_observed = false;
110
18863bdd
AK		 111#define KVM_NR_SHARED_MSRS 16
112
113struct kvm_shared_msrs_global {
114 int nr;
2bf78fa7 115 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118struct kvm_shared_msrs {
119 struct user_return_notifier urn;
120 bool registered;
2bf78fa7
SY		 121 struct kvm_shared_msr_values {
122 u64 host;
123 u64 curr;
124 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 128static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 129
417bc304 130struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 131 { "pf_fixed", VCPU_STAT(pf_fixed) },
132 { "pf_guest", VCPU_STAT(pf_guest) },
133 { "tlb_flush", VCPU_STAT(tlb_flush) },
134 { "invlpg", VCPU_STAT(invlpg) },
135 { "exits", VCPU_STAT(exits) },
136 { "io_exits", VCPU_STAT(io_exits) },
137 { "mmio_exits", VCPU_STAT(mmio_exits) },
138 { "signal_exits", VCPU_STAT(signal_exits) },
139 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 140 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 141 { "halt_exits", VCPU_STAT(halt_exits) },
142 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 143 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 144 { "request_irq", VCPU_STAT(request_irq_exits) },
145 { "irq_exits", VCPU_STAT(irq_exits) },
146 { "host_state_reload", VCPU_STAT(host_state_reload) },
147 { "efer_reload", VCPU_STAT(efer_reload) },
148 { "fpu_reload", VCPU_STAT(fpu_reload) },
149 { "insn_emulation", VCPU_STAT(insn_emulation) },
150 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 151 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 152 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 153 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
154 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
155 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
156 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
157 { "mmu_flooded", VM_STAT(mmu_flooded) },
158 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 159 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 160 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 161 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 162 { "largepages", VM_STAT(lpages) },
417bc304
HB		 163 { NULL }
164};
165
2acf923e
DC		 166u64 __read_mostly host_xcr0;
167
b6785def 168static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 169
af585b92
GN		 170static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171{
172 int i;
173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
174 vcpu->arch.apf.gfns[i] = ~0;
175}
176
18863bdd
AK		 177static void kvm_on_user_return(struct user_return_notifier *urn)
178{
179 unsigned slot;
18863bdd
AK		 180 struct kvm_shared_msrs *locals
181 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 182 struct kvm_shared_msr_values *values;
18863bdd
AK		 183
184 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 185 values = &locals->values[slot];
186 if (values->host != values->curr) {
187 wrmsrl(shared_msrs_global.msrs[slot], values->host);
188 values->curr = values->host;
18863bdd
AK		 189 }
190 }
191 locals->registered = false;
192 user_return_notifier_unregister(urn);
193}
194
2bf78fa7 195static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 196{
18863bdd 197 u64 value;
013f6a5d
MT		 198 unsigned int cpu = smp_processor_id();
199 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 200
2bf78fa7
SY		 201 /* only read, and nobody should modify it at this time,
202 * so don't need lock */
203 if (slot >= shared_msrs_global.nr) {
204 printk(KERN_ERR "kvm: invalid MSR slot!");
205 return;
206 }
207 rdmsrl_safe(msr, &value);
208 smsr->values[slot].host = value;
209 smsr->values[slot].curr = value;
210}
211
212void kvm_define_shared_msr(unsigned slot, u32 msr)
213{
18863bdd
AK		 214 if (slot >= shared_msrs_global.nr)
215 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 216 shared_msrs_global.msrs[slot] = msr;
217 /* we need ensured the shared_msr_global have been updated */
218 smp_wmb();
18863bdd
AK		 219}
220EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
221
222static void kvm_shared_msr_cpu_online(void)
223{
224 unsigned i;
18863bdd
AK		 225
226 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 227 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 228}
229
d5696725 230void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 231{
013f6a5d
MT		 232 unsigned int cpu = smp_processor_id();
233 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 234
2bf78fa7 235 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 236 return;
2bf78fa7
SY		 237 smsr->values[slot].curr = value;
238 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 239 if (!smsr->registered) {
240 smsr->urn.on_user_return = kvm_on_user_return;
241 user_return_notifier_register(&smsr->urn);
242 smsr->registered = true;
243 }
244}
245EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
246
3548bab5
AK		 247static void drop_user_return_notifiers(void *ignore)
248{
013f6a5d
MT		 249 unsigned int cpu = smp_processor_id();
250 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 251
252 if (smsr->registered)
253 kvm_on_user_return(&smsr->urn);
254}
255
6866b83e
CO		 256u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
257{
8a5a87d9 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
58cb628d
JK		 262int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
263{
264 u64 old_state = vcpu->arch.apic_base &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 new_state = msr_info->data &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
269 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
270
271 if (!msr_info->host_initiated &&
272 ((msr_info->data & reserved_bits) != 0 ||
273 new_state == X2APIC_ENABLE ||
274 (new_state == MSR_IA32_APICBASE_ENABLE &&
275 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
276 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
277 old_state == 0)))
278 return 1;
279
280 kvm_lapic_set_base(vcpu, msr_info->data);
281 return 0;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_set_apic_base);
284
2605fc21 285asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 286{
287 /* Fault while not rebooting. We want the trace. */
288 BUG();
289}
290EXPORT_SYMBOL_GPL(kvm_spurious_fault);
291
3fd28fce
ED		 292#define EXCPT_BENIGN 0
293#define EXCPT_CONTRIBUTORY 1
294#define EXCPT_PF 2
295
296static int exception_class(int vector)
297{
298 switch (vector) {
299 case PF_VECTOR:
300 return EXCPT_PF;
301 case DE_VECTOR:
302 case TS_VECTOR:
303 case NP_VECTOR:
304 case SS_VECTOR:
305 case GP_VECTOR:
306 return EXCPT_CONTRIBUTORY;
307 default:
308 break;
309 }
310 return EXCPT_BENIGN;
311}
312
313static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 314 unsigned nr, bool has_error, u32 error_code,
315 bool reinject)
3fd28fce
ED		 316{
317 u32 prev_nr;
318 int class1, class2;
319
3842d135
AK		 320 kvm_make_request(KVM_REQ_EVENT, vcpu);
321
3fd28fce
ED		 322 if (!vcpu->arch.exception.pending) {
323 queue:
324 vcpu->arch.exception.pending = true;
325 vcpu->arch.exception.has_error_code = has_error;
326 vcpu->arch.exception.nr = nr;
327 vcpu->arch.exception.error_code = error_code;
3f0fd292 328 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 329 return;
330 }
331
332 /* to check exception */
333 prev_nr = vcpu->arch.exception.nr;
334 if (prev_nr == DF_VECTOR) {
335 /* triple fault -> shutdown */
a8eeb04a 336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 337 return;
338 }
339 class1 = exception_class(prev_nr);
340 class2 = exception_class(nr);
341 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
342 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
343 /* generate double fault per SDM Table 5-5 */
344 vcpu->arch.exception.pending = true;
345 vcpu->arch.exception.has_error_code = true;
346 vcpu->arch.exception.nr = DF_VECTOR;
347 vcpu->arch.exception.error_code = 0;
348 } else
349 /* replace previous exception with a new one in a hope
350 that instruction re-execution will regenerate lost
351 exception */
352 goto queue;
353}
354
298101da
AK		 355void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
356{
ce7ddec4 357 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 358}
359EXPORT_SYMBOL_GPL(kvm_queue_exception);
360
ce7ddec4
JR		 361void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
362{
363 kvm_multiple_exception(vcpu, nr, false, 0, true);
364}
365EXPORT_SYMBOL_GPL(kvm_requeue_exception);
366
db8fcefa 367void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 368{
db8fcefa
AP		 369 if (err)
370 kvm_inject_gp(vcpu, 0);
371 else
372 kvm_x86_ops->skip_emulated_instruction(vcpu);
373}
374EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 375
6389ee94 376void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 377{
378 ++vcpu->stat.pf_guest;
6389ee94
AK		 379 vcpu->arch.cr2 = fault->address;
380 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 381}
27d6c865 382EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 383
6389ee94 384void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 385{
6389ee94
AK		 386 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
387 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 388 else
6389ee94 389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 390}
391
3419ffc8
SY		 392void kvm_inject_nmi(struct kvm_vcpu *vcpu)
393{
7460fb4a
AK		 394 atomic_inc(&vcpu->arch.nmi_queued);
395 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 396}
397EXPORT_SYMBOL_GPL(kvm_inject_nmi);
398
298101da
AK		 399void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
400{
ce7ddec4 401 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 402}
403EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
404
ce7ddec4
JR		 405void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
406{
407 kvm_multiple_exception(vcpu, nr, true, error_code, true);
408}
409EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
410
0a79b009
AK		 411/*
412 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
413 * a #GP and return false.
414 */
415bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 416{
0a79b009
AK		 417 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
418 return true;
419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
420 return false;
298101da 421}
0a79b009 422EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 423
ec92fe44
JR		 424/*
425 * This function will be used to read from the physical memory of the currently
426 * running guest. The difference to kvm_read_guest_page is that this function
427 * can read from guest physical or from the guest's guest physical memory.
428 */
429int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
430 gfn_t ngfn, void *data, int offset, int len,
431 u32 access)
432{
433 gfn_t real_gfn;
434 gpa_t ngpa;
435
436 ngpa = gfn_to_gpa(ngfn);
437 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
438 if (real_gfn == UNMAPPED_GVA)
439 return -EFAULT;
440
441 real_gfn = gpa_to_gfn(real_gfn);
442
443 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
444}
445EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
446
3d06b8bf
JR		 447int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
448 void *data, int offset, int len, u32 access)
449{
450 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
451 data, offset, len, access);
452}
453
a03490ed
CO		 454/*
455 * Load the pae pdptrs. Return true is they are all valid.
456 */
ff03a073 457int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 458{
459 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
460 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
461 int i;
462 int ret;
ff03a073 463 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 464
ff03a073
JR		 465 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
466 offset * sizeof(u64), sizeof(pdpte),
467 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 468 if (ret < 0) {
469 ret = 0;
470 goto out;
471 }
472 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 473 if (is_present_gpte(pdpte[i]) &&
20c466b5 474 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 475 ret = 0;
476 goto out;
477 }
478 }
479 ret = 1;
480
ff03a073 481 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail);
484 __set_bit(VCPU_EXREG_PDPTR,
485 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 486out:
a03490ed
CO		 487
488 return ret;
489}
cc4b6871 490EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 491
d835dfec
AK		 492static bool pdptrs_changed(struct kvm_vcpu *vcpu)
493{
ff03a073 494 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 495 bool changed = true;
3d06b8bf
JR		 496 int offset;
497 gfn_t gfn;
d835dfec
AK		 498 int r;
499
500 if (is_long_mode(vcpu) || !is_pae(vcpu))
501 return false;
502
6de4f3ad
AK		 503 if (!test_bit(VCPU_EXREG_PDPTR,
504 (unsigned long *)&vcpu->arch.regs_avail))
505 return true;
506
9f8fe504
AK		 507 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
508 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 509 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
510 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 511 if (r < 0)
512 goto out;
ff03a073 513 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 514out:
d835dfec
AK		 515
516 return changed;
517}
518
49a9b07e 519int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 520{
aad82703
SY		 521 unsigned long old_cr0 = kvm_read_cr0(vcpu);
522 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
523 X86_CR0_CD | X86_CR0_NW;
524
f9a48e6a
AK		 525 cr0 |= X86_CR0_ET;
526
ab344828 527#ifdef CONFIG_X86_64
0f12244f
GN		 528 if (cr0 & 0xffffffff00000000UL)
529 return 1;
ab344828
GN		 530#endif
531
532 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 533
0f12244f
GN		 534 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
535 return 1;
a03490ed 536
0f12244f
GN		 537 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
538 return 1;
a03490ed
CO		 539
540 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
541#ifdef CONFIG_X86_64
f6801dff 542 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 543 int cs_db, cs_l;
544
0f12244f
GN		 545 if (!is_pae(vcpu))
546 return 1;
a03490ed 547 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 548 if (cs_l)
549 return 1;
a03490ed
CO		 550 } else
551#endif
ff03a073 552 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 553 kvm_read_cr3(vcpu)))
0f12244f 554 return 1;
a03490ed
CO		 555 }
556
ad756a16
MJ		 557 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
558 return 1;
559
a03490ed 560 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 561
d170c419 562 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 563 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 564 kvm_async_pf_hash_reset(vcpu);
565 }
e5f3f027 566
aad82703
SY		 567 if ((cr0 ^ old_cr0) & update_bits)
568 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 569 return 0;
570}
2d3ad1f4 571EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 572
2d3ad1f4 573void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 574{
49a9b07e 575 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 578
42bdf991
MT		 579static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
580{
581 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
582 !vcpu->guest_xcr0_loaded) {
583 /* kvm_set_xcr() also depends on this */
584 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
585 vcpu->guest_xcr0_loaded = 1;
586 }
587}
588
589static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
590{
591 if (vcpu->guest_xcr0_loaded) {
592 if (vcpu->arch.xcr0 != host_xcr0)
593 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
594 vcpu->guest_xcr0_loaded = 0;
595 }
596}
597
2acf923e
DC		 598int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599{
56c103ec
LJ		 600 u64 xcr0 = xcr;
601 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 602 u64 valid_bits;
2acf923e
DC		 603
604 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
605 if (index != XCR_XFEATURE_ENABLED_MASK)
606 return 1;
2acf923e
DC		 607 if (!(xcr0 & XSTATE_FP))
608 return 1;
609 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
610 return 1;
46c34cb0
PB		 611
612 /*
613 * Do not allow the guest to set bits that we do not support
614 * saving. However, xcr0 bit 0 is always set, even if the
615 * emulated CPU does not support XSAVE (see fx_init).
616 */
617 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
618 if (xcr0 & ~valid_bits)
2acf923e 619 return 1;
46c34cb0 620
390bd528
LJ		 621 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
622 return 1;
623
42bdf991 624 kvm_put_guest_xcr0(vcpu);
2acf923e 625 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 626
627 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
628 kvm_update_cpuid(vcpu);
2acf923e
DC		 629 return 0;
630}
631
632int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
633{
764bcbc5
Z		 634 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
635 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 636 kvm_inject_gp(vcpu, 0);
637 return 1;
638 }
639 return 0;
640}
641EXPORT_SYMBOL_GPL(kvm_set_xcr);
642
a83b29c6 643int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 644{
fc78f519 645 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 646 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
647 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 648 if (cr4 & CR4_RESERVED_BITS)
649 return 1;
a03490ed 650
2acf923e
DC		 651 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
652 return 1;
653
c68b734f
YW		 654 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
655 return 1;
656
97ec8c06
FW		 657 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
658 return 1;
659
afcbf13f 660 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 661 return 1;
662
a03490ed 663 if (is_long_mode(vcpu)) {
0f12244f
GN		 664 if (!(cr4 & X86_CR4_PAE))
665 return 1;
a2edf57f
AK		 666 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
667 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 668 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
0f12244f
GN		 670 return 1;
671
ad756a16
MJ		 672 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
673 if (!guest_cpuid_has_pcid(vcpu))
674 return 1;
675
676 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
677 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
678 return 1;
679 }
680
5e1746d6 681 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 682 return 1;
a03490ed 683
ad756a16
MJ		 684 if (((cr4 ^ old_cr4) & pdptr_bits) ||
685 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 686 kvm_mmu_reset_context(vcpu);
0f12244f 687
97ec8c06
FW		 688 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
689 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
690
2acf923e 691 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 692 kvm_update_cpuid(vcpu);
2acf923e 693
0f12244f
GN		 694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 697
2390218b 698int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 699{
9f8fe504 700 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 701 kvm_mmu_sync_roots(vcpu);
d835dfec 702 kvm_mmu_flush_tlb(vcpu);
0f12244f 703 return 0;
d835dfec
AK		 704 }
705
a03490ed 706 if (is_long_mode(vcpu)) {
d9f89b88
JK		 707 if (cr3 & CR3_L_MODE_RESERVED_BITS)
708 return 1;
709 } else if (is_pae(vcpu) && is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 711 return 1;
a03490ed 712
0f12244f 713 vcpu->arch.cr3 = cr3;
aff48baa 714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 715 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 716 return 0;
717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 719
eea1cff9 720int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 721{
0f12244f
GN		 722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
a03490ed
CO		 724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
ad312c7c 727 vcpu->arch.cr8 = cr8;
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 731
2d3ad1f4 732unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 733{
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
ad312c7c 737 return vcpu->arch.cr8;
a03490ed 738}
2d3ad1f4 739EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 740
73aaf249
JK		 741static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742{
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745}
746
c8639010
JK		 747static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748{
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 756 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
757 if (dr7 & DR7_BP_EN_MASK)
758 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 759}
760
338dbc97 761static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 762{
763 switch (dr) {
764 case 0 ... 3:
765 vcpu->arch.db[dr] = val;
766 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
767 vcpu->arch.eff_db[dr] = val;
768 break;
769 case 4:
338dbc97
GN		 770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
771 return 1; /* #UD */
020df079
GN		 772 /* fall through */
773 case 6:
338dbc97
GN		 774 if (val & 0xffffffff00000000ULL)
775 return -1; /* #GP */
020df079 776 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 777 kvm_update_dr6(vcpu);
020df079
GN		 778 break;
779 case 5:
338dbc97
GN		 780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 return 1; /* #UD */
020df079
GN		 782 /* fall through */
783 default: /* 7 */
338dbc97
GN		 784 if (val & 0xffffffff00000000ULL)
785 return -1; /* #GP */
020df079 786 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 787 kvm_update_dr7(vcpu);
020df079
GN		 788 break;
789 }
790
791 return 0;
792}
338dbc97
GN		 793
794int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
795{
796 int res;
797
798 res = __kvm_set_dr(vcpu, dr, val);
799 if (res > 0)
800 kvm_queue_exception(vcpu, UD_VECTOR);
801 else if (res < 0)
802 kvm_inject_gp(vcpu, 0);
803
804 return res;
805}
020df079
GN		 806EXPORT_SYMBOL_GPL(kvm_set_dr);
807
338dbc97 808static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 809{
810 switch (dr) {
811 case 0 ... 3:
812 *val = vcpu->arch.db[dr];
813 break;
814 case 4:
338dbc97 815 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 816 return 1;
020df079
GN		 817 /* fall through */
818 case 6:
73aaf249
JK		 819 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
820 *val = vcpu->arch.dr6;
821 else
822 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 823 break;
824 case 5:
338dbc97 825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 826 return 1;
020df079
GN		 827 /* fall through */
828 default: /* 7 */
829 *val = vcpu->arch.dr7;
830 break;
831 }
832
833 return 0;
834}
338dbc97
GN		 835
836int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
837{
838 if (_kvm_get_dr(vcpu, dr, val)) {
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 return 1;
841 }
842 return 0;
843}
020df079
GN		 844EXPORT_SYMBOL_GPL(kvm_get_dr);
845
022cd0e8
AK		 846bool kvm_rdpmc(struct kvm_vcpu *vcpu)
847{
848 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
849 u64 data;
850 int err;
851
852 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
853 if (err)
854 return err;
855 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
856 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
857 return err;
858}
859EXPORT_SYMBOL_GPL(kvm_rdpmc);
860
043405e1
CO		 861/*
862 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
863 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
864 *
865 * This list is modified at module load time to reflect the
e3267cbb
GC		 866 * capabilities of the host cpu. This capabilities test skips MSRs that are
867 * kvm-specific. Those are put in the beginning of the list.
043405e1 868 */
e3267cbb 869
e984097b 870#define KVM_SAVE_MSRS_BEGIN 12
043405e1 871static u32 msrs_to_save[] = {
e3267cbb 872 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 873 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 874 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 875 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 876 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 877 MSR_KVM_PV_EOI_EN,
043405e1 878 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 879 MSR_STAR,
043405e1
CO		 880#ifdef CONFIG_X86_64
881 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
882#endif
b3897a49 883 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 884 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 885};
886
887static unsigned num_msrs_to_save;
888
f1d24831 889static const u32 emulated_msrs[] = {
ba904635 890 MSR_IA32_TSC_ADJUST,
a3e06bbe 891 MSR_IA32_TSCDEADLINE,
043405e1 892 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 893 MSR_IA32_MCG_STATUS,
894 MSR_IA32_MCG_CTL,
043405e1
CO		 895};
896
384bb783 897bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 898{
b69e8cae 899 if (efer & efer_reserved_bits)
384bb783 900 return false;
15c4a640 901
1b2fd70c
AG		 902 if (efer & EFER_FFXSR) {
903 struct kvm_cpuid_entry2 *feat;
904
905 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 906 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 907 return false;
1b2fd70c
AG		 908 }
909
d8017474
AG		 910 if (efer & EFER_SVME) {
911 struct kvm_cpuid_entry2 *feat;
912
913 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 914 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 915 return false;
d8017474
AG		 916 }
917
384bb783
JK		 918 return true;
919}
920EXPORT_SYMBOL_GPL(kvm_valid_efer);
921
922static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
923{
924 u64 old_efer = vcpu->arch.efer;
925
926 if (!kvm_valid_efer(vcpu, efer))
927 return 1;
928
929 if (is_paging(vcpu)
930 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
931 return 1;
932
15c4a640 933 efer &= ~EFER_LMA;
f6801dff 934 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 935
a3d204e2
SY		 936 kvm_x86_ops->set_efer(vcpu, efer);
937
aad82703
SY		 938 /* Update reserved bits */
939 if ((efer ^ old_efer) & EFER_NX)
940 kvm_mmu_reset_context(vcpu);
941
b69e8cae 942 return 0;
15c4a640
CO		 943}
944
f2b4b7dd
JR		 945void kvm_enable_efer_bits(u64 mask)
946{
947 efer_reserved_bits &= ~mask;
948}
949EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
950
951
15c4a640
CO		 952/*
953 * Writes msr value into into the appropriate "register".
954 * Returns 0 on success, non-0 otherwise.
955 * Assumes vcpu_load() was already called.
956 */
8fe8ab46 957int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 958{
8fe8ab46 959 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 960}
961
313a3dc7
CO		 962/*
963 * Adapt set_msr() to msr_io()'s calling convention
964 */
965static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
966{
8fe8ab46
WA		 967 struct msr_data msr;
968
969 msr.data = *data;
970 msr.index = index;
971 msr.host_initiated = true;
972 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 973}
974
16e8d74d
MT		 975#ifdef CONFIG_X86_64
976struct pvclock_gtod_data {
977 seqcount_t seq;
978
979 struct { /* extract of a clocksource struct */
980 int vclock_mode;
981 cycle_t cycle_last;
982 cycle_t mask;
983 u32 mult;
984 u32 shift;
985 } clock;
986
987 /* open coded 'struct timespec' */
988 u64 monotonic_time_snsec;
989 time_t monotonic_time_sec;
990};
991
992static struct pvclock_gtod_data pvclock_gtod_data;
993
994static void update_pvclock_gtod(struct timekeeper *tk)
995{
996 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
997
998 write_seqcount_begin(&vdata->seq);
999
1000 /* copy pvclock gtod data */
1001 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1002 vdata->clock.cycle_last = tk->clock->cycle_last;
1003 vdata->clock.mask = tk->clock->mask;
1004 vdata->clock.mult = tk->mult;
1005 vdata->clock.shift = tk->shift;
1006
1007 vdata->monotonic_time_sec = tk->xtime_sec
1008 + tk->wall_to_monotonic.tv_sec;
1009 vdata->monotonic_time_snsec = tk->xtime_nsec
1010 + (tk->wall_to_monotonic.tv_nsec
1011 << tk->shift);
1012 while (vdata->monotonic_time_snsec >=
1013 (((u64)NSEC_PER_SEC) << tk->shift)) {
1014 vdata->monotonic_time_snsec -=
1015 ((u64)NSEC_PER_SEC) << tk->shift;
1016 vdata->monotonic_time_sec++;
1017 }
1018
1019 write_seqcount_end(&vdata->seq);
1020}
1021#endif
1022
1023
18068523
GOC		 1024static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1025{
9ed3c444
AK		 1026 int version;
1027 int r;
50d0a0f9 1028 struct pvclock_wall_clock wc;
923de3cf 1029 struct timespec boot;
18068523
GOC		 1030
1031 if (!wall_clock)
1032 return;
1033
9ed3c444
AK		 1034 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1035 if (r)
1036 return;
1037
1038 if (version & 1)
1039 ++version; /* first time write, random junk */
1040
1041 ++version;
18068523 1042
18068523
GOC		 1043 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1044
50d0a0f9
GH		 1045 /*
1046 * The guest calculates current wall clock time by adding
34c238a1 1047 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1048 * wall clock specified here. guest system time equals host
1049 * system time for us, thus we must fill in host boot time here.
1050 */
923de3cf 1051 getboottime(&boot);
50d0a0f9 1052
4b648665
BR		 1053 if (kvm->arch.kvmclock_offset) {
1054 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1055 boot = timespec_sub(boot, ts);
1056 }
50d0a0f9
GH		 1057 wc.sec = boot.tv_sec;
1058 wc.nsec = boot.tv_nsec;
1059 wc.version = version;
18068523
GOC		 1060
1061 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1062
1063 version++;
1064 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1065}
1066
50d0a0f9
GH		 1067static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1068{
1069 uint32_t quotient, remainder;
1070
1071 /* Don't try to replace with do_div(), this one calculates
1072 * "(dividend << 32) / divisor" */
1073 __asm__ ( "divl %4"
1074 : "=a" (quotient), "=d" (remainder)
1075 : "0" (0), "1" (dividend), "r" (divisor) );
1076 return quotient;
1077}
1078
5f4e3f88
ZA		 1079static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1080 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1081{
5f4e3f88 1082 uint64_t scaled64;
50d0a0f9
GH		 1083 int32_t shift = 0;
1084 uint64_t tps64;
1085 uint32_t tps32;
1086
5f4e3f88
ZA		 1087 tps64 = base_khz * 1000LL;
1088 scaled64 = scaled_khz * 1000LL;
50933623 1089 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1090 tps64 >>= 1;
1091 shift--;
1092 }
1093
1094 tps32 = (uint32_t)tps64;
50933623
JK		 1095 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1096 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1097 scaled64 >>= 1;
1098 else
1099 tps32 <<= 1;
50d0a0f9
GH		 1100 shift++;
1101 }
1102
5f4e3f88
ZA		 1103 *pshift = shift;
1104 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1105
5f4e3f88
ZA		 1106 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1107 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1108}
1109
759379dd
ZA		 1110static inline u64 get_kernel_ns(void)
1111{
1112 struct timespec ts;
1113
759379dd
ZA		 1114 ktime_get_ts(&ts);
1115 monotonic_to_bootbased(&ts);
1116 return timespec_to_ns(&ts);
50d0a0f9
GH		 1117}
1118
d828199e 1119#ifdef CONFIG_X86_64
16e8d74d 1120static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1121#endif
16e8d74d 1122
c8076604 1123static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1124unsigned long max_tsc_khz;
c8076604 1125
cc578287 1126static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1127{
cc578287
ZA		 1128 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1129 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1130}
1131
cc578287 1132static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1133{
cc578287
ZA		 1134 u64 v = (u64)khz * (1000000 + ppm);
1135 do_div(v, 1000000);
1136 return v;
1e993611
JR		 1137}
1138
cc578287 1139static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1140{
cc578287
ZA		 1141 u32 thresh_lo, thresh_hi;
1142 int use_scaling = 0;
217fc9cf 1143
03ba32ca
MT		 1144 /* tsc_khz can be zero if TSC calibration fails */
1145 if (this_tsc_khz == 0)
1146 return;
1147
c285545f
ZA		 1148 /* Compute a scale to convert nanoseconds in TSC cycles */
1149 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1150 &vcpu->arch.virtual_tsc_shift,
1151 &vcpu->arch.virtual_tsc_mult);
1152 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1153
1154 /*
1155 * Compute the variation in TSC rate which is acceptable
1156 * within the range of tolerance and decide if the
1157 * rate being applied is within that bounds of the hardware
1158 * rate. If so, no scaling or compensation need be done.
1159 */
1160 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1161 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1162 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1163 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1164 use_scaling = 1;
1165 }
1166 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1167}
1168
1169static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1170{
e26101b1 1171 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1172 vcpu->arch.virtual_tsc_mult,
1173 vcpu->arch.virtual_tsc_shift);
e26101b1 1174 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1175 return tsc;
1176}
1177
b48aa97e
MT		 1178void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1179{
1180#ifdef CONFIG_X86_64
1181 bool vcpus_matched;
1182 bool do_request = false;
1183 struct kvm_arch *ka = &vcpu->kvm->arch;
1184 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1185
1186 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1187 atomic_read(&vcpu->kvm->online_vcpus));
1188
1189 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1190 if (!ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (!vcpus_matched && ka->use_master_clock)
1194 do_request = 1;
1195
1196 if (do_request)
1197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1198
1199 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1200 atomic_read(&vcpu->kvm->online_vcpus),
1201 ka->use_master_clock, gtod->clock.vclock_mode);
1202#endif
1203}
1204
ba904635
WA		 1205static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1206{
1207 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1208 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1209}
1210
8fe8ab46 1211void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1212{
1213 struct kvm *kvm = vcpu->kvm;
f38e098f 1214 u64 offset, ns, elapsed;
99e3e30a 1215 unsigned long flags;
02626b6a 1216 s64 usdiff;
b48aa97e 1217 bool matched;
0d3da0d2 1218 bool already_matched;
8fe8ab46 1219 u64 data = msr->data;
99e3e30a 1220
038f8c11 1221 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1222 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1223 ns = get_kernel_ns();
f38e098f 1224 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1225
03ba32ca 1226 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1227 int faulted = 0;
1228
03ba32ca
MT		 1229 /* n.b - signed multiplication and division required */
1230 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1231#ifdef CONFIG_X86_64
03ba32ca 1232 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1233#else
03ba32ca 1234 /* do_div() only does unsigned */
8915aa27
MT		 1235 asm("1: idivl %[divisor]\n"
1236 "2: xor %%edx, %%edx\n"
1237 " movl $0, %[faulted]\n"
1238 "3:\n"
1239 ".section .fixup,\"ax\"\n"
1240 "4: movl $1, %[faulted]\n"
1241 " jmp 3b\n"
1242 ".previous\n"
1243
1244 _ASM_EXTABLE(1b, 4b)
1245
1246 : "=A"(usdiff), [faulted] "=r" (faulted)
1247 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1248
5d3cb0f6 1249#endif
03ba32ca
MT		 1250 do_div(elapsed, 1000);
1251 usdiff -= elapsed;
1252 if (usdiff < 0)
1253 usdiff = -usdiff;
8915aa27
MT		 1254
1255 /* idivl overflow => difference is larger than USEC_PER_SEC */
1256 if (faulted)
1257 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1258 } else
1259 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1260
1261 /*
5d3cb0f6
ZA		 1262 * Special case: TSC write with a small delta (1 second) of virtual
1263 * cycle time against real time is interpreted as an attempt to
1264 * synchronize the CPU.
1265 *
1266 * For a reliable TSC, we can match TSC offsets, and for an unstable
1267 * TSC, we add elapsed time in this computation. We could let the
1268 * compensation code attempt to catch up if we fall behind, but
1269 * it's better to try to match offsets from the beginning.
1270 */
02626b6a 1271 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1272 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1273 if (!check_tsc_unstable()) {
e26101b1 1274 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1275 pr_debug("kvm: matched tsc offset for %llu\n", data);
1276 } else {
857e4099 1277 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1278 data += delta;
1279 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1280 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1281 }
b48aa97e 1282 matched = true;
0d3da0d2 1283 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1284 } else {
1285 /*
1286 * We split periods of matched TSC writes into generations.
1287 * For each generation, we track the original measured
1288 * nanosecond time, offset, and write, so if TSCs are in
1289 * sync, we can match exact offset, and if not, we can match
4a969980 1290 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1291 *
1292 * These values are tracked in kvm->arch.cur_xxx variables.
1293 */
1294 kvm->arch.cur_tsc_generation++;
1295 kvm->arch.cur_tsc_nsec = ns;
1296 kvm->arch.cur_tsc_write = data;
1297 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1298 matched = false;
0d3da0d2 1299 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1300 kvm->arch.cur_tsc_generation, data);
f38e098f 1301 }
e26101b1
ZA		 1302
1303 /*
1304 * We also track th most recent recorded KHZ, write and time to
1305 * allow the matching interval to be extended at each write.
1306 */
f38e098f
ZA		 1307 kvm->arch.last_tsc_nsec = ns;
1308 kvm->arch.last_tsc_write = data;
5d3cb0f6 1309 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1310
b183aa58 1311 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1312
1313 /* Keep track of which generation this VCPU has synchronized to */
1314 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1315 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1316 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1317
ba904635
WA		 1318 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1319 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1320 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1321 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1322
1323 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1324 if (!matched) {
b48aa97e 1325 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1326 } else if (!already_matched) {
1327 kvm->arch.nr_vcpus_matched_tsc++;
1328 }
b48aa97e
MT		 1329
1330 kvm_track_tsc_matching(vcpu);
1331 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1332}
e26101b1 1333
99e3e30a
ZA		 1334EXPORT_SYMBOL_GPL(kvm_write_tsc);
1335
d828199e
MT		 1336#ifdef CONFIG_X86_64
1337
1338static cycle_t read_tsc(void)
1339{
1340 cycle_t ret;
1341 u64 last;
1342
1343 /*
1344 * Empirically, a fence (of type that depends on the CPU)
1345 * before rdtsc is enough to ensure that rdtsc is ordered
1346 * with respect to loads. The various CPU manuals are unclear
1347 * as to whether rdtsc can be reordered with later loads,
1348 * but no one has ever seen it happen.
1349 */
1350 rdtsc_barrier();
1351 ret = (cycle_t)vget_cycles();
1352
1353 last = pvclock_gtod_data.clock.cycle_last;
1354
1355 if (likely(ret >= last))
1356 return ret;
1357
1358 /*
1359 * GCC likes to generate cmov here, but this branch is extremely
1360 * predictable (it's just a funciton of time and the likely is
1361 * very likely) and there's a data dependence, so force GCC
1362 * to generate a branch instead. I don't barrier() because
1363 * we don't actually need a barrier, and if this function
1364 * ever gets inlined it will generate worse code.
1365 */
1366 asm volatile ("");
1367 return last;
1368}
1369
1370static inline u64 vgettsc(cycle_t *cycle_now)
1371{
1372 long v;
1373 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1374
1375 *cycle_now = read_tsc();
1376
1377 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1378 return v * gtod->clock.mult;
1379}
1380
1381static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1382{
1383 unsigned long seq;
1384 u64 ns;
1385 int mode;
1386 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1387
1388 ts->tv_nsec = 0;
1389 do {
1390 seq = read_seqcount_begin(&gtod->seq);
1391 mode = gtod->clock.vclock_mode;
1392 ts->tv_sec = gtod->monotonic_time_sec;
1393 ns = gtod->monotonic_time_snsec;
1394 ns += vgettsc(cycle_now);
1395 ns >>= gtod->clock.shift;
1396 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1397 timespec_add_ns(ts, ns);
1398
1399 return mode;
1400}
1401
1402/* returns true if host is using tsc clocksource */
1403static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1404{
1405 struct timespec ts;
1406
1407 /* checked again under seqlock below */
1408 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1409 return false;
1410
1411 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1412 return false;
1413
1414 monotonic_to_bootbased(&ts);
1415 *kernel_ns = timespec_to_ns(&ts);
1416
1417 return true;
1418}
1419#endif
1420
1421/*
1422 *
b48aa97e
MT		 1423 * Assuming a stable TSC across physical CPUS, and a stable TSC
1424 * across virtual CPUs, the following condition is possible.
1425 * Each numbered line represents an event visible to both
d828199e
MT		 1426 * CPUs at the next numbered event.
1427 *
1428 * "timespecX" represents host monotonic time. "tscX" represents
1429 * RDTSC value.
1430 *
1431 * VCPU0 on CPU0 | VCPU1 on CPU1
1432 *
1433 * 1. read timespec0,tsc0
1434 * 2. | timespec1 = timespec0 + N
1435 * | tsc1 = tsc0 + M
1436 * 3. transition to guest | transition to guest
1437 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1438 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1439 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1440 *
1441 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1442 *
1443 * - ret0 < ret1
1444 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1445 * ...
1446 * - 0 < N - M => M < N
1447 *
1448 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1449 * always the case (the difference between two distinct xtime instances
1450 * might be smaller then the difference between corresponding TSC reads,
1451 * when updating guest vcpus pvclock areas).
1452 *
1453 * To avoid that problem, do not allow visibility of distinct
1454 * system_timestamp/tsc_timestamp values simultaneously: use a master
1455 * copy of host monotonic time values. Update that master copy
1456 * in lockstep.
1457 *
b48aa97e 1458 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1459 *
1460 */
1461
1462static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1463{
1464#ifdef CONFIG_X86_64
1465 struct kvm_arch *ka = &kvm->arch;
1466 int vclock_mode;
b48aa97e
MT		 1467 bool host_tsc_clocksource, vcpus_matched;
1468
1469 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1470 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1471
1472 /*
1473 * If the host uses TSC clock, then passthrough TSC as stable
1474 * to the guest.
1475 */
b48aa97e 1476 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1477 &ka->master_kernel_ns,
1478 &ka->master_cycle_now);
1479
16a96021
MT		 1480 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1481 && !backwards_tsc_observed;
b48aa97e 1482
d828199e
MT		 1483 if (ka->use_master_clock)
1484 atomic_set(&kvm_guest_has_master_clock, 1);
1485
1486 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1487 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1488 vcpus_matched);
d828199e
MT		 1489#endif
1490}
1491
2e762ff7
MT		 1492static void kvm_gen_update_masterclock(struct kvm *kvm)
1493{
1494#ifdef CONFIG_X86_64
1495 int i;
1496 struct kvm_vcpu *vcpu;
1497 struct kvm_arch *ka = &kvm->arch;
1498
1499 spin_lock(&ka->pvclock_gtod_sync_lock);
1500 kvm_make_mclock_inprogress_request(kvm);
1501 /* no guest entries from this point */
1502 pvclock_update_vm_gtod_copy(kvm);
1503
1504 kvm_for_each_vcpu(i, vcpu, kvm)
1505 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1506
1507 /* guest entries allowed */
1508 kvm_for_each_vcpu(i, vcpu, kvm)
1509 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1510
1511 spin_unlock(&ka->pvclock_gtod_sync_lock);
1512#endif
1513}
1514
34c238a1 1515static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1516{
d828199e 1517 unsigned long flags, this_tsc_khz;
18068523 1518 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1519 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1520 s64 kernel_ns;
d828199e 1521 u64 tsc_timestamp, host_tsc;
0b79459b 1522 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1523 u8 pvclock_flags;
d828199e
MT		 1524 bool use_master_clock;
1525
1526 kernel_ns = 0;
1527 host_tsc = 0;
18068523 1528
d828199e
MT		 1529 /*
1530 * If the host uses TSC clock, then passthrough TSC as stable
1531 * to the guest.
1532 */
1533 spin_lock(&ka->pvclock_gtod_sync_lock);
1534 use_master_clock = ka->use_master_clock;
1535 if (use_master_clock) {
1536 host_tsc = ka->master_cycle_now;
1537 kernel_ns = ka->master_kernel_ns;
1538 }
1539 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1540
1541 /* Keep irq disabled to prevent changes to the clock */
1542 local_irq_save(flags);
1543 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1544 if (unlikely(this_tsc_khz == 0)) {
1545 local_irq_restore(flags);
1546 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1547 return 1;
1548 }
d828199e
MT		 1549 if (!use_master_clock) {
1550 host_tsc = native_read_tsc();
1551 kernel_ns = get_kernel_ns();
1552 }
1553
1554 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1555
c285545f
ZA		 1556 /*
1557 * We may have to catch up the TSC to match elapsed wall clock
1558 * time for two reasons, even if kvmclock is used.
1559 * 1) CPU could have been running below the maximum TSC rate
1560 * 2) Broken TSC compensation resets the base at each VCPU
1561 * entry to avoid unknown leaps of TSC even when running
1562 * again on the same CPU. This may cause apparent elapsed
1563 * time to disappear, and the guest to stand still or run
1564 * very slowly.
1565 */
1566 if (vcpu->tsc_catchup) {
1567 u64 tsc = compute_guest_tsc(v, kernel_ns);
1568 if (tsc > tsc_timestamp) {
f1e2b260 1569 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1570 tsc_timestamp = tsc;
1571 }
50d0a0f9
GH		 1572 }
1573
18068523
GOC		 1574 local_irq_restore(flags);
1575
0b79459b 1576 if (!vcpu->pv_time_enabled)
c285545f 1577 return 0;
18068523 1578
e48672fa 1579 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1580 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1581 &vcpu->hv_clock.tsc_shift,
1582 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1583 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1584 }
1585
1586 /* With all the info we got, fill in the values */
1d5f066e 1587 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1588 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1589 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1590
18068523
GOC		 1591 /*
1592 * The interface expects us to write an even number signaling that the
1593 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1594 * state, we just increase by 2 at the end.
18068523 1595 */
50d0a0f9 1596 vcpu->hv_clock.version += 2;
18068523 1597
0b79459b
AH		 1598 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1599 &guest_hv_clock, sizeof(guest_hv_clock))))
1600 return 0;
78c0337a
MT		 1601
1602 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1603 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1604
1605 if (vcpu->pvclock_set_guest_stopped_request) {
1606 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1607 vcpu->pvclock_set_guest_stopped_request = false;
1608 }
1609
d828199e
MT		 1610 /* If the host uses TSC clocksource, then it is stable */
1611 if (use_master_clock)
1612 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1613
78c0337a
MT		 1614 vcpu->hv_clock.flags = pvclock_flags;
1615
0b79459b
AH		 1616 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1617 &vcpu->hv_clock,
1618 sizeof(vcpu->hv_clock));
8cfdc000 1619 return 0;
c8076604
GH		 1620}
1621
0061d53d
MT		 1622/*
1623 * kvmclock updates which are isolated to a given vcpu, such as
1624 * vcpu->cpu migration, should not allow system_timestamp from
1625 * the rest of the vcpus to remain static. Otherwise ntp frequency
1626 * correction applies to one vcpu's system_timestamp but not
1627 * the others.
1628 *
1629 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1630 * We need to rate-limit these requests though, as they can
1631 * considerably slow guests that have a large number of vcpus.
1632 * The time for a remote vcpu to update its kvmclock is bound
1633 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1634 */
1635
7e44e449
AJ		 1636#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1637
1638static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1639{
1640 int i;
7e44e449
AJ		 1641 struct delayed_work *dwork = to_delayed_work(work);
1642 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1643 kvmclock_update_work);
1644 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1645 struct kvm_vcpu *vcpu;
1646
1647 kvm_for_each_vcpu(i, vcpu, kvm) {
1648 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1649 kvm_vcpu_kick(vcpu);
1650 }
1651}
1652
7e44e449
AJ		 1653static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1654{
1655 struct kvm *kvm = v->kvm;
1656
1657 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1658 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1659 KVMCLOCK_UPDATE_DELAY);
1660}
1661
332967a3
AJ		 1662#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1663
1664static void kvmclock_sync_fn(struct work_struct *work)
1665{
1666 struct delayed_work *dwork = to_delayed_work(work);
1667 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1668 kvmclock_sync_work);
1669 struct kvm *kvm = container_of(ka, struct kvm, arch);
1670
1671 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1672 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1673 KVMCLOCK_SYNC_PERIOD);
1674}
1675
9ba075a6
AK		 1676static bool msr_mtrr_valid(unsigned msr)
1677{
1678 switch (msr) {
1679 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1680 case MSR_MTRRfix64K_00000:
1681 case MSR_MTRRfix16K_80000:
1682 case MSR_MTRRfix16K_A0000:
1683 case MSR_MTRRfix4K_C0000:
1684 case MSR_MTRRfix4K_C8000:
1685 case MSR_MTRRfix4K_D0000:
1686 case MSR_MTRRfix4K_D8000:
1687 case MSR_MTRRfix4K_E0000:
1688 case MSR_MTRRfix4K_E8000:
1689 case MSR_MTRRfix4K_F0000:
1690 case MSR_MTRRfix4K_F8000:
1691 case MSR_MTRRdefType:
1692 case MSR_IA32_CR_PAT:
1693 return true;
1694 case 0x2f8:
1695 return true;
1696 }
1697 return false;
1698}
1699
d6289b93
MT		 1700static bool valid_pat_type(unsigned t)
1701{
1702 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1703}
1704
1705static bool valid_mtrr_type(unsigned t)
1706{
1707 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1708}
1709
1710static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1711{
1712 int i;
1713
1714 if (!msr_mtrr_valid(msr))
1715 return false;
1716
1717 if (msr == MSR_IA32_CR_PAT) {
1718 for (i = 0; i < 8; i++)
1719 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1720 return false;
1721 return true;
1722 } else if (msr == MSR_MTRRdefType) {
1723 if (data & ~0xcff)
1724 return false;
1725 return valid_mtrr_type(data & 0xff);
1726 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1727 for (i = 0; i < 8 ; i++)
1728 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1729 return false;
1730 return true;
1731 }
1732
1733 /* variable MTRRs */
1734 return valid_mtrr_type(data & 0xff);
1735}
1736
9ba075a6
AK		 1737static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1738{
0bed3b56
SY		 1739 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1740
d6289b93 1741 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1742 return 1;
1743
0bed3b56
SY		 1744 if (msr == MSR_MTRRdefType) {
1745 vcpu->arch.mtrr_state.def_type = data;
1746 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1747 } else if (msr == MSR_MTRRfix64K_00000)
1748 p[0] = data;
1749 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1750 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1751 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1752 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1753 else if (msr == MSR_IA32_CR_PAT)
1754 vcpu->arch.pat = data;
1755 else { /* Variable MTRRs */
1756 int idx, is_mtrr_mask;
1757 u64 *pt;
1758
1759 idx = (msr - 0x200) / 2;
1760 is_mtrr_mask = msr - 0x200 - 2 * idx;
1761 if (!is_mtrr_mask)
1762 pt =
1763 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1764 else
1765 pt =
1766 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1767 *pt = data;
1768 }
1769
1770 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1771 return 0;
1772}
15c4a640 1773
890ca9ae 1774static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1775{
890ca9ae
HY		 1776 u64 mcg_cap = vcpu->arch.mcg_cap;
1777 unsigned bank_num = mcg_cap & 0xff;
1778
15c4a640 1779 switch (msr) {
15c4a640 1780 case MSR_IA32_MCG_STATUS:
890ca9ae 1781 vcpu->arch.mcg_status = data;
15c4a640 1782 break;
c7ac679c 1783 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1784 if (!(mcg_cap & MCG_CTL_P))
1785 return 1;
1786 if (data != 0 && data != ~(u64)0)
1787 return -1;
1788 vcpu->arch.mcg_ctl = data;
1789 break;
1790 default:
1791 if (msr >= MSR_IA32_MC0_CTL &&
1792 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1793 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1794 /* only 0 or all 1s can be written to IA32_MCi_CTL
1795 * some Linux kernels though clear bit 10 in bank 4 to
1796 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1797 * this to avoid an uncatched #GP in the guest
1798 */
890ca9ae 1799 if ((offset & 0x3) == 0 &&
114be429 1800 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1801 return -1;
1802 vcpu->arch.mce_banks[offset] = data;
1803 break;
1804 }
1805 return 1;
1806 }
1807 return 0;
1808}
1809
ffde22ac
ES		 1810static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1811{
1812 struct kvm *kvm = vcpu->kvm;
1813 int lm = is_long_mode(vcpu);
1814 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1815 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1816 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1817 : kvm->arch.xen_hvm_config.blob_size_32;
1818 u32 page_num = data & ~PAGE_MASK;
1819 u64 page_addr = data & PAGE_MASK;
1820 u8 *page;
1821 int r;
1822
1823 r = -E2BIG;
1824 if (page_num >= blob_size)
1825 goto out;
1826 r = -ENOMEM;
ff5c2c03
SL		 1827 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1828 if (IS_ERR(page)) {
1829 r = PTR_ERR(page);
ffde22ac 1830 goto out;
ff5c2c03 1831 }
ffde22ac
ES		 1832 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1833 goto out_free;
1834 r = 0;
1835out_free:
1836 kfree(page);
1837out:
1838 return r;
1839}
1840
55cd8e5a
GN		 1841static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1842{
1843 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1844}
1845
1846static bool kvm_hv_msr_partition_wide(u32 msr)
1847{
1848 bool r = false;
1849 switch (msr) {
1850 case HV_X64_MSR_GUEST_OS_ID:
1851 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1852 case HV_X64_MSR_REFERENCE_TSC:
1853 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1854 r = true;
1855 break;
1856 }
1857
1858 return r;
1859}
1860
1861static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1862{
1863 struct kvm *kvm = vcpu->kvm;
1864
1865 switch (msr) {
1866 case HV_X64_MSR_GUEST_OS_ID:
1867 kvm->arch.hv_guest_os_id = data;
1868 /* setting guest os id to zero disables hypercall page */
1869 if (!kvm->arch.hv_guest_os_id)
1870 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1871 break;
1872 case HV_X64_MSR_HYPERCALL: {
1873 u64 gfn;
1874 unsigned long addr;
1875 u8 instructions[4];
1876
1877 /* if guest os id is not set hypercall should remain disabled */
1878 if (!kvm->arch.hv_guest_os_id)
1879 break;
1880 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1881 kvm->arch.hv_hypercall = data;
1882 break;
1883 }
1884 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1885 addr = gfn_to_hva(kvm, gfn);
1886 if (kvm_is_error_hva(addr))
1887 return 1;
1888 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1889 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1890 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1891 return 1;
1892 kvm->arch.hv_hypercall = data;
b94b64c9 1893 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1894 break;
1895 }
e984097b
VR		 1896 case HV_X64_MSR_REFERENCE_TSC: {
1897 u64 gfn;
1898 HV_REFERENCE_TSC_PAGE tsc_ref;
1899 memset(&tsc_ref, 0, sizeof(tsc_ref));
1900 kvm->arch.hv_tsc_page = data;
1901 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1902 break;
1903 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1904 if (kvm_write_guest(kvm, data,
1905 &tsc_ref, sizeof(tsc_ref)))
1906 return 1;
1907 mark_page_dirty(kvm, gfn);
1908 break;
1909 }
55cd8e5a 1910 default:
a737f256
CD		 1911 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1912 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1913 return 1;
1914 }
1915 return 0;
1916}
1917
1918static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1919{
10388a07
GN		 1920 switch (msr) {
1921 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1922 u64 gfn;
10388a07 1923 unsigned long addr;
55cd8e5a 1924
10388a07
GN		 1925 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1926 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1927 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1928 return 1;
10388a07
GN		 1929 break;
1930 }
b3af1e88
VR		 1931 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1932 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1933 if (kvm_is_error_hva(addr))
1934 return 1;
8b0cedff 1935 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1936 return 1;
1937 vcpu->arch.hv_vapic = data;
b3af1e88 1938 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1939 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1940 return 1;
10388a07
GN		 1941 break;
1942 }
1943 case HV_X64_MSR_EOI:
1944 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1945 case HV_X64_MSR_ICR:
1946 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1947 case HV_X64_MSR_TPR:
1948 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1949 default:
a737f256
CD		 1950 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1951 "data 0x%llx\n", msr, data);
10388a07
GN		 1952 return 1;
1953 }
1954
1955 return 0;
55cd8e5a
GN		 1956}
1957
344d9588
GN		 1958static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1959{
1960 gpa_t gpa = data & ~0x3f;
1961
4a969980 1962 /* Bits 2:5 are reserved, Should be zero */
6adba527 1963 if (data & 0x3c)
344d9588
GN		 1964 return 1;
1965
1966 vcpu->arch.apf.msr_val = data;
1967
1968 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1969 kvm_clear_async_pf_completion_queue(vcpu);
1970 kvm_async_pf_hash_reset(vcpu);
1971 return 0;
1972 }
1973
8f964525
AH		 1974 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1975 sizeof(u32)))
344d9588
GN		 1976 return 1;
1977
6adba527 1978 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1979 kvm_async_pf_wakeup_all(vcpu);
1980 return 0;
1981}
1982
12f9a48f
GC		 1983static void kvmclock_reset(struct kvm_vcpu *vcpu)
1984{
0b79459b 1985 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1986}
1987
c9aaa895
GC		 1988static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1989{
1990 u64 delta;
1991
1992 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1993 return;
1994
1995 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1996 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1997 vcpu->arch.st.accum_steal = delta;
1998}
1999
2000static void record_steal_time(struct kvm_vcpu *vcpu)
2001{
2002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2003 return;
2004
2005 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2006 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2007 return;
2008
2009 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2010 vcpu->arch.st.steal.version += 2;
2011 vcpu->arch.st.accum_steal = 0;
2012
2013 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2014 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2015}
2016
8fe8ab46 2017int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2018{
5753785f 2019 bool pr = false;
8fe8ab46
WA		 2020 u32 msr = msr_info->index;
2021 u64 data = msr_info->data;
5753785f 2022
15c4a640 2023 switch (msr) {
2e32b719
BP		 2024 case MSR_AMD64_NB_CFG:
2025 case MSR_IA32_UCODE_REV:
2026 case MSR_IA32_UCODE_WRITE:
2027 case MSR_VM_HSAVE_PA:
2028 case MSR_AMD64_PATCH_LOADER:
2029 case MSR_AMD64_BU_CFG2:
2030 break;
2031
15c4a640 2032 case MSR_EFER:
b69e8cae 2033 return set_efer(vcpu, data);
8f1589d9
AP		 2034 case MSR_K7_HWCR:
2035 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2036 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2037 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2038 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2039 if (data != 0) {
a737f256
CD		 2040 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2041 data);
8f1589d9
AP		 2042 return 1;
2043 }
15c4a640 2044 break;
f7c6d140
AP		 2045 case MSR_FAM10H_MMIO_CONF_BASE:
2046 if (data != 0) {
a737f256
CD		 2047 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2048 "0x%llx\n", data);
f7c6d140
AP		 2049 return 1;
2050 }
15c4a640 2051 break;
b5e2fec0
AG		 2052 case MSR_IA32_DEBUGCTLMSR:
2053 if (!data) {
2054 /* We support the non-activated case already */
2055 break;
2056 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2057 /* Values other than LBR and BTF are vendor-specific,
2058 thus reserved and should throw a #GP */
2059 return 1;
2060 }
a737f256
CD		 2061 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2062 __func__, data);
b5e2fec0 2063 break;
9ba075a6
AK		 2064 case 0x200 ... 0x2ff:
2065 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2066 case MSR_IA32_APICBASE:
58cb628d 2067 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2068 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2069 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2070 case MSR_IA32_TSCDEADLINE:
2071 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2072 break;
ba904635
WA		 2073 case MSR_IA32_TSC_ADJUST:
2074 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2075 if (!msr_info->host_initiated) {
2076 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2077 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2078 }
2079 vcpu->arch.ia32_tsc_adjust_msr = data;
2080 }
2081 break;
15c4a640 2082 case MSR_IA32_MISC_ENABLE:
ad312c7c 2083 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2084 break;
11c6bffa 2085 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2086 case MSR_KVM_WALL_CLOCK:
2087 vcpu->kvm->arch.wall_clock = data;
2088 kvm_write_wall_clock(vcpu->kvm, data);
2089 break;
11c6bffa 2090 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2091 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2092 u64 gpa_offset;
12f9a48f 2093 kvmclock_reset(vcpu);
18068523
GOC		 2094
2095 vcpu->arch.time = data;
0061d53d 2096 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2097
2098 /* we verify if the enable bit is set... */
2099 if (!(data & 1))
2100 break;
2101
0b79459b 2102 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2103
0b79459b 2104 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2105 &vcpu->arch.pv_time, data & ~1ULL,
2106 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2107 vcpu->arch.pv_time_enabled = false;
2108 else
2109 vcpu->arch.pv_time_enabled = true;
32cad84f 2110
18068523
GOC		 2111 break;
2112 }
344d9588
GN		 2113 case MSR_KVM_ASYNC_PF_EN:
2114 if (kvm_pv_enable_async_pf(vcpu, data))
2115 return 1;
2116 break;
c9aaa895
GC		 2117 case MSR_KVM_STEAL_TIME:
2118
2119 if (unlikely(!sched_info_on()))
2120 return 1;
2121
2122 if (data & KVM_STEAL_RESERVED_MASK)
2123 return 1;
2124
2125 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2126 data & KVM_STEAL_VALID_BITS,
2127 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2128 return 1;
2129
2130 vcpu->arch.st.msr_val = data;
2131
2132 if (!(data & KVM_MSR_ENABLED))
2133 break;
2134
2135 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2136
2137 preempt_disable();
2138 accumulate_steal_time(vcpu);
2139 preempt_enable();
2140
2141 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2142
2143 break;
ae7a2a3f
MT		 2144 case MSR_KVM_PV_EOI_EN:
2145 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2146 return 1;
2147 break;
c9aaa895 2148
890ca9ae
HY		 2149 case MSR_IA32_MCG_CTL:
2150 case MSR_IA32_MCG_STATUS:
2151 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2152 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2153
2154 /* Performance counters are not protected by a CPUID bit,
2155 * so we should check all of them in the generic path for the sake of
2156 * cross vendor migration.
2157 * Writing a zero into the event select MSRs disables them,
2158 * which we perfectly emulate ;-). Any other value should be at least
2159 * reported, some guests depend on them.
2160 */
71db6023
AP		 2161 case MSR_K7_EVNTSEL0:
2162 case MSR_K7_EVNTSEL1:
2163 case MSR_K7_EVNTSEL2:
2164 case MSR_K7_EVNTSEL3:
2165 if (data != 0)
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2167 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2168 break;
2169 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2170 * so we ignore writes to make it happy.
2171 */
71db6023
AP		 2172 case MSR_K7_PERFCTR0:
2173 case MSR_K7_PERFCTR1:
2174 case MSR_K7_PERFCTR2:
2175 case MSR_K7_PERFCTR3:
a737f256
CD		 2176 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2177 "0x%x data 0x%llx\n", msr, data);
71db6023 2178 break;
5753785f
GN		 2179 case MSR_P6_PERFCTR0:
2180 case MSR_P6_PERFCTR1:
2181 pr = true;
2182 case MSR_P6_EVNTSEL0:
2183 case MSR_P6_EVNTSEL1:
2184 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2185 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2186
2187 if (pr || data != 0)
a737f256
CD		 2188 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2189 "0x%x data 0x%llx\n", msr, data);
5753785f 2190 break;
84e0cefa
JS		 2191 case MSR_K7_CLK_CTL:
2192 /*
2193 * Ignore all writes to this no longer documented MSR.
2194 * Writes are only relevant for old K7 processors,
2195 * all pre-dating SVM, but a recommended workaround from
4a969980 2196 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2197 * affected processor models on the command line, hence
2198 * the need to ignore the workaround.
2199 */
2200 break;
55cd8e5a
GN		 2201 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2202 if (kvm_hv_msr_partition_wide(msr)) {
2203 int r;
2204 mutex_lock(&vcpu->kvm->lock);
2205 r = set_msr_hyperv_pw(vcpu, msr, data);
2206 mutex_unlock(&vcpu->kvm->lock);
2207 return r;
2208 } else
2209 return set_msr_hyperv(vcpu, msr, data);
2210 break;
91c9c3ed 2211 case MSR_IA32_BBL_CR_CTL3:
2212 /* Drop writes to this legacy MSR -- see rdmsr
2213 * counterpart for further detail.
2214 */
a737f256 2215 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2216 break;
2b036c6b
BO		 2217 case MSR_AMD64_OSVW_ID_LENGTH:
2218 if (!guest_cpuid_has_osvw(vcpu))
2219 return 1;
2220 vcpu->arch.osvw.length = data;
2221 break;
2222 case MSR_AMD64_OSVW_STATUS:
2223 if (!guest_cpuid_has_osvw(vcpu))
2224 return 1;
2225 vcpu->arch.osvw.status = data;
2226 break;
15c4a640 2227 default:
ffde22ac
ES		 2228 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2229 return xen_hvm_config(vcpu, data);
f5132b01 2230 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2231 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2232 if (!ignore_msrs) {
a737f256
CD		 2233 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2234 msr, data);
ed85c068
AP		 2235 return 1;
2236 } else {
a737f256
CD		 2237 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2238 msr, data);
ed85c068
AP		 2239 break;
2240 }
15c4a640
CO		 2241 }
2242 return 0;
2243}
2244EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2245
2246
2247/*
2248 * Reads an msr value (of 'msr_index') into 'pdata'.
2249 * Returns 0 on success, non-0 otherwise.
2250 * Assumes vcpu_load() was already called.
2251 */
2252int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2253{
2254 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2255}
2256
9ba075a6
AK		 2257static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2258{
0bed3b56
SY		 2259 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2260
9ba075a6
AK		 2261 if (!msr_mtrr_valid(msr))
2262 return 1;
2263
0bed3b56
SY		 2264 if (msr == MSR_MTRRdefType)
2265 *pdata = vcpu->arch.mtrr_state.def_type +
2266 (vcpu->arch.mtrr_state.enabled << 10);
2267 else if (msr == MSR_MTRRfix64K_00000)
2268 *pdata = p[0];
2269 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2270 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2271 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2272 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2273 else if (msr == MSR_IA32_CR_PAT)
2274 *pdata = vcpu->arch.pat;
2275 else { /* Variable MTRRs */
2276 int idx, is_mtrr_mask;
2277 u64 *pt;
2278
2279 idx = (msr - 0x200) / 2;
2280 is_mtrr_mask = msr - 0x200 - 2 * idx;
2281 if (!is_mtrr_mask)
2282 pt =
2283 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2284 else
2285 pt =
2286 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2287 *pdata = *pt;
2288 }
2289
9ba075a6
AK		 2290 return 0;
2291}
2292
890ca9ae 2293static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2294{
2295 u64 data;
890ca9ae
HY		 2296 u64 mcg_cap = vcpu->arch.mcg_cap;
2297 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2298
2299 switch (msr) {
15c4a640
CO		 2300 case MSR_IA32_P5_MC_ADDR:
2301 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2302 data = 0;
2303 break;
15c4a640 2304 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2305 data = vcpu->arch.mcg_cap;
2306 break;
c7ac679c 2307 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2308 if (!(mcg_cap & MCG_CTL_P))
2309 return 1;
2310 data = vcpu->arch.mcg_ctl;
2311 break;
2312 case MSR_IA32_MCG_STATUS:
2313 data = vcpu->arch.mcg_status;
2314 break;
2315 default:
2316 if (msr >= MSR_IA32_MC0_CTL &&
2317 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2318 u32 offset = msr - MSR_IA32_MC0_CTL;
2319 data = vcpu->arch.mce_banks[offset];
2320 break;
2321 }
2322 return 1;
2323 }
2324 *pdata = data;
2325 return 0;
2326}
2327
55cd8e5a
GN		 2328static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2329{
2330 u64 data = 0;
2331 struct kvm *kvm = vcpu->kvm;
2332
2333 switch (msr) {
2334 case HV_X64_MSR_GUEST_OS_ID:
2335 data = kvm->arch.hv_guest_os_id;
2336 break;
2337 case HV_X64_MSR_HYPERCALL:
2338 data = kvm->arch.hv_hypercall;
2339 break;
e984097b
VR		 2340 case HV_X64_MSR_TIME_REF_COUNT: {
2341 data =
2342 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2343 break;
2344 }
2345 case HV_X64_MSR_REFERENCE_TSC:
2346 data = kvm->arch.hv_tsc_page;
2347 break;
55cd8e5a 2348 default:
a737f256 2349 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2350 return 1;
2351 }
2352
2353 *pdata = data;
2354 return 0;
2355}
2356
2357static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2358{
2359 u64 data = 0;
2360
2361 switch (msr) {
2362 case HV_X64_MSR_VP_INDEX: {
2363 int r;
2364 struct kvm_vcpu *v;
684851a1
TY		 2365 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2366 if (v == vcpu) {
55cd8e5a 2367 data = r;
684851a1
TY		 2368 break;
2369 }
2370 }
55cd8e5a
GN		 2371 break;
2372 }
10388a07
GN		 2373 case HV_X64_MSR_EOI:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2375 case HV_X64_MSR_ICR:
2376 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2377 case HV_X64_MSR_TPR:
2378 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2379 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2380 data = vcpu->arch.hv_vapic;
2381 break;
55cd8e5a 2382 default:
a737f256 2383 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2384 return 1;
2385 }
2386 *pdata = data;
2387 return 0;
2388}
2389
890ca9ae
HY		 2390int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391{
2392 u64 data;
2393
2394 switch (msr) {
890ca9ae 2395 case MSR_IA32_PLATFORM_ID:
15c4a640 2396 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2397 case MSR_IA32_DEBUGCTLMSR:
2398 case MSR_IA32_LASTBRANCHFROMIP:
2399 case MSR_IA32_LASTBRANCHTOIP:
2400 case MSR_IA32_LASTINTFROMIP:
2401 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2402 case MSR_K8_SYSCFG:
2403 case MSR_K7_HWCR:
61a6bd67 2404 case MSR_VM_HSAVE_PA:
9e699624 2405 case MSR_K7_EVNTSEL0:
1f3ee616 2406 case MSR_K7_PERFCTR0:
1fdbd48c 2407 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2408 case MSR_AMD64_NB_CFG:
f7c6d140 2409 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2410 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2411 data = 0;
2412 break;
5753785f
GN		 2413 case MSR_P6_PERFCTR0:
2414 case MSR_P6_PERFCTR1:
2415 case MSR_P6_EVNTSEL0:
2416 case MSR_P6_EVNTSEL1:
2417 if (kvm_pmu_msr(vcpu, msr))
2418 return kvm_pmu_get_msr(vcpu, msr, pdata);
2419 data = 0;
2420 break;
742bc670
MT		 2421 case MSR_IA32_UCODE_REV:
2422 data = 0x100000000ULL;
2423 break;
9ba075a6
AK		 2424 case MSR_MTRRcap:
2425 data = 0x500 | KVM_NR_VAR_MTRR;
2426 break;
2427 case 0x200 ... 0x2ff:
2428 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2429 case 0xcd: /* fsb frequency */
2430 data = 3;
2431 break;
7b914098
JS		 2432 /*
2433 * MSR_EBC_FREQUENCY_ID
2434 * Conservative value valid for even the basic CPU models.
2435 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2436 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2437 * and 266MHz for model 3, or 4. Set Core Clock
2438 * Frequency to System Bus Frequency Ratio to 1 (bits
2439 * 31:24) even though these are only valid for CPU
2440 * models > 2, however guests may end up dividing or
2441 * multiplying by zero otherwise.
2442 */
2443 case MSR_EBC_FREQUENCY_ID:
2444 data = 1 << 24;
2445 break;
15c4a640
CO		 2446 case MSR_IA32_APICBASE:
2447 data = kvm_get_apic_base(vcpu);
2448 break;
0105d1a5
GN		 2449 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2450 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2451 break;
a3e06bbe
LJ		 2452 case MSR_IA32_TSCDEADLINE:
2453 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2454 break;
ba904635
WA		 2455 case MSR_IA32_TSC_ADJUST:
2456 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2457 break;
15c4a640 2458 case MSR_IA32_MISC_ENABLE:
ad312c7c 2459 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2460 break;
847f0ad8
AG		 2461 case MSR_IA32_PERF_STATUS:
2462 /* TSC increment by tick */
2463 data = 1000ULL;
2464 /* CPU multiplier */
2465 data |= (((uint64_t)4ULL) << 40);
2466 break;
15c4a640 2467 case MSR_EFER:
f6801dff 2468 data = vcpu->arch.efer;
15c4a640 2469 break;
18068523 2470 case MSR_KVM_WALL_CLOCK:
11c6bffa 2471 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2472 data = vcpu->kvm->arch.wall_clock;
2473 break;
2474 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2475 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2476 data = vcpu->arch.time;
2477 break;
344d9588
GN		 2478 case MSR_KVM_ASYNC_PF_EN:
2479 data = vcpu->arch.apf.msr_val;
2480 break;
c9aaa895
GC		 2481 case MSR_KVM_STEAL_TIME:
2482 data = vcpu->arch.st.msr_val;
2483 break;
1d92128f
MT		 2484 case MSR_KVM_PV_EOI_EN:
2485 data = vcpu->arch.pv_eoi.msr_val;
2486 break;
890ca9ae
HY		 2487 case MSR_IA32_P5_MC_ADDR:
2488 case MSR_IA32_P5_MC_TYPE:
2489 case MSR_IA32_MCG_CAP:
2490 case MSR_IA32_MCG_CTL:
2491 case MSR_IA32_MCG_STATUS:
2492 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2493 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2494 case MSR_K7_CLK_CTL:
2495 /*
2496 * Provide expected ramp-up count for K7. All other
2497 * are set to zero, indicating minimum divisors for
2498 * every field.
2499 *
2500 * This prevents guest kernels on AMD host with CPU
2501 * type 6, model 8 and higher from exploding due to
2502 * the rdmsr failing.
2503 */
2504 data = 0x20000000;
2505 break;
55cd8e5a
GN		 2506 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2507 if (kvm_hv_msr_partition_wide(msr)) {
2508 int r;
2509 mutex_lock(&vcpu->kvm->lock);
2510 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2511 mutex_unlock(&vcpu->kvm->lock);
2512 return r;
2513 } else
2514 return get_msr_hyperv(vcpu, msr, pdata);
2515 break;
91c9c3ed 2516 case MSR_IA32_BBL_CR_CTL3:
2517 /* This legacy MSR exists but isn't fully documented in current
2518 * silicon. It is however accessed by winxp in very narrow
2519 * scenarios where it sets bit #19, itself documented as
2520 * a "reserved" bit. Best effort attempt to source coherent
2521 * read data here should the balance of the register be
2522 * interpreted by the guest:
2523 *
2524 * L2 cache control register 3: 64GB range, 256KB size,
2525 * enabled, latency 0x1, configured
2526 */
2527 data = 0xbe702111;
2528 break;
2b036c6b
BO		 2529 case MSR_AMD64_OSVW_ID_LENGTH:
2530 if (!guest_cpuid_has_osvw(vcpu))
2531 return 1;
2532 data = vcpu->arch.osvw.length;
2533 break;
2534 case MSR_AMD64_OSVW_STATUS:
2535 if (!guest_cpuid_has_osvw(vcpu))
2536 return 1;
2537 data = vcpu->arch.osvw.status;
2538 break;
15c4a640 2539 default:
f5132b01
GN		 2540 if (kvm_pmu_msr(vcpu, msr))
2541 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2542 if (!ignore_msrs) {
a737f256 2543 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2544 return 1;
2545 } else {
a737f256 2546 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2547 data = 0;
2548 }
2549 break;
15c4a640
CO		 2550 }
2551 *pdata = data;
2552 return 0;
2553}
2554EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2555
313a3dc7
CO		 2556/*
2557 * Read or write a bunch of msrs. All parameters are kernel addresses.
2558 *
2559 * @return number of msrs set successfully.
2560 */
2561static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2562 struct kvm_msr_entry *entries,
2563 int (*do_msr)(struct kvm_vcpu *vcpu,
2564 unsigned index, u64 *data))
2565{
f656ce01 2566 int i, idx;
313a3dc7 2567
f656ce01 2568 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2569 for (i = 0; i < msrs->nmsrs; ++i)
2570 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2571 break;
f656ce01 2572 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2573
313a3dc7
CO		 2574 return i;
2575}
2576
2577/*
2578 * Read or write a bunch of msrs. Parameters are user addresses.
2579 *
2580 * @return number of msrs set successfully.
2581 */
2582static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2583 int (*do_msr)(struct kvm_vcpu *vcpu,
2584 unsigned index, u64 *data),
2585 int writeback)
2586{
2587 struct kvm_msrs msrs;
2588 struct kvm_msr_entry *entries;
2589 int r, n;
2590 unsigned size;
2591
2592 r = -EFAULT;
2593 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2594 goto out;
2595
2596 r = -E2BIG;
2597 if (msrs.nmsrs >= MAX_IO_MSRS)
2598 goto out;
2599
313a3dc7 2600 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2601 entries = memdup_user(user_msrs->entries, size);
2602 if (IS_ERR(entries)) {
2603 r = PTR_ERR(entries);
313a3dc7 2604 goto out;
ff5c2c03 2605 }
313a3dc7
CO		 2606
2607 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2608 if (r < 0)
2609 goto out_free;
2610
2611 r = -EFAULT;
2612 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2613 goto out_free;
2614
2615 r = n;
2616
2617out_free:
7a73c028 2618 kfree(entries);
313a3dc7
CO		 2619out:
2620 return r;
2621}
2622
018d00d2
ZX		 2623int kvm_dev_ioctl_check_extension(long ext)
2624{
2625 int r;
2626
2627 switch (ext) {
2628 case KVM_CAP_IRQCHIP:
2629 case KVM_CAP_HLT:
2630 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2631 case KVM_CAP_SET_TSS_ADDR:
07716717 2632 case KVM_CAP_EXT_CPUID:
9c15bb1d 2633 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2634 case KVM_CAP_CLOCKSOURCE:
7837699f 2635 case KVM_CAP_PIT:
a28e4f5a 2636 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2637 case KVM_CAP_MP_STATE:
ed848624 2638 case KVM_CAP_SYNC_MMU:
a355c85c 2639 case KVM_CAP_USER_NMI:
52d939a0 2640 case KVM_CAP_REINJECT_CONTROL:
4925663a 2641 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2642 case KVM_CAP_IRQFD:
d34e6b17 2643 case KVM_CAP_IOEVENTFD:
f848a5a8 2644 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2645 case KVM_CAP_PIT2:
e9f42757 2646 case KVM_CAP_PIT_STATE2:
b927a3ce 2647 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2648 case KVM_CAP_XEN_HVM:
afbcf7ab 2649 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2650 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2651 case KVM_CAP_HYPERV:
10388a07 2652 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2653 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2654 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2655 case KVM_CAP_DEBUGREGS:
d2be1651 2656 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2657 case KVM_CAP_XSAVE:
344d9588 2658 case KVM_CAP_ASYNC_PF:
92a1f12d 2659 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2660 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2661 case KVM_CAP_READONLY_MEM:
5f66b620 2662 case KVM_CAP_HYPERV_TIME:
100943c5 2663 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2664#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2665 case KVM_CAP_ASSIGN_DEV_IRQ:
2666 case KVM_CAP_PCI_2_3:
2667#endif
018d00d2
ZX		 2668 r = 1;
2669 break;
542472b5
LV		 2670 case KVM_CAP_COALESCED_MMIO:
2671 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2672 break;
774ead3a
AK		 2673 case KVM_CAP_VAPIC:
2674 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2675 break;
f725230a 2676 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2677 r = KVM_SOFT_MAX_VCPUS;
2678 break;
2679 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2680 r = KVM_MAX_VCPUS;
2681 break;
a988b910 2682 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2683 r = KVM_USER_MEM_SLOTS;
a988b910 2684 break;
a68a6a72
MT		 2685 case KVM_CAP_PV_MMU: /* obsolete */
2686 r = 0;
2f333bcb 2687 break;
4cee4b72 2688#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2689 case KVM_CAP_IOMMU:
a1b60c1c 2690 r = iommu_present(&pci_bus_type);
62c476c7 2691 break;
4cee4b72 2692#endif
890ca9ae
HY		 2693 case KVM_CAP_MCE:
2694 r = KVM_MAX_MCE_BANKS;
2695 break;
2d5b5a66
SY		 2696 case KVM_CAP_XCRS:
2697 r = cpu_has_xsave;
2698 break;
92a1f12d
JR		 2699 case KVM_CAP_TSC_CONTROL:
2700 r = kvm_has_tsc_control;
2701 break;
4d25a066
JK		 2702 case KVM_CAP_TSC_DEADLINE_TIMER:
2703 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2704 break;
018d00d2
ZX		 2705 default:
2706 r = 0;
2707 break;
2708 }
2709 return r;
2710
2711}
2712
043405e1
CO		 2713long kvm_arch_dev_ioctl(struct file *filp,
2714 unsigned int ioctl, unsigned long arg)
2715{
2716 void __user *argp = (void __user *)arg;
2717 long r;
2718
2719 switch (ioctl) {
2720 case KVM_GET_MSR_INDEX_LIST: {
2721 struct kvm_msr_list __user *user_msr_list = argp;
2722 struct kvm_msr_list msr_list;
2723 unsigned n;
2724
2725 r = -EFAULT;
2726 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2727 goto out;
2728 n = msr_list.nmsrs;
2729 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2730 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2731 goto out;
2732 r = -E2BIG;
e125e7b6 2733 if (n < msr_list.nmsrs)
043405e1
CO		 2734 goto out;
2735 r = -EFAULT;
2736 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2737 num_msrs_to_save * sizeof(u32)))
2738 goto out;
e125e7b6 2739 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2740 &emulated_msrs,
2741 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2742 goto out;
2743 r = 0;
2744 break;
2745 }
9c15bb1d
BP		 2746 case KVM_GET_SUPPORTED_CPUID:
2747 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2748 struct kvm_cpuid2 __user *cpuid_arg = argp;
2749 struct kvm_cpuid2 cpuid;
2750
2751 r = -EFAULT;
2752 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2753 goto out;
9c15bb1d
BP		 2754
2755 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2756 ioctl);
674eea0f
AK		 2757 if (r)
2758 goto out;
2759
2760 r = -EFAULT;
2761 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2762 goto out;
2763 r = 0;
2764 break;
2765 }
890ca9ae
HY		 2766 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2767 u64 mce_cap;
2768
2769 mce_cap = KVM_MCE_CAP_SUPPORTED;
2770 r = -EFAULT;
2771 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2772 goto out;
2773 r = 0;
2774 break;
2775 }
043405e1
CO		 2776 default:
2777 r = -EINVAL;
2778 }
2779out:
2780 return r;
2781}
2782
f5f48ee1
SY		 2783static void wbinvd_ipi(void *garbage)
2784{
2785 wbinvd();
2786}
2787
2788static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2789{
e0f0bbc5 2790 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2791}
2792
313a3dc7
CO		 2793void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2794{
f5f48ee1
SY		 2795 /* Address WBINVD may be executed by guest */
2796 if (need_emulate_wbinvd(vcpu)) {
2797 if (kvm_x86_ops->has_wbinvd_exit())
2798 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2799 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2800 smp_call_function_single(vcpu->cpu,
2801 wbinvd_ipi, NULL, 1);
2802 }
2803
313a3dc7 2804 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2805
0dd6a6ed
ZA		 2806 /* Apply any externally detected TSC adjustments (due to suspend) */
2807 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2808 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2809 vcpu->arch.tsc_offset_adjustment = 0;
2810 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2811 }
8f6055cb 2812
48434c20 2813 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2814 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2815 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2816 if (tsc_delta < 0)
2817 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2818 if (check_tsc_unstable()) {
b183aa58
ZA		 2819 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2820 vcpu->arch.last_guest_tsc);
2821 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2822 vcpu->arch.tsc_catchup = 1;
c285545f 2823 }
d98d07ca
MT		 2824 /*
2825 * On a host with synchronized TSC, there is no need to update
2826 * kvmclock on vcpu->cpu migration
2827 */
2828 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2829 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2830 if (vcpu->cpu != cpu)
2831 kvm_migrate_timers(vcpu);
e48672fa 2832 vcpu->cpu = cpu;
6b7d7e76 2833 }
c9aaa895
GC		 2834
2835 accumulate_steal_time(vcpu);
2836 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2837}
2838
2839void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2840{
02daab21 2841 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2842 kvm_put_guest_fpu(vcpu);
6f526ec5 2843 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2844}
2845
313a3dc7
CO		 2846static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2847 struct kvm_lapic_state *s)
2848{
5a71785d 2849 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2850 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2851
2852 return 0;
2853}
2854
2855static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2856 struct kvm_lapic_state *s)
2857{
64eb0620 2858 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2859 update_cr8_intercept(vcpu);
313a3dc7
CO		 2860
2861 return 0;
2862}
2863
f77bc6a4
ZX		 2864static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2865 struct kvm_interrupt *irq)
2866{
02cdb50f 2867 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2868 return -EINVAL;
2869 if (irqchip_in_kernel(vcpu->kvm))
2870 return -ENXIO;
f77bc6a4 2871
66fd3f7f 2872 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2873 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2874
f77bc6a4
ZX		 2875 return 0;
2876}
2877
c4abb7c9
JK		 2878static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2879{
c4abb7c9 2880 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2881
2882 return 0;
2883}
2884
b209749f
AK		 2885static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2886 struct kvm_tpr_access_ctl *tac)
2887{
2888 if (tac->flags)
2889 return -EINVAL;
2890 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2891 return 0;
2892}
2893
890ca9ae
HY		 2894static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2895 u64 mcg_cap)
2896{
2897 int r;
2898 unsigned bank_num = mcg_cap & 0xff, bank;
2899
2900 r = -EINVAL;
a9e38c3e 2901 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2902 goto out;
2903 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2904 goto out;
2905 r = 0;
2906 vcpu->arch.mcg_cap = mcg_cap;
2907 /* Init IA32_MCG_CTL to all 1s */
2908 if (mcg_cap & MCG_CTL_P)
2909 vcpu->arch.mcg_ctl = ~(u64)0;
2910 /* Init IA32_MCi_CTL to all 1s */
2911 for (bank = 0; bank < bank_num; bank++)
2912 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2913out:
2914 return r;
2915}
2916
2917static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2918 struct kvm_x86_mce *mce)
2919{
2920 u64 mcg_cap = vcpu->arch.mcg_cap;
2921 unsigned bank_num = mcg_cap & 0xff;
2922 u64 *banks = vcpu->arch.mce_banks;
2923
2924 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2925 return -EINVAL;
2926 /*
2927 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2928 * reporting is disabled
2929 */
2930 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2931 vcpu->arch.mcg_ctl != ~(u64)0)
2932 return 0;
2933 banks += 4 * mce->bank;
2934 /*
2935 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2936 * reporting is disabled for the bank
2937 */
2938 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2939 return 0;
2940 if (mce->status & MCI_STATUS_UC) {
2941 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2942 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2943 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2944 return 0;
2945 }
2946 if (banks[1] & MCI_STATUS_VAL)
2947 mce->status |= MCI_STATUS_OVER;
2948 banks[2] = mce->addr;
2949 banks[3] = mce->misc;
2950 vcpu->arch.mcg_status = mce->mcg_status;
2951 banks[1] = mce->status;
2952 kvm_queue_exception(vcpu, MC_VECTOR);
2953 } else if (!(banks[1] & MCI_STATUS_VAL)
2954 || !(banks[1] & MCI_STATUS_UC)) {
2955 if (banks[1] & MCI_STATUS_VAL)
2956 mce->status |= MCI_STATUS_OVER;
2957 banks[2] = mce->addr;
2958 banks[3] = mce->misc;
2959 banks[1] = mce->status;
2960 } else
2961 banks[1] |= MCI_STATUS_OVER;
2962 return 0;
2963}
2964
3cfc3092
JK		 2965static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2966 struct kvm_vcpu_events *events)
2967{
7460fb4a 2968 process_nmi(vcpu);
03b82a30
JK		 2969 events->exception.injected =
2970 vcpu->arch.exception.pending &&
2971 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2972 events->exception.nr = vcpu->arch.exception.nr;
2973 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2974 events->exception.pad = 0;
3cfc3092
JK		 2975 events->exception.error_code = vcpu->arch.exception.error_code;
2976
03b82a30
JK		 2977 events->interrupt.injected =
2978 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2979 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2980 events->interrupt.soft = 0;
37ccdcbe 2981 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2982
2983 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2984 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2985 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2986 events->nmi.pad = 0;
3cfc3092 2987
66450a21 2988 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2989
dab4b911 2990 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2991 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2992 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2993}
2994
2995static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2996 struct kvm_vcpu_events *events)
2997{
dab4b911 2998 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2999 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3000 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3001 return -EINVAL;
3002
7460fb4a 3003 process_nmi(vcpu);
3cfc3092
JK		 3004 vcpu->arch.exception.pending = events->exception.injected;
3005 vcpu->arch.exception.nr = events->exception.nr;
3006 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3007 vcpu->arch.exception.error_code = events->exception.error_code;
3008
3009 vcpu->arch.interrupt.pending = events->interrupt.injected;
3010 vcpu->arch.interrupt.nr = events->interrupt.nr;
3011 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3012 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3013 kvm_x86_ops->set_interrupt_shadow(vcpu,
3014 events->interrupt.shadow);
3cfc3092
JK		 3015
3016 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3017 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3018 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3019 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3020
66450a21
JK		 3021 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3022 kvm_vcpu_has_lapic(vcpu))
3023 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3024
3842d135
AK		 3025 kvm_make_request(KVM_REQ_EVENT, vcpu);
3026
3cfc3092
JK		 3027 return 0;
3028}
3029
a1efbe77
JK		 3030static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3032{
73aaf249
JK		 3033 unsigned long val;
3034
a1efbe77 3035 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3036 _kvm_get_dr(vcpu, 6, &val);
3037 dbgregs->dr6 = val;
a1efbe77
JK		 3038 dbgregs->dr7 = vcpu->arch.dr7;
3039 dbgregs->flags = 0;
97e69aa6 3040 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3041}
3042
3043static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3044 struct kvm_debugregs *dbgregs)
3045{
3046 if (dbgregs->flags)
3047 return -EINVAL;
3048
a1efbe77
JK		 3049 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3050 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3051 kvm_update_dr6(vcpu);
a1efbe77 3052 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3053 kvm_update_dr7(vcpu);
a1efbe77 3054
a1efbe77
JK		 3055 return 0;
3056}
3057
2d5b5a66
SY		 3058static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3059 struct kvm_xsave *guest_xsave)
3060{
4344ee98 3061 if (cpu_has_xsave) {
2d5b5a66
SY		 3062 memcpy(guest_xsave->region,
3063 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3064 vcpu->arch.guest_xstate_size);
3065 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3066 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3067 } else {
2d5b5a66
SY		 3068 memcpy(guest_xsave->region,
3069 &vcpu->arch.guest_fpu.state->fxsave,
3070 sizeof(struct i387_fxsave_struct));
3071 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3072 XSTATE_FPSSE;
3073 }
3074}
3075
3076static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3077 struct kvm_xsave *guest_xsave)
3078{
3079 u64 xstate_bv =
3080 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3081
d7876f1b
PB		 3082 if (cpu_has_xsave) {
3083 /*
3084 * Here we allow setting states that are not present in
3085 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3086 * with old userspace.
3087 */
4ff41732 3088 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3089 return -EINVAL;
2d5b5a66 3090 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3091 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3092 } else {
2d5b5a66
SY		 3093 if (xstate_bv & ~XSTATE_FPSSE)
3094 return -EINVAL;
3095 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3096 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3097 }
3098 return 0;
3099}
3100
3101static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3102 struct kvm_xcrs *guest_xcrs)
3103{
3104 if (!cpu_has_xsave) {
3105 guest_xcrs->nr_xcrs = 0;
3106 return;
3107 }
3108
3109 guest_xcrs->nr_xcrs = 1;
3110 guest_xcrs->flags = 0;
3111 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3112 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3113}
3114
3115static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3116 struct kvm_xcrs *guest_xcrs)
3117{
3118 int i, r = 0;
3119
3120 if (!cpu_has_xsave)
3121 return -EINVAL;
3122
3123 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3124 return -EINVAL;
3125
3126 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3127 /* Only support XCR0 currently */
c67a04cb 3128 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3129 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3130 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3131 break;
3132 }
3133 if (r)
3134 r = -EINVAL;
3135 return r;
3136}
3137
1c0b28c2
EM		 3138/*
3139 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3140 * stopped by the hypervisor. This function will be called from the host only.
3141 * EINVAL is returned when the host attempts to set the flag for a guest that
3142 * does not support pv clocks.
3143 */
3144static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3145{
0b79459b 3146 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3147 return -EINVAL;
51d59c6b 3148 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3150 return 0;
3151}
3152
313a3dc7
CO		 3153long kvm_arch_vcpu_ioctl(struct file *filp,
3154 unsigned int ioctl, unsigned long arg)
3155{
3156 struct kvm_vcpu *vcpu = filp->private_data;
3157 void __user *argp = (void __user *)arg;
3158 int r;
d1ac91d8
AK		 3159 union {
3160 struct kvm_lapic_state *lapic;
3161 struct kvm_xsave *xsave;
3162 struct kvm_xcrs *xcrs;
3163 void *buffer;
3164 } u;
3165
3166 u.buffer = NULL;
313a3dc7
CO		 3167 switch (ioctl) {
3168 case KVM_GET_LAPIC: {
2204ae3c
MT		 3169 r = -EINVAL;
3170 if (!vcpu->arch.apic)
3171 goto out;
d1ac91d8 3172 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3173
b772ff36 3174 r = -ENOMEM;
d1ac91d8 3175 if (!u.lapic)
b772ff36 3176 goto out;
d1ac91d8 3177 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3178 if (r)
3179 goto out;
3180 r = -EFAULT;
d1ac91d8 3181 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3182 goto out;
3183 r = 0;
3184 break;
3185 }
3186 case KVM_SET_LAPIC: {
2204ae3c
MT		 3187 r = -EINVAL;
3188 if (!vcpu->arch.apic)
3189 goto out;
ff5c2c03 3190 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3191 if (IS_ERR(u.lapic))
3192 return PTR_ERR(u.lapic);
ff5c2c03 3193
d1ac91d8 3194 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3195 break;
3196 }
f77bc6a4
ZX		 3197 case KVM_INTERRUPT: {
3198 struct kvm_interrupt irq;
3199
3200 r = -EFAULT;
3201 if (copy_from_user(&irq, argp, sizeof irq))
3202 goto out;
3203 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3204 break;
3205 }
c4abb7c9
JK		 3206 case KVM_NMI: {
3207 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3208 break;
3209 }
313a3dc7
CO		 3210 case KVM_SET_CPUID: {
3211 struct kvm_cpuid __user *cpuid_arg = argp;
3212 struct kvm_cpuid cpuid;
3213
3214 r = -EFAULT;
3215 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3216 goto out;
3217 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3218 break;
3219 }
07716717
DK		 3220 case KVM_SET_CPUID2: {
3221 struct kvm_cpuid2 __user *cpuid_arg = argp;
3222 struct kvm_cpuid2 cpuid;
3223
3224 r = -EFAULT;
3225 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3226 goto out;
3227 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3228 cpuid_arg->entries);
07716717
DK		 3229 break;
3230 }
3231 case KVM_GET_CPUID2: {
3232 struct kvm_cpuid2 __user *cpuid_arg = argp;
3233 struct kvm_cpuid2 cpuid;
3234
3235 r = -EFAULT;
3236 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3237 goto out;
3238 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3239 cpuid_arg->entries);
07716717
DK		 3240 if (r)
3241 goto out;
3242 r = -EFAULT;
3243 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3244 goto out;
3245 r = 0;
3246 break;
3247 }
313a3dc7
CO		 3248 case KVM_GET_MSRS:
3249 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3250 break;
3251 case KVM_SET_MSRS:
3252 r = msr_io(vcpu, argp, do_set_msr, 0);
3253 break;
b209749f
AK		 3254 case KVM_TPR_ACCESS_REPORTING: {
3255 struct kvm_tpr_access_ctl tac;
3256
3257 r = -EFAULT;
3258 if (copy_from_user(&tac, argp, sizeof tac))
3259 goto out;
3260 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3261 if (r)
3262 goto out;
3263 r = -EFAULT;
3264 if (copy_to_user(argp, &tac, sizeof tac))
3265 goto out;
3266 r = 0;
3267 break;
3268 };
b93463aa
AK		 3269 case KVM_SET_VAPIC_ADDR: {
3270 struct kvm_vapic_addr va;
3271
3272 r = -EINVAL;
3273 if (!irqchip_in_kernel(vcpu->kvm))
3274 goto out;
3275 r = -EFAULT;
3276 if (copy_from_user(&va, argp, sizeof va))
3277 goto out;
fda4e2e8 3278 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3279 break;
3280 }
890ca9ae
HY		 3281 case KVM_X86_SETUP_MCE: {
3282 u64 mcg_cap;
3283
3284 r = -EFAULT;
3285 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3286 goto out;
3287 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3288 break;
3289 }
3290 case KVM_X86_SET_MCE: {
3291 struct kvm_x86_mce mce;
3292
3293 r = -EFAULT;
3294 if (copy_from_user(&mce, argp, sizeof mce))
3295 goto out;
3296 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3297 break;
3298 }
3cfc3092
JK		 3299 case KVM_GET_VCPU_EVENTS: {
3300 struct kvm_vcpu_events events;
3301
3302 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3303
3304 r = -EFAULT;
3305 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3306 break;
3307 r = 0;
3308 break;
3309 }
3310 case KVM_SET_VCPU_EVENTS: {
3311 struct kvm_vcpu_events events;
3312
3313 r = -EFAULT;
3314 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3315 break;
3316
3317 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3318 break;
3319 }
a1efbe77
JK		 3320 case KVM_GET_DEBUGREGS: {
3321 struct kvm_debugregs dbgregs;
3322
3323 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3324
3325 r = -EFAULT;
3326 if (copy_to_user(argp, &dbgregs,
3327 sizeof(struct kvm_debugregs)))
3328 break;
3329 r = 0;
3330 break;
3331 }
3332 case KVM_SET_DEBUGREGS: {
3333 struct kvm_debugregs dbgregs;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&dbgregs, argp,
3337 sizeof(struct kvm_debugregs)))
3338 break;
3339
3340 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3341 break;
3342 }
2d5b5a66 3343 case KVM_GET_XSAVE: {
d1ac91d8 3344 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3345 r = -ENOMEM;
d1ac91d8 3346 if (!u.xsave)
2d5b5a66
SY		 3347 break;
3348
d1ac91d8 3349 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3350
3351 r = -EFAULT;
d1ac91d8 3352 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3353 break;
3354 r = 0;
3355 break;
3356 }
3357 case KVM_SET_XSAVE: {
ff5c2c03 3358 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3359 if (IS_ERR(u.xsave))
3360 return PTR_ERR(u.xsave);
2d5b5a66 3361
d1ac91d8 3362 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3363 break;
3364 }
3365 case KVM_GET_XCRS: {
d1ac91d8 3366 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3367 r = -ENOMEM;
d1ac91d8 3368 if (!u.xcrs)
2d5b5a66
SY		 3369 break;
3370
d1ac91d8 3371 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3372
3373 r = -EFAULT;
d1ac91d8 3374 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3375 sizeof(struct kvm_xcrs)))
3376 break;
3377 r = 0;
3378 break;
3379 }
3380 case KVM_SET_XCRS: {
ff5c2c03 3381 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3382 if (IS_ERR(u.xcrs))
3383 return PTR_ERR(u.xcrs);
2d5b5a66 3384
d1ac91d8 3385 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3386 break;
3387 }
92a1f12d
JR		 3388 case KVM_SET_TSC_KHZ: {
3389 u32 user_tsc_khz;
3390
3391 r = -EINVAL;
92a1f12d
JR		 3392 user_tsc_khz = (u32)arg;
3393
3394 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3395 goto out;
3396
cc578287
ZA		 3397 if (user_tsc_khz == 0)
3398 user_tsc_khz = tsc_khz;
3399
3400 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3401
3402 r = 0;
3403 goto out;
3404 }
3405 case KVM_GET_TSC_KHZ: {
cc578287 3406 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3407 goto out;
3408 }
1c0b28c2
EM		 3409 case KVM_KVMCLOCK_CTRL: {
3410 r = kvm_set_guest_paused(vcpu);
3411 goto out;
3412 }
313a3dc7
CO		 3413 default:
3414 r = -EINVAL;
3415 }
3416out:
d1ac91d8 3417 kfree(u.buffer);
313a3dc7
CO		 3418 return r;
3419}
3420
5b1c1493
CO		 3421int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3422{
3423 return VM_FAULT_SIGBUS;
3424}
3425
1fe779f8
CO		 3426static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3427{
3428 int ret;
3429
3430 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3431 return -EINVAL;
1fe779f8
CO		 3432 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3433 return ret;
3434}
3435
b927a3ce
SY		 3436static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3437 u64 ident_addr)
3438{
3439 kvm->arch.ept_identity_map_addr = ident_addr;
3440 return 0;
3441}
3442
1fe779f8
CO		 3443static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3444 u32 kvm_nr_mmu_pages)
3445{
3446 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3447 return -EINVAL;
3448
79fac95e 3449 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3450
3451 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3452 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3453
79fac95e 3454 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3455 return 0;
3456}
3457
3458static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3459{
39de71ec 3460 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3461}
3462
1fe779f8
CO		 3463static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3464{
3465 int r;
3466
3467 r = 0;
3468 switch (chip->chip_id) {
3469 case KVM_IRQCHIP_PIC_MASTER:
3470 memcpy(&chip->chip.pic,
3471 &pic_irqchip(kvm)->pics[0],
3472 sizeof(struct kvm_pic_state));
3473 break;
3474 case KVM_IRQCHIP_PIC_SLAVE:
3475 memcpy(&chip->chip.pic,
3476 &pic_irqchip(kvm)->pics[1],
3477 sizeof(struct kvm_pic_state));
3478 break;
3479 case KVM_IRQCHIP_IOAPIC:
eba0226b 3480 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3481 break;
3482 default:
3483 r = -EINVAL;
3484 break;
3485 }
3486 return r;
3487}
3488
3489static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3490{
3491 int r;
3492
3493 r = 0;
3494 switch (chip->chip_id) {
3495 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3496 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3497 memcpy(&pic_irqchip(kvm)->pics[0],
3498 &chip->chip.pic,
3499 sizeof(struct kvm_pic_state));
f4f51050 3500 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3501 break;
3502 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3503 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3504 memcpy(&pic_irqchip(kvm)->pics[1],
3505 &chip->chip.pic,
3506 sizeof(struct kvm_pic_state));
f4f51050 3507 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3508 break;
3509 case KVM_IRQCHIP_IOAPIC:
eba0226b 3510 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3511 break;
3512 default:
3513 r = -EINVAL;
3514 break;
3515 }
3516 kvm_pic_update_irq(pic_irqchip(kvm));
3517 return r;
3518}
3519
e0f63cb9
SY		 3520static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3521{
3522 int r = 0;
3523
894a9c55 3524 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3525 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3526 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3527 return r;
3528}
3529
3530static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3531{
3532 int r = 0;
3533
894a9c55 3534 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3535 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3536 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3537 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3538 return r;
3539}
3540
3541static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3542{
3543 int r = 0;
3544
3545 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3546 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3547 sizeof(ps->channels));
3548 ps->flags = kvm->arch.vpit->pit_state.flags;
3549 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3550 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3551 return r;
3552}
3553
3554static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3555{
3556 int r = 0, start = 0;
3557 u32 prev_legacy, cur_legacy;
3558 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3559 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3560 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3561 if (!prev_legacy && cur_legacy)
3562 start = 1;
3563 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3564 sizeof(kvm->arch.vpit->pit_state.channels));
3565 kvm->arch.vpit->pit_state.flags = ps->flags;
3566 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3567 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3568 return r;
3569}
3570
52d939a0
MT		 3571static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3572 struct kvm_reinject_control *control)
3573{
3574 if (!kvm->arch.vpit)
3575 return -ENXIO;
894a9c55 3576 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3577 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3578 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3579 return 0;
3580}
3581
95d4c16c 3582/**
60c34612
TY		 3583 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3584 * @kvm: kvm instance
3585 * @log: slot id and address to which we copy the log
95d4c16c 3586 *
60c34612
TY		 3587 * We need to keep it in mind that VCPU threads can write to the bitmap
3588 * concurrently. So, to avoid losing data, we keep the following order for
3589 * each bit:
95d4c16c 3590 *
60c34612
TY		 3591 * 1. Take a snapshot of the bit and clear it if needed.
3592 * 2. Write protect the corresponding page.
3593 * 3. Flush TLB's if needed.
3594 * 4. Copy the snapshot to the userspace.
95d4c16c 3595 *
60c34612
TY		 3596 * Between 2 and 3, the guest may write to the page using the remaining TLB
3597 * entry. This is not a problem because the page will be reported dirty at
3598 * step 4 using the snapshot taken before and step 3 ensures that successive
3599 * writes will be logged for the next call.
5bb064dc 3600 */
60c34612 3601int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3602{
7850ac54 3603 int r;
5bb064dc 3604 struct kvm_memory_slot *memslot;
60c34612
TY		 3605 unsigned long n, i;
3606 unsigned long *dirty_bitmap;
3607 unsigned long *dirty_bitmap_buffer;
3608 bool is_dirty = false;
5bb064dc 3609
79fac95e 3610 mutex_lock(&kvm->slots_lock);
5bb064dc 3611
b050b015 3612 r = -EINVAL;
bbacc0c1 3613 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3614 goto out;
3615
28a37544 3616 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3617
3618 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3619 r = -ENOENT;
60c34612 3620 if (!dirty_bitmap)
b050b015
MT		 3621 goto out;
3622
87bf6e7d 3623 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3624
60c34612
TY		 3625 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3626 memset(dirty_bitmap_buffer, 0, n);
b050b015 3627
60c34612 3628 spin_lock(&kvm->mmu_lock);
b050b015 3629
60c34612
TY		 3630 for (i = 0; i < n / sizeof(long); i++) {
3631 unsigned long mask;
3632 gfn_t offset;
cdfca7b3 3633
60c34612
TY		 3634 if (!dirty_bitmap[i])
3635 continue;
b050b015 3636
60c34612 3637 is_dirty = true;
914ebccd 3638
60c34612
TY		 3639 mask = xchg(&dirty_bitmap[i], 0);
3640 dirty_bitmap_buffer[i] = mask;
edde99ce 3641
60c34612
TY		 3642 offset = i * BITS_PER_LONG;
3643 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3644 }
60c34612
TY		 3645
3646 spin_unlock(&kvm->mmu_lock);
3647
198c74f4
XG		 3648 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3649 lockdep_assert_held(&kvm->slots_lock);
3650
3651 /*
3652 * All the TLBs can be flushed out of mmu lock, see the comments in
3653 * kvm_mmu_slot_remove_write_access().
3654 */
3655 if (is_dirty)
3656 kvm_flush_remote_tlbs(kvm);
3657
60c34612
TY		 3658 r = -EFAULT;
3659 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3660 goto out;
b050b015 3661
5bb064dc
ZX		 3662 r = 0;
3663out:
79fac95e 3664 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3665 return r;
3666}
3667
aa2fbe6d
YZ		 3668int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3669 bool line_status)
23d43cf9
CD		 3670{
3671 if (!irqchip_in_kernel(kvm))
3672 return -ENXIO;
3673
3674 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3675 irq_event->irq, irq_event->level,
3676 line_status);
23d43cf9
CD		 3677 return 0;
3678}
3679
1fe779f8
CO		 3680long kvm_arch_vm_ioctl(struct file *filp,
3681 unsigned int ioctl, unsigned long arg)
3682{
3683 struct kvm *kvm = filp->private_data;
3684 void __user *argp = (void __user *)arg;
367e1319 3685 int r = -ENOTTY;
f0d66275
DH		 3686 /*
3687 * This union makes it completely explicit to gcc-3.x
3688 * that these two variables' stack usage should be
3689 * combined, not added together.
3690 */
3691 union {
3692 struct kvm_pit_state ps;
e9f42757 3693 struct kvm_pit_state2 ps2;
c5ff41ce 3694 struct kvm_pit_config pit_config;
f0d66275 3695 } u;
1fe779f8
CO		 3696
3697 switch (ioctl) {
3698 case KVM_SET_TSS_ADDR:
3699 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3700 break;
b927a3ce
SY		 3701 case KVM_SET_IDENTITY_MAP_ADDR: {
3702 u64 ident_addr;
3703
3704 r = -EFAULT;
3705 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3706 goto out;
3707 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3708 break;
3709 }
1fe779f8
CO		 3710 case KVM_SET_NR_MMU_PAGES:
3711 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3712 break;
3713 case KVM_GET_NR_MMU_PAGES:
3714 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3715 break;
3ddea128
MT		 3716 case KVM_CREATE_IRQCHIP: {
3717 struct kvm_pic *vpic;
3718
3719 mutex_lock(&kvm->lock);
3720 r = -EEXIST;
3721 if (kvm->arch.vpic)
3722 goto create_irqchip_unlock;
3e515705
AK		 3723 r = -EINVAL;
3724 if (atomic_read(&kvm->online_vcpus))
3725 goto create_irqchip_unlock;
1fe779f8 3726 r = -ENOMEM;
3ddea128
MT		 3727 vpic = kvm_create_pic(kvm);
3728 if (vpic) {
1fe779f8
CO		 3729 r = kvm_ioapic_init(kvm);
3730 if (r) {
175504cd 3731 mutex_lock(&kvm->slots_lock);
72bb2fcd 3732 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3733 &vpic->dev_master);
3734 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3735 &vpic->dev_slave);
3736 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3737 &vpic->dev_eclr);
175504cd 3738 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3739 kfree(vpic);
3740 goto create_irqchip_unlock;
1fe779f8
CO		 3741 }
3742 } else
3ddea128
MT		 3743 goto create_irqchip_unlock;
3744 smp_wmb();
3745 kvm->arch.vpic = vpic;
3746 smp_wmb();
399ec807
AK		 3747 r = kvm_setup_default_irq_routing(kvm);
3748 if (r) {
175504cd 3749 mutex_lock(&kvm->slots_lock);
3ddea128 3750 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3751 kvm_ioapic_destroy(kvm);
3752 kvm_destroy_pic(kvm);
3ddea128 3753 mutex_unlock(&kvm->irq_lock);
175504cd 3754 mutex_unlock(&kvm->slots_lock);
399ec807 3755 }
3ddea128
MT		 3756 create_irqchip_unlock:
3757 mutex_unlock(&kvm->lock);
1fe779f8 3758 break;
3ddea128 3759 }
7837699f 3760 case KVM_CREATE_PIT:
c5ff41ce
JK		 3761 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3762 goto create_pit;
3763 case KVM_CREATE_PIT2:
3764 r = -EFAULT;
3765 if (copy_from_user(&u.pit_config, argp,
3766 sizeof(struct kvm_pit_config)))
3767 goto out;
3768 create_pit:
79fac95e 3769 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3770 r = -EEXIST;
3771 if (kvm->arch.vpit)
3772 goto create_pit_unlock;
7837699f 3773 r = -ENOMEM;
c5ff41ce 3774 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3775 if (kvm->arch.vpit)
3776 r = 0;
269e05e4 3777 create_pit_unlock:
79fac95e 3778 mutex_unlock(&kvm->slots_lock);
7837699f 3779 break;
1fe779f8
CO		 3780 case KVM_GET_IRQCHIP: {
3781 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3782 struct kvm_irqchip *chip;
1fe779f8 3783
ff5c2c03
SL		 3784 chip = memdup_user(argp, sizeof(*chip));
3785 if (IS_ERR(chip)) {
3786 r = PTR_ERR(chip);
1fe779f8 3787 goto out;
ff5c2c03
SL		 3788 }
3789
1fe779f8
CO		 3790 r = -ENXIO;
3791 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3792 goto get_irqchip_out;
3793 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3794 if (r)
f0d66275 3795 goto get_irqchip_out;
1fe779f8 3796 r = -EFAULT;
f0d66275
DH		 3797 if (copy_to_user(argp, chip, sizeof *chip))
3798 goto get_irqchip_out;
1fe779f8 3799 r = 0;
f0d66275
DH		 3800 get_irqchip_out:
3801 kfree(chip);
1fe779f8
CO		 3802 break;
3803 }
3804 case KVM_SET_IRQCHIP: {
3805 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3806 struct kvm_irqchip *chip;
1fe779f8 3807
ff5c2c03
SL		 3808 chip = memdup_user(argp, sizeof(*chip));
3809 if (IS_ERR(chip)) {
3810 r = PTR_ERR(chip);
1fe779f8 3811 goto out;
ff5c2c03
SL		 3812 }
3813
1fe779f8
CO		 3814 r = -ENXIO;
3815 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3816 goto set_irqchip_out;
3817 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3818 if (r)
f0d66275 3819 goto set_irqchip_out;
1fe779f8 3820 r = 0;
f0d66275
DH		 3821 set_irqchip_out:
3822 kfree(chip);
1fe779f8
CO		 3823 break;
3824 }
e0f63cb9 3825 case KVM_GET_PIT: {
e0f63cb9 3826 r = -EFAULT;
f0d66275 3827 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3828 goto out;
3829 r = -ENXIO;
3830 if (!kvm->arch.vpit)
3831 goto out;
f0d66275 3832 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3833 if (r)
3834 goto out;
3835 r = -EFAULT;
f0d66275 3836 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3837 goto out;
3838 r = 0;
3839 break;
3840 }
3841 case KVM_SET_PIT: {
e0f63cb9 3842 r = -EFAULT;
f0d66275 3843 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3844 goto out;
3845 r = -ENXIO;
3846 if (!kvm->arch.vpit)
3847 goto out;
f0d66275 3848 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3849 break;
3850 }
e9f42757
BK		 3851 case KVM_GET_PIT2: {
3852 r = -ENXIO;
3853 if (!kvm->arch.vpit)
3854 goto out;
3855 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3856 if (r)
3857 goto out;
3858 r = -EFAULT;
3859 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3860 goto out;
3861 r = 0;
3862 break;
3863 }
3864 case KVM_SET_PIT2: {
3865 r = -EFAULT;
3866 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3867 goto out;
3868 r = -ENXIO;
3869 if (!kvm->arch.vpit)
3870 goto out;
3871 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3872 break;
3873 }
52d939a0
MT		 3874 case KVM_REINJECT_CONTROL: {
3875 struct kvm_reinject_control control;
3876 r = -EFAULT;
3877 if (copy_from_user(&control, argp, sizeof(control)))
3878 goto out;
3879 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3880 break;
3881 }
ffde22ac
ES		 3882 case KVM_XEN_HVM_CONFIG: {
3883 r = -EFAULT;
3884 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3885 sizeof(struct kvm_xen_hvm_config)))
3886 goto out;
3887 r = -EINVAL;
3888 if (kvm->arch.xen_hvm_config.flags)
3889 goto out;
3890 r = 0;
3891 break;
3892 }
afbcf7ab 3893 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3894 struct kvm_clock_data user_ns;
3895 u64 now_ns;
3896 s64 delta;
3897
3898 r = -EFAULT;
3899 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3900 goto out;
3901
3902 r = -EINVAL;
3903 if (user_ns.flags)
3904 goto out;
3905
3906 r = 0;
395c6b0a 3907 local_irq_disable();
759379dd 3908 now_ns = get_kernel_ns();
afbcf7ab 3909 delta = user_ns.clock - now_ns;
395c6b0a 3910 local_irq_enable();
afbcf7ab 3911 kvm->arch.kvmclock_offset = delta;
2e762ff7 3912 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3913 break;
3914 }
3915 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3916 struct kvm_clock_data user_ns;
3917 u64 now_ns;
3918
395c6b0a 3919 local_irq_disable();
759379dd 3920 now_ns = get_kernel_ns();
afbcf7ab 3921 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3922 local_irq_enable();
afbcf7ab 3923 user_ns.flags = 0;
97e69aa6 3924 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3925
3926 r = -EFAULT;
3927 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3928 goto out;
3929 r = 0;
3930 break;
3931 }
3932
1fe779f8
CO		 3933 default:
3934 ;
3935 }
3936out:
3937 return r;
3938}
3939
a16b043c 3940static void kvm_init_msr_list(void)
043405e1
CO		 3941{
3942 u32 dummy[2];
3943 unsigned i, j;
3944
e3267cbb
GC		 3945 /* skip the first msrs in the list. KVM-specific */
3946 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3947 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3948 continue;
93c4adc7
PB		 3949
3950 /*
3951 * Even MSRs that are valid in the host may not be exposed
3952 * to the guests in some cases. We could work around this
3953 * in VMX with the generic MSR save/load machinery, but it
3954 * is not really worthwhile since it will really only
3955 * happen with nested virtualization.
3956 */
3957 switch (msrs_to_save[i]) {
3958 case MSR_IA32_BNDCFGS:
3959 if (!kvm_x86_ops->mpx_supported())
3960 continue;
3961 break;
3962 default:
3963 break;
3964 }
3965
043405e1
CO		 3966 if (j < i)
3967 msrs_to_save[j] = msrs_to_save[i];
3968 j++;
3969 }
3970 num_msrs_to_save = j;
3971}
3972
bda9020e
MT		 3973static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3974 const void *v)
bbd9b64e 3975{
70252a10
AK		 3976 int handled = 0;
3977 int n;
3978
3979 do {
3980 n = min(len, 8);
3981 if (!(vcpu->arch.apic &&
3982 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3983 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3984 break;
3985 handled += n;
3986 addr += n;
3987 len -= n;
3988 v += n;
3989 } while (len);
bbd9b64e 3990
70252a10 3991 return handled;
bbd9b64e
CO		 3992}
3993
bda9020e 3994static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3995{
70252a10
AK		 3996 int handled = 0;
3997 int n;
3998
3999 do {
4000 n = min(len, 8);
4001 if (!(vcpu->arch.apic &&
4002 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4003 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4004 break;
4005 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4006 handled += n;
4007 addr += n;
4008 len -= n;
4009 v += n;
4010 } while (len);
bbd9b64e 4011
70252a10 4012 return handled;
bbd9b64e
CO		 4013}
4014
2dafc6c2
GN		 4015static void kvm_set_segment(struct kvm_vcpu *vcpu,
4016 struct kvm_segment *var, int seg)
4017{
4018 kvm_x86_ops->set_segment(vcpu, var, seg);
4019}
4020
4021void kvm_get_segment(struct kvm_vcpu *vcpu,
4022 struct kvm_segment *var, int seg)
4023{
4024 kvm_x86_ops->get_segment(vcpu, var, seg);
4025}
4026
e459e322 4027gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4028{
4029 gpa_t t_gpa;
ab9ae313 4030 struct x86_exception exception;
02f59dc9
JR		 4031
4032 BUG_ON(!mmu_is_nested(vcpu));
4033
4034 /* NPT walks are always user-walks */
4035 access |= PFERR_USER_MASK;
ab9ae313 4036 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4037
4038 return t_gpa;
4039}
4040
ab9ae313
AK		 4041gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4042 struct x86_exception *exception)
1871c602
GN		 4043{
4044 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4045 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4046}
4047
ab9ae313
AK		 4048 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4049 struct x86_exception *exception)
1871c602
GN		 4050{
4051 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4052 access |= PFERR_FETCH_MASK;
ab9ae313 4053 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4054}
4055
ab9ae313
AK		 4056gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4057 struct x86_exception *exception)
1871c602
GN		 4058{
4059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4060 access |= PFERR_WRITE_MASK;
ab9ae313 4061 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4062}
4063
4064/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4065gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4066 struct x86_exception *exception)
1871c602 4067{
ab9ae313 4068 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4069}
4070
4071static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4072 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4073 struct x86_exception *exception)
bbd9b64e
CO		 4074{
4075 void *data = val;
10589a46 4076 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4077
4078 while (bytes) {
14dfe855 4079 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4080 exception);
bbd9b64e 4081 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4082 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4083 int ret;
4084
bcc55cba 4085 if (gpa == UNMAPPED_GVA)
ab9ae313 4086 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4087 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4088 if (ret < 0) {
c3cd7ffa 4089 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4090 goto out;
4091 }
bbd9b64e 4092
77c2002e
IE		 4093 bytes -= toread;
4094 data += toread;
4095 addr += toread;
bbd9b64e 4096 }
10589a46 4097out:
10589a46 4098 return r;
bbd9b64e 4099}
77c2002e 4100
1871c602 4101/* used for instruction fetching */
0f65dd70
AK		 4102static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4103 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4104 struct x86_exception *exception)
1871c602 4105{
0f65dd70 4106 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4107 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4108
1871c602 4109 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4110 access | PFERR_FETCH_MASK,
4111 exception);
1871c602
GN		 4112}
4113
064aea77 4114int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4115 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4116 struct x86_exception *exception)
1871c602 4117{
0f65dd70 4118 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4119 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4120
1871c602 4121 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4122 exception);
1871c602 4123}
064aea77 4124EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4125
0f65dd70
AK		 4126static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4127 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4128 struct x86_exception *exception)
1871c602 4129{
0f65dd70 4130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4131 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4132}
4133
6a4d7550 4134int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4135 gva_t addr, void *val,
2dafc6c2 4136 unsigned int bytes,
bcc55cba 4137 struct x86_exception *exception)
77c2002e 4138{
0f65dd70 4139 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4140 void *data = val;
4141 int r = X86EMUL_CONTINUE;
4142
4143 while (bytes) {
14dfe855
JR		 4144 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4145 PFERR_WRITE_MASK,
ab9ae313 4146 exception);
77c2002e
IE		 4147 unsigned offset = addr & (PAGE_SIZE-1);
4148 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4149 int ret;
4150
bcc55cba 4151 if (gpa == UNMAPPED_GVA)
ab9ae313 4152 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4153 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4154 if (ret < 0) {
c3cd7ffa 4155 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4156 goto out;
4157 }
4158
4159 bytes -= towrite;
4160 data += towrite;
4161 addr += towrite;
4162 }
4163out:
4164 return r;
4165}
6a4d7550 4166EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4167
af7cc7d1
XG		 4168static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4169 gpa_t *gpa, struct x86_exception *exception,
4170 bool write)
4171{
97d64b78
AK		 4172 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4173 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4174
97d64b78 4175 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4176 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4177 vcpu->arch.access, access)) {
bebb106a
XG		 4178 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4179 (gva & (PAGE_SIZE - 1));
4f022648 4180 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4181 return 1;
4182 }
4183
af7cc7d1
XG		 4184 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4185
4186 if (*gpa == UNMAPPED_GVA)
4187 return -1;
4188
4189 /* For APIC access vmexit */
4190 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4191 return 1;
4192
4f022648
XG		 4193 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4194 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4195 return 1;
4f022648 4196 }
bebb106a 4197
af7cc7d1
XG		 4198 return 0;
4199}
4200
3200f405 4201int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4202 const void *val, int bytes)
bbd9b64e
CO		 4203{
4204 int ret;
4205
4206 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4207 if (ret < 0)
bbd9b64e 4208 return 0;
f57f2ef5 4209 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4210 return 1;
4211}
4212
77d197b2
XG		 4213struct read_write_emulator_ops {
4214 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4215 int bytes);
4216 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217 void *val, int bytes);
4218 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 int bytes, void *val);
4220 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4221 void *val, int bytes);
4222 bool write;
4223};
4224
4225static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4226{
4227 if (vcpu->mmio_read_completed) {
77d197b2 4228 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4229 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4230 vcpu->mmio_read_completed = 0;
4231 return 1;
4232 }
4233
4234 return 0;
4235}
4236
4237static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4238 void *val, int bytes)
4239{
4240 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4241}
4242
4243static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4244 void *val, int bytes)
4245{
4246 return emulator_write_phys(vcpu, gpa, val, bytes);
4247}
4248
4249static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4250{
4251 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4252 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4253}
4254
4255static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4256 void *val, int bytes)
4257{
4258 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4259 return X86EMUL_IO_NEEDED;
4260}
4261
4262static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4263 void *val, int bytes)
4264{
f78146b0
AK		 4265 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4266
87da7e66 4267 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4268 return X86EMUL_CONTINUE;
4269}
4270
0fbe9b0b 4271static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4272 .read_write_prepare = read_prepare,
4273 .read_write_emulate = read_emulate,
4274 .read_write_mmio = vcpu_mmio_read,
4275 .read_write_exit_mmio = read_exit_mmio,
4276};
4277
0fbe9b0b 4278static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4279 .read_write_emulate = write_emulate,
4280 .read_write_mmio = write_mmio,
4281 .read_write_exit_mmio = write_exit_mmio,
4282 .write = true,
4283};
4284
22388a3c
XG		 4285static int emulator_read_write_onepage(unsigned long addr, void *val,
4286 unsigned int bytes,
4287 struct x86_exception *exception,
4288 struct kvm_vcpu *vcpu,
0fbe9b0b 4289 const struct read_write_emulator_ops *ops)
bbd9b64e 4290{
af7cc7d1
XG		 4291 gpa_t gpa;
4292 int handled, ret;
22388a3c 4293 bool write = ops->write;
f78146b0 4294 struct kvm_mmio_fragment *frag;
10589a46 4295
22388a3c 4296 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4297
af7cc7d1 4298 if (ret < 0)
bbd9b64e 4299 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4300
4301 /* For APIC access vmexit */
af7cc7d1 4302 if (ret)
bbd9b64e
CO		 4303 goto mmio;
4304
22388a3c 4305 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4306 return X86EMUL_CONTINUE;
4307
4308mmio:
4309 /*
4310 * Is this MMIO handled locally?
4311 */
22388a3c 4312 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4313 if (handled == bytes)
bbd9b64e 4314 return X86EMUL_CONTINUE;
bbd9b64e 4315
70252a10
AK		 4316 gpa += handled;
4317 bytes -= handled;
4318 val += handled;
4319
87da7e66
XG		 4320 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4321 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4322 frag->gpa = gpa;
4323 frag->data = val;
4324 frag->len = bytes;
f78146b0 4325 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4326}
4327
22388a3c
XG		 4328int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4329 void *val, unsigned int bytes,
4330 struct x86_exception *exception,
0fbe9b0b 4331 const struct read_write_emulator_ops *ops)
bbd9b64e 4332{
0f65dd70 4333 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4334 gpa_t gpa;
4335 int rc;
4336
4337 if (ops->read_write_prepare &&
4338 ops->read_write_prepare(vcpu, val, bytes))
4339 return X86EMUL_CONTINUE;
4340
4341 vcpu->mmio_nr_fragments = 0;
0f65dd70 4342
bbd9b64e
CO		 4343 /* Crossing a page boundary? */
4344 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4345 int now;
bbd9b64e
CO		 4346
4347 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4348 rc = emulator_read_write_onepage(addr, val, now, exception,
4349 vcpu, ops);
4350
bbd9b64e
CO		 4351 if (rc != X86EMUL_CONTINUE)
4352 return rc;
4353 addr += now;
4354 val += now;
4355 bytes -= now;
4356 }
22388a3c 4357
f78146b0
AK		 4358 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4359 vcpu, ops);
4360 if (rc != X86EMUL_CONTINUE)
4361 return rc;
4362
4363 if (!vcpu->mmio_nr_fragments)
4364 return rc;
4365
4366 gpa = vcpu->mmio_fragments[0].gpa;
4367
4368 vcpu->mmio_needed = 1;
4369 vcpu->mmio_cur_fragment = 0;
4370
87da7e66 4371 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4372 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4373 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4374 vcpu->run->mmio.phys_addr = gpa;
4375
4376 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4377}
4378
4379static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4380 unsigned long addr,
4381 void *val,
4382 unsigned int bytes,
4383 struct x86_exception *exception)
4384{
4385 return emulator_read_write(ctxt, addr, val, bytes,
4386 exception, &read_emultor);
4387}
4388
4389int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4390 unsigned long addr,
4391 const void *val,
4392 unsigned int bytes,
4393 struct x86_exception *exception)
4394{
4395 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4396 exception, &write_emultor);
bbd9b64e 4397}
bbd9b64e 4398
daea3e73
AK		 4399#define CMPXCHG_TYPE(t, ptr, old, new) \
4400 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4401
4402#ifdef CONFIG_X86_64
4403# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4404#else
4405# define CMPXCHG64(ptr, old, new) \
9749a6c0 4406 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4407#endif
4408
0f65dd70
AK		 4409static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4410 unsigned long addr,
bbd9b64e
CO		 4411 const void *old,
4412 const void *new,
4413 unsigned int bytes,
0f65dd70 4414 struct x86_exception *exception)
bbd9b64e 4415{
0f65dd70 4416 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4417 gpa_t gpa;
4418 struct page *page;
4419 char *kaddr;
4420 bool exchanged;
2bacc55c 4421
daea3e73
AK		 4422 /* guests cmpxchg8b have to be emulated atomically */
4423 if (bytes > 8 || (bytes & (bytes - 1)))
4424 goto emul_write;
10589a46 4425
daea3e73 4426 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4427
daea3e73
AK		 4428 if (gpa == UNMAPPED_GVA ||
4429 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4430 goto emul_write;
2bacc55c 4431
daea3e73
AK		 4432 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4433 goto emul_write;
72dc67a6 4434
daea3e73 4435 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4436 if (is_error_page(page))
c19b8bd6 4437 goto emul_write;
72dc67a6 4438
8fd75e12 4439 kaddr = kmap_atomic(page);
daea3e73
AK		 4440 kaddr += offset_in_page(gpa);
4441 switch (bytes) {
4442 case 1:
4443 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4444 break;
4445 case 2:
4446 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4447 break;
4448 case 4:
4449 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4450 break;
4451 case 8:
4452 exchanged = CMPXCHG64(kaddr, old, new);
4453 break;
4454 default:
4455 BUG();
2bacc55c 4456 }
8fd75e12 4457 kunmap_atomic(kaddr);
daea3e73
AK		 4458 kvm_release_page_dirty(page);
4459
4460 if (!exchanged)
4461 return X86EMUL_CMPXCHG_FAILED;
4462
d3714010 4463 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4464 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4465
4466 return X86EMUL_CONTINUE;
4a5f48f6 4467
3200f405 4468emul_write:
daea3e73 4469 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4470
0f65dd70 4471 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4472}
4473
cf8f70bf
GN		 4474static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4475{
4476 /* TODO: String I/O for in kernel device */
4477 int r;
4478
4479 if (vcpu->arch.pio.in)
4480 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4481 vcpu->arch.pio.size, pd);
4482 else
4483 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4484 vcpu->arch.pio.port, vcpu->arch.pio.size,
4485 pd);
4486 return r;
4487}
4488
6f6fbe98
XG		 4489static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4490 unsigned short port, void *val,
4491 unsigned int count, bool in)
cf8f70bf 4492{
cf8f70bf 4493 vcpu->arch.pio.port = port;
6f6fbe98 4494 vcpu->arch.pio.in = in;
7972995b 4495 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4496 vcpu->arch.pio.size = size;
4497
4498 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4499 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4500 return 1;
4501 }
4502
4503 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4504 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4505 vcpu->run->io.size = size;
4506 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4507 vcpu->run->io.count = count;
4508 vcpu->run->io.port = port;
4509
4510 return 0;
4511}
4512
6f6fbe98
XG		 4513static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4514 int size, unsigned short port, void *val,
4515 unsigned int count)
cf8f70bf 4516{
ca1d4a9e 4517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4518 int ret;
ca1d4a9e 4519
6f6fbe98
XG		 4520 if (vcpu->arch.pio.count)
4521 goto data_avail;
cf8f70bf 4522
6f6fbe98
XG		 4523 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4524 if (ret) {
4525data_avail:
4526 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4527 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4528 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4529 return 1;
4530 }
4531
cf8f70bf
GN		 4532 return 0;
4533}
4534
6f6fbe98
XG		 4535static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4536 int size, unsigned short port,
4537 const void *val, unsigned int count)
4538{
4539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4540
4541 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4542 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4543 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4544}
4545
bbd9b64e
CO		 4546static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4547{
4548 return kvm_x86_ops->get_segment_base(vcpu, seg);
4549}
4550
3cb16fe7 4551static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4552{
3cb16fe7 4553 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4554}
4555
f5f48ee1
SY		 4556int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4557{
4558 if (!need_emulate_wbinvd(vcpu))
4559 return X86EMUL_CONTINUE;
4560
4561 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4562 int cpu = get_cpu();
4563
4564 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4565 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4566 wbinvd_ipi, NULL, 1);
2eec7343 4567 put_cpu();
f5f48ee1 4568 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4569 } else
4570 wbinvd();
f5f48ee1
SY		 4571 return X86EMUL_CONTINUE;
4572}
4573EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4574
bcaf5cc5
AK		 4575static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4576{
4577 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4578}
4579
717746e3 4580int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4581{
717746e3 4582 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4583}
4584
717746e3 4585int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4586{
338dbc97 4587
717746e3 4588 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4589}
4590
52a46617 4591static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4592{
52a46617 4593 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4594}
4595
717746e3 4596static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4597{
717746e3 4598 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4599 unsigned long value;
4600
4601 switch (cr) {
4602 case 0:
4603 value = kvm_read_cr0(vcpu);
4604 break;
4605 case 2:
4606 value = vcpu->arch.cr2;
4607 break;
4608 case 3:
9f8fe504 4609 value = kvm_read_cr3(vcpu);
52a46617
GN		 4610 break;
4611 case 4:
4612 value = kvm_read_cr4(vcpu);
4613 break;
4614 case 8:
4615 value = kvm_get_cr8(vcpu);
4616 break;
4617 default:
a737f256 4618 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4619 return 0;
4620 }
4621
4622 return value;
4623}
4624
717746e3 4625static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4626{
717746e3 4627 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4628 int res = 0;
4629
52a46617
GN		 4630 switch (cr) {
4631 case 0:
49a9b07e 4632 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4633 break;
4634 case 2:
4635 vcpu->arch.cr2 = val;
4636 break;
4637 case 3:
2390218b 4638 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4639 break;
4640 case 4:
a83b29c6 4641 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4642 break;
4643 case 8:
eea1cff9 4644 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4645 break;
4646 default:
a737f256 4647 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4648 res = -1;
52a46617 4649 }
0f12244f
GN		 4650
4651 return res;
52a46617
GN		 4652}
4653
717746e3 4654static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4655{
717746e3 4656 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4657}
4658
4bff1e86 4659static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4660{
4bff1e86 4661 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4662}
4663
4bff1e86 4664static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4665{
4bff1e86 4666 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4667}
4668
1ac9d0cf
AK		 4669static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4670{
4671 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4672}
4673
4674static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4675{
4676 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4677}
4678
4bff1e86
AK		 4679static unsigned long emulator_get_cached_segment_base(
4680 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4681{
4bff1e86 4682 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4683}
4684
1aa36616
AK		 4685static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4686 struct desc_struct *desc, u32 *base3,
4687 int seg)
2dafc6c2
GN		 4688{
4689 struct kvm_segment var;
4690
4bff1e86 4691 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4692 *selector = var.selector;
2dafc6c2 4693
378a8b09
GN		 4694 if (var.unusable) {
4695 memset(desc, 0, sizeof(*desc));
2dafc6c2 4696 return false;
378a8b09 4697 }
2dafc6c2
GN		 4698
4699 if (var.g)
4700 var.limit >>= 12;
4701 set_desc_limit(desc, var.limit);
4702 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4703#ifdef CONFIG_X86_64
4704 if (base3)
4705 *base3 = var.base >> 32;
4706#endif
2dafc6c2
GN		 4707 desc->type = var.type;
4708 desc->s = var.s;
4709 desc->dpl = var.dpl;
4710 desc->p = var.present;
4711 desc->avl = var.avl;
4712 desc->l = var.l;
4713 desc->d = var.db;
4714 desc->g = var.g;
4715
4716 return true;
4717}
4718
1aa36616
AK		 4719static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4720 struct desc_struct *desc, u32 base3,
4721 int seg)
2dafc6c2 4722{
4bff1e86 4723 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4724 struct kvm_segment var;
4725
1aa36616 4726 var.selector = selector;
2dafc6c2 4727 var.base = get_desc_base(desc);
5601d05b
GN		 4728#ifdef CONFIG_X86_64
4729 var.base |= ((u64)base3) << 32;
4730#endif
2dafc6c2
GN		 4731 var.limit = get_desc_limit(desc);
4732 if (desc->g)
4733 var.limit = (var.limit << 12) | 0xfff;
4734 var.type = desc->type;
2dafc6c2
GN		 4735 var.dpl = desc->dpl;
4736 var.db = desc->d;
4737 var.s = desc->s;
4738 var.l = desc->l;
4739 var.g = desc->g;
4740 var.avl = desc->avl;
4741 var.present = desc->p;
4742 var.unusable = !var.present;
4743 var.padding = 0;
4744
4745 kvm_set_segment(vcpu, &var, seg);
4746 return;
4747}
4748
717746e3
AK		 4749static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4750 u32 msr_index, u64 *pdata)
4751{
4752 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4753}
4754
4755static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4756 u32 msr_index, u64 data)
4757{
8fe8ab46
WA		 4758 struct msr_data msr;
4759
4760 msr.data = data;
4761 msr.index = msr_index;
4762 msr.host_initiated = false;
4763 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4764}
4765
67f4d428
NA		 4766static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4767 u32 pmc)
4768{
4769 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4770}
4771
222d21aa
AK		 4772static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4773 u32 pmc, u64 *pdata)
4774{
4775 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4776}
4777
6c3287f7
AK		 4778static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4779{
4780 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4781}
4782
5037f6f3
AK		 4783static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4784{
4785 preempt_disable();
5197b808 4786 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4787 /*
4788 * CR0.TS may reference the host fpu state, not the guest fpu state,
4789 * so it may be clear at this point.
4790 */
4791 clts();
4792}
4793
4794static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4795{
4796 preempt_enable();
4797}
4798
2953538e 4799static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4800 struct x86_instruction_info *info,
c4f035c6
AK		 4801 enum x86_intercept_stage stage)
4802{
2953538e 4803 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4804}
4805
0017f93a 4806static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4807 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4808{
0017f93a 4809 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4810}
4811
dd856efa
AK		 4812static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4813{
4814 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4815}
4816
4817static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4818{
4819 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4820}
4821
0225fb50 4822static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4823 .read_gpr = emulator_read_gpr,
4824 .write_gpr = emulator_write_gpr,
1871c602 4825 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4826 .write_std = kvm_write_guest_virt_system,
1871c602 4827 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4828 .read_emulated = emulator_read_emulated,
4829 .write_emulated = emulator_write_emulated,
4830 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4831 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4832 .pio_in_emulated = emulator_pio_in_emulated,
4833 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4834 .get_segment = emulator_get_segment,
4835 .set_segment = emulator_set_segment,
5951c442 4836 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4837 .get_gdt = emulator_get_gdt,
160ce1f1 4838 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4839 .set_gdt = emulator_set_gdt,
4840 .set_idt = emulator_set_idt,
52a46617
GN		 4841 .get_cr = emulator_get_cr,
4842 .set_cr = emulator_set_cr,
9c537244 4843 .cpl = emulator_get_cpl,
35aa5375
GN		 4844 .get_dr = emulator_get_dr,
4845 .set_dr = emulator_set_dr,
717746e3
AK		 4846 .set_msr = emulator_set_msr,
4847 .get_msr = emulator_get_msr,
67f4d428 4848 .check_pmc = emulator_check_pmc,
222d21aa 4849 .read_pmc = emulator_read_pmc,
6c3287f7 4850 .halt = emulator_halt,
bcaf5cc5 4851 .wbinvd = emulator_wbinvd,
d6aa1000 4852 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4853 .get_fpu = emulator_get_fpu,
4854 .put_fpu = emulator_put_fpu,
c4f035c6 4855 .intercept = emulator_intercept,
bdb42f5a 4856 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4857};
4858
95cb2295
GN		 4859static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4860{
37ccdcbe 4861 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4862 /*
4863 * an sti; sti; sequence only disable interrupts for the first
4864 * instruction. So, if the last instruction, be it emulated or
4865 * not, left the system with the INT_STI flag enabled, it
4866 * means that the last instruction is an sti. We should not
4867 * leave the flag on in this case. The same goes for mov ss
4868 */
37ccdcbe
PB		 4869 if (int_shadow & mask)
4870 mask = 0;
4871 if (unlikely(int_shadow || mask))
95cb2295
GN		 4872 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4873}
4874
54b8486f
GN		 4875static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4876{
4877 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4878 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4879 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4880 else if (ctxt->exception.error_code_valid)
4881 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4882 ctxt->exception.error_code);
54b8486f 4883 else
da9cb575 4884 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4885}
4886
dd856efa 4887static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4888{
1ce19dc1
BP		 4889 memset(&ctxt->opcode_len, 0,
4890 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4891
9dac77fa
AK		 4892 ctxt->fetch.start = 0;
4893 ctxt->fetch.end = 0;
4894 ctxt->io_read.pos = 0;
4895 ctxt->io_read.end = 0;
4896 ctxt->mem_read.pos = 0;
4897 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4898}
4899
8ec4722d
MG		 4900static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4901{
adf52235 4902 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4903 int cs_db, cs_l;
4904
8ec4722d
MG		 4905 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4906
adf52235
TY		 4907 ctxt->eflags = kvm_get_rflags(vcpu);
4908 ctxt->eip = kvm_rip_read(vcpu);
4909 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4910 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4911 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4912 cs_db ? X86EMUL_MODE_PROT32 :
4913 X86EMUL_MODE_PROT16;
4914 ctxt->guest_mode = is_guest_mode(vcpu);
4915
dd856efa 4916 init_decode_cache(ctxt);
7ae441ea 4917 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4918}
4919
71f9833b 4920int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4921{
9d74191a 4922 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4923 int ret;
4924
4925 init_emulate_ctxt(vcpu);
4926
9dac77fa
AK		 4927 ctxt->op_bytes = 2;
4928 ctxt->ad_bytes = 2;
4929 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4930 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4931
4932 if (ret != X86EMUL_CONTINUE)
4933 return EMULATE_FAIL;
4934
9dac77fa 4935 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4936 kvm_rip_write(vcpu, ctxt->eip);
4937 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4938
4939 if (irq == NMI_VECTOR)
7460fb4a 4940 vcpu->arch.nmi_pending = 0;
63995653
MG		 4941 else
4942 vcpu->arch.interrupt.pending = false;
4943
4944 return EMULATE_DONE;
4945}
4946EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4947
6d77dbfc
GN		 4948static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4949{
fc3a9157
JR		 4950 int r = EMULATE_DONE;
4951
6d77dbfc
GN		 4952 ++vcpu->stat.insn_emulation_fail;
4953 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4954 if (!is_guest_mode(vcpu)) {
4955 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4956 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4957 vcpu->run->internal.ndata = 0;
4958 r = EMULATE_FAIL;
4959 }
6d77dbfc 4960 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4961
4962 return r;
6d77dbfc
GN		 4963}
4964
93c05d3e 4965static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4966 bool write_fault_to_shadow_pgtable,
4967 int emulation_type)
a6f177ef 4968{
95b3cf69 4969 gpa_t gpa = cr2;
8e3d9d06 4970 pfn_t pfn;
a6f177ef 4971
991eebf9
GN		 4972 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4973 return false;
4974
95b3cf69
XG		 4975 if (!vcpu->arch.mmu.direct_map) {
4976 /*
4977 * Write permission should be allowed since only
4978 * write access need to be emulated.
4979 */
4980 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4981
95b3cf69
XG		 4982 /*
4983 * If the mapping is invalid in guest, let cpu retry
4984 * it to generate fault.
4985 */
4986 if (gpa == UNMAPPED_GVA)
4987 return true;
4988 }
a6f177ef 4989
8e3d9d06
XG		 4990 /*
4991 * Do not retry the unhandleable instruction if it faults on the
4992 * readonly host memory, otherwise it will goto a infinite loop:
4993 * retry instruction -> write #PF -> emulation fail -> retry
4994 * instruction -> ...
4995 */
4996 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4997
4998 /*
4999 * If the instruction failed on the error pfn, it can not be fixed,
5000 * report the error to userspace.
5001 */
5002 if (is_error_noslot_pfn(pfn))
5003 return false;
5004
5005 kvm_release_pfn_clean(pfn);
5006
5007 /* The instructions are well-emulated on direct mmu. */
5008 if (vcpu->arch.mmu.direct_map) {
5009 unsigned int indirect_shadow_pages;
5010
5011 spin_lock(&vcpu->kvm->mmu_lock);
5012 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5013 spin_unlock(&vcpu->kvm->mmu_lock);
5014
5015 if (indirect_shadow_pages)
5016 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5017
a6f177ef 5018 return true;
8e3d9d06 5019 }
a6f177ef 5020
95b3cf69
XG		 5021 /*
5022 * if emulation was due to access to shadowed page table
5023 * and it failed try to unshadow page and re-enter the
5024 * guest to let CPU execute the instruction.
5025 */
5026 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5027
5028 /*
5029 * If the access faults on its page table, it can not
5030 * be fixed by unprotecting shadow page and it should
5031 * be reported to userspace.
5032 */
5033 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5034}
5035
1cb3f3ae
XG		 5036static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5037 unsigned long cr2, int emulation_type)
5038{
5039 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5040 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5041
5042 last_retry_eip = vcpu->arch.last_retry_eip;
5043 last_retry_addr = vcpu->arch.last_retry_addr;
5044
5045 /*
5046 * If the emulation is caused by #PF and it is non-page_table
5047 * writing instruction, it means the VM-EXIT is caused by shadow
5048 * page protected, we can zap the shadow page and retry this
5049 * instruction directly.
5050 *
5051 * Note: if the guest uses a non-page-table modifying instruction
5052 * on the PDE that points to the instruction, then we will unmap
5053 * the instruction and go to an infinite loop. So, we cache the
5054 * last retried eip and the last fault address, if we meet the eip
5055 * and the address again, we can break out of the potential infinite
5056 * loop.
5057 */
5058 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5059
5060 if (!(emulation_type & EMULTYPE_RETRY))
5061 return false;
5062
5063 if (x86_page_table_writing_insn(ctxt))
5064 return false;
5065
5066 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5067 return false;
5068
5069 vcpu->arch.last_retry_eip = ctxt->eip;
5070 vcpu->arch.last_retry_addr = cr2;
5071
5072 if (!vcpu->arch.mmu.direct_map)
5073 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5074
22368028 5075 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5076
5077 return true;
5078}
5079
716d51ab
GN		 5080static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5081static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5082
4a1e10d5
PB		 5083static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5084 unsigned long *db)
5085{
5086 u32 dr6 = 0;
5087 int i;
5088 u32 enable, rwlen;
5089
5090 enable = dr7;
5091 rwlen = dr7 >> 16;
5092 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5093 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5094 dr6 |= (1 << i);
5095 return dr6;
5096}
5097
663f4c61
PB		 5098static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5099{
5100 struct kvm_run *kvm_run = vcpu->run;
5101
5102 /*
5103 * Use the "raw" value to see if TF was passed to the processor.
5104 * Note that the new value of the flags has not been saved yet.
5105 *
5106 * This is correct even for TF set by the guest, because "the
5107 * processor will not generate this exception after the instruction
5108 * that sets the TF flag".
5109 */
5110 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5111
5112 if (unlikely(rflags & X86_EFLAGS_TF)) {
5113 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5114 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5115 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5116 kvm_run->debug.arch.exception = DB_VECTOR;
5117 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5118 *r = EMULATE_USER_EXIT;
5119 } else {
5120 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5121 /*
5122 * "Certain debug exceptions may clear bit 0-3. The
5123 * remaining contents of the DR6 register are never
5124 * cleared by the processor".
5125 */
5126 vcpu->arch.dr6 &= ~15;
5127 vcpu->arch.dr6 |= DR6_BS;
5128 kvm_queue_exception(vcpu, DB_VECTOR);
5129 }
5130 }
5131}
5132
4a1e10d5
PB		 5133static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5134{
5135 struct kvm_run *kvm_run = vcpu->run;
5136 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5137 u32 dr6 = 0;
5138
5139 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5140 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5141 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5142 vcpu->arch.guest_debug_dr7,
5143 vcpu->arch.eff_db);
5144
5145 if (dr6 != 0) {
5146 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5147 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5148 get_segment_base(vcpu, VCPU_SREG_CS);
5149
5150 kvm_run->debug.arch.exception = DB_VECTOR;
5151 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5152 *r = EMULATE_USER_EXIT;
5153 return true;
5154 }
5155 }
5156
5157 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5158 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5159 vcpu->arch.dr7,
5160 vcpu->arch.db);
5161
5162 if (dr6 != 0) {
5163 vcpu->arch.dr6 &= ~15;
5164 vcpu->arch.dr6 |= dr6;
5165 kvm_queue_exception(vcpu, DB_VECTOR);
5166 *r = EMULATE_DONE;
5167 return true;
5168 }
5169 }
5170
5171 return false;
5172}
5173
51d8b661
AP		 5174int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5175 unsigned long cr2,
dc25e89e
AP		 5176 int emulation_type,
5177 void *insn,
5178 int insn_len)
bbd9b64e 5179{
95cb2295 5180 int r;
9d74191a 5181 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5182 bool writeback = true;
93c05d3e 5183 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5184
93c05d3e
XG		 5185 /*
5186 * Clear write_fault_to_shadow_pgtable here to ensure it is
5187 * never reused.
5188 */
5189 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5190 kvm_clear_exception_queue(vcpu);
8d7d8102 5191
571008da 5192 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5193 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5194
5195 /*
5196 * We will reenter on the same instruction since
5197 * we do not set complete_userspace_io. This does not
5198 * handle watchpoints yet, those would be handled in
5199 * the emulate_ops.
5200 */
5201 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5202 return r;
5203
9d74191a
TY		 5204 ctxt->interruptibility = 0;
5205 ctxt->have_exception = false;
5206 ctxt->perm_ok = false;
bbd9b64e 5207
b51e974f 5208 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5209
9d74191a 5210 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5211
e46479f8 5212 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5213 ++vcpu->stat.insn_emulation;
1d2887e2 5214 if (r != EMULATION_OK) {
4005996e
AK		 5215 if (emulation_type & EMULTYPE_TRAP_UD)
5216 return EMULATE_FAIL;
991eebf9
GN		 5217 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5218 emulation_type))
bbd9b64e 5219 return EMULATE_DONE;
6d77dbfc
GN		 5220 if (emulation_type & EMULTYPE_SKIP)
5221 return EMULATE_FAIL;
5222 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5223 }
5224 }
5225
ba8afb6b 5226 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5227 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5228 return EMULATE_DONE;
5229 }
5230
1cb3f3ae
XG		 5231 if (retry_instruction(ctxt, cr2, emulation_type))
5232 return EMULATE_DONE;
5233
7ae441ea 5234 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5235 changes registers values during IO operation */
7ae441ea
GN		 5236 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5237 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5238 emulator_invalidate_register_cache(ctxt);
7ae441ea 5239 }
4d2179e1 5240
5cd21917 5241restart:
9d74191a 5242 r = x86_emulate_insn(ctxt);
bbd9b64e 5243
775fde86
JR		 5244 if (r == EMULATION_INTERCEPTED)
5245 return EMULATE_DONE;
5246
d2ddd1c4 5247 if (r == EMULATION_FAILED) {
991eebf9
GN		 5248 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5249 emulation_type))
c3cd7ffa
GN		 5250 return EMULATE_DONE;
5251
6d77dbfc 5252 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5253 }
5254
9d74191a 5255 if (ctxt->have_exception) {
54b8486f 5256 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5257 r = EMULATE_DONE;
5258 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5259 if (!vcpu->arch.pio.in) {
5260 /* FIXME: return into emulator if single-stepping. */
3457e419 5261 vcpu->arch.pio.count = 0;
0912c977 5262 } else {
7ae441ea 5263 writeback = false;
716d51ab
GN		 5264 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5265 }
ac0a48c3 5266 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5267 } else if (vcpu->mmio_needed) {
5268 if (!vcpu->mmio_is_write)
5269 writeback = false;
ac0a48c3 5270 r = EMULATE_USER_EXIT;
716d51ab 5271 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5272 } else if (r == EMULATION_RESTART)
5cd21917 5273 goto restart;
d2ddd1c4
GN		 5274 else
5275 r = EMULATE_DONE;
f850e2e6 5276
7ae441ea 5277 if (writeback) {
9d74191a 5278 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5279 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5280 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5281 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5282 if (r == EMULATE_DONE)
5283 kvm_vcpu_check_singlestep(vcpu, &r);
5284 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5285 } else
5286 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5287
5288 return r;
de7d789a 5289}
51d8b661 5290EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5291
cf8f70bf 5292int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5293{
cf8f70bf 5294 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5295 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5296 size, port, &val, 1);
cf8f70bf 5297 /* do not return to emulator after return from userspace */
7972995b 5298 vcpu->arch.pio.count = 0;
de7d789a
CO		 5299 return ret;
5300}
cf8f70bf 5301EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5302
8cfdc000
ZA		 5303static void tsc_bad(void *info)
5304{
0a3aee0d 5305 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5306}
5307
5308static void tsc_khz_changed(void *data)
c8076604 5309{
8cfdc000
ZA		 5310 struct cpufreq_freqs *freq = data;
5311 unsigned long khz = 0;
5312
5313 if (data)
5314 khz = freq->new;
5315 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5316 khz = cpufreq_quick_get(raw_smp_processor_id());
5317 if (!khz)
5318 khz = tsc_khz;
0a3aee0d 5319 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5320}
5321
c8076604
GH		 5322static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5323 void *data)
5324{
5325 struct cpufreq_freqs *freq = data;
5326 struct kvm *kvm;
5327 struct kvm_vcpu *vcpu;
5328 int i, send_ipi = 0;
5329
8cfdc000
ZA		 5330 /*
5331 * We allow guests to temporarily run on slowing clocks,
5332 * provided we notify them after, or to run on accelerating
5333 * clocks, provided we notify them before. Thus time never
5334 * goes backwards.
5335 *
5336 * However, we have a problem. We can't atomically update
5337 * the frequency of a given CPU from this function; it is
5338 * merely a notifier, which can be called from any CPU.
5339 * Changing the TSC frequency at arbitrary points in time
5340 * requires a recomputation of local variables related to
5341 * the TSC for each VCPU. We must flag these local variables
5342 * to be updated and be sure the update takes place with the
5343 * new frequency before any guests proceed.
5344 *
5345 * Unfortunately, the combination of hotplug CPU and frequency
5346 * change creates an intractable locking scenario; the order
5347 * of when these callouts happen is undefined with respect to
5348 * CPU hotplug, and they can race with each other. As such,
5349 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5350 * undefined; you can actually have a CPU frequency change take
5351 * place in between the computation of X and the setting of the
5352 * variable. To protect against this problem, all updates of
5353 * the per_cpu tsc_khz variable are done in an interrupt
5354 * protected IPI, and all callers wishing to update the value
5355 * must wait for a synchronous IPI to complete (which is trivial
5356 * if the caller is on the CPU already). This establishes the
5357 * necessary total order on variable updates.
5358 *
5359 * Note that because a guest time update may take place
5360 * anytime after the setting of the VCPU's request bit, the
5361 * correct TSC value must be set before the request. However,
5362 * to ensure the update actually makes it to any guest which
5363 * starts running in hardware virtualization between the set
5364 * and the acquisition of the spinlock, we must also ping the
5365 * CPU after setting the request bit.
5366 *
5367 */
5368
c8076604
GH		 5369 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5370 return 0;
5371 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5372 return 0;
8cfdc000
ZA		 5373
5374 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5375
2f303b74 5376 spin_lock(&kvm_lock);
c8076604 5377 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5378 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5379 if (vcpu->cpu != freq->cpu)
5380 continue;
c285545f 5381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5382 if (vcpu->cpu != smp_processor_id())
8cfdc000 5383 send_ipi = 1;
c8076604
GH		 5384 }
5385 }
2f303b74 5386 spin_unlock(&kvm_lock);
c8076604
GH		 5387
5388 if (freq->old < freq->new && send_ipi) {
5389 /*
5390 * We upscale the frequency. Must make the guest
5391 * doesn't see old kvmclock values while running with
5392 * the new frequency, otherwise we risk the guest sees
5393 * time go backwards.
5394 *
5395 * In case we update the frequency for another cpu
5396 * (which might be in guest context) send an interrupt
5397 * to kick the cpu out of guest context. Next time
5398 * guest context is entered kvmclock will be updated,
5399 * so the guest will not see stale values.
5400 */
8cfdc000 5401 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5402 }
5403 return 0;
5404}
5405
5406static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5407 .notifier_call = kvmclock_cpufreq_notifier
5408};
5409
5410static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5411 unsigned long action, void *hcpu)
5412{
5413 unsigned int cpu = (unsigned long)hcpu;
5414
5415 switch (action) {
5416 case CPU_ONLINE:
5417 case CPU_DOWN_FAILED:
5418 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5419 break;
5420 case CPU_DOWN_PREPARE:
5421 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5422 break;
5423 }
5424 return NOTIFY_OK;
5425}
5426
5427static struct notifier_block kvmclock_cpu_notifier_block = {
5428 .notifier_call = kvmclock_cpu_notifier,
5429 .priority = -INT_MAX
c8076604
GH		 5430};
5431
b820cc0c
ZA		 5432static void kvm_timer_init(void)
5433{
5434 int cpu;
5435
c285545f 5436 max_tsc_khz = tsc_khz;
460dd42e
SB		 5437
5438 cpu_notifier_register_begin();
b820cc0c 5439 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5440#ifdef CONFIG_CPU_FREQ
5441 struct cpufreq_policy policy;
5442 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5443 cpu = get_cpu();
5444 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5445 if (policy.cpuinfo.max_freq)
5446 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5447 put_cpu();
c285545f 5448#endif
b820cc0c
ZA		 5449 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5450 CPUFREQ_TRANSITION_NOTIFIER);
5451 }
c285545f 5452 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5453 for_each_online_cpu(cpu)
5454 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5455
5456 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5457 cpu_notifier_register_done();
5458
b820cc0c
ZA		 5459}
5460
ff9d07a0
ZY		 5461static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5462
f5132b01 5463int kvm_is_in_guest(void)
ff9d07a0 5464{
086c9855 5465 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5466}
5467
5468static int kvm_is_user_mode(void)
5469{
5470 int user_mode = 3;
dcf46b94 5471
086c9855
AS		 5472 if (__this_cpu_read(current_vcpu))
5473 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5474
ff9d07a0
ZY		 5475 return user_mode != 0;
5476}
5477
5478static unsigned long kvm_get_guest_ip(void)
5479{
5480 unsigned long ip = 0;
dcf46b94 5481
086c9855
AS		 5482 if (__this_cpu_read(current_vcpu))
5483 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5484
ff9d07a0
ZY		 5485 return ip;
5486}
5487
5488static struct perf_guest_info_callbacks kvm_guest_cbs = {
5489 .is_in_guest = kvm_is_in_guest,
5490 .is_user_mode = kvm_is_user_mode,
5491 .get_guest_ip = kvm_get_guest_ip,
5492};
5493
5494void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5495{
086c9855 5496 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5497}
5498EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5499
5500void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5501{
086c9855 5502 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5503}
5504EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5505
ce88decf
XG		 5506static void kvm_set_mmio_spte_mask(void)
5507{
5508 u64 mask;
5509 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5510
5511 /*
5512 * Set the reserved bits and the present bit of an paging-structure
5513 * entry to generate page fault with PFER.RSV = 1.
5514 */
885032b9
XG		 5515 /* Mask the reserved physical address bits. */
5516 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5517
5518 /* Bit 62 is always reserved for 32bit host. */
5519 mask |= 0x3ull << 62;
5520
5521 /* Set the present bit. */
ce88decf
XG		 5522 mask |= 1ull;
5523
5524#ifdef CONFIG_X86_64
5525 /*
5526 * If reserved bit is not supported, clear the present bit to disable
5527 * mmio page fault.
5528 */
5529 if (maxphyaddr == 52)
5530 mask &= ~1ull;
5531#endif
5532
5533 kvm_mmu_set_mmio_spte_mask(mask);
5534}
5535
16e8d74d
MT		 5536#ifdef CONFIG_X86_64
5537static void pvclock_gtod_update_fn(struct work_struct *work)
5538{
d828199e
MT		 5539 struct kvm *kvm;
5540
5541 struct kvm_vcpu *vcpu;
5542 int i;
5543
2f303b74 5544 spin_lock(&kvm_lock);
d828199e
MT		 5545 list_for_each_entry(kvm, &vm_list, vm_list)
5546 kvm_for_each_vcpu(i, vcpu, kvm)
5547 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5548 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5549 spin_unlock(&kvm_lock);
16e8d74d
MT		 5550}
5551
5552static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5553
5554/*
5555 * Notification about pvclock gtod data update.
5556 */
5557static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5558 void *priv)
5559{
5560 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5561 struct timekeeper *tk = priv;
5562
5563 update_pvclock_gtod(tk);
5564
5565 /* disable master clock if host does not trust, or does not
5566 * use, TSC clocksource
5567 */
5568 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5569 atomic_read(&kvm_guest_has_master_clock) != 0)
5570 queue_work(system_long_wq, &pvclock_gtod_work);
5571
5572 return 0;
5573}
5574
5575static struct notifier_block pvclock_gtod_notifier = {
5576 .notifier_call = pvclock_gtod_notify,
5577};
5578#endif
5579
f8c16bba 5580int kvm_arch_init(void *opaque)
043405e1 5581{
b820cc0c 5582 int r;
6b61edf7 5583 struct kvm_x86_ops *ops = opaque;
f8c16bba 5584
f8c16bba
ZX		 5585 if (kvm_x86_ops) {
5586 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5587 r = -EEXIST;
5588 goto out;
f8c16bba
ZX		 5589 }
5590
5591 if (!ops->cpu_has_kvm_support()) {
5592 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5593 r = -EOPNOTSUPP;
5594 goto out;
f8c16bba
ZX		 5595 }
5596 if (ops->disabled_by_bios()) {
5597 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5598 r = -EOPNOTSUPP;
5599 goto out;
f8c16bba
ZX		 5600 }
5601
013f6a5d
MT		 5602 r = -ENOMEM;
5603 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5604 if (!shared_msrs) {
5605 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5606 goto out;
5607 }
5608
97db56ce
AK		 5609 r = kvm_mmu_module_init();
5610 if (r)
013f6a5d 5611 goto out_free_percpu;
97db56ce 5612
ce88decf 5613 kvm_set_mmio_spte_mask();
97db56ce 5614
f8c16bba 5615 kvm_x86_ops = ops;
920c8377
PB		 5616 kvm_init_msr_list();
5617
7b52345e 5618 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5619 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5620
b820cc0c 5621 kvm_timer_init();
c8076604 5622
ff9d07a0
ZY		 5623 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5624
2acf923e
DC		 5625 if (cpu_has_xsave)
5626 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5627
c5cc421b 5628 kvm_lapic_init();
16e8d74d
MT		 5629#ifdef CONFIG_X86_64
5630 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5631#endif
5632
f8c16bba 5633 return 0;
56c6d28a 5634
013f6a5d
MT		 5635out_free_percpu:
5636 free_percpu(shared_msrs);
56c6d28a 5637out:
56c6d28a 5638 return r;
043405e1 5639}
8776e519 5640
f8c16bba
ZX		 5641void kvm_arch_exit(void)
5642{
ff9d07a0
ZY		 5643 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5644
888d256e
JK		 5645 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5646 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5647 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5648 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5649#ifdef CONFIG_X86_64
5650 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5651#endif
f8c16bba 5652 kvm_x86_ops = NULL;
56c6d28a 5653 kvm_mmu_module_exit();
013f6a5d 5654 free_percpu(shared_msrs);
56c6d28a 5655}
f8c16bba 5656
8776e519
HB		 5657int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5658{
5659 ++vcpu->stat.halt_exits;
5660 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5661 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5662 return 1;
5663 } else {
5664 vcpu->run->exit_reason = KVM_EXIT_HLT;
5665 return 0;
5666 }
5667}
5668EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5669
55cd8e5a
GN		 5670int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5671{
5672 u64 param, ingpa, outgpa, ret;
5673 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5674 bool fast, longmode;
55cd8e5a
GN		 5675
5676 /*
5677 * hypercall generates UD from non zero cpl and real mode
5678 * per HYPER-V spec
5679 */
3eeb3288 5680 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5681 kvm_queue_exception(vcpu, UD_VECTOR);
5682 return 0;
5683 }
5684
a449c7aa 5685 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5686
5687 if (!longmode) {
ccd46936
GN		 5688 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5689 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5690 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5691 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5692 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5693 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5694 }
5695#ifdef CONFIG_X86_64
5696 else {
5697 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5698 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5699 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5700 }
5701#endif
5702
5703 code = param & 0xffff;
5704 fast = (param >> 16) & 0x1;
5705 rep_cnt = (param >> 32) & 0xfff;
5706 rep_idx = (param >> 48) & 0xfff;
5707
5708 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5709
c25bc163
GN		 5710 switch (code) {
5711 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5712 kvm_vcpu_on_spin(vcpu);
5713 break;
5714 default:
5715 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5716 break;
5717 }
55cd8e5a
GN		 5718
5719 ret = res | (((u64)rep_done & 0xfff) << 32);
5720 if (longmode) {
5721 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5722 } else {
5723 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5724 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5725 }
5726
5727 return 1;
5728}
5729
6aef266c
SV		 5730/*
5731 * kvm_pv_kick_cpu_op: Kick a vcpu.
5732 *
5733 * @apicid - apicid of vcpu to be kicked.
5734 */
5735static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5736{
24d2166b 5737 struct kvm_lapic_irq lapic_irq;
6aef266c 5738
24d2166b
R		 5739 lapic_irq.shorthand = 0;
5740 lapic_irq.dest_mode = 0;
5741 lapic_irq.dest_id = apicid;
6aef266c 5742
24d2166b
R		 5743 lapic_irq.delivery_mode = APIC_DM_REMRD;
5744 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5745}
5746
8776e519
HB		 5747int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5748{
5749 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5750 int op_64_bit, r = 1;
8776e519 5751
55cd8e5a
GN		 5752 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5753 return kvm_hv_hypercall(vcpu);
5754
5fdbf976
MT		 5755 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5756 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5757 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5758 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5759 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5760
229456fc 5761 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5762
a449c7aa
NA		 5763 op_64_bit = is_64_bit_mode(vcpu);
5764 if (!op_64_bit) {
8776e519
HB		 5765 nr &= 0xFFFFFFFF;
5766 a0 &= 0xFFFFFFFF;
5767 a1 &= 0xFFFFFFFF;
5768 a2 &= 0xFFFFFFFF;
5769 a3 &= 0xFFFFFFFF;
5770 }
5771
07708c4a
JK		 5772 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5773 ret = -KVM_EPERM;
5774 goto out;
5775 }
5776
8776e519 5777 switch (nr) {
b93463aa
AK		 5778 case KVM_HC_VAPIC_POLL_IRQ:
5779 ret = 0;
5780 break;
6aef266c
SV		 5781 case KVM_HC_KICK_CPU:
5782 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5783 ret = 0;
5784 break;
8776e519
HB		 5785 default:
5786 ret = -KVM_ENOSYS;
5787 break;
5788 }
07708c4a 5789out:
a449c7aa
NA		 5790 if (!op_64_bit)
5791 ret = (u32)ret;
5fdbf976 5792 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5793 ++vcpu->stat.hypercalls;
2f333bcb 5794 return r;
8776e519
HB		 5795}
5796EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5797
b6785def 5798static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5799{
d6aa1000 5800 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5801 char instruction[3];
5fdbf976 5802 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5803
8776e519 5804 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5805
9d74191a 5806 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5807}
5808
b6c7a5dc
HB		 5809/*
5810 * Check if userspace requested an interrupt window, and that the
5811 * interrupt window is open.
5812 *
5813 * No need to exit to userspace if we already have an interrupt queued.
5814 */
851ba692 5815static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5816{
8061823a 5817 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5818 vcpu->run->request_interrupt_window &&
5df56646 5819 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5820}
5821
851ba692 5822static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5823{
851ba692
AK		 5824 struct kvm_run *kvm_run = vcpu->run;
5825
91586a3b 5826 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5827 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5828 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5829 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5830 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5831 else
b6c7a5dc 5832 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5833 kvm_arch_interrupt_allowed(vcpu) &&
5834 !kvm_cpu_has_interrupt(vcpu) &&
5835 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5836}
5837
95ba8273
GN		 5838static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5839{
5840 int max_irr, tpr;
5841
5842 if (!kvm_x86_ops->update_cr8_intercept)
5843 return;
5844
88c808fd
AK		 5845 if (!vcpu->arch.apic)
5846 return;
5847
8db3baa2
GN		 5848 if (!vcpu->arch.apic->vapic_addr)
5849 max_irr = kvm_lapic_find_highest_irr(vcpu);
5850 else
5851 max_irr = -1;
95ba8273
GN		 5852
5853 if (max_irr != -1)
5854 max_irr >>= 4;
5855
5856 tpr = kvm_lapic_get_cr8(vcpu);
5857
5858 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5859}
5860
b6b8a145 5861static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5862{
b6b8a145
JK		 5863 int r;
5864
95ba8273 5865 /* try to reinject previous events if any */
b59bb7bd 5866 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5867 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5868 vcpu->arch.exception.has_error_code,
5869 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5870 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5871 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5872 vcpu->arch.exception.error_code,
5873 vcpu->arch.exception.reinject);
b6b8a145 5874 return 0;
b59bb7bd
GN		 5875 }
5876
95ba8273
GN		 5877 if (vcpu->arch.nmi_injected) {
5878 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5879 return 0;
95ba8273
GN		 5880 }
5881
5882 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5883 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5884 return 0;
5885 }
5886
5887 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5888 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5889 if (r != 0)
5890 return r;
95ba8273
GN		 5891 }
5892
5893 /* try to inject new event if pending */
5894 if (vcpu->arch.nmi_pending) {
5895 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5896 --vcpu->arch.nmi_pending;
95ba8273
GN		 5897 vcpu->arch.nmi_injected = true;
5898 kvm_x86_ops->set_nmi(vcpu);
5899 }
c7c9c56c 5900 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5901 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5902 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5903 false);
5904 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5905 }
5906 }
b6b8a145 5907 return 0;
95ba8273
GN		 5908}
5909
7460fb4a
AK		 5910static void process_nmi(struct kvm_vcpu *vcpu)
5911{
5912 unsigned limit = 2;
5913
5914 /*
5915 * x86 is limited to one NMI running, and one NMI pending after it.
5916 * If an NMI is already in progress, limit further NMIs to just one.
5917 * Otherwise, allow two (and we'll inject the first one immediately).
5918 */
5919 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5920 limit = 1;
5921
5922 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5923 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5924 kvm_make_request(KVM_REQ_EVENT, vcpu);
5925}
5926
3d81bc7e 5927static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5928{
5929 u64 eoi_exit_bitmap[4];
cf9e65b7 5930 u32 tmr[8];
c7c9c56c 5931
3d81bc7e
YZ		 5932 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5933 return;
c7c9c56c
YZ		 5934
5935 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5936 memset(tmr, 0, 32);
c7c9c56c 5937
cf9e65b7 5938 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5939 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5940 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5941}
5942
9357d939
TY		 5943/*
5944 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5945 * exiting to the userspace. Otherwise, the value will be returned to the
5946 * userspace.
5947 */
851ba692 5948static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5949{
5950 int r;
6a8b1d13 5951 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5952 vcpu->run->request_interrupt_window;
730dca42 5953 bool req_immediate_exit = false;
b6c7a5dc 5954
3e007509 5955 if (vcpu->requests) {
a8eeb04a 5956 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5957 kvm_mmu_unload(vcpu);
a8eeb04a 5958 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5959 __kvm_migrate_timers(vcpu);
d828199e
MT		 5960 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5961 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5962 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5963 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5964 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5965 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5966 if (unlikely(r))
5967 goto out;
5968 }
a8eeb04a 5969 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5970 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5971 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5972 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5973 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5974 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5975 r = 0;
5976 goto out;
5977 }
a8eeb04a 5978 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5979 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5980 r = 0;
5981 goto out;
5982 }
a8eeb04a 5983 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5984 vcpu->fpu_active = 0;
5985 kvm_x86_ops->fpu_deactivate(vcpu);
5986 }
af585b92
GN		 5987 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5988 /* Page is swapped out. Do synthetic halt */
5989 vcpu->arch.apf.halted = true;
5990 r = 1;
5991 goto out;
5992 }
c9aaa895
GC		 5993 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5994 record_steal_time(vcpu);
7460fb4a
AK		 5995 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5996 process_nmi(vcpu);
f5132b01
GN		 5997 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5998 kvm_handle_pmu_event(vcpu);
5999 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6000 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6001 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6002 vcpu_scan_ioapic(vcpu);
2f52d58c 6003 }
b93463aa 6004
b463a6f7 6005 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6006 kvm_apic_accept_events(vcpu);
6007 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6008 r = 1;
6009 goto out;
6010 }
6011
b6b8a145
JK		 6012 if (inject_pending_event(vcpu, req_int_win) != 0)
6013 req_immediate_exit = true;
b463a6f7 6014 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6015 else if (vcpu->arch.nmi_pending)
c9a7953f 6016 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6017 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6018 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6019
6020 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6021 /*
6022 * Update architecture specific hints for APIC
6023 * virtual interrupt delivery.
6024 */
6025 if (kvm_x86_ops->hwapic_irr_update)
6026 kvm_x86_ops->hwapic_irr_update(vcpu,
6027 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6028 update_cr8_intercept(vcpu);
6029 kvm_lapic_sync_to_vapic(vcpu);
6030 }
6031 }
6032
d8368af8
AK		 6033 r = kvm_mmu_reload(vcpu);
6034 if (unlikely(r)) {
d905c069 6035 goto cancel_injection;
d8368af8
AK		 6036 }
6037
b6c7a5dc
HB		 6038 preempt_disable();
6039
6040 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6041 if (vcpu->fpu_active)
6042 kvm_load_guest_fpu(vcpu);
2acf923e 6043 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6044
6b7e2d09
XG		 6045 vcpu->mode = IN_GUEST_MODE;
6046
01b71917
MT		 6047 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6048
6b7e2d09
XG		 6049 /* We should set ->mode before check ->requests,
6050 * see the comment in make_all_cpus_request.
6051 */
01b71917 6052 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6053
d94e1dc9 6054 local_irq_disable();
32f88400 6055
6b7e2d09 6056 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6057 || need_resched() || signal_pending(current)) {
6b7e2d09 6058 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6059 smp_wmb();
6c142801
AK		 6060 local_irq_enable();
6061 preempt_enable();
01b71917 6062 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6063 r = 1;
d905c069 6064 goto cancel_injection;
6c142801
AK		 6065 }
6066
d6185f20
NHE		 6067 if (req_immediate_exit)
6068 smp_send_reschedule(vcpu->cpu);
6069
b6c7a5dc
HB		 6070 kvm_guest_enter();
6071
42dbaa5a 6072 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6073 set_debugreg(0, 7);
6074 set_debugreg(vcpu->arch.eff_db[0], 0);
6075 set_debugreg(vcpu->arch.eff_db[1], 1);
6076 set_debugreg(vcpu->arch.eff_db[2], 2);
6077 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6078 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6079 }
b6c7a5dc 6080
229456fc 6081 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6082 kvm_x86_ops->run(vcpu);
b6c7a5dc 6083
c77fb5fe
PB		 6084 /*
6085 * Do this here before restoring debug registers on the host. And
6086 * since we do this before handling the vmexit, a DR access vmexit
6087 * can (a) read the correct value of the debug registers, (b) set
6088 * KVM_DEBUGREG_WONT_EXIT again.
6089 */
6090 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6091 int i;
6092
6093 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6094 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6095 for (i = 0; i < KVM_NR_DB_REGS; i++)
6096 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6097 }
6098
24f1e32c
FW		 6099 /*
6100 * If the guest has used debug registers, at least dr7
6101 * will be disabled while returning to the host.
6102 * If we don't have active breakpoints in the host, we don't
6103 * care about the messed up debug address registers. But if
6104 * we have some of them active, restore the old state.
6105 */
59d8eb53 6106 if (hw_breakpoint_active())
24f1e32c 6107 hw_breakpoint_restore();
42dbaa5a 6108
886b470c
MT		 6109 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6110 native_read_tsc());
1d5f066e 6111
6b7e2d09 6112 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6113 smp_wmb();
a547c6db
YZ		 6114
6115 /* Interrupt is enabled by handle_external_intr() */
6116 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6117
6118 ++vcpu->stat.exits;
6119
6120 /*
6121 * We must have an instruction between local_irq_enable() and
6122 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6123 * the interrupt shadow. The stat.exits increment will do nicely.
6124 * But we need to prevent reordering, hence this barrier():
6125 */
6126 barrier();
6127
6128 kvm_guest_exit();
6129
6130 preempt_enable();
6131
f656ce01 6132 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6133
b6c7a5dc
HB		 6134 /*
6135 * Profile KVM exit RIPs:
6136 */
6137 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6138 unsigned long rip = kvm_rip_read(vcpu);
6139 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6140 }
6141
cc578287
ZA		 6142 if (unlikely(vcpu->arch.tsc_always_catchup))
6143 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6144
5cfb1d5a
MT		 6145 if (vcpu->arch.apic_attention)
6146 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6147
851ba692 6148 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6149 return r;
6150
6151cancel_injection:
6152 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6153 if (unlikely(vcpu->arch.apic_attention))
6154 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6155out:
6156 return r;
6157}
b6c7a5dc 6158
09cec754 6159
851ba692 6160static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6161{
6162 int r;
f656ce01 6163 struct kvm *kvm = vcpu->kvm;
d7690175 6164
f656ce01 6165 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6166
6167 r = 1;
6168 while (r > 0) {
af585b92
GN		 6169 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6170 !vcpu->arch.apf.halted)
851ba692 6171 r = vcpu_enter_guest(vcpu);
d7690175 6172 else {
f656ce01 6173 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6174 kvm_vcpu_block(vcpu);
f656ce01 6175 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6176 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6177 kvm_apic_accept_events(vcpu);
09cec754
GN		 6178 switch(vcpu->arch.mp_state) {
6179 case KVM_MP_STATE_HALTED:
6aef266c 6180 vcpu->arch.pv.pv_unhalted = false;
d7690175 6181 vcpu->arch.mp_state =
09cec754
GN		 6182 KVM_MP_STATE_RUNNABLE;
6183 case KVM_MP_STATE_RUNNABLE:
af585b92 6184 vcpu->arch.apf.halted = false;
09cec754 6185 break;
66450a21
JK		 6186 case KVM_MP_STATE_INIT_RECEIVED:
6187 break;
09cec754
GN		 6188 default:
6189 r = -EINTR;
6190 break;
6191 }
6192 }
d7690175
MT		 6193 }
6194
09cec754
GN		 6195 if (r <= 0)
6196 break;
6197
6198 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6199 if (kvm_cpu_has_pending_timer(vcpu))
6200 kvm_inject_pending_timer_irqs(vcpu);
6201
851ba692 6202 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6203 r = -EINTR;
851ba692 6204 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6205 ++vcpu->stat.request_irq_exits;
6206 }
af585b92
GN		 6207
6208 kvm_check_async_pf_completion(vcpu);
6209
09cec754
GN		 6210 if (signal_pending(current)) {
6211 r = -EINTR;
851ba692 6212 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6213 ++vcpu->stat.signal_exits;
6214 }
6215 if (need_resched()) {
f656ce01 6216 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6217 cond_resched();
f656ce01 6218 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6219 }
b6c7a5dc
HB		 6220 }
6221
f656ce01 6222 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6223
6224 return r;
6225}
6226
716d51ab
GN		 6227static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6228{
6229 int r;
6230 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6231 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6232 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6233 if (r != EMULATE_DONE)
6234 return 0;
6235 return 1;
6236}
6237
6238static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6239{
6240 BUG_ON(!vcpu->arch.pio.count);
6241
6242 return complete_emulated_io(vcpu);
6243}
6244
f78146b0
AK		 6245/*
6246 * Implements the following, as a state machine:
6247 *
6248 * read:
6249 * for each fragment
87da7e66
XG		 6250 * for each mmio piece in the fragment
6251 * write gpa, len
6252 * exit
6253 * copy data
f78146b0
AK		 6254 * execute insn
6255 *
6256 * write:
6257 * for each fragment
87da7e66
XG		 6258 * for each mmio piece in the fragment
6259 * write gpa, len
6260 * copy data
6261 * exit
f78146b0 6262 */
716d51ab 6263static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6264{
6265 struct kvm_run *run = vcpu->run;
f78146b0 6266 struct kvm_mmio_fragment *frag;
87da7e66 6267 unsigned len;
5287f194 6268
716d51ab 6269 BUG_ON(!vcpu->mmio_needed);
5287f194 6270
716d51ab 6271 /* Complete previous fragment */
87da7e66
XG		 6272 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6273 len = min(8u, frag->len);
716d51ab 6274 if (!vcpu->mmio_is_write)
87da7e66
XG		 6275 memcpy(frag->data, run->mmio.data, len);
6276
6277 if (frag->len <= 8) {
6278 /* Switch to the next fragment. */
6279 frag++;
6280 vcpu->mmio_cur_fragment++;
6281 } else {
6282 /* Go forward to the next mmio piece. */
6283 frag->data += len;
6284 frag->gpa += len;
6285 frag->len -= len;
6286 }
6287
a08d3b3b 6288 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6289 vcpu->mmio_needed = 0;
0912c977
PB		 6290
6291 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6292 if (vcpu->mmio_is_write)
716d51ab
GN		 6293 return 1;
6294 vcpu->mmio_read_completed = 1;
6295 return complete_emulated_io(vcpu);
6296 }
87da7e66 6297
716d51ab
GN		 6298 run->exit_reason = KVM_EXIT_MMIO;
6299 run->mmio.phys_addr = frag->gpa;
6300 if (vcpu->mmio_is_write)
87da7e66
XG		 6301 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6302 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6303 run->mmio.is_write = vcpu->mmio_is_write;
6304 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6305 return 0;
5287f194
AK		 6306}
6307
716d51ab 6308
b6c7a5dc
HB		 6309int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6310{
6311 int r;
6312 sigset_t sigsaved;
6313
e5c30142
AK		 6314 if (!tsk_used_math(current) && init_fpu(current))
6315 return -ENOMEM;
6316
ac9f6dc0
AK		 6317 if (vcpu->sigset_active)
6318 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6319
a4535290 6320 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6321 kvm_vcpu_block(vcpu);
66450a21 6322 kvm_apic_accept_events(vcpu);
d7690175 6323 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6324 r = -EAGAIN;
6325 goto out;
b6c7a5dc
HB		 6326 }
6327
b6c7a5dc 6328 /* re-sync apic's tpr */
eea1cff9
AP		 6329 if (!irqchip_in_kernel(vcpu->kvm)) {
6330 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6331 r = -EINVAL;
6332 goto out;
6333 }
6334 }
b6c7a5dc 6335
716d51ab
GN		 6336 if (unlikely(vcpu->arch.complete_userspace_io)) {
6337 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6338 vcpu->arch.complete_userspace_io = NULL;
6339 r = cui(vcpu);
6340 if (r <= 0)
6341 goto out;
6342 } else
6343 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6344
851ba692 6345 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6346
6347out:
f1d86e46 6348 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6349 if (vcpu->sigset_active)
6350 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6351
b6c7a5dc
HB		 6352 return r;
6353}
6354
6355int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6356{
7ae441ea
GN		 6357 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6358 /*
6359 * We are here if userspace calls get_regs() in the middle of
6360 * instruction emulation. Registers state needs to be copied
4a969980 6361 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6362 * that usually, but some bad designed PV devices (vmware
6363 * backdoor interface) need this to work
6364 */
dd856efa 6365 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6366 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6367 }
5fdbf976
MT		 6368 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6369 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6370 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6371 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6372 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6373 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6374 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6375 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6376#ifdef CONFIG_X86_64
5fdbf976
MT		 6377 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6378 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6379 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6380 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6381 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6382 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6383 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6384 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6385#endif
6386
5fdbf976 6387 regs->rip = kvm_rip_read(vcpu);
91586a3b 6388 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6389
b6c7a5dc
HB		 6390 return 0;
6391}
6392
6393int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6394{
7ae441ea
GN		 6395 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6396 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6397
5fdbf976
MT		 6398 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6399 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6400 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6401 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6402 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6403 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6404 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6405 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6406#ifdef CONFIG_X86_64
5fdbf976
MT		 6407 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6408 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6409 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6410 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6411 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6412 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6413 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6414 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6415#endif
6416
5fdbf976 6417 kvm_rip_write(vcpu, regs->rip);
91586a3b 6418 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6419
b4f14abd
JK		 6420 vcpu->arch.exception.pending = false;
6421
3842d135
AK		 6422 kvm_make_request(KVM_REQ_EVENT, vcpu);
6423
b6c7a5dc
HB		 6424 return 0;
6425}
6426
b6c7a5dc
HB		 6427void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6428{
6429 struct kvm_segment cs;
6430
3e6e0aab 6431 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6432 *db = cs.db;
6433 *l = cs.l;
6434}
6435EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6436
6437int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6438 struct kvm_sregs *sregs)
6439{
89a27f4d 6440 struct desc_ptr dt;
b6c7a5dc 6441
3e6e0aab
GT		 6442 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6443 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6444 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6445 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6446 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6447 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6448
3e6e0aab
GT		 6449 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6450 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6451
6452 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6453 sregs->idt.limit = dt.size;
6454 sregs->idt.base = dt.address;
b6c7a5dc 6455 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6456 sregs->gdt.limit = dt.size;
6457 sregs->gdt.base = dt.address;
b6c7a5dc 6458
4d4ec087 6459 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6460 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6461 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6462 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6463 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6464 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6465 sregs->apic_base = kvm_get_apic_base(vcpu);
6466
923c61bb 6467 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6468
36752c9b 6469 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6470 set_bit(vcpu->arch.interrupt.nr,
6471 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6472
b6c7a5dc
HB		 6473 return 0;
6474}
6475
62d9f0db
MT		 6476int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6477 struct kvm_mp_state *mp_state)
6478{
66450a21 6479 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6480 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6481 vcpu->arch.pv.pv_unhalted)
6482 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6483 else
6484 mp_state->mp_state = vcpu->arch.mp_state;
6485
62d9f0db
MT		 6486 return 0;
6487}
6488
6489int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6490 struct kvm_mp_state *mp_state)
6491{
66450a21
JK		 6492 if (!kvm_vcpu_has_lapic(vcpu) &&
6493 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6494 return -EINVAL;
6495
6496 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6497 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6498 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6499 } else
6500 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6501 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6502 return 0;
6503}
6504
7f3d35fd
KW		 6505int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6506 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6507{
9d74191a 6508 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6509 int ret;
e01c2426 6510
8ec4722d 6511 init_emulate_ctxt(vcpu);
c697518a 6512
7f3d35fd 6513 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6514 has_error_code, error_code);
c697518a 6515
c697518a 6516 if (ret)
19d04437 6517 return EMULATE_FAIL;
37817f29 6518
9d74191a
TY		 6519 kvm_rip_write(vcpu, ctxt->eip);
6520 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6521 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6522 return EMULATE_DONE;
37817f29
IE		 6523}
6524EXPORT_SYMBOL_GPL(kvm_task_switch);
6525
b6c7a5dc
HB		 6526int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6527 struct kvm_sregs *sregs)
6528{
58cb628d 6529 struct msr_data apic_base_msr;
b6c7a5dc 6530 int mmu_reset_needed = 0;
63f42e02 6531 int pending_vec, max_bits, idx;
89a27f4d 6532 struct desc_ptr dt;
b6c7a5dc 6533
6d1068b3
PM		 6534 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6535 return -EINVAL;
6536
89a27f4d
GN		 6537 dt.size = sregs->idt.limit;
6538 dt.address = sregs->idt.base;
b6c7a5dc 6539 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6540 dt.size = sregs->gdt.limit;
6541 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6542 kvm_x86_ops->set_gdt(vcpu, &dt);
6543
ad312c7c 6544 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6545 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6546 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6547 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6548
2d3ad1f4 6549 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6550
f6801dff 6551 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6552 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6553 apic_base_msr.data = sregs->apic_base;
6554 apic_base_msr.host_initiated = true;
6555 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6556
4d4ec087 6557 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6558 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6559 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6560
fc78f519 6561 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6562 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6563 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6564 kvm_update_cpuid(vcpu);
63f42e02
XG		 6565
6566 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6567 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6568 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6569 mmu_reset_needed = 1;
6570 }
63f42e02 6571 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6572
6573 if (mmu_reset_needed)
6574 kvm_mmu_reset_context(vcpu);
6575
a50abc3b 6576 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6577 pending_vec = find_first_bit(
6578 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6579 if (pending_vec < max_bits) {
66fd3f7f 6580 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6581 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6582 }
6583
3e6e0aab
GT		 6584 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6585 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6586 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6587 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6588 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6589 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6590
3e6e0aab
GT		 6591 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6592 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6593
5f0269f5
ME		 6594 update_cr8_intercept(vcpu);
6595
9c3e4aab 6596 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6597 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6598 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6599 !is_protmode(vcpu))
9c3e4aab
MT		 6600 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6601
3842d135
AK		 6602 kvm_make_request(KVM_REQ_EVENT, vcpu);
6603
b6c7a5dc
HB		 6604 return 0;
6605}
6606
d0bfb940
JK		 6607int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6608 struct kvm_guest_debug *dbg)
b6c7a5dc 6609{
355be0b9 6610 unsigned long rflags;
ae675ef0 6611 int i, r;
b6c7a5dc 6612
4f926bf2
JK		 6613 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6614 r = -EBUSY;
6615 if (vcpu->arch.exception.pending)
2122ff5e 6616 goto out;
4f926bf2
JK		 6617 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6618 kvm_queue_exception(vcpu, DB_VECTOR);
6619 else
6620 kvm_queue_exception(vcpu, BP_VECTOR);
6621 }
6622
91586a3b
JK		 6623 /*
6624 * Read rflags as long as potentially injected trace flags are still
6625 * filtered out.
6626 */
6627 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6628
6629 vcpu->guest_debug = dbg->control;
6630 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6631 vcpu->guest_debug = 0;
6632
6633 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6634 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6635 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6636 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6637 } else {
6638 for (i = 0; i < KVM_NR_DB_REGS; i++)
6639 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6640 }
c8639010 6641 kvm_update_dr7(vcpu);
ae675ef0 6642
f92653ee
JK		 6643 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6644 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6645 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6646
91586a3b
JK		 6647 /*
6648 * Trigger an rflags update that will inject or remove the trace
6649 * flags.
6650 */
6651 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6652
c8639010 6653 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6654
4f926bf2 6655 r = 0;
d0bfb940 6656
2122ff5e 6657out:
b6c7a5dc
HB		 6658
6659 return r;
6660}
6661
8b006791
ZX		 6662/*
6663 * Translate a guest virtual address to a guest physical address.
6664 */
6665int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6666 struct kvm_translation *tr)
6667{
6668 unsigned long vaddr = tr->linear_address;
6669 gpa_t gpa;
f656ce01 6670 int idx;
8b006791 6671
f656ce01 6672 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6673 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6674 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6675 tr->physical_address = gpa;
6676 tr->valid = gpa != UNMAPPED_GVA;
6677 tr->writeable = 1;
6678 tr->usermode = 0;
8b006791
ZX		 6679
6680 return 0;
6681}
6682
d0752060
HB		 6683int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6684{
98918833
SY		 6685 struct i387_fxsave_struct *fxsave =
6686 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6687
d0752060
HB		 6688 memcpy(fpu->fpr, fxsave->st_space, 128);
6689 fpu->fcw = fxsave->cwd;
6690 fpu->fsw = fxsave->swd;
6691 fpu->ftwx = fxsave->twd;
6692 fpu->last_opcode = fxsave->fop;
6693 fpu->last_ip = fxsave->rip;
6694 fpu->last_dp = fxsave->rdp;
6695 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6696
d0752060
HB		 6697 return 0;
6698}
6699
6700int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6701{
98918833
SY		 6702 struct i387_fxsave_struct *fxsave =
6703 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6704
d0752060
HB		 6705 memcpy(fxsave->st_space, fpu->fpr, 128);
6706 fxsave->cwd = fpu->fcw;
6707 fxsave->swd = fpu->fsw;
6708 fxsave->twd = fpu->ftwx;
6709 fxsave->fop = fpu->last_opcode;
6710 fxsave->rip = fpu->last_ip;
6711 fxsave->rdp = fpu->last_dp;
6712 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6713
d0752060
HB		 6714 return 0;
6715}
6716
10ab25cd 6717int fx_init(struct kvm_vcpu *vcpu)
d0752060 6718{
10ab25cd
JK		 6719 int err;
6720
6721 err = fpu_alloc(&vcpu->arch.guest_fpu);
6722 if (err)
6723 return err;
6724
98918833 6725 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6726
2acf923e
DC		 6727 /*
6728 * Ensure guest xcr0 is valid for loading
6729 */
6730 vcpu->arch.xcr0 = XSTATE_FP;
6731
ad312c7c 6732 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6733
6734 return 0;
d0752060
HB		 6735}
6736EXPORT_SYMBOL_GPL(fx_init);
6737
98918833
SY		 6738static void fx_free(struct kvm_vcpu *vcpu)
6739{
6740 fpu_free(&vcpu->arch.guest_fpu);
6741}
6742
d0752060
HB		 6743void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6744{
2608d7a1 6745 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6746 return;
6747
2acf923e
DC		 6748 /*
6749 * Restore all possible states in the guest,
6750 * and assume host would use all available bits.
6751 * Guest xcr0 would be loaded later.
6752 */
6753 kvm_put_guest_xcr0(vcpu);
d0752060 6754 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6755 __kernel_fpu_begin();
98918833 6756 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6757 trace_kvm_fpu(1);
d0752060 6758}
d0752060
HB		 6759
6760void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6761{
2acf923e
DC		 6762 kvm_put_guest_xcr0(vcpu);
6763
d0752060
HB		 6764 if (!vcpu->guest_fpu_loaded)
6765 return;
6766
6767 vcpu->guest_fpu_loaded = 0;
98918833 6768 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6769 __kernel_fpu_end();
f096ed85 6770 ++vcpu->stat.fpu_reload;
a8eeb04a 6771 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6772 trace_kvm_fpu(0);
d0752060 6773}
e9b11c17
ZX		 6774
6775void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6776{
12f9a48f 6777 kvmclock_reset(vcpu);
7f1ea208 6778
f5f48ee1 6779 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6780 fx_free(vcpu);
e9b11c17
ZX		 6781 kvm_x86_ops->vcpu_free(vcpu);
6782}
6783
6784struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6785 unsigned int id)
6786{
6755bae8
ZA		 6787 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6788 printk_once(KERN_WARNING
6789 "kvm: SMP vm created on host with unstable TSC; "
6790 "guest TSC will not be reliable\n");
26e5215f
AK		 6791 return kvm_x86_ops->vcpu_create(kvm, id);
6792}
e9b11c17 6793
26e5215f
AK		 6794int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6795{
6796 int r;
e9b11c17 6797
0bed3b56 6798 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6799 r = vcpu_load(vcpu);
6800 if (r)
6801 return r;
57f252f2 6802 kvm_vcpu_reset(vcpu);
8a3c1a33 6803 kvm_mmu_setup(vcpu);
e9b11c17 6804 vcpu_put(vcpu);
e9b11c17 6805
26e5215f 6806 return r;
e9b11c17
ZX		 6807}
6808
42897d86
MT		 6809int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6810{
6811 int r;
8fe8ab46 6812 struct msr_data msr;
332967a3 6813 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6814
6815 r = vcpu_load(vcpu);
6816 if (r)
6817 return r;
8fe8ab46
WA		 6818 msr.data = 0x0;
6819 msr.index = MSR_IA32_TSC;
6820 msr.host_initiated = true;
6821 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6822 vcpu_put(vcpu);
6823
332967a3
AJ		 6824 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6825 KVMCLOCK_SYNC_PERIOD);
6826
42897d86
MT		 6827 return r;
6828}
6829
d40ccc62 6830void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6831{
9fc77441 6832 int r;
344d9588
GN		 6833 vcpu->arch.apf.msr_val = 0;
6834
9fc77441
MT		 6835 r = vcpu_load(vcpu);
6836 BUG_ON(r);
e9b11c17
ZX		 6837 kvm_mmu_unload(vcpu);
6838 vcpu_put(vcpu);
6839
98918833 6840 fx_free(vcpu);
e9b11c17
ZX		 6841 kvm_x86_ops->vcpu_free(vcpu);
6842}
6843
66450a21 6844void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6845{
7460fb4a
AK		 6846 atomic_set(&vcpu->arch.nmi_queued, 0);
6847 vcpu->arch.nmi_pending = 0;
448fa4a9 6848 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6849 kvm_clear_interrupt_queue(vcpu);
6850 kvm_clear_exception_queue(vcpu);
448fa4a9 6851
42dbaa5a
JK		 6852 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6853 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6854 kvm_update_dr6(vcpu);
42dbaa5a 6855 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6856 kvm_update_dr7(vcpu);
42dbaa5a 6857
3842d135 6858 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6859 vcpu->arch.apf.msr_val = 0;
c9aaa895 6860 vcpu->arch.st.msr_val = 0;
3842d135 6861
12f9a48f
GC		 6862 kvmclock_reset(vcpu);
6863
af585b92
GN		 6864 kvm_clear_async_pf_completion_queue(vcpu);
6865 kvm_async_pf_hash_reset(vcpu);
6866 vcpu->arch.apf.halted = false;
3842d135 6867
f5132b01
GN		 6868 kvm_pmu_reset(vcpu);
6869
66f7b72e
JS		 6870 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6871 vcpu->arch.regs_avail = ~0;
6872 vcpu->arch.regs_dirty = ~0;
6873
57f252f2 6874 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6875}
6876
66450a21
JK		 6877void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6878{
6879 struct kvm_segment cs;
6880
6881 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6882 cs.selector = vector << 8;
6883 cs.base = vector << 12;
6884 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6885 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6886}
6887
10474ae8 6888int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6889{
ca84d1a2
ZA		 6890 struct kvm *kvm;
6891 struct kvm_vcpu *vcpu;
6892 int i;
0dd6a6ed
ZA		 6893 int ret;
6894 u64 local_tsc;
6895 u64 max_tsc = 0;
6896 bool stable, backwards_tsc = false;
18863bdd
AK		 6897
6898 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6899 ret = kvm_x86_ops->hardware_enable(garbage);
6900 if (ret != 0)
6901 return ret;
6902
6903 local_tsc = native_read_tsc();
6904 stable = !check_tsc_unstable();
6905 list_for_each_entry(kvm, &vm_list, vm_list) {
6906 kvm_for_each_vcpu(i, vcpu, kvm) {
6907 if (!stable && vcpu->cpu == smp_processor_id())
6908 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6909 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6910 backwards_tsc = true;
6911 if (vcpu->arch.last_host_tsc > max_tsc)
6912 max_tsc = vcpu->arch.last_host_tsc;
6913 }
6914 }
6915 }
6916
6917 /*
6918 * Sometimes, even reliable TSCs go backwards. This happens on
6919 * platforms that reset TSC during suspend or hibernate actions, but
6920 * maintain synchronization. We must compensate. Fortunately, we can
6921 * detect that condition here, which happens early in CPU bringup,
6922 * before any KVM threads can be running. Unfortunately, we can't
6923 * bring the TSCs fully up to date with real time, as we aren't yet far
6924 * enough into CPU bringup that we know how much real time has actually
6925 * elapsed; our helper function, get_kernel_ns() will be using boot
6926 * variables that haven't been updated yet.
6927 *
6928 * So we simply find the maximum observed TSC above, then record the
6929 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6930 * the adjustment will be applied. Note that we accumulate
6931 * adjustments, in case multiple suspend cycles happen before some VCPU
6932 * gets a chance to run again. In the event that no KVM threads get a
6933 * chance to run, we will miss the entire elapsed period, as we'll have
6934 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6935 * loose cycle time. This isn't too big a deal, since the loss will be
6936 * uniform across all VCPUs (not to mention the scenario is extremely
6937 * unlikely). It is possible that a second hibernate recovery happens
6938 * much faster than a first, causing the observed TSC here to be
6939 * smaller; this would require additional padding adjustment, which is
6940 * why we set last_host_tsc to the local tsc observed here.
6941 *
6942 * N.B. - this code below runs only on platforms with reliable TSC,
6943 * as that is the only way backwards_tsc is set above. Also note
6944 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6945 * have the same delta_cyc adjustment applied if backwards_tsc
6946 * is detected. Note further, this adjustment is only done once,
6947 * as we reset last_host_tsc on all VCPUs to stop this from being
6948 * called multiple times (one for each physical CPU bringup).
6949 *
4a969980 6950 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6951 * will be compensated by the logic in vcpu_load, which sets the TSC to
6952 * catchup mode. This will catchup all VCPUs to real time, but cannot
6953 * guarantee that they stay in perfect synchronization.
6954 */
6955 if (backwards_tsc) {
6956 u64 delta_cyc = max_tsc - local_tsc;
16a96021 6957 backwards_tsc_observed = true;
0dd6a6ed
ZA		 6958 list_for_each_entry(kvm, &vm_list, vm_list) {
6959 kvm_for_each_vcpu(i, vcpu, kvm) {
6960 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6961 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6962 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6963 &vcpu->requests);
0dd6a6ed
ZA		 6964 }
6965
6966 /*
6967 * We have to disable TSC offset matching.. if you were
6968 * booting a VM while issuing an S4 host suspend....
6969 * you may have some problem. Solving this issue is
6970 * left as an exercise to the reader.
6971 */
6972 kvm->arch.last_tsc_nsec = 0;
6973 kvm->arch.last_tsc_write = 0;
6974 }
6975
6976 }
6977 return 0;
e9b11c17
ZX		 6978}
6979
6980void kvm_arch_hardware_disable(void *garbage)
6981{
6982 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6983 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6984}
6985
6986int kvm_arch_hardware_setup(void)
6987{
6988 return kvm_x86_ops->hardware_setup();
6989}
6990
6991void kvm_arch_hardware_unsetup(void)
6992{
6993 kvm_x86_ops->hardware_unsetup();
6994}
6995
6996void kvm_arch_check_processor_compat(void *rtn)
6997{
6998 kvm_x86_ops->check_processor_compatibility(rtn);
6999}
7000
3e515705
AK		 7001bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7002{
7003 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7004}
7005
54e9818f
GN		 7006struct static_key kvm_no_apic_vcpu __read_mostly;
7007
e9b11c17
ZX		 7008int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7009{
7010 struct page *page;
7011 struct kvm *kvm;
7012 int r;
7013
7014 BUG_ON(vcpu->kvm == NULL);
7015 kvm = vcpu->kvm;
7016
6aef266c 7017 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7018 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7019 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7020 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7021 else
a4535290 7022 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7023
7024 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7025 if (!page) {
7026 r = -ENOMEM;
7027 goto fail;
7028 }
ad312c7c 7029 vcpu->arch.pio_data = page_address(page);
e9b11c17 7030
cc578287 7031 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7032
e9b11c17
ZX		 7033 r = kvm_mmu_create(vcpu);
7034 if (r < 0)
7035 goto fail_free_pio_data;
7036
7037 if (irqchip_in_kernel(kvm)) {
7038 r = kvm_create_lapic(vcpu);
7039 if (r < 0)
7040 goto fail_mmu_destroy;
54e9818f
GN		 7041 } else
7042 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7043
890ca9ae
HY		 7044 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7045 GFP_KERNEL);
7046 if (!vcpu->arch.mce_banks) {
7047 r = -ENOMEM;
443c39bc 7048 goto fail_free_lapic;
890ca9ae
HY		 7049 }
7050 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7051
f1797359
WY		 7052 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7053 r = -ENOMEM;
f5f48ee1 7054 goto fail_free_mce_banks;
f1797359 7055 }
f5f48ee1 7056
66f7b72e
JS		 7057 r = fx_init(vcpu);
7058 if (r)
7059 goto fail_free_wbinvd_dirty_mask;
7060
ba904635 7061 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7062 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7063
7064 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7065 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7066
af585b92 7067 kvm_async_pf_hash_reset(vcpu);
f5132b01 7068 kvm_pmu_init(vcpu);
af585b92 7069
e9b11c17 7070 return 0;
66f7b72e
JS		 7071fail_free_wbinvd_dirty_mask:
7072 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7073fail_free_mce_banks:
7074 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7075fail_free_lapic:
7076 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7077fail_mmu_destroy:
7078 kvm_mmu_destroy(vcpu);
7079fail_free_pio_data:
ad312c7c 7080 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7081fail:
7082 return r;
7083}
7084
7085void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7086{
f656ce01
MT		 7087 int idx;
7088
f5132b01 7089 kvm_pmu_destroy(vcpu);
36cb93fd 7090 kfree(vcpu->arch.mce_banks);
e9b11c17 7091 kvm_free_lapic(vcpu);
f656ce01 7092 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7093 kvm_mmu_destroy(vcpu);
f656ce01 7094 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7095 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7096 if (!irqchip_in_kernel(vcpu->kvm))
7097 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7098}
d19a9cd2 7099
e08b9637 7100int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7101{
e08b9637
CO		 7102 if (type)
7103 return -EINVAL;
7104
f05e70ac 7105 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7106 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7107 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7108 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7109
5550af4d
SY		 7110 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7111 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7112 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7113 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7114 &kvm->arch.irq_sources_bitmap);
5550af4d 7115
038f8c11 7116 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7117 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7118 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7119
7120 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7121
7e44e449 7122 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7123 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7124
d89f5eff 7125 return 0;
d19a9cd2
ZX		 7126}
7127
7128static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7129{
9fc77441
MT		 7130 int r;
7131 r = vcpu_load(vcpu);
7132 BUG_ON(r);
d19a9cd2
ZX		 7133 kvm_mmu_unload(vcpu);
7134 vcpu_put(vcpu);
7135}
7136
7137static void kvm_free_vcpus(struct kvm *kvm)
7138{
7139 unsigned int i;
988a2cae 7140 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7141
7142 /*
7143 * Unpin any mmu pages first.
7144 */
af585b92
GN		 7145 kvm_for_each_vcpu(i, vcpu, kvm) {
7146 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7147 kvm_unload_vcpu_mmu(vcpu);
af585b92 7148 }
988a2cae
GN		 7149 kvm_for_each_vcpu(i, vcpu, kvm)
7150 kvm_arch_vcpu_free(vcpu);
7151
7152 mutex_lock(&kvm->lock);
7153 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7154 kvm->vcpus[i] = NULL;
d19a9cd2 7155
988a2cae
GN		 7156 atomic_set(&kvm->online_vcpus, 0);
7157 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7158}
7159
ad8ba2cd
SY		 7160void kvm_arch_sync_events(struct kvm *kvm)
7161{
332967a3 7162 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7163 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7164 kvm_free_all_assigned_devices(kvm);
aea924f6 7165 kvm_free_pit(kvm);
ad8ba2cd
SY		 7166}
7167
d19a9cd2
ZX		 7168void kvm_arch_destroy_vm(struct kvm *kvm)
7169{
27469d29
AH		 7170 if (current->mm == kvm->mm) {
7171 /*
7172 * Free memory regions allocated on behalf of userspace,
7173 * unless the the memory map has changed due to process exit
7174 * or fd copying.
7175 */
7176 struct kvm_userspace_memory_region mem;
7177 memset(&mem, 0, sizeof(mem));
7178 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7179 kvm_set_memory_region(kvm, &mem);
7180
7181 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7182 kvm_set_memory_region(kvm, &mem);
7183
7184 mem.slot = TSS_PRIVATE_MEMSLOT;
7185 kvm_set_memory_region(kvm, &mem);
7186 }
6eb55818 7187 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7188 kfree(kvm->arch.vpic);
7189 kfree(kvm->arch.vioapic);
d19a9cd2 7190 kvm_free_vcpus(kvm);
3d45830c
AK		 7191 if (kvm->arch.apic_access_page)
7192 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7193 if (kvm->arch.ept_identity_pagetable)
7194 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7195 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7196}
0de10343 7197
5587027c 7198void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7199 struct kvm_memory_slot *dont)
7200{
7201 int i;
7202
d89cc617
TY		 7203 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7204 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7205 kvm_kvfree(free->arch.rmap[i]);
7206 free->arch.rmap[i] = NULL;
77d11309 7207 }
d89cc617
TY		 7208 if (i == 0)
7209 continue;
7210
7211 if (!dont || free->arch.lpage_info[i - 1] !=
7212 dont->arch.lpage_info[i - 1]) {
7213 kvm_kvfree(free->arch.lpage_info[i - 1]);
7214 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7215 }
7216 }
7217}
7218
5587027c
AK		 7219int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7220 unsigned long npages)
db3fe4eb
TY		 7221{
7222 int i;
7223
d89cc617 7224 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7225 unsigned long ugfn;
7226 int lpages;
d89cc617 7227 int level = i + 1;
db3fe4eb
TY		 7228
7229 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7230 slot->base_gfn, level) + 1;
7231
d89cc617
TY		 7232 slot->arch.rmap[i] =
7233 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7234 if (!slot->arch.rmap[i])
77d11309 7235 goto out_free;
d89cc617
TY		 7236 if (i == 0)
7237 continue;
77d11309 7238
d89cc617
TY		 7239 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7240 sizeof(*slot->arch.lpage_info[i - 1]));
7241 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7242 goto out_free;
7243
7244 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7245 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7246 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7247 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7248 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7249 /*
7250 * If the gfn and userspace address are not aligned wrt each
7251 * other, or if explicitly asked to, disable large page
7252 * support for this slot
7253 */
7254 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7255 !kvm_largepages_enabled()) {
7256 unsigned long j;
7257
7258 for (j = 0; j < lpages; ++j)
d89cc617 7259 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7260 }
7261 }
7262
7263 return 0;
7264
7265out_free:
d89cc617
TY		 7266 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7267 kvm_kvfree(slot->arch.rmap[i]);
7268 slot->arch.rmap[i] = NULL;
7269 if (i == 0)
7270 continue;
7271
7272 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7273 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7274 }
7275 return -ENOMEM;
7276}
7277
e59dbe09
TY		 7278void kvm_arch_memslots_updated(struct kvm *kvm)
7279{
e6dff7d1
TY		 7280 /*
7281 * memslots->generation has been incremented.
7282 * mmio generation may have reached its maximum value.
7283 */
7284 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7285}
7286
f7784b8e
MT		 7287int kvm_arch_prepare_memory_region(struct kvm *kvm,
7288 struct kvm_memory_slot *memslot,
f7784b8e 7289 struct kvm_userspace_memory_region *mem,
7b6195a9 7290 enum kvm_mr_change change)
0de10343 7291{
7a905b14
TY		 7292 /*
7293 * Only private memory slots need to be mapped here since
7294 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7295 */
7b6195a9 7296 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7297 unsigned long userspace_addr;
604b38ac 7298
7a905b14
TY		 7299 /*
7300 * MAP_SHARED to prevent internal slot pages from being moved
7301 * by fork()/COW.
7302 */
7b6195a9 7303 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7304 PROT_READ | PROT_WRITE,
7305 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7306
7a905b14
TY		 7307 if (IS_ERR((void *)userspace_addr))
7308 return PTR_ERR((void *)userspace_addr);
604b38ac 7309
7a905b14 7310 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7311 }
7312
f7784b8e
MT		 7313 return 0;
7314}
7315
7316void kvm_arch_commit_memory_region(struct kvm *kvm,
7317 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7318 const struct kvm_memory_slot *old,
7319 enum kvm_mr_change change)
f7784b8e
MT		 7320{
7321
8482644a 7322 int nr_mmu_pages = 0;
f7784b8e 7323
8482644a 7324 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7325 int ret;
7326
8482644a
TY		 7327 ret = vm_munmap(old->userspace_addr,
7328 old->npages * PAGE_SIZE);
f7784b8e
MT		 7329 if (ret < 0)
7330 printk(KERN_WARNING
7331 "kvm_vm_ioctl_set_memory_region: "
7332 "failed to munmap memory\n");
7333 }
7334
48c0e4e9
XG		 7335 if (!kvm->arch.n_requested_mmu_pages)
7336 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7337
48c0e4e9 7338 if (nr_mmu_pages)
0de10343 7339 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7340 /*
7341 * Write protect all pages for dirty logging.
c126d94f
XG		 7342 *
7343 * All the sptes including the large sptes which point to this
7344 * slot are set to readonly. We can not create any new large
7345 * spte on this slot until the end of the logging.
7346 *
7347 * See the comments in fast_page_fault().
c972f3b1 7348 */
8482644a 7349 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7350 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7351}
1d737c8a 7352
2df72e9b 7353void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7354{
6ca18b69 7355 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7356}
7357
2df72e9b
MT		 7358void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7359 struct kvm_memory_slot *slot)
7360{
6ca18b69 7361 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7362}
7363
1d737c8a
ZX		 7364int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7365{
b6b8a145
JK		 7366 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7367 kvm_x86_ops->check_nested_events(vcpu, false);
7368
af585b92
GN		 7369 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7370 !vcpu->arch.apf.halted)
7371 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7372 || kvm_apic_has_events(vcpu)
6aef266c 7373 || vcpu->arch.pv.pv_unhalted
7460fb4a 7374 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7375 (kvm_arch_interrupt_allowed(vcpu) &&
7376 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7377}
5736199a 7378
b6d33834 7379int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7380{
b6d33834 7381 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7382}
78646121
GN		 7383
7384int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7385{
7386 return kvm_x86_ops->interrupt_allowed(vcpu);
7387}
229456fc 7388
f92653ee
JK		 7389bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7390{
7391 unsigned long current_rip = kvm_rip_read(vcpu) +
7392 get_segment_base(vcpu, VCPU_SREG_CS);
7393
7394 return current_rip == linear_rip;
7395}
7396EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7397
94fe45da
JK		 7398unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7399{
7400 unsigned long rflags;
7401
7402 rflags = kvm_x86_ops->get_rflags(vcpu);
7403 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7404 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7405 return rflags;
7406}
7407EXPORT_SYMBOL_GPL(kvm_get_rflags);
7408
7409void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7410{
7411 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7412 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7413 rflags |= X86_EFLAGS_TF;
94fe45da 7414 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7415 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7416}
7417EXPORT_SYMBOL_GPL(kvm_set_rflags);
7418
56028d08
GN		 7419void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7420{
7421 int r;
7422
fb67e14f 7423 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7424 work->wakeup_all)
56028d08
GN		 7425 return;
7426
7427 r = kvm_mmu_reload(vcpu);
7428 if (unlikely(r))
7429 return;
7430
fb67e14f
XG		 7431 if (!vcpu->arch.mmu.direct_map &&
7432 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7433 return;
7434
56028d08
GN		 7435 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7436}
7437
af585b92
GN		 7438static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7439{
7440 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7441}
7442
7443static inline u32 kvm_async_pf_next_probe(u32 key)
7444{
7445 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7446}
7447
7448static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7449{
7450 u32 key = kvm_async_pf_hash_fn(gfn);
7451
7452 while (vcpu->arch.apf.gfns[key] != ~0)
7453 key = kvm_async_pf_next_probe(key);
7454
7455 vcpu->arch.apf.gfns[key] = gfn;
7456}
7457
7458static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7459{
7460 int i;
7461 u32 key = kvm_async_pf_hash_fn(gfn);
7462
7463 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7464 (vcpu->arch.apf.gfns[key] != gfn &&
7465 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7466 key = kvm_async_pf_next_probe(key);
7467
7468 return key;
7469}
7470
7471bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7472{
7473 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7474}
7475
7476static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7477{
7478 u32 i, j, k;
7479
7480 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7481 while (true) {
7482 vcpu->arch.apf.gfns[i] = ~0;
7483 do {
7484 j = kvm_async_pf_next_probe(j);
7485 if (vcpu->arch.apf.gfns[j] == ~0)
7486 return;
7487 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7488 /*
7489 * k lies cyclically in ]i,j]
7490 * | i.k.j |
7491 * |....j i.k.| or |.k..j i...|
7492 */
7493 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7494 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7495 i = j;
7496 }
7497}
7498
7c90705b
GN		 7499static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7500{
7501
7502 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7503 sizeof(val));
7504}
7505
af585b92
GN		 7506void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7507 struct kvm_async_pf *work)
7508{
6389ee94
AK		 7509 struct x86_exception fault;
7510
7c90705b 7511 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7512 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7513
7514 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7515 (vcpu->arch.apf.send_user_only &&
7516 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7517 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7518 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7519 fault.vector = PF_VECTOR;
7520 fault.error_code_valid = true;
7521 fault.error_code = 0;
7522 fault.nested_page_fault = false;
7523 fault.address = work->arch.token;
7524 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7525 }
af585b92
GN		 7526}
7527
7528void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7529 struct kvm_async_pf *work)
7530{
6389ee94
AK		 7531 struct x86_exception fault;
7532
7c90705b 7533 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7534 if (work->wakeup_all)
7c90705b
GN		 7535 work->arch.token = ~0; /* broadcast wakeup */
7536 else
7537 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7538
7539 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7540 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7541 fault.vector = PF_VECTOR;
7542 fault.error_code_valid = true;
7543 fault.error_code = 0;
7544 fault.nested_page_fault = false;
7545 fault.address = work->arch.token;
7546 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7547 }
e6d53e3b 7548 vcpu->arch.apf.halted = false;
a4fa1635 7549 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7550}
7551
7552bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7553{
7554 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7555 return true;
7556 else
7557 return !kvm_event_needs_reinjection(vcpu) &&
7558 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7559}
7560
e0f0bbc5
AW		 7561void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7562{
7563 atomic_inc(&kvm->arch.noncoherent_dma_count);
7564}
7565EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7566
7567void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7568{
7569 atomic_dec(&kvm->arch.noncoherent_dma_count);
7570}
7571EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7572
7573bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7574{
7575 return atomic_read(&kvm->arch.noncoherent_dma_count);
7576}
7577EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7578
229456fc
MT		 7579EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7580EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7581EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7582EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7583EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7584EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7586EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git