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asmlinkage: Revert "lto: Make asmlinkage __visible"
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
97ec8c06
FW		 655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
656 return 1;
657
afcbf13f 658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 659 return 1;
660
a03490ed 661 if (is_long_mode(vcpu)) {
0f12244f
GN		 662 if (!(cr4 & X86_CR4_PAE))
663 return 1;
a2edf57f
AK		 664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
667 kvm_read_cr3(vcpu)))
0f12244f
GN		 668 return 1;
669
ad756a16
MJ		 670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671 if (!guest_cpuid_has_pcid(vcpu))
672 return 1;
673
674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
676 return 1;
677 }
678
5e1746d6 679 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 680 return 1;
a03490ed 681
ad756a16
MJ		 682 if (((cr4 ^ old_cr4) & pdptr_bits) ||
683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 684 kvm_mmu_reset_context(vcpu);
0f12244f 685
97ec8c06
FW		 686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
688
2acf923e 689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 690 kvm_update_cpuid(vcpu);
2acf923e 691
0f12244f
GN		 692 return 0;
693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 695
2390218b 696int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 697{
9f8fe504 698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 699 kvm_mmu_sync_roots(vcpu);
d835dfec 700 kvm_mmu_flush_tlb(vcpu);
0f12244f 701 return 0;
d835dfec
AK		 702 }
703
a03490ed 704 if (is_long_mode(vcpu)) {
471842ec 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 706 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
707 return 1;
708 } else
709 if (cr3 & CR3_L_MODE_RESERVED_BITS)
710 return 1;
a03490ed
CO		 711 } else {
712 if (is_pae(vcpu)) {
0f12244f
GN		 713 if (cr3 & CR3_PAE_RESERVED_BITS)
714 return 1;
ff03a073
JR		 715 if (is_paging(vcpu) &&
716 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 717 return 1;
a03490ed
CO		 718 }
719 /*
720 * We don't check reserved bits in nonpae mode, because
721 * this isn't enforced, and VMware depends on this.
722 */
723 }
724
0f12244f 725 vcpu->arch.cr3 = cr3;
aff48baa 726 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 727 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 731
eea1cff9 732int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 733{
0f12244f
GN		 734 if (cr8 & CR8_RESERVED_BITS)
735 return 1;
a03490ed
CO		 736 if (irqchip_in_kernel(vcpu->kvm))
737 kvm_lapic_set_tpr(vcpu, cr8);
738 else
ad312c7c 739 vcpu->arch.cr8 = cr8;
0f12244f
GN		 740 return 0;
741}
2d3ad1f4 742EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 743
2d3ad1f4 744unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 745{
746 if (irqchip_in_kernel(vcpu->kvm))
747 return kvm_lapic_get_cr8(vcpu);
748 else
ad312c7c 749 return vcpu->arch.cr8;
a03490ed 750}
2d3ad1f4 751EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 752
73aaf249
JK		 753static void kvm_update_dr6(struct kvm_vcpu *vcpu)
754{
755 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
756 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
757}
758
c8639010
JK		 759static void kvm_update_dr7(struct kvm_vcpu *vcpu)
760{
761 unsigned long dr7;
762
763 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
764 dr7 = vcpu->arch.guest_debug_dr7;
765 else
766 dr7 = vcpu->arch.dr7;
767 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 768 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
769 if (dr7 & DR7_BP_EN_MASK)
770 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 771}
772
338dbc97 773static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 774{
775 switch (dr) {
776 case 0 ... 3:
777 vcpu->arch.db[dr] = val;
778 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
779 vcpu->arch.eff_db[dr] = val;
780 break;
781 case 4:
338dbc97
GN		 782 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
783 return 1; /* #UD */
020df079
GN		 784 /* fall through */
785 case 6:
338dbc97
GN		 786 if (val & 0xffffffff00000000ULL)
787 return -1; /* #GP */
020df079 788 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 789 kvm_update_dr6(vcpu);
020df079
GN		 790 break;
791 case 5:
338dbc97
GN		 792 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
793 return 1; /* #UD */
020df079
GN		 794 /* fall through */
795 default: /* 7 */
338dbc97
GN		 796 if (val & 0xffffffff00000000ULL)
797 return -1; /* #GP */
020df079 798 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 799 kvm_update_dr7(vcpu);
020df079
GN		 800 break;
801 }
802
803 return 0;
804}
338dbc97
GN		 805
806int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
807{
808 int res;
809
810 res = __kvm_set_dr(vcpu, dr, val);
811 if (res > 0)
812 kvm_queue_exception(vcpu, UD_VECTOR);
813 else if (res < 0)
814 kvm_inject_gp(vcpu, 0);
815
816 return res;
817}
020df079
GN		 818EXPORT_SYMBOL_GPL(kvm_set_dr);
819
338dbc97 820static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 821{
822 switch (dr) {
823 case 0 ... 3:
824 *val = vcpu->arch.db[dr];
825 break;
826 case 4:
338dbc97 827 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 828 return 1;
020df079
GN		 829 /* fall through */
830 case 6:
73aaf249
JK		 831 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
832 *val = vcpu->arch.dr6;
833 else
834 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 835 break;
836 case 5:
338dbc97 837 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 838 return 1;
020df079
GN		 839 /* fall through */
840 default: /* 7 */
841 *val = vcpu->arch.dr7;
842 break;
843 }
844
845 return 0;
846}
338dbc97
GN		 847
848int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
849{
850 if (_kvm_get_dr(vcpu, dr, val)) {
851 kvm_queue_exception(vcpu, UD_VECTOR);
852 return 1;
853 }
854 return 0;
855}
020df079
GN		 856EXPORT_SYMBOL_GPL(kvm_get_dr);
857
022cd0e8
AK		 858bool kvm_rdpmc(struct kvm_vcpu *vcpu)
859{
860 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
861 u64 data;
862 int err;
863
864 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
865 if (err)
866 return err;
867 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
868 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
869 return err;
870}
871EXPORT_SYMBOL_GPL(kvm_rdpmc);
872
043405e1
CO		 873/*
874 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
875 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
876 *
877 * This list is modified at module load time to reflect the
e3267cbb
GC		 878 * capabilities of the host cpu. This capabilities test skips MSRs that are
879 * kvm-specific. Those are put in the beginning of the list.
043405e1 880 */
e3267cbb 881
e984097b 882#define KVM_SAVE_MSRS_BEGIN 12
043405e1 883static u32 msrs_to_save[] = {
e3267cbb 884 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 885 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 886 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 887 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 888 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 889 MSR_KVM_PV_EOI_EN,
043405e1 890 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 891 MSR_STAR,
043405e1
CO		 892#ifdef CONFIG_X86_64
893 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
894#endif
b3897a49 895 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 896 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 897};
898
899static unsigned num_msrs_to_save;
900
f1d24831 901static const u32 emulated_msrs[] = {
ba904635 902 MSR_IA32_TSC_ADJUST,
a3e06bbe 903 MSR_IA32_TSCDEADLINE,
043405e1 904 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 905 MSR_IA32_MCG_STATUS,
906 MSR_IA32_MCG_CTL,
043405e1
CO		 907};
908
384bb783 909bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 910{
b69e8cae 911 if (efer & efer_reserved_bits)
384bb783 912 return false;
15c4a640 913
1b2fd70c
AG		 914 if (efer & EFER_FFXSR) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 918 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 919 return false;
1b2fd70c
AG		 920 }
921
d8017474
AG		 922 if (efer & EFER_SVME) {
923 struct kvm_cpuid_entry2 *feat;
924
925 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 926 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 927 return false;
d8017474
AG		 928 }
929
384bb783
JK		 930 return true;
931}
932EXPORT_SYMBOL_GPL(kvm_valid_efer);
933
934static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
935{
936 u64 old_efer = vcpu->arch.efer;
937
938 if (!kvm_valid_efer(vcpu, efer))
939 return 1;
940
941 if (is_paging(vcpu)
942 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
943 return 1;
944
15c4a640 945 efer &= ~EFER_LMA;
f6801dff 946 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 947
a3d204e2
SY		 948 kvm_x86_ops->set_efer(vcpu, efer);
949
aad82703
SY		 950 /* Update reserved bits */
951 if ((efer ^ old_efer) & EFER_NX)
952 kvm_mmu_reset_context(vcpu);
953
b69e8cae 954 return 0;
15c4a640
CO		 955}
956
f2b4b7dd
JR		 957void kvm_enable_efer_bits(u64 mask)
958{
959 efer_reserved_bits &= ~mask;
960}
961EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
962
963
15c4a640
CO		 964/*
965 * Writes msr value into into the appropriate "register".
966 * Returns 0 on success, non-0 otherwise.
967 * Assumes vcpu_load() was already called.
968 */
8fe8ab46 969int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 970{
8fe8ab46 971 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 972}
973
313a3dc7
CO		 974/*
975 * Adapt set_msr() to msr_io()'s calling convention
976 */
977static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
978{
8fe8ab46
WA		 979 struct msr_data msr;
980
981 msr.data = *data;
982 msr.index = index;
983 msr.host_initiated = true;
984 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 985}
986
16e8d74d
MT		 987#ifdef CONFIG_X86_64
988struct pvclock_gtod_data {
989 seqcount_t seq;
990
991 struct { /* extract of a clocksource struct */
992 int vclock_mode;
993 cycle_t cycle_last;
994 cycle_t mask;
995 u32 mult;
996 u32 shift;
997 } clock;
998
999 /* open coded 'struct timespec' */
1000 u64 monotonic_time_snsec;
1001 time_t monotonic_time_sec;
1002};
1003
1004static struct pvclock_gtod_data pvclock_gtod_data;
1005
1006static void update_pvclock_gtod(struct timekeeper *tk)
1007{
1008 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1009
1010 write_seqcount_begin(&vdata->seq);
1011
1012 /* copy pvclock gtod data */
1013 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1014 vdata->clock.cycle_last = tk->clock->cycle_last;
1015 vdata->clock.mask = tk->clock->mask;
1016 vdata->clock.mult = tk->mult;
1017 vdata->clock.shift = tk->shift;
1018
1019 vdata->monotonic_time_sec = tk->xtime_sec
1020 + tk->wall_to_monotonic.tv_sec;
1021 vdata->monotonic_time_snsec = tk->xtime_nsec
1022 + (tk->wall_to_monotonic.tv_nsec
1023 << tk->shift);
1024 while (vdata->monotonic_time_snsec >=
1025 (((u64)NSEC_PER_SEC) << tk->shift)) {
1026 vdata->monotonic_time_snsec -=
1027 ((u64)NSEC_PER_SEC) << tk->shift;
1028 vdata->monotonic_time_sec++;
1029 }
1030
1031 write_seqcount_end(&vdata->seq);
1032}
1033#endif
1034
1035
18068523
GOC		 1036static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1037{
9ed3c444
AK		 1038 int version;
1039 int r;
50d0a0f9 1040 struct pvclock_wall_clock wc;
923de3cf 1041 struct timespec boot;
18068523
GOC		 1042
1043 if (!wall_clock)
1044 return;
1045
9ed3c444
AK		 1046 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1047 if (r)
1048 return;
1049
1050 if (version & 1)
1051 ++version; /* first time write, random junk */
1052
1053 ++version;
18068523 1054
18068523
GOC		 1055 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1056
50d0a0f9
GH		 1057 /*
1058 * The guest calculates current wall clock time by adding
34c238a1 1059 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1060 * wall clock specified here. guest system time equals host
1061 * system time for us, thus we must fill in host boot time here.
1062 */
923de3cf 1063 getboottime(&boot);
50d0a0f9 1064
4b648665
BR		 1065 if (kvm->arch.kvmclock_offset) {
1066 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1067 boot = timespec_sub(boot, ts);
1068 }
50d0a0f9
GH		 1069 wc.sec = boot.tv_sec;
1070 wc.nsec = boot.tv_nsec;
1071 wc.version = version;
18068523
GOC		 1072
1073 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1074
1075 version++;
1076 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1077}
1078
50d0a0f9
GH		 1079static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1080{
1081 uint32_t quotient, remainder;
1082
1083 /* Don't try to replace with do_div(), this one calculates
1084 * "(dividend << 32) / divisor" */
1085 __asm__ ( "divl %4"
1086 : "=a" (quotient), "=d" (remainder)
1087 : "0" (0), "1" (dividend), "r" (divisor) );
1088 return quotient;
1089}
1090
5f4e3f88
ZA		 1091static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1092 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1093{
5f4e3f88 1094 uint64_t scaled64;
50d0a0f9
GH		 1095 int32_t shift = 0;
1096 uint64_t tps64;
1097 uint32_t tps32;
1098
5f4e3f88
ZA		 1099 tps64 = base_khz * 1000LL;
1100 scaled64 = scaled_khz * 1000LL;
50933623 1101 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1102 tps64 >>= 1;
1103 shift--;
1104 }
1105
1106 tps32 = (uint32_t)tps64;
50933623
JK		 1107 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1108 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1109 scaled64 >>= 1;
1110 else
1111 tps32 <<= 1;
50d0a0f9
GH		 1112 shift++;
1113 }
1114
5f4e3f88
ZA		 1115 *pshift = shift;
1116 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1117
5f4e3f88
ZA		 1118 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1119 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1120}
1121
759379dd
ZA		 1122static inline u64 get_kernel_ns(void)
1123{
1124 struct timespec ts;
1125
759379dd
ZA		 1126 ktime_get_ts(&ts);
1127 monotonic_to_bootbased(&ts);
1128 return timespec_to_ns(&ts);
50d0a0f9
GH		 1129}
1130
d828199e 1131#ifdef CONFIG_X86_64
16e8d74d 1132static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1133#endif
16e8d74d 1134
c8076604 1135static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1136unsigned long max_tsc_khz;
c8076604 1137
cc578287 1138static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1139{
cc578287
ZA		 1140 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1141 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1142}
1143
cc578287 1144static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1145{
cc578287
ZA		 1146 u64 v = (u64)khz * (1000000 + ppm);
1147 do_div(v, 1000000);
1148 return v;
1e993611
JR		 1149}
1150
cc578287 1151static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1152{
cc578287
ZA		 1153 u32 thresh_lo, thresh_hi;
1154 int use_scaling = 0;
217fc9cf 1155
03ba32ca
MT		 1156 /* tsc_khz can be zero if TSC calibration fails */
1157 if (this_tsc_khz == 0)
1158 return;
1159
c285545f
ZA		 1160 /* Compute a scale to convert nanoseconds in TSC cycles */
1161 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1162 &vcpu->arch.virtual_tsc_shift,
1163 &vcpu->arch.virtual_tsc_mult);
1164 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1165
1166 /*
1167 * Compute the variation in TSC rate which is acceptable
1168 * within the range of tolerance and decide if the
1169 * rate being applied is within that bounds of the hardware
1170 * rate. If so, no scaling or compensation need be done.
1171 */
1172 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1173 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1174 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1175 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1176 use_scaling = 1;
1177 }
1178 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1179}
1180
1181static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1182{
e26101b1 1183 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1184 vcpu->arch.virtual_tsc_mult,
1185 vcpu->arch.virtual_tsc_shift);
e26101b1 1186 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1187 return tsc;
1188}
1189
b48aa97e
MT		 1190void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1191{
1192#ifdef CONFIG_X86_64
1193 bool vcpus_matched;
1194 bool do_request = false;
1195 struct kvm_arch *ka = &vcpu->kvm->arch;
1196 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1197
1198 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1199 atomic_read(&vcpu->kvm->online_vcpus));
1200
1201 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1202 if (!ka->use_master_clock)
1203 do_request = 1;
1204
1205 if (!vcpus_matched && ka->use_master_clock)
1206 do_request = 1;
1207
1208 if (do_request)
1209 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1210
1211 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1212 atomic_read(&vcpu->kvm->online_vcpus),
1213 ka->use_master_clock, gtod->clock.vclock_mode);
1214#endif
1215}
1216
ba904635
WA		 1217static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1218{
1219 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1220 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1221}
1222
8fe8ab46 1223void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1224{
1225 struct kvm *kvm = vcpu->kvm;
f38e098f 1226 u64 offset, ns, elapsed;
99e3e30a 1227 unsigned long flags;
02626b6a 1228 s64 usdiff;
b48aa97e 1229 bool matched;
8fe8ab46 1230 u64 data = msr->data;
99e3e30a 1231
038f8c11 1232 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1233 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1234 ns = get_kernel_ns();
f38e098f 1235 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1236
03ba32ca 1237 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1238 int faulted = 0;
1239
03ba32ca
MT		 1240 /* n.b - signed multiplication and division required */
1241 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1242#ifdef CONFIG_X86_64
03ba32ca 1243 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1244#else
03ba32ca 1245 /* do_div() only does unsigned */
8915aa27
MT		 1246 asm("1: idivl %[divisor]\n"
1247 "2: xor %%edx, %%edx\n"
1248 " movl $0, %[faulted]\n"
1249 "3:\n"
1250 ".section .fixup,\"ax\"\n"
1251 "4: movl $1, %[faulted]\n"
1252 " jmp 3b\n"
1253 ".previous\n"
1254
1255 _ASM_EXTABLE(1b, 4b)
1256
1257 : "=A"(usdiff), [faulted] "=r" (faulted)
1258 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1259
5d3cb0f6 1260#endif
03ba32ca
MT		 1261 do_div(elapsed, 1000);
1262 usdiff -= elapsed;
1263 if (usdiff < 0)
1264 usdiff = -usdiff;
8915aa27
MT		 1265
1266 /* idivl overflow => difference is larger than USEC_PER_SEC */
1267 if (faulted)
1268 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1269 } else
1270 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1271
1272 /*
5d3cb0f6
ZA		 1273 * Special case: TSC write with a small delta (1 second) of virtual
1274 * cycle time against real time is interpreted as an attempt to
1275 * synchronize the CPU.
1276 *
1277 * For a reliable TSC, we can match TSC offsets, and for an unstable
1278 * TSC, we add elapsed time in this computation. We could let the
1279 * compensation code attempt to catch up if we fall behind, but
1280 * it's better to try to match offsets from the beginning.
1281 */
02626b6a 1282 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1283 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1284 if (!check_tsc_unstable()) {
e26101b1 1285 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1286 pr_debug("kvm: matched tsc offset for %llu\n", data);
1287 } else {
857e4099 1288 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1289 data += delta;
1290 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1291 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1292 }
b48aa97e 1293 matched = true;
e26101b1
ZA		 1294 } else {
1295 /*
1296 * We split periods of matched TSC writes into generations.
1297 * For each generation, we track the original measured
1298 * nanosecond time, offset, and write, so if TSCs are in
1299 * sync, we can match exact offset, and if not, we can match
4a969980 1300 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1301 *
1302 * These values are tracked in kvm->arch.cur_xxx variables.
1303 */
1304 kvm->arch.cur_tsc_generation++;
1305 kvm->arch.cur_tsc_nsec = ns;
1306 kvm->arch.cur_tsc_write = data;
1307 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1308 matched = false;
e26101b1
ZA		 1309 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1310 kvm->arch.cur_tsc_generation, data);
f38e098f 1311 }
e26101b1
ZA		 1312
1313 /*
1314 * We also track th most recent recorded KHZ, write and time to
1315 * allow the matching interval to be extended at each write.
1316 */
f38e098f
ZA		 1317 kvm->arch.last_tsc_nsec = ns;
1318 kvm->arch.last_tsc_write = data;
5d3cb0f6 1319 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1320
b183aa58 1321 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1322
1323 /* Keep track of which generation this VCPU has synchronized to */
1324 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1325 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1326 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1327
ba904635
WA		 1328 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1329 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1330 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1331 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1332
1333 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1334 if (matched)
1335 kvm->arch.nr_vcpus_matched_tsc++;
1336 else
1337 kvm->arch.nr_vcpus_matched_tsc = 0;
1338
1339 kvm_track_tsc_matching(vcpu);
1340 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1341}
e26101b1 1342
99e3e30a
ZA		 1343EXPORT_SYMBOL_GPL(kvm_write_tsc);
1344
d828199e
MT		 1345#ifdef CONFIG_X86_64
1346
1347static cycle_t read_tsc(void)
1348{
1349 cycle_t ret;
1350 u64 last;
1351
1352 /*
1353 * Empirically, a fence (of type that depends on the CPU)
1354 * before rdtsc is enough to ensure that rdtsc is ordered
1355 * with respect to loads. The various CPU manuals are unclear
1356 * as to whether rdtsc can be reordered with later loads,
1357 * but no one has ever seen it happen.
1358 */
1359 rdtsc_barrier();
1360 ret = (cycle_t)vget_cycles();
1361
1362 last = pvclock_gtod_data.clock.cycle_last;
1363
1364 if (likely(ret >= last))
1365 return ret;
1366
1367 /*
1368 * GCC likes to generate cmov here, but this branch is extremely
1369 * predictable (it's just a funciton of time and the likely is
1370 * very likely) and there's a data dependence, so force GCC
1371 * to generate a branch instead. I don't barrier() because
1372 * we don't actually need a barrier, and if this function
1373 * ever gets inlined it will generate worse code.
1374 */
1375 asm volatile ("");
1376 return last;
1377}
1378
1379static inline u64 vgettsc(cycle_t *cycle_now)
1380{
1381 long v;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 *cycle_now = read_tsc();
1385
1386 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1387 return v * gtod->clock.mult;
1388}
1389
1390static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1391{
1392 unsigned long seq;
1393 u64 ns;
1394 int mode;
1395 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1396
1397 ts->tv_nsec = 0;
1398 do {
1399 seq = read_seqcount_begin(&gtod->seq);
1400 mode = gtod->clock.vclock_mode;
1401 ts->tv_sec = gtod->monotonic_time_sec;
1402 ns = gtod->monotonic_time_snsec;
1403 ns += vgettsc(cycle_now);
1404 ns >>= gtod->clock.shift;
1405 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1406 timespec_add_ns(ts, ns);
1407
1408 return mode;
1409}
1410
1411/* returns true if host is using tsc clocksource */
1412static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1413{
1414 struct timespec ts;
1415
1416 /* checked again under seqlock below */
1417 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1418 return false;
1419
1420 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1421 return false;
1422
1423 monotonic_to_bootbased(&ts);
1424 *kernel_ns = timespec_to_ns(&ts);
1425
1426 return true;
1427}
1428#endif
1429
1430/*
1431 *
b48aa97e
MT		 1432 * Assuming a stable TSC across physical CPUS, and a stable TSC
1433 * across virtual CPUs, the following condition is possible.
1434 * Each numbered line represents an event visible to both
d828199e
MT		 1435 * CPUs at the next numbered event.
1436 *
1437 * "timespecX" represents host monotonic time. "tscX" represents
1438 * RDTSC value.
1439 *
1440 * VCPU0 on CPU0 | VCPU1 on CPU1
1441 *
1442 * 1. read timespec0,tsc0
1443 * 2. | timespec1 = timespec0 + N
1444 * | tsc1 = tsc0 + M
1445 * 3. transition to guest | transition to guest
1446 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1447 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1448 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1449 *
1450 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1451 *
1452 * - ret0 < ret1
1453 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1454 * ...
1455 * - 0 < N - M => M < N
1456 *
1457 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1458 * always the case (the difference between two distinct xtime instances
1459 * might be smaller then the difference between corresponding TSC reads,
1460 * when updating guest vcpus pvclock areas).
1461 *
1462 * To avoid that problem, do not allow visibility of distinct
1463 * system_timestamp/tsc_timestamp values simultaneously: use a master
1464 * copy of host monotonic time values. Update that master copy
1465 * in lockstep.
1466 *
b48aa97e 1467 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1468 *
1469 */
1470
1471static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1472{
1473#ifdef CONFIG_X86_64
1474 struct kvm_arch *ka = &kvm->arch;
1475 int vclock_mode;
b48aa97e
MT		 1476 bool host_tsc_clocksource, vcpus_matched;
1477
1478 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1479 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1480
1481 /*
1482 * If the host uses TSC clock, then passthrough TSC as stable
1483 * to the guest.
1484 */
b48aa97e 1485 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1486 &ka->master_kernel_ns,
1487 &ka->master_cycle_now);
1488
b48aa97e
MT		 1489 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1490
d828199e
MT		 1491 if (ka->use_master_clock)
1492 atomic_set(&kvm_guest_has_master_clock, 1);
1493
1494 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1495 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1496 vcpus_matched);
d828199e
MT		 1497#endif
1498}
1499
2e762ff7
MT		 1500static void kvm_gen_update_masterclock(struct kvm *kvm)
1501{
1502#ifdef CONFIG_X86_64
1503 int i;
1504 struct kvm_vcpu *vcpu;
1505 struct kvm_arch *ka = &kvm->arch;
1506
1507 spin_lock(&ka->pvclock_gtod_sync_lock);
1508 kvm_make_mclock_inprogress_request(kvm);
1509 /* no guest entries from this point */
1510 pvclock_update_vm_gtod_copy(kvm);
1511
1512 kvm_for_each_vcpu(i, vcpu, kvm)
1513 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1514
1515 /* guest entries allowed */
1516 kvm_for_each_vcpu(i, vcpu, kvm)
1517 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1518
1519 spin_unlock(&ka->pvclock_gtod_sync_lock);
1520#endif
1521}
1522
34c238a1 1523static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1524{
d828199e 1525 unsigned long flags, this_tsc_khz;
18068523 1526 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1527 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1528 s64 kernel_ns;
d828199e 1529 u64 tsc_timestamp, host_tsc;
0b79459b 1530 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1531 u8 pvclock_flags;
d828199e
MT		 1532 bool use_master_clock;
1533
1534 kernel_ns = 0;
1535 host_tsc = 0;
18068523 1536
d828199e
MT		 1537 /*
1538 * If the host uses TSC clock, then passthrough TSC as stable
1539 * to the guest.
1540 */
1541 spin_lock(&ka->pvclock_gtod_sync_lock);
1542 use_master_clock = ka->use_master_clock;
1543 if (use_master_clock) {
1544 host_tsc = ka->master_cycle_now;
1545 kernel_ns = ka->master_kernel_ns;
1546 }
1547 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1548
1549 /* Keep irq disabled to prevent changes to the clock */
1550 local_irq_save(flags);
1551 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1552 if (unlikely(this_tsc_khz == 0)) {
1553 local_irq_restore(flags);
1554 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1555 return 1;
1556 }
d828199e
MT		 1557 if (!use_master_clock) {
1558 host_tsc = native_read_tsc();
1559 kernel_ns = get_kernel_ns();
1560 }
1561
1562 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1563
c285545f
ZA		 1564 /*
1565 * We may have to catch up the TSC to match elapsed wall clock
1566 * time for two reasons, even if kvmclock is used.
1567 * 1) CPU could have been running below the maximum TSC rate
1568 * 2) Broken TSC compensation resets the base at each VCPU
1569 * entry to avoid unknown leaps of TSC even when running
1570 * again on the same CPU. This may cause apparent elapsed
1571 * time to disappear, and the guest to stand still or run
1572 * very slowly.
1573 */
1574 if (vcpu->tsc_catchup) {
1575 u64 tsc = compute_guest_tsc(v, kernel_ns);
1576 if (tsc > tsc_timestamp) {
f1e2b260 1577 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1578 tsc_timestamp = tsc;
1579 }
50d0a0f9
GH		 1580 }
1581
18068523
GOC		 1582 local_irq_restore(flags);
1583
0b79459b 1584 if (!vcpu->pv_time_enabled)
c285545f 1585 return 0;
18068523 1586
e48672fa 1587 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1588 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1589 &vcpu->hv_clock.tsc_shift,
1590 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1591 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1592 }
1593
1594 /* With all the info we got, fill in the values */
1d5f066e 1595 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1596 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1597 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1598
18068523
GOC		 1599 /*
1600 * The interface expects us to write an even number signaling that the
1601 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1602 * state, we just increase by 2 at the end.
18068523 1603 */
50d0a0f9 1604 vcpu->hv_clock.version += 2;
18068523 1605
0b79459b
AH		 1606 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1607 &guest_hv_clock, sizeof(guest_hv_clock))))
1608 return 0;
78c0337a
MT		 1609
1610 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1611 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1612
1613 if (vcpu->pvclock_set_guest_stopped_request) {
1614 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1615 vcpu->pvclock_set_guest_stopped_request = false;
1616 }
1617
d828199e
MT		 1618 /* If the host uses TSC clocksource, then it is stable */
1619 if (use_master_clock)
1620 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1621
78c0337a
MT		 1622 vcpu->hv_clock.flags = pvclock_flags;
1623
0b79459b
AH		 1624 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1625 &vcpu->hv_clock,
1626 sizeof(vcpu->hv_clock));
8cfdc000 1627 return 0;
c8076604
GH		 1628}
1629
0061d53d
MT		 1630/*
1631 * kvmclock updates which are isolated to a given vcpu, such as
1632 * vcpu->cpu migration, should not allow system_timestamp from
1633 * the rest of the vcpus to remain static. Otherwise ntp frequency
1634 * correction applies to one vcpu's system_timestamp but not
1635 * the others.
1636 *
1637 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1638 * We need to rate-limit these requests though, as they can
1639 * considerably slow guests that have a large number of vcpus.
1640 * The time for a remote vcpu to update its kvmclock is bound
1641 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1642 */
1643
7e44e449
AJ		 1644#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1645
1646static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1647{
1648 int i;
7e44e449
AJ		 1649 struct delayed_work *dwork = to_delayed_work(work);
1650 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1651 kvmclock_update_work);
1652 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1653 struct kvm_vcpu *vcpu;
1654
1655 kvm_for_each_vcpu(i, vcpu, kvm) {
1656 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1657 kvm_vcpu_kick(vcpu);
1658 }
1659}
1660
7e44e449
AJ		 1661static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1662{
1663 struct kvm *kvm = v->kvm;
1664
1665 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1666 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1667 KVMCLOCK_UPDATE_DELAY);
1668}
1669
332967a3
AJ		 1670#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1671
1672static void kvmclock_sync_fn(struct work_struct *work)
1673{
1674 struct delayed_work *dwork = to_delayed_work(work);
1675 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1676 kvmclock_sync_work);
1677 struct kvm *kvm = container_of(ka, struct kvm, arch);
1678
1679 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1680 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1681 KVMCLOCK_SYNC_PERIOD);
1682}
1683
9ba075a6
AK		 1684static bool msr_mtrr_valid(unsigned msr)
1685{
1686 switch (msr) {
1687 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1688 case MSR_MTRRfix64K_00000:
1689 case MSR_MTRRfix16K_80000:
1690 case MSR_MTRRfix16K_A0000:
1691 case MSR_MTRRfix4K_C0000:
1692 case MSR_MTRRfix4K_C8000:
1693 case MSR_MTRRfix4K_D0000:
1694 case MSR_MTRRfix4K_D8000:
1695 case MSR_MTRRfix4K_E0000:
1696 case MSR_MTRRfix4K_E8000:
1697 case MSR_MTRRfix4K_F0000:
1698 case MSR_MTRRfix4K_F8000:
1699 case MSR_MTRRdefType:
1700 case MSR_IA32_CR_PAT:
1701 return true;
1702 case 0x2f8:
1703 return true;
1704 }
1705 return false;
1706}
1707
d6289b93
MT		 1708static bool valid_pat_type(unsigned t)
1709{
1710 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1711}
1712
1713static bool valid_mtrr_type(unsigned t)
1714{
1715 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1716}
1717
1718static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1719{
1720 int i;
1721
1722 if (!msr_mtrr_valid(msr))
1723 return false;
1724
1725 if (msr == MSR_IA32_CR_PAT) {
1726 for (i = 0; i < 8; i++)
1727 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1728 return false;
1729 return true;
1730 } else if (msr == MSR_MTRRdefType) {
1731 if (data & ~0xcff)
1732 return false;
1733 return valid_mtrr_type(data & 0xff);
1734 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1735 for (i = 0; i < 8 ; i++)
1736 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1737 return false;
1738 return true;
1739 }
1740
1741 /* variable MTRRs */
1742 return valid_mtrr_type(data & 0xff);
1743}
1744
9ba075a6
AK		 1745static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1746{
0bed3b56
SY		 1747 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1748
d6289b93 1749 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1750 return 1;
1751
0bed3b56
SY		 1752 if (msr == MSR_MTRRdefType) {
1753 vcpu->arch.mtrr_state.def_type = data;
1754 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1755 } else if (msr == MSR_MTRRfix64K_00000)
1756 p[0] = data;
1757 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1758 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1759 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1760 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1761 else if (msr == MSR_IA32_CR_PAT)
1762 vcpu->arch.pat = data;
1763 else { /* Variable MTRRs */
1764 int idx, is_mtrr_mask;
1765 u64 *pt;
1766
1767 idx = (msr - 0x200) / 2;
1768 is_mtrr_mask = msr - 0x200 - 2 * idx;
1769 if (!is_mtrr_mask)
1770 pt =
1771 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1772 else
1773 pt =
1774 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1775 *pt = data;
1776 }
1777
1778 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1779 return 0;
1780}
15c4a640 1781
890ca9ae 1782static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1783{
890ca9ae
HY		 1784 u64 mcg_cap = vcpu->arch.mcg_cap;
1785 unsigned bank_num = mcg_cap & 0xff;
1786
15c4a640 1787 switch (msr) {
15c4a640 1788 case MSR_IA32_MCG_STATUS:
890ca9ae 1789 vcpu->arch.mcg_status = data;
15c4a640 1790 break;
c7ac679c 1791 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1792 if (!(mcg_cap & MCG_CTL_P))
1793 return 1;
1794 if (data != 0 && data != ~(u64)0)
1795 return -1;
1796 vcpu->arch.mcg_ctl = data;
1797 break;
1798 default:
1799 if (msr >= MSR_IA32_MC0_CTL &&
1800 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1801 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1802 /* only 0 or all 1s can be written to IA32_MCi_CTL
1803 * some Linux kernels though clear bit 10 in bank 4 to
1804 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1805 * this to avoid an uncatched #GP in the guest
1806 */
890ca9ae 1807 if ((offset & 0x3) == 0 &&
114be429 1808 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1809 return -1;
1810 vcpu->arch.mce_banks[offset] = data;
1811 break;
1812 }
1813 return 1;
1814 }
1815 return 0;
1816}
1817
ffde22ac
ES		 1818static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1819{
1820 struct kvm *kvm = vcpu->kvm;
1821 int lm = is_long_mode(vcpu);
1822 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1823 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1824 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1825 : kvm->arch.xen_hvm_config.blob_size_32;
1826 u32 page_num = data & ~PAGE_MASK;
1827 u64 page_addr = data & PAGE_MASK;
1828 u8 *page;
1829 int r;
1830
1831 r = -E2BIG;
1832 if (page_num >= blob_size)
1833 goto out;
1834 r = -ENOMEM;
ff5c2c03
SL		 1835 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1836 if (IS_ERR(page)) {
1837 r = PTR_ERR(page);
ffde22ac 1838 goto out;
ff5c2c03 1839 }
ffde22ac
ES		 1840 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1841 goto out_free;
1842 r = 0;
1843out_free:
1844 kfree(page);
1845out:
1846 return r;
1847}
1848
55cd8e5a
GN		 1849static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1850{
1851 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1852}
1853
1854static bool kvm_hv_msr_partition_wide(u32 msr)
1855{
1856 bool r = false;
1857 switch (msr) {
1858 case HV_X64_MSR_GUEST_OS_ID:
1859 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1860 case HV_X64_MSR_REFERENCE_TSC:
1861 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1862 r = true;
1863 break;
1864 }
1865
1866 return r;
1867}
1868
1869static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1870{
1871 struct kvm *kvm = vcpu->kvm;
1872
1873 switch (msr) {
1874 case HV_X64_MSR_GUEST_OS_ID:
1875 kvm->arch.hv_guest_os_id = data;
1876 /* setting guest os id to zero disables hypercall page */
1877 if (!kvm->arch.hv_guest_os_id)
1878 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1879 break;
1880 case HV_X64_MSR_HYPERCALL: {
1881 u64 gfn;
1882 unsigned long addr;
1883 u8 instructions[4];
1884
1885 /* if guest os id is not set hypercall should remain disabled */
1886 if (!kvm->arch.hv_guest_os_id)
1887 break;
1888 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1889 kvm->arch.hv_hypercall = data;
1890 break;
1891 }
1892 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1893 addr = gfn_to_hva(kvm, gfn);
1894 if (kvm_is_error_hva(addr))
1895 return 1;
1896 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1897 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1898 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1899 return 1;
1900 kvm->arch.hv_hypercall = data;
b94b64c9 1901 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1902 break;
1903 }
e984097b
VR		 1904 case HV_X64_MSR_REFERENCE_TSC: {
1905 u64 gfn;
1906 HV_REFERENCE_TSC_PAGE tsc_ref;
1907 memset(&tsc_ref, 0, sizeof(tsc_ref));
1908 kvm->arch.hv_tsc_page = data;
1909 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1910 break;
1911 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1912 if (kvm_write_guest(kvm, data,
1913 &tsc_ref, sizeof(tsc_ref)))
1914 return 1;
1915 mark_page_dirty(kvm, gfn);
1916 break;
1917 }
55cd8e5a 1918 default:
a737f256
CD		 1919 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1920 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1921 return 1;
1922 }
1923 return 0;
1924}
1925
1926static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1927{
10388a07
GN		 1928 switch (msr) {
1929 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1930 u64 gfn;
10388a07 1931 unsigned long addr;
55cd8e5a 1932
10388a07
GN		 1933 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1934 vcpu->arch.hv_vapic = data;
1935 break;
1936 }
b3af1e88
VR		 1937 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1938 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1939 if (kvm_is_error_hva(addr))
1940 return 1;
8b0cedff 1941 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1942 return 1;
1943 vcpu->arch.hv_vapic = data;
b3af1e88 1944 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1945 break;
1946 }
1947 case HV_X64_MSR_EOI:
1948 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1949 case HV_X64_MSR_ICR:
1950 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1951 case HV_X64_MSR_TPR:
1952 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1953 default:
a737f256
CD		 1954 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1955 "data 0x%llx\n", msr, data);
10388a07
GN		 1956 return 1;
1957 }
1958
1959 return 0;
55cd8e5a
GN		 1960}
1961
344d9588
GN		 1962static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1963{
1964 gpa_t gpa = data & ~0x3f;
1965
4a969980 1966 /* Bits 2:5 are reserved, Should be zero */
6adba527 1967 if (data & 0x3c)
344d9588
GN		 1968 return 1;
1969
1970 vcpu->arch.apf.msr_val = data;
1971
1972 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1973 kvm_clear_async_pf_completion_queue(vcpu);
1974 kvm_async_pf_hash_reset(vcpu);
1975 return 0;
1976 }
1977
8f964525
AH		 1978 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1979 sizeof(u32)))
344d9588
GN		 1980 return 1;
1981
6adba527 1982 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1983 kvm_async_pf_wakeup_all(vcpu);
1984 return 0;
1985}
1986
12f9a48f
GC		 1987static void kvmclock_reset(struct kvm_vcpu *vcpu)
1988{
0b79459b 1989 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1990}
1991
c9aaa895
GC		 1992static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1993{
1994 u64 delta;
1995
1996 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1997 return;
1998
1999 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2000 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2001 vcpu->arch.st.accum_steal = delta;
2002}
2003
2004static void record_steal_time(struct kvm_vcpu *vcpu)
2005{
2006 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2007 return;
2008
2009 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2010 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2011 return;
2012
2013 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2014 vcpu->arch.st.steal.version += 2;
2015 vcpu->arch.st.accum_steal = 0;
2016
2017 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2018 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2019}
2020
8fe8ab46 2021int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2022{
5753785f 2023 bool pr = false;
8fe8ab46
WA		 2024 u32 msr = msr_info->index;
2025 u64 data = msr_info->data;
5753785f 2026
15c4a640 2027 switch (msr) {
2e32b719
BP		 2028 case MSR_AMD64_NB_CFG:
2029 case MSR_IA32_UCODE_REV:
2030 case MSR_IA32_UCODE_WRITE:
2031 case MSR_VM_HSAVE_PA:
2032 case MSR_AMD64_PATCH_LOADER:
2033 case MSR_AMD64_BU_CFG2:
2034 break;
2035
15c4a640 2036 case MSR_EFER:
b69e8cae 2037 return set_efer(vcpu, data);
8f1589d9
AP		 2038 case MSR_K7_HWCR:
2039 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2040 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2041 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2042 if (data != 0) {
a737f256
CD		 2043 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2044 data);
8f1589d9
AP		 2045 return 1;
2046 }
15c4a640 2047 break;
f7c6d140
AP		 2048 case MSR_FAM10H_MMIO_CONF_BASE:
2049 if (data != 0) {
a737f256
CD		 2050 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2051 "0x%llx\n", data);
f7c6d140
AP		 2052 return 1;
2053 }
15c4a640 2054 break;
b5e2fec0
AG		 2055 case MSR_IA32_DEBUGCTLMSR:
2056 if (!data) {
2057 /* We support the non-activated case already */
2058 break;
2059 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2060 /* Values other than LBR and BTF are vendor-specific,
2061 thus reserved and should throw a #GP */
2062 return 1;
2063 }
a737f256
CD		 2064 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2065 __func__, data);
b5e2fec0 2066 break;
9ba075a6
AK		 2067 case 0x200 ... 0x2ff:
2068 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2069 case MSR_IA32_APICBASE:
58cb628d 2070 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2071 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2072 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2073 case MSR_IA32_TSCDEADLINE:
2074 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2075 break;
ba904635
WA		 2076 case MSR_IA32_TSC_ADJUST:
2077 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2078 if (!msr_info->host_initiated) {
2079 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2080 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2081 }
2082 vcpu->arch.ia32_tsc_adjust_msr = data;
2083 }
2084 break;
15c4a640 2085 case MSR_IA32_MISC_ENABLE:
ad312c7c 2086 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2087 break;
11c6bffa 2088 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2089 case MSR_KVM_WALL_CLOCK:
2090 vcpu->kvm->arch.wall_clock = data;
2091 kvm_write_wall_clock(vcpu->kvm, data);
2092 break;
11c6bffa 2093 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2094 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2095 u64 gpa_offset;
12f9a48f 2096 kvmclock_reset(vcpu);
18068523
GOC		 2097
2098 vcpu->arch.time = data;
0061d53d 2099 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2100
2101 /* we verify if the enable bit is set... */
2102 if (!(data & 1))
2103 break;
2104
0b79459b 2105 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2106
0b79459b 2107 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2108 &vcpu->arch.pv_time, data & ~1ULL,
2109 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2110 vcpu->arch.pv_time_enabled = false;
2111 else
2112 vcpu->arch.pv_time_enabled = true;
32cad84f 2113
18068523
GOC		 2114 break;
2115 }
344d9588
GN		 2116 case MSR_KVM_ASYNC_PF_EN:
2117 if (kvm_pv_enable_async_pf(vcpu, data))
2118 return 1;
2119 break;
c9aaa895
GC		 2120 case MSR_KVM_STEAL_TIME:
2121
2122 if (unlikely(!sched_info_on()))
2123 return 1;
2124
2125 if (data & KVM_STEAL_RESERVED_MASK)
2126 return 1;
2127
2128 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2129 data & KVM_STEAL_VALID_BITS,
2130 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2131 return 1;
2132
2133 vcpu->arch.st.msr_val = data;
2134
2135 if (!(data & KVM_MSR_ENABLED))
2136 break;
2137
2138 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2139
2140 preempt_disable();
2141 accumulate_steal_time(vcpu);
2142 preempt_enable();
2143
2144 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2145
2146 break;
ae7a2a3f
MT		 2147 case MSR_KVM_PV_EOI_EN:
2148 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2149 return 1;
2150 break;
c9aaa895 2151
890ca9ae
HY		 2152 case MSR_IA32_MCG_CTL:
2153 case MSR_IA32_MCG_STATUS:
2154 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2155 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2156
2157 /* Performance counters are not protected by a CPUID bit,
2158 * so we should check all of them in the generic path for the sake of
2159 * cross vendor migration.
2160 * Writing a zero into the event select MSRs disables them,
2161 * which we perfectly emulate ;-). Any other value should be at least
2162 * reported, some guests depend on them.
2163 */
71db6023
AP		 2164 case MSR_K7_EVNTSEL0:
2165 case MSR_K7_EVNTSEL1:
2166 case MSR_K7_EVNTSEL2:
2167 case MSR_K7_EVNTSEL3:
2168 if (data != 0)
a737f256
CD		 2169 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2170 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2171 break;
2172 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2173 * so we ignore writes to make it happy.
2174 */
71db6023
AP		 2175 case MSR_K7_PERFCTR0:
2176 case MSR_K7_PERFCTR1:
2177 case MSR_K7_PERFCTR2:
2178 case MSR_K7_PERFCTR3:
a737f256
CD		 2179 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2180 "0x%x data 0x%llx\n", msr, data);
71db6023 2181 break;
5753785f
GN		 2182 case MSR_P6_PERFCTR0:
2183 case MSR_P6_PERFCTR1:
2184 pr = true;
2185 case MSR_P6_EVNTSEL0:
2186 case MSR_P6_EVNTSEL1:
2187 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2188 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2189
2190 if (pr || data != 0)
a737f256
CD		 2191 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2192 "0x%x data 0x%llx\n", msr, data);
5753785f 2193 break;
84e0cefa
JS		 2194 case MSR_K7_CLK_CTL:
2195 /*
2196 * Ignore all writes to this no longer documented MSR.
2197 * Writes are only relevant for old K7 processors,
2198 * all pre-dating SVM, but a recommended workaround from
4a969980 2199 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2200 * affected processor models on the command line, hence
2201 * the need to ignore the workaround.
2202 */
2203 break;
55cd8e5a
GN		 2204 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2205 if (kvm_hv_msr_partition_wide(msr)) {
2206 int r;
2207 mutex_lock(&vcpu->kvm->lock);
2208 r = set_msr_hyperv_pw(vcpu, msr, data);
2209 mutex_unlock(&vcpu->kvm->lock);
2210 return r;
2211 } else
2212 return set_msr_hyperv(vcpu, msr, data);
2213 break;
91c9c3ed 2214 case MSR_IA32_BBL_CR_CTL3:
2215 /* Drop writes to this legacy MSR -- see rdmsr
2216 * counterpart for further detail.
2217 */
a737f256 2218 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2219 break;
2b036c6b
BO		 2220 case MSR_AMD64_OSVW_ID_LENGTH:
2221 if (!guest_cpuid_has_osvw(vcpu))
2222 return 1;
2223 vcpu->arch.osvw.length = data;
2224 break;
2225 case MSR_AMD64_OSVW_STATUS:
2226 if (!guest_cpuid_has_osvw(vcpu))
2227 return 1;
2228 vcpu->arch.osvw.status = data;
2229 break;
15c4a640 2230 default:
ffde22ac
ES		 2231 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2232 return xen_hvm_config(vcpu, data);
f5132b01 2233 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2234 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2235 if (!ignore_msrs) {
a737f256
CD		 2236 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2237 msr, data);
ed85c068
AP		 2238 return 1;
2239 } else {
a737f256
CD		 2240 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2241 msr, data);
ed85c068
AP		 2242 break;
2243 }
15c4a640
CO		 2244 }
2245 return 0;
2246}
2247EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2248
2249
2250/*
2251 * Reads an msr value (of 'msr_index') into 'pdata'.
2252 * Returns 0 on success, non-0 otherwise.
2253 * Assumes vcpu_load() was already called.
2254 */
2255int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2256{
2257 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2258}
2259
9ba075a6
AK		 2260static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2261{
0bed3b56
SY		 2262 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2263
9ba075a6
AK		 2264 if (!msr_mtrr_valid(msr))
2265 return 1;
2266
0bed3b56
SY		 2267 if (msr == MSR_MTRRdefType)
2268 *pdata = vcpu->arch.mtrr_state.def_type +
2269 (vcpu->arch.mtrr_state.enabled << 10);
2270 else if (msr == MSR_MTRRfix64K_00000)
2271 *pdata = p[0];
2272 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2273 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2274 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2275 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2276 else if (msr == MSR_IA32_CR_PAT)
2277 *pdata = vcpu->arch.pat;
2278 else { /* Variable MTRRs */
2279 int idx, is_mtrr_mask;
2280 u64 *pt;
2281
2282 idx = (msr - 0x200) / 2;
2283 is_mtrr_mask = msr - 0x200 - 2 * idx;
2284 if (!is_mtrr_mask)
2285 pt =
2286 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2287 else
2288 pt =
2289 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2290 *pdata = *pt;
2291 }
2292
9ba075a6
AK		 2293 return 0;
2294}
2295
890ca9ae 2296static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2297{
2298 u64 data;
890ca9ae
HY		 2299 u64 mcg_cap = vcpu->arch.mcg_cap;
2300 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2301
2302 switch (msr) {
15c4a640
CO		 2303 case MSR_IA32_P5_MC_ADDR:
2304 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2305 data = 0;
2306 break;
15c4a640 2307 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2308 data = vcpu->arch.mcg_cap;
2309 break;
c7ac679c 2310 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2311 if (!(mcg_cap & MCG_CTL_P))
2312 return 1;
2313 data = vcpu->arch.mcg_ctl;
2314 break;
2315 case MSR_IA32_MCG_STATUS:
2316 data = vcpu->arch.mcg_status;
2317 break;
2318 default:
2319 if (msr >= MSR_IA32_MC0_CTL &&
2320 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2321 u32 offset = msr - MSR_IA32_MC0_CTL;
2322 data = vcpu->arch.mce_banks[offset];
2323 break;
2324 }
2325 return 1;
2326 }
2327 *pdata = data;
2328 return 0;
2329}
2330
55cd8e5a
GN		 2331static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2332{
2333 u64 data = 0;
2334 struct kvm *kvm = vcpu->kvm;
2335
2336 switch (msr) {
2337 case HV_X64_MSR_GUEST_OS_ID:
2338 data = kvm->arch.hv_guest_os_id;
2339 break;
2340 case HV_X64_MSR_HYPERCALL:
2341 data = kvm->arch.hv_hypercall;
2342 break;
e984097b
VR		 2343 case HV_X64_MSR_TIME_REF_COUNT: {
2344 data =
2345 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2346 break;
2347 }
2348 case HV_X64_MSR_REFERENCE_TSC:
2349 data = kvm->arch.hv_tsc_page;
2350 break;
55cd8e5a 2351 default:
a737f256 2352 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2353 return 1;
2354 }
2355
2356 *pdata = data;
2357 return 0;
2358}
2359
2360static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2361{
2362 u64 data = 0;
2363
2364 switch (msr) {
2365 case HV_X64_MSR_VP_INDEX: {
2366 int r;
2367 struct kvm_vcpu *v;
684851a1
TY		 2368 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2369 if (v == vcpu) {
55cd8e5a 2370 data = r;
684851a1
TY		 2371 break;
2372 }
2373 }
55cd8e5a
GN		 2374 break;
2375 }
10388a07
GN		 2376 case HV_X64_MSR_EOI:
2377 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2378 case HV_X64_MSR_ICR:
2379 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2380 case HV_X64_MSR_TPR:
2381 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2382 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2383 data = vcpu->arch.hv_vapic;
2384 break;
55cd8e5a 2385 default:
a737f256 2386 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2387 return 1;
2388 }
2389 *pdata = data;
2390 return 0;
2391}
2392
890ca9ae
HY		 2393int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2394{
2395 u64 data;
2396
2397 switch (msr) {
890ca9ae 2398 case MSR_IA32_PLATFORM_ID:
15c4a640 2399 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2400 case MSR_IA32_DEBUGCTLMSR:
2401 case MSR_IA32_LASTBRANCHFROMIP:
2402 case MSR_IA32_LASTBRANCHTOIP:
2403 case MSR_IA32_LASTINTFROMIP:
2404 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2405 case MSR_K8_SYSCFG:
2406 case MSR_K7_HWCR:
61a6bd67 2407 case MSR_VM_HSAVE_PA:
9e699624 2408 case MSR_K7_EVNTSEL0:
1f3ee616 2409 case MSR_K7_PERFCTR0:
1fdbd48c 2410 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2411 case MSR_AMD64_NB_CFG:
f7c6d140 2412 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2413 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2414 data = 0;
2415 break;
5753785f
GN		 2416 case MSR_P6_PERFCTR0:
2417 case MSR_P6_PERFCTR1:
2418 case MSR_P6_EVNTSEL0:
2419 case MSR_P6_EVNTSEL1:
2420 if (kvm_pmu_msr(vcpu, msr))
2421 return kvm_pmu_get_msr(vcpu, msr, pdata);
2422 data = 0;
2423 break;
742bc670
MT		 2424 case MSR_IA32_UCODE_REV:
2425 data = 0x100000000ULL;
2426 break;
9ba075a6
AK		 2427 case MSR_MTRRcap:
2428 data = 0x500 | KVM_NR_VAR_MTRR;
2429 break;
2430 case 0x200 ... 0x2ff:
2431 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2432 case 0xcd: /* fsb frequency */
2433 data = 3;
2434 break;
7b914098
JS		 2435 /*
2436 * MSR_EBC_FREQUENCY_ID
2437 * Conservative value valid for even the basic CPU models.
2438 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2439 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2440 * and 266MHz for model 3, or 4. Set Core Clock
2441 * Frequency to System Bus Frequency Ratio to 1 (bits
2442 * 31:24) even though these are only valid for CPU
2443 * models > 2, however guests may end up dividing or
2444 * multiplying by zero otherwise.
2445 */
2446 case MSR_EBC_FREQUENCY_ID:
2447 data = 1 << 24;
2448 break;
15c4a640
CO		 2449 case MSR_IA32_APICBASE:
2450 data = kvm_get_apic_base(vcpu);
2451 break;
0105d1a5
GN		 2452 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2453 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2454 break;
a3e06bbe
LJ		 2455 case MSR_IA32_TSCDEADLINE:
2456 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2457 break;
ba904635
WA		 2458 case MSR_IA32_TSC_ADJUST:
2459 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2460 break;
15c4a640 2461 case MSR_IA32_MISC_ENABLE:
ad312c7c 2462 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2463 break;
847f0ad8
AG		 2464 case MSR_IA32_PERF_STATUS:
2465 /* TSC increment by tick */
2466 data = 1000ULL;
2467 /* CPU multiplier */
2468 data |= (((uint64_t)4ULL) << 40);
2469 break;
15c4a640 2470 case MSR_EFER:
f6801dff 2471 data = vcpu->arch.efer;
15c4a640 2472 break;
18068523 2473 case MSR_KVM_WALL_CLOCK:
11c6bffa 2474 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2475 data = vcpu->kvm->arch.wall_clock;
2476 break;
2477 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2478 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2479 data = vcpu->arch.time;
2480 break;
344d9588
GN		 2481 case MSR_KVM_ASYNC_PF_EN:
2482 data = vcpu->arch.apf.msr_val;
2483 break;
c9aaa895
GC		 2484 case MSR_KVM_STEAL_TIME:
2485 data = vcpu->arch.st.msr_val;
2486 break;
1d92128f
MT		 2487 case MSR_KVM_PV_EOI_EN:
2488 data = vcpu->arch.pv_eoi.msr_val;
2489 break;
890ca9ae
HY		 2490 case MSR_IA32_P5_MC_ADDR:
2491 case MSR_IA32_P5_MC_TYPE:
2492 case MSR_IA32_MCG_CAP:
2493 case MSR_IA32_MCG_CTL:
2494 case MSR_IA32_MCG_STATUS:
2495 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2496 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2497 case MSR_K7_CLK_CTL:
2498 /*
2499 * Provide expected ramp-up count for K7. All other
2500 * are set to zero, indicating minimum divisors for
2501 * every field.
2502 *
2503 * This prevents guest kernels on AMD host with CPU
2504 * type 6, model 8 and higher from exploding due to
2505 * the rdmsr failing.
2506 */
2507 data = 0x20000000;
2508 break;
55cd8e5a
GN		 2509 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2510 if (kvm_hv_msr_partition_wide(msr)) {
2511 int r;
2512 mutex_lock(&vcpu->kvm->lock);
2513 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2514 mutex_unlock(&vcpu->kvm->lock);
2515 return r;
2516 } else
2517 return get_msr_hyperv(vcpu, msr, pdata);
2518 break;
91c9c3ed 2519 case MSR_IA32_BBL_CR_CTL3:
2520 /* This legacy MSR exists but isn't fully documented in current
2521 * silicon. It is however accessed by winxp in very narrow
2522 * scenarios where it sets bit #19, itself documented as
2523 * a "reserved" bit. Best effort attempt to source coherent
2524 * read data here should the balance of the register be
2525 * interpreted by the guest:
2526 *
2527 * L2 cache control register 3: 64GB range, 256KB size,
2528 * enabled, latency 0x1, configured
2529 */
2530 data = 0xbe702111;
2531 break;
2b036c6b
BO		 2532 case MSR_AMD64_OSVW_ID_LENGTH:
2533 if (!guest_cpuid_has_osvw(vcpu))
2534 return 1;
2535 data = vcpu->arch.osvw.length;
2536 break;
2537 case MSR_AMD64_OSVW_STATUS:
2538 if (!guest_cpuid_has_osvw(vcpu))
2539 return 1;
2540 data = vcpu->arch.osvw.status;
2541 break;
15c4a640 2542 default:
f5132b01
GN		 2543 if (kvm_pmu_msr(vcpu, msr))
2544 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2545 if (!ignore_msrs) {
a737f256 2546 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2547 return 1;
2548 } else {
a737f256 2549 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2550 data = 0;
2551 }
2552 break;
15c4a640
CO		 2553 }
2554 *pdata = data;
2555 return 0;
2556}
2557EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2558
313a3dc7
CO		 2559/*
2560 * Read or write a bunch of msrs. All parameters are kernel addresses.
2561 *
2562 * @return number of msrs set successfully.
2563 */
2564static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2565 struct kvm_msr_entry *entries,
2566 int (*do_msr)(struct kvm_vcpu *vcpu,
2567 unsigned index, u64 *data))
2568{
f656ce01 2569 int i, idx;
313a3dc7 2570
f656ce01 2571 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2572 for (i = 0; i < msrs->nmsrs; ++i)
2573 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2574 break;
f656ce01 2575 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2576
313a3dc7
CO		 2577 return i;
2578}
2579
2580/*
2581 * Read or write a bunch of msrs. Parameters are user addresses.
2582 *
2583 * @return number of msrs set successfully.
2584 */
2585static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2586 int (*do_msr)(struct kvm_vcpu *vcpu,
2587 unsigned index, u64 *data),
2588 int writeback)
2589{
2590 struct kvm_msrs msrs;
2591 struct kvm_msr_entry *entries;
2592 int r, n;
2593 unsigned size;
2594
2595 r = -EFAULT;
2596 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2597 goto out;
2598
2599 r = -E2BIG;
2600 if (msrs.nmsrs >= MAX_IO_MSRS)
2601 goto out;
2602
313a3dc7 2603 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2604 entries = memdup_user(user_msrs->entries, size);
2605 if (IS_ERR(entries)) {
2606 r = PTR_ERR(entries);
313a3dc7 2607 goto out;
ff5c2c03 2608 }
313a3dc7
CO		 2609
2610 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2611 if (r < 0)
2612 goto out_free;
2613
2614 r = -EFAULT;
2615 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2616 goto out_free;
2617
2618 r = n;
2619
2620out_free:
7a73c028 2621 kfree(entries);
313a3dc7
CO		 2622out:
2623 return r;
2624}
2625
018d00d2
ZX		 2626int kvm_dev_ioctl_check_extension(long ext)
2627{
2628 int r;
2629
2630 switch (ext) {
2631 case KVM_CAP_IRQCHIP:
2632 case KVM_CAP_HLT:
2633 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2634 case KVM_CAP_SET_TSS_ADDR:
07716717 2635 case KVM_CAP_EXT_CPUID:
9c15bb1d 2636 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2637 case KVM_CAP_CLOCKSOURCE:
7837699f 2638 case KVM_CAP_PIT:
a28e4f5a 2639 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2640 case KVM_CAP_MP_STATE:
ed848624 2641 case KVM_CAP_SYNC_MMU:
a355c85c 2642 case KVM_CAP_USER_NMI:
52d939a0 2643 case KVM_CAP_REINJECT_CONTROL:
4925663a 2644 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2645 case KVM_CAP_IRQFD:
d34e6b17 2646 case KVM_CAP_IOEVENTFD:
c5ff41ce 2647 case KVM_CAP_PIT2:
e9f42757 2648 case KVM_CAP_PIT_STATE2:
b927a3ce 2649 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2650 case KVM_CAP_XEN_HVM:
afbcf7ab 2651 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2652 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2653 case KVM_CAP_HYPERV:
10388a07 2654 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2655 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2656 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2657 case KVM_CAP_DEBUGREGS:
d2be1651 2658 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2659 case KVM_CAP_XSAVE:
344d9588 2660 case KVM_CAP_ASYNC_PF:
92a1f12d 2661 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2662 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2663 case KVM_CAP_READONLY_MEM:
5f66b620 2664 case KVM_CAP_HYPERV_TIME:
100943c5 2665 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2666#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2667 case KVM_CAP_ASSIGN_DEV_IRQ:
2668 case KVM_CAP_PCI_2_3:
2669#endif
018d00d2
ZX		 2670 r = 1;
2671 break;
542472b5
LV		 2672 case KVM_CAP_COALESCED_MMIO:
2673 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2674 break;
774ead3a
AK		 2675 case KVM_CAP_VAPIC:
2676 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2677 break;
f725230a 2678 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2679 r = KVM_SOFT_MAX_VCPUS;
2680 break;
2681 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2682 r = KVM_MAX_VCPUS;
2683 break;
a988b910 2684 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2685 r = KVM_USER_MEM_SLOTS;
a988b910 2686 break;
a68a6a72
MT		 2687 case KVM_CAP_PV_MMU: /* obsolete */
2688 r = 0;
2f333bcb 2689 break;
4cee4b72 2690#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2691 case KVM_CAP_IOMMU:
a1b60c1c 2692 r = iommu_present(&pci_bus_type);
62c476c7 2693 break;
4cee4b72 2694#endif
890ca9ae
HY		 2695 case KVM_CAP_MCE:
2696 r = KVM_MAX_MCE_BANKS;
2697 break;
2d5b5a66
SY		 2698 case KVM_CAP_XCRS:
2699 r = cpu_has_xsave;
2700 break;
92a1f12d
JR		 2701 case KVM_CAP_TSC_CONTROL:
2702 r = kvm_has_tsc_control;
2703 break;
4d25a066
JK		 2704 case KVM_CAP_TSC_DEADLINE_TIMER:
2705 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2706 break;
018d00d2
ZX		 2707 default:
2708 r = 0;
2709 break;
2710 }
2711 return r;
2712
2713}
2714
043405e1
CO		 2715long kvm_arch_dev_ioctl(struct file *filp,
2716 unsigned int ioctl, unsigned long arg)
2717{
2718 void __user *argp = (void __user *)arg;
2719 long r;
2720
2721 switch (ioctl) {
2722 case KVM_GET_MSR_INDEX_LIST: {
2723 struct kvm_msr_list __user *user_msr_list = argp;
2724 struct kvm_msr_list msr_list;
2725 unsigned n;
2726
2727 r = -EFAULT;
2728 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2729 goto out;
2730 n = msr_list.nmsrs;
2731 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2732 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2733 goto out;
2734 r = -E2BIG;
e125e7b6 2735 if (n < msr_list.nmsrs)
043405e1
CO		 2736 goto out;
2737 r = -EFAULT;
2738 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2739 num_msrs_to_save * sizeof(u32)))
2740 goto out;
e125e7b6 2741 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2742 &emulated_msrs,
2743 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2744 goto out;
2745 r = 0;
2746 break;
2747 }
9c15bb1d
BP		 2748 case KVM_GET_SUPPORTED_CPUID:
2749 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2750 struct kvm_cpuid2 __user *cpuid_arg = argp;
2751 struct kvm_cpuid2 cpuid;
2752
2753 r = -EFAULT;
2754 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2755 goto out;
9c15bb1d
BP		 2756
2757 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2758 ioctl);
674eea0f
AK		 2759 if (r)
2760 goto out;
2761
2762 r = -EFAULT;
2763 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2764 goto out;
2765 r = 0;
2766 break;
2767 }
890ca9ae
HY		 2768 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2769 u64 mce_cap;
2770
2771 mce_cap = KVM_MCE_CAP_SUPPORTED;
2772 r = -EFAULT;
2773 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2774 goto out;
2775 r = 0;
2776 break;
2777 }
043405e1
CO		 2778 default:
2779 r = -EINVAL;
2780 }
2781out:
2782 return r;
2783}
2784
f5f48ee1
SY		 2785static void wbinvd_ipi(void *garbage)
2786{
2787 wbinvd();
2788}
2789
2790static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2791{
e0f0bbc5 2792 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2793}
2794
313a3dc7
CO		 2795void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2796{
f5f48ee1
SY		 2797 /* Address WBINVD may be executed by guest */
2798 if (need_emulate_wbinvd(vcpu)) {
2799 if (kvm_x86_ops->has_wbinvd_exit())
2800 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2801 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2802 smp_call_function_single(vcpu->cpu,
2803 wbinvd_ipi, NULL, 1);
2804 }
2805
313a3dc7 2806 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2807
0dd6a6ed
ZA		 2808 /* Apply any externally detected TSC adjustments (due to suspend) */
2809 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2810 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2811 vcpu->arch.tsc_offset_adjustment = 0;
2812 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2813 }
8f6055cb 2814
48434c20 2815 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2816 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2817 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2818 if (tsc_delta < 0)
2819 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2820 if (check_tsc_unstable()) {
b183aa58
ZA		 2821 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2822 vcpu->arch.last_guest_tsc);
2823 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2824 vcpu->arch.tsc_catchup = 1;
c285545f 2825 }
d98d07ca
MT		 2826 /*
2827 * On a host with synchronized TSC, there is no need to update
2828 * kvmclock on vcpu->cpu migration
2829 */
2830 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2831 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2832 if (vcpu->cpu != cpu)
2833 kvm_migrate_timers(vcpu);
e48672fa 2834 vcpu->cpu = cpu;
6b7d7e76 2835 }
c9aaa895
GC		 2836
2837 accumulate_steal_time(vcpu);
2838 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2839}
2840
2841void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2842{
02daab21 2843 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2844 kvm_put_guest_fpu(vcpu);
6f526ec5 2845 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2846}
2847
313a3dc7
CO		 2848static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2849 struct kvm_lapic_state *s)
2850{
5a71785d 2851 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2852 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2853
2854 return 0;
2855}
2856
2857static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2858 struct kvm_lapic_state *s)
2859{
64eb0620 2860 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2861 update_cr8_intercept(vcpu);
313a3dc7
CO		 2862
2863 return 0;
2864}
2865
f77bc6a4
ZX		 2866static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2867 struct kvm_interrupt *irq)
2868{
02cdb50f 2869 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2870 return -EINVAL;
2871 if (irqchip_in_kernel(vcpu->kvm))
2872 return -ENXIO;
f77bc6a4 2873
66fd3f7f 2874 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2875 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2876
f77bc6a4
ZX		 2877 return 0;
2878}
2879
c4abb7c9
JK		 2880static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2881{
c4abb7c9 2882 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2883
2884 return 0;
2885}
2886
b209749f
AK		 2887static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2888 struct kvm_tpr_access_ctl *tac)
2889{
2890 if (tac->flags)
2891 return -EINVAL;
2892 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2893 return 0;
2894}
2895
890ca9ae
HY		 2896static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2897 u64 mcg_cap)
2898{
2899 int r;
2900 unsigned bank_num = mcg_cap & 0xff, bank;
2901
2902 r = -EINVAL;
a9e38c3e 2903 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2904 goto out;
2905 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2906 goto out;
2907 r = 0;
2908 vcpu->arch.mcg_cap = mcg_cap;
2909 /* Init IA32_MCG_CTL to all 1s */
2910 if (mcg_cap & MCG_CTL_P)
2911 vcpu->arch.mcg_ctl = ~(u64)0;
2912 /* Init IA32_MCi_CTL to all 1s */
2913 for (bank = 0; bank < bank_num; bank++)
2914 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2915out:
2916 return r;
2917}
2918
2919static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2920 struct kvm_x86_mce *mce)
2921{
2922 u64 mcg_cap = vcpu->arch.mcg_cap;
2923 unsigned bank_num = mcg_cap & 0xff;
2924 u64 *banks = vcpu->arch.mce_banks;
2925
2926 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2927 return -EINVAL;
2928 /*
2929 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2930 * reporting is disabled
2931 */
2932 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2933 vcpu->arch.mcg_ctl != ~(u64)0)
2934 return 0;
2935 banks += 4 * mce->bank;
2936 /*
2937 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2938 * reporting is disabled for the bank
2939 */
2940 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2941 return 0;
2942 if (mce->status & MCI_STATUS_UC) {
2943 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2944 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2945 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2946 return 0;
2947 }
2948 if (banks[1] & MCI_STATUS_VAL)
2949 mce->status |= MCI_STATUS_OVER;
2950 banks[2] = mce->addr;
2951 banks[3] = mce->misc;
2952 vcpu->arch.mcg_status = mce->mcg_status;
2953 banks[1] = mce->status;
2954 kvm_queue_exception(vcpu, MC_VECTOR);
2955 } else if (!(banks[1] & MCI_STATUS_VAL)
2956 || !(banks[1] & MCI_STATUS_UC)) {
2957 if (banks[1] & MCI_STATUS_VAL)
2958 mce->status |= MCI_STATUS_OVER;
2959 banks[2] = mce->addr;
2960 banks[3] = mce->misc;
2961 banks[1] = mce->status;
2962 } else
2963 banks[1] |= MCI_STATUS_OVER;
2964 return 0;
2965}
2966
3cfc3092
JK		 2967static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2968 struct kvm_vcpu_events *events)
2969{
7460fb4a 2970 process_nmi(vcpu);
03b82a30
JK		 2971 events->exception.injected =
2972 vcpu->arch.exception.pending &&
2973 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2974 events->exception.nr = vcpu->arch.exception.nr;
2975 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2976 events->exception.pad = 0;
3cfc3092
JK		 2977 events->exception.error_code = vcpu->arch.exception.error_code;
2978
03b82a30
JK		 2979 events->interrupt.injected =
2980 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2981 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2982 events->interrupt.soft = 0;
48005f64
JK		 2983 events->interrupt.shadow =
2984 kvm_x86_ops->get_interrupt_shadow(vcpu,
2985 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2986
2987 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2988 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2989 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2990 events->nmi.pad = 0;
3cfc3092 2991
66450a21 2992 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2993
dab4b911 2994 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2995 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2996 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2997}
2998
2999static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3000 struct kvm_vcpu_events *events)
3001{
dab4b911 3002 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3003 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3004 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3005 return -EINVAL;
3006
7460fb4a 3007 process_nmi(vcpu);
3cfc3092
JK		 3008 vcpu->arch.exception.pending = events->exception.injected;
3009 vcpu->arch.exception.nr = events->exception.nr;
3010 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3011 vcpu->arch.exception.error_code = events->exception.error_code;
3012
3013 vcpu->arch.interrupt.pending = events->interrupt.injected;
3014 vcpu->arch.interrupt.nr = events->interrupt.nr;
3015 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3016 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3017 kvm_x86_ops->set_interrupt_shadow(vcpu,
3018 events->interrupt.shadow);
3cfc3092
JK		 3019
3020 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3021 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3022 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3023 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3024
66450a21
JK		 3025 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3026 kvm_vcpu_has_lapic(vcpu))
3027 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3028
3842d135
AK		 3029 kvm_make_request(KVM_REQ_EVENT, vcpu);
3030
3cfc3092
JK		 3031 return 0;
3032}
3033
a1efbe77
JK		 3034static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3035 struct kvm_debugregs *dbgregs)
3036{
73aaf249
JK		 3037 unsigned long val;
3038
a1efbe77 3039 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3040 _kvm_get_dr(vcpu, 6, &val);
3041 dbgregs->dr6 = val;
a1efbe77
JK		 3042 dbgregs->dr7 = vcpu->arch.dr7;
3043 dbgregs->flags = 0;
97e69aa6 3044 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3045}
3046
3047static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3048 struct kvm_debugregs *dbgregs)
3049{
3050 if (dbgregs->flags)
3051 return -EINVAL;
3052
a1efbe77
JK		 3053 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3054 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3055 kvm_update_dr6(vcpu);
a1efbe77 3056 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3057 kvm_update_dr7(vcpu);
a1efbe77 3058
a1efbe77
JK		 3059 return 0;
3060}
3061
2d5b5a66
SY		 3062static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3063 struct kvm_xsave *guest_xsave)
3064{
4344ee98 3065 if (cpu_has_xsave) {
2d5b5a66
SY		 3066 memcpy(guest_xsave->region,
3067 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3068 vcpu->arch.guest_xstate_size);
3069 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3070 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3071 } else {
2d5b5a66
SY		 3072 memcpy(guest_xsave->region,
3073 &vcpu->arch.guest_fpu.state->fxsave,
3074 sizeof(struct i387_fxsave_struct));
3075 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3076 XSTATE_FPSSE;
3077 }
3078}
3079
3080static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3081 struct kvm_xsave *guest_xsave)
3082{
3083 u64 xstate_bv =
3084 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3085
d7876f1b
PB		 3086 if (cpu_has_xsave) {
3087 /*
3088 * Here we allow setting states that are not present in
3089 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3090 * with old userspace.
3091 */
4ff41732 3092 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3093 return -EINVAL;
2d5b5a66 3094 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3095 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3096 } else {
2d5b5a66
SY		 3097 if (xstate_bv & ~XSTATE_FPSSE)
3098 return -EINVAL;
3099 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3100 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3101 }
3102 return 0;
3103}
3104
3105static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3106 struct kvm_xcrs *guest_xcrs)
3107{
3108 if (!cpu_has_xsave) {
3109 guest_xcrs->nr_xcrs = 0;
3110 return;
3111 }
3112
3113 guest_xcrs->nr_xcrs = 1;
3114 guest_xcrs->flags = 0;
3115 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3116 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3117}
3118
3119static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3120 struct kvm_xcrs *guest_xcrs)
3121{
3122 int i, r = 0;
3123
3124 if (!cpu_has_xsave)
3125 return -EINVAL;
3126
3127 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3128 return -EINVAL;
3129
3130 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3131 /* Only support XCR0 currently */
c67a04cb 3132 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3133 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3134 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3135 break;
3136 }
3137 if (r)
3138 r = -EINVAL;
3139 return r;
3140}
3141
1c0b28c2
EM		 3142/*
3143 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3144 * stopped by the hypervisor. This function will be called from the host only.
3145 * EINVAL is returned when the host attempts to set the flag for a guest that
3146 * does not support pv clocks.
3147 */
3148static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3149{
0b79459b 3150 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3151 return -EINVAL;
51d59c6b 3152 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3153 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3154 return 0;
3155}
3156
313a3dc7
CO		 3157long kvm_arch_vcpu_ioctl(struct file *filp,
3158 unsigned int ioctl, unsigned long arg)
3159{
3160 struct kvm_vcpu *vcpu = filp->private_data;
3161 void __user *argp = (void __user *)arg;
3162 int r;
d1ac91d8
AK		 3163 union {
3164 struct kvm_lapic_state *lapic;
3165 struct kvm_xsave *xsave;
3166 struct kvm_xcrs *xcrs;
3167 void *buffer;
3168 } u;
3169
3170 u.buffer = NULL;
313a3dc7
CO		 3171 switch (ioctl) {
3172 case KVM_GET_LAPIC: {
2204ae3c
MT		 3173 r = -EINVAL;
3174 if (!vcpu->arch.apic)
3175 goto out;
d1ac91d8 3176 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3177
b772ff36 3178 r = -ENOMEM;
d1ac91d8 3179 if (!u.lapic)
b772ff36 3180 goto out;
d1ac91d8 3181 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3182 if (r)
3183 goto out;
3184 r = -EFAULT;
d1ac91d8 3185 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3186 goto out;
3187 r = 0;
3188 break;
3189 }
3190 case KVM_SET_LAPIC: {
2204ae3c
MT		 3191 r = -EINVAL;
3192 if (!vcpu->arch.apic)
3193 goto out;
ff5c2c03 3194 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3195 if (IS_ERR(u.lapic))
3196 return PTR_ERR(u.lapic);
ff5c2c03 3197
d1ac91d8 3198 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3199 break;
3200 }
f77bc6a4
ZX		 3201 case KVM_INTERRUPT: {
3202 struct kvm_interrupt irq;
3203
3204 r = -EFAULT;
3205 if (copy_from_user(&irq, argp, sizeof irq))
3206 goto out;
3207 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3208 break;
3209 }
c4abb7c9
JK		 3210 case KVM_NMI: {
3211 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3212 break;
3213 }
313a3dc7
CO		 3214 case KVM_SET_CPUID: {
3215 struct kvm_cpuid __user *cpuid_arg = argp;
3216 struct kvm_cpuid cpuid;
3217
3218 r = -EFAULT;
3219 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3220 goto out;
3221 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3222 break;
3223 }
07716717
DK		 3224 case KVM_SET_CPUID2: {
3225 struct kvm_cpuid2 __user *cpuid_arg = argp;
3226 struct kvm_cpuid2 cpuid;
3227
3228 r = -EFAULT;
3229 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3230 goto out;
3231 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3232 cpuid_arg->entries);
07716717
DK		 3233 break;
3234 }
3235 case KVM_GET_CPUID2: {
3236 struct kvm_cpuid2 __user *cpuid_arg = argp;
3237 struct kvm_cpuid2 cpuid;
3238
3239 r = -EFAULT;
3240 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3241 goto out;
3242 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3243 cpuid_arg->entries);
07716717
DK		 3244 if (r)
3245 goto out;
3246 r = -EFAULT;
3247 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3248 goto out;
3249 r = 0;
3250 break;
3251 }
313a3dc7
CO		 3252 case KVM_GET_MSRS:
3253 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3254 break;
3255 case KVM_SET_MSRS:
3256 r = msr_io(vcpu, argp, do_set_msr, 0);
3257 break;
b209749f
AK		 3258 case KVM_TPR_ACCESS_REPORTING: {
3259 struct kvm_tpr_access_ctl tac;
3260
3261 r = -EFAULT;
3262 if (copy_from_user(&tac, argp, sizeof tac))
3263 goto out;
3264 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3265 if (r)
3266 goto out;
3267 r = -EFAULT;
3268 if (copy_to_user(argp, &tac, sizeof tac))
3269 goto out;
3270 r = 0;
3271 break;
3272 };
b93463aa
AK		 3273 case KVM_SET_VAPIC_ADDR: {
3274 struct kvm_vapic_addr va;
3275
3276 r = -EINVAL;
3277 if (!irqchip_in_kernel(vcpu->kvm))
3278 goto out;
3279 r = -EFAULT;
3280 if (copy_from_user(&va, argp, sizeof va))
3281 goto out;
fda4e2e8 3282 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3283 break;
3284 }
890ca9ae
HY		 3285 case KVM_X86_SETUP_MCE: {
3286 u64 mcg_cap;
3287
3288 r = -EFAULT;
3289 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3290 goto out;
3291 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3292 break;
3293 }
3294 case KVM_X86_SET_MCE: {
3295 struct kvm_x86_mce mce;
3296
3297 r = -EFAULT;
3298 if (copy_from_user(&mce, argp, sizeof mce))
3299 goto out;
3300 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3301 break;
3302 }
3cfc3092
JK		 3303 case KVM_GET_VCPU_EVENTS: {
3304 struct kvm_vcpu_events events;
3305
3306 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3307
3308 r = -EFAULT;
3309 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3310 break;
3311 r = 0;
3312 break;
3313 }
3314 case KVM_SET_VCPU_EVENTS: {
3315 struct kvm_vcpu_events events;
3316
3317 r = -EFAULT;
3318 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3319 break;
3320
3321 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3322 break;
3323 }
a1efbe77
JK		 3324 case KVM_GET_DEBUGREGS: {
3325 struct kvm_debugregs dbgregs;
3326
3327 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3328
3329 r = -EFAULT;
3330 if (copy_to_user(argp, &dbgregs,
3331 sizeof(struct kvm_debugregs)))
3332 break;
3333 r = 0;
3334 break;
3335 }
3336 case KVM_SET_DEBUGREGS: {
3337 struct kvm_debugregs dbgregs;
3338
3339 r = -EFAULT;
3340 if (copy_from_user(&dbgregs, argp,
3341 sizeof(struct kvm_debugregs)))
3342 break;
3343
3344 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3345 break;
3346 }
2d5b5a66 3347 case KVM_GET_XSAVE: {
d1ac91d8 3348 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3349 r = -ENOMEM;
d1ac91d8 3350 if (!u.xsave)
2d5b5a66
SY		 3351 break;
3352
d1ac91d8 3353 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3354
3355 r = -EFAULT;
d1ac91d8 3356 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3357 break;
3358 r = 0;
3359 break;
3360 }
3361 case KVM_SET_XSAVE: {
ff5c2c03 3362 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3363 if (IS_ERR(u.xsave))
3364 return PTR_ERR(u.xsave);
2d5b5a66 3365
d1ac91d8 3366 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3367 break;
3368 }
3369 case KVM_GET_XCRS: {
d1ac91d8 3370 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3371 r = -ENOMEM;
d1ac91d8 3372 if (!u.xcrs)
2d5b5a66
SY		 3373 break;
3374
d1ac91d8 3375 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3376
3377 r = -EFAULT;
d1ac91d8 3378 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3379 sizeof(struct kvm_xcrs)))
3380 break;
3381 r = 0;
3382 break;
3383 }
3384 case KVM_SET_XCRS: {
ff5c2c03 3385 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3386 if (IS_ERR(u.xcrs))
3387 return PTR_ERR(u.xcrs);
2d5b5a66 3388
d1ac91d8 3389 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3390 break;
3391 }
92a1f12d
JR		 3392 case KVM_SET_TSC_KHZ: {
3393 u32 user_tsc_khz;
3394
3395 r = -EINVAL;
92a1f12d
JR		 3396 user_tsc_khz = (u32)arg;
3397
3398 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3399 goto out;
3400
cc578287
ZA		 3401 if (user_tsc_khz == 0)
3402 user_tsc_khz = tsc_khz;
3403
3404 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3405
3406 r = 0;
3407 goto out;
3408 }
3409 case KVM_GET_TSC_KHZ: {
cc578287 3410 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3411 goto out;
3412 }
1c0b28c2
EM		 3413 case KVM_KVMCLOCK_CTRL: {
3414 r = kvm_set_guest_paused(vcpu);
3415 goto out;
3416 }
313a3dc7
CO		 3417 default:
3418 r = -EINVAL;
3419 }
3420out:
d1ac91d8 3421 kfree(u.buffer);
313a3dc7
CO		 3422 return r;
3423}
3424
5b1c1493
CO		 3425int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3426{
3427 return VM_FAULT_SIGBUS;
3428}
3429
1fe779f8
CO		 3430static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3431{
3432 int ret;
3433
3434 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3435 return -EINVAL;
1fe779f8
CO		 3436 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3437 return ret;
3438}
3439
b927a3ce
SY		 3440static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3441 u64 ident_addr)
3442{
3443 kvm->arch.ept_identity_map_addr = ident_addr;
3444 return 0;
3445}
3446
1fe779f8
CO		 3447static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3448 u32 kvm_nr_mmu_pages)
3449{
3450 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3451 return -EINVAL;
3452
79fac95e 3453 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3454
3455 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3456 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3457
79fac95e 3458 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3459 return 0;
3460}
3461
3462static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3463{
39de71ec 3464 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3465}
3466
1fe779f8
CO		 3467static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3468{
3469 int r;
3470
3471 r = 0;
3472 switch (chip->chip_id) {
3473 case KVM_IRQCHIP_PIC_MASTER:
3474 memcpy(&chip->chip.pic,
3475 &pic_irqchip(kvm)->pics[0],
3476 sizeof(struct kvm_pic_state));
3477 break;
3478 case KVM_IRQCHIP_PIC_SLAVE:
3479 memcpy(&chip->chip.pic,
3480 &pic_irqchip(kvm)->pics[1],
3481 sizeof(struct kvm_pic_state));
3482 break;
3483 case KVM_IRQCHIP_IOAPIC:
eba0226b 3484 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3485 break;
3486 default:
3487 r = -EINVAL;
3488 break;
3489 }
3490 return r;
3491}
3492
3493static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3494{
3495 int r;
3496
3497 r = 0;
3498 switch (chip->chip_id) {
3499 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3500 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3501 memcpy(&pic_irqchip(kvm)->pics[0],
3502 &chip->chip.pic,
3503 sizeof(struct kvm_pic_state));
f4f51050 3504 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3505 break;
3506 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3507 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3508 memcpy(&pic_irqchip(kvm)->pics[1],
3509 &chip->chip.pic,
3510 sizeof(struct kvm_pic_state));
f4f51050 3511 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3512 break;
3513 case KVM_IRQCHIP_IOAPIC:
eba0226b 3514 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3515 break;
3516 default:
3517 r = -EINVAL;
3518 break;
3519 }
3520 kvm_pic_update_irq(pic_irqchip(kvm));
3521 return r;
3522}
3523
e0f63cb9
SY		 3524static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3525{
3526 int r = 0;
3527
894a9c55 3528 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3529 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3530 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3531 return r;
3532}
3533
3534static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3535{
3536 int r = 0;
3537
894a9c55 3538 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3539 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3540 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3541 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3542 return r;
3543}
3544
3545static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3546{
3547 int r = 0;
3548
3549 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3550 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3551 sizeof(ps->channels));
3552 ps->flags = kvm->arch.vpit->pit_state.flags;
3553 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3554 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3555 return r;
3556}
3557
3558static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3559{
3560 int r = 0, start = 0;
3561 u32 prev_legacy, cur_legacy;
3562 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3563 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3564 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3565 if (!prev_legacy && cur_legacy)
3566 start = 1;
3567 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3568 sizeof(kvm->arch.vpit->pit_state.channels));
3569 kvm->arch.vpit->pit_state.flags = ps->flags;
3570 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3571 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3572 return r;
3573}
3574
52d939a0
MT		 3575static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3576 struct kvm_reinject_control *control)
3577{
3578 if (!kvm->arch.vpit)
3579 return -ENXIO;
894a9c55 3580 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3581 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3582 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3583 return 0;
3584}
3585
95d4c16c 3586/**
60c34612
TY		 3587 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3588 * @kvm: kvm instance
3589 * @log: slot id and address to which we copy the log
95d4c16c 3590 *
60c34612
TY		 3591 * We need to keep it in mind that VCPU threads can write to the bitmap
3592 * concurrently. So, to avoid losing data, we keep the following order for
3593 * each bit:
95d4c16c 3594 *
60c34612
TY		 3595 * 1. Take a snapshot of the bit and clear it if needed.
3596 * 2. Write protect the corresponding page.
3597 * 3. Flush TLB's if needed.
3598 * 4. Copy the snapshot to the userspace.
95d4c16c 3599 *
60c34612
TY		 3600 * Between 2 and 3, the guest may write to the page using the remaining TLB
3601 * entry. This is not a problem because the page will be reported dirty at
3602 * step 4 using the snapshot taken before and step 3 ensures that successive
3603 * writes will be logged for the next call.
5bb064dc 3604 */
60c34612 3605int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3606{
7850ac54 3607 int r;
5bb064dc 3608 struct kvm_memory_slot *memslot;
60c34612
TY		 3609 unsigned long n, i;
3610 unsigned long *dirty_bitmap;
3611 unsigned long *dirty_bitmap_buffer;
3612 bool is_dirty = false;
5bb064dc 3613
79fac95e 3614 mutex_lock(&kvm->slots_lock);
5bb064dc 3615
b050b015 3616 r = -EINVAL;
bbacc0c1 3617 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3618 goto out;
3619
28a37544 3620 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3621
3622 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3623 r = -ENOENT;
60c34612 3624 if (!dirty_bitmap)
b050b015
MT		 3625 goto out;
3626
87bf6e7d 3627 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3628
60c34612
TY		 3629 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3630 memset(dirty_bitmap_buffer, 0, n);
b050b015 3631
60c34612 3632 spin_lock(&kvm->mmu_lock);
b050b015 3633
60c34612
TY		 3634 for (i = 0; i < n / sizeof(long); i++) {
3635 unsigned long mask;
3636 gfn_t offset;
cdfca7b3 3637
60c34612
TY		 3638 if (!dirty_bitmap[i])
3639 continue;
b050b015 3640
60c34612 3641 is_dirty = true;
914ebccd 3642
60c34612
TY		 3643 mask = xchg(&dirty_bitmap[i], 0);
3644 dirty_bitmap_buffer[i] = mask;
edde99ce 3645
60c34612
TY		 3646 offset = i * BITS_PER_LONG;
3647 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3648 }
60c34612
TY		 3649 if (is_dirty)
3650 kvm_flush_remote_tlbs(kvm);
3651
3652 spin_unlock(&kvm->mmu_lock);
3653
3654 r = -EFAULT;
3655 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3656 goto out;
b050b015 3657
5bb064dc
ZX		 3658 r = 0;
3659out:
79fac95e 3660 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3661 return r;
3662}
3663
aa2fbe6d
YZ		 3664int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3665 bool line_status)
23d43cf9
CD		 3666{
3667 if (!irqchip_in_kernel(kvm))
3668 return -ENXIO;
3669
3670 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3671 irq_event->irq, irq_event->level,
3672 line_status);
23d43cf9
CD		 3673 return 0;
3674}
3675
1fe779f8
CO		 3676long kvm_arch_vm_ioctl(struct file *filp,
3677 unsigned int ioctl, unsigned long arg)
3678{
3679 struct kvm *kvm = filp->private_data;
3680 void __user *argp = (void __user *)arg;
367e1319 3681 int r = -ENOTTY;
f0d66275
DH		 3682 /*
3683 * This union makes it completely explicit to gcc-3.x
3684 * that these two variables' stack usage should be
3685 * combined, not added together.
3686 */
3687 union {
3688 struct kvm_pit_state ps;
e9f42757 3689 struct kvm_pit_state2 ps2;
c5ff41ce 3690 struct kvm_pit_config pit_config;
f0d66275 3691 } u;
1fe779f8
CO		 3692
3693 switch (ioctl) {
3694 case KVM_SET_TSS_ADDR:
3695 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3696 break;
b927a3ce
SY		 3697 case KVM_SET_IDENTITY_MAP_ADDR: {
3698 u64 ident_addr;
3699
3700 r = -EFAULT;
3701 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3702 goto out;
3703 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3704 break;
3705 }
1fe779f8
CO		 3706 case KVM_SET_NR_MMU_PAGES:
3707 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3708 break;
3709 case KVM_GET_NR_MMU_PAGES:
3710 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3711 break;
3ddea128
MT		 3712 case KVM_CREATE_IRQCHIP: {
3713 struct kvm_pic *vpic;
3714
3715 mutex_lock(&kvm->lock);
3716 r = -EEXIST;
3717 if (kvm->arch.vpic)
3718 goto create_irqchip_unlock;
3e515705
AK		 3719 r = -EINVAL;
3720 if (atomic_read(&kvm->online_vcpus))
3721 goto create_irqchip_unlock;
1fe779f8 3722 r = -ENOMEM;
3ddea128
MT		 3723 vpic = kvm_create_pic(kvm);
3724 if (vpic) {
1fe779f8
CO		 3725 r = kvm_ioapic_init(kvm);
3726 if (r) {
175504cd 3727 mutex_lock(&kvm->slots_lock);
72bb2fcd 3728 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3729 &vpic->dev_master);
3730 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3731 &vpic->dev_slave);
3732 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3733 &vpic->dev_eclr);
175504cd 3734 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3735 kfree(vpic);
3736 goto create_irqchip_unlock;
1fe779f8
CO		 3737 }
3738 } else
3ddea128
MT		 3739 goto create_irqchip_unlock;
3740 smp_wmb();
3741 kvm->arch.vpic = vpic;
3742 smp_wmb();
399ec807
AK		 3743 r = kvm_setup_default_irq_routing(kvm);
3744 if (r) {
175504cd 3745 mutex_lock(&kvm->slots_lock);
3ddea128 3746 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3747 kvm_ioapic_destroy(kvm);
3748 kvm_destroy_pic(kvm);
3ddea128 3749 mutex_unlock(&kvm->irq_lock);
175504cd 3750 mutex_unlock(&kvm->slots_lock);
399ec807 3751 }
3ddea128
MT		 3752 create_irqchip_unlock:
3753 mutex_unlock(&kvm->lock);
1fe779f8 3754 break;
3ddea128 3755 }
7837699f 3756 case KVM_CREATE_PIT:
c5ff41ce
JK		 3757 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3758 goto create_pit;
3759 case KVM_CREATE_PIT2:
3760 r = -EFAULT;
3761 if (copy_from_user(&u.pit_config, argp,
3762 sizeof(struct kvm_pit_config)))
3763 goto out;
3764 create_pit:
79fac95e 3765 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3766 r = -EEXIST;
3767 if (kvm->arch.vpit)
3768 goto create_pit_unlock;
7837699f 3769 r = -ENOMEM;
c5ff41ce 3770 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3771 if (kvm->arch.vpit)
3772 r = 0;
269e05e4 3773 create_pit_unlock:
79fac95e 3774 mutex_unlock(&kvm->slots_lock);
7837699f 3775 break;
1fe779f8
CO		 3776 case KVM_GET_IRQCHIP: {
3777 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3778 struct kvm_irqchip *chip;
1fe779f8 3779
ff5c2c03
SL		 3780 chip = memdup_user(argp, sizeof(*chip));
3781 if (IS_ERR(chip)) {
3782 r = PTR_ERR(chip);
1fe779f8 3783 goto out;
ff5c2c03
SL		 3784 }
3785
1fe779f8
CO		 3786 r = -ENXIO;
3787 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3788 goto get_irqchip_out;
3789 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3790 if (r)
f0d66275 3791 goto get_irqchip_out;
1fe779f8 3792 r = -EFAULT;
f0d66275
DH		 3793 if (copy_to_user(argp, chip, sizeof *chip))
3794 goto get_irqchip_out;
1fe779f8 3795 r = 0;
f0d66275
DH		 3796 get_irqchip_out:
3797 kfree(chip);
1fe779f8
CO		 3798 break;
3799 }
3800 case KVM_SET_IRQCHIP: {
3801 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3802 struct kvm_irqchip *chip;
1fe779f8 3803
ff5c2c03
SL		 3804 chip = memdup_user(argp, sizeof(*chip));
3805 if (IS_ERR(chip)) {
3806 r = PTR_ERR(chip);
1fe779f8 3807 goto out;
ff5c2c03
SL		 3808 }
3809
1fe779f8
CO		 3810 r = -ENXIO;
3811 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3812 goto set_irqchip_out;
3813 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3814 if (r)
f0d66275 3815 goto set_irqchip_out;
1fe779f8 3816 r = 0;
f0d66275
DH		 3817 set_irqchip_out:
3818 kfree(chip);
1fe779f8
CO		 3819 break;
3820 }
e0f63cb9 3821 case KVM_GET_PIT: {
e0f63cb9 3822 r = -EFAULT;
f0d66275 3823 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3824 goto out;
3825 r = -ENXIO;
3826 if (!kvm->arch.vpit)
3827 goto out;
f0d66275 3828 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3829 if (r)
3830 goto out;
3831 r = -EFAULT;
f0d66275 3832 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3833 goto out;
3834 r = 0;
3835 break;
3836 }
3837 case KVM_SET_PIT: {
e0f63cb9 3838 r = -EFAULT;
f0d66275 3839 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3840 goto out;
3841 r = -ENXIO;
3842 if (!kvm->arch.vpit)
3843 goto out;
f0d66275 3844 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3845 break;
3846 }
e9f42757
BK		 3847 case KVM_GET_PIT2: {
3848 r = -ENXIO;
3849 if (!kvm->arch.vpit)
3850 goto out;
3851 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3852 if (r)
3853 goto out;
3854 r = -EFAULT;
3855 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3856 goto out;
3857 r = 0;
3858 break;
3859 }
3860 case KVM_SET_PIT2: {
3861 r = -EFAULT;
3862 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3863 goto out;
3864 r = -ENXIO;
3865 if (!kvm->arch.vpit)
3866 goto out;
3867 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3868 break;
3869 }
52d939a0
MT		 3870 case KVM_REINJECT_CONTROL: {
3871 struct kvm_reinject_control control;
3872 r = -EFAULT;
3873 if (copy_from_user(&control, argp, sizeof(control)))
3874 goto out;
3875 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3876 break;
3877 }
ffde22ac
ES		 3878 case KVM_XEN_HVM_CONFIG: {
3879 r = -EFAULT;
3880 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3881 sizeof(struct kvm_xen_hvm_config)))
3882 goto out;
3883 r = -EINVAL;
3884 if (kvm->arch.xen_hvm_config.flags)
3885 goto out;
3886 r = 0;
3887 break;
3888 }
afbcf7ab 3889 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3890 struct kvm_clock_data user_ns;
3891 u64 now_ns;
3892 s64 delta;
3893
3894 r = -EFAULT;
3895 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3896 goto out;
3897
3898 r = -EINVAL;
3899 if (user_ns.flags)
3900 goto out;
3901
3902 r = 0;
395c6b0a 3903 local_irq_disable();
759379dd 3904 now_ns = get_kernel_ns();
afbcf7ab 3905 delta = user_ns.clock - now_ns;
395c6b0a 3906 local_irq_enable();
afbcf7ab 3907 kvm->arch.kvmclock_offset = delta;
2e762ff7 3908 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3909 break;
3910 }
3911 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3912 struct kvm_clock_data user_ns;
3913 u64 now_ns;
3914
395c6b0a 3915 local_irq_disable();
759379dd 3916 now_ns = get_kernel_ns();
afbcf7ab 3917 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3918 local_irq_enable();
afbcf7ab 3919 user_ns.flags = 0;
97e69aa6 3920 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3921
3922 r = -EFAULT;
3923 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3924 goto out;
3925 r = 0;
3926 break;
3927 }
3928
1fe779f8
CO		 3929 default:
3930 ;
3931 }
3932out:
3933 return r;
3934}
3935
a16b043c 3936static void kvm_init_msr_list(void)
043405e1
CO		 3937{
3938 u32 dummy[2];
3939 unsigned i, j;
3940
e3267cbb
GC		 3941 /* skip the first msrs in the list. KVM-specific */
3942 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3943 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3944 continue;
93c4adc7
PB		 3945
3946 /*
3947 * Even MSRs that are valid in the host may not be exposed
3948 * to the guests in some cases. We could work around this
3949 * in VMX with the generic MSR save/load machinery, but it
3950 * is not really worthwhile since it will really only
3951 * happen with nested virtualization.
3952 */
3953 switch (msrs_to_save[i]) {
3954 case MSR_IA32_BNDCFGS:
3955 if (!kvm_x86_ops->mpx_supported())
3956 continue;
3957 break;
3958 default:
3959 break;
3960 }
3961
043405e1
CO		 3962 if (j < i)
3963 msrs_to_save[j] = msrs_to_save[i];
3964 j++;
3965 }
3966 num_msrs_to_save = j;
3967}
3968
bda9020e
MT		 3969static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3970 const void *v)
bbd9b64e 3971{
70252a10
AK		 3972 int handled = 0;
3973 int n;
3974
3975 do {
3976 n = min(len, 8);
3977 if (!(vcpu->arch.apic &&
3978 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3979 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3980 break;
3981 handled += n;
3982 addr += n;
3983 len -= n;
3984 v += n;
3985 } while (len);
bbd9b64e 3986
70252a10 3987 return handled;
bbd9b64e
CO		 3988}
3989
bda9020e 3990static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3991{
70252a10
AK		 3992 int handled = 0;
3993 int n;
3994
3995 do {
3996 n = min(len, 8);
3997 if (!(vcpu->arch.apic &&
3998 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3999 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4000 break;
4001 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4002 handled += n;
4003 addr += n;
4004 len -= n;
4005 v += n;
4006 } while (len);
bbd9b64e 4007
70252a10 4008 return handled;
bbd9b64e
CO		 4009}
4010
2dafc6c2
GN		 4011static void kvm_set_segment(struct kvm_vcpu *vcpu,
4012 struct kvm_segment *var, int seg)
4013{
4014 kvm_x86_ops->set_segment(vcpu, var, seg);
4015}
4016
4017void kvm_get_segment(struct kvm_vcpu *vcpu,
4018 struct kvm_segment *var, int seg)
4019{
4020 kvm_x86_ops->get_segment(vcpu, var, seg);
4021}
4022
e459e322 4023gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4024{
4025 gpa_t t_gpa;
ab9ae313 4026 struct x86_exception exception;
02f59dc9
JR		 4027
4028 BUG_ON(!mmu_is_nested(vcpu));
4029
4030 /* NPT walks are always user-walks */
4031 access |= PFERR_USER_MASK;
ab9ae313 4032 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4033
4034 return t_gpa;
4035}
4036
ab9ae313
AK		 4037gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4038 struct x86_exception *exception)
1871c602
GN		 4039{
4040 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4041 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4042}
4043
ab9ae313
AK		 4044 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4045 struct x86_exception *exception)
1871c602
GN		 4046{
4047 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4048 access |= PFERR_FETCH_MASK;
ab9ae313 4049 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4050}
4051
ab9ae313
AK		 4052gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4053 struct x86_exception *exception)
1871c602
GN		 4054{
4055 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4056 access |= PFERR_WRITE_MASK;
ab9ae313 4057 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4058}
4059
4060/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4061gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4062 struct x86_exception *exception)
1871c602 4063{
ab9ae313 4064 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4065}
4066
4067static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4068 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4069 struct x86_exception *exception)
bbd9b64e
CO		 4070{
4071 void *data = val;
10589a46 4072 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4073
4074 while (bytes) {
14dfe855 4075 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4076 exception);
bbd9b64e 4077 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4078 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4079 int ret;
4080
bcc55cba 4081 if (gpa == UNMAPPED_GVA)
ab9ae313 4082 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4083 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4084 if (ret < 0) {
c3cd7ffa 4085 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4086 goto out;
4087 }
bbd9b64e 4088
77c2002e
IE		 4089 bytes -= toread;
4090 data += toread;
4091 addr += toread;
bbd9b64e 4092 }
10589a46 4093out:
10589a46 4094 return r;
bbd9b64e 4095}
77c2002e 4096
1871c602 4097/* used for instruction fetching */
0f65dd70
AK		 4098static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4099 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4100 struct x86_exception *exception)
1871c602 4101{
0f65dd70 4102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4103 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4104
1871c602 4105 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4106 access | PFERR_FETCH_MASK,
4107 exception);
1871c602
GN		 4108}
4109
064aea77 4110int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4111 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4112 struct x86_exception *exception)
1871c602 4113{
0f65dd70 4114 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4115 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4116
1871c602 4117 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4118 exception);
1871c602 4119}
064aea77 4120EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4121
0f65dd70
AK		 4122static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4123 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4124 struct x86_exception *exception)
1871c602 4125{
0f65dd70 4126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4127 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4128}
4129
6a4d7550 4130int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4131 gva_t addr, void *val,
2dafc6c2 4132 unsigned int bytes,
bcc55cba 4133 struct x86_exception *exception)
77c2002e 4134{
0f65dd70 4135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4136 void *data = val;
4137 int r = X86EMUL_CONTINUE;
4138
4139 while (bytes) {
14dfe855
JR		 4140 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4141 PFERR_WRITE_MASK,
ab9ae313 4142 exception);
77c2002e
IE		 4143 unsigned offset = addr & (PAGE_SIZE-1);
4144 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4145 int ret;
4146
bcc55cba 4147 if (gpa == UNMAPPED_GVA)
ab9ae313 4148 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4149 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4150 if (ret < 0) {
c3cd7ffa 4151 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4152 goto out;
4153 }
4154
4155 bytes -= towrite;
4156 data += towrite;
4157 addr += towrite;
4158 }
4159out:
4160 return r;
4161}
6a4d7550 4162EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4163
af7cc7d1
XG		 4164static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4165 gpa_t *gpa, struct x86_exception *exception,
4166 bool write)
4167{
97d64b78
AK		 4168 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4169 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4170
97d64b78 4171 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4172 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4173 vcpu->arch.access, access)) {
bebb106a
XG		 4174 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4175 (gva & (PAGE_SIZE - 1));
4f022648 4176 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4177 return 1;
4178 }
4179
af7cc7d1
XG		 4180 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4181
4182 if (*gpa == UNMAPPED_GVA)
4183 return -1;
4184
4185 /* For APIC access vmexit */
4186 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4187 return 1;
4188
4f022648
XG		 4189 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4190 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4191 return 1;
4f022648 4192 }
bebb106a 4193
af7cc7d1
XG		 4194 return 0;
4195}
4196
3200f405 4197int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4198 const void *val, int bytes)
bbd9b64e
CO		 4199{
4200 int ret;
4201
4202 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4203 if (ret < 0)
bbd9b64e 4204 return 0;
f57f2ef5 4205 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4206 return 1;
4207}
4208
77d197b2
XG		 4209struct read_write_emulator_ops {
4210 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4211 int bytes);
4212 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4213 void *val, int bytes);
4214 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215 int bytes, void *val);
4216 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217 void *val, int bytes);
4218 bool write;
4219};
4220
4221static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4222{
4223 if (vcpu->mmio_read_completed) {
77d197b2 4224 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4225 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4226 vcpu->mmio_read_completed = 0;
4227 return 1;
4228 }
4229
4230 return 0;
4231}
4232
4233static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4234 void *val, int bytes)
4235{
4236 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4237}
4238
4239static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4240 void *val, int bytes)
4241{
4242 return emulator_write_phys(vcpu, gpa, val, bytes);
4243}
4244
4245static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4246{
4247 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4248 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4249}
4250
4251static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4252 void *val, int bytes)
4253{
4254 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4255 return X86EMUL_IO_NEEDED;
4256}
4257
4258static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4259 void *val, int bytes)
4260{
f78146b0
AK		 4261 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4262
87da7e66 4263 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4264 return X86EMUL_CONTINUE;
4265}
4266
0fbe9b0b 4267static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4268 .read_write_prepare = read_prepare,
4269 .read_write_emulate = read_emulate,
4270 .read_write_mmio = vcpu_mmio_read,
4271 .read_write_exit_mmio = read_exit_mmio,
4272};
4273
0fbe9b0b 4274static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4275 .read_write_emulate = write_emulate,
4276 .read_write_mmio = write_mmio,
4277 .read_write_exit_mmio = write_exit_mmio,
4278 .write = true,
4279};
4280
22388a3c
XG		 4281static int emulator_read_write_onepage(unsigned long addr, void *val,
4282 unsigned int bytes,
4283 struct x86_exception *exception,
4284 struct kvm_vcpu *vcpu,
0fbe9b0b 4285 const struct read_write_emulator_ops *ops)
bbd9b64e 4286{
af7cc7d1
XG		 4287 gpa_t gpa;
4288 int handled, ret;
22388a3c 4289 bool write = ops->write;
f78146b0 4290 struct kvm_mmio_fragment *frag;
10589a46 4291
22388a3c 4292 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4293
af7cc7d1 4294 if (ret < 0)
bbd9b64e 4295 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4296
4297 /* For APIC access vmexit */
af7cc7d1 4298 if (ret)
bbd9b64e
CO		 4299 goto mmio;
4300
22388a3c 4301 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4302 return X86EMUL_CONTINUE;
4303
4304mmio:
4305 /*
4306 * Is this MMIO handled locally?
4307 */
22388a3c 4308 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4309 if (handled == bytes)
bbd9b64e 4310 return X86EMUL_CONTINUE;
bbd9b64e 4311
70252a10
AK		 4312 gpa += handled;
4313 bytes -= handled;
4314 val += handled;
4315
87da7e66
XG		 4316 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4317 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4318 frag->gpa = gpa;
4319 frag->data = val;
4320 frag->len = bytes;
f78146b0 4321 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4322}
4323
22388a3c
XG		 4324int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4325 void *val, unsigned int bytes,
4326 struct x86_exception *exception,
0fbe9b0b 4327 const struct read_write_emulator_ops *ops)
bbd9b64e 4328{
0f65dd70 4329 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4330 gpa_t gpa;
4331 int rc;
4332
4333 if (ops->read_write_prepare &&
4334 ops->read_write_prepare(vcpu, val, bytes))
4335 return X86EMUL_CONTINUE;
4336
4337 vcpu->mmio_nr_fragments = 0;
0f65dd70 4338
bbd9b64e
CO		 4339 /* Crossing a page boundary? */
4340 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4341 int now;
bbd9b64e
CO		 4342
4343 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4344 rc = emulator_read_write_onepage(addr, val, now, exception,
4345 vcpu, ops);
4346
bbd9b64e
CO		 4347 if (rc != X86EMUL_CONTINUE)
4348 return rc;
4349 addr += now;
4350 val += now;
4351 bytes -= now;
4352 }
22388a3c 4353
f78146b0
AK		 4354 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4355 vcpu, ops);
4356 if (rc != X86EMUL_CONTINUE)
4357 return rc;
4358
4359 if (!vcpu->mmio_nr_fragments)
4360 return rc;
4361
4362 gpa = vcpu->mmio_fragments[0].gpa;
4363
4364 vcpu->mmio_needed = 1;
4365 vcpu->mmio_cur_fragment = 0;
4366
87da7e66 4367 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4368 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4369 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4370 vcpu->run->mmio.phys_addr = gpa;
4371
4372 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4373}
4374
4375static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4376 unsigned long addr,
4377 void *val,
4378 unsigned int bytes,
4379 struct x86_exception *exception)
4380{
4381 return emulator_read_write(ctxt, addr, val, bytes,
4382 exception, &read_emultor);
4383}
4384
4385int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4386 unsigned long addr,
4387 const void *val,
4388 unsigned int bytes,
4389 struct x86_exception *exception)
4390{
4391 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4392 exception, &write_emultor);
bbd9b64e 4393}
bbd9b64e 4394
daea3e73
AK		 4395#define CMPXCHG_TYPE(t, ptr, old, new) \
4396 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4397
4398#ifdef CONFIG_X86_64
4399# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4400#else
4401# define CMPXCHG64(ptr, old, new) \
9749a6c0 4402 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4403#endif
4404
0f65dd70
AK		 4405static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4406 unsigned long addr,
bbd9b64e
CO		 4407 const void *old,
4408 const void *new,
4409 unsigned int bytes,
0f65dd70 4410 struct x86_exception *exception)
bbd9b64e 4411{
0f65dd70 4412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4413 gpa_t gpa;
4414 struct page *page;
4415 char *kaddr;
4416 bool exchanged;
2bacc55c 4417
daea3e73
AK		 4418 /* guests cmpxchg8b have to be emulated atomically */
4419 if (bytes > 8 || (bytes & (bytes - 1)))
4420 goto emul_write;
10589a46 4421
daea3e73 4422 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4423
daea3e73
AK		 4424 if (gpa == UNMAPPED_GVA ||
4425 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4426 goto emul_write;
2bacc55c 4427
daea3e73
AK		 4428 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4429 goto emul_write;
72dc67a6 4430
daea3e73 4431 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4432 if (is_error_page(page))
c19b8bd6 4433 goto emul_write;
72dc67a6 4434
8fd75e12 4435 kaddr = kmap_atomic(page);
daea3e73
AK		 4436 kaddr += offset_in_page(gpa);
4437 switch (bytes) {
4438 case 1:
4439 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4440 break;
4441 case 2:
4442 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4443 break;
4444 case 4:
4445 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4446 break;
4447 case 8:
4448 exchanged = CMPXCHG64(kaddr, old, new);
4449 break;
4450 default:
4451 BUG();
2bacc55c 4452 }
8fd75e12 4453 kunmap_atomic(kaddr);
daea3e73
AK		 4454 kvm_release_page_dirty(page);
4455
4456 if (!exchanged)
4457 return X86EMUL_CMPXCHG_FAILED;
4458
d3714010 4459 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4460 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4461
4462 return X86EMUL_CONTINUE;
4a5f48f6 4463
3200f405 4464emul_write:
daea3e73 4465 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4466
0f65dd70 4467 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4468}
4469
cf8f70bf
GN		 4470static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4471{
4472 /* TODO: String I/O for in kernel device */
4473 int r;
4474
4475 if (vcpu->arch.pio.in)
4476 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4477 vcpu->arch.pio.size, pd);
4478 else
4479 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4480 vcpu->arch.pio.port, vcpu->arch.pio.size,
4481 pd);
4482 return r;
4483}
4484
6f6fbe98
XG		 4485static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4486 unsigned short port, void *val,
4487 unsigned int count, bool in)
cf8f70bf 4488{
6f6fbe98 4489 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4490
4491 vcpu->arch.pio.port = port;
6f6fbe98 4492 vcpu->arch.pio.in = in;
7972995b 4493 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4494 vcpu->arch.pio.size = size;
4495
4496 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4497 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4498 return 1;
4499 }
4500
4501 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4502 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4503 vcpu->run->io.size = size;
4504 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4505 vcpu->run->io.count = count;
4506 vcpu->run->io.port = port;
4507
4508 return 0;
4509}
4510
6f6fbe98
XG		 4511static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4512 int size, unsigned short port, void *val,
4513 unsigned int count)
cf8f70bf 4514{
ca1d4a9e 4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4516 int ret;
ca1d4a9e 4517
6f6fbe98
XG		 4518 if (vcpu->arch.pio.count)
4519 goto data_avail;
cf8f70bf 4520
6f6fbe98
XG		 4521 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4522 if (ret) {
4523data_avail:
4524 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4525 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4526 return 1;
4527 }
4528
cf8f70bf
GN		 4529 return 0;
4530}
4531
6f6fbe98
XG		 4532static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4533 int size, unsigned short port,
4534 const void *val, unsigned int count)
4535{
4536 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4537
4538 memcpy(vcpu->arch.pio_data, val, size * count);
4539 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4540}
4541
bbd9b64e
CO		 4542static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4543{
4544 return kvm_x86_ops->get_segment_base(vcpu, seg);
4545}
4546
3cb16fe7 4547static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4548{
3cb16fe7 4549 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4550}
4551
f5f48ee1
SY		 4552int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4553{
4554 if (!need_emulate_wbinvd(vcpu))
4555 return X86EMUL_CONTINUE;
4556
4557 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4558 int cpu = get_cpu();
4559
4560 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4561 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4562 wbinvd_ipi, NULL, 1);
2eec7343 4563 put_cpu();
f5f48ee1 4564 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4565 } else
4566 wbinvd();
f5f48ee1
SY		 4567 return X86EMUL_CONTINUE;
4568}
4569EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4570
bcaf5cc5
AK		 4571static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4572{
4573 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4574}
4575
717746e3 4576int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4577{
717746e3 4578 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4579}
4580
717746e3 4581int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4582{
338dbc97 4583
717746e3 4584 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4585}
4586
52a46617 4587static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4588{
52a46617 4589 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4590}
4591
717746e3 4592static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4593{
717746e3 4594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4595 unsigned long value;
4596
4597 switch (cr) {
4598 case 0:
4599 value = kvm_read_cr0(vcpu);
4600 break;
4601 case 2:
4602 value = vcpu->arch.cr2;
4603 break;
4604 case 3:
9f8fe504 4605 value = kvm_read_cr3(vcpu);
52a46617
GN		 4606 break;
4607 case 4:
4608 value = kvm_read_cr4(vcpu);
4609 break;
4610 case 8:
4611 value = kvm_get_cr8(vcpu);
4612 break;
4613 default:
a737f256 4614 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4615 return 0;
4616 }
4617
4618 return value;
4619}
4620
717746e3 4621static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4622{
717746e3 4623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4624 int res = 0;
4625
52a46617
GN		 4626 switch (cr) {
4627 case 0:
49a9b07e 4628 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4629 break;
4630 case 2:
4631 vcpu->arch.cr2 = val;
4632 break;
4633 case 3:
2390218b 4634 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4635 break;
4636 case 4:
a83b29c6 4637 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4638 break;
4639 case 8:
eea1cff9 4640 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4641 break;
4642 default:
a737f256 4643 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4644 res = -1;
52a46617 4645 }
0f12244f
GN		 4646
4647 return res;
52a46617
GN		 4648}
4649
4cee4798
KW		 4650static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4651{
4652 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4653}
4654
717746e3 4655static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4656{
717746e3 4657 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4658}
4659
4bff1e86 4660static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4661{
4bff1e86 4662 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4663}
4664
4bff1e86 4665static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4666{
4bff1e86 4667 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4668}
4669
1ac9d0cf
AK		 4670static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4671{
4672 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4673}
4674
4675static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4676{
4677 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4678}
4679
4bff1e86
AK		 4680static unsigned long emulator_get_cached_segment_base(
4681 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4682{
4bff1e86 4683 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4684}
4685
1aa36616
AK		 4686static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4687 struct desc_struct *desc, u32 *base3,
4688 int seg)
2dafc6c2
GN		 4689{
4690 struct kvm_segment var;
4691
4bff1e86 4692 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4693 *selector = var.selector;
2dafc6c2 4694
378a8b09
GN		 4695 if (var.unusable) {
4696 memset(desc, 0, sizeof(*desc));
2dafc6c2 4697 return false;
378a8b09 4698 }
2dafc6c2
GN		 4699
4700 if (var.g)
4701 var.limit >>= 12;
4702 set_desc_limit(desc, var.limit);
4703 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4704#ifdef CONFIG_X86_64
4705 if (base3)
4706 *base3 = var.base >> 32;
4707#endif
2dafc6c2
GN		 4708 desc->type = var.type;
4709 desc->s = var.s;
4710 desc->dpl = var.dpl;
4711 desc->p = var.present;
4712 desc->avl = var.avl;
4713 desc->l = var.l;
4714 desc->d = var.db;
4715 desc->g = var.g;
4716
4717 return true;
4718}
4719
1aa36616
AK		 4720static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4721 struct desc_struct *desc, u32 base3,
4722 int seg)
2dafc6c2 4723{
4bff1e86 4724 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4725 struct kvm_segment var;
4726
1aa36616 4727 var.selector = selector;
2dafc6c2 4728 var.base = get_desc_base(desc);
5601d05b
GN		 4729#ifdef CONFIG_X86_64
4730 var.base |= ((u64)base3) << 32;
4731#endif
2dafc6c2
GN		 4732 var.limit = get_desc_limit(desc);
4733 if (desc->g)
4734 var.limit = (var.limit << 12) | 0xfff;
4735 var.type = desc->type;
4736 var.present = desc->p;
4737 var.dpl = desc->dpl;
4738 var.db = desc->d;
4739 var.s = desc->s;
4740 var.l = desc->l;
4741 var.g = desc->g;
4742 var.avl = desc->avl;
4743 var.present = desc->p;
4744 var.unusable = !var.present;
4745 var.padding = 0;
4746
4747 kvm_set_segment(vcpu, &var, seg);
4748 return;
4749}
4750
717746e3
AK		 4751static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4752 u32 msr_index, u64 *pdata)
4753{
4754 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4755}
4756
4757static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4758 u32 msr_index, u64 data)
4759{
8fe8ab46
WA		 4760 struct msr_data msr;
4761
4762 msr.data = data;
4763 msr.index = msr_index;
4764 msr.host_initiated = false;
4765 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4766}
4767
222d21aa
AK		 4768static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4769 u32 pmc, u64 *pdata)
4770{
4771 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4772}
4773
6c3287f7
AK		 4774static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4775{
4776 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4777}
4778
5037f6f3
AK		 4779static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4780{
4781 preempt_disable();
5197b808 4782 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4783 /*
4784 * CR0.TS may reference the host fpu state, not the guest fpu state,
4785 * so it may be clear at this point.
4786 */
4787 clts();
4788}
4789
4790static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4791{
4792 preempt_enable();
4793}
4794
2953538e 4795static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4796 struct x86_instruction_info *info,
c4f035c6
AK		 4797 enum x86_intercept_stage stage)
4798{
2953538e 4799 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4800}
4801
0017f93a 4802static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4803 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4804{
0017f93a 4805 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4806}
4807
dd856efa
AK		 4808static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4809{
4810 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4811}
4812
4813static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4814{
4815 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4816}
4817
0225fb50 4818static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4819 .read_gpr = emulator_read_gpr,
4820 .write_gpr = emulator_write_gpr,
1871c602 4821 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4822 .write_std = kvm_write_guest_virt_system,
1871c602 4823 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4824 .read_emulated = emulator_read_emulated,
4825 .write_emulated = emulator_write_emulated,
4826 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4827 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4828 .pio_in_emulated = emulator_pio_in_emulated,
4829 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4830 .get_segment = emulator_get_segment,
4831 .set_segment = emulator_set_segment,
5951c442 4832 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4833 .get_gdt = emulator_get_gdt,
160ce1f1 4834 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4835 .set_gdt = emulator_set_gdt,
4836 .set_idt = emulator_set_idt,
52a46617
GN		 4837 .get_cr = emulator_get_cr,
4838 .set_cr = emulator_set_cr,
4cee4798 4839 .set_rflags = emulator_set_rflags,
9c537244 4840 .cpl = emulator_get_cpl,
35aa5375
GN		 4841 .get_dr = emulator_get_dr,
4842 .set_dr = emulator_set_dr,
717746e3
AK		 4843 .set_msr = emulator_set_msr,
4844 .get_msr = emulator_get_msr,
222d21aa 4845 .read_pmc = emulator_read_pmc,
6c3287f7 4846 .halt = emulator_halt,
bcaf5cc5 4847 .wbinvd = emulator_wbinvd,
d6aa1000 4848 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4849 .get_fpu = emulator_get_fpu,
4850 .put_fpu = emulator_put_fpu,
c4f035c6 4851 .intercept = emulator_intercept,
bdb42f5a 4852 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4853};
4854
95cb2295
GN		 4855static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4856{
4857 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4858 /*
4859 * an sti; sti; sequence only disable interrupts for the first
4860 * instruction. So, if the last instruction, be it emulated or
4861 * not, left the system with the INT_STI flag enabled, it
4862 * means that the last instruction is an sti. We should not
4863 * leave the flag on in this case. The same goes for mov ss
4864 */
4865 if (!(int_shadow & mask))
4866 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4867}
4868
54b8486f
GN		 4869static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4870{
4871 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4872 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4873 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4874 else if (ctxt->exception.error_code_valid)
4875 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4876 ctxt->exception.error_code);
54b8486f 4877 else
da9cb575 4878 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4879}
4880
dd856efa 4881static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4882{
1ce19dc1
BP		 4883 memset(&ctxt->opcode_len, 0,
4884 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4885
9dac77fa
AK		 4886 ctxt->fetch.start = 0;
4887 ctxt->fetch.end = 0;
4888 ctxt->io_read.pos = 0;
4889 ctxt->io_read.end = 0;
4890 ctxt->mem_read.pos = 0;
4891 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4892}
4893
8ec4722d
MG		 4894static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4895{
adf52235 4896 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4897 int cs_db, cs_l;
4898
8ec4722d
MG		 4899 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4900
adf52235
TY		 4901 ctxt->eflags = kvm_get_rflags(vcpu);
4902 ctxt->eip = kvm_rip_read(vcpu);
4903 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4904 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4905 cs_l ? X86EMUL_MODE_PROT64 :
4906 cs_db ? X86EMUL_MODE_PROT32 :
4907 X86EMUL_MODE_PROT16;
4908 ctxt->guest_mode = is_guest_mode(vcpu);
4909
dd856efa 4910 init_decode_cache(ctxt);
7ae441ea 4911 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4912}
4913
71f9833b 4914int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4915{
9d74191a 4916 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4917 int ret;
4918
4919 init_emulate_ctxt(vcpu);
4920
9dac77fa
AK		 4921 ctxt->op_bytes = 2;
4922 ctxt->ad_bytes = 2;
4923 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4924 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4925
4926 if (ret != X86EMUL_CONTINUE)
4927 return EMULATE_FAIL;
4928
9dac77fa 4929 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4930 kvm_rip_write(vcpu, ctxt->eip);
4931 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4932
4933 if (irq == NMI_VECTOR)
7460fb4a 4934 vcpu->arch.nmi_pending = 0;
63995653
MG		 4935 else
4936 vcpu->arch.interrupt.pending = false;
4937
4938 return EMULATE_DONE;
4939}
4940EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4941
6d77dbfc
GN		 4942static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4943{
fc3a9157
JR		 4944 int r = EMULATE_DONE;
4945
6d77dbfc
GN		 4946 ++vcpu->stat.insn_emulation_fail;
4947 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4948 if (!is_guest_mode(vcpu)) {
4949 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4950 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4951 vcpu->run->internal.ndata = 0;
4952 r = EMULATE_FAIL;
4953 }
6d77dbfc 4954 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4955
4956 return r;
6d77dbfc
GN		 4957}
4958
93c05d3e 4959static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4960 bool write_fault_to_shadow_pgtable,
4961 int emulation_type)
a6f177ef 4962{
95b3cf69 4963 gpa_t gpa = cr2;
8e3d9d06 4964 pfn_t pfn;
a6f177ef 4965
991eebf9
GN		 4966 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4967 return false;
4968
95b3cf69
XG		 4969 if (!vcpu->arch.mmu.direct_map) {
4970 /*
4971 * Write permission should be allowed since only
4972 * write access need to be emulated.
4973 */
4974 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4975
95b3cf69
XG		 4976 /*
4977 * If the mapping is invalid in guest, let cpu retry
4978 * it to generate fault.
4979 */
4980 if (gpa == UNMAPPED_GVA)
4981 return true;
4982 }
a6f177ef 4983
8e3d9d06
XG		 4984 /*
4985 * Do not retry the unhandleable instruction if it faults on the
4986 * readonly host memory, otherwise it will goto a infinite loop:
4987 * retry instruction -> write #PF -> emulation fail -> retry
4988 * instruction -> ...
4989 */
4990 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4991
4992 /*
4993 * If the instruction failed on the error pfn, it can not be fixed,
4994 * report the error to userspace.
4995 */
4996 if (is_error_noslot_pfn(pfn))
4997 return false;
4998
4999 kvm_release_pfn_clean(pfn);
5000
5001 /* The instructions are well-emulated on direct mmu. */
5002 if (vcpu->arch.mmu.direct_map) {
5003 unsigned int indirect_shadow_pages;
5004
5005 spin_lock(&vcpu->kvm->mmu_lock);
5006 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5007 spin_unlock(&vcpu->kvm->mmu_lock);
5008
5009 if (indirect_shadow_pages)
5010 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5011
a6f177ef 5012 return true;
8e3d9d06 5013 }
a6f177ef 5014
95b3cf69
XG		 5015 /*
5016 * if emulation was due to access to shadowed page table
5017 * and it failed try to unshadow page and re-enter the
5018 * guest to let CPU execute the instruction.
5019 */
5020 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5021
5022 /*
5023 * If the access faults on its page table, it can not
5024 * be fixed by unprotecting shadow page and it should
5025 * be reported to userspace.
5026 */
5027 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5028}
5029
1cb3f3ae
XG		 5030static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5031 unsigned long cr2, int emulation_type)
5032{
5033 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5034 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5035
5036 last_retry_eip = vcpu->arch.last_retry_eip;
5037 last_retry_addr = vcpu->arch.last_retry_addr;
5038
5039 /*
5040 * If the emulation is caused by #PF and it is non-page_table
5041 * writing instruction, it means the VM-EXIT is caused by shadow
5042 * page protected, we can zap the shadow page and retry this
5043 * instruction directly.
5044 *
5045 * Note: if the guest uses a non-page-table modifying instruction
5046 * on the PDE that points to the instruction, then we will unmap
5047 * the instruction and go to an infinite loop. So, we cache the
5048 * last retried eip and the last fault address, if we meet the eip
5049 * and the address again, we can break out of the potential infinite
5050 * loop.
5051 */
5052 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5053
5054 if (!(emulation_type & EMULTYPE_RETRY))
5055 return false;
5056
5057 if (x86_page_table_writing_insn(ctxt))
5058 return false;
5059
5060 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5061 return false;
5062
5063 vcpu->arch.last_retry_eip = ctxt->eip;
5064 vcpu->arch.last_retry_addr = cr2;
5065
5066 if (!vcpu->arch.mmu.direct_map)
5067 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5068
22368028 5069 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5070
5071 return true;
5072}
5073
716d51ab
GN		 5074static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5075static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5076
4a1e10d5
PB		 5077static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5078 unsigned long *db)
5079{
5080 u32 dr6 = 0;
5081 int i;
5082 u32 enable, rwlen;
5083
5084 enable = dr7;
5085 rwlen = dr7 >> 16;
5086 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5087 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5088 dr6 |= (1 << i);
5089 return dr6;
5090}
5091
663f4c61
PB		 5092static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5093{
5094 struct kvm_run *kvm_run = vcpu->run;
5095
5096 /*
5097 * Use the "raw" value to see if TF was passed to the processor.
5098 * Note that the new value of the flags has not been saved yet.
5099 *
5100 * This is correct even for TF set by the guest, because "the
5101 * processor will not generate this exception after the instruction
5102 * that sets the TF flag".
5103 */
5104 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5105
5106 if (unlikely(rflags & X86_EFLAGS_TF)) {
5107 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5108 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5109 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5110 kvm_run->debug.arch.exception = DB_VECTOR;
5111 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5112 *r = EMULATE_USER_EXIT;
5113 } else {
5114 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5115 /*
5116 * "Certain debug exceptions may clear bit 0-3. The
5117 * remaining contents of the DR6 register are never
5118 * cleared by the processor".
5119 */
5120 vcpu->arch.dr6 &= ~15;
5121 vcpu->arch.dr6 |= DR6_BS;
5122 kvm_queue_exception(vcpu, DB_VECTOR);
5123 }
5124 }
5125}
5126
4a1e10d5
PB		 5127static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5128{
5129 struct kvm_run *kvm_run = vcpu->run;
5130 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5131 u32 dr6 = 0;
5132
5133 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5134 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5135 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5136 vcpu->arch.guest_debug_dr7,
5137 vcpu->arch.eff_db);
5138
5139 if (dr6 != 0) {
5140 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5141 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5142 get_segment_base(vcpu, VCPU_SREG_CS);
5143
5144 kvm_run->debug.arch.exception = DB_VECTOR;
5145 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5146 *r = EMULATE_USER_EXIT;
5147 return true;
5148 }
5149 }
5150
5151 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5152 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5153 vcpu->arch.dr7,
5154 vcpu->arch.db);
5155
5156 if (dr6 != 0) {
5157 vcpu->arch.dr6 &= ~15;
5158 vcpu->arch.dr6 |= dr6;
5159 kvm_queue_exception(vcpu, DB_VECTOR);
5160 *r = EMULATE_DONE;
5161 return true;
5162 }
5163 }
5164
5165 return false;
5166}
5167
51d8b661
AP		 5168int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5169 unsigned long cr2,
dc25e89e
AP		 5170 int emulation_type,
5171 void *insn,
5172 int insn_len)
bbd9b64e 5173{
95cb2295 5174 int r;
9d74191a 5175 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5176 bool writeback = true;
93c05d3e 5177 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5178
93c05d3e
XG		 5179 /*
5180 * Clear write_fault_to_shadow_pgtable here to ensure it is
5181 * never reused.
5182 */
5183 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5184 kvm_clear_exception_queue(vcpu);
8d7d8102 5185
571008da 5186 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5187 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5188
5189 /*
5190 * We will reenter on the same instruction since
5191 * we do not set complete_userspace_io. This does not
5192 * handle watchpoints yet, those would be handled in
5193 * the emulate_ops.
5194 */
5195 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5196 return r;
5197
9d74191a
TY		 5198 ctxt->interruptibility = 0;
5199 ctxt->have_exception = false;
5200 ctxt->perm_ok = false;
bbd9b64e 5201
b51e974f 5202 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5203
9d74191a 5204 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5205
e46479f8 5206 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5207 ++vcpu->stat.insn_emulation;
1d2887e2 5208 if (r != EMULATION_OK) {
4005996e
AK		 5209 if (emulation_type & EMULTYPE_TRAP_UD)
5210 return EMULATE_FAIL;
991eebf9
GN		 5211 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5212 emulation_type))
bbd9b64e 5213 return EMULATE_DONE;
6d77dbfc
GN		 5214 if (emulation_type & EMULTYPE_SKIP)
5215 return EMULATE_FAIL;
5216 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5217 }
5218 }
5219
ba8afb6b 5220 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5221 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5222 return EMULATE_DONE;
5223 }
5224
1cb3f3ae
XG		 5225 if (retry_instruction(ctxt, cr2, emulation_type))
5226 return EMULATE_DONE;
5227
7ae441ea 5228 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5229 changes registers values during IO operation */
7ae441ea
GN		 5230 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5231 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5232 emulator_invalidate_register_cache(ctxt);
7ae441ea 5233 }
4d2179e1 5234
5cd21917 5235restart:
9d74191a 5236 r = x86_emulate_insn(ctxt);
bbd9b64e 5237
775fde86
JR		 5238 if (r == EMULATION_INTERCEPTED)
5239 return EMULATE_DONE;
5240
d2ddd1c4 5241 if (r == EMULATION_FAILED) {
991eebf9
GN		 5242 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5243 emulation_type))
c3cd7ffa
GN		 5244 return EMULATE_DONE;
5245
6d77dbfc 5246 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5247 }
5248
9d74191a 5249 if (ctxt->have_exception) {
54b8486f 5250 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5251 r = EMULATE_DONE;
5252 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5253 if (!vcpu->arch.pio.in) {
5254 /* FIXME: return into emulator if single-stepping. */
3457e419 5255 vcpu->arch.pio.count = 0;
0912c977 5256 } else {
7ae441ea 5257 writeback = false;
716d51ab
GN		 5258 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5259 }
ac0a48c3 5260 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5261 } else if (vcpu->mmio_needed) {
5262 if (!vcpu->mmio_is_write)
5263 writeback = false;
ac0a48c3 5264 r = EMULATE_USER_EXIT;
716d51ab 5265 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5266 } else if (r == EMULATION_RESTART)
5cd21917 5267 goto restart;
d2ddd1c4
GN		 5268 else
5269 r = EMULATE_DONE;
f850e2e6 5270
7ae441ea 5271 if (writeback) {
9d74191a 5272 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5273 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5274 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5275 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5276 if (r == EMULATE_DONE)
5277 kvm_vcpu_check_singlestep(vcpu, &r);
5278 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5279 } else
5280 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5281
5282 return r;
de7d789a 5283}
51d8b661 5284EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5285
cf8f70bf 5286int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5287{
cf8f70bf 5288 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5289 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5290 size, port, &val, 1);
cf8f70bf 5291 /* do not return to emulator after return from userspace */
7972995b 5292 vcpu->arch.pio.count = 0;
de7d789a
CO		 5293 return ret;
5294}
cf8f70bf 5295EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5296
8cfdc000
ZA		 5297static void tsc_bad(void *info)
5298{
0a3aee0d 5299 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5300}
5301
5302static void tsc_khz_changed(void *data)
c8076604 5303{
8cfdc000
ZA		 5304 struct cpufreq_freqs *freq = data;
5305 unsigned long khz = 0;
5306
5307 if (data)
5308 khz = freq->new;
5309 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5310 khz = cpufreq_quick_get(raw_smp_processor_id());
5311 if (!khz)
5312 khz = tsc_khz;
0a3aee0d 5313 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5314}
5315
c8076604
GH		 5316static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5317 void *data)
5318{
5319 struct cpufreq_freqs *freq = data;
5320 struct kvm *kvm;
5321 struct kvm_vcpu *vcpu;
5322 int i, send_ipi = 0;
5323
8cfdc000
ZA		 5324 /*
5325 * We allow guests to temporarily run on slowing clocks,
5326 * provided we notify them after, or to run on accelerating
5327 * clocks, provided we notify them before. Thus time never
5328 * goes backwards.
5329 *
5330 * However, we have a problem. We can't atomically update
5331 * the frequency of a given CPU from this function; it is
5332 * merely a notifier, which can be called from any CPU.
5333 * Changing the TSC frequency at arbitrary points in time
5334 * requires a recomputation of local variables related to
5335 * the TSC for each VCPU. We must flag these local variables
5336 * to be updated and be sure the update takes place with the
5337 * new frequency before any guests proceed.
5338 *
5339 * Unfortunately, the combination of hotplug CPU and frequency
5340 * change creates an intractable locking scenario; the order
5341 * of when these callouts happen is undefined with respect to
5342 * CPU hotplug, and they can race with each other. As such,
5343 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5344 * undefined; you can actually have a CPU frequency change take
5345 * place in between the computation of X and the setting of the
5346 * variable. To protect against this problem, all updates of
5347 * the per_cpu tsc_khz variable are done in an interrupt
5348 * protected IPI, and all callers wishing to update the value
5349 * must wait for a synchronous IPI to complete (which is trivial
5350 * if the caller is on the CPU already). This establishes the
5351 * necessary total order on variable updates.
5352 *
5353 * Note that because a guest time update may take place
5354 * anytime after the setting of the VCPU's request bit, the
5355 * correct TSC value must be set before the request. However,
5356 * to ensure the update actually makes it to any guest which
5357 * starts running in hardware virtualization between the set
5358 * and the acquisition of the spinlock, we must also ping the
5359 * CPU after setting the request bit.
5360 *
5361 */
5362
c8076604
GH		 5363 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5364 return 0;
5365 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5366 return 0;
8cfdc000
ZA		 5367
5368 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5369
2f303b74 5370 spin_lock(&kvm_lock);
c8076604 5371 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5372 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5373 if (vcpu->cpu != freq->cpu)
5374 continue;
c285545f 5375 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5376 if (vcpu->cpu != smp_processor_id())
8cfdc000 5377 send_ipi = 1;
c8076604
GH		 5378 }
5379 }
2f303b74 5380 spin_unlock(&kvm_lock);
c8076604
GH		 5381
5382 if (freq->old < freq->new && send_ipi) {
5383 /*
5384 * We upscale the frequency. Must make the guest
5385 * doesn't see old kvmclock values while running with
5386 * the new frequency, otherwise we risk the guest sees
5387 * time go backwards.
5388 *
5389 * In case we update the frequency for another cpu
5390 * (which might be in guest context) send an interrupt
5391 * to kick the cpu out of guest context. Next time
5392 * guest context is entered kvmclock will be updated,
5393 * so the guest will not see stale values.
5394 */
8cfdc000 5395 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5396 }
5397 return 0;
5398}
5399
5400static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5401 .notifier_call = kvmclock_cpufreq_notifier
5402};
5403
5404static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5405 unsigned long action, void *hcpu)
5406{
5407 unsigned int cpu = (unsigned long)hcpu;
5408
5409 switch (action) {
5410 case CPU_ONLINE:
5411 case CPU_DOWN_FAILED:
5412 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5413 break;
5414 case CPU_DOWN_PREPARE:
5415 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5416 break;
5417 }
5418 return NOTIFY_OK;
5419}
5420
5421static struct notifier_block kvmclock_cpu_notifier_block = {
5422 .notifier_call = kvmclock_cpu_notifier,
5423 .priority = -INT_MAX
c8076604
GH		 5424};
5425
b820cc0c
ZA		 5426static void kvm_timer_init(void)
5427{
5428 int cpu;
5429
c285545f 5430 max_tsc_khz = tsc_khz;
460dd42e
SB		 5431
5432 cpu_notifier_register_begin();
b820cc0c 5433 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5434#ifdef CONFIG_CPU_FREQ
5435 struct cpufreq_policy policy;
5436 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5437 cpu = get_cpu();
5438 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5439 if (policy.cpuinfo.max_freq)
5440 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5441 put_cpu();
c285545f 5442#endif
b820cc0c
ZA		 5443 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5444 CPUFREQ_TRANSITION_NOTIFIER);
5445 }
c285545f 5446 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5447 for_each_online_cpu(cpu)
5448 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5449
5450 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5451 cpu_notifier_register_done();
5452
b820cc0c
ZA		 5453}
5454
ff9d07a0
ZY		 5455static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5456
f5132b01 5457int kvm_is_in_guest(void)
ff9d07a0 5458{
086c9855 5459 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5460}
5461
5462static int kvm_is_user_mode(void)
5463{
5464 int user_mode = 3;
dcf46b94 5465
086c9855
AS		 5466 if (__this_cpu_read(current_vcpu))
5467 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5468
ff9d07a0
ZY		 5469 return user_mode != 0;
5470}
5471
5472static unsigned long kvm_get_guest_ip(void)
5473{
5474 unsigned long ip = 0;
dcf46b94 5475
086c9855
AS		 5476 if (__this_cpu_read(current_vcpu))
5477 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5478
ff9d07a0
ZY		 5479 return ip;
5480}
5481
5482static struct perf_guest_info_callbacks kvm_guest_cbs = {
5483 .is_in_guest = kvm_is_in_guest,
5484 .is_user_mode = kvm_is_user_mode,
5485 .get_guest_ip = kvm_get_guest_ip,
5486};
5487
5488void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5489{
086c9855 5490 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5491}
5492EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5493
5494void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5495{
086c9855 5496 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5497}
5498EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5499
ce88decf
XG		 5500static void kvm_set_mmio_spte_mask(void)
5501{
5502 u64 mask;
5503 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5504
5505 /*
5506 * Set the reserved bits and the present bit of an paging-structure
5507 * entry to generate page fault with PFER.RSV = 1.
5508 */
885032b9
XG		 5509 /* Mask the reserved physical address bits. */
5510 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5511
5512 /* Bit 62 is always reserved for 32bit host. */
5513 mask |= 0x3ull << 62;
5514
5515 /* Set the present bit. */
ce88decf
XG		 5516 mask |= 1ull;
5517
5518#ifdef CONFIG_X86_64
5519 /*
5520 * If reserved bit is not supported, clear the present bit to disable
5521 * mmio page fault.
5522 */
5523 if (maxphyaddr == 52)
5524 mask &= ~1ull;
5525#endif
5526
5527 kvm_mmu_set_mmio_spte_mask(mask);
5528}
5529
16e8d74d
MT		 5530#ifdef CONFIG_X86_64
5531static void pvclock_gtod_update_fn(struct work_struct *work)
5532{
d828199e
MT		 5533 struct kvm *kvm;
5534
5535 struct kvm_vcpu *vcpu;
5536 int i;
5537
2f303b74 5538 spin_lock(&kvm_lock);
d828199e
MT		 5539 list_for_each_entry(kvm, &vm_list, vm_list)
5540 kvm_for_each_vcpu(i, vcpu, kvm)
5541 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5542 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5543 spin_unlock(&kvm_lock);
16e8d74d
MT		 5544}
5545
5546static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5547
5548/*
5549 * Notification about pvclock gtod data update.
5550 */
5551static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5552 void *priv)
5553{
5554 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5555 struct timekeeper *tk = priv;
5556
5557 update_pvclock_gtod(tk);
5558
5559 /* disable master clock if host does not trust, or does not
5560 * use, TSC clocksource
5561 */
5562 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5563 atomic_read(&kvm_guest_has_master_clock) != 0)
5564 queue_work(system_long_wq, &pvclock_gtod_work);
5565
5566 return 0;
5567}
5568
5569static struct notifier_block pvclock_gtod_notifier = {
5570 .notifier_call = pvclock_gtod_notify,
5571};
5572#endif
5573
f8c16bba 5574int kvm_arch_init(void *opaque)
043405e1 5575{
b820cc0c 5576 int r;
6b61edf7 5577 struct kvm_x86_ops *ops = opaque;
f8c16bba 5578
f8c16bba
ZX		 5579 if (kvm_x86_ops) {
5580 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5581 r = -EEXIST;
5582 goto out;
f8c16bba
ZX		 5583 }
5584
5585 if (!ops->cpu_has_kvm_support()) {
5586 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5587 r = -EOPNOTSUPP;
5588 goto out;
f8c16bba
ZX		 5589 }
5590 if (ops->disabled_by_bios()) {
5591 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5592 r = -EOPNOTSUPP;
5593 goto out;
f8c16bba
ZX		 5594 }
5595
013f6a5d
MT		 5596 r = -ENOMEM;
5597 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5598 if (!shared_msrs) {
5599 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5600 goto out;
5601 }
5602
97db56ce
AK		 5603 r = kvm_mmu_module_init();
5604 if (r)
013f6a5d 5605 goto out_free_percpu;
97db56ce 5606
ce88decf 5607 kvm_set_mmio_spte_mask();
97db56ce 5608
f8c16bba 5609 kvm_x86_ops = ops;
920c8377
PB		 5610 kvm_init_msr_list();
5611
7b52345e 5612 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5613 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5614
b820cc0c 5615 kvm_timer_init();
c8076604 5616
ff9d07a0
ZY		 5617 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5618
2acf923e
DC		 5619 if (cpu_has_xsave)
5620 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5621
c5cc421b 5622 kvm_lapic_init();
16e8d74d
MT		 5623#ifdef CONFIG_X86_64
5624 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5625#endif
5626
f8c16bba 5627 return 0;
56c6d28a 5628
013f6a5d
MT		 5629out_free_percpu:
5630 free_percpu(shared_msrs);
56c6d28a 5631out:
56c6d28a 5632 return r;
043405e1 5633}
8776e519 5634
f8c16bba
ZX		 5635void kvm_arch_exit(void)
5636{
ff9d07a0
ZY		 5637 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5638
888d256e
JK		 5639 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5640 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5641 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5642 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5643#ifdef CONFIG_X86_64
5644 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5645#endif
f8c16bba 5646 kvm_x86_ops = NULL;
56c6d28a 5647 kvm_mmu_module_exit();
013f6a5d 5648 free_percpu(shared_msrs);
56c6d28a 5649}
f8c16bba 5650
8776e519
HB		 5651int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5652{
5653 ++vcpu->stat.halt_exits;
5654 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5655 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5656 return 1;
5657 } else {
5658 vcpu->run->exit_reason = KVM_EXIT_HLT;
5659 return 0;
5660 }
5661}
5662EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5663
55cd8e5a
GN		 5664int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5665{
5666 u64 param, ingpa, outgpa, ret;
5667 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5668 bool fast, longmode;
5669 int cs_db, cs_l;
5670
5671 /*
5672 * hypercall generates UD from non zero cpl and real mode
5673 * per HYPER-V spec
5674 */
3eeb3288 5675 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5676 kvm_queue_exception(vcpu, UD_VECTOR);
5677 return 0;
5678 }
5679
5680 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5681 longmode = is_long_mode(vcpu) && cs_l == 1;
5682
5683 if (!longmode) {
ccd46936
GN		 5684 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5685 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5686 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5687 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5688 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5689 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5690 }
5691#ifdef CONFIG_X86_64
5692 else {
5693 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5694 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5695 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5696 }
5697#endif
5698
5699 code = param & 0xffff;
5700 fast = (param >> 16) & 0x1;
5701 rep_cnt = (param >> 32) & 0xfff;
5702 rep_idx = (param >> 48) & 0xfff;
5703
5704 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5705
c25bc163
GN		 5706 switch (code) {
5707 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5708 kvm_vcpu_on_spin(vcpu);
5709 break;
5710 default:
5711 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5712 break;
5713 }
55cd8e5a
GN		 5714
5715 ret = res | (((u64)rep_done & 0xfff) << 32);
5716 if (longmode) {
5717 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5718 } else {
5719 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5720 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5721 }
5722
5723 return 1;
5724}
5725
6aef266c
SV		 5726/*
5727 * kvm_pv_kick_cpu_op: Kick a vcpu.
5728 *
5729 * @apicid - apicid of vcpu to be kicked.
5730 */
5731static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5732{
24d2166b 5733 struct kvm_lapic_irq lapic_irq;
6aef266c 5734
24d2166b
R		 5735 lapic_irq.shorthand = 0;
5736 lapic_irq.dest_mode = 0;
5737 lapic_irq.dest_id = apicid;
6aef266c 5738
24d2166b
R		 5739 lapic_irq.delivery_mode = APIC_DM_REMRD;
5740 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5741}
5742
8776e519
HB		 5743int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5744{
5745 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5746 int r = 1;
8776e519 5747
55cd8e5a
GN		 5748 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5749 return kvm_hv_hypercall(vcpu);
5750
5fdbf976
MT		 5751 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5752 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5753 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5756
229456fc 5757 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5758
8776e519
HB		 5759 if (!is_long_mode(vcpu)) {
5760 nr &= 0xFFFFFFFF;
5761 a0 &= 0xFFFFFFFF;
5762 a1 &= 0xFFFFFFFF;
5763 a2 &= 0xFFFFFFFF;
5764 a3 &= 0xFFFFFFFF;
5765 }
5766
07708c4a
JK		 5767 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5768 ret = -KVM_EPERM;
5769 goto out;
5770 }
5771
8776e519 5772 switch (nr) {
b93463aa
AK		 5773 case KVM_HC_VAPIC_POLL_IRQ:
5774 ret = 0;
5775 break;
6aef266c
SV		 5776 case KVM_HC_KICK_CPU:
5777 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5778 ret = 0;
5779 break;
8776e519
HB		 5780 default:
5781 ret = -KVM_ENOSYS;
5782 break;
5783 }
07708c4a 5784out:
5fdbf976 5785 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5786 ++vcpu->stat.hypercalls;
2f333bcb 5787 return r;
8776e519
HB		 5788}
5789EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5790
b6785def 5791static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5792{
d6aa1000 5793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5794 char instruction[3];
5fdbf976 5795 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5796
8776e519 5797 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5798
9d74191a 5799 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5800}
5801
b6c7a5dc
HB		 5802/*
5803 * Check if userspace requested an interrupt window, and that the
5804 * interrupt window is open.
5805 *
5806 * No need to exit to userspace if we already have an interrupt queued.
5807 */
851ba692 5808static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5809{
8061823a 5810 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5811 vcpu->run->request_interrupt_window &&
5df56646 5812 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5813}
5814
851ba692 5815static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5816{
851ba692
AK		 5817 struct kvm_run *kvm_run = vcpu->run;
5818
91586a3b 5819 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5820 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5821 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5822 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5823 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5824 else
b6c7a5dc 5825 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5826 kvm_arch_interrupt_allowed(vcpu) &&
5827 !kvm_cpu_has_interrupt(vcpu) &&
5828 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5829}
5830
95ba8273
GN		 5831static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5832{
5833 int max_irr, tpr;
5834
5835 if (!kvm_x86_ops->update_cr8_intercept)
5836 return;
5837
88c808fd
AK		 5838 if (!vcpu->arch.apic)
5839 return;
5840
8db3baa2
GN		 5841 if (!vcpu->arch.apic->vapic_addr)
5842 max_irr = kvm_lapic_find_highest_irr(vcpu);
5843 else
5844 max_irr = -1;
95ba8273
GN		 5845
5846 if (max_irr != -1)
5847 max_irr >>= 4;
5848
5849 tpr = kvm_lapic_get_cr8(vcpu);
5850
5851 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5852}
5853
b6b8a145 5854static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5855{
b6b8a145
JK		 5856 int r;
5857
95ba8273 5858 /* try to reinject previous events if any */
b59bb7bd 5859 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5860 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5861 vcpu->arch.exception.has_error_code,
5862 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5863 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5864 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5865 vcpu->arch.exception.error_code,
5866 vcpu->arch.exception.reinject);
b6b8a145 5867 return 0;
b59bb7bd
GN		 5868 }
5869
95ba8273
GN		 5870 if (vcpu->arch.nmi_injected) {
5871 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5872 return 0;
95ba8273
GN		 5873 }
5874
5875 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5876 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5877 return 0;
5878 }
5879
5880 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5881 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5882 if (r != 0)
5883 return r;
95ba8273
GN		 5884 }
5885
5886 /* try to inject new event if pending */
5887 if (vcpu->arch.nmi_pending) {
5888 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5889 --vcpu->arch.nmi_pending;
95ba8273
GN		 5890 vcpu->arch.nmi_injected = true;
5891 kvm_x86_ops->set_nmi(vcpu);
5892 }
c7c9c56c 5893 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5894 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5895 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5896 false);
5897 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5898 }
5899 }
b6b8a145 5900 return 0;
95ba8273
GN		 5901}
5902
7460fb4a
AK		 5903static void process_nmi(struct kvm_vcpu *vcpu)
5904{
5905 unsigned limit = 2;
5906
5907 /*
5908 * x86 is limited to one NMI running, and one NMI pending after it.
5909 * If an NMI is already in progress, limit further NMIs to just one.
5910 * Otherwise, allow two (and we'll inject the first one immediately).
5911 */
5912 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5913 limit = 1;
5914
5915 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5916 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5917 kvm_make_request(KVM_REQ_EVENT, vcpu);
5918}
5919
3d81bc7e 5920static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5921{
5922 u64 eoi_exit_bitmap[4];
cf9e65b7 5923 u32 tmr[8];
c7c9c56c 5924
3d81bc7e
YZ		 5925 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5926 return;
c7c9c56c
YZ		 5927
5928 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5929 memset(tmr, 0, 32);
c7c9c56c 5930
cf9e65b7 5931 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5932 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5933 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5934}
5935
9357d939
TY		 5936/*
5937 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5938 * exiting to the userspace. Otherwise, the value will be returned to the
5939 * userspace.
5940 */
851ba692 5941static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5942{
5943 int r;
6a8b1d13 5944 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5945 vcpu->run->request_interrupt_window;
730dca42 5946 bool req_immediate_exit = false;
b6c7a5dc 5947
3e007509 5948 if (vcpu->requests) {
a8eeb04a 5949 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5950 kvm_mmu_unload(vcpu);
a8eeb04a 5951 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5952 __kvm_migrate_timers(vcpu);
d828199e
MT		 5953 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5954 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5955 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5956 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5957 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5958 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5959 if (unlikely(r))
5960 goto out;
5961 }
a8eeb04a 5962 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5963 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5964 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5965 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5966 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5967 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5968 r = 0;
5969 goto out;
5970 }
a8eeb04a 5971 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5972 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5973 r = 0;
5974 goto out;
5975 }
a8eeb04a 5976 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5977 vcpu->fpu_active = 0;
5978 kvm_x86_ops->fpu_deactivate(vcpu);
5979 }
af585b92
GN		 5980 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5981 /* Page is swapped out. Do synthetic halt */
5982 vcpu->arch.apf.halted = true;
5983 r = 1;
5984 goto out;
5985 }
c9aaa895
GC		 5986 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5987 record_steal_time(vcpu);
7460fb4a
AK		 5988 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5989 process_nmi(vcpu);
f5132b01
GN		 5990 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5991 kvm_handle_pmu_event(vcpu);
5992 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5993 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5994 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5995 vcpu_scan_ioapic(vcpu);
2f52d58c 5996 }
b93463aa 5997
b463a6f7 5998 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5999 kvm_apic_accept_events(vcpu);
6000 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6001 r = 1;
6002 goto out;
6003 }
6004
b6b8a145
JK		 6005 if (inject_pending_event(vcpu, req_int_win) != 0)
6006 req_immediate_exit = true;
b463a6f7 6007 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6008 else if (vcpu->arch.nmi_pending)
c9a7953f 6009 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6010 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6011 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6012
6013 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6014 /*
6015 * Update architecture specific hints for APIC
6016 * virtual interrupt delivery.
6017 */
6018 if (kvm_x86_ops->hwapic_irr_update)
6019 kvm_x86_ops->hwapic_irr_update(vcpu,
6020 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6021 update_cr8_intercept(vcpu);
6022 kvm_lapic_sync_to_vapic(vcpu);
6023 }
6024 }
6025
d8368af8
AK		 6026 r = kvm_mmu_reload(vcpu);
6027 if (unlikely(r)) {
d905c069 6028 goto cancel_injection;
d8368af8
AK		 6029 }
6030
b6c7a5dc
HB		 6031 preempt_disable();
6032
6033 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6034 if (vcpu->fpu_active)
6035 kvm_load_guest_fpu(vcpu);
2acf923e 6036 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6037
6b7e2d09
XG		 6038 vcpu->mode = IN_GUEST_MODE;
6039
01b71917
MT		 6040 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6041
6b7e2d09
XG		 6042 /* We should set ->mode before check ->requests,
6043 * see the comment in make_all_cpus_request.
6044 */
01b71917 6045 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6046
d94e1dc9 6047 local_irq_disable();
32f88400 6048
6b7e2d09 6049 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6050 || need_resched() || signal_pending(current)) {
6b7e2d09 6051 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6052 smp_wmb();
6c142801
AK		 6053 local_irq_enable();
6054 preempt_enable();
01b71917 6055 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6056 r = 1;
d905c069 6057 goto cancel_injection;
6c142801
AK		 6058 }
6059
d6185f20
NHE		 6060 if (req_immediate_exit)
6061 smp_send_reschedule(vcpu->cpu);
6062
b6c7a5dc
HB		 6063 kvm_guest_enter();
6064
42dbaa5a 6065 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6066 set_debugreg(0, 7);
6067 set_debugreg(vcpu->arch.eff_db[0], 0);
6068 set_debugreg(vcpu->arch.eff_db[1], 1);
6069 set_debugreg(vcpu->arch.eff_db[2], 2);
6070 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6071 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6072 }
b6c7a5dc 6073
229456fc 6074 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6075 kvm_x86_ops->run(vcpu);
b6c7a5dc 6076
c77fb5fe
PB		 6077 /*
6078 * Do this here before restoring debug registers on the host. And
6079 * since we do this before handling the vmexit, a DR access vmexit
6080 * can (a) read the correct value of the debug registers, (b) set
6081 * KVM_DEBUGREG_WONT_EXIT again.
6082 */
6083 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6084 int i;
6085
6086 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6087 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6088 for (i = 0; i < KVM_NR_DB_REGS; i++)
6089 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6090 }
6091
24f1e32c
FW		 6092 /*
6093 * If the guest has used debug registers, at least dr7
6094 * will be disabled while returning to the host.
6095 * If we don't have active breakpoints in the host, we don't
6096 * care about the messed up debug address registers. But if
6097 * we have some of them active, restore the old state.
6098 */
59d8eb53 6099 if (hw_breakpoint_active())
24f1e32c 6100 hw_breakpoint_restore();
42dbaa5a 6101
886b470c
MT		 6102 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6103 native_read_tsc());
1d5f066e 6104
6b7e2d09 6105 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6106 smp_wmb();
a547c6db
YZ		 6107
6108 /* Interrupt is enabled by handle_external_intr() */
6109 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6110
6111 ++vcpu->stat.exits;
6112
6113 /*
6114 * We must have an instruction between local_irq_enable() and
6115 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6116 * the interrupt shadow. The stat.exits increment will do nicely.
6117 * But we need to prevent reordering, hence this barrier():
6118 */
6119 barrier();
6120
6121 kvm_guest_exit();
6122
6123 preempt_enable();
6124
f656ce01 6125 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6126
b6c7a5dc
HB		 6127 /*
6128 * Profile KVM exit RIPs:
6129 */
6130 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6131 unsigned long rip = kvm_rip_read(vcpu);
6132 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6133 }
6134
cc578287
ZA		 6135 if (unlikely(vcpu->arch.tsc_always_catchup))
6136 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6137
5cfb1d5a
MT		 6138 if (vcpu->arch.apic_attention)
6139 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6140
851ba692 6141 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6142 return r;
6143
6144cancel_injection:
6145 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6146 if (unlikely(vcpu->arch.apic_attention))
6147 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6148out:
6149 return r;
6150}
b6c7a5dc 6151
09cec754 6152
851ba692 6153static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6154{
6155 int r;
f656ce01 6156 struct kvm *kvm = vcpu->kvm;
d7690175 6157
f656ce01 6158 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6159
6160 r = 1;
6161 while (r > 0) {
af585b92
GN		 6162 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6163 !vcpu->arch.apf.halted)
851ba692 6164 r = vcpu_enter_guest(vcpu);
d7690175 6165 else {
f656ce01 6166 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6167 kvm_vcpu_block(vcpu);
f656ce01 6168 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6169 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6170 kvm_apic_accept_events(vcpu);
09cec754
GN		 6171 switch(vcpu->arch.mp_state) {
6172 case KVM_MP_STATE_HALTED:
6aef266c 6173 vcpu->arch.pv.pv_unhalted = false;
d7690175 6174 vcpu->arch.mp_state =
09cec754
GN		 6175 KVM_MP_STATE_RUNNABLE;
6176 case KVM_MP_STATE_RUNNABLE:
af585b92 6177 vcpu->arch.apf.halted = false;
09cec754 6178 break;
66450a21
JK		 6179 case KVM_MP_STATE_INIT_RECEIVED:
6180 break;
09cec754
GN		 6181 default:
6182 r = -EINTR;
6183 break;
6184 }
6185 }
d7690175
MT		 6186 }
6187
09cec754
GN		 6188 if (r <= 0)
6189 break;
6190
6191 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6192 if (kvm_cpu_has_pending_timer(vcpu))
6193 kvm_inject_pending_timer_irqs(vcpu);
6194
851ba692 6195 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6196 r = -EINTR;
851ba692 6197 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6198 ++vcpu->stat.request_irq_exits;
6199 }
af585b92
GN		 6200
6201 kvm_check_async_pf_completion(vcpu);
6202
09cec754
GN		 6203 if (signal_pending(current)) {
6204 r = -EINTR;
851ba692 6205 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6206 ++vcpu->stat.signal_exits;
6207 }
6208 if (need_resched()) {
f656ce01 6209 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6210 cond_resched();
f656ce01 6211 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6212 }
b6c7a5dc
HB		 6213 }
6214
f656ce01 6215 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6216
6217 return r;
6218}
6219
716d51ab
GN		 6220static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6221{
6222 int r;
6223 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6224 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6225 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6226 if (r != EMULATE_DONE)
6227 return 0;
6228 return 1;
6229}
6230
6231static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6232{
6233 BUG_ON(!vcpu->arch.pio.count);
6234
6235 return complete_emulated_io(vcpu);
6236}
6237
f78146b0
AK		 6238/*
6239 * Implements the following, as a state machine:
6240 *
6241 * read:
6242 * for each fragment
87da7e66
XG		 6243 * for each mmio piece in the fragment
6244 * write gpa, len
6245 * exit
6246 * copy data
f78146b0
AK		 6247 * execute insn
6248 *
6249 * write:
6250 * for each fragment
87da7e66
XG		 6251 * for each mmio piece in the fragment
6252 * write gpa, len
6253 * copy data
6254 * exit
f78146b0 6255 */
716d51ab 6256static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6257{
6258 struct kvm_run *run = vcpu->run;
f78146b0 6259 struct kvm_mmio_fragment *frag;
87da7e66 6260 unsigned len;
5287f194 6261
716d51ab 6262 BUG_ON(!vcpu->mmio_needed);
5287f194 6263
716d51ab 6264 /* Complete previous fragment */
87da7e66
XG		 6265 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6266 len = min(8u, frag->len);
716d51ab 6267 if (!vcpu->mmio_is_write)
87da7e66
XG		 6268 memcpy(frag->data, run->mmio.data, len);
6269
6270 if (frag->len <= 8) {
6271 /* Switch to the next fragment. */
6272 frag++;
6273 vcpu->mmio_cur_fragment++;
6274 } else {
6275 /* Go forward to the next mmio piece. */
6276 frag->data += len;
6277 frag->gpa += len;
6278 frag->len -= len;
6279 }
6280
a08d3b3b 6281 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6282 vcpu->mmio_needed = 0;
0912c977
PB		 6283
6284 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6285 if (vcpu->mmio_is_write)
716d51ab
GN		 6286 return 1;
6287 vcpu->mmio_read_completed = 1;
6288 return complete_emulated_io(vcpu);
6289 }
87da7e66 6290
716d51ab
GN		 6291 run->exit_reason = KVM_EXIT_MMIO;
6292 run->mmio.phys_addr = frag->gpa;
6293 if (vcpu->mmio_is_write)
87da7e66
XG		 6294 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6295 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6296 run->mmio.is_write = vcpu->mmio_is_write;
6297 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6298 return 0;
5287f194
AK		 6299}
6300
716d51ab 6301
b6c7a5dc
HB		 6302int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6303{
6304 int r;
6305 sigset_t sigsaved;
6306
e5c30142
AK		 6307 if (!tsk_used_math(current) && init_fpu(current))
6308 return -ENOMEM;
6309
ac9f6dc0
AK		 6310 if (vcpu->sigset_active)
6311 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6312
a4535290 6313 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6314 kvm_vcpu_block(vcpu);
66450a21 6315 kvm_apic_accept_events(vcpu);
d7690175 6316 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6317 r = -EAGAIN;
6318 goto out;
b6c7a5dc
HB		 6319 }
6320
b6c7a5dc 6321 /* re-sync apic's tpr */
eea1cff9
AP		 6322 if (!irqchip_in_kernel(vcpu->kvm)) {
6323 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6324 r = -EINVAL;
6325 goto out;
6326 }
6327 }
b6c7a5dc 6328
716d51ab
GN		 6329 if (unlikely(vcpu->arch.complete_userspace_io)) {
6330 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6331 vcpu->arch.complete_userspace_io = NULL;
6332 r = cui(vcpu);
6333 if (r <= 0)
6334 goto out;
6335 } else
6336 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6337
851ba692 6338 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6339
6340out:
f1d86e46 6341 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6342 if (vcpu->sigset_active)
6343 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6344
b6c7a5dc
HB		 6345 return r;
6346}
6347
6348int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6349{
7ae441ea
GN		 6350 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6351 /*
6352 * We are here if userspace calls get_regs() in the middle of
6353 * instruction emulation. Registers state needs to be copied
4a969980 6354 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6355 * that usually, but some bad designed PV devices (vmware
6356 * backdoor interface) need this to work
6357 */
dd856efa 6358 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6359 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6360 }
5fdbf976
MT		 6361 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6362 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6363 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6364 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6365 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6366 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6367 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6368 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6369#ifdef CONFIG_X86_64
5fdbf976
MT		 6370 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6371 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6372 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6373 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6374 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6375 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6376 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6377 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6378#endif
6379
5fdbf976 6380 regs->rip = kvm_rip_read(vcpu);
91586a3b 6381 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6382
b6c7a5dc
HB		 6383 return 0;
6384}
6385
6386int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6387{
7ae441ea
GN		 6388 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6389 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6390
5fdbf976
MT		 6391 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6392 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6393 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6394 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6395 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6396 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6397 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6398 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6399#ifdef CONFIG_X86_64
5fdbf976
MT		 6400 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6401 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6402 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6403 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6404 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6405 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6406 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6407 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6408#endif
6409
5fdbf976 6410 kvm_rip_write(vcpu, regs->rip);
91586a3b 6411 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6412
b4f14abd
JK		 6413 vcpu->arch.exception.pending = false;
6414
3842d135
AK		 6415 kvm_make_request(KVM_REQ_EVENT, vcpu);
6416
b6c7a5dc
HB		 6417 return 0;
6418}
6419
b6c7a5dc
HB		 6420void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6421{
6422 struct kvm_segment cs;
6423
3e6e0aab 6424 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6425 *db = cs.db;
6426 *l = cs.l;
6427}
6428EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6429
6430int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6431 struct kvm_sregs *sregs)
6432{
89a27f4d 6433 struct desc_ptr dt;
b6c7a5dc 6434
3e6e0aab
GT		 6435 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6436 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6437 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6438 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6439 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6440 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6441
3e6e0aab
GT		 6442 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6443 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6444
6445 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6446 sregs->idt.limit = dt.size;
6447 sregs->idt.base = dt.address;
b6c7a5dc 6448 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6449 sregs->gdt.limit = dt.size;
6450 sregs->gdt.base = dt.address;
b6c7a5dc 6451
4d4ec087 6452 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6453 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6454 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6455 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6456 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6457 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6458 sregs->apic_base = kvm_get_apic_base(vcpu);
6459
923c61bb 6460 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6461
36752c9b 6462 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6463 set_bit(vcpu->arch.interrupt.nr,
6464 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6465
b6c7a5dc
HB		 6466 return 0;
6467}
6468
62d9f0db
MT		 6469int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6470 struct kvm_mp_state *mp_state)
6471{
66450a21 6472 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6473 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6474 vcpu->arch.pv.pv_unhalted)
6475 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6476 else
6477 mp_state->mp_state = vcpu->arch.mp_state;
6478
62d9f0db
MT		 6479 return 0;
6480}
6481
6482int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6483 struct kvm_mp_state *mp_state)
6484{
66450a21
JK		 6485 if (!kvm_vcpu_has_lapic(vcpu) &&
6486 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6487 return -EINVAL;
6488
6489 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6490 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6491 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6492 } else
6493 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6494 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6495 return 0;
6496}
6497
7f3d35fd
KW		 6498int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6499 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6500{
9d74191a 6501 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6502 int ret;
e01c2426 6503
8ec4722d 6504 init_emulate_ctxt(vcpu);
c697518a 6505
7f3d35fd 6506 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6507 has_error_code, error_code);
c697518a 6508
c697518a 6509 if (ret)
19d04437 6510 return EMULATE_FAIL;
37817f29 6511
9d74191a
TY		 6512 kvm_rip_write(vcpu, ctxt->eip);
6513 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6514 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6515 return EMULATE_DONE;
37817f29
IE		 6516}
6517EXPORT_SYMBOL_GPL(kvm_task_switch);
6518
b6c7a5dc
HB		 6519int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6520 struct kvm_sregs *sregs)
6521{
58cb628d 6522 struct msr_data apic_base_msr;
b6c7a5dc 6523 int mmu_reset_needed = 0;
63f42e02 6524 int pending_vec, max_bits, idx;
89a27f4d 6525 struct desc_ptr dt;
b6c7a5dc 6526
6d1068b3
PM		 6527 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6528 return -EINVAL;
6529
89a27f4d
GN		 6530 dt.size = sregs->idt.limit;
6531 dt.address = sregs->idt.base;
b6c7a5dc 6532 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6533 dt.size = sregs->gdt.limit;
6534 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6535 kvm_x86_ops->set_gdt(vcpu, &dt);
6536
ad312c7c 6537 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6538 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6539 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6540 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6541
2d3ad1f4 6542 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6543
f6801dff 6544 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6545 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6546 apic_base_msr.data = sregs->apic_base;
6547 apic_base_msr.host_initiated = true;
6548 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6549
4d4ec087 6550 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6551 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6552 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6553
fc78f519 6554 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6555 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6556 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6557 kvm_update_cpuid(vcpu);
63f42e02
XG		 6558
6559 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6560 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6561 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6562 mmu_reset_needed = 1;
6563 }
63f42e02 6564 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6565
6566 if (mmu_reset_needed)
6567 kvm_mmu_reset_context(vcpu);
6568
a50abc3b 6569 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6570 pending_vec = find_first_bit(
6571 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6572 if (pending_vec < max_bits) {
66fd3f7f 6573 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6574 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6575 }
6576
3e6e0aab
GT		 6577 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6578 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6579 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6580 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6581 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6582 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6583
3e6e0aab
GT		 6584 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6585 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6586
5f0269f5
ME		 6587 update_cr8_intercept(vcpu);
6588
9c3e4aab 6589 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6590 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6591 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6592 !is_protmode(vcpu))
9c3e4aab
MT		 6593 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6594
3842d135
AK		 6595 kvm_make_request(KVM_REQ_EVENT, vcpu);
6596
b6c7a5dc
HB		 6597 return 0;
6598}
6599
d0bfb940
JK		 6600int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6601 struct kvm_guest_debug *dbg)
b6c7a5dc 6602{
355be0b9 6603 unsigned long rflags;
ae675ef0 6604 int i, r;
b6c7a5dc 6605
4f926bf2
JK		 6606 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6607 r = -EBUSY;
6608 if (vcpu->arch.exception.pending)
2122ff5e 6609 goto out;
4f926bf2
JK		 6610 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6611 kvm_queue_exception(vcpu, DB_VECTOR);
6612 else
6613 kvm_queue_exception(vcpu, BP_VECTOR);
6614 }
6615
91586a3b
JK		 6616 /*
6617 * Read rflags as long as potentially injected trace flags are still
6618 * filtered out.
6619 */
6620 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6621
6622 vcpu->guest_debug = dbg->control;
6623 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6624 vcpu->guest_debug = 0;
6625
6626 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6627 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6628 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6629 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6630 } else {
6631 for (i = 0; i < KVM_NR_DB_REGS; i++)
6632 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6633 }
c8639010 6634 kvm_update_dr7(vcpu);
ae675ef0 6635
f92653ee
JK		 6636 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6637 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6638 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6639
91586a3b
JK		 6640 /*
6641 * Trigger an rflags update that will inject or remove the trace
6642 * flags.
6643 */
6644 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6645
c8639010 6646 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6647
4f926bf2 6648 r = 0;
d0bfb940 6649
2122ff5e 6650out:
b6c7a5dc
HB		 6651
6652 return r;
6653}
6654
8b006791
ZX		 6655/*
6656 * Translate a guest virtual address to a guest physical address.
6657 */
6658int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6659 struct kvm_translation *tr)
6660{
6661 unsigned long vaddr = tr->linear_address;
6662 gpa_t gpa;
f656ce01 6663 int idx;
8b006791 6664
f656ce01 6665 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6666 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6667 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6668 tr->physical_address = gpa;
6669 tr->valid = gpa != UNMAPPED_GVA;
6670 tr->writeable = 1;
6671 tr->usermode = 0;
8b006791
ZX		 6672
6673 return 0;
6674}
6675
d0752060
HB		 6676int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6677{
98918833
SY		 6678 struct i387_fxsave_struct *fxsave =
6679 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6680
d0752060
HB		 6681 memcpy(fpu->fpr, fxsave->st_space, 128);
6682 fpu->fcw = fxsave->cwd;
6683 fpu->fsw = fxsave->swd;
6684 fpu->ftwx = fxsave->twd;
6685 fpu->last_opcode = fxsave->fop;
6686 fpu->last_ip = fxsave->rip;
6687 fpu->last_dp = fxsave->rdp;
6688 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6689
d0752060
HB		 6690 return 0;
6691}
6692
6693int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6694{
98918833
SY		 6695 struct i387_fxsave_struct *fxsave =
6696 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6697
d0752060
HB		 6698 memcpy(fxsave->st_space, fpu->fpr, 128);
6699 fxsave->cwd = fpu->fcw;
6700 fxsave->swd = fpu->fsw;
6701 fxsave->twd = fpu->ftwx;
6702 fxsave->fop = fpu->last_opcode;
6703 fxsave->rip = fpu->last_ip;
6704 fxsave->rdp = fpu->last_dp;
6705 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6706
d0752060
HB		 6707 return 0;
6708}
6709
10ab25cd 6710int fx_init(struct kvm_vcpu *vcpu)
d0752060 6711{
10ab25cd
JK		 6712 int err;
6713
6714 err = fpu_alloc(&vcpu->arch.guest_fpu);
6715 if (err)
6716 return err;
6717
98918833 6718 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6719
2acf923e
DC		 6720 /*
6721 * Ensure guest xcr0 is valid for loading
6722 */
6723 vcpu->arch.xcr0 = XSTATE_FP;
6724
ad312c7c 6725 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6726
6727 return 0;
d0752060
HB		 6728}
6729EXPORT_SYMBOL_GPL(fx_init);
6730
98918833
SY		 6731static void fx_free(struct kvm_vcpu *vcpu)
6732{
6733 fpu_free(&vcpu->arch.guest_fpu);
6734}
6735
d0752060
HB		 6736void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6737{
2608d7a1 6738 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6739 return;
6740
2acf923e
DC		 6741 /*
6742 * Restore all possible states in the guest,
6743 * and assume host would use all available bits.
6744 * Guest xcr0 would be loaded later.
6745 */
6746 kvm_put_guest_xcr0(vcpu);
d0752060 6747 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6748 __kernel_fpu_begin();
98918833 6749 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6750 trace_kvm_fpu(1);
d0752060 6751}
d0752060
HB		 6752
6753void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6754{
2acf923e
DC		 6755 kvm_put_guest_xcr0(vcpu);
6756
d0752060
HB		 6757 if (!vcpu->guest_fpu_loaded)
6758 return;
6759
6760 vcpu->guest_fpu_loaded = 0;
98918833 6761 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6762 __kernel_fpu_end();
f096ed85 6763 ++vcpu->stat.fpu_reload;
a8eeb04a 6764 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6765 trace_kvm_fpu(0);
d0752060 6766}
e9b11c17
ZX		 6767
6768void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6769{
12f9a48f 6770 kvmclock_reset(vcpu);
7f1ea208 6771
f5f48ee1 6772 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6773 fx_free(vcpu);
e9b11c17
ZX		 6774 kvm_x86_ops->vcpu_free(vcpu);
6775}
6776
6777struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6778 unsigned int id)
6779{
6755bae8
ZA		 6780 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6781 printk_once(KERN_WARNING
6782 "kvm: SMP vm created on host with unstable TSC; "
6783 "guest TSC will not be reliable\n");
26e5215f
AK		 6784 return kvm_x86_ops->vcpu_create(kvm, id);
6785}
e9b11c17 6786
26e5215f
AK		 6787int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6788{
6789 int r;
e9b11c17 6790
0bed3b56 6791 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6792 r = vcpu_load(vcpu);
6793 if (r)
6794 return r;
57f252f2 6795 kvm_vcpu_reset(vcpu);
8a3c1a33 6796 kvm_mmu_setup(vcpu);
e9b11c17 6797 vcpu_put(vcpu);
e9b11c17 6798
26e5215f 6799 return r;
e9b11c17
ZX		 6800}
6801
42897d86
MT		 6802int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6803{
6804 int r;
8fe8ab46 6805 struct msr_data msr;
332967a3 6806 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6807
6808 r = vcpu_load(vcpu);
6809 if (r)
6810 return r;
8fe8ab46
WA		 6811 msr.data = 0x0;
6812 msr.index = MSR_IA32_TSC;
6813 msr.host_initiated = true;
6814 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6815 vcpu_put(vcpu);
6816
332967a3
AJ		 6817 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6818 KVMCLOCK_SYNC_PERIOD);
6819
42897d86
MT		 6820 return r;
6821}
6822
d40ccc62 6823void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6824{
9fc77441 6825 int r;
344d9588
GN		 6826 vcpu->arch.apf.msr_val = 0;
6827
9fc77441
MT		 6828 r = vcpu_load(vcpu);
6829 BUG_ON(r);
e9b11c17
ZX		 6830 kvm_mmu_unload(vcpu);
6831 vcpu_put(vcpu);
6832
98918833 6833 fx_free(vcpu);
e9b11c17
ZX		 6834 kvm_x86_ops->vcpu_free(vcpu);
6835}
6836
66450a21 6837void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6838{
7460fb4a
AK		 6839 atomic_set(&vcpu->arch.nmi_queued, 0);
6840 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6841 vcpu->arch.nmi_injected = false;
6842
42dbaa5a
JK		 6843 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6844 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6845 kvm_update_dr6(vcpu);
42dbaa5a 6846 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6847 kvm_update_dr7(vcpu);
42dbaa5a 6848
3842d135 6849 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6850 vcpu->arch.apf.msr_val = 0;
c9aaa895 6851 vcpu->arch.st.msr_val = 0;
3842d135 6852
12f9a48f
GC		 6853 kvmclock_reset(vcpu);
6854
af585b92
GN		 6855 kvm_clear_async_pf_completion_queue(vcpu);
6856 kvm_async_pf_hash_reset(vcpu);
6857 vcpu->arch.apf.halted = false;
3842d135 6858
f5132b01
GN		 6859 kvm_pmu_reset(vcpu);
6860
66f7b72e
JS		 6861 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6862 vcpu->arch.regs_avail = ~0;
6863 vcpu->arch.regs_dirty = ~0;
6864
57f252f2 6865 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6866}
6867
66450a21
JK		 6868void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6869{
6870 struct kvm_segment cs;
6871
6872 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6873 cs.selector = vector << 8;
6874 cs.base = vector << 12;
6875 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6876 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6877}
6878
10474ae8 6879int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6880{
ca84d1a2
ZA		 6881 struct kvm *kvm;
6882 struct kvm_vcpu *vcpu;
6883 int i;
0dd6a6ed
ZA		 6884 int ret;
6885 u64 local_tsc;
6886 u64 max_tsc = 0;
6887 bool stable, backwards_tsc = false;
18863bdd
AK		 6888
6889 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6890 ret = kvm_x86_ops->hardware_enable(garbage);
6891 if (ret != 0)
6892 return ret;
6893
6894 local_tsc = native_read_tsc();
6895 stable = !check_tsc_unstable();
6896 list_for_each_entry(kvm, &vm_list, vm_list) {
6897 kvm_for_each_vcpu(i, vcpu, kvm) {
6898 if (!stable && vcpu->cpu == smp_processor_id())
6899 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6900 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6901 backwards_tsc = true;
6902 if (vcpu->arch.last_host_tsc > max_tsc)
6903 max_tsc = vcpu->arch.last_host_tsc;
6904 }
6905 }
6906 }
6907
6908 /*
6909 * Sometimes, even reliable TSCs go backwards. This happens on
6910 * platforms that reset TSC during suspend or hibernate actions, but
6911 * maintain synchronization. We must compensate. Fortunately, we can
6912 * detect that condition here, which happens early in CPU bringup,
6913 * before any KVM threads can be running. Unfortunately, we can't
6914 * bring the TSCs fully up to date with real time, as we aren't yet far
6915 * enough into CPU bringup that we know how much real time has actually
6916 * elapsed; our helper function, get_kernel_ns() will be using boot
6917 * variables that haven't been updated yet.
6918 *
6919 * So we simply find the maximum observed TSC above, then record the
6920 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6921 * the adjustment will be applied. Note that we accumulate
6922 * adjustments, in case multiple suspend cycles happen before some VCPU
6923 * gets a chance to run again. In the event that no KVM threads get a
6924 * chance to run, we will miss the entire elapsed period, as we'll have
6925 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6926 * loose cycle time. This isn't too big a deal, since the loss will be
6927 * uniform across all VCPUs (not to mention the scenario is extremely
6928 * unlikely). It is possible that a second hibernate recovery happens
6929 * much faster than a first, causing the observed TSC here to be
6930 * smaller; this would require additional padding adjustment, which is
6931 * why we set last_host_tsc to the local tsc observed here.
6932 *
6933 * N.B. - this code below runs only on platforms with reliable TSC,
6934 * as that is the only way backwards_tsc is set above. Also note
6935 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6936 * have the same delta_cyc adjustment applied if backwards_tsc
6937 * is detected. Note further, this adjustment is only done once,
6938 * as we reset last_host_tsc on all VCPUs to stop this from being
6939 * called multiple times (one for each physical CPU bringup).
6940 *
4a969980 6941 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6942 * will be compensated by the logic in vcpu_load, which sets the TSC to
6943 * catchup mode. This will catchup all VCPUs to real time, but cannot
6944 * guarantee that they stay in perfect synchronization.
6945 */
6946 if (backwards_tsc) {
6947 u64 delta_cyc = max_tsc - local_tsc;
6948 list_for_each_entry(kvm, &vm_list, vm_list) {
6949 kvm_for_each_vcpu(i, vcpu, kvm) {
6950 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6951 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6952 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6953 &vcpu->requests);
0dd6a6ed
ZA		 6954 }
6955
6956 /*
6957 * We have to disable TSC offset matching.. if you were
6958 * booting a VM while issuing an S4 host suspend....
6959 * you may have some problem. Solving this issue is
6960 * left as an exercise to the reader.
6961 */
6962 kvm->arch.last_tsc_nsec = 0;
6963 kvm->arch.last_tsc_write = 0;
6964 }
6965
6966 }
6967 return 0;
e9b11c17
ZX		 6968}
6969
6970void kvm_arch_hardware_disable(void *garbage)
6971{
6972 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6973 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6974}
6975
6976int kvm_arch_hardware_setup(void)
6977{
6978 return kvm_x86_ops->hardware_setup();
6979}
6980
6981void kvm_arch_hardware_unsetup(void)
6982{
6983 kvm_x86_ops->hardware_unsetup();
6984}
6985
6986void kvm_arch_check_processor_compat(void *rtn)
6987{
6988 kvm_x86_ops->check_processor_compatibility(rtn);
6989}
6990
3e515705
AK		 6991bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6992{
6993 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6994}
6995
54e9818f
GN		 6996struct static_key kvm_no_apic_vcpu __read_mostly;
6997
e9b11c17
ZX		 6998int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6999{
7000 struct page *page;
7001 struct kvm *kvm;
7002 int r;
7003
7004 BUG_ON(vcpu->kvm == NULL);
7005 kvm = vcpu->kvm;
7006
6aef266c 7007 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7008 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7009 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7010 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7011 else
a4535290 7012 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7013
7014 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7015 if (!page) {
7016 r = -ENOMEM;
7017 goto fail;
7018 }
ad312c7c 7019 vcpu->arch.pio_data = page_address(page);
e9b11c17 7020
cc578287 7021 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7022
e9b11c17
ZX		 7023 r = kvm_mmu_create(vcpu);
7024 if (r < 0)
7025 goto fail_free_pio_data;
7026
7027 if (irqchip_in_kernel(kvm)) {
7028 r = kvm_create_lapic(vcpu);
7029 if (r < 0)
7030 goto fail_mmu_destroy;
54e9818f
GN		 7031 } else
7032 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7033
890ca9ae
HY		 7034 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7035 GFP_KERNEL);
7036 if (!vcpu->arch.mce_banks) {
7037 r = -ENOMEM;
443c39bc 7038 goto fail_free_lapic;
890ca9ae
HY		 7039 }
7040 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7041
f1797359
WY		 7042 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7043 r = -ENOMEM;
f5f48ee1 7044 goto fail_free_mce_banks;
f1797359 7045 }
f5f48ee1 7046
66f7b72e
JS		 7047 r = fx_init(vcpu);
7048 if (r)
7049 goto fail_free_wbinvd_dirty_mask;
7050
ba904635 7051 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7052 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7053
7054 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7055 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7056
af585b92 7057 kvm_async_pf_hash_reset(vcpu);
f5132b01 7058 kvm_pmu_init(vcpu);
af585b92 7059
e9b11c17 7060 return 0;
66f7b72e
JS		 7061fail_free_wbinvd_dirty_mask:
7062 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7063fail_free_mce_banks:
7064 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7065fail_free_lapic:
7066 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7067fail_mmu_destroy:
7068 kvm_mmu_destroy(vcpu);
7069fail_free_pio_data:
ad312c7c 7070 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7071fail:
7072 return r;
7073}
7074
7075void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7076{
f656ce01
MT		 7077 int idx;
7078
f5132b01 7079 kvm_pmu_destroy(vcpu);
36cb93fd 7080 kfree(vcpu->arch.mce_banks);
e9b11c17 7081 kvm_free_lapic(vcpu);
f656ce01 7082 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7083 kvm_mmu_destroy(vcpu);
f656ce01 7084 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7085 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7086 if (!irqchip_in_kernel(vcpu->kvm))
7087 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7088}
d19a9cd2 7089
e08b9637 7090int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7091{
e08b9637
CO		 7092 if (type)
7093 return -EINVAL;
7094
f05e70ac 7095 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7096 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7097 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7098 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7099
5550af4d
SY		 7100 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7101 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7102 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7103 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7104 &kvm->arch.irq_sources_bitmap);
5550af4d 7105
038f8c11 7106 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7107 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7108 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7109
7110 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7111
7e44e449 7112 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7113 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7114
d89f5eff 7115 return 0;
d19a9cd2
ZX		 7116}
7117
7118static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7119{
9fc77441
MT		 7120 int r;
7121 r = vcpu_load(vcpu);
7122 BUG_ON(r);
d19a9cd2
ZX		 7123 kvm_mmu_unload(vcpu);
7124 vcpu_put(vcpu);
7125}
7126
7127static void kvm_free_vcpus(struct kvm *kvm)
7128{
7129 unsigned int i;
988a2cae 7130 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7131
7132 /*
7133 * Unpin any mmu pages first.
7134 */
af585b92
GN		 7135 kvm_for_each_vcpu(i, vcpu, kvm) {
7136 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7137 kvm_unload_vcpu_mmu(vcpu);
af585b92 7138 }
988a2cae
GN		 7139 kvm_for_each_vcpu(i, vcpu, kvm)
7140 kvm_arch_vcpu_free(vcpu);
7141
7142 mutex_lock(&kvm->lock);
7143 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7144 kvm->vcpus[i] = NULL;
d19a9cd2 7145
988a2cae
GN		 7146 atomic_set(&kvm->online_vcpus, 0);
7147 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7148}
7149
ad8ba2cd
SY		 7150void kvm_arch_sync_events(struct kvm *kvm)
7151{
332967a3 7152 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7153 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7154 kvm_free_all_assigned_devices(kvm);
aea924f6 7155 kvm_free_pit(kvm);
ad8ba2cd
SY		 7156}
7157
d19a9cd2
ZX		 7158void kvm_arch_destroy_vm(struct kvm *kvm)
7159{
27469d29
AH		 7160 if (current->mm == kvm->mm) {
7161 /*
7162 * Free memory regions allocated on behalf of userspace,
7163 * unless the the memory map has changed due to process exit
7164 * or fd copying.
7165 */
7166 struct kvm_userspace_memory_region mem;
7167 memset(&mem, 0, sizeof(mem));
7168 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7169 kvm_set_memory_region(kvm, &mem);
7170
7171 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7172 kvm_set_memory_region(kvm, &mem);
7173
7174 mem.slot = TSS_PRIVATE_MEMSLOT;
7175 kvm_set_memory_region(kvm, &mem);
7176 }
6eb55818 7177 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7178 kfree(kvm->arch.vpic);
7179 kfree(kvm->arch.vioapic);
d19a9cd2 7180 kvm_free_vcpus(kvm);
3d45830c
AK		 7181 if (kvm->arch.apic_access_page)
7182 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7183 if (kvm->arch.ept_identity_pagetable)
7184 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7185 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7186}
0de10343 7187
5587027c 7188void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7189 struct kvm_memory_slot *dont)
7190{
7191 int i;
7192
d89cc617
TY		 7193 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7194 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7195 kvm_kvfree(free->arch.rmap[i]);
7196 free->arch.rmap[i] = NULL;
77d11309 7197 }
d89cc617
TY		 7198 if (i == 0)
7199 continue;
7200
7201 if (!dont || free->arch.lpage_info[i - 1] !=
7202 dont->arch.lpage_info[i - 1]) {
7203 kvm_kvfree(free->arch.lpage_info[i - 1]);
7204 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7205 }
7206 }
7207}
7208
5587027c
AK		 7209int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7210 unsigned long npages)
db3fe4eb
TY		 7211{
7212 int i;
7213
d89cc617 7214 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7215 unsigned long ugfn;
7216 int lpages;
d89cc617 7217 int level = i + 1;
db3fe4eb
TY		 7218
7219 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7220 slot->base_gfn, level) + 1;
7221
d89cc617
TY		 7222 slot->arch.rmap[i] =
7223 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7224 if (!slot->arch.rmap[i])
77d11309 7225 goto out_free;
d89cc617
TY		 7226 if (i == 0)
7227 continue;
77d11309 7228
d89cc617
TY		 7229 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7230 sizeof(*slot->arch.lpage_info[i - 1]));
7231 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7232 goto out_free;
7233
7234 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7235 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7236 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7237 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7238 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7239 /*
7240 * If the gfn and userspace address are not aligned wrt each
7241 * other, or if explicitly asked to, disable large page
7242 * support for this slot
7243 */
7244 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7245 !kvm_largepages_enabled()) {
7246 unsigned long j;
7247
7248 for (j = 0; j < lpages; ++j)
d89cc617 7249 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7250 }
7251 }
7252
7253 return 0;
7254
7255out_free:
d89cc617
TY		 7256 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7257 kvm_kvfree(slot->arch.rmap[i]);
7258 slot->arch.rmap[i] = NULL;
7259 if (i == 0)
7260 continue;
7261
7262 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7263 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7264 }
7265 return -ENOMEM;
7266}
7267
e59dbe09
TY		 7268void kvm_arch_memslots_updated(struct kvm *kvm)
7269{
e6dff7d1
TY		 7270 /*
7271 * memslots->generation has been incremented.
7272 * mmio generation may have reached its maximum value.
7273 */
7274 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7275}
7276
f7784b8e
MT		 7277int kvm_arch_prepare_memory_region(struct kvm *kvm,
7278 struct kvm_memory_slot *memslot,
f7784b8e 7279 struct kvm_userspace_memory_region *mem,
7b6195a9 7280 enum kvm_mr_change change)
0de10343 7281{
7a905b14
TY		 7282 /*
7283 * Only private memory slots need to be mapped here since
7284 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7285 */
7b6195a9 7286 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7287 unsigned long userspace_addr;
604b38ac 7288
7a905b14
TY		 7289 /*
7290 * MAP_SHARED to prevent internal slot pages from being moved
7291 * by fork()/COW.
7292 */
7b6195a9 7293 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7294 PROT_READ | PROT_WRITE,
7295 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7296
7a905b14
TY		 7297 if (IS_ERR((void *)userspace_addr))
7298 return PTR_ERR((void *)userspace_addr);
604b38ac 7299
7a905b14 7300 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7301 }
7302
f7784b8e
MT		 7303 return 0;
7304}
7305
7306void kvm_arch_commit_memory_region(struct kvm *kvm,
7307 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7308 const struct kvm_memory_slot *old,
7309 enum kvm_mr_change change)
f7784b8e
MT		 7310{
7311
8482644a 7312 int nr_mmu_pages = 0;
f7784b8e 7313
8482644a 7314 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7315 int ret;
7316
8482644a
TY		 7317 ret = vm_munmap(old->userspace_addr,
7318 old->npages * PAGE_SIZE);
f7784b8e
MT		 7319 if (ret < 0)
7320 printk(KERN_WARNING
7321 "kvm_vm_ioctl_set_memory_region: "
7322 "failed to munmap memory\n");
7323 }
7324
48c0e4e9
XG		 7325 if (!kvm->arch.n_requested_mmu_pages)
7326 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7327
48c0e4e9 7328 if (nr_mmu_pages)
0de10343 7329 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7330 /*
7331 * Write protect all pages for dirty logging.
7332 * Existing largepage mappings are destroyed here and new ones will
7333 * not be created until the end of the logging.
7334 */
8482644a 7335 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7336 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7337}
1d737c8a 7338
2df72e9b 7339void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7340{
6ca18b69 7341 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7342}
7343
2df72e9b
MT		 7344void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7345 struct kvm_memory_slot *slot)
7346{
6ca18b69 7347 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7348}
7349
1d737c8a
ZX		 7350int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7351{
b6b8a145
JK		 7352 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7353 kvm_x86_ops->check_nested_events(vcpu, false);
7354
af585b92
GN		 7355 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7356 !vcpu->arch.apf.halted)
7357 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7358 || kvm_apic_has_events(vcpu)
6aef266c 7359 || vcpu->arch.pv.pv_unhalted
7460fb4a 7360 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7361 (kvm_arch_interrupt_allowed(vcpu) &&
7362 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7363}
5736199a 7364
b6d33834 7365int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7366{
b6d33834 7367 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7368}
78646121
GN		 7369
7370int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7371{
7372 return kvm_x86_ops->interrupt_allowed(vcpu);
7373}
229456fc 7374
f92653ee
JK		 7375bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7376{
7377 unsigned long current_rip = kvm_rip_read(vcpu) +
7378 get_segment_base(vcpu, VCPU_SREG_CS);
7379
7380 return current_rip == linear_rip;
7381}
7382EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7383
94fe45da
JK		 7384unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7385{
7386 unsigned long rflags;
7387
7388 rflags = kvm_x86_ops->get_rflags(vcpu);
7389 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7390 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7391 return rflags;
7392}
7393EXPORT_SYMBOL_GPL(kvm_get_rflags);
7394
7395void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7396{
7397 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7398 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7399 rflags |= X86_EFLAGS_TF;
94fe45da 7400 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7401 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7402}
7403EXPORT_SYMBOL_GPL(kvm_set_rflags);
7404
56028d08
GN		 7405void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7406{
7407 int r;
7408
fb67e14f 7409 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7410 work->wakeup_all)
56028d08
GN		 7411 return;
7412
7413 r = kvm_mmu_reload(vcpu);
7414 if (unlikely(r))
7415 return;
7416
fb67e14f
XG		 7417 if (!vcpu->arch.mmu.direct_map &&
7418 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7419 return;
7420
56028d08
GN		 7421 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7422}
7423
af585b92
GN		 7424static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7425{
7426 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7427}
7428
7429static inline u32 kvm_async_pf_next_probe(u32 key)
7430{
7431 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7432}
7433
7434static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7435{
7436 u32 key = kvm_async_pf_hash_fn(gfn);
7437
7438 while (vcpu->arch.apf.gfns[key] != ~0)
7439 key = kvm_async_pf_next_probe(key);
7440
7441 vcpu->arch.apf.gfns[key] = gfn;
7442}
7443
7444static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7445{
7446 int i;
7447 u32 key = kvm_async_pf_hash_fn(gfn);
7448
7449 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7450 (vcpu->arch.apf.gfns[key] != gfn &&
7451 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7452 key = kvm_async_pf_next_probe(key);
7453
7454 return key;
7455}
7456
7457bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7458{
7459 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7460}
7461
7462static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7463{
7464 u32 i, j, k;
7465
7466 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7467 while (true) {
7468 vcpu->arch.apf.gfns[i] = ~0;
7469 do {
7470 j = kvm_async_pf_next_probe(j);
7471 if (vcpu->arch.apf.gfns[j] == ~0)
7472 return;
7473 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7474 /*
7475 * k lies cyclically in ]i,j]
7476 * | i.k.j |
7477 * |....j i.k.| or |.k..j i...|
7478 */
7479 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7480 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7481 i = j;
7482 }
7483}
7484
7c90705b
GN		 7485static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7486{
7487
7488 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7489 sizeof(val));
7490}
7491
af585b92
GN		 7492void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7493 struct kvm_async_pf *work)
7494{
6389ee94
AK		 7495 struct x86_exception fault;
7496
7c90705b 7497 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7498 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7499
7500 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7501 (vcpu->arch.apf.send_user_only &&
7502 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7503 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7504 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7505 fault.vector = PF_VECTOR;
7506 fault.error_code_valid = true;
7507 fault.error_code = 0;
7508 fault.nested_page_fault = false;
7509 fault.address = work->arch.token;
7510 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7511 }
af585b92
GN		 7512}
7513
7514void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7515 struct kvm_async_pf *work)
7516{
6389ee94
AK		 7517 struct x86_exception fault;
7518
7c90705b 7519 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7520 if (work->wakeup_all)
7c90705b
GN		 7521 work->arch.token = ~0; /* broadcast wakeup */
7522 else
7523 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7524
7525 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7526 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7527 fault.vector = PF_VECTOR;
7528 fault.error_code_valid = true;
7529 fault.error_code = 0;
7530 fault.nested_page_fault = false;
7531 fault.address = work->arch.token;
7532 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7533 }
e6d53e3b 7534 vcpu->arch.apf.halted = false;
a4fa1635 7535 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7536}
7537
7538bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7539{
7540 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7541 return true;
7542 else
7543 return !kvm_event_needs_reinjection(vcpu) &&
7544 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7545}
7546
e0f0bbc5
AW		 7547void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7548{
7549 atomic_inc(&kvm->arch.noncoherent_dma_count);
7550}
7551EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7552
7553void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7554{
7555 atomic_dec(&kvm->arch.noncoherent_dma_count);
7556}
7557EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7558
7559bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7560{
7561 return atomic_read(&kvm->arch.noncoherent_dma_count);
7562}
7563EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7564
229456fc
MT		 7565EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7566EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7567EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7568EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7569EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7570EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7571EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7572EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7573EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7574EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7575EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7576EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7577EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git