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KVM: Remove SMAP bit from CR4_RESERVED_BITS
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
afcbf13f 655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 656 return 1;
657
a03490ed 658 if (is_long_mode(vcpu)) {
0f12244f
GN		 659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
a2edf57f
AK		 661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
0f12244f
GN		 665 return 1;
666
ad756a16
MJ		 667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
5e1746d6 676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 677 return 1;
a03490ed 678
ad756a16
MJ		 679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 681 kvm_mmu_reset_context(vcpu);
0f12244f 682
2acf923e 683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 684 kvm_update_cpuid(vcpu);
2acf923e 685
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 689
2390218b 690int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 691{
9f8fe504 692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 693 kvm_mmu_sync_roots(vcpu);
d835dfec 694 kvm_mmu_flush_tlb(vcpu);
0f12244f 695 return 0;
d835dfec
AK		 696 }
697
a03490ed 698 if (is_long_mode(vcpu)) {
471842ec 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
a03490ed
CO		 705 } else {
706 if (is_pae(vcpu)) {
0f12244f
GN		 707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
ff03a073
JR		 709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 711 return 1;
a03490ed
CO		 712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
0f12244f 719 vcpu->arch.cr3 = cr3;
aff48baa 720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 721 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 722 return 0;
723}
2d3ad1f4 724EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 725
eea1cff9 726int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 727{
0f12244f
GN		 728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
a03490ed
CO		 730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
ad312c7c 733 vcpu->arch.cr8 = cr8;
0f12244f
GN		 734 return 0;
735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 737
2d3ad1f4 738unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 739{
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
ad312c7c 743 return vcpu->arch.cr8;
a03490ed 744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 746
73aaf249
JK		 747static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748{
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751}
752
c8639010
JK		 753static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754{
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 762 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
763 if (dr7 & DR7_BP_EN_MASK)
764 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 765}
766
338dbc97 767static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 768{
769 switch (dr) {
770 case 0 ... 3:
771 vcpu->arch.db[dr] = val;
772 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
773 vcpu->arch.eff_db[dr] = val;
774 break;
775 case 4:
338dbc97
GN		 776 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
777 return 1; /* #UD */
020df079
GN		 778 /* fall through */
779 case 6:
338dbc97
GN		 780 if (val & 0xffffffff00000000ULL)
781 return -1; /* #GP */
020df079 782 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 783 kvm_update_dr6(vcpu);
020df079
GN		 784 break;
785 case 5:
338dbc97
GN		 786 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
787 return 1; /* #UD */
020df079
GN		 788 /* fall through */
789 default: /* 7 */
338dbc97
GN		 790 if (val & 0xffffffff00000000ULL)
791 return -1; /* #GP */
020df079 792 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 793 kvm_update_dr7(vcpu);
020df079
GN		 794 break;
795 }
796
797 return 0;
798}
338dbc97
GN		 799
800int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
801{
802 int res;
803
804 res = __kvm_set_dr(vcpu, dr, val);
805 if (res > 0)
806 kvm_queue_exception(vcpu, UD_VECTOR);
807 else if (res < 0)
808 kvm_inject_gp(vcpu, 0);
809
810 return res;
811}
020df079
GN		 812EXPORT_SYMBOL_GPL(kvm_set_dr);
813
338dbc97 814static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 815{
816 switch (dr) {
817 case 0 ... 3:
818 *val = vcpu->arch.db[dr];
819 break;
820 case 4:
338dbc97 821 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 822 return 1;
020df079
GN		 823 /* fall through */
824 case 6:
73aaf249
JK		 825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 *val = vcpu->arch.dr6;
827 else
828 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 829 break;
830 case 5:
338dbc97 831 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 832 return 1;
020df079
GN		 833 /* fall through */
834 default: /* 7 */
835 *val = vcpu->arch.dr7;
836 break;
837 }
838
839 return 0;
840}
338dbc97
GN		 841
842int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
843{
844 if (_kvm_get_dr(vcpu, dr, val)) {
845 kvm_queue_exception(vcpu, UD_VECTOR);
846 return 1;
847 }
848 return 0;
849}
020df079
GN		 850EXPORT_SYMBOL_GPL(kvm_get_dr);
851
022cd0e8
AK		 852bool kvm_rdpmc(struct kvm_vcpu *vcpu)
853{
854 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
855 u64 data;
856 int err;
857
858 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
859 if (err)
860 return err;
861 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
862 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
863 return err;
864}
865EXPORT_SYMBOL_GPL(kvm_rdpmc);
866
043405e1
CO		 867/*
868 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
869 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
870 *
871 * This list is modified at module load time to reflect the
e3267cbb
GC		 872 * capabilities of the host cpu. This capabilities test skips MSRs that are
873 * kvm-specific. Those are put in the beginning of the list.
043405e1 874 */
e3267cbb 875
e984097b 876#define KVM_SAVE_MSRS_BEGIN 12
043405e1 877static u32 msrs_to_save[] = {
e3267cbb 878 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 879 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 880 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 881 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 882 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 883 MSR_KVM_PV_EOI_EN,
043405e1 884 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 885 MSR_STAR,
043405e1
CO		 886#ifdef CONFIG_X86_64
887 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
888#endif
b3897a49 889 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 890 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 891};
892
893static unsigned num_msrs_to_save;
894
f1d24831 895static const u32 emulated_msrs[] = {
ba904635 896 MSR_IA32_TSC_ADJUST,
a3e06bbe 897 MSR_IA32_TSCDEADLINE,
043405e1 898 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 899 MSR_IA32_MCG_STATUS,
900 MSR_IA32_MCG_CTL,
043405e1
CO		 901};
902
384bb783 903bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 904{
b69e8cae 905 if (efer & efer_reserved_bits)
384bb783 906 return false;
15c4a640 907
1b2fd70c
AG		 908 if (efer & EFER_FFXSR) {
909 struct kvm_cpuid_entry2 *feat;
910
911 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 912 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 913 return false;
1b2fd70c
AG		 914 }
915
d8017474
AG		 916 if (efer & EFER_SVME) {
917 struct kvm_cpuid_entry2 *feat;
918
919 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 920 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 921 return false;
d8017474
AG		 922 }
923
384bb783
JK		 924 return true;
925}
926EXPORT_SYMBOL_GPL(kvm_valid_efer);
927
928static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
929{
930 u64 old_efer = vcpu->arch.efer;
931
932 if (!kvm_valid_efer(vcpu, efer))
933 return 1;
934
935 if (is_paging(vcpu)
936 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
937 return 1;
938
15c4a640 939 efer &= ~EFER_LMA;
f6801dff 940 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 941
a3d204e2
SY		 942 kvm_x86_ops->set_efer(vcpu, efer);
943
aad82703
SY		 944 /* Update reserved bits */
945 if ((efer ^ old_efer) & EFER_NX)
946 kvm_mmu_reset_context(vcpu);
947
b69e8cae 948 return 0;
15c4a640
CO		 949}
950
f2b4b7dd
JR		 951void kvm_enable_efer_bits(u64 mask)
952{
953 efer_reserved_bits &= ~mask;
954}
955EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
956
957
15c4a640
CO		 958/*
959 * Writes msr value into into the appropriate "register".
960 * Returns 0 on success, non-0 otherwise.
961 * Assumes vcpu_load() was already called.
962 */
8fe8ab46 963int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 964{
8fe8ab46 965 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 966}
967
313a3dc7
CO		 968/*
969 * Adapt set_msr() to msr_io()'s calling convention
970 */
971static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
972{
8fe8ab46
WA		 973 struct msr_data msr;
974
975 msr.data = *data;
976 msr.index = index;
977 msr.host_initiated = true;
978 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 979}
980
16e8d74d
MT		 981#ifdef CONFIG_X86_64
982struct pvclock_gtod_data {
983 seqcount_t seq;
984
985 struct { /* extract of a clocksource struct */
986 int vclock_mode;
987 cycle_t cycle_last;
988 cycle_t mask;
989 u32 mult;
990 u32 shift;
991 } clock;
992
993 /* open coded 'struct timespec' */
994 u64 monotonic_time_snsec;
995 time_t monotonic_time_sec;
996};
997
998static struct pvclock_gtod_data pvclock_gtod_data;
999
1000static void update_pvclock_gtod(struct timekeeper *tk)
1001{
1002 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1003
1004 write_seqcount_begin(&vdata->seq);
1005
1006 /* copy pvclock gtod data */
1007 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1008 vdata->clock.cycle_last = tk->clock->cycle_last;
1009 vdata->clock.mask = tk->clock->mask;
1010 vdata->clock.mult = tk->mult;
1011 vdata->clock.shift = tk->shift;
1012
1013 vdata->monotonic_time_sec = tk->xtime_sec
1014 + tk->wall_to_monotonic.tv_sec;
1015 vdata->monotonic_time_snsec = tk->xtime_nsec
1016 + (tk->wall_to_monotonic.tv_nsec
1017 << tk->shift);
1018 while (vdata->monotonic_time_snsec >=
1019 (((u64)NSEC_PER_SEC) << tk->shift)) {
1020 vdata->monotonic_time_snsec -=
1021 ((u64)NSEC_PER_SEC) << tk->shift;
1022 vdata->monotonic_time_sec++;
1023 }
1024
1025 write_seqcount_end(&vdata->seq);
1026}
1027#endif
1028
1029
18068523
GOC		 1030static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1031{
9ed3c444
AK		 1032 int version;
1033 int r;
50d0a0f9 1034 struct pvclock_wall_clock wc;
923de3cf 1035 struct timespec boot;
18068523
GOC		 1036
1037 if (!wall_clock)
1038 return;
1039
9ed3c444
AK		 1040 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1041 if (r)
1042 return;
1043
1044 if (version & 1)
1045 ++version; /* first time write, random junk */
1046
1047 ++version;
18068523 1048
18068523
GOC		 1049 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1050
50d0a0f9
GH		 1051 /*
1052 * The guest calculates current wall clock time by adding
34c238a1 1053 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1054 * wall clock specified here. guest system time equals host
1055 * system time for us, thus we must fill in host boot time here.
1056 */
923de3cf 1057 getboottime(&boot);
50d0a0f9 1058
4b648665
BR		 1059 if (kvm->arch.kvmclock_offset) {
1060 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1061 boot = timespec_sub(boot, ts);
1062 }
50d0a0f9
GH		 1063 wc.sec = boot.tv_sec;
1064 wc.nsec = boot.tv_nsec;
1065 wc.version = version;
18068523
GOC		 1066
1067 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1068
1069 version++;
1070 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1071}
1072
50d0a0f9
GH		 1073static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1074{
1075 uint32_t quotient, remainder;
1076
1077 /* Don't try to replace with do_div(), this one calculates
1078 * "(dividend << 32) / divisor" */
1079 __asm__ ( "divl %4"
1080 : "=a" (quotient), "=d" (remainder)
1081 : "0" (0), "1" (dividend), "r" (divisor) );
1082 return quotient;
1083}
1084
5f4e3f88
ZA		 1085static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1086 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1087{
5f4e3f88 1088 uint64_t scaled64;
50d0a0f9
GH		 1089 int32_t shift = 0;
1090 uint64_t tps64;
1091 uint32_t tps32;
1092
5f4e3f88
ZA		 1093 tps64 = base_khz * 1000LL;
1094 scaled64 = scaled_khz * 1000LL;
50933623 1095 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1096 tps64 >>= 1;
1097 shift--;
1098 }
1099
1100 tps32 = (uint32_t)tps64;
50933623
JK		 1101 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1102 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1103 scaled64 >>= 1;
1104 else
1105 tps32 <<= 1;
50d0a0f9
GH		 1106 shift++;
1107 }
1108
5f4e3f88
ZA		 1109 *pshift = shift;
1110 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1111
5f4e3f88
ZA		 1112 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1113 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1114}
1115
759379dd
ZA		 1116static inline u64 get_kernel_ns(void)
1117{
1118 struct timespec ts;
1119
1120 WARN_ON(preemptible());
1121 ktime_get_ts(&ts);
1122 monotonic_to_bootbased(&ts);
1123 return timespec_to_ns(&ts);
50d0a0f9
GH		 1124}
1125
d828199e 1126#ifdef CONFIG_X86_64
16e8d74d 1127static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1128#endif
16e8d74d 1129
c8076604 1130static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1131unsigned long max_tsc_khz;
c8076604 1132
cc578287 1133static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1134{
cc578287
ZA		 1135 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1136 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1137}
1138
cc578287 1139static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1140{
cc578287
ZA		 1141 u64 v = (u64)khz * (1000000 + ppm);
1142 do_div(v, 1000000);
1143 return v;
1e993611
JR		 1144}
1145
cc578287 1146static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1147{
cc578287
ZA		 1148 u32 thresh_lo, thresh_hi;
1149 int use_scaling = 0;
217fc9cf 1150
03ba32ca
MT		 1151 /* tsc_khz can be zero if TSC calibration fails */
1152 if (this_tsc_khz == 0)
1153 return;
1154
c285545f
ZA		 1155 /* Compute a scale to convert nanoseconds in TSC cycles */
1156 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1157 &vcpu->arch.virtual_tsc_shift,
1158 &vcpu->arch.virtual_tsc_mult);
1159 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1160
1161 /*
1162 * Compute the variation in TSC rate which is acceptable
1163 * within the range of tolerance and decide if the
1164 * rate being applied is within that bounds of the hardware
1165 * rate. If so, no scaling or compensation need be done.
1166 */
1167 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1168 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1169 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1170 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1171 use_scaling = 1;
1172 }
1173 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1174}
1175
1176static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1177{
e26101b1 1178 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1179 vcpu->arch.virtual_tsc_mult,
1180 vcpu->arch.virtual_tsc_shift);
e26101b1 1181 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1182 return tsc;
1183}
1184
b48aa97e
MT		 1185void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1186{
1187#ifdef CONFIG_X86_64
1188 bool vcpus_matched;
1189 bool do_request = false;
1190 struct kvm_arch *ka = &vcpu->kvm->arch;
1191 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1192
1193 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1194 atomic_read(&vcpu->kvm->online_vcpus));
1195
1196 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1197 if (!ka->use_master_clock)
1198 do_request = 1;
1199
1200 if (!vcpus_matched && ka->use_master_clock)
1201 do_request = 1;
1202
1203 if (do_request)
1204 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1205
1206 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1207 atomic_read(&vcpu->kvm->online_vcpus),
1208 ka->use_master_clock, gtod->clock.vclock_mode);
1209#endif
1210}
1211
ba904635
WA		 1212static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1213{
1214 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1215 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1216}
1217
8fe8ab46 1218void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1219{
1220 struct kvm *kvm = vcpu->kvm;
f38e098f 1221 u64 offset, ns, elapsed;
99e3e30a 1222 unsigned long flags;
02626b6a 1223 s64 usdiff;
b48aa97e 1224 bool matched;
8fe8ab46 1225 u64 data = msr->data;
99e3e30a 1226
038f8c11 1227 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1228 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1229 ns = get_kernel_ns();
f38e098f 1230 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1231
03ba32ca 1232 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1233 int faulted = 0;
1234
03ba32ca
MT		 1235 /* n.b - signed multiplication and division required */
1236 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1237#ifdef CONFIG_X86_64
03ba32ca 1238 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1239#else
03ba32ca 1240 /* do_div() only does unsigned */
8915aa27
MT		 1241 asm("1: idivl %[divisor]\n"
1242 "2: xor %%edx, %%edx\n"
1243 " movl $0, %[faulted]\n"
1244 "3:\n"
1245 ".section .fixup,\"ax\"\n"
1246 "4: movl $1, %[faulted]\n"
1247 " jmp 3b\n"
1248 ".previous\n"
1249
1250 _ASM_EXTABLE(1b, 4b)
1251
1252 : "=A"(usdiff), [faulted] "=r" (faulted)
1253 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1254
5d3cb0f6 1255#endif
03ba32ca
MT		 1256 do_div(elapsed, 1000);
1257 usdiff -= elapsed;
1258 if (usdiff < 0)
1259 usdiff = -usdiff;
8915aa27
MT		 1260
1261 /* idivl overflow => difference is larger than USEC_PER_SEC */
1262 if (faulted)
1263 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1264 } else
1265 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1266
1267 /*
5d3cb0f6
ZA		 1268 * Special case: TSC write with a small delta (1 second) of virtual
1269 * cycle time against real time is interpreted as an attempt to
1270 * synchronize the CPU.
1271 *
1272 * For a reliable TSC, we can match TSC offsets, and for an unstable
1273 * TSC, we add elapsed time in this computation. We could let the
1274 * compensation code attempt to catch up if we fall behind, but
1275 * it's better to try to match offsets from the beginning.
1276 */
02626b6a 1277 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1278 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1279 if (!check_tsc_unstable()) {
e26101b1 1280 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1281 pr_debug("kvm: matched tsc offset for %llu\n", data);
1282 } else {
857e4099 1283 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1284 data += delta;
1285 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1286 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1287 }
b48aa97e 1288 matched = true;
e26101b1
ZA		 1289 } else {
1290 /*
1291 * We split periods of matched TSC writes into generations.
1292 * For each generation, we track the original measured
1293 * nanosecond time, offset, and write, so if TSCs are in
1294 * sync, we can match exact offset, and if not, we can match
4a969980 1295 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1296 *
1297 * These values are tracked in kvm->arch.cur_xxx variables.
1298 */
1299 kvm->arch.cur_tsc_generation++;
1300 kvm->arch.cur_tsc_nsec = ns;
1301 kvm->arch.cur_tsc_write = data;
1302 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1303 matched = false;
e26101b1
ZA		 1304 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1305 kvm->arch.cur_tsc_generation, data);
f38e098f 1306 }
e26101b1
ZA		 1307
1308 /*
1309 * We also track th most recent recorded KHZ, write and time to
1310 * allow the matching interval to be extended at each write.
1311 */
f38e098f
ZA		 1312 kvm->arch.last_tsc_nsec = ns;
1313 kvm->arch.last_tsc_write = data;
5d3cb0f6 1314 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1315
b183aa58 1316 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1317
1318 /* Keep track of which generation this VCPU has synchronized to */
1319 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1320 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1321 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1322
ba904635
WA		 1323 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1324 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1325 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1326 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1327
1328 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1329 if (matched)
1330 kvm->arch.nr_vcpus_matched_tsc++;
1331 else
1332 kvm->arch.nr_vcpus_matched_tsc = 0;
1333
1334 kvm_track_tsc_matching(vcpu);
1335 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1336}
e26101b1 1337
99e3e30a
ZA		 1338EXPORT_SYMBOL_GPL(kvm_write_tsc);
1339
d828199e
MT		 1340#ifdef CONFIG_X86_64
1341
1342static cycle_t read_tsc(void)
1343{
1344 cycle_t ret;
1345 u64 last;
1346
1347 /*
1348 * Empirically, a fence (of type that depends on the CPU)
1349 * before rdtsc is enough to ensure that rdtsc is ordered
1350 * with respect to loads. The various CPU manuals are unclear
1351 * as to whether rdtsc can be reordered with later loads,
1352 * but no one has ever seen it happen.
1353 */
1354 rdtsc_barrier();
1355 ret = (cycle_t)vget_cycles();
1356
1357 last = pvclock_gtod_data.clock.cycle_last;
1358
1359 if (likely(ret >= last))
1360 return ret;
1361
1362 /*
1363 * GCC likes to generate cmov here, but this branch is extremely
1364 * predictable (it's just a funciton of time and the likely is
1365 * very likely) and there's a data dependence, so force GCC
1366 * to generate a branch instead. I don't barrier() because
1367 * we don't actually need a barrier, and if this function
1368 * ever gets inlined it will generate worse code.
1369 */
1370 asm volatile ("");
1371 return last;
1372}
1373
1374static inline u64 vgettsc(cycle_t *cycle_now)
1375{
1376 long v;
1377 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1378
1379 *cycle_now = read_tsc();
1380
1381 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1382 return v * gtod->clock.mult;
1383}
1384
1385static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1386{
1387 unsigned long seq;
1388 u64 ns;
1389 int mode;
1390 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1391
1392 ts->tv_nsec = 0;
1393 do {
1394 seq = read_seqcount_begin(&gtod->seq);
1395 mode = gtod->clock.vclock_mode;
1396 ts->tv_sec = gtod->monotonic_time_sec;
1397 ns = gtod->monotonic_time_snsec;
1398 ns += vgettsc(cycle_now);
1399 ns >>= gtod->clock.shift;
1400 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1401 timespec_add_ns(ts, ns);
1402
1403 return mode;
1404}
1405
1406/* returns true if host is using tsc clocksource */
1407static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1408{
1409 struct timespec ts;
1410
1411 /* checked again under seqlock below */
1412 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1413 return false;
1414
1415 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1416 return false;
1417
1418 monotonic_to_bootbased(&ts);
1419 *kernel_ns = timespec_to_ns(&ts);
1420
1421 return true;
1422}
1423#endif
1424
1425/*
1426 *
b48aa97e
MT		 1427 * Assuming a stable TSC across physical CPUS, and a stable TSC
1428 * across virtual CPUs, the following condition is possible.
1429 * Each numbered line represents an event visible to both
d828199e
MT		 1430 * CPUs at the next numbered event.
1431 *
1432 * "timespecX" represents host monotonic time. "tscX" represents
1433 * RDTSC value.
1434 *
1435 * VCPU0 on CPU0 | VCPU1 on CPU1
1436 *
1437 * 1. read timespec0,tsc0
1438 * 2. | timespec1 = timespec0 + N
1439 * | tsc1 = tsc0 + M
1440 * 3. transition to guest | transition to guest
1441 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1442 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1443 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1444 *
1445 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1446 *
1447 * - ret0 < ret1
1448 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1449 * ...
1450 * - 0 < N - M => M < N
1451 *
1452 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1453 * always the case (the difference between two distinct xtime instances
1454 * might be smaller then the difference between corresponding TSC reads,
1455 * when updating guest vcpus pvclock areas).
1456 *
1457 * To avoid that problem, do not allow visibility of distinct
1458 * system_timestamp/tsc_timestamp values simultaneously: use a master
1459 * copy of host monotonic time values. Update that master copy
1460 * in lockstep.
1461 *
b48aa97e 1462 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1463 *
1464 */
1465
1466static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1467{
1468#ifdef CONFIG_X86_64
1469 struct kvm_arch *ka = &kvm->arch;
1470 int vclock_mode;
b48aa97e
MT		 1471 bool host_tsc_clocksource, vcpus_matched;
1472
1473 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1474 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1475
1476 /*
1477 * If the host uses TSC clock, then passthrough TSC as stable
1478 * to the guest.
1479 */
b48aa97e 1480 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1481 &ka->master_kernel_ns,
1482 &ka->master_cycle_now);
1483
b48aa97e
MT		 1484 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1485
d828199e
MT		 1486 if (ka->use_master_clock)
1487 atomic_set(&kvm_guest_has_master_clock, 1);
1488
1489 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1490 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1491 vcpus_matched);
d828199e
MT		 1492#endif
1493}
1494
2e762ff7
MT		 1495static void kvm_gen_update_masterclock(struct kvm *kvm)
1496{
1497#ifdef CONFIG_X86_64
1498 int i;
1499 struct kvm_vcpu *vcpu;
1500 struct kvm_arch *ka = &kvm->arch;
1501
1502 spin_lock(&ka->pvclock_gtod_sync_lock);
1503 kvm_make_mclock_inprogress_request(kvm);
1504 /* no guest entries from this point */
1505 pvclock_update_vm_gtod_copy(kvm);
1506
1507 kvm_for_each_vcpu(i, vcpu, kvm)
1508 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1509
1510 /* guest entries allowed */
1511 kvm_for_each_vcpu(i, vcpu, kvm)
1512 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1513
1514 spin_unlock(&ka->pvclock_gtod_sync_lock);
1515#endif
1516}
1517
34c238a1 1518static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1519{
d828199e 1520 unsigned long flags, this_tsc_khz;
18068523 1521 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1522 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1523 s64 kernel_ns;
d828199e 1524 u64 tsc_timestamp, host_tsc;
0b79459b 1525 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1526 u8 pvclock_flags;
d828199e
MT		 1527 bool use_master_clock;
1528
1529 kernel_ns = 0;
1530 host_tsc = 0;
18068523 1531
d828199e
MT		 1532 /*
1533 * If the host uses TSC clock, then passthrough TSC as stable
1534 * to the guest.
1535 */
1536 spin_lock(&ka->pvclock_gtod_sync_lock);
1537 use_master_clock = ka->use_master_clock;
1538 if (use_master_clock) {
1539 host_tsc = ka->master_cycle_now;
1540 kernel_ns = ka->master_kernel_ns;
1541 }
1542 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1543
1544 /* Keep irq disabled to prevent changes to the clock */
1545 local_irq_save(flags);
1546 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1547 if (unlikely(this_tsc_khz == 0)) {
1548 local_irq_restore(flags);
1549 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1550 return 1;
1551 }
d828199e
MT		 1552 if (!use_master_clock) {
1553 host_tsc = native_read_tsc();
1554 kernel_ns = get_kernel_ns();
1555 }
1556
1557 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1558
c285545f
ZA		 1559 /*
1560 * We may have to catch up the TSC to match elapsed wall clock
1561 * time for two reasons, even if kvmclock is used.
1562 * 1) CPU could have been running below the maximum TSC rate
1563 * 2) Broken TSC compensation resets the base at each VCPU
1564 * entry to avoid unknown leaps of TSC even when running
1565 * again on the same CPU. This may cause apparent elapsed
1566 * time to disappear, and the guest to stand still or run
1567 * very slowly.
1568 */
1569 if (vcpu->tsc_catchup) {
1570 u64 tsc = compute_guest_tsc(v, kernel_ns);
1571 if (tsc > tsc_timestamp) {
f1e2b260 1572 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1573 tsc_timestamp = tsc;
1574 }
50d0a0f9
GH		 1575 }
1576
18068523
GOC		 1577 local_irq_restore(flags);
1578
0b79459b 1579 if (!vcpu->pv_time_enabled)
c285545f 1580 return 0;
18068523 1581
e48672fa 1582 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1583 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1584 &vcpu->hv_clock.tsc_shift,
1585 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1586 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1587 }
1588
1589 /* With all the info we got, fill in the values */
1d5f066e 1590 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1591 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1592 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1593
18068523
GOC		 1594 /*
1595 * The interface expects us to write an even number signaling that the
1596 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1597 * state, we just increase by 2 at the end.
18068523 1598 */
50d0a0f9 1599 vcpu->hv_clock.version += 2;
18068523 1600
0b79459b
AH		 1601 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1602 &guest_hv_clock, sizeof(guest_hv_clock))))
1603 return 0;
78c0337a
MT		 1604
1605 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1606 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1607
1608 if (vcpu->pvclock_set_guest_stopped_request) {
1609 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1610 vcpu->pvclock_set_guest_stopped_request = false;
1611 }
1612
d828199e
MT		 1613 /* If the host uses TSC clocksource, then it is stable */
1614 if (use_master_clock)
1615 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1616
78c0337a
MT		 1617 vcpu->hv_clock.flags = pvclock_flags;
1618
0b79459b
AH		 1619 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1620 &vcpu->hv_clock,
1621 sizeof(vcpu->hv_clock));
8cfdc000 1622 return 0;
c8076604
GH		 1623}
1624
0061d53d
MT		 1625/*
1626 * kvmclock updates which are isolated to a given vcpu, such as
1627 * vcpu->cpu migration, should not allow system_timestamp from
1628 * the rest of the vcpus to remain static. Otherwise ntp frequency
1629 * correction applies to one vcpu's system_timestamp but not
1630 * the others.
1631 *
1632 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1633 * We need to rate-limit these requests though, as they can
1634 * considerably slow guests that have a large number of vcpus.
1635 * The time for a remote vcpu to update its kvmclock is bound
1636 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1637 */
1638
7e44e449
AJ		 1639#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1640
1641static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1642{
1643 int i;
7e44e449
AJ		 1644 struct delayed_work *dwork = to_delayed_work(work);
1645 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1646 kvmclock_update_work);
1647 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1648 struct kvm_vcpu *vcpu;
1649
1650 kvm_for_each_vcpu(i, vcpu, kvm) {
1651 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1652 kvm_vcpu_kick(vcpu);
1653 }
1654}
1655
7e44e449
AJ		 1656static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1657{
1658 struct kvm *kvm = v->kvm;
1659
1660 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1661 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1662 KVMCLOCK_UPDATE_DELAY);
1663}
1664
332967a3
AJ		 1665#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1666
1667static void kvmclock_sync_fn(struct work_struct *work)
1668{
1669 struct delayed_work *dwork = to_delayed_work(work);
1670 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1671 kvmclock_sync_work);
1672 struct kvm *kvm = container_of(ka, struct kvm, arch);
1673
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1675 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1676 KVMCLOCK_SYNC_PERIOD);
1677}
1678
9ba075a6
AK		 1679static bool msr_mtrr_valid(unsigned msr)
1680{
1681 switch (msr) {
1682 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1683 case MSR_MTRRfix64K_00000:
1684 case MSR_MTRRfix16K_80000:
1685 case MSR_MTRRfix16K_A0000:
1686 case MSR_MTRRfix4K_C0000:
1687 case MSR_MTRRfix4K_C8000:
1688 case MSR_MTRRfix4K_D0000:
1689 case MSR_MTRRfix4K_D8000:
1690 case MSR_MTRRfix4K_E0000:
1691 case MSR_MTRRfix4K_E8000:
1692 case MSR_MTRRfix4K_F0000:
1693 case MSR_MTRRfix4K_F8000:
1694 case MSR_MTRRdefType:
1695 case MSR_IA32_CR_PAT:
1696 return true;
1697 case 0x2f8:
1698 return true;
1699 }
1700 return false;
1701}
1702
d6289b93
MT		 1703static bool valid_pat_type(unsigned t)
1704{
1705 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1706}
1707
1708static bool valid_mtrr_type(unsigned t)
1709{
1710 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1711}
1712
1713static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1714{
1715 int i;
1716
1717 if (!msr_mtrr_valid(msr))
1718 return false;
1719
1720 if (msr == MSR_IA32_CR_PAT) {
1721 for (i = 0; i < 8; i++)
1722 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1723 return false;
1724 return true;
1725 } else if (msr == MSR_MTRRdefType) {
1726 if (data & ~0xcff)
1727 return false;
1728 return valid_mtrr_type(data & 0xff);
1729 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1730 for (i = 0; i < 8 ; i++)
1731 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1732 return false;
1733 return true;
1734 }
1735
1736 /* variable MTRRs */
1737 return valid_mtrr_type(data & 0xff);
1738}
1739
9ba075a6
AK		 1740static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1741{
0bed3b56
SY		 1742 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1743
d6289b93 1744 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1745 return 1;
1746
0bed3b56
SY		 1747 if (msr == MSR_MTRRdefType) {
1748 vcpu->arch.mtrr_state.def_type = data;
1749 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1750 } else if (msr == MSR_MTRRfix64K_00000)
1751 p[0] = data;
1752 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1753 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1754 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1755 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1756 else if (msr == MSR_IA32_CR_PAT)
1757 vcpu->arch.pat = data;
1758 else { /* Variable MTRRs */
1759 int idx, is_mtrr_mask;
1760 u64 *pt;
1761
1762 idx = (msr - 0x200) / 2;
1763 is_mtrr_mask = msr - 0x200 - 2 * idx;
1764 if (!is_mtrr_mask)
1765 pt =
1766 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1767 else
1768 pt =
1769 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1770 *pt = data;
1771 }
1772
1773 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1774 return 0;
1775}
15c4a640 1776
890ca9ae 1777static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1778{
890ca9ae
HY		 1779 u64 mcg_cap = vcpu->arch.mcg_cap;
1780 unsigned bank_num = mcg_cap & 0xff;
1781
15c4a640 1782 switch (msr) {
15c4a640 1783 case MSR_IA32_MCG_STATUS:
890ca9ae 1784 vcpu->arch.mcg_status = data;
15c4a640 1785 break;
c7ac679c 1786 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1787 if (!(mcg_cap & MCG_CTL_P))
1788 return 1;
1789 if (data != 0 && data != ~(u64)0)
1790 return -1;
1791 vcpu->arch.mcg_ctl = data;
1792 break;
1793 default:
1794 if (msr >= MSR_IA32_MC0_CTL &&
1795 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1796 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1797 /* only 0 or all 1s can be written to IA32_MCi_CTL
1798 * some Linux kernels though clear bit 10 in bank 4 to
1799 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1800 * this to avoid an uncatched #GP in the guest
1801 */
890ca9ae 1802 if ((offset & 0x3) == 0 &&
114be429 1803 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1804 return -1;
1805 vcpu->arch.mce_banks[offset] = data;
1806 break;
1807 }
1808 return 1;
1809 }
1810 return 0;
1811}
1812
ffde22ac
ES		 1813static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1814{
1815 struct kvm *kvm = vcpu->kvm;
1816 int lm = is_long_mode(vcpu);
1817 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1818 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1819 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1820 : kvm->arch.xen_hvm_config.blob_size_32;
1821 u32 page_num = data & ~PAGE_MASK;
1822 u64 page_addr = data & PAGE_MASK;
1823 u8 *page;
1824 int r;
1825
1826 r = -E2BIG;
1827 if (page_num >= blob_size)
1828 goto out;
1829 r = -ENOMEM;
ff5c2c03
SL		 1830 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1831 if (IS_ERR(page)) {
1832 r = PTR_ERR(page);
ffde22ac 1833 goto out;
ff5c2c03 1834 }
ffde22ac
ES		 1835 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1836 goto out_free;
1837 r = 0;
1838out_free:
1839 kfree(page);
1840out:
1841 return r;
1842}
1843
55cd8e5a
GN		 1844static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1845{
1846 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1847}
1848
1849static bool kvm_hv_msr_partition_wide(u32 msr)
1850{
1851 bool r = false;
1852 switch (msr) {
1853 case HV_X64_MSR_GUEST_OS_ID:
1854 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1855 case HV_X64_MSR_REFERENCE_TSC:
1856 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1857 r = true;
1858 break;
1859 }
1860
1861 return r;
1862}
1863
1864static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1865{
1866 struct kvm *kvm = vcpu->kvm;
1867
1868 switch (msr) {
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 kvm->arch.hv_guest_os_id = data;
1871 /* setting guest os id to zero disables hypercall page */
1872 if (!kvm->arch.hv_guest_os_id)
1873 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1874 break;
1875 case HV_X64_MSR_HYPERCALL: {
1876 u64 gfn;
1877 unsigned long addr;
1878 u8 instructions[4];
1879
1880 /* if guest os id is not set hypercall should remain disabled */
1881 if (!kvm->arch.hv_guest_os_id)
1882 break;
1883 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1884 kvm->arch.hv_hypercall = data;
1885 break;
1886 }
1887 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1888 addr = gfn_to_hva(kvm, gfn);
1889 if (kvm_is_error_hva(addr))
1890 return 1;
1891 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1892 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1893 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1894 return 1;
1895 kvm->arch.hv_hypercall = data;
b94b64c9 1896 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1897 break;
1898 }
e984097b
VR		 1899 case HV_X64_MSR_REFERENCE_TSC: {
1900 u64 gfn;
1901 HV_REFERENCE_TSC_PAGE tsc_ref;
1902 memset(&tsc_ref, 0, sizeof(tsc_ref));
1903 kvm->arch.hv_tsc_page = data;
1904 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1905 break;
1906 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1907 if (kvm_write_guest(kvm, data,
1908 &tsc_ref, sizeof(tsc_ref)))
1909 return 1;
1910 mark_page_dirty(kvm, gfn);
1911 break;
1912 }
55cd8e5a 1913 default:
a737f256
CD		 1914 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1915 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1916 return 1;
1917 }
1918 return 0;
1919}
1920
1921static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1922{
10388a07
GN		 1923 switch (msr) {
1924 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1925 u64 gfn;
10388a07 1926 unsigned long addr;
55cd8e5a 1927
10388a07
GN		 1928 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1929 vcpu->arch.hv_vapic = data;
1930 break;
1931 }
b3af1e88
VR		 1932 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1933 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1934 if (kvm_is_error_hva(addr))
1935 return 1;
8b0cedff 1936 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1937 return 1;
1938 vcpu->arch.hv_vapic = data;
b3af1e88 1939 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1940 break;
1941 }
1942 case HV_X64_MSR_EOI:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1944 case HV_X64_MSR_ICR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1946 case HV_X64_MSR_TPR:
1947 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1948 default:
a737f256
CD		 1949 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1950 "data 0x%llx\n", msr, data);
10388a07
GN		 1951 return 1;
1952 }
1953
1954 return 0;
55cd8e5a
GN		 1955}
1956
344d9588
GN		 1957static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1958{
1959 gpa_t gpa = data & ~0x3f;
1960
4a969980 1961 /* Bits 2:5 are reserved, Should be zero */
6adba527 1962 if (data & 0x3c)
344d9588
GN		 1963 return 1;
1964
1965 vcpu->arch.apf.msr_val = data;
1966
1967 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1968 kvm_clear_async_pf_completion_queue(vcpu);
1969 kvm_async_pf_hash_reset(vcpu);
1970 return 0;
1971 }
1972
8f964525
AH		 1973 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1974 sizeof(u32)))
344d9588
GN		 1975 return 1;
1976
6adba527 1977 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1978 kvm_async_pf_wakeup_all(vcpu);
1979 return 0;
1980}
1981
12f9a48f
GC		 1982static void kvmclock_reset(struct kvm_vcpu *vcpu)
1983{
0b79459b 1984 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1985}
1986
c9aaa895
GC		 1987static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1988{
1989 u64 delta;
1990
1991 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1992 return;
1993
1994 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1995 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1996 vcpu->arch.st.accum_steal = delta;
1997}
1998
1999static void record_steal_time(struct kvm_vcpu *vcpu)
2000{
2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2002 return;
2003
2004 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2005 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2006 return;
2007
2008 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2009 vcpu->arch.st.steal.version += 2;
2010 vcpu->arch.st.accum_steal = 0;
2011
2012 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2013 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2014}
2015
8fe8ab46 2016int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2017{
5753785f 2018 bool pr = false;
8fe8ab46
WA		 2019 u32 msr = msr_info->index;
2020 u64 data = msr_info->data;
5753785f 2021
15c4a640 2022 switch (msr) {
2e32b719
BP		 2023 case MSR_AMD64_NB_CFG:
2024 case MSR_IA32_UCODE_REV:
2025 case MSR_IA32_UCODE_WRITE:
2026 case MSR_VM_HSAVE_PA:
2027 case MSR_AMD64_PATCH_LOADER:
2028 case MSR_AMD64_BU_CFG2:
2029 break;
2030
15c4a640 2031 case MSR_EFER:
b69e8cae 2032 return set_efer(vcpu, data);
8f1589d9
AP		 2033 case MSR_K7_HWCR:
2034 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2035 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2036 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2037 if (data != 0) {
a737f256
CD		 2038 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2039 data);
8f1589d9
AP		 2040 return 1;
2041 }
15c4a640 2042 break;
f7c6d140
AP		 2043 case MSR_FAM10H_MMIO_CONF_BASE:
2044 if (data != 0) {
a737f256
CD		 2045 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2046 "0x%llx\n", data);
f7c6d140
AP		 2047 return 1;
2048 }
15c4a640 2049 break;
b5e2fec0
AG		 2050 case MSR_IA32_DEBUGCTLMSR:
2051 if (!data) {
2052 /* We support the non-activated case already */
2053 break;
2054 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2055 /* Values other than LBR and BTF are vendor-specific,
2056 thus reserved and should throw a #GP */
2057 return 1;
2058 }
a737f256
CD		 2059 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2060 __func__, data);
b5e2fec0 2061 break;
9ba075a6
AK		 2062 case 0x200 ... 0x2ff:
2063 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2064 case MSR_IA32_APICBASE:
58cb628d 2065 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2066 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2067 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2068 case MSR_IA32_TSCDEADLINE:
2069 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2070 break;
ba904635
WA		 2071 case MSR_IA32_TSC_ADJUST:
2072 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2073 if (!msr_info->host_initiated) {
2074 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2075 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2076 }
2077 vcpu->arch.ia32_tsc_adjust_msr = data;
2078 }
2079 break;
15c4a640 2080 case MSR_IA32_MISC_ENABLE:
ad312c7c 2081 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2082 break;
11c6bffa 2083 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2084 case MSR_KVM_WALL_CLOCK:
2085 vcpu->kvm->arch.wall_clock = data;
2086 kvm_write_wall_clock(vcpu->kvm, data);
2087 break;
11c6bffa 2088 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2089 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2090 u64 gpa_offset;
12f9a48f 2091 kvmclock_reset(vcpu);
18068523
GOC		 2092
2093 vcpu->arch.time = data;
0061d53d 2094 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2095
2096 /* we verify if the enable bit is set... */
2097 if (!(data & 1))
2098 break;
2099
0b79459b 2100 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2101
0b79459b 2102 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2103 &vcpu->arch.pv_time, data & ~1ULL,
2104 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2105 vcpu->arch.pv_time_enabled = false;
2106 else
2107 vcpu->arch.pv_time_enabled = true;
32cad84f 2108
18068523
GOC		 2109 break;
2110 }
344d9588
GN		 2111 case MSR_KVM_ASYNC_PF_EN:
2112 if (kvm_pv_enable_async_pf(vcpu, data))
2113 return 1;
2114 break;
c9aaa895
GC		 2115 case MSR_KVM_STEAL_TIME:
2116
2117 if (unlikely(!sched_info_on()))
2118 return 1;
2119
2120 if (data & KVM_STEAL_RESERVED_MASK)
2121 return 1;
2122
2123 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2124 data & KVM_STEAL_VALID_BITS,
2125 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2126 return 1;
2127
2128 vcpu->arch.st.msr_val = data;
2129
2130 if (!(data & KVM_MSR_ENABLED))
2131 break;
2132
2133 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2134
2135 preempt_disable();
2136 accumulate_steal_time(vcpu);
2137 preempt_enable();
2138
2139 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2140
2141 break;
ae7a2a3f
MT		 2142 case MSR_KVM_PV_EOI_EN:
2143 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2144 return 1;
2145 break;
c9aaa895 2146
890ca9ae
HY		 2147 case MSR_IA32_MCG_CTL:
2148 case MSR_IA32_MCG_STATUS:
2149 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2150 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2151
2152 /* Performance counters are not protected by a CPUID bit,
2153 * so we should check all of them in the generic path for the sake of
2154 * cross vendor migration.
2155 * Writing a zero into the event select MSRs disables them,
2156 * which we perfectly emulate ;-). Any other value should be at least
2157 * reported, some guests depend on them.
2158 */
71db6023
AP		 2159 case MSR_K7_EVNTSEL0:
2160 case MSR_K7_EVNTSEL1:
2161 case MSR_K7_EVNTSEL2:
2162 case MSR_K7_EVNTSEL3:
2163 if (data != 0)
a737f256
CD		 2164 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2165 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2166 break;
2167 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2168 * so we ignore writes to make it happy.
2169 */
71db6023
AP		 2170 case MSR_K7_PERFCTR0:
2171 case MSR_K7_PERFCTR1:
2172 case MSR_K7_PERFCTR2:
2173 case MSR_K7_PERFCTR3:
a737f256
CD		 2174 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2175 "0x%x data 0x%llx\n", msr, data);
71db6023 2176 break;
5753785f
GN		 2177 case MSR_P6_PERFCTR0:
2178 case MSR_P6_PERFCTR1:
2179 pr = true;
2180 case MSR_P6_EVNTSEL0:
2181 case MSR_P6_EVNTSEL1:
2182 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2183 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2184
2185 if (pr || data != 0)
a737f256
CD		 2186 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2187 "0x%x data 0x%llx\n", msr, data);
5753785f 2188 break;
84e0cefa
JS		 2189 case MSR_K7_CLK_CTL:
2190 /*
2191 * Ignore all writes to this no longer documented MSR.
2192 * Writes are only relevant for old K7 processors,
2193 * all pre-dating SVM, but a recommended workaround from
4a969980 2194 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2195 * affected processor models on the command line, hence
2196 * the need to ignore the workaround.
2197 */
2198 break;
55cd8e5a
GN		 2199 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2200 if (kvm_hv_msr_partition_wide(msr)) {
2201 int r;
2202 mutex_lock(&vcpu->kvm->lock);
2203 r = set_msr_hyperv_pw(vcpu, msr, data);
2204 mutex_unlock(&vcpu->kvm->lock);
2205 return r;
2206 } else
2207 return set_msr_hyperv(vcpu, msr, data);
2208 break;
91c9c3ed 2209 case MSR_IA32_BBL_CR_CTL3:
2210 /* Drop writes to this legacy MSR -- see rdmsr
2211 * counterpart for further detail.
2212 */
a737f256 2213 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2214 break;
2b036c6b
BO		 2215 case MSR_AMD64_OSVW_ID_LENGTH:
2216 if (!guest_cpuid_has_osvw(vcpu))
2217 return 1;
2218 vcpu->arch.osvw.length = data;
2219 break;
2220 case MSR_AMD64_OSVW_STATUS:
2221 if (!guest_cpuid_has_osvw(vcpu))
2222 return 1;
2223 vcpu->arch.osvw.status = data;
2224 break;
15c4a640 2225 default:
ffde22ac
ES		 2226 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2227 return xen_hvm_config(vcpu, data);
f5132b01 2228 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2229 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2230 if (!ignore_msrs) {
a737f256
CD		 2231 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2232 msr, data);
ed85c068
AP		 2233 return 1;
2234 } else {
a737f256
CD		 2235 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2236 msr, data);
ed85c068
AP		 2237 break;
2238 }
15c4a640
CO		 2239 }
2240 return 0;
2241}
2242EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2243
2244
2245/*
2246 * Reads an msr value (of 'msr_index') into 'pdata'.
2247 * Returns 0 on success, non-0 otherwise.
2248 * Assumes vcpu_load() was already called.
2249 */
2250int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2251{
2252 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2253}
2254
9ba075a6
AK		 2255static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2256{
0bed3b56
SY		 2257 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2258
9ba075a6
AK		 2259 if (!msr_mtrr_valid(msr))
2260 return 1;
2261
0bed3b56
SY		 2262 if (msr == MSR_MTRRdefType)
2263 *pdata = vcpu->arch.mtrr_state.def_type +
2264 (vcpu->arch.mtrr_state.enabled << 10);
2265 else if (msr == MSR_MTRRfix64K_00000)
2266 *pdata = p[0];
2267 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2268 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2269 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2270 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2271 else if (msr == MSR_IA32_CR_PAT)
2272 *pdata = vcpu->arch.pat;
2273 else { /* Variable MTRRs */
2274 int idx, is_mtrr_mask;
2275 u64 *pt;
2276
2277 idx = (msr - 0x200) / 2;
2278 is_mtrr_mask = msr - 0x200 - 2 * idx;
2279 if (!is_mtrr_mask)
2280 pt =
2281 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2282 else
2283 pt =
2284 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2285 *pdata = *pt;
2286 }
2287
9ba075a6
AK		 2288 return 0;
2289}
2290
890ca9ae 2291static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2292{
2293 u64 data;
890ca9ae
HY		 2294 u64 mcg_cap = vcpu->arch.mcg_cap;
2295 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2296
2297 switch (msr) {
15c4a640
CO		 2298 case MSR_IA32_P5_MC_ADDR:
2299 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2300 data = 0;
2301 break;
15c4a640 2302 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2303 data = vcpu->arch.mcg_cap;
2304 break;
c7ac679c 2305 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2306 if (!(mcg_cap & MCG_CTL_P))
2307 return 1;
2308 data = vcpu->arch.mcg_ctl;
2309 break;
2310 case MSR_IA32_MCG_STATUS:
2311 data = vcpu->arch.mcg_status;
2312 break;
2313 default:
2314 if (msr >= MSR_IA32_MC0_CTL &&
2315 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2316 u32 offset = msr - MSR_IA32_MC0_CTL;
2317 data = vcpu->arch.mce_banks[offset];
2318 break;
2319 }
2320 return 1;
2321 }
2322 *pdata = data;
2323 return 0;
2324}
2325
55cd8e5a
GN		 2326static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327{
2328 u64 data = 0;
2329 struct kvm *kvm = vcpu->kvm;
2330
2331 switch (msr) {
2332 case HV_X64_MSR_GUEST_OS_ID:
2333 data = kvm->arch.hv_guest_os_id;
2334 break;
2335 case HV_X64_MSR_HYPERCALL:
2336 data = kvm->arch.hv_hypercall;
2337 break;
e984097b
VR		 2338 case HV_X64_MSR_TIME_REF_COUNT: {
2339 data =
2340 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2341 break;
2342 }
2343 case HV_X64_MSR_REFERENCE_TSC:
2344 data = kvm->arch.hv_tsc_page;
2345 break;
55cd8e5a 2346 default:
a737f256 2347 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2348 return 1;
2349 }
2350
2351 *pdata = data;
2352 return 0;
2353}
2354
2355static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2356{
2357 u64 data = 0;
2358
2359 switch (msr) {
2360 case HV_X64_MSR_VP_INDEX: {
2361 int r;
2362 struct kvm_vcpu *v;
684851a1
TY		 2363 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2364 if (v == vcpu) {
55cd8e5a 2365 data = r;
684851a1
TY		 2366 break;
2367 }
2368 }
55cd8e5a
GN		 2369 break;
2370 }
10388a07
GN		 2371 case HV_X64_MSR_EOI:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2373 case HV_X64_MSR_ICR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2375 case HV_X64_MSR_TPR:
2376 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2377 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2378 data = vcpu->arch.hv_vapic;
2379 break;
55cd8e5a 2380 default:
a737f256 2381 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2382 return 1;
2383 }
2384 *pdata = data;
2385 return 0;
2386}
2387
890ca9ae
HY		 2388int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2389{
2390 u64 data;
2391
2392 switch (msr) {
890ca9ae 2393 case MSR_IA32_PLATFORM_ID:
15c4a640 2394 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2395 case MSR_IA32_DEBUGCTLMSR:
2396 case MSR_IA32_LASTBRANCHFROMIP:
2397 case MSR_IA32_LASTBRANCHTOIP:
2398 case MSR_IA32_LASTINTFROMIP:
2399 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2400 case MSR_K8_SYSCFG:
2401 case MSR_K7_HWCR:
61a6bd67 2402 case MSR_VM_HSAVE_PA:
9e699624 2403 case MSR_K7_EVNTSEL0:
1f3ee616 2404 case MSR_K7_PERFCTR0:
1fdbd48c 2405 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2406 case MSR_AMD64_NB_CFG:
f7c6d140 2407 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2408 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2409 data = 0;
2410 break;
5753785f
GN		 2411 case MSR_P6_PERFCTR0:
2412 case MSR_P6_PERFCTR1:
2413 case MSR_P6_EVNTSEL0:
2414 case MSR_P6_EVNTSEL1:
2415 if (kvm_pmu_msr(vcpu, msr))
2416 return kvm_pmu_get_msr(vcpu, msr, pdata);
2417 data = 0;
2418 break;
742bc670
MT		 2419 case MSR_IA32_UCODE_REV:
2420 data = 0x100000000ULL;
2421 break;
9ba075a6
AK		 2422 case MSR_MTRRcap:
2423 data = 0x500 | KVM_NR_VAR_MTRR;
2424 break;
2425 case 0x200 ... 0x2ff:
2426 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2427 case 0xcd: /* fsb frequency */
2428 data = 3;
2429 break;
7b914098
JS		 2430 /*
2431 * MSR_EBC_FREQUENCY_ID
2432 * Conservative value valid for even the basic CPU models.
2433 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2434 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2435 * and 266MHz for model 3, or 4. Set Core Clock
2436 * Frequency to System Bus Frequency Ratio to 1 (bits
2437 * 31:24) even though these are only valid for CPU
2438 * models > 2, however guests may end up dividing or
2439 * multiplying by zero otherwise.
2440 */
2441 case MSR_EBC_FREQUENCY_ID:
2442 data = 1 << 24;
2443 break;
15c4a640
CO		 2444 case MSR_IA32_APICBASE:
2445 data = kvm_get_apic_base(vcpu);
2446 break;
0105d1a5
GN		 2447 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2448 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2449 break;
a3e06bbe
LJ		 2450 case MSR_IA32_TSCDEADLINE:
2451 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2452 break;
ba904635
WA		 2453 case MSR_IA32_TSC_ADJUST:
2454 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2455 break;
15c4a640 2456 case MSR_IA32_MISC_ENABLE:
ad312c7c 2457 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2458 break;
847f0ad8
AG		 2459 case MSR_IA32_PERF_STATUS:
2460 /* TSC increment by tick */
2461 data = 1000ULL;
2462 /* CPU multiplier */
2463 data |= (((uint64_t)4ULL) << 40);
2464 break;
15c4a640 2465 case MSR_EFER:
f6801dff 2466 data = vcpu->arch.efer;
15c4a640 2467 break;
18068523 2468 case MSR_KVM_WALL_CLOCK:
11c6bffa 2469 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2470 data = vcpu->kvm->arch.wall_clock;
2471 break;
2472 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2473 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2474 data = vcpu->arch.time;
2475 break;
344d9588
GN		 2476 case MSR_KVM_ASYNC_PF_EN:
2477 data = vcpu->arch.apf.msr_val;
2478 break;
c9aaa895
GC		 2479 case MSR_KVM_STEAL_TIME:
2480 data = vcpu->arch.st.msr_val;
2481 break;
1d92128f
MT		 2482 case MSR_KVM_PV_EOI_EN:
2483 data = vcpu->arch.pv_eoi.msr_val;
2484 break;
890ca9ae
HY		 2485 case MSR_IA32_P5_MC_ADDR:
2486 case MSR_IA32_P5_MC_TYPE:
2487 case MSR_IA32_MCG_CAP:
2488 case MSR_IA32_MCG_CTL:
2489 case MSR_IA32_MCG_STATUS:
2490 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2491 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2492 case MSR_K7_CLK_CTL:
2493 /*
2494 * Provide expected ramp-up count for K7. All other
2495 * are set to zero, indicating minimum divisors for
2496 * every field.
2497 *
2498 * This prevents guest kernels on AMD host with CPU
2499 * type 6, model 8 and higher from exploding due to
2500 * the rdmsr failing.
2501 */
2502 data = 0x20000000;
2503 break;
55cd8e5a
GN		 2504 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2505 if (kvm_hv_msr_partition_wide(msr)) {
2506 int r;
2507 mutex_lock(&vcpu->kvm->lock);
2508 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2509 mutex_unlock(&vcpu->kvm->lock);
2510 return r;
2511 } else
2512 return get_msr_hyperv(vcpu, msr, pdata);
2513 break;
91c9c3ed 2514 case MSR_IA32_BBL_CR_CTL3:
2515 /* This legacy MSR exists but isn't fully documented in current
2516 * silicon. It is however accessed by winxp in very narrow
2517 * scenarios where it sets bit #19, itself documented as
2518 * a "reserved" bit. Best effort attempt to source coherent
2519 * read data here should the balance of the register be
2520 * interpreted by the guest:
2521 *
2522 * L2 cache control register 3: 64GB range, 256KB size,
2523 * enabled, latency 0x1, configured
2524 */
2525 data = 0xbe702111;
2526 break;
2b036c6b
BO		 2527 case MSR_AMD64_OSVW_ID_LENGTH:
2528 if (!guest_cpuid_has_osvw(vcpu))
2529 return 1;
2530 data = vcpu->arch.osvw.length;
2531 break;
2532 case MSR_AMD64_OSVW_STATUS:
2533 if (!guest_cpuid_has_osvw(vcpu))
2534 return 1;
2535 data = vcpu->arch.osvw.status;
2536 break;
15c4a640 2537 default:
f5132b01
GN		 2538 if (kvm_pmu_msr(vcpu, msr))
2539 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2540 if (!ignore_msrs) {
a737f256 2541 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2542 return 1;
2543 } else {
a737f256 2544 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2545 data = 0;
2546 }
2547 break;
15c4a640
CO		 2548 }
2549 *pdata = data;
2550 return 0;
2551}
2552EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2553
313a3dc7
CO		 2554/*
2555 * Read or write a bunch of msrs. All parameters are kernel addresses.
2556 *
2557 * @return number of msrs set successfully.
2558 */
2559static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2560 struct kvm_msr_entry *entries,
2561 int (*do_msr)(struct kvm_vcpu *vcpu,
2562 unsigned index, u64 *data))
2563{
f656ce01 2564 int i, idx;
313a3dc7 2565
f656ce01 2566 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2567 for (i = 0; i < msrs->nmsrs; ++i)
2568 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2569 break;
f656ce01 2570 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2571
313a3dc7
CO		 2572 return i;
2573}
2574
2575/*
2576 * Read or write a bunch of msrs. Parameters are user addresses.
2577 *
2578 * @return number of msrs set successfully.
2579 */
2580static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2581 int (*do_msr)(struct kvm_vcpu *vcpu,
2582 unsigned index, u64 *data),
2583 int writeback)
2584{
2585 struct kvm_msrs msrs;
2586 struct kvm_msr_entry *entries;
2587 int r, n;
2588 unsigned size;
2589
2590 r = -EFAULT;
2591 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2592 goto out;
2593
2594 r = -E2BIG;
2595 if (msrs.nmsrs >= MAX_IO_MSRS)
2596 goto out;
2597
313a3dc7 2598 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2599 entries = memdup_user(user_msrs->entries, size);
2600 if (IS_ERR(entries)) {
2601 r = PTR_ERR(entries);
313a3dc7 2602 goto out;
ff5c2c03 2603 }
313a3dc7
CO		 2604
2605 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2606 if (r < 0)
2607 goto out_free;
2608
2609 r = -EFAULT;
2610 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2611 goto out_free;
2612
2613 r = n;
2614
2615out_free:
7a73c028 2616 kfree(entries);
313a3dc7
CO		 2617out:
2618 return r;
2619}
2620
018d00d2
ZX		 2621int kvm_dev_ioctl_check_extension(long ext)
2622{
2623 int r;
2624
2625 switch (ext) {
2626 case KVM_CAP_IRQCHIP:
2627 case KVM_CAP_HLT:
2628 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2629 case KVM_CAP_SET_TSS_ADDR:
07716717 2630 case KVM_CAP_EXT_CPUID:
9c15bb1d 2631 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2632 case KVM_CAP_CLOCKSOURCE:
7837699f 2633 case KVM_CAP_PIT:
a28e4f5a 2634 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2635 case KVM_CAP_MP_STATE:
ed848624 2636 case KVM_CAP_SYNC_MMU:
a355c85c 2637 case KVM_CAP_USER_NMI:
52d939a0 2638 case KVM_CAP_REINJECT_CONTROL:
4925663a 2639 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2640 case KVM_CAP_IRQFD:
d34e6b17 2641 case KVM_CAP_IOEVENTFD:
c5ff41ce 2642 case KVM_CAP_PIT2:
e9f42757 2643 case KVM_CAP_PIT_STATE2:
b927a3ce 2644 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2645 case KVM_CAP_XEN_HVM:
afbcf7ab 2646 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2647 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2648 case KVM_CAP_HYPERV:
10388a07 2649 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2650 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2651 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2652 case KVM_CAP_DEBUGREGS:
d2be1651 2653 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2654 case KVM_CAP_XSAVE:
344d9588 2655 case KVM_CAP_ASYNC_PF:
92a1f12d 2656 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2657 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2658 case KVM_CAP_READONLY_MEM:
5f66b620 2659 case KVM_CAP_HYPERV_TIME:
100943c5 2660 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2661#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2662 case KVM_CAP_ASSIGN_DEV_IRQ:
2663 case KVM_CAP_PCI_2_3:
2664#endif
018d00d2
ZX		 2665 r = 1;
2666 break;
542472b5
LV		 2667 case KVM_CAP_COALESCED_MMIO:
2668 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2669 break;
774ead3a
AK		 2670 case KVM_CAP_VAPIC:
2671 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2672 break;
f725230a 2673 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2674 r = KVM_SOFT_MAX_VCPUS;
2675 break;
2676 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2677 r = KVM_MAX_VCPUS;
2678 break;
a988b910 2679 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2680 r = KVM_USER_MEM_SLOTS;
a988b910 2681 break;
a68a6a72
MT		 2682 case KVM_CAP_PV_MMU: /* obsolete */
2683 r = 0;
2f333bcb 2684 break;
4cee4b72 2685#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2686 case KVM_CAP_IOMMU:
a1b60c1c 2687 r = iommu_present(&pci_bus_type);
62c476c7 2688 break;
4cee4b72 2689#endif
890ca9ae
HY		 2690 case KVM_CAP_MCE:
2691 r = KVM_MAX_MCE_BANKS;
2692 break;
2d5b5a66
SY		 2693 case KVM_CAP_XCRS:
2694 r = cpu_has_xsave;
2695 break;
92a1f12d
JR		 2696 case KVM_CAP_TSC_CONTROL:
2697 r = kvm_has_tsc_control;
2698 break;
4d25a066
JK		 2699 case KVM_CAP_TSC_DEADLINE_TIMER:
2700 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2701 break;
018d00d2
ZX		 2702 default:
2703 r = 0;
2704 break;
2705 }
2706 return r;
2707
2708}
2709
043405e1
CO		 2710long kvm_arch_dev_ioctl(struct file *filp,
2711 unsigned int ioctl, unsigned long arg)
2712{
2713 void __user *argp = (void __user *)arg;
2714 long r;
2715
2716 switch (ioctl) {
2717 case KVM_GET_MSR_INDEX_LIST: {
2718 struct kvm_msr_list __user *user_msr_list = argp;
2719 struct kvm_msr_list msr_list;
2720 unsigned n;
2721
2722 r = -EFAULT;
2723 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2724 goto out;
2725 n = msr_list.nmsrs;
2726 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2727 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2728 goto out;
2729 r = -E2BIG;
e125e7b6 2730 if (n < msr_list.nmsrs)
043405e1
CO		 2731 goto out;
2732 r = -EFAULT;
2733 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2734 num_msrs_to_save * sizeof(u32)))
2735 goto out;
e125e7b6 2736 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2737 &emulated_msrs,
2738 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2739 goto out;
2740 r = 0;
2741 break;
2742 }
9c15bb1d
BP		 2743 case KVM_GET_SUPPORTED_CPUID:
2744 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2745 struct kvm_cpuid2 __user *cpuid_arg = argp;
2746 struct kvm_cpuid2 cpuid;
2747
2748 r = -EFAULT;
2749 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2750 goto out;
9c15bb1d
BP		 2751
2752 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2753 ioctl);
674eea0f
AK		 2754 if (r)
2755 goto out;
2756
2757 r = -EFAULT;
2758 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2759 goto out;
2760 r = 0;
2761 break;
2762 }
890ca9ae
HY		 2763 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2764 u64 mce_cap;
2765
2766 mce_cap = KVM_MCE_CAP_SUPPORTED;
2767 r = -EFAULT;
2768 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2769 goto out;
2770 r = 0;
2771 break;
2772 }
043405e1
CO		 2773 default:
2774 r = -EINVAL;
2775 }
2776out:
2777 return r;
2778}
2779
f5f48ee1
SY		 2780static void wbinvd_ipi(void *garbage)
2781{
2782 wbinvd();
2783}
2784
2785static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2786{
e0f0bbc5 2787 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2788}
2789
313a3dc7
CO		 2790void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2791{
f5f48ee1
SY		 2792 /* Address WBINVD may be executed by guest */
2793 if (need_emulate_wbinvd(vcpu)) {
2794 if (kvm_x86_ops->has_wbinvd_exit())
2795 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2796 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2797 smp_call_function_single(vcpu->cpu,
2798 wbinvd_ipi, NULL, 1);
2799 }
2800
313a3dc7 2801 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2802
0dd6a6ed
ZA		 2803 /* Apply any externally detected TSC adjustments (due to suspend) */
2804 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2805 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2806 vcpu->arch.tsc_offset_adjustment = 0;
2807 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2808 }
8f6055cb 2809
48434c20 2810 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2811 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2812 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2813 if (tsc_delta < 0)
2814 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2815 if (check_tsc_unstable()) {
b183aa58
ZA		 2816 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2817 vcpu->arch.last_guest_tsc);
2818 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2819 vcpu->arch.tsc_catchup = 1;
c285545f 2820 }
d98d07ca
MT		 2821 /*
2822 * On a host with synchronized TSC, there is no need to update
2823 * kvmclock on vcpu->cpu migration
2824 */
2825 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2826 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2827 if (vcpu->cpu != cpu)
2828 kvm_migrate_timers(vcpu);
e48672fa 2829 vcpu->cpu = cpu;
6b7d7e76 2830 }
c9aaa895
GC		 2831
2832 accumulate_steal_time(vcpu);
2833 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2834}
2835
2836void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2837{
02daab21 2838 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2839 kvm_put_guest_fpu(vcpu);
6f526ec5 2840 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2841}
2842
313a3dc7
CO		 2843static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2844 struct kvm_lapic_state *s)
2845{
5a71785d 2846 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2847 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2848
2849 return 0;
2850}
2851
2852static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2853 struct kvm_lapic_state *s)
2854{
64eb0620 2855 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2856 update_cr8_intercept(vcpu);
313a3dc7
CO		 2857
2858 return 0;
2859}
2860
f77bc6a4
ZX		 2861static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2862 struct kvm_interrupt *irq)
2863{
02cdb50f 2864 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2865 return -EINVAL;
2866 if (irqchip_in_kernel(vcpu->kvm))
2867 return -ENXIO;
f77bc6a4 2868
66fd3f7f 2869 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2870 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2871
f77bc6a4
ZX		 2872 return 0;
2873}
2874
c4abb7c9
JK		 2875static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2876{
c4abb7c9 2877 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2878
2879 return 0;
2880}
2881
b209749f
AK		 2882static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2883 struct kvm_tpr_access_ctl *tac)
2884{
2885 if (tac->flags)
2886 return -EINVAL;
2887 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2888 return 0;
2889}
2890
890ca9ae
HY		 2891static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2892 u64 mcg_cap)
2893{
2894 int r;
2895 unsigned bank_num = mcg_cap & 0xff, bank;
2896
2897 r = -EINVAL;
a9e38c3e 2898 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2899 goto out;
2900 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2901 goto out;
2902 r = 0;
2903 vcpu->arch.mcg_cap = mcg_cap;
2904 /* Init IA32_MCG_CTL to all 1s */
2905 if (mcg_cap & MCG_CTL_P)
2906 vcpu->arch.mcg_ctl = ~(u64)0;
2907 /* Init IA32_MCi_CTL to all 1s */
2908 for (bank = 0; bank < bank_num; bank++)
2909 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2910out:
2911 return r;
2912}
2913
2914static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2915 struct kvm_x86_mce *mce)
2916{
2917 u64 mcg_cap = vcpu->arch.mcg_cap;
2918 unsigned bank_num = mcg_cap & 0xff;
2919 u64 *banks = vcpu->arch.mce_banks;
2920
2921 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2922 return -EINVAL;
2923 /*
2924 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2925 * reporting is disabled
2926 */
2927 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2928 vcpu->arch.mcg_ctl != ~(u64)0)
2929 return 0;
2930 banks += 4 * mce->bank;
2931 /*
2932 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2933 * reporting is disabled for the bank
2934 */
2935 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2936 return 0;
2937 if (mce->status & MCI_STATUS_UC) {
2938 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2939 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2940 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2941 return 0;
2942 }
2943 if (banks[1] & MCI_STATUS_VAL)
2944 mce->status |= MCI_STATUS_OVER;
2945 banks[2] = mce->addr;
2946 banks[3] = mce->misc;
2947 vcpu->arch.mcg_status = mce->mcg_status;
2948 banks[1] = mce->status;
2949 kvm_queue_exception(vcpu, MC_VECTOR);
2950 } else if (!(banks[1] & MCI_STATUS_VAL)
2951 || !(banks[1] & MCI_STATUS_UC)) {
2952 if (banks[1] & MCI_STATUS_VAL)
2953 mce->status |= MCI_STATUS_OVER;
2954 banks[2] = mce->addr;
2955 banks[3] = mce->misc;
2956 banks[1] = mce->status;
2957 } else
2958 banks[1] |= MCI_STATUS_OVER;
2959 return 0;
2960}
2961
3cfc3092
JK		 2962static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964{
7460fb4a 2965 process_nmi(vcpu);
03b82a30
JK		 2966 events->exception.injected =
2967 vcpu->arch.exception.pending &&
2968 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2969 events->exception.nr = vcpu->arch.exception.nr;
2970 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2971 events->exception.pad = 0;
3cfc3092
JK		 2972 events->exception.error_code = vcpu->arch.exception.error_code;
2973
03b82a30
JK		 2974 events->interrupt.injected =
2975 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2976 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2977 events->interrupt.soft = 0;
48005f64
JK		 2978 events->interrupt.shadow =
2979 kvm_x86_ops->get_interrupt_shadow(vcpu,
2980 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2981
2982 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2983 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2984 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2985 events->nmi.pad = 0;
3cfc3092 2986
66450a21 2987 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2988
dab4b911 2989 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2990 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2991 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2992}
2993
2994static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2995 struct kvm_vcpu_events *events)
2996{
dab4b911 2997 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2998 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2999 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3000 return -EINVAL;
3001
7460fb4a 3002 process_nmi(vcpu);
3cfc3092
JK		 3003 vcpu->arch.exception.pending = events->exception.injected;
3004 vcpu->arch.exception.nr = events->exception.nr;
3005 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3006 vcpu->arch.exception.error_code = events->exception.error_code;
3007
3008 vcpu->arch.interrupt.pending = events->interrupt.injected;
3009 vcpu->arch.interrupt.nr = events->interrupt.nr;
3010 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3011 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3012 kvm_x86_ops->set_interrupt_shadow(vcpu,
3013 events->interrupt.shadow);
3cfc3092
JK		 3014
3015 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3016 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3017 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3018 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3019
66450a21
JK		 3020 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3021 kvm_vcpu_has_lapic(vcpu))
3022 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3023
3842d135
AK		 3024 kvm_make_request(KVM_REQ_EVENT, vcpu);
3025
3cfc3092
JK		 3026 return 0;
3027}
3028
a1efbe77
JK		 3029static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3030 struct kvm_debugregs *dbgregs)
3031{
73aaf249
JK		 3032 unsigned long val;
3033
a1efbe77 3034 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3035 _kvm_get_dr(vcpu, 6, &val);
3036 dbgregs->dr6 = val;
a1efbe77
JK		 3037 dbgregs->dr7 = vcpu->arch.dr7;
3038 dbgregs->flags = 0;
97e69aa6 3039 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3040}
3041
3042static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3043 struct kvm_debugregs *dbgregs)
3044{
3045 if (dbgregs->flags)
3046 return -EINVAL;
3047
a1efbe77
JK		 3048 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3049 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3050 kvm_update_dr6(vcpu);
a1efbe77 3051 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3052 kvm_update_dr7(vcpu);
a1efbe77 3053
a1efbe77
JK		 3054 return 0;
3055}
3056
2d5b5a66
SY		 3057static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3058 struct kvm_xsave *guest_xsave)
3059{
4344ee98 3060 if (cpu_has_xsave) {
2d5b5a66
SY		 3061 memcpy(guest_xsave->region,
3062 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3063 vcpu->arch.guest_xstate_size);
3064 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3065 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3066 } else {
2d5b5a66
SY		 3067 memcpy(guest_xsave->region,
3068 &vcpu->arch.guest_fpu.state->fxsave,
3069 sizeof(struct i387_fxsave_struct));
3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3071 XSTATE_FPSSE;
3072 }
3073}
3074
3075static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3076 struct kvm_xsave *guest_xsave)
3077{
3078 u64 xstate_bv =
3079 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3080
d7876f1b
PB		 3081 if (cpu_has_xsave) {
3082 /*
3083 * Here we allow setting states that are not present in
3084 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3085 * with old userspace.
3086 */
4ff41732 3087 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3088 return -EINVAL;
2d5b5a66 3089 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3090 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3091 } else {
2d5b5a66
SY		 3092 if (xstate_bv & ~XSTATE_FPSSE)
3093 return -EINVAL;
3094 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3095 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3096 }
3097 return 0;
3098}
3099
3100static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3101 struct kvm_xcrs *guest_xcrs)
3102{
3103 if (!cpu_has_xsave) {
3104 guest_xcrs->nr_xcrs = 0;
3105 return;
3106 }
3107
3108 guest_xcrs->nr_xcrs = 1;
3109 guest_xcrs->flags = 0;
3110 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3111 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3112}
3113
3114static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3115 struct kvm_xcrs *guest_xcrs)
3116{
3117 int i, r = 0;
3118
3119 if (!cpu_has_xsave)
3120 return -EINVAL;
3121
3122 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3123 return -EINVAL;
3124
3125 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3126 /* Only support XCR0 currently */
c67a04cb 3127 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3128 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3129 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3130 break;
3131 }
3132 if (r)
3133 r = -EINVAL;
3134 return r;
3135}
3136
1c0b28c2
EM		 3137/*
3138 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3139 * stopped by the hypervisor. This function will be called from the host only.
3140 * EINVAL is returned when the host attempts to set the flag for a guest that
3141 * does not support pv clocks.
3142 */
3143static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3144{
0b79459b 3145 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3146 return -EINVAL;
51d59c6b 3147 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3148 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3149 return 0;
3150}
3151
313a3dc7
CO		 3152long kvm_arch_vcpu_ioctl(struct file *filp,
3153 unsigned int ioctl, unsigned long arg)
3154{
3155 struct kvm_vcpu *vcpu = filp->private_data;
3156 void __user *argp = (void __user *)arg;
3157 int r;
d1ac91d8
AK		 3158 union {
3159 struct kvm_lapic_state *lapic;
3160 struct kvm_xsave *xsave;
3161 struct kvm_xcrs *xcrs;
3162 void *buffer;
3163 } u;
3164
3165 u.buffer = NULL;
313a3dc7
CO		 3166 switch (ioctl) {
3167 case KVM_GET_LAPIC: {
2204ae3c
MT		 3168 r = -EINVAL;
3169 if (!vcpu->arch.apic)
3170 goto out;
d1ac91d8 3171 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3172
b772ff36 3173 r = -ENOMEM;
d1ac91d8 3174 if (!u.lapic)
b772ff36 3175 goto out;
d1ac91d8 3176 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3177 if (r)
3178 goto out;
3179 r = -EFAULT;
d1ac91d8 3180 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3181 goto out;
3182 r = 0;
3183 break;
3184 }
3185 case KVM_SET_LAPIC: {
2204ae3c
MT		 3186 r = -EINVAL;
3187 if (!vcpu->arch.apic)
3188 goto out;
ff5c2c03 3189 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3190 if (IS_ERR(u.lapic))
3191 return PTR_ERR(u.lapic);
ff5c2c03 3192
d1ac91d8 3193 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3194 break;
3195 }
f77bc6a4
ZX		 3196 case KVM_INTERRUPT: {
3197 struct kvm_interrupt irq;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&irq, argp, sizeof irq))
3201 goto out;
3202 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3203 break;
3204 }
c4abb7c9
JK		 3205 case KVM_NMI: {
3206 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3207 break;
3208 }
313a3dc7
CO		 3209 case KVM_SET_CPUID: {
3210 struct kvm_cpuid __user *cpuid_arg = argp;
3211 struct kvm_cpuid cpuid;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3215 goto out;
3216 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3217 break;
3218 }
07716717
DK		 3219 case KVM_SET_CPUID2: {
3220 struct kvm_cpuid2 __user *cpuid_arg = argp;
3221 struct kvm_cpuid2 cpuid;
3222
3223 r = -EFAULT;
3224 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3225 goto out;
3226 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3227 cpuid_arg->entries);
07716717
DK		 3228 break;
3229 }
3230 case KVM_GET_CPUID2: {
3231 struct kvm_cpuid2 __user *cpuid_arg = argp;
3232 struct kvm_cpuid2 cpuid;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3236 goto out;
3237 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3238 cpuid_arg->entries);
07716717
DK		 3239 if (r)
3240 goto out;
3241 r = -EFAULT;
3242 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3243 goto out;
3244 r = 0;
3245 break;
3246 }
313a3dc7
CO		 3247 case KVM_GET_MSRS:
3248 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3249 break;
3250 case KVM_SET_MSRS:
3251 r = msr_io(vcpu, argp, do_set_msr, 0);
3252 break;
b209749f
AK		 3253 case KVM_TPR_ACCESS_REPORTING: {
3254 struct kvm_tpr_access_ctl tac;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&tac, argp, sizeof tac))
3258 goto out;
3259 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3260 if (r)
3261 goto out;
3262 r = -EFAULT;
3263 if (copy_to_user(argp, &tac, sizeof tac))
3264 goto out;
3265 r = 0;
3266 break;
3267 };
b93463aa
AK		 3268 case KVM_SET_VAPIC_ADDR: {
3269 struct kvm_vapic_addr va;
3270
3271 r = -EINVAL;
3272 if (!irqchip_in_kernel(vcpu->kvm))
3273 goto out;
3274 r = -EFAULT;
3275 if (copy_from_user(&va, argp, sizeof va))
3276 goto out;
fda4e2e8 3277 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3278 break;
3279 }
890ca9ae
HY		 3280 case KVM_X86_SETUP_MCE: {
3281 u64 mcg_cap;
3282
3283 r = -EFAULT;
3284 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3285 goto out;
3286 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3287 break;
3288 }
3289 case KVM_X86_SET_MCE: {
3290 struct kvm_x86_mce mce;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&mce, argp, sizeof mce))
3294 goto out;
3295 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3296 break;
3297 }
3cfc3092
JK		 3298 case KVM_GET_VCPU_EVENTS: {
3299 struct kvm_vcpu_events events;
3300
3301 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3302
3303 r = -EFAULT;
3304 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3305 break;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_SET_VCPU_EVENTS: {
3310 struct kvm_vcpu_events events;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3314 break;
3315
3316 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3317 break;
3318 }
a1efbe77
JK		 3319 case KVM_GET_DEBUGREGS: {
3320 struct kvm_debugregs dbgregs;
3321
3322 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3323
3324 r = -EFAULT;
3325 if (copy_to_user(argp, &dbgregs,
3326 sizeof(struct kvm_debugregs)))
3327 break;
3328 r = 0;
3329 break;
3330 }
3331 case KVM_SET_DEBUGREGS: {
3332 struct kvm_debugregs dbgregs;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&dbgregs, argp,
3336 sizeof(struct kvm_debugregs)))
3337 break;
3338
3339 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3340 break;
3341 }
2d5b5a66 3342 case KVM_GET_XSAVE: {
d1ac91d8 3343 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3344 r = -ENOMEM;
d1ac91d8 3345 if (!u.xsave)
2d5b5a66
SY		 3346 break;
3347
d1ac91d8 3348 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3349
3350 r = -EFAULT;
d1ac91d8 3351 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3352 break;
3353 r = 0;
3354 break;
3355 }
3356 case KVM_SET_XSAVE: {
ff5c2c03 3357 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3358 if (IS_ERR(u.xsave))
3359 return PTR_ERR(u.xsave);
2d5b5a66 3360
d1ac91d8 3361 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3362 break;
3363 }
3364 case KVM_GET_XCRS: {
d1ac91d8 3365 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3366 r = -ENOMEM;
d1ac91d8 3367 if (!u.xcrs)
2d5b5a66
SY		 3368 break;
3369
d1ac91d8 3370 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3371
3372 r = -EFAULT;
d1ac91d8 3373 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3374 sizeof(struct kvm_xcrs)))
3375 break;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_XCRS: {
ff5c2c03 3380 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3381 if (IS_ERR(u.xcrs))
3382 return PTR_ERR(u.xcrs);
2d5b5a66 3383
d1ac91d8 3384 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3385 break;
3386 }
92a1f12d
JR		 3387 case KVM_SET_TSC_KHZ: {
3388 u32 user_tsc_khz;
3389
3390 r = -EINVAL;
92a1f12d
JR		 3391 user_tsc_khz = (u32)arg;
3392
3393 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3394 goto out;
3395
cc578287
ZA		 3396 if (user_tsc_khz == 0)
3397 user_tsc_khz = tsc_khz;
3398
3399 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3400
3401 r = 0;
3402 goto out;
3403 }
3404 case KVM_GET_TSC_KHZ: {
cc578287 3405 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3406 goto out;
3407 }
1c0b28c2
EM		 3408 case KVM_KVMCLOCK_CTRL: {
3409 r = kvm_set_guest_paused(vcpu);
3410 goto out;
3411 }
313a3dc7
CO		 3412 default:
3413 r = -EINVAL;
3414 }
3415out:
d1ac91d8 3416 kfree(u.buffer);
313a3dc7
CO		 3417 return r;
3418}
3419
5b1c1493
CO		 3420int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3421{
3422 return VM_FAULT_SIGBUS;
3423}
3424
1fe779f8
CO		 3425static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3426{
3427 int ret;
3428
3429 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3430 return -EINVAL;
1fe779f8
CO		 3431 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3432 return ret;
3433}
3434
b927a3ce
SY		 3435static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3436 u64 ident_addr)
3437{
3438 kvm->arch.ept_identity_map_addr = ident_addr;
3439 return 0;
3440}
3441
1fe779f8
CO		 3442static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3443 u32 kvm_nr_mmu_pages)
3444{
3445 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3446 return -EINVAL;
3447
79fac95e 3448 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3449
3450 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3451 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3452
79fac95e 3453 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3454 return 0;
3455}
3456
3457static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3458{
39de71ec 3459 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3460}
3461
1fe779f8
CO		 3462static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3463{
3464 int r;
3465
3466 r = 0;
3467 switch (chip->chip_id) {
3468 case KVM_IRQCHIP_PIC_MASTER:
3469 memcpy(&chip->chip.pic,
3470 &pic_irqchip(kvm)->pics[0],
3471 sizeof(struct kvm_pic_state));
3472 break;
3473 case KVM_IRQCHIP_PIC_SLAVE:
3474 memcpy(&chip->chip.pic,
3475 &pic_irqchip(kvm)->pics[1],
3476 sizeof(struct kvm_pic_state));
3477 break;
3478 case KVM_IRQCHIP_IOAPIC:
eba0226b 3479 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3480 break;
3481 default:
3482 r = -EINVAL;
3483 break;
3484 }
3485 return r;
3486}
3487
3488static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3489{
3490 int r;
3491
3492 r = 0;
3493 switch (chip->chip_id) {
3494 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3495 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3496 memcpy(&pic_irqchip(kvm)->pics[0],
3497 &chip->chip.pic,
3498 sizeof(struct kvm_pic_state));
f4f51050 3499 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3500 break;
3501 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3502 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3503 memcpy(&pic_irqchip(kvm)->pics[1],
3504 &chip->chip.pic,
3505 sizeof(struct kvm_pic_state));
f4f51050 3506 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3507 break;
3508 case KVM_IRQCHIP_IOAPIC:
eba0226b 3509 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3510 break;
3511 default:
3512 r = -EINVAL;
3513 break;
3514 }
3515 kvm_pic_update_irq(pic_irqchip(kvm));
3516 return r;
3517}
3518
e0f63cb9
SY		 3519static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3520{
3521 int r = 0;
3522
894a9c55 3523 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3524 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3525 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3526 return r;
3527}
3528
3529static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3530{
3531 int r = 0;
3532
894a9c55 3533 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3534 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3535 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3536 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3537 return r;
3538}
3539
3540static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3541{
3542 int r = 0;
3543
3544 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3545 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3546 sizeof(ps->channels));
3547 ps->flags = kvm->arch.vpit->pit_state.flags;
3548 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3549 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3550 return r;
3551}
3552
3553static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3554{
3555 int r = 0, start = 0;
3556 u32 prev_legacy, cur_legacy;
3557 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3558 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3560 if (!prev_legacy && cur_legacy)
3561 start = 1;
3562 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3563 sizeof(kvm->arch.vpit->pit_state.channels));
3564 kvm->arch.vpit->pit_state.flags = ps->flags;
3565 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3566 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3567 return r;
3568}
3569
52d939a0
MT		 3570static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3571 struct kvm_reinject_control *control)
3572{
3573 if (!kvm->arch.vpit)
3574 return -ENXIO;
894a9c55 3575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3576 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3578 return 0;
3579}
3580
95d4c16c 3581/**
60c34612
TY		 3582 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3583 * @kvm: kvm instance
3584 * @log: slot id and address to which we copy the log
95d4c16c 3585 *
60c34612
TY		 3586 * We need to keep it in mind that VCPU threads can write to the bitmap
3587 * concurrently. So, to avoid losing data, we keep the following order for
3588 * each bit:
95d4c16c 3589 *
60c34612
TY		 3590 * 1. Take a snapshot of the bit and clear it if needed.
3591 * 2. Write protect the corresponding page.
3592 * 3. Flush TLB's if needed.
3593 * 4. Copy the snapshot to the userspace.
95d4c16c 3594 *
60c34612
TY		 3595 * Between 2 and 3, the guest may write to the page using the remaining TLB
3596 * entry. This is not a problem because the page will be reported dirty at
3597 * step 4 using the snapshot taken before and step 3 ensures that successive
3598 * writes will be logged for the next call.
5bb064dc 3599 */
60c34612 3600int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3601{
7850ac54 3602 int r;
5bb064dc 3603 struct kvm_memory_slot *memslot;
60c34612
TY		 3604 unsigned long n, i;
3605 unsigned long *dirty_bitmap;
3606 unsigned long *dirty_bitmap_buffer;
3607 bool is_dirty = false;
5bb064dc 3608
79fac95e 3609 mutex_lock(&kvm->slots_lock);
5bb064dc 3610
b050b015 3611 r = -EINVAL;
bbacc0c1 3612 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3613 goto out;
3614
28a37544 3615 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3616
3617 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3618 r = -ENOENT;
60c34612 3619 if (!dirty_bitmap)
b050b015
MT		 3620 goto out;
3621
87bf6e7d 3622 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3623
60c34612
TY		 3624 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3625 memset(dirty_bitmap_buffer, 0, n);
b050b015 3626
60c34612 3627 spin_lock(&kvm->mmu_lock);
b050b015 3628
60c34612
TY		 3629 for (i = 0; i < n / sizeof(long); i++) {
3630 unsigned long mask;
3631 gfn_t offset;
cdfca7b3 3632
60c34612
TY		 3633 if (!dirty_bitmap[i])
3634 continue;
b050b015 3635
60c34612 3636 is_dirty = true;
914ebccd 3637
60c34612
TY		 3638 mask = xchg(&dirty_bitmap[i], 0);
3639 dirty_bitmap_buffer[i] = mask;
edde99ce 3640
60c34612
TY		 3641 offset = i * BITS_PER_LONG;
3642 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3643 }
60c34612
TY		 3644 if (is_dirty)
3645 kvm_flush_remote_tlbs(kvm);
3646
3647 spin_unlock(&kvm->mmu_lock);
3648
3649 r = -EFAULT;
3650 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3651 goto out;
b050b015 3652
5bb064dc
ZX		 3653 r = 0;
3654out:
79fac95e 3655 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3656 return r;
3657}
3658
aa2fbe6d
YZ		 3659int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3660 bool line_status)
23d43cf9
CD		 3661{
3662 if (!irqchip_in_kernel(kvm))
3663 return -ENXIO;
3664
3665 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3666 irq_event->irq, irq_event->level,
3667 line_status);
23d43cf9
CD		 3668 return 0;
3669}
3670
1fe779f8
CO		 3671long kvm_arch_vm_ioctl(struct file *filp,
3672 unsigned int ioctl, unsigned long arg)
3673{
3674 struct kvm *kvm = filp->private_data;
3675 void __user *argp = (void __user *)arg;
367e1319 3676 int r = -ENOTTY;
f0d66275
DH		 3677 /*
3678 * This union makes it completely explicit to gcc-3.x
3679 * that these two variables' stack usage should be
3680 * combined, not added together.
3681 */
3682 union {
3683 struct kvm_pit_state ps;
e9f42757 3684 struct kvm_pit_state2 ps2;
c5ff41ce 3685 struct kvm_pit_config pit_config;
f0d66275 3686 } u;
1fe779f8
CO		 3687
3688 switch (ioctl) {
3689 case KVM_SET_TSS_ADDR:
3690 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3691 break;
b927a3ce
SY		 3692 case KVM_SET_IDENTITY_MAP_ADDR: {
3693 u64 ident_addr;
3694
3695 r = -EFAULT;
3696 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3697 goto out;
3698 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3699 break;
3700 }
1fe779f8
CO		 3701 case KVM_SET_NR_MMU_PAGES:
3702 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3703 break;
3704 case KVM_GET_NR_MMU_PAGES:
3705 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3706 break;
3ddea128
MT		 3707 case KVM_CREATE_IRQCHIP: {
3708 struct kvm_pic *vpic;
3709
3710 mutex_lock(&kvm->lock);
3711 r = -EEXIST;
3712 if (kvm->arch.vpic)
3713 goto create_irqchip_unlock;
3e515705
AK		 3714 r = -EINVAL;
3715 if (atomic_read(&kvm->online_vcpus))
3716 goto create_irqchip_unlock;
1fe779f8 3717 r = -ENOMEM;
3ddea128
MT		 3718 vpic = kvm_create_pic(kvm);
3719 if (vpic) {
1fe779f8
CO		 3720 r = kvm_ioapic_init(kvm);
3721 if (r) {
175504cd 3722 mutex_lock(&kvm->slots_lock);
72bb2fcd 3723 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3724 &vpic->dev_master);
3725 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3726 &vpic->dev_slave);
3727 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3728 &vpic->dev_eclr);
175504cd 3729 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3730 kfree(vpic);
3731 goto create_irqchip_unlock;
1fe779f8
CO		 3732 }
3733 } else
3ddea128
MT		 3734 goto create_irqchip_unlock;
3735 smp_wmb();
3736 kvm->arch.vpic = vpic;
3737 smp_wmb();
399ec807
AK		 3738 r = kvm_setup_default_irq_routing(kvm);
3739 if (r) {
175504cd 3740 mutex_lock(&kvm->slots_lock);
3ddea128 3741 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3742 kvm_ioapic_destroy(kvm);
3743 kvm_destroy_pic(kvm);
3ddea128 3744 mutex_unlock(&kvm->irq_lock);
175504cd 3745 mutex_unlock(&kvm->slots_lock);
399ec807 3746 }
3ddea128
MT		 3747 create_irqchip_unlock:
3748 mutex_unlock(&kvm->lock);
1fe779f8 3749 break;
3ddea128 3750 }
7837699f 3751 case KVM_CREATE_PIT:
c5ff41ce
JK		 3752 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3753 goto create_pit;
3754 case KVM_CREATE_PIT2:
3755 r = -EFAULT;
3756 if (copy_from_user(&u.pit_config, argp,
3757 sizeof(struct kvm_pit_config)))
3758 goto out;
3759 create_pit:
79fac95e 3760 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3761 r = -EEXIST;
3762 if (kvm->arch.vpit)
3763 goto create_pit_unlock;
7837699f 3764 r = -ENOMEM;
c5ff41ce 3765 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3766 if (kvm->arch.vpit)
3767 r = 0;
269e05e4 3768 create_pit_unlock:
79fac95e 3769 mutex_unlock(&kvm->slots_lock);
7837699f 3770 break;
1fe779f8
CO		 3771 case KVM_GET_IRQCHIP: {
3772 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3773 struct kvm_irqchip *chip;
1fe779f8 3774
ff5c2c03
SL		 3775 chip = memdup_user(argp, sizeof(*chip));
3776 if (IS_ERR(chip)) {
3777 r = PTR_ERR(chip);
1fe779f8 3778 goto out;
ff5c2c03
SL		 3779 }
3780
1fe779f8
CO		 3781 r = -ENXIO;
3782 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3783 goto get_irqchip_out;
3784 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3785 if (r)
f0d66275 3786 goto get_irqchip_out;
1fe779f8 3787 r = -EFAULT;
f0d66275
DH		 3788 if (copy_to_user(argp, chip, sizeof *chip))
3789 goto get_irqchip_out;
1fe779f8 3790 r = 0;
f0d66275
DH		 3791 get_irqchip_out:
3792 kfree(chip);
1fe779f8
CO		 3793 break;
3794 }
3795 case KVM_SET_IRQCHIP: {
3796 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3797 struct kvm_irqchip *chip;
1fe779f8 3798
ff5c2c03
SL		 3799 chip = memdup_user(argp, sizeof(*chip));
3800 if (IS_ERR(chip)) {
3801 r = PTR_ERR(chip);
1fe779f8 3802 goto out;
ff5c2c03
SL		 3803 }
3804
1fe779f8
CO		 3805 r = -ENXIO;
3806 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3807 goto set_irqchip_out;
3808 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3809 if (r)
f0d66275 3810 goto set_irqchip_out;
1fe779f8 3811 r = 0;
f0d66275
DH		 3812 set_irqchip_out:
3813 kfree(chip);
1fe779f8
CO		 3814 break;
3815 }
e0f63cb9 3816 case KVM_GET_PIT: {
e0f63cb9 3817 r = -EFAULT;
f0d66275 3818 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3819 goto out;
3820 r = -ENXIO;
3821 if (!kvm->arch.vpit)
3822 goto out;
f0d66275 3823 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3824 if (r)
3825 goto out;
3826 r = -EFAULT;
f0d66275 3827 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3828 goto out;
3829 r = 0;
3830 break;
3831 }
3832 case KVM_SET_PIT: {
e0f63cb9 3833 r = -EFAULT;
f0d66275 3834 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3835 goto out;
3836 r = -ENXIO;
3837 if (!kvm->arch.vpit)
3838 goto out;
f0d66275 3839 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3840 break;
3841 }
e9f42757
BK		 3842 case KVM_GET_PIT2: {
3843 r = -ENXIO;
3844 if (!kvm->arch.vpit)
3845 goto out;
3846 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3847 if (r)
3848 goto out;
3849 r = -EFAULT;
3850 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3851 goto out;
3852 r = 0;
3853 break;
3854 }
3855 case KVM_SET_PIT2: {
3856 r = -EFAULT;
3857 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3858 goto out;
3859 r = -ENXIO;
3860 if (!kvm->arch.vpit)
3861 goto out;
3862 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3863 break;
3864 }
52d939a0
MT		 3865 case KVM_REINJECT_CONTROL: {
3866 struct kvm_reinject_control control;
3867 r = -EFAULT;
3868 if (copy_from_user(&control, argp, sizeof(control)))
3869 goto out;
3870 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3871 break;
3872 }
ffde22ac
ES		 3873 case KVM_XEN_HVM_CONFIG: {
3874 r = -EFAULT;
3875 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3876 sizeof(struct kvm_xen_hvm_config)))
3877 goto out;
3878 r = -EINVAL;
3879 if (kvm->arch.xen_hvm_config.flags)
3880 goto out;
3881 r = 0;
3882 break;
3883 }
afbcf7ab 3884 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3885 struct kvm_clock_data user_ns;
3886 u64 now_ns;
3887 s64 delta;
3888
3889 r = -EFAULT;
3890 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3891 goto out;
3892
3893 r = -EINVAL;
3894 if (user_ns.flags)
3895 goto out;
3896
3897 r = 0;
395c6b0a 3898 local_irq_disable();
759379dd 3899 now_ns = get_kernel_ns();
afbcf7ab 3900 delta = user_ns.clock - now_ns;
395c6b0a 3901 local_irq_enable();
afbcf7ab 3902 kvm->arch.kvmclock_offset = delta;
2e762ff7 3903 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3904 break;
3905 }
3906 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3907 struct kvm_clock_data user_ns;
3908 u64 now_ns;
3909
395c6b0a 3910 local_irq_disable();
759379dd 3911 now_ns = get_kernel_ns();
afbcf7ab 3912 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3913 local_irq_enable();
afbcf7ab 3914 user_ns.flags = 0;
97e69aa6 3915 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3916
3917 r = -EFAULT;
3918 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3919 goto out;
3920 r = 0;
3921 break;
3922 }
3923
1fe779f8
CO		 3924 default:
3925 ;
3926 }
3927out:
3928 return r;
3929}
3930
a16b043c 3931static void kvm_init_msr_list(void)
043405e1
CO		 3932{
3933 u32 dummy[2];
3934 unsigned i, j;
3935
e3267cbb
GC		 3936 /* skip the first msrs in the list. KVM-specific */
3937 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3938 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3939 continue;
93c4adc7
PB		 3940
3941 /*
3942 * Even MSRs that are valid in the host may not be exposed
3943 * to the guests in some cases. We could work around this
3944 * in VMX with the generic MSR save/load machinery, but it
3945 * is not really worthwhile since it will really only
3946 * happen with nested virtualization.
3947 */
3948 switch (msrs_to_save[i]) {
3949 case MSR_IA32_BNDCFGS:
3950 if (!kvm_x86_ops->mpx_supported())
3951 continue;
3952 break;
3953 default:
3954 break;
3955 }
3956
043405e1
CO		 3957 if (j < i)
3958 msrs_to_save[j] = msrs_to_save[i];
3959 j++;
3960 }
3961 num_msrs_to_save = j;
3962}
3963
bda9020e
MT		 3964static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3965 const void *v)
bbd9b64e 3966{
70252a10
AK		 3967 int handled = 0;
3968 int n;
3969
3970 do {
3971 n = min(len, 8);
3972 if (!(vcpu->arch.apic &&
3973 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3974 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3975 break;
3976 handled += n;
3977 addr += n;
3978 len -= n;
3979 v += n;
3980 } while (len);
bbd9b64e 3981
70252a10 3982 return handled;
bbd9b64e
CO		 3983}
3984
bda9020e 3985static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3986{
70252a10
AK		 3987 int handled = 0;
3988 int n;
3989
3990 do {
3991 n = min(len, 8);
3992 if (!(vcpu->arch.apic &&
3993 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3994 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3995 break;
3996 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3997 handled += n;
3998 addr += n;
3999 len -= n;
4000 v += n;
4001 } while (len);
bbd9b64e 4002
70252a10 4003 return handled;
bbd9b64e
CO		 4004}
4005
2dafc6c2
GN		 4006static void kvm_set_segment(struct kvm_vcpu *vcpu,
4007 struct kvm_segment *var, int seg)
4008{
4009 kvm_x86_ops->set_segment(vcpu, var, seg);
4010}
4011
4012void kvm_get_segment(struct kvm_vcpu *vcpu,
4013 struct kvm_segment *var, int seg)
4014{
4015 kvm_x86_ops->get_segment(vcpu, var, seg);
4016}
4017
e459e322 4018gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4019{
4020 gpa_t t_gpa;
ab9ae313 4021 struct x86_exception exception;
02f59dc9
JR		 4022
4023 BUG_ON(!mmu_is_nested(vcpu));
4024
4025 /* NPT walks are always user-walks */
4026 access |= PFERR_USER_MASK;
ab9ae313 4027 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4028
4029 return t_gpa;
4030}
4031
ab9ae313
AK		 4032gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4033 struct x86_exception *exception)
1871c602
GN		 4034{
4035 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4036 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4037}
4038
ab9ae313
AK		 4039 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4040 struct x86_exception *exception)
1871c602
GN		 4041{
4042 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4043 access |= PFERR_FETCH_MASK;
ab9ae313 4044 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4045}
4046
ab9ae313
AK		 4047gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4048 struct x86_exception *exception)
1871c602
GN		 4049{
4050 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4051 access |= PFERR_WRITE_MASK;
ab9ae313 4052 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4053}
4054
4055/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4056gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4057 struct x86_exception *exception)
1871c602 4058{
ab9ae313 4059 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4060}
4061
4062static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4063 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4064 struct x86_exception *exception)
bbd9b64e
CO		 4065{
4066 void *data = val;
10589a46 4067 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4068
4069 while (bytes) {
14dfe855 4070 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4071 exception);
bbd9b64e 4072 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4073 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4074 int ret;
4075
bcc55cba 4076 if (gpa == UNMAPPED_GVA)
ab9ae313 4077 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4078 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4079 if (ret < 0) {
c3cd7ffa 4080 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4081 goto out;
4082 }
bbd9b64e 4083
77c2002e
IE		 4084 bytes -= toread;
4085 data += toread;
4086 addr += toread;
bbd9b64e 4087 }
10589a46 4088out:
10589a46 4089 return r;
bbd9b64e 4090}
77c2002e 4091
1871c602 4092/* used for instruction fetching */
0f65dd70
AK		 4093static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4094 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4095 struct x86_exception *exception)
1871c602 4096{
0f65dd70 4097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4099
1871c602 4100 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4101 access | PFERR_FETCH_MASK,
4102 exception);
1871c602
GN		 4103}
4104
064aea77 4105int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4106 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4107 struct x86_exception *exception)
1871c602 4108{
0f65dd70 4109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4110 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4111
1871c602 4112 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4113 exception);
1871c602 4114}
064aea77 4115EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4116
0f65dd70
AK		 4117static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4118 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4119 struct x86_exception *exception)
1871c602 4120{
0f65dd70 4121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4122 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4123}
4124
6a4d7550 4125int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4126 gva_t addr, void *val,
2dafc6c2 4127 unsigned int bytes,
bcc55cba 4128 struct x86_exception *exception)
77c2002e 4129{
0f65dd70 4130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4131 void *data = val;
4132 int r = X86EMUL_CONTINUE;
4133
4134 while (bytes) {
14dfe855
JR		 4135 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4136 PFERR_WRITE_MASK,
ab9ae313 4137 exception);
77c2002e
IE		 4138 unsigned offset = addr & (PAGE_SIZE-1);
4139 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4140 int ret;
4141
bcc55cba 4142 if (gpa == UNMAPPED_GVA)
ab9ae313 4143 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4144 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4145 if (ret < 0) {
c3cd7ffa 4146 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4147 goto out;
4148 }
4149
4150 bytes -= towrite;
4151 data += towrite;
4152 addr += towrite;
4153 }
4154out:
4155 return r;
4156}
6a4d7550 4157EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4158
af7cc7d1
XG		 4159static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4160 gpa_t *gpa, struct x86_exception *exception,
4161 bool write)
4162{
97d64b78
AK		 4163 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4164 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4165
97d64b78
AK		 4166 if (vcpu_match_mmio_gva(vcpu, gva)
4167 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4168 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4169 (gva & (PAGE_SIZE - 1));
4f022648 4170 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4171 return 1;
4172 }
4173
af7cc7d1
XG		 4174 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4175
4176 if (*gpa == UNMAPPED_GVA)
4177 return -1;
4178
4179 /* For APIC access vmexit */
4180 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4181 return 1;
4182
4f022648
XG		 4183 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4184 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4185 return 1;
4f022648 4186 }
bebb106a 4187
af7cc7d1
XG		 4188 return 0;
4189}
4190
3200f405 4191int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4192 const void *val, int bytes)
bbd9b64e
CO		 4193{
4194 int ret;
4195
4196 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4197 if (ret < 0)
bbd9b64e 4198 return 0;
f57f2ef5 4199 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4200 return 1;
4201}
4202
77d197b2
XG		 4203struct read_write_emulator_ops {
4204 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4205 int bytes);
4206 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes);
4208 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4209 int bytes, void *val);
4210 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4211 void *val, int bytes);
4212 bool write;
4213};
4214
4215static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4216{
4217 if (vcpu->mmio_read_completed) {
77d197b2 4218 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4219 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4220 vcpu->mmio_read_completed = 0;
4221 return 1;
4222 }
4223
4224 return 0;
4225}
4226
4227static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4228 void *val, int bytes)
4229{
4230 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4231}
4232
4233static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4234 void *val, int bytes)
4235{
4236 return emulator_write_phys(vcpu, gpa, val, bytes);
4237}
4238
4239static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4240{
4241 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4242 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4243}
4244
4245static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4246 void *val, int bytes)
4247{
4248 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4249 return X86EMUL_IO_NEEDED;
4250}
4251
4252static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4253 void *val, int bytes)
4254{
f78146b0
AK		 4255 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4256
87da7e66 4257 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4258 return X86EMUL_CONTINUE;
4259}
4260
0fbe9b0b 4261static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4262 .read_write_prepare = read_prepare,
4263 .read_write_emulate = read_emulate,
4264 .read_write_mmio = vcpu_mmio_read,
4265 .read_write_exit_mmio = read_exit_mmio,
4266};
4267
0fbe9b0b 4268static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4269 .read_write_emulate = write_emulate,
4270 .read_write_mmio = write_mmio,
4271 .read_write_exit_mmio = write_exit_mmio,
4272 .write = true,
4273};
4274
22388a3c
XG		 4275static int emulator_read_write_onepage(unsigned long addr, void *val,
4276 unsigned int bytes,
4277 struct x86_exception *exception,
4278 struct kvm_vcpu *vcpu,
0fbe9b0b 4279 const struct read_write_emulator_ops *ops)
bbd9b64e 4280{
af7cc7d1
XG		 4281 gpa_t gpa;
4282 int handled, ret;
22388a3c 4283 bool write = ops->write;
f78146b0 4284 struct kvm_mmio_fragment *frag;
10589a46 4285
22388a3c 4286 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4287
af7cc7d1 4288 if (ret < 0)
bbd9b64e 4289 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4290
4291 /* For APIC access vmexit */
af7cc7d1 4292 if (ret)
bbd9b64e
CO		 4293 goto mmio;
4294
22388a3c 4295 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4296 return X86EMUL_CONTINUE;
4297
4298mmio:
4299 /*
4300 * Is this MMIO handled locally?
4301 */
22388a3c 4302 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4303 if (handled == bytes)
bbd9b64e 4304 return X86EMUL_CONTINUE;
bbd9b64e 4305
70252a10
AK		 4306 gpa += handled;
4307 bytes -= handled;
4308 val += handled;
4309
87da7e66
XG		 4310 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4311 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4312 frag->gpa = gpa;
4313 frag->data = val;
4314 frag->len = bytes;
f78146b0 4315 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4316}
4317
22388a3c
XG		 4318int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4319 void *val, unsigned int bytes,
4320 struct x86_exception *exception,
0fbe9b0b 4321 const struct read_write_emulator_ops *ops)
bbd9b64e 4322{
0f65dd70 4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4324 gpa_t gpa;
4325 int rc;
4326
4327 if (ops->read_write_prepare &&
4328 ops->read_write_prepare(vcpu, val, bytes))
4329 return X86EMUL_CONTINUE;
4330
4331 vcpu->mmio_nr_fragments = 0;
0f65dd70 4332
bbd9b64e
CO		 4333 /* Crossing a page boundary? */
4334 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4335 int now;
bbd9b64e
CO		 4336
4337 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4338 rc = emulator_read_write_onepage(addr, val, now, exception,
4339 vcpu, ops);
4340
bbd9b64e
CO		 4341 if (rc != X86EMUL_CONTINUE)
4342 return rc;
4343 addr += now;
4344 val += now;
4345 bytes -= now;
4346 }
22388a3c 4347
f78146b0
AK		 4348 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4349 vcpu, ops);
4350 if (rc != X86EMUL_CONTINUE)
4351 return rc;
4352
4353 if (!vcpu->mmio_nr_fragments)
4354 return rc;
4355
4356 gpa = vcpu->mmio_fragments[0].gpa;
4357
4358 vcpu->mmio_needed = 1;
4359 vcpu->mmio_cur_fragment = 0;
4360
87da7e66 4361 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4362 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4363 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4364 vcpu->run->mmio.phys_addr = gpa;
4365
4366 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4367}
4368
4369static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4370 unsigned long addr,
4371 void *val,
4372 unsigned int bytes,
4373 struct x86_exception *exception)
4374{
4375 return emulator_read_write(ctxt, addr, val, bytes,
4376 exception, &read_emultor);
4377}
4378
4379int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4380 unsigned long addr,
4381 const void *val,
4382 unsigned int bytes,
4383 struct x86_exception *exception)
4384{
4385 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4386 exception, &write_emultor);
bbd9b64e 4387}
bbd9b64e 4388
daea3e73
AK		 4389#define CMPXCHG_TYPE(t, ptr, old, new) \
4390 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4391
4392#ifdef CONFIG_X86_64
4393# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4394#else
4395# define CMPXCHG64(ptr, old, new) \
9749a6c0 4396 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4397#endif
4398
0f65dd70
AK		 4399static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4400 unsigned long addr,
bbd9b64e
CO		 4401 const void *old,
4402 const void *new,
4403 unsigned int bytes,
0f65dd70 4404 struct x86_exception *exception)
bbd9b64e 4405{
0f65dd70 4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4407 gpa_t gpa;
4408 struct page *page;
4409 char *kaddr;
4410 bool exchanged;
2bacc55c 4411
daea3e73
AK		 4412 /* guests cmpxchg8b have to be emulated atomically */
4413 if (bytes > 8 || (bytes & (bytes - 1)))
4414 goto emul_write;
10589a46 4415
daea3e73 4416 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4417
daea3e73
AK		 4418 if (gpa == UNMAPPED_GVA ||
4419 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4420 goto emul_write;
2bacc55c 4421
daea3e73
AK		 4422 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4423 goto emul_write;
72dc67a6 4424
daea3e73 4425 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4426 if (is_error_page(page))
c19b8bd6 4427 goto emul_write;
72dc67a6 4428
8fd75e12 4429 kaddr = kmap_atomic(page);
daea3e73
AK		 4430 kaddr += offset_in_page(gpa);
4431 switch (bytes) {
4432 case 1:
4433 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4434 break;
4435 case 2:
4436 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4437 break;
4438 case 4:
4439 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4440 break;
4441 case 8:
4442 exchanged = CMPXCHG64(kaddr, old, new);
4443 break;
4444 default:
4445 BUG();
2bacc55c 4446 }
8fd75e12 4447 kunmap_atomic(kaddr);
daea3e73
AK		 4448 kvm_release_page_dirty(page);
4449
4450 if (!exchanged)
4451 return X86EMUL_CMPXCHG_FAILED;
4452
d3714010 4453 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4454 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4455
4456 return X86EMUL_CONTINUE;
4a5f48f6 4457
3200f405 4458emul_write:
daea3e73 4459 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4460
0f65dd70 4461 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4462}
4463
cf8f70bf
GN		 4464static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4465{
4466 /* TODO: String I/O for in kernel device */
4467 int r;
4468
4469 if (vcpu->arch.pio.in)
4470 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4471 vcpu->arch.pio.size, pd);
4472 else
4473 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4474 vcpu->arch.pio.port, vcpu->arch.pio.size,
4475 pd);
4476 return r;
4477}
4478
6f6fbe98
XG		 4479static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4480 unsigned short port, void *val,
4481 unsigned int count, bool in)
cf8f70bf 4482{
6f6fbe98 4483 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4484
4485 vcpu->arch.pio.port = port;
6f6fbe98 4486 vcpu->arch.pio.in = in;
7972995b 4487 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4488 vcpu->arch.pio.size = size;
4489
4490 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4491 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4492 return 1;
4493 }
4494
4495 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4496 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4497 vcpu->run->io.size = size;
4498 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4499 vcpu->run->io.count = count;
4500 vcpu->run->io.port = port;
4501
4502 return 0;
4503}
4504
6f6fbe98
XG		 4505static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4506 int size, unsigned short port, void *val,
4507 unsigned int count)
cf8f70bf 4508{
ca1d4a9e 4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4510 int ret;
ca1d4a9e 4511
6f6fbe98
XG		 4512 if (vcpu->arch.pio.count)
4513 goto data_avail;
cf8f70bf 4514
6f6fbe98
XG		 4515 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4516 if (ret) {
4517data_avail:
4518 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4519 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4520 return 1;
4521 }
4522
cf8f70bf
GN		 4523 return 0;
4524}
4525
6f6fbe98
XG		 4526static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4527 int size, unsigned short port,
4528 const void *val, unsigned int count)
4529{
4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4531
4532 memcpy(vcpu->arch.pio_data, val, size * count);
4533 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4534}
4535
bbd9b64e
CO		 4536static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4537{
4538 return kvm_x86_ops->get_segment_base(vcpu, seg);
4539}
4540
3cb16fe7 4541static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4542{
3cb16fe7 4543 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4544}
4545
f5f48ee1
SY		 4546int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4547{
4548 if (!need_emulate_wbinvd(vcpu))
4549 return X86EMUL_CONTINUE;
4550
4551 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4552 int cpu = get_cpu();
4553
4554 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4555 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4556 wbinvd_ipi, NULL, 1);
2eec7343 4557 put_cpu();
f5f48ee1 4558 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4559 } else
4560 wbinvd();
f5f48ee1
SY		 4561 return X86EMUL_CONTINUE;
4562}
4563EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4564
bcaf5cc5
AK		 4565static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4566{
4567 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4568}
4569
717746e3 4570int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4571{
717746e3 4572 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4573}
4574
717746e3 4575int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4576{
338dbc97 4577
717746e3 4578 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4579}
4580
52a46617 4581static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4582{
52a46617 4583 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4584}
4585
717746e3 4586static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4587{
717746e3 4588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4589 unsigned long value;
4590
4591 switch (cr) {
4592 case 0:
4593 value = kvm_read_cr0(vcpu);
4594 break;
4595 case 2:
4596 value = vcpu->arch.cr2;
4597 break;
4598 case 3:
9f8fe504 4599 value = kvm_read_cr3(vcpu);
52a46617
GN		 4600 break;
4601 case 4:
4602 value = kvm_read_cr4(vcpu);
4603 break;
4604 case 8:
4605 value = kvm_get_cr8(vcpu);
4606 break;
4607 default:
a737f256 4608 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4609 return 0;
4610 }
4611
4612 return value;
4613}
4614
717746e3 4615static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4616{
717746e3 4617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4618 int res = 0;
4619
52a46617
GN		 4620 switch (cr) {
4621 case 0:
49a9b07e 4622 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4623 break;
4624 case 2:
4625 vcpu->arch.cr2 = val;
4626 break;
4627 case 3:
2390218b 4628 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4629 break;
4630 case 4:
a83b29c6 4631 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4632 break;
4633 case 8:
eea1cff9 4634 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4635 break;
4636 default:
a737f256 4637 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4638 res = -1;
52a46617 4639 }
0f12244f
GN		 4640
4641 return res;
52a46617
GN		 4642}
4643
4cee4798
KW		 4644static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4645{
4646 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4647}
4648
717746e3 4649static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4650{
717746e3 4651 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4652}
4653
4bff1e86 4654static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4655{
4bff1e86 4656 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4657}
4658
4bff1e86 4659static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4660{
4bff1e86 4661 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4662}
4663
1ac9d0cf
AK		 4664static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4665{
4666 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4667}
4668
4669static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4670{
4671 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4672}
4673
4bff1e86
AK		 4674static unsigned long emulator_get_cached_segment_base(
4675 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4676{
4bff1e86 4677 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4678}
4679
1aa36616
AK		 4680static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4681 struct desc_struct *desc, u32 *base3,
4682 int seg)
2dafc6c2
GN		 4683{
4684 struct kvm_segment var;
4685
4bff1e86 4686 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4687 *selector = var.selector;
2dafc6c2 4688
378a8b09
GN		 4689 if (var.unusable) {
4690 memset(desc, 0, sizeof(*desc));
2dafc6c2 4691 return false;
378a8b09 4692 }
2dafc6c2
GN		 4693
4694 if (var.g)
4695 var.limit >>= 12;
4696 set_desc_limit(desc, var.limit);
4697 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4698#ifdef CONFIG_X86_64
4699 if (base3)
4700 *base3 = var.base >> 32;
4701#endif
2dafc6c2
GN		 4702 desc->type = var.type;
4703 desc->s = var.s;
4704 desc->dpl = var.dpl;
4705 desc->p = var.present;
4706 desc->avl = var.avl;
4707 desc->l = var.l;
4708 desc->d = var.db;
4709 desc->g = var.g;
4710
4711 return true;
4712}
4713
1aa36616
AK		 4714static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4715 struct desc_struct *desc, u32 base3,
4716 int seg)
2dafc6c2 4717{
4bff1e86 4718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4719 struct kvm_segment var;
4720
1aa36616 4721 var.selector = selector;
2dafc6c2 4722 var.base = get_desc_base(desc);
5601d05b
GN		 4723#ifdef CONFIG_X86_64
4724 var.base |= ((u64)base3) << 32;
4725#endif
2dafc6c2
GN		 4726 var.limit = get_desc_limit(desc);
4727 if (desc->g)
4728 var.limit = (var.limit << 12) | 0xfff;
4729 var.type = desc->type;
4730 var.present = desc->p;
4731 var.dpl = desc->dpl;
4732 var.db = desc->d;
4733 var.s = desc->s;
4734 var.l = desc->l;
4735 var.g = desc->g;
4736 var.avl = desc->avl;
4737 var.present = desc->p;
4738 var.unusable = !var.present;
4739 var.padding = 0;
4740
4741 kvm_set_segment(vcpu, &var, seg);
4742 return;
4743}
4744
717746e3
AK		 4745static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4746 u32 msr_index, u64 *pdata)
4747{
4748 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4749}
4750
4751static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4752 u32 msr_index, u64 data)
4753{
8fe8ab46
WA		 4754 struct msr_data msr;
4755
4756 msr.data = data;
4757 msr.index = msr_index;
4758 msr.host_initiated = false;
4759 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4760}
4761
222d21aa
AK		 4762static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4763 u32 pmc, u64 *pdata)
4764{
4765 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4766}
4767
6c3287f7
AK		 4768static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4769{
4770 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4771}
4772
5037f6f3
AK		 4773static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4774{
4775 preempt_disable();
5197b808 4776 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4777 /*
4778 * CR0.TS may reference the host fpu state, not the guest fpu state,
4779 * so it may be clear at this point.
4780 */
4781 clts();
4782}
4783
4784static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4785{
4786 preempt_enable();
4787}
4788
2953538e 4789static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4790 struct x86_instruction_info *info,
c4f035c6
AK		 4791 enum x86_intercept_stage stage)
4792{
2953538e 4793 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4794}
4795
0017f93a 4796static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4797 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4798{
0017f93a 4799 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4800}
4801
dd856efa
AK		 4802static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4803{
4804 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4805}
4806
4807static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4808{
4809 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4810}
4811
0225fb50 4812static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4813 .read_gpr = emulator_read_gpr,
4814 .write_gpr = emulator_write_gpr,
1871c602 4815 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4816 .write_std = kvm_write_guest_virt_system,
1871c602 4817 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4818 .read_emulated = emulator_read_emulated,
4819 .write_emulated = emulator_write_emulated,
4820 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4821 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4822 .pio_in_emulated = emulator_pio_in_emulated,
4823 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4824 .get_segment = emulator_get_segment,
4825 .set_segment = emulator_set_segment,
5951c442 4826 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4827 .get_gdt = emulator_get_gdt,
160ce1f1 4828 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4829 .set_gdt = emulator_set_gdt,
4830 .set_idt = emulator_set_idt,
52a46617
GN		 4831 .get_cr = emulator_get_cr,
4832 .set_cr = emulator_set_cr,
4cee4798 4833 .set_rflags = emulator_set_rflags,
9c537244 4834 .cpl = emulator_get_cpl,
35aa5375
GN		 4835 .get_dr = emulator_get_dr,
4836 .set_dr = emulator_set_dr,
717746e3
AK		 4837 .set_msr = emulator_set_msr,
4838 .get_msr = emulator_get_msr,
222d21aa 4839 .read_pmc = emulator_read_pmc,
6c3287f7 4840 .halt = emulator_halt,
bcaf5cc5 4841 .wbinvd = emulator_wbinvd,
d6aa1000 4842 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4843 .get_fpu = emulator_get_fpu,
4844 .put_fpu = emulator_put_fpu,
c4f035c6 4845 .intercept = emulator_intercept,
bdb42f5a 4846 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4847};
4848
95cb2295
GN		 4849static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4850{
4851 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4852 /*
4853 * an sti; sti; sequence only disable interrupts for the first
4854 * instruction. So, if the last instruction, be it emulated or
4855 * not, left the system with the INT_STI flag enabled, it
4856 * means that the last instruction is an sti. We should not
4857 * leave the flag on in this case. The same goes for mov ss
4858 */
4859 if (!(int_shadow & mask))
4860 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4861}
4862
54b8486f
GN		 4863static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4864{
4865 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4866 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4867 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4868 else if (ctxt->exception.error_code_valid)
4869 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4870 ctxt->exception.error_code);
54b8486f 4871 else
da9cb575 4872 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4873}
4874
dd856efa 4875static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4876{
1ce19dc1
BP		 4877 memset(&ctxt->opcode_len, 0,
4878 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4879
9dac77fa
AK		 4880 ctxt->fetch.start = 0;
4881 ctxt->fetch.end = 0;
4882 ctxt->io_read.pos = 0;
4883 ctxt->io_read.end = 0;
4884 ctxt->mem_read.pos = 0;
4885 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4886}
4887
8ec4722d
MG		 4888static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4889{
adf52235 4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4891 int cs_db, cs_l;
4892
8ec4722d
MG		 4893 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4894
adf52235
TY		 4895 ctxt->eflags = kvm_get_rflags(vcpu);
4896 ctxt->eip = kvm_rip_read(vcpu);
4897 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4898 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4899 cs_l ? X86EMUL_MODE_PROT64 :
4900 cs_db ? X86EMUL_MODE_PROT32 :
4901 X86EMUL_MODE_PROT16;
4902 ctxt->guest_mode = is_guest_mode(vcpu);
4903
dd856efa 4904 init_decode_cache(ctxt);
7ae441ea 4905 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4906}
4907
71f9833b 4908int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4909{
9d74191a 4910 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4911 int ret;
4912
4913 init_emulate_ctxt(vcpu);
4914
9dac77fa
AK		 4915 ctxt->op_bytes = 2;
4916 ctxt->ad_bytes = 2;
4917 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4918 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4919
4920 if (ret != X86EMUL_CONTINUE)
4921 return EMULATE_FAIL;
4922
9dac77fa 4923 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4924 kvm_rip_write(vcpu, ctxt->eip);
4925 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4926
4927 if (irq == NMI_VECTOR)
7460fb4a 4928 vcpu->arch.nmi_pending = 0;
63995653
MG		 4929 else
4930 vcpu->arch.interrupt.pending = false;
4931
4932 return EMULATE_DONE;
4933}
4934EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4935
6d77dbfc
GN		 4936static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4937{
fc3a9157
JR		 4938 int r = EMULATE_DONE;
4939
6d77dbfc
GN		 4940 ++vcpu->stat.insn_emulation_fail;
4941 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4942 if (!is_guest_mode(vcpu)) {
4943 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4944 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4945 vcpu->run->internal.ndata = 0;
4946 r = EMULATE_FAIL;
4947 }
6d77dbfc 4948 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4949
4950 return r;
6d77dbfc
GN		 4951}
4952
93c05d3e 4953static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4954 bool write_fault_to_shadow_pgtable,
4955 int emulation_type)
a6f177ef 4956{
95b3cf69 4957 gpa_t gpa = cr2;
8e3d9d06 4958 pfn_t pfn;
a6f177ef 4959
991eebf9
GN		 4960 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4961 return false;
4962
95b3cf69
XG		 4963 if (!vcpu->arch.mmu.direct_map) {
4964 /*
4965 * Write permission should be allowed since only
4966 * write access need to be emulated.
4967 */
4968 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4969
95b3cf69
XG		 4970 /*
4971 * If the mapping is invalid in guest, let cpu retry
4972 * it to generate fault.
4973 */
4974 if (gpa == UNMAPPED_GVA)
4975 return true;
4976 }
a6f177ef 4977
8e3d9d06
XG		 4978 /*
4979 * Do not retry the unhandleable instruction if it faults on the
4980 * readonly host memory, otherwise it will goto a infinite loop:
4981 * retry instruction -> write #PF -> emulation fail -> retry
4982 * instruction -> ...
4983 */
4984 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4985
4986 /*
4987 * If the instruction failed on the error pfn, it can not be fixed,
4988 * report the error to userspace.
4989 */
4990 if (is_error_noslot_pfn(pfn))
4991 return false;
4992
4993 kvm_release_pfn_clean(pfn);
4994
4995 /* The instructions are well-emulated on direct mmu. */
4996 if (vcpu->arch.mmu.direct_map) {
4997 unsigned int indirect_shadow_pages;
4998
4999 spin_lock(&vcpu->kvm->mmu_lock);
5000 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5001 spin_unlock(&vcpu->kvm->mmu_lock);
5002
5003 if (indirect_shadow_pages)
5004 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5005
a6f177ef 5006 return true;
8e3d9d06 5007 }
a6f177ef 5008
95b3cf69
XG		 5009 /*
5010 * if emulation was due to access to shadowed page table
5011 * and it failed try to unshadow page and re-enter the
5012 * guest to let CPU execute the instruction.
5013 */
5014 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5015
5016 /*
5017 * If the access faults on its page table, it can not
5018 * be fixed by unprotecting shadow page and it should
5019 * be reported to userspace.
5020 */
5021 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5022}
5023
1cb3f3ae
XG		 5024static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5025 unsigned long cr2, int emulation_type)
5026{
5027 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5028 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5029
5030 last_retry_eip = vcpu->arch.last_retry_eip;
5031 last_retry_addr = vcpu->arch.last_retry_addr;
5032
5033 /*
5034 * If the emulation is caused by #PF and it is non-page_table
5035 * writing instruction, it means the VM-EXIT is caused by shadow
5036 * page protected, we can zap the shadow page and retry this
5037 * instruction directly.
5038 *
5039 * Note: if the guest uses a non-page-table modifying instruction
5040 * on the PDE that points to the instruction, then we will unmap
5041 * the instruction and go to an infinite loop. So, we cache the
5042 * last retried eip and the last fault address, if we meet the eip
5043 * and the address again, we can break out of the potential infinite
5044 * loop.
5045 */
5046 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5047
5048 if (!(emulation_type & EMULTYPE_RETRY))
5049 return false;
5050
5051 if (x86_page_table_writing_insn(ctxt))
5052 return false;
5053
5054 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5055 return false;
5056
5057 vcpu->arch.last_retry_eip = ctxt->eip;
5058 vcpu->arch.last_retry_addr = cr2;
5059
5060 if (!vcpu->arch.mmu.direct_map)
5061 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5062
22368028 5063 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5064
5065 return true;
5066}
5067
716d51ab
GN		 5068static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5069static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5070
4a1e10d5
PB		 5071static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5072 unsigned long *db)
5073{
5074 u32 dr6 = 0;
5075 int i;
5076 u32 enable, rwlen;
5077
5078 enable = dr7;
5079 rwlen = dr7 >> 16;
5080 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5081 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5082 dr6 |= (1 << i);
5083 return dr6;
5084}
5085
663f4c61
PB		 5086static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5087{
5088 struct kvm_run *kvm_run = vcpu->run;
5089
5090 /*
5091 * Use the "raw" value to see if TF was passed to the processor.
5092 * Note that the new value of the flags has not been saved yet.
5093 *
5094 * This is correct even for TF set by the guest, because "the
5095 * processor will not generate this exception after the instruction
5096 * that sets the TF flag".
5097 */
5098 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5099
5100 if (unlikely(rflags & X86_EFLAGS_TF)) {
5101 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5102 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5103 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5104 kvm_run->debug.arch.exception = DB_VECTOR;
5105 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5106 *r = EMULATE_USER_EXIT;
5107 } else {
5108 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5109 /*
5110 * "Certain debug exceptions may clear bit 0-3. The
5111 * remaining contents of the DR6 register are never
5112 * cleared by the processor".
5113 */
5114 vcpu->arch.dr6 &= ~15;
5115 vcpu->arch.dr6 |= DR6_BS;
5116 kvm_queue_exception(vcpu, DB_VECTOR);
5117 }
5118 }
5119}
5120
4a1e10d5
PB		 5121static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5122{
5123 struct kvm_run *kvm_run = vcpu->run;
5124 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5125 u32 dr6 = 0;
5126
5127 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5128 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5129 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5130 vcpu->arch.guest_debug_dr7,
5131 vcpu->arch.eff_db);
5132
5133 if (dr6 != 0) {
5134 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5135 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5136 get_segment_base(vcpu, VCPU_SREG_CS);
5137
5138 kvm_run->debug.arch.exception = DB_VECTOR;
5139 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5140 *r = EMULATE_USER_EXIT;
5141 return true;
5142 }
5143 }
5144
5145 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5146 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5147 vcpu->arch.dr7,
5148 vcpu->arch.db);
5149
5150 if (dr6 != 0) {
5151 vcpu->arch.dr6 &= ~15;
5152 vcpu->arch.dr6 |= dr6;
5153 kvm_queue_exception(vcpu, DB_VECTOR);
5154 *r = EMULATE_DONE;
5155 return true;
5156 }
5157 }
5158
5159 return false;
5160}
5161
51d8b661
AP		 5162int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5163 unsigned long cr2,
dc25e89e
AP		 5164 int emulation_type,
5165 void *insn,
5166 int insn_len)
bbd9b64e 5167{
95cb2295 5168 int r;
9d74191a 5169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5170 bool writeback = true;
93c05d3e 5171 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5172
93c05d3e
XG		 5173 /*
5174 * Clear write_fault_to_shadow_pgtable here to ensure it is
5175 * never reused.
5176 */
5177 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5178 kvm_clear_exception_queue(vcpu);
8d7d8102 5179
571008da 5180 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5181 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5182
5183 /*
5184 * We will reenter on the same instruction since
5185 * we do not set complete_userspace_io. This does not
5186 * handle watchpoints yet, those would be handled in
5187 * the emulate_ops.
5188 */
5189 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5190 return r;
5191
9d74191a
TY		 5192 ctxt->interruptibility = 0;
5193 ctxt->have_exception = false;
5194 ctxt->perm_ok = false;
bbd9b64e 5195
b51e974f 5196 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5197
9d74191a 5198 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5199
e46479f8 5200 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5201 ++vcpu->stat.insn_emulation;
1d2887e2 5202 if (r != EMULATION_OK) {
4005996e
AK		 5203 if (emulation_type & EMULTYPE_TRAP_UD)
5204 return EMULATE_FAIL;
991eebf9
GN		 5205 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5206 emulation_type))
bbd9b64e 5207 return EMULATE_DONE;
6d77dbfc
GN		 5208 if (emulation_type & EMULTYPE_SKIP)
5209 return EMULATE_FAIL;
5210 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5211 }
5212 }
5213
ba8afb6b 5214 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5215 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5216 return EMULATE_DONE;
5217 }
5218
1cb3f3ae
XG		 5219 if (retry_instruction(ctxt, cr2, emulation_type))
5220 return EMULATE_DONE;
5221
7ae441ea 5222 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5223 changes registers values during IO operation */
7ae441ea
GN		 5224 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5225 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5226 emulator_invalidate_register_cache(ctxt);
7ae441ea 5227 }
4d2179e1 5228
5cd21917 5229restart:
9d74191a 5230 r = x86_emulate_insn(ctxt);
bbd9b64e 5231
775fde86
JR		 5232 if (r == EMULATION_INTERCEPTED)
5233 return EMULATE_DONE;
5234
d2ddd1c4 5235 if (r == EMULATION_FAILED) {
991eebf9
GN		 5236 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5237 emulation_type))
c3cd7ffa
GN		 5238 return EMULATE_DONE;
5239
6d77dbfc 5240 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5241 }
5242
9d74191a 5243 if (ctxt->have_exception) {
54b8486f 5244 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5245 r = EMULATE_DONE;
5246 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5247 if (!vcpu->arch.pio.in) {
5248 /* FIXME: return into emulator if single-stepping. */
3457e419 5249 vcpu->arch.pio.count = 0;
0912c977 5250 } else {
7ae441ea 5251 writeback = false;
716d51ab
GN		 5252 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5253 }
ac0a48c3 5254 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5255 } else if (vcpu->mmio_needed) {
5256 if (!vcpu->mmio_is_write)
5257 writeback = false;
ac0a48c3 5258 r = EMULATE_USER_EXIT;
716d51ab 5259 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5260 } else if (r == EMULATION_RESTART)
5cd21917 5261 goto restart;
d2ddd1c4
GN		 5262 else
5263 r = EMULATE_DONE;
f850e2e6 5264
7ae441ea 5265 if (writeback) {
9d74191a 5266 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5267 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5268 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5269 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5270 if (r == EMULATE_DONE)
5271 kvm_vcpu_check_singlestep(vcpu, &r);
5272 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5273 } else
5274 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5275
5276 return r;
de7d789a 5277}
51d8b661 5278EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5279
cf8f70bf 5280int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5281{
cf8f70bf 5282 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5283 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5284 size, port, &val, 1);
cf8f70bf 5285 /* do not return to emulator after return from userspace */
7972995b 5286 vcpu->arch.pio.count = 0;
de7d789a
CO		 5287 return ret;
5288}
cf8f70bf 5289EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5290
8cfdc000
ZA		 5291static void tsc_bad(void *info)
5292{
0a3aee0d 5293 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5294}
5295
5296static void tsc_khz_changed(void *data)
c8076604 5297{
8cfdc000
ZA		 5298 struct cpufreq_freqs *freq = data;
5299 unsigned long khz = 0;
5300
5301 if (data)
5302 khz = freq->new;
5303 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5304 khz = cpufreq_quick_get(raw_smp_processor_id());
5305 if (!khz)
5306 khz = tsc_khz;
0a3aee0d 5307 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5308}
5309
c8076604
GH		 5310static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5311 void *data)
5312{
5313 struct cpufreq_freqs *freq = data;
5314 struct kvm *kvm;
5315 struct kvm_vcpu *vcpu;
5316 int i, send_ipi = 0;
5317
8cfdc000
ZA		 5318 /*
5319 * We allow guests to temporarily run on slowing clocks,
5320 * provided we notify them after, or to run on accelerating
5321 * clocks, provided we notify them before. Thus time never
5322 * goes backwards.
5323 *
5324 * However, we have a problem. We can't atomically update
5325 * the frequency of a given CPU from this function; it is
5326 * merely a notifier, which can be called from any CPU.
5327 * Changing the TSC frequency at arbitrary points in time
5328 * requires a recomputation of local variables related to
5329 * the TSC for each VCPU. We must flag these local variables
5330 * to be updated and be sure the update takes place with the
5331 * new frequency before any guests proceed.
5332 *
5333 * Unfortunately, the combination of hotplug CPU and frequency
5334 * change creates an intractable locking scenario; the order
5335 * of when these callouts happen is undefined with respect to
5336 * CPU hotplug, and they can race with each other. As such,
5337 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5338 * undefined; you can actually have a CPU frequency change take
5339 * place in between the computation of X and the setting of the
5340 * variable. To protect against this problem, all updates of
5341 * the per_cpu tsc_khz variable are done in an interrupt
5342 * protected IPI, and all callers wishing to update the value
5343 * must wait for a synchronous IPI to complete (which is trivial
5344 * if the caller is on the CPU already). This establishes the
5345 * necessary total order on variable updates.
5346 *
5347 * Note that because a guest time update may take place
5348 * anytime after the setting of the VCPU's request bit, the
5349 * correct TSC value must be set before the request. However,
5350 * to ensure the update actually makes it to any guest which
5351 * starts running in hardware virtualization between the set
5352 * and the acquisition of the spinlock, we must also ping the
5353 * CPU after setting the request bit.
5354 *
5355 */
5356
c8076604
GH		 5357 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5358 return 0;
5359 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5360 return 0;
8cfdc000
ZA		 5361
5362 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5363
2f303b74 5364 spin_lock(&kvm_lock);
c8076604 5365 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5366 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5367 if (vcpu->cpu != freq->cpu)
5368 continue;
c285545f 5369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5370 if (vcpu->cpu != smp_processor_id())
8cfdc000 5371 send_ipi = 1;
c8076604
GH		 5372 }
5373 }
2f303b74 5374 spin_unlock(&kvm_lock);
c8076604
GH		 5375
5376 if (freq->old < freq->new && send_ipi) {
5377 /*
5378 * We upscale the frequency. Must make the guest
5379 * doesn't see old kvmclock values while running with
5380 * the new frequency, otherwise we risk the guest sees
5381 * time go backwards.
5382 *
5383 * In case we update the frequency for another cpu
5384 * (which might be in guest context) send an interrupt
5385 * to kick the cpu out of guest context. Next time
5386 * guest context is entered kvmclock will be updated,
5387 * so the guest will not see stale values.
5388 */
8cfdc000 5389 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5390 }
5391 return 0;
5392}
5393
5394static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5395 .notifier_call = kvmclock_cpufreq_notifier
5396};
5397
5398static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5399 unsigned long action, void *hcpu)
5400{
5401 unsigned int cpu = (unsigned long)hcpu;
5402
5403 switch (action) {
5404 case CPU_ONLINE:
5405 case CPU_DOWN_FAILED:
5406 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5407 break;
5408 case CPU_DOWN_PREPARE:
5409 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5410 break;
5411 }
5412 return NOTIFY_OK;
5413}
5414
5415static struct notifier_block kvmclock_cpu_notifier_block = {
5416 .notifier_call = kvmclock_cpu_notifier,
5417 .priority = -INT_MAX
c8076604
GH		 5418};
5419
b820cc0c
ZA		 5420static void kvm_timer_init(void)
5421{
5422 int cpu;
5423
c285545f 5424 max_tsc_khz = tsc_khz;
8cfdc000 5425 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5426 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5427#ifdef CONFIG_CPU_FREQ
5428 struct cpufreq_policy policy;
5429 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5430 cpu = get_cpu();
5431 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5432 if (policy.cpuinfo.max_freq)
5433 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5434 put_cpu();
c285545f 5435#endif
b820cc0c
ZA		 5436 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5437 CPUFREQ_TRANSITION_NOTIFIER);
5438 }
c285545f 5439 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5440 for_each_online_cpu(cpu)
5441 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5442}
5443
ff9d07a0
ZY		 5444static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5445
f5132b01 5446int kvm_is_in_guest(void)
ff9d07a0 5447{
086c9855 5448 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5449}
5450
5451static int kvm_is_user_mode(void)
5452{
5453 int user_mode = 3;
dcf46b94 5454
086c9855
AS		 5455 if (__this_cpu_read(current_vcpu))
5456 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5457
ff9d07a0
ZY		 5458 return user_mode != 0;
5459}
5460
5461static unsigned long kvm_get_guest_ip(void)
5462{
5463 unsigned long ip = 0;
dcf46b94 5464
086c9855
AS		 5465 if (__this_cpu_read(current_vcpu))
5466 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5467
ff9d07a0
ZY		 5468 return ip;
5469}
5470
5471static struct perf_guest_info_callbacks kvm_guest_cbs = {
5472 .is_in_guest = kvm_is_in_guest,
5473 .is_user_mode = kvm_is_user_mode,
5474 .get_guest_ip = kvm_get_guest_ip,
5475};
5476
5477void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5478{
086c9855 5479 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5480}
5481EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5482
5483void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5484{
086c9855 5485 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5486}
5487EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5488
ce88decf
XG		 5489static void kvm_set_mmio_spte_mask(void)
5490{
5491 u64 mask;
5492 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5493
5494 /*
5495 * Set the reserved bits and the present bit of an paging-structure
5496 * entry to generate page fault with PFER.RSV = 1.
5497 */
885032b9
XG		 5498 /* Mask the reserved physical address bits. */
5499 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5500
5501 /* Bit 62 is always reserved for 32bit host. */
5502 mask |= 0x3ull << 62;
5503
5504 /* Set the present bit. */
ce88decf
XG		 5505 mask |= 1ull;
5506
5507#ifdef CONFIG_X86_64
5508 /*
5509 * If reserved bit is not supported, clear the present bit to disable
5510 * mmio page fault.
5511 */
5512 if (maxphyaddr == 52)
5513 mask &= ~1ull;
5514#endif
5515
5516 kvm_mmu_set_mmio_spte_mask(mask);
5517}
5518
16e8d74d
MT		 5519#ifdef CONFIG_X86_64
5520static void pvclock_gtod_update_fn(struct work_struct *work)
5521{
d828199e
MT		 5522 struct kvm *kvm;
5523
5524 struct kvm_vcpu *vcpu;
5525 int i;
5526
2f303b74 5527 spin_lock(&kvm_lock);
d828199e
MT		 5528 list_for_each_entry(kvm, &vm_list, vm_list)
5529 kvm_for_each_vcpu(i, vcpu, kvm)
5530 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5531 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5532 spin_unlock(&kvm_lock);
16e8d74d
MT		 5533}
5534
5535static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5536
5537/*
5538 * Notification about pvclock gtod data update.
5539 */
5540static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5541 void *priv)
5542{
5543 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5544 struct timekeeper *tk = priv;
5545
5546 update_pvclock_gtod(tk);
5547
5548 /* disable master clock if host does not trust, or does not
5549 * use, TSC clocksource
5550 */
5551 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5552 atomic_read(&kvm_guest_has_master_clock) != 0)
5553 queue_work(system_long_wq, &pvclock_gtod_work);
5554
5555 return 0;
5556}
5557
5558static struct notifier_block pvclock_gtod_notifier = {
5559 .notifier_call = pvclock_gtod_notify,
5560};
5561#endif
5562
f8c16bba 5563int kvm_arch_init(void *opaque)
043405e1 5564{
b820cc0c 5565 int r;
6b61edf7 5566 struct kvm_x86_ops *ops = opaque;
f8c16bba 5567
f8c16bba
ZX		 5568 if (kvm_x86_ops) {
5569 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5570 r = -EEXIST;
5571 goto out;
f8c16bba
ZX		 5572 }
5573
5574 if (!ops->cpu_has_kvm_support()) {
5575 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5576 r = -EOPNOTSUPP;
5577 goto out;
f8c16bba
ZX		 5578 }
5579 if (ops->disabled_by_bios()) {
5580 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5581 r = -EOPNOTSUPP;
5582 goto out;
f8c16bba
ZX		 5583 }
5584
013f6a5d
MT		 5585 r = -ENOMEM;
5586 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5587 if (!shared_msrs) {
5588 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5589 goto out;
5590 }
5591
97db56ce
AK		 5592 r = kvm_mmu_module_init();
5593 if (r)
013f6a5d 5594 goto out_free_percpu;
97db56ce 5595
ce88decf 5596 kvm_set_mmio_spte_mask();
97db56ce 5597
f8c16bba 5598 kvm_x86_ops = ops;
920c8377
PB		 5599 kvm_init_msr_list();
5600
7b52345e 5601 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5602 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5603
b820cc0c 5604 kvm_timer_init();
c8076604 5605
ff9d07a0
ZY		 5606 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5607
2acf923e
DC		 5608 if (cpu_has_xsave)
5609 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5610
c5cc421b 5611 kvm_lapic_init();
16e8d74d
MT		 5612#ifdef CONFIG_X86_64
5613 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5614#endif
5615
f8c16bba 5616 return 0;
56c6d28a 5617
013f6a5d
MT		 5618out_free_percpu:
5619 free_percpu(shared_msrs);
56c6d28a 5620out:
56c6d28a 5621 return r;
043405e1 5622}
8776e519 5623
f8c16bba
ZX		 5624void kvm_arch_exit(void)
5625{
ff9d07a0
ZY		 5626 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5627
888d256e
JK		 5628 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5629 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5630 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5631 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5632#ifdef CONFIG_X86_64
5633 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5634#endif
f8c16bba 5635 kvm_x86_ops = NULL;
56c6d28a 5636 kvm_mmu_module_exit();
013f6a5d 5637 free_percpu(shared_msrs);
56c6d28a 5638}
f8c16bba 5639
8776e519
HB		 5640int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5641{
5642 ++vcpu->stat.halt_exits;
5643 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5644 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5645 return 1;
5646 } else {
5647 vcpu->run->exit_reason = KVM_EXIT_HLT;
5648 return 0;
5649 }
5650}
5651EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5652
55cd8e5a
GN		 5653int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5654{
5655 u64 param, ingpa, outgpa, ret;
5656 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5657 bool fast, longmode;
5658 int cs_db, cs_l;
5659
5660 /*
5661 * hypercall generates UD from non zero cpl and real mode
5662 * per HYPER-V spec
5663 */
3eeb3288 5664 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5665 kvm_queue_exception(vcpu, UD_VECTOR);
5666 return 0;
5667 }
5668
5669 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5670 longmode = is_long_mode(vcpu) && cs_l == 1;
5671
5672 if (!longmode) {
ccd46936
GN		 5673 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5674 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5675 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5676 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5677 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5678 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5679 }
5680#ifdef CONFIG_X86_64
5681 else {
5682 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5683 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5684 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5685 }
5686#endif
5687
5688 code = param & 0xffff;
5689 fast = (param >> 16) & 0x1;
5690 rep_cnt = (param >> 32) & 0xfff;
5691 rep_idx = (param >> 48) & 0xfff;
5692
5693 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5694
c25bc163
GN		 5695 switch (code) {
5696 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5697 kvm_vcpu_on_spin(vcpu);
5698 break;
5699 default:
5700 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5701 break;
5702 }
55cd8e5a
GN		 5703
5704 ret = res | (((u64)rep_done & 0xfff) << 32);
5705 if (longmode) {
5706 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5707 } else {
5708 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5709 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5710 }
5711
5712 return 1;
5713}
5714
6aef266c
SV		 5715/*
5716 * kvm_pv_kick_cpu_op: Kick a vcpu.
5717 *
5718 * @apicid - apicid of vcpu to be kicked.
5719 */
5720static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5721{
24d2166b 5722 struct kvm_lapic_irq lapic_irq;
6aef266c 5723
24d2166b
R		 5724 lapic_irq.shorthand = 0;
5725 lapic_irq.dest_mode = 0;
5726 lapic_irq.dest_id = apicid;
6aef266c 5727
24d2166b
R		 5728 lapic_irq.delivery_mode = APIC_DM_REMRD;
5729 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5730}
5731
8776e519
HB		 5732int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5733{
5734 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5735 int r = 1;
8776e519 5736
55cd8e5a
GN		 5737 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5738 return kvm_hv_hypercall(vcpu);
5739
5fdbf976
MT		 5740 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5741 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5742 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5743 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5744 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5745
229456fc 5746 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5747
8776e519
HB		 5748 if (!is_long_mode(vcpu)) {
5749 nr &= 0xFFFFFFFF;
5750 a0 &= 0xFFFFFFFF;
5751 a1 &= 0xFFFFFFFF;
5752 a2 &= 0xFFFFFFFF;
5753 a3 &= 0xFFFFFFFF;
5754 }
5755
07708c4a
JK		 5756 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5757 ret = -KVM_EPERM;
5758 goto out;
5759 }
5760
8776e519 5761 switch (nr) {
b93463aa
AK		 5762 case KVM_HC_VAPIC_POLL_IRQ:
5763 ret = 0;
5764 break;
6aef266c
SV		 5765 case KVM_HC_KICK_CPU:
5766 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5767 ret = 0;
5768 break;
8776e519
HB		 5769 default:
5770 ret = -KVM_ENOSYS;
5771 break;
5772 }
07708c4a 5773out:
5fdbf976 5774 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5775 ++vcpu->stat.hypercalls;
2f333bcb 5776 return r;
8776e519
HB		 5777}
5778EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5779
b6785def 5780static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5781{
d6aa1000 5782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5783 char instruction[3];
5fdbf976 5784 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5785
8776e519 5786 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5787
9d74191a 5788 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5789}
5790
b6c7a5dc
HB		 5791/*
5792 * Check if userspace requested an interrupt window, and that the
5793 * interrupt window is open.
5794 *
5795 * No need to exit to userspace if we already have an interrupt queued.
5796 */
851ba692 5797static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5798{
8061823a 5799 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5800 vcpu->run->request_interrupt_window &&
5df56646 5801 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5802}
5803
851ba692 5804static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5805{
851ba692
AK		 5806 struct kvm_run *kvm_run = vcpu->run;
5807
91586a3b 5808 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5809 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5810 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5811 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5812 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5813 else
b6c7a5dc 5814 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5815 kvm_arch_interrupt_allowed(vcpu) &&
5816 !kvm_cpu_has_interrupt(vcpu) &&
5817 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5818}
5819
95ba8273
GN		 5820static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5821{
5822 int max_irr, tpr;
5823
5824 if (!kvm_x86_ops->update_cr8_intercept)
5825 return;
5826
88c808fd
AK		 5827 if (!vcpu->arch.apic)
5828 return;
5829
8db3baa2
GN		 5830 if (!vcpu->arch.apic->vapic_addr)
5831 max_irr = kvm_lapic_find_highest_irr(vcpu);
5832 else
5833 max_irr = -1;
95ba8273
GN		 5834
5835 if (max_irr != -1)
5836 max_irr >>= 4;
5837
5838 tpr = kvm_lapic_get_cr8(vcpu);
5839
5840 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5841}
5842
b6b8a145 5843static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5844{
b6b8a145
JK		 5845 int r;
5846
95ba8273 5847 /* try to reinject previous events if any */
b59bb7bd 5848 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5849 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5850 vcpu->arch.exception.has_error_code,
5851 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5852 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5853 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5854 vcpu->arch.exception.error_code,
5855 vcpu->arch.exception.reinject);
b6b8a145 5856 return 0;
b59bb7bd
GN		 5857 }
5858
95ba8273
GN		 5859 if (vcpu->arch.nmi_injected) {
5860 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5861 return 0;
95ba8273
GN		 5862 }
5863
5864 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5865 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5866 return 0;
5867 }
5868
5869 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5870 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5871 if (r != 0)
5872 return r;
95ba8273
GN		 5873 }
5874
5875 /* try to inject new event if pending */
5876 if (vcpu->arch.nmi_pending) {
5877 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5878 --vcpu->arch.nmi_pending;
95ba8273
GN		 5879 vcpu->arch.nmi_injected = true;
5880 kvm_x86_ops->set_nmi(vcpu);
5881 }
c7c9c56c 5882 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5883 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5884 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5885 false);
5886 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5887 }
5888 }
b6b8a145 5889 return 0;
95ba8273
GN		 5890}
5891
7460fb4a
AK		 5892static void process_nmi(struct kvm_vcpu *vcpu)
5893{
5894 unsigned limit = 2;
5895
5896 /*
5897 * x86 is limited to one NMI running, and one NMI pending after it.
5898 * If an NMI is already in progress, limit further NMIs to just one.
5899 * Otherwise, allow two (and we'll inject the first one immediately).
5900 */
5901 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5902 limit = 1;
5903
5904 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5905 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5906 kvm_make_request(KVM_REQ_EVENT, vcpu);
5907}
5908
3d81bc7e 5909static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5910{
5911 u64 eoi_exit_bitmap[4];
cf9e65b7 5912 u32 tmr[8];
c7c9c56c 5913
3d81bc7e
YZ		 5914 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5915 return;
c7c9c56c
YZ		 5916
5917 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5918 memset(tmr, 0, 32);
c7c9c56c 5919
cf9e65b7 5920 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5921 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5922 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5923}
5924
9357d939
TY		 5925/*
5926 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5927 * exiting to the userspace. Otherwise, the value will be returned to the
5928 * userspace.
5929 */
851ba692 5930static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5931{
5932 int r;
6a8b1d13 5933 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5934 vcpu->run->request_interrupt_window;
730dca42 5935 bool req_immediate_exit = false;
b6c7a5dc 5936
3e007509 5937 if (vcpu->requests) {
a8eeb04a 5938 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5939 kvm_mmu_unload(vcpu);
a8eeb04a 5940 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5941 __kvm_migrate_timers(vcpu);
d828199e
MT		 5942 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5943 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5944 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5945 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5946 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5947 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5948 if (unlikely(r))
5949 goto out;
5950 }
a8eeb04a 5951 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5952 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5953 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5954 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5955 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5956 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5957 r = 0;
5958 goto out;
5959 }
a8eeb04a 5960 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5961 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5962 r = 0;
5963 goto out;
5964 }
a8eeb04a 5965 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5966 vcpu->fpu_active = 0;
5967 kvm_x86_ops->fpu_deactivate(vcpu);
5968 }
af585b92
GN		 5969 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5970 /* Page is swapped out. Do synthetic halt */
5971 vcpu->arch.apf.halted = true;
5972 r = 1;
5973 goto out;
5974 }
c9aaa895
GC		 5975 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5976 record_steal_time(vcpu);
7460fb4a
AK		 5977 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5978 process_nmi(vcpu);
f5132b01
GN		 5979 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5980 kvm_handle_pmu_event(vcpu);
5981 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5982 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5983 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5984 vcpu_scan_ioapic(vcpu);
2f52d58c 5985 }
b93463aa 5986
b463a6f7 5987 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5988 kvm_apic_accept_events(vcpu);
5989 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5990 r = 1;
5991 goto out;
5992 }
5993
b6b8a145
JK		 5994 if (inject_pending_event(vcpu, req_int_win) != 0)
5995 req_immediate_exit = true;
b463a6f7 5996 /* enable NMI/IRQ window open exits if needed */
b6b8a145 5997 else if (vcpu->arch.nmi_pending)
c9a7953f 5998 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5999 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6000 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6001
6002 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6003 /*
6004 * Update architecture specific hints for APIC
6005 * virtual interrupt delivery.
6006 */
6007 if (kvm_x86_ops->hwapic_irr_update)
6008 kvm_x86_ops->hwapic_irr_update(vcpu,
6009 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6010 update_cr8_intercept(vcpu);
6011 kvm_lapic_sync_to_vapic(vcpu);
6012 }
6013 }
6014
d8368af8
AK		 6015 r = kvm_mmu_reload(vcpu);
6016 if (unlikely(r)) {
d905c069 6017 goto cancel_injection;
d8368af8
AK		 6018 }
6019
b6c7a5dc
HB		 6020 preempt_disable();
6021
6022 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6023 if (vcpu->fpu_active)
6024 kvm_load_guest_fpu(vcpu);
2acf923e 6025 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6026
6b7e2d09
XG		 6027 vcpu->mode = IN_GUEST_MODE;
6028
01b71917
MT		 6029 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6030
6b7e2d09
XG		 6031 /* We should set ->mode before check ->requests,
6032 * see the comment in make_all_cpus_request.
6033 */
01b71917 6034 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6035
d94e1dc9 6036 local_irq_disable();
32f88400 6037
6b7e2d09 6038 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6039 || need_resched() || signal_pending(current)) {
6b7e2d09 6040 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6041 smp_wmb();
6c142801
AK		 6042 local_irq_enable();
6043 preempt_enable();
01b71917 6044 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6045 r = 1;
d905c069 6046 goto cancel_injection;
6c142801
AK		 6047 }
6048
d6185f20
NHE		 6049 if (req_immediate_exit)
6050 smp_send_reschedule(vcpu->cpu);
6051
b6c7a5dc
HB		 6052 kvm_guest_enter();
6053
42dbaa5a 6054 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6055 set_debugreg(0, 7);
6056 set_debugreg(vcpu->arch.eff_db[0], 0);
6057 set_debugreg(vcpu->arch.eff_db[1], 1);
6058 set_debugreg(vcpu->arch.eff_db[2], 2);
6059 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6060 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6061 }
b6c7a5dc 6062
229456fc 6063 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6064 kvm_x86_ops->run(vcpu);
b6c7a5dc 6065
c77fb5fe
PB		 6066 /*
6067 * Do this here before restoring debug registers on the host. And
6068 * since we do this before handling the vmexit, a DR access vmexit
6069 * can (a) read the correct value of the debug registers, (b) set
6070 * KVM_DEBUGREG_WONT_EXIT again.
6071 */
6072 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6073 int i;
6074
6075 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6076 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6077 for (i = 0; i < KVM_NR_DB_REGS; i++)
6078 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6079 }
6080
24f1e32c
FW		 6081 /*
6082 * If the guest has used debug registers, at least dr7
6083 * will be disabled while returning to the host.
6084 * If we don't have active breakpoints in the host, we don't
6085 * care about the messed up debug address registers. But if
6086 * we have some of them active, restore the old state.
6087 */
59d8eb53 6088 if (hw_breakpoint_active())
24f1e32c 6089 hw_breakpoint_restore();
42dbaa5a 6090
886b470c
MT		 6091 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6092 native_read_tsc());
1d5f066e 6093
6b7e2d09 6094 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6095 smp_wmb();
a547c6db
YZ		 6096
6097 /* Interrupt is enabled by handle_external_intr() */
6098 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6099
6100 ++vcpu->stat.exits;
6101
6102 /*
6103 * We must have an instruction between local_irq_enable() and
6104 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6105 * the interrupt shadow. The stat.exits increment will do nicely.
6106 * But we need to prevent reordering, hence this barrier():
6107 */
6108 barrier();
6109
6110 kvm_guest_exit();
6111
6112 preempt_enable();
6113
f656ce01 6114 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6115
b6c7a5dc
HB		 6116 /*
6117 * Profile KVM exit RIPs:
6118 */
6119 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6120 unsigned long rip = kvm_rip_read(vcpu);
6121 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6122 }
6123
cc578287
ZA		 6124 if (unlikely(vcpu->arch.tsc_always_catchup))
6125 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6126
5cfb1d5a
MT		 6127 if (vcpu->arch.apic_attention)
6128 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6129
851ba692 6130 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6131 return r;
6132
6133cancel_injection:
6134 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6135 if (unlikely(vcpu->arch.apic_attention))
6136 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6137out:
6138 return r;
6139}
b6c7a5dc 6140
09cec754 6141
851ba692 6142static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6143{
6144 int r;
f656ce01 6145 struct kvm *kvm = vcpu->kvm;
d7690175 6146
f656ce01 6147 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6148
6149 r = 1;
6150 while (r > 0) {
af585b92
GN		 6151 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6152 !vcpu->arch.apf.halted)
851ba692 6153 r = vcpu_enter_guest(vcpu);
d7690175 6154 else {
f656ce01 6155 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6156 kvm_vcpu_block(vcpu);
f656ce01 6157 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6158 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6159 kvm_apic_accept_events(vcpu);
09cec754
GN		 6160 switch(vcpu->arch.mp_state) {
6161 case KVM_MP_STATE_HALTED:
6aef266c 6162 vcpu->arch.pv.pv_unhalted = false;
d7690175 6163 vcpu->arch.mp_state =
09cec754
GN		 6164 KVM_MP_STATE_RUNNABLE;
6165 case KVM_MP_STATE_RUNNABLE:
af585b92 6166 vcpu->arch.apf.halted = false;
09cec754 6167 break;
66450a21
JK		 6168 case KVM_MP_STATE_INIT_RECEIVED:
6169 break;
09cec754
GN		 6170 default:
6171 r = -EINTR;
6172 break;
6173 }
6174 }
d7690175
MT		 6175 }
6176
09cec754
GN		 6177 if (r <= 0)
6178 break;
6179
6180 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6181 if (kvm_cpu_has_pending_timer(vcpu))
6182 kvm_inject_pending_timer_irqs(vcpu);
6183
851ba692 6184 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6185 r = -EINTR;
851ba692 6186 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6187 ++vcpu->stat.request_irq_exits;
6188 }
af585b92
GN		 6189
6190 kvm_check_async_pf_completion(vcpu);
6191
09cec754
GN		 6192 if (signal_pending(current)) {
6193 r = -EINTR;
851ba692 6194 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6195 ++vcpu->stat.signal_exits;
6196 }
6197 if (need_resched()) {
f656ce01 6198 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6199 cond_resched();
f656ce01 6200 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6201 }
b6c7a5dc
HB		 6202 }
6203
f656ce01 6204 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6205
6206 return r;
6207}
6208
716d51ab
GN		 6209static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6210{
6211 int r;
6212 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6213 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6214 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6215 if (r != EMULATE_DONE)
6216 return 0;
6217 return 1;
6218}
6219
6220static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6221{
6222 BUG_ON(!vcpu->arch.pio.count);
6223
6224 return complete_emulated_io(vcpu);
6225}
6226
f78146b0
AK		 6227/*
6228 * Implements the following, as a state machine:
6229 *
6230 * read:
6231 * for each fragment
87da7e66
XG		 6232 * for each mmio piece in the fragment
6233 * write gpa, len
6234 * exit
6235 * copy data
f78146b0
AK		 6236 * execute insn
6237 *
6238 * write:
6239 * for each fragment
87da7e66
XG		 6240 * for each mmio piece in the fragment
6241 * write gpa, len
6242 * copy data
6243 * exit
f78146b0 6244 */
716d51ab 6245static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6246{
6247 struct kvm_run *run = vcpu->run;
f78146b0 6248 struct kvm_mmio_fragment *frag;
87da7e66 6249 unsigned len;
5287f194 6250
716d51ab 6251 BUG_ON(!vcpu->mmio_needed);
5287f194 6252
716d51ab 6253 /* Complete previous fragment */
87da7e66
XG		 6254 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6255 len = min(8u, frag->len);
716d51ab 6256 if (!vcpu->mmio_is_write)
87da7e66
XG		 6257 memcpy(frag->data, run->mmio.data, len);
6258
6259 if (frag->len <= 8) {
6260 /* Switch to the next fragment. */
6261 frag++;
6262 vcpu->mmio_cur_fragment++;
6263 } else {
6264 /* Go forward to the next mmio piece. */
6265 frag->data += len;
6266 frag->gpa += len;
6267 frag->len -= len;
6268 }
6269
a08d3b3b 6270 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6271 vcpu->mmio_needed = 0;
0912c977
PB		 6272
6273 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6274 if (vcpu->mmio_is_write)
716d51ab
GN		 6275 return 1;
6276 vcpu->mmio_read_completed = 1;
6277 return complete_emulated_io(vcpu);
6278 }
87da7e66 6279
716d51ab
GN		 6280 run->exit_reason = KVM_EXIT_MMIO;
6281 run->mmio.phys_addr = frag->gpa;
6282 if (vcpu->mmio_is_write)
87da7e66
XG		 6283 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6284 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6285 run->mmio.is_write = vcpu->mmio_is_write;
6286 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6287 return 0;
5287f194
AK		 6288}
6289
716d51ab 6290
b6c7a5dc
HB		 6291int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6292{
6293 int r;
6294 sigset_t sigsaved;
6295
e5c30142
AK		 6296 if (!tsk_used_math(current) && init_fpu(current))
6297 return -ENOMEM;
6298
ac9f6dc0
AK		 6299 if (vcpu->sigset_active)
6300 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6301
a4535290 6302 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6303 kvm_vcpu_block(vcpu);
66450a21 6304 kvm_apic_accept_events(vcpu);
d7690175 6305 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6306 r = -EAGAIN;
6307 goto out;
b6c7a5dc
HB		 6308 }
6309
b6c7a5dc 6310 /* re-sync apic's tpr */
eea1cff9
AP		 6311 if (!irqchip_in_kernel(vcpu->kvm)) {
6312 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6313 r = -EINVAL;
6314 goto out;
6315 }
6316 }
b6c7a5dc 6317
716d51ab
GN		 6318 if (unlikely(vcpu->arch.complete_userspace_io)) {
6319 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6320 vcpu->arch.complete_userspace_io = NULL;
6321 r = cui(vcpu);
6322 if (r <= 0)
6323 goto out;
6324 } else
6325 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6326
851ba692 6327 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6328
6329out:
f1d86e46 6330 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6331 if (vcpu->sigset_active)
6332 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6333
b6c7a5dc
HB		 6334 return r;
6335}
6336
6337int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6338{
7ae441ea
GN		 6339 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6340 /*
6341 * We are here if userspace calls get_regs() in the middle of
6342 * instruction emulation. Registers state needs to be copied
4a969980 6343 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6344 * that usually, but some bad designed PV devices (vmware
6345 * backdoor interface) need this to work
6346 */
dd856efa 6347 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6348 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6349 }
5fdbf976
MT		 6350 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6351 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6352 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6353 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6354 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6355 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6356 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6357 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6358#ifdef CONFIG_X86_64
5fdbf976
MT		 6359 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6360 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6361 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6362 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6363 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6364 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6365 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6366 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6367#endif
6368
5fdbf976 6369 regs->rip = kvm_rip_read(vcpu);
91586a3b 6370 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6371
b6c7a5dc
HB		 6372 return 0;
6373}
6374
6375int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6376{
7ae441ea
GN		 6377 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6378 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6379
5fdbf976
MT		 6380 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6381 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6382 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6383 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6384 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6385 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6386 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6387 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6388#ifdef CONFIG_X86_64
5fdbf976
MT		 6389 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6390 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6391 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6392 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6393 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6394 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6395 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6396 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6397#endif
6398
5fdbf976 6399 kvm_rip_write(vcpu, regs->rip);
91586a3b 6400 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6401
b4f14abd
JK		 6402 vcpu->arch.exception.pending = false;
6403
3842d135
AK		 6404 kvm_make_request(KVM_REQ_EVENT, vcpu);
6405
b6c7a5dc
HB		 6406 return 0;
6407}
6408
b6c7a5dc
HB		 6409void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6410{
6411 struct kvm_segment cs;
6412
3e6e0aab 6413 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6414 *db = cs.db;
6415 *l = cs.l;
6416}
6417EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6418
6419int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6420 struct kvm_sregs *sregs)
6421{
89a27f4d 6422 struct desc_ptr dt;
b6c7a5dc 6423
3e6e0aab
GT		 6424 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6425 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6426 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6427 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6428 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6429 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6430
3e6e0aab
GT		 6431 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6432 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6433
6434 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6435 sregs->idt.limit = dt.size;
6436 sregs->idt.base = dt.address;
b6c7a5dc 6437 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6438 sregs->gdt.limit = dt.size;
6439 sregs->gdt.base = dt.address;
b6c7a5dc 6440
4d4ec087 6441 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6442 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6443 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6444 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6445 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6446 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6447 sregs->apic_base = kvm_get_apic_base(vcpu);
6448
923c61bb 6449 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6450
36752c9b 6451 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6452 set_bit(vcpu->arch.interrupt.nr,
6453 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6454
b6c7a5dc
HB		 6455 return 0;
6456}
6457
62d9f0db
MT		 6458int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6459 struct kvm_mp_state *mp_state)
6460{
66450a21 6461 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6462 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6463 vcpu->arch.pv.pv_unhalted)
6464 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6465 else
6466 mp_state->mp_state = vcpu->arch.mp_state;
6467
62d9f0db
MT		 6468 return 0;
6469}
6470
6471int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6472 struct kvm_mp_state *mp_state)
6473{
66450a21
JK		 6474 if (!kvm_vcpu_has_lapic(vcpu) &&
6475 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6476 return -EINVAL;
6477
6478 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6479 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6480 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6481 } else
6482 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6483 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6484 return 0;
6485}
6486
7f3d35fd
KW		 6487int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6488 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6489{
9d74191a 6490 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6491 int ret;
e01c2426 6492
8ec4722d 6493 init_emulate_ctxt(vcpu);
c697518a 6494
7f3d35fd 6495 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6496 has_error_code, error_code);
c697518a 6497
c697518a 6498 if (ret)
19d04437 6499 return EMULATE_FAIL;
37817f29 6500
9d74191a
TY		 6501 kvm_rip_write(vcpu, ctxt->eip);
6502 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6503 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6504 return EMULATE_DONE;
37817f29
IE		 6505}
6506EXPORT_SYMBOL_GPL(kvm_task_switch);
6507
b6c7a5dc
HB		 6508int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6509 struct kvm_sregs *sregs)
6510{
58cb628d 6511 struct msr_data apic_base_msr;
b6c7a5dc 6512 int mmu_reset_needed = 0;
63f42e02 6513 int pending_vec, max_bits, idx;
89a27f4d 6514 struct desc_ptr dt;
b6c7a5dc 6515
6d1068b3
PM		 6516 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6517 return -EINVAL;
6518
89a27f4d
GN		 6519 dt.size = sregs->idt.limit;
6520 dt.address = sregs->idt.base;
b6c7a5dc 6521 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6522 dt.size = sregs->gdt.limit;
6523 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6524 kvm_x86_ops->set_gdt(vcpu, &dt);
6525
ad312c7c 6526 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6527 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6528 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6529 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6530
2d3ad1f4 6531 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6532
f6801dff 6533 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6534 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6535 apic_base_msr.data = sregs->apic_base;
6536 apic_base_msr.host_initiated = true;
6537 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6538
4d4ec087 6539 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6540 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6541 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6542
fc78f519 6543 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6544 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6545 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6546 kvm_update_cpuid(vcpu);
63f42e02
XG		 6547
6548 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6549 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6550 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6551 mmu_reset_needed = 1;
6552 }
63f42e02 6553 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6554
6555 if (mmu_reset_needed)
6556 kvm_mmu_reset_context(vcpu);
6557
a50abc3b 6558 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6559 pending_vec = find_first_bit(
6560 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6561 if (pending_vec < max_bits) {
66fd3f7f 6562 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6563 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6564 }
6565
3e6e0aab
GT		 6566 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6567 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6568 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6569 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6570 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6571 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6572
3e6e0aab
GT		 6573 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6574 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6575
5f0269f5
ME		 6576 update_cr8_intercept(vcpu);
6577
9c3e4aab 6578 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6579 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6580 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6581 !is_protmode(vcpu))
9c3e4aab
MT		 6582 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6583
3842d135
AK		 6584 kvm_make_request(KVM_REQ_EVENT, vcpu);
6585
b6c7a5dc
HB		 6586 return 0;
6587}
6588
d0bfb940
JK		 6589int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6590 struct kvm_guest_debug *dbg)
b6c7a5dc 6591{
355be0b9 6592 unsigned long rflags;
ae675ef0 6593 int i, r;
b6c7a5dc 6594
4f926bf2
JK		 6595 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6596 r = -EBUSY;
6597 if (vcpu->arch.exception.pending)
2122ff5e 6598 goto out;
4f926bf2
JK		 6599 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6600 kvm_queue_exception(vcpu, DB_VECTOR);
6601 else
6602 kvm_queue_exception(vcpu, BP_VECTOR);
6603 }
6604
91586a3b
JK		 6605 /*
6606 * Read rflags as long as potentially injected trace flags are still
6607 * filtered out.
6608 */
6609 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6610
6611 vcpu->guest_debug = dbg->control;
6612 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6613 vcpu->guest_debug = 0;
6614
6615 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6616 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6617 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6618 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6619 } else {
6620 for (i = 0; i < KVM_NR_DB_REGS; i++)
6621 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6622 }
c8639010 6623 kvm_update_dr7(vcpu);
ae675ef0 6624
f92653ee
JK		 6625 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6626 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6627 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6628
91586a3b
JK		 6629 /*
6630 * Trigger an rflags update that will inject or remove the trace
6631 * flags.
6632 */
6633 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6634
c8639010 6635 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6636
4f926bf2 6637 r = 0;
d0bfb940 6638
2122ff5e 6639out:
b6c7a5dc
HB		 6640
6641 return r;
6642}
6643
8b006791
ZX		 6644/*
6645 * Translate a guest virtual address to a guest physical address.
6646 */
6647int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6648 struct kvm_translation *tr)
6649{
6650 unsigned long vaddr = tr->linear_address;
6651 gpa_t gpa;
f656ce01 6652 int idx;
8b006791 6653
f656ce01 6654 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6655 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6656 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6657 tr->physical_address = gpa;
6658 tr->valid = gpa != UNMAPPED_GVA;
6659 tr->writeable = 1;
6660 tr->usermode = 0;
8b006791
ZX		 6661
6662 return 0;
6663}
6664
d0752060
HB		 6665int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6666{
98918833
SY		 6667 struct i387_fxsave_struct *fxsave =
6668 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6669
d0752060
HB		 6670 memcpy(fpu->fpr, fxsave->st_space, 128);
6671 fpu->fcw = fxsave->cwd;
6672 fpu->fsw = fxsave->swd;
6673 fpu->ftwx = fxsave->twd;
6674 fpu->last_opcode = fxsave->fop;
6675 fpu->last_ip = fxsave->rip;
6676 fpu->last_dp = fxsave->rdp;
6677 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6678
d0752060
HB		 6679 return 0;
6680}
6681
6682int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6683{
98918833
SY		 6684 struct i387_fxsave_struct *fxsave =
6685 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6686
d0752060
HB		 6687 memcpy(fxsave->st_space, fpu->fpr, 128);
6688 fxsave->cwd = fpu->fcw;
6689 fxsave->swd = fpu->fsw;
6690 fxsave->twd = fpu->ftwx;
6691 fxsave->fop = fpu->last_opcode;
6692 fxsave->rip = fpu->last_ip;
6693 fxsave->rdp = fpu->last_dp;
6694 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6695
d0752060
HB		 6696 return 0;
6697}
6698
10ab25cd 6699int fx_init(struct kvm_vcpu *vcpu)
d0752060 6700{
10ab25cd
JK		 6701 int err;
6702
6703 err = fpu_alloc(&vcpu->arch.guest_fpu);
6704 if (err)
6705 return err;
6706
98918833 6707 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6708
2acf923e
DC		 6709 /*
6710 * Ensure guest xcr0 is valid for loading
6711 */
6712 vcpu->arch.xcr0 = XSTATE_FP;
6713
ad312c7c 6714 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6715
6716 return 0;
d0752060
HB		 6717}
6718EXPORT_SYMBOL_GPL(fx_init);
6719
98918833
SY		 6720static void fx_free(struct kvm_vcpu *vcpu)
6721{
6722 fpu_free(&vcpu->arch.guest_fpu);
6723}
6724
d0752060
HB		 6725void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6726{
2608d7a1 6727 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6728 return;
6729
2acf923e
DC		 6730 /*
6731 * Restore all possible states in the guest,
6732 * and assume host would use all available bits.
6733 * Guest xcr0 would be loaded later.
6734 */
6735 kvm_put_guest_xcr0(vcpu);
d0752060 6736 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6737 __kernel_fpu_begin();
98918833 6738 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6739 trace_kvm_fpu(1);
d0752060 6740}
d0752060
HB		 6741
6742void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6743{
2acf923e
DC		 6744 kvm_put_guest_xcr0(vcpu);
6745
d0752060
HB		 6746 if (!vcpu->guest_fpu_loaded)
6747 return;
6748
6749 vcpu->guest_fpu_loaded = 0;
98918833 6750 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6751 __kernel_fpu_end();
f096ed85 6752 ++vcpu->stat.fpu_reload;
a8eeb04a 6753 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6754 trace_kvm_fpu(0);
d0752060 6755}
e9b11c17
ZX		 6756
6757void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6758{
12f9a48f 6759 kvmclock_reset(vcpu);
7f1ea208 6760
f5f48ee1 6761 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6762 fx_free(vcpu);
e9b11c17
ZX		 6763 kvm_x86_ops->vcpu_free(vcpu);
6764}
6765
6766struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6767 unsigned int id)
6768{
6755bae8
ZA		 6769 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6770 printk_once(KERN_WARNING
6771 "kvm: SMP vm created on host with unstable TSC; "
6772 "guest TSC will not be reliable\n");
26e5215f
AK		 6773 return kvm_x86_ops->vcpu_create(kvm, id);
6774}
e9b11c17 6775
26e5215f
AK		 6776int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6777{
6778 int r;
e9b11c17 6779
0bed3b56 6780 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6781 r = vcpu_load(vcpu);
6782 if (r)
6783 return r;
57f252f2 6784 kvm_vcpu_reset(vcpu);
8a3c1a33 6785 kvm_mmu_setup(vcpu);
e9b11c17 6786 vcpu_put(vcpu);
e9b11c17 6787
26e5215f 6788 return r;
e9b11c17
ZX		 6789}
6790
42897d86
MT		 6791int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6792{
6793 int r;
8fe8ab46 6794 struct msr_data msr;
332967a3 6795 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6796
6797 r = vcpu_load(vcpu);
6798 if (r)
6799 return r;
8fe8ab46
WA		 6800 msr.data = 0x0;
6801 msr.index = MSR_IA32_TSC;
6802 msr.host_initiated = true;
6803 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6804 vcpu_put(vcpu);
6805
332967a3
AJ		 6806 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6807 KVMCLOCK_SYNC_PERIOD);
6808
42897d86
MT		 6809 return r;
6810}
6811
d40ccc62 6812void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6813{
9fc77441 6814 int r;
344d9588
GN		 6815 vcpu->arch.apf.msr_val = 0;
6816
9fc77441
MT		 6817 r = vcpu_load(vcpu);
6818 BUG_ON(r);
e9b11c17
ZX		 6819 kvm_mmu_unload(vcpu);
6820 vcpu_put(vcpu);
6821
98918833 6822 fx_free(vcpu);
e9b11c17
ZX		 6823 kvm_x86_ops->vcpu_free(vcpu);
6824}
6825
66450a21 6826void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6827{
7460fb4a
AK		 6828 atomic_set(&vcpu->arch.nmi_queued, 0);
6829 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6830 vcpu->arch.nmi_injected = false;
6831
42dbaa5a
JK		 6832 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6833 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6834 kvm_update_dr6(vcpu);
42dbaa5a 6835 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6836 kvm_update_dr7(vcpu);
42dbaa5a 6837
3842d135 6838 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6839 vcpu->arch.apf.msr_val = 0;
c9aaa895 6840 vcpu->arch.st.msr_val = 0;
3842d135 6841
12f9a48f
GC		 6842 kvmclock_reset(vcpu);
6843
af585b92
GN		 6844 kvm_clear_async_pf_completion_queue(vcpu);
6845 kvm_async_pf_hash_reset(vcpu);
6846 vcpu->arch.apf.halted = false;
3842d135 6847
f5132b01
GN		 6848 kvm_pmu_reset(vcpu);
6849
66f7b72e
JS		 6850 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6851 vcpu->arch.regs_avail = ~0;
6852 vcpu->arch.regs_dirty = ~0;
6853
57f252f2 6854 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6855}
6856
66450a21
JK		 6857void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6858{
6859 struct kvm_segment cs;
6860
6861 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6862 cs.selector = vector << 8;
6863 cs.base = vector << 12;
6864 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6865 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6866}
6867
10474ae8 6868int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6869{
ca84d1a2
ZA		 6870 struct kvm *kvm;
6871 struct kvm_vcpu *vcpu;
6872 int i;
0dd6a6ed
ZA		 6873 int ret;
6874 u64 local_tsc;
6875 u64 max_tsc = 0;
6876 bool stable, backwards_tsc = false;
18863bdd
AK		 6877
6878 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6879 ret = kvm_x86_ops->hardware_enable(garbage);
6880 if (ret != 0)
6881 return ret;
6882
6883 local_tsc = native_read_tsc();
6884 stable = !check_tsc_unstable();
6885 list_for_each_entry(kvm, &vm_list, vm_list) {
6886 kvm_for_each_vcpu(i, vcpu, kvm) {
6887 if (!stable && vcpu->cpu == smp_processor_id())
6888 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6889 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6890 backwards_tsc = true;
6891 if (vcpu->arch.last_host_tsc > max_tsc)
6892 max_tsc = vcpu->arch.last_host_tsc;
6893 }
6894 }
6895 }
6896
6897 /*
6898 * Sometimes, even reliable TSCs go backwards. This happens on
6899 * platforms that reset TSC during suspend or hibernate actions, but
6900 * maintain synchronization. We must compensate. Fortunately, we can
6901 * detect that condition here, which happens early in CPU bringup,
6902 * before any KVM threads can be running. Unfortunately, we can't
6903 * bring the TSCs fully up to date with real time, as we aren't yet far
6904 * enough into CPU bringup that we know how much real time has actually
6905 * elapsed; our helper function, get_kernel_ns() will be using boot
6906 * variables that haven't been updated yet.
6907 *
6908 * So we simply find the maximum observed TSC above, then record the
6909 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6910 * the adjustment will be applied. Note that we accumulate
6911 * adjustments, in case multiple suspend cycles happen before some VCPU
6912 * gets a chance to run again. In the event that no KVM threads get a
6913 * chance to run, we will miss the entire elapsed period, as we'll have
6914 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6915 * loose cycle time. This isn't too big a deal, since the loss will be
6916 * uniform across all VCPUs (not to mention the scenario is extremely
6917 * unlikely). It is possible that a second hibernate recovery happens
6918 * much faster than a first, causing the observed TSC here to be
6919 * smaller; this would require additional padding adjustment, which is
6920 * why we set last_host_tsc to the local tsc observed here.
6921 *
6922 * N.B. - this code below runs only on platforms with reliable TSC,
6923 * as that is the only way backwards_tsc is set above. Also note
6924 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6925 * have the same delta_cyc adjustment applied if backwards_tsc
6926 * is detected. Note further, this adjustment is only done once,
6927 * as we reset last_host_tsc on all VCPUs to stop this from being
6928 * called multiple times (one for each physical CPU bringup).
6929 *
4a969980 6930 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6931 * will be compensated by the logic in vcpu_load, which sets the TSC to
6932 * catchup mode. This will catchup all VCPUs to real time, but cannot
6933 * guarantee that they stay in perfect synchronization.
6934 */
6935 if (backwards_tsc) {
6936 u64 delta_cyc = max_tsc - local_tsc;
6937 list_for_each_entry(kvm, &vm_list, vm_list) {
6938 kvm_for_each_vcpu(i, vcpu, kvm) {
6939 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6940 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6941 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6942 &vcpu->requests);
0dd6a6ed
ZA		 6943 }
6944
6945 /*
6946 * We have to disable TSC offset matching.. if you were
6947 * booting a VM while issuing an S4 host suspend....
6948 * you may have some problem. Solving this issue is
6949 * left as an exercise to the reader.
6950 */
6951 kvm->arch.last_tsc_nsec = 0;
6952 kvm->arch.last_tsc_write = 0;
6953 }
6954
6955 }
6956 return 0;
e9b11c17
ZX		 6957}
6958
6959void kvm_arch_hardware_disable(void *garbage)
6960{
6961 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6962 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6963}
6964
6965int kvm_arch_hardware_setup(void)
6966{
6967 return kvm_x86_ops->hardware_setup();
6968}
6969
6970void kvm_arch_hardware_unsetup(void)
6971{
6972 kvm_x86_ops->hardware_unsetup();
6973}
6974
6975void kvm_arch_check_processor_compat(void *rtn)
6976{
6977 kvm_x86_ops->check_processor_compatibility(rtn);
6978}
6979
3e515705
AK		 6980bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6981{
6982 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6983}
6984
54e9818f
GN		 6985struct static_key kvm_no_apic_vcpu __read_mostly;
6986
e9b11c17
ZX		 6987int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6988{
6989 struct page *page;
6990 struct kvm *kvm;
6991 int r;
6992
6993 BUG_ON(vcpu->kvm == NULL);
6994 kvm = vcpu->kvm;
6995
6aef266c 6996 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6997 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6998 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7000 else
a4535290 7001 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7002
7003 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7004 if (!page) {
7005 r = -ENOMEM;
7006 goto fail;
7007 }
ad312c7c 7008 vcpu->arch.pio_data = page_address(page);
e9b11c17 7009
cc578287 7010 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7011
e9b11c17
ZX		 7012 r = kvm_mmu_create(vcpu);
7013 if (r < 0)
7014 goto fail_free_pio_data;
7015
7016 if (irqchip_in_kernel(kvm)) {
7017 r = kvm_create_lapic(vcpu);
7018 if (r < 0)
7019 goto fail_mmu_destroy;
54e9818f
GN		 7020 } else
7021 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7022
890ca9ae
HY		 7023 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7024 GFP_KERNEL);
7025 if (!vcpu->arch.mce_banks) {
7026 r = -ENOMEM;
443c39bc 7027 goto fail_free_lapic;
890ca9ae
HY		 7028 }
7029 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7030
f1797359
WY		 7031 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7032 r = -ENOMEM;
f5f48ee1 7033 goto fail_free_mce_banks;
f1797359 7034 }
f5f48ee1 7035
66f7b72e
JS		 7036 r = fx_init(vcpu);
7037 if (r)
7038 goto fail_free_wbinvd_dirty_mask;
7039
ba904635 7040 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7041 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7042
7043 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7044 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7045
af585b92 7046 kvm_async_pf_hash_reset(vcpu);
f5132b01 7047 kvm_pmu_init(vcpu);
af585b92 7048
e9b11c17 7049 return 0;
66f7b72e
JS		 7050fail_free_wbinvd_dirty_mask:
7051 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7052fail_free_mce_banks:
7053 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7054fail_free_lapic:
7055 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7056fail_mmu_destroy:
7057 kvm_mmu_destroy(vcpu);
7058fail_free_pio_data:
ad312c7c 7059 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7060fail:
7061 return r;
7062}
7063
7064void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7065{
f656ce01
MT		 7066 int idx;
7067
f5132b01 7068 kvm_pmu_destroy(vcpu);
36cb93fd 7069 kfree(vcpu->arch.mce_banks);
e9b11c17 7070 kvm_free_lapic(vcpu);
f656ce01 7071 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7072 kvm_mmu_destroy(vcpu);
f656ce01 7073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7074 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7075 if (!irqchip_in_kernel(vcpu->kvm))
7076 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7077}
d19a9cd2 7078
e08b9637 7079int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7080{
e08b9637
CO		 7081 if (type)
7082 return -EINVAL;
7083
f05e70ac 7084 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7085 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7086 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7087 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7088
5550af4d
SY		 7089 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7090 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7091 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7092 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7093 &kvm->arch.irq_sources_bitmap);
5550af4d 7094
038f8c11 7095 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7096 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7097 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7098
7099 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7100
7e44e449 7101 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7102 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7103
d89f5eff 7104 return 0;
d19a9cd2
ZX		 7105}
7106
7107static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7108{
9fc77441
MT		 7109 int r;
7110 r = vcpu_load(vcpu);
7111 BUG_ON(r);
d19a9cd2
ZX		 7112 kvm_mmu_unload(vcpu);
7113 vcpu_put(vcpu);
7114}
7115
7116static void kvm_free_vcpus(struct kvm *kvm)
7117{
7118 unsigned int i;
988a2cae 7119 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7120
7121 /*
7122 * Unpin any mmu pages first.
7123 */
af585b92
GN		 7124 kvm_for_each_vcpu(i, vcpu, kvm) {
7125 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7126 kvm_unload_vcpu_mmu(vcpu);
af585b92 7127 }
988a2cae
GN		 7128 kvm_for_each_vcpu(i, vcpu, kvm)
7129 kvm_arch_vcpu_free(vcpu);
7130
7131 mutex_lock(&kvm->lock);
7132 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7133 kvm->vcpus[i] = NULL;
d19a9cd2 7134
988a2cae
GN		 7135 atomic_set(&kvm->online_vcpus, 0);
7136 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7137}
7138
ad8ba2cd
SY		 7139void kvm_arch_sync_events(struct kvm *kvm)
7140{
332967a3 7141 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7142 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7143 kvm_free_all_assigned_devices(kvm);
aea924f6 7144 kvm_free_pit(kvm);
ad8ba2cd
SY		 7145}
7146
d19a9cd2
ZX		 7147void kvm_arch_destroy_vm(struct kvm *kvm)
7148{
27469d29
AH		 7149 if (current->mm == kvm->mm) {
7150 /*
7151 * Free memory regions allocated on behalf of userspace,
7152 * unless the the memory map has changed due to process exit
7153 * or fd copying.
7154 */
7155 struct kvm_userspace_memory_region mem;
7156 memset(&mem, 0, sizeof(mem));
7157 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7158 kvm_set_memory_region(kvm, &mem);
7159
7160 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7161 kvm_set_memory_region(kvm, &mem);
7162
7163 mem.slot = TSS_PRIVATE_MEMSLOT;
7164 kvm_set_memory_region(kvm, &mem);
7165 }
6eb55818 7166 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7167 kfree(kvm->arch.vpic);
7168 kfree(kvm->arch.vioapic);
d19a9cd2 7169 kvm_free_vcpus(kvm);
3d45830c
AK		 7170 if (kvm->arch.apic_access_page)
7171 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7172 if (kvm->arch.ept_identity_pagetable)
7173 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7174 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7175}
0de10343 7176
5587027c 7177void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7178 struct kvm_memory_slot *dont)
7179{
7180 int i;
7181
d89cc617
TY		 7182 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7183 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7184 kvm_kvfree(free->arch.rmap[i]);
7185 free->arch.rmap[i] = NULL;
77d11309 7186 }
d89cc617
TY		 7187 if (i == 0)
7188 continue;
7189
7190 if (!dont || free->arch.lpage_info[i - 1] !=
7191 dont->arch.lpage_info[i - 1]) {
7192 kvm_kvfree(free->arch.lpage_info[i - 1]);
7193 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7194 }
7195 }
7196}
7197
5587027c
AK		 7198int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7199 unsigned long npages)
db3fe4eb
TY		 7200{
7201 int i;
7202
d89cc617 7203 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7204 unsigned long ugfn;
7205 int lpages;
d89cc617 7206 int level = i + 1;
db3fe4eb
TY		 7207
7208 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7209 slot->base_gfn, level) + 1;
7210
d89cc617
TY		 7211 slot->arch.rmap[i] =
7212 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7213 if (!slot->arch.rmap[i])
77d11309 7214 goto out_free;
d89cc617
TY		 7215 if (i == 0)
7216 continue;
77d11309 7217
d89cc617
TY		 7218 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7219 sizeof(*slot->arch.lpage_info[i - 1]));
7220 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7221 goto out_free;
7222
7223 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7224 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7225 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7226 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7227 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7228 /*
7229 * If the gfn and userspace address are not aligned wrt each
7230 * other, or if explicitly asked to, disable large page
7231 * support for this slot
7232 */
7233 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7234 !kvm_largepages_enabled()) {
7235 unsigned long j;
7236
7237 for (j = 0; j < lpages; ++j)
d89cc617 7238 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7239 }
7240 }
7241
7242 return 0;
7243
7244out_free:
d89cc617
TY		 7245 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7246 kvm_kvfree(slot->arch.rmap[i]);
7247 slot->arch.rmap[i] = NULL;
7248 if (i == 0)
7249 continue;
7250
7251 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7252 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7253 }
7254 return -ENOMEM;
7255}
7256
e59dbe09
TY		 7257void kvm_arch_memslots_updated(struct kvm *kvm)
7258{
e6dff7d1
TY		 7259 /*
7260 * memslots->generation has been incremented.
7261 * mmio generation may have reached its maximum value.
7262 */
7263 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7264}
7265
f7784b8e
MT		 7266int kvm_arch_prepare_memory_region(struct kvm *kvm,
7267 struct kvm_memory_slot *memslot,
f7784b8e 7268 struct kvm_userspace_memory_region *mem,
7b6195a9 7269 enum kvm_mr_change change)
0de10343 7270{
7a905b14
TY		 7271 /*
7272 * Only private memory slots need to be mapped here since
7273 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7274 */
7b6195a9 7275 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7276 unsigned long userspace_addr;
604b38ac 7277
7a905b14
TY		 7278 /*
7279 * MAP_SHARED to prevent internal slot pages from being moved
7280 * by fork()/COW.
7281 */
7b6195a9 7282 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7283 PROT_READ | PROT_WRITE,
7284 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7285
7a905b14
TY		 7286 if (IS_ERR((void *)userspace_addr))
7287 return PTR_ERR((void *)userspace_addr);
604b38ac 7288
7a905b14 7289 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7290 }
7291
f7784b8e
MT		 7292 return 0;
7293}
7294
7295void kvm_arch_commit_memory_region(struct kvm *kvm,
7296 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7297 const struct kvm_memory_slot *old,
7298 enum kvm_mr_change change)
f7784b8e
MT		 7299{
7300
8482644a 7301 int nr_mmu_pages = 0;
f7784b8e 7302
8482644a 7303 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7304 int ret;
7305
8482644a
TY		 7306 ret = vm_munmap(old->userspace_addr,
7307 old->npages * PAGE_SIZE);
f7784b8e
MT		 7308 if (ret < 0)
7309 printk(KERN_WARNING
7310 "kvm_vm_ioctl_set_memory_region: "
7311 "failed to munmap memory\n");
7312 }
7313
48c0e4e9
XG		 7314 if (!kvm->arch.n_requested_mmu_pages)
7315 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7316
48c0e4e9 7317 if (nr_mmu_pages)
0de10343 7318 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7319 /*
7320 * Write protect all pages for dirty logging.
7321 * Existing largepage mappings are destroyed here and new ones will
7322 * not be created until the end of the logging.
7323 */
8482644a 7324 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7325 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7326}
1d737c8a 7327
2df72e9b 7328void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7329{
6ca18b69 7330 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7331}
7332
2df72e9b
MT		 7333void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7334 struct kvm_memory_slot *slot)
7335{
6ca18b69 7336 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7337}
7338
1d737c8a
ZX		 7339int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7340{
b6b8a145
JK		 7341 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7342 kvm_x86_ops->check_nested_events(vcpu, false);
7343
af585b92
GN		 7344 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7345 !vcpu->arch.apf.halted)
7346 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7347 || kvm_apic_has_events(vcpu)
6aef266c 7348 || vcpu->arch.pv.pv_unhalted
7460fb4a 7349 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7350 (kvm_arch_interrupt_allowed(vcpu) &&
7351 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7352}
5736199a 7353
b6d33834 7354int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7355{
b6d33834 7356 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7357}
78646121
GN		 7358
7359int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7360{
7361 return kvm_x86_ops->interrupt_allowed(vcpu);
7362}
229456fc 7363
f92653ee
JK		 7364bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7365{
7366 unsigned long current_rip = kvm_rip_read(vcpu) +
7367 get_segment_base(vcpu, VCPU_SREG_CS);
7368
7369 return current_rip == linear_rip;
7370}
7371EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7372
94fe45da
JK		 7373unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7374{
7375 unsigned long rflags;
7376
7377 rflags = kvm_x86_ops->get_rflags(vcpu);
7378 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7379 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7380 return rflags;
7381}
7382EXPORT_SYMBOL_GPL(kvm_get_rflags);
7383
7384void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7385{
7386 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7387 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7388 rflags |= X86_EFLAGS_TF;
94fe45da 7389 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7390 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7391}
7392EXPORT_SYMBOL_GPL(kvm_set_rflags);
7393
56028d08
GN		 7394void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7395{
7396 int r;
7397
fb67e14f 7398 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7399 work->wakeup_all)
56028d08
GN		 7400 return;
7401
7402 r = kvm_mmu_reload(vcpu);
7403 if (unlikely(r))
7404 return;
7405
fb67e14f
XG		 7406 if (!vcpu->arch.mmu.direct_map &&
7407 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7408 return;
7409
56028d08
GN		 7410 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7411}
7412
af585b92
GN		 7413static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7414{
7415 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7416}
7417
7418static inline u32 kvm_async_pf_next_probe(u32 key)
7419{
7420 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7421}
7422
7423static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7424{
7425 u32 key = kvm_async_pf_hash_fn(gfn);
7426
7427 while (vcpu->arch.apf.gfns[key] != ~0)
7428 key = kvm_async_pf_next_probe(key);
7429
7430 vcpu->arch.apf.gfns[key] = gfn;
7431}
7432
7433static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7434{
7435 int i;
7436 u32 key = kvm_async_pf_hash_fn(gfn);
7437
7438 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7439 (vcpu->arch.apf.gfns[key] != gfn &&
7440 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7441 key = kvm_async_pf_next_probe(key);
7442
7443 return key;
7444}
7445
7446bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7447{
7448 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7449}
7450
7451static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7452{
7453 u32 i, j, k;
7454
7455 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7456 while (true) {
7457 vcpu->arch.apf.gfns[i] = ~0;
7458 do {
7459 j = kvm_async_pf_next_probe(j);
7460 if (vcpu->arch.apf.gfns[j] == ~0)
7461 return;
7462 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7463 /*
7464 * k lies cyclically in ]i,j]
7465 * | i.k.j |
7466 * |....j i.k.| or |.k..j i...|
7467 */
7468 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7469 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7470 i = j;
7471 }
7472}
7473
7c90705b
GN		 7474static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7475{
7476
7477 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7478 sizeof(val));
7479}
7480
af585b92
GN		 7481void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7482 struct kvm_async_pf *work)
7483{
6389ee94
AK		 7484 struct x86_exception fault;
7485
7c90705b 7486 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7487 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7488
7489 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7490 (vcpu->arch.apf.send_user_only &&
7491 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7492 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7493 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7494 fault.vector = PF_VECTOR;
7495 fault.error_code_valid = true;
7496 fault.error_code = 0;
7497 fault.nested_page_fault = false;
7498 fault.address = work->arch.token;
7499 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7500 }
af585b92
GN		 7501}
7502
7503void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7504 struct kvm_async_pf *work)
7505{
6389ee94
AK		 7506 struct x86_exception fault;
7507
7c90705b 7508 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7509 if (work->wakeup_all)
7c90705b
GN		 7510 work->arch.token = ~0; /* broadcast wakeup */
7511 else
7512 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7513
7514 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7515 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7516 fault.vector = PF_VECTOR;
7517 fault.error_code_valid = true;
7518 fault.error_code = 0;
7519 fault.nested_page_fault = false;
7520 fault.address = work->arch.token;
7521 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7522 }
e6d53e3b 7523 vcpu->arch.apf.halted = false;
a4fa1635 7524 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7525}
7526
7527bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7528{
7529 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7530 return true;
7531 else
7532 return !kvm_event_needs_reinjection(vcpu) &&
7533 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7534}
7535
e0f0bbc5
AW		 7536void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7537{
7538 atomic_inc(&kvm->arch.noncoherent_dma_count);
7539}
7540EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7541
7542void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7543{
7544 atomic_dec(&kvm->arch.noncoherent_dma_count);
7545}
7546EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7547
7548bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7549{
7550 return atomic_read(&kvm->arch.noncoherent_dma_count);
7551}
7552EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7553
229456fc
MT		 7554EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7555EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7556EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7557EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7558EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7559EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7560EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7561EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7562EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7563EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7564EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7565EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7566EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git