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KVM: x86: Sync DR7 on KVM_SET_DEBUGREGS
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261{
262 /* TODO: reserve bits check */
8a5a87d9 263 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 264}
265EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
e3ba45b8
GL		 267asmlinkage void kvm_spurious_fault(void)
268{
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271}
272EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
3fd28fce
ED		 274#define EXCPT_BENIGN 0
275#define EXCPT_CONTRIBUTORY 1
276#define EXCPT_PF 2
277
278static int exception_class(int vector)
279{
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293}
294
295static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
3fd28fce
ED		 298{
299 u32 prev_nr;
300 int class1, class2;
301
3842d135
AK		 302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
3fd28fce
ED		 304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
3f0fd292 310 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
a8eeb04a 318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335}
336
298101da
AK		 337void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338{
ce7ddec4 339 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 340}
341EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
ce7ddec4
JR		 343void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344{
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346}
347EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
db8fcefa 349void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 350{
db8fcefa
AP		 351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355}
356EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 357
6389ee94 358void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 359{
360 ++vcpu->stat.pf_guest;
6389ee94
AK		 361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 363}
27d6c865 364EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 365
6389ee94 366void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 367{
6389ee94
AK		 368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 370 else
6389ee94 371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 372}
373
3419ffc8
SY		 374void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375{
7460fb4a
AK		 376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 378}
379EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
298101da
AK		 381void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382{
ce7ddec4 383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 384}
385EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
ce7ddec4
JR		 387void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388{
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390}
391EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
0a79b009
AK		 393/*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 398{
0a79b009
AK		 399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
298101da 403}
0a79b009 404EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 405
ec92fe44
JR		 406/*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414{
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426}
427EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
3d06b8bf
JR		 429int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431{
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434}
435
a03490ed
CO		 436/*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
ff03a073 439int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 440{
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
ff03a073 445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 446
ff03a073
JR		 447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 455 if (is_present_gpte(pdpte[i]) &&
20c466b5 456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
ff03a073 463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 468out:
a03490ed
CO		 469
470 return ret;
471}
cc4b6871 472EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 473
d835dfec
AK		 474static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475{
ff03a073 476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 477 bool changed = true;
3d06b8bf
JR		 478 int offset;
479 gfn_t gfn;
d835dfec
AK		 480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
6de4f3ad
AK		 485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
9f8fe504
AK		 489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 493 if (r < 0)
494 goto out;
ff03a073 495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 496out:
d835dfec
AK		 497
498 return changed;
499}
500
49a9b07e 501int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 502{
aad82703
SY		 503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
f9a48e6a
AK		 507 cr0 |= X86_CR0_ET;
508
ab344828 509#ifdef CONFIG_X86_64
0f12244f
GN		 510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
ab344828
GN		 512#endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
a03490ed 518
0f12244f
GN		 519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
a03490ed
CO		 521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523#ifdef CONFIG_X86_64
f6801dff 524 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 525 int cs_db, cs_l;
526
0f12244f
GN		 527 if (!is_pae(vcpu))
528 return 1;
a03490ed 529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 530 if (cs_l)
531 return 1;
a03490ed
CO		 532 } else
533#endif
ff03a073 534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 535 kvm_read_cr3(vcpu)))
0f12244f 536 return 1;
a03490ed
CO		 537 }
538
ad756a16
MJ		 539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
a03490ed 542 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 543
d170c419 544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 545 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 546 kvm_async_pf_hash_reset(vcpu);
547 }
e5f3f027 548
aad82703
SY		 549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 551 return 0;
552}
2d3ad1f4 553EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 554
2d3ad1f4 555void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 556{
49a9b07e 557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 558}
2d3ad1f4 559EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 560
42bdf991
MT		 561static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562{
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569}
570
571static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572{
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578}
579
2acf923e
DC		 580int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581{
582 u64 xcr0;
46c34cb0 583 u64 valid_bits;
2acf923e
DC		 584
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
587 return 1;
588 xcr0 = xcr;
2acf923e
DC		 589 if (!(xcr0 & XSTATE_FP))
590 return 1;
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592 return 1;
46c34cb0
PB		 593
594 /*
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
598 */
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
2acf923e 601 return 1;
46c34cb0 602
42bdf991 603 kvm_put_guest_xcr0(vcpu);
2acf923e 604 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 605 return 0;
606}
607
608int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609{
764bcbc5
Z		 610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 612 kvm_inject_gp(vcpu, 0);
613 return 1;
614 }
615 return 0;
616}
617EXPORT_SYMBOL_GPL(kvm_set_xcr);
618
a83b29c6 619int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 620{
fc78f519 621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 624 if (cr4 & CR4_RESERVED_BITS)
625 return 1;
a03490ed 626
2acf923e
DC		 627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628 return 1;
629
c68b734f
YW		 630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631 return 1;
632
afcbf13f 633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 634 return 1;
635
a03490ed 636 if (is_long_mode(vcpu)) {
0f12244f
GN		 637 if (!(cr4 & X86_CR4_PAE))
638 return 1;
a2edf57f
AK		 639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
0f12244f
GN		 643 return 1;
644
ad756a16
MJ		 645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
647 return 1;
648
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651 return 1;
652 }
653
5e1746d6 654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 655 return 1;
a03490ed 656
ad756a16
MJ		 657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 659 kvm_mmu_reset_context(vcpu);
0f12244f 660
2acf923e 661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 662 kvm_update_cpuid(vcpu);
2acf923e 663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 667
2390218b 668int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 669{
9f8fe504 670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 671 kvm_mmu_sync_roots(vcpu);
d835dfec 672 kvm_mmu_flush_tlb(vcpu);
0f12244f 673 return 0;
d835dfec
AK		 674 }
675
a03490ed 676 if (is_long_mode(vcpu)) {
471842ec 677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679 return 1;
680 } else
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 return 1;
a03490ed
CO		 683 } else {
684 if (is_pae(vcpu)) {
0f12244f
GN		 685 if (cr3 & CR3_PAE_RESERVED_BITS)
686 return 1;
ff03a073
JR		 687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691 /*
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
694 */
695 }
696
0f12244f 697 vcpu->arch.cr3 = cr3;
aff48baa 698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 699 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 703
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 705{
0f12244f
GN		 706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
a03490ed
CO		 708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
ad312c7c 711 vcpu->arch.cr8 = cr8;
0f12244f
GN		 712 return 0;
713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 715
2d3ad1f4 716unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 717{
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
ad312c7c 721 return vcpu->arch.cr8;
a03490ed 722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 724
c8639010
JK		 725static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726{
727 unsigned long dr7;
728
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
731 else
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735}
736
338dbc97 737static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 738{
739 switch (dr) {
740 case 0 ... 3:
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
744 break;
745 case 4:
338dbc97
GN		 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
020df079
GN		 748 /* fall through */
749 case 6:
338dbc97
GN		 750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
020df079
GN		 752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753 break;
754 case 5:
338dbc97
GN		 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756 return 1; /* #UD */
020df079
GN		 757 /* fall through */
758 default: /* 7 */
338dbc97
GN		 759 if (val & 0xffffffff00000000ULL)
760 return -1; /* #GP */
020df079 761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 762 kvm_update_dr7(vcpu);
020df079
GN		 763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770{
771 int res;
772
773 res = __kvm_set_dr(vcpu, dr, val);
774 if (res > 0)
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 else if (res < 0)
777 kvm_inject_gp(vcpu, 0);
778
779 return res;
780}
020df079
GN		 781EXPORT_SYMBOL_GPL(kvm_set_dr);
782
338dbc97 783static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 784{
785 switch (dr) {
786 case 0 ... 3:
787 *val = vcpu->arch.db[dr];
788 break;
789 case 4:
338dbc97 790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 791 return 1;
020df079
GN		 792 /* fall through */
793 case 6:
794 *val = vcpu->arch.dr6;
795 break;
796 case 5:
338dbc97 797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 798 return 1;
020df079
GN		 799 /* fall through */
800 default: /* 7 */
801 *val = vcpu->arch.dr7;
802 break;
803 }
804
805 return 0;
806}
338dbc97
GN		 807
808int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809{
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
812 return 1;
813 }
814 return 0;
815}
020df079
GN		 816EXPORT_SYMBOL_GPL(kvm_get_dr);
817
022cd0e8
AK		 818bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819{
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821 u64 data;
822 int err;
823
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825 if (err)
826 return err;
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829 return err;
830}
831EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
043405e1
CO		 833/*
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 *
837 * This list is modified at module load time to reflect the
e3267cbb
GC		 838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
043405e1 840 */
e3267cbb 841
e984097b 842#define KVM_SAVE_MSRS_BEGIN 12
043405e1 843static u32 msrs_to_save[] = {
e3267cbb 844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 847 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 848 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 849 MSR_KVM_PV_EOI_EN,
043405e1 850 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 851 MSR_STAR,
043405e1
CO		 852#ifdef CONFIG_X86_64
853 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
854#endif
b3897a49
NHE		 855 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
856 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 857};
858
859static unsigned num_msrs_to_save;
860
f1d24831 861static const u32 emulated_msrs[] = {
ba904635 862 MSR_IA32_TSC_ADJUST,
a3e06bbe 863 MSR_IA32_TSCDEADLINE,
043405e1 864 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 865 MSR_IA32_MCG_STATUS,
866 MSR_IA32_MCG_CTL,
043405e1
CO		 867};
868
384bb783 869bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 870{
b69e8cae 871 if (efer & efer_reserved_bits)
384bb783 872 return false;
15c4a640 873
1b2fd70c
AG		 874 if (efer & EFER_FFXSR) {
875 struct kvm_cpuid_entry2 *feat;
876
877 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 878 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 879 return false;
1b2fd70c
AG		 880 }
881
d8017474
AG		 882 if (efer & EFER_SVME) {
883 struct kvm_cpuid_entry2 *feat;
884
885 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 886 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 887 return false;
d8017474
AG		 888 }
889
384bb783
JK		 890 return true;
891}
892EXPORT_SYMBOL_GPL(kvm_valid_efer);
893
894static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
895{
896 u64 old_efer = vcpu->arch.efer;
897
898 if (!kvm_valid_efer(vcpu, efer))
899 return 1;
900
901 if (is_paging(vcpu)
902 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
903 return 1;
904
15c4a640 905 efer &= ~EFER_LMA;
f6801dff 906 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 907
a3d204e2
SY		 908 kvm_x86_ops->set_efer(vcpu, efer);
909
aad82703
SY		 910 /* Update reserved bits */
911 if ((efer ^ old_efer) & EFER_NX)
912 kvm_mmu_reset_context(vcpu);
913
b69e8cae 914 return 0;
15c4a640
CO		 915}
916
f2b4b7dd
JR		 917void kvm_enable_efer_bits(u64 mask)
918{
919 efer_reserved_bits &= ~mask;
920}
921EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
922
923
15c4a640
CO		 924/*
925 * Writes msr value into into the appropriate "register".
926 * Returns 0 on success, non-0 otherwise.
927 * Assumes vcpu_load() was already called.
928 */
8fe8ab46 929int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 930{
8fe8ab46 931 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 932}
933
313a3dc7
CO		 934/*
935 * Adapt set_msr() to msr_io()'s calling convention
936 */
937static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
938{
8fe8ab46
WA		 939 struct msr_data msr;
940
941 msr.data = *data;
942 msr.index = index;
943 msr.host_initiated = true;
944 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 945}
946
16e8d74d
MT		 947#ifdef CONFIG_X86_64
948struct pvclock_gtod_data {
949 seqcount_t seq;
950
951 struct { /* extract of a clocksource struct */
952 int vclock_mode;
953 cycle_t cycle_last;
954 cycle_t mask;
955 u32 mult;
956 u32 shift;
957 } clock;
958
959 /* open coded 'struct timespec' */
960 u64 monotonic_time_snsec;
961 time_t monotonic_time_sec;
962};
963
964static struct pvclock_gtod_data pvclock_gtod_data;
965
966static void update_pvclock_gtod(struct timekeeper *tk)
967{
968 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
969
970 write_seqcount_begin(&vdata->seq);
971
972 /* copy pvclock gtod data */
973 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
974 vdata->clock.cycle_last = tk->clock->cycle_last;
975 vdata->clock.mask = tk->clock->mask;
976 vdata->clock.mult = tk->mult;
977 vdata->clock.shift = tk->shift;
978
979 vdata->monotonic_time_sec = tk->xtime_sec
980 + tk->wall_to_monotonic.tv_sec;
981 vdata->monotonic_time_snsec = tk->xtime_nsec
982 + (tk->wall_to_monotonic.tv_nsec
983 << tk->shift);
984 while (vdata->monotonic_time_snsec >=
985 (((u64)NSEC_PER_SEC) << tk->shift)) {
986 vdata->monotonic_time_snsec -=
987 ((u64)NSEC_PER_SEC) << tk->shift;
988 vdata->monotonic_time_sec++;
989 }
990
991 write_seqcount_end(&vdata->seq);
992}
993#endif
994
995
18068523
GOC		 996static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
997{
9ed3c444
AK		 998 int version;
999 int r;
50d0a0f9 1000 struct pvclock_wall_clock wc;
923de3cf 1001 struct timespec boot;
18068523
GOC		 1002
1003 if (!wall_clock)
1004 return;
1005
9ed3c444
AK		 1006 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1007 if (r)
1008 return;
1009
1010 if (version & 1)
1011 ++version; /* first time write, random junk */
1012
1013 ++version;
18068523 1014
18068523
GOC		 1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1016
50d0a0f9
GH		 1017 /*
1018 * The guest calculates current wall clock time by adding
34c238a1 1019 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1020 * wall clock specified here. guest system time equals host
1021 * system time for us, thus we must fill in host boot time here.
1022 */
923de3cf 1023 getboottime(&boot);
50d0a0f9 1024
4b648665
BR		 1025 if (kvm->arch.kvmclock_offset) {
1026 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1027 boot = timespec_sub(boot, ts);
1028 }
50d0a0f9
GH		 1029 wc.sec = boot.tv_sec;
1030 wc.nsec = boot.tv_nsec;
1031 wc.version = version;
18068523
GOC		 1032
1033 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1034
1035 version++;
1036 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1037}
1038
50d0a0f9
GH		 1039static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1040{
1041 uint32_t quotient, remainder;
1042
1043 /* Don't try to replace with do_div(), this one calculates
1044 * "(dividend << 32) / divisor" */
1045 __asm__ ( "divl %4"
1046 : "=a" (quotient), "=d" (remainder)
1047 : "0" (0), "1" (dividend), "r" (divisor) );
1048 return quotient;
1049}
1050
5f4e3f88
ZA		 1051static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1052 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1053{
5f4e3f88 1054 uint64_t scaled64;
50d0a0f9
GH		 1055 int32_t shift = 0;
1056 uint64_t tps64;
1057 uint32_t tps32;
1058
5f4e3f88
ZA		 1059 tps64 = base_khz * 1000LL;
1060 scaled64 = scaled_khz * 1000LL;
50933623 1061 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1062 tps64 >>= 1;
1063 shift--;
1064 }
1065
1066 tps32 = (uint32_t)tps64;
50933623
JK		 1067 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1068 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1069 scaled64 >>= 1;
1070 else
1071 tps32 <<= 1;
50d0a0f9
GH		 1072 shift++;
1073 }
1074
5f4e3f88
ZA		 1075 *pshift = shift;
1076 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1077
5f4e3f88
ZA		 1078 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1079 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1080}
1081
759379dd
ZA		 1082static inline u64 get_kernel_ns(void)
1083{
1084 struct timespec ts;
1085
1086 WARN_ON(preemptible());
1087 ktime_get_ts(&ts);
1088 monotonic_to_bootbased(&ts);
1089 return timespec_to_ns(&ts);
50d0a0f9
GH		 1090}
1091
d828199e 1092#ifdef CONFIG_X86_64
16e8d74d 1093static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1094#endif
16e8d74d 1095
c8076604 1096static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1097unsigned long max_tsc_khz;
c8076604 1098
cc578287 1099static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1100{
cc578287
ZA		 1101 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1102 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1103}
1104
cc578287 1105static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1106{
cc578287
ZA		 1107 u64 v = (u64)khz * (1000000 + ppm);
1108 do_div(v, 1000000);
1109 return v;
1e993611
JR		 1110}
1111
cc578287 1112static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1113{
cc578287
ZA		 1114 u32 thresh_lo, thresh_hi;
1115 int use_scaling = 0;
217fc9cf 1116
03ba32ca
MT		 1117 /* tsc_khz can be zero if TSC calibration fails */
1118 if (this_tsc_khz == 0)
1119 return;
1120
c285545f
ZA		 1121 /* Compute a scale to convert nanoseconds in TSC cycles */
1122 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1123 &vcpu->arch.virtual_tsc_shift,
1124 &vcpu->arch.virtual_tsc_mult);
1125 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1126
1127 /*
1128 * Compute the variation in TSC rate which is acceptable
1129 * within the range of tolerance and decide if the
1130 * rate being applied is within that bounds of the hardware
1131 * rate. If so, no scaling or compensation need be done.
1132 */
1133 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1134 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1135 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1136 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1137 use_scaling = 1;
1138 }
1139 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1140}
1141
1142static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1143{
e26101b1 1144 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1145 vcpu->arch.virtual_tsc_mult,
1146 vcpu->arch.virtual_tsc_shift);
e26101b1 1147 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1148 return tsc;
1149}
1150
b48aa97e
MT		 1151void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1152{
1153#ifdef CONFIG_X86_64
1154 bool vcpus_matched;
1155 bool do_request = false;
1156 struct kvm_arch *ka = &vcpu->kvm->arch;
1157 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1158
1159 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1160 atomic_read(&vcpu->kvm->online_vcpus));
1161
1162 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1163 if (!ka->use_master_clock)
1164 do_request = 1;
1165
1166 if (!vcpus_matched && ka->use_master_clock)
1167 do_request = 1;
1168
1169 if (do_request)
1170 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1171
1172 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1173 atomic_read(&vcpu->kvm->online_vcpus),
1174 ka->use_master_clock, gtod->clock.vclock_mode);
1175#endif
1176}
1177
ba904635
WA		 1178static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1179{
1180 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1181 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1182}
1183
8fe8ab46 1184void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1185{
1186 struct kvm *kvm = vcpu->kvm;
f38e098f 1187 u64 offset, ns, elapsed;
99e3e30a 1188 unsigned long flags;
02626b6a 1189 s64 usdiff;
b48aa97e 1190 bool matched;
8fe8ab46 1191 u64 data = msr->data;
99e3e30a 1192
038f8c11 1193 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1194 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1195 ns = get_kernel_ns();
f38e098f 1196 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1197
03ba32ca 1198 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1199 int faulted = 0;
1200
03ba32ca
MT		 1201 /* n.b - signed multiplication and division required */
1202 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1203#ifdef CONFIG_X86_64
03ba32ca 1204 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1205#else
03ba32ca 1206 /* do_div() only does unsigned */
8915aa27
MT		 1207 asm("1: idivl %[divisor]\n"
1208 "2: xor %%edx, %%edx\n"
1209 " movl $0, %[faulted]\n"
1210 "3:\n"
1211 ".section .fixup,\"ax\"\n"
1212 "4: movl $1, %[faulted]\n"
1213 " jmp 3b\n"
1214 ".previous\n"
1215
1216 _ASM_EXTABLE(1b, 4b)
1217
1218 : "=A"(usdiff), [faulted] "=r" (faulted)
1219 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1220
5d3cb0f6 1221#endif
03ba32ca
MT		 1222 do_div(elapsed, 1000);
1223 usdiff -= elapsed;
1224 if (usdiff < 0)
1225 usdiff = -usdiff;
8915aa27
MT		 1226
1227 /* idivl overflow => difference is larger than USEC_PER_SEC */
1228 if (faulted)
1229 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1230 } else
1231 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1232
1233 /*
5d3cb0f6
ZA		 1234 * Special case: TSC write with a small delta (1 second) of virtual
1235 * cycle time against real time is interpreted as an attempt to
1236 * synchronize the CPU.
1237 *
1238 * For a reliable TSC, we can match TSC offsets, and for an unstable
1239 * TSC, we add elapsed time in this computation. We could let the
1240 * compensation code attempt to catch up if we fall behind, but
1241 * it's better to try to match offsets from the beginning.
1242 */
02626b6a 1243 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1244 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1245 if (!check_tsc_unstable()) {
e26101b1 1246 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1247 pr_debug("kvm: matched tsc offset for %llu\n", data);
1248 } else {
857e4099 1249 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1250 data += delta;
1251 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1252 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1253 }
b48aa97e 1254 matched = true;
e26101b1
ZA		 1255 } else {
1256 /*
1257 * We split periods of matched TSC writes into generations.
1258 * For each generation, we track the original measured
1259 * nanosecond time, offset, and write, so if TSCs are in
1260 * sync, we can match exact offset, and if not, we can match
4a969980 1261 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1262 *
1263 * These values are tracked in kvm->arch.cur_xxx variables.
1264 */
1265 kvm->arch.cur_tsc_generation++;
1266 kvm->arch.cur_tsc_nsec = ns;
1267 kvm->arch.cur_tsc_write = data;
1268 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1269 matched = false;
e26101b1
ZA		 1270 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1271 kvm->arch.cur_tsc_generation, data);
f38e098f 1272 }
e26101b1
ZA		 1273
1274 /*
1275 * We also track th most recent recorded KHZ, write and time to
1276 * allow the matching interval to be extended at each write.
1277 */
f38e098f
ZA		 1278 kvm->arch.last_tsc_nsec = ns;
1279 kvm->arch.last_tsc_write = data;
5d3cb0f6 1280 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1281
b183aa58 1282 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1283
1284 /* Keep track of which generation this VCPU has synchronized to */
1285 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1286 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1287 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1288
ba904635
WA		 1289 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1290 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1291 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1292 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1293
1294 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1295 if (matched)
1296 kvm->arch.nr_vcpus_matched_tsc++;
1297 else
1298 kvm->arch.nr_vcpus_matched_tsc = 0;
1299
1300 kvm_track_tsc_matching(vcpu);
1301 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1302}
e26101b1 1303
99e3e30a
ZA		 1304EXPORT_SYMBOL_GPL(kvm_write_tsc);
1305
d828199e
MT		 1306#ifdef CONFIG_X86_64
1307
1308static cycle_t read_tsc(void)
1309{
1310 cycle_t ret;
1311 u64 last;
1312
1313 /*
1314 * Empirically, a fence (of type that depends on the CPU)
1315 * before rdtsc is enough to ensure that rdtsc is ordered
1316 * with respect to loads. The various CPU manuals are unclear
1317 * as to whether rdtsc can be reordered with later loads,
1318 * but no one has ever seen it happen.
1319 */
1320 rdtsc_barrier();
1321 ret = (cycle_t)vget_cycles();
1322
1323 last = pvclock_gtod_data.clock.cycle_last;
1324
1325 if (likely(ret >= last))
1326 return ret;
1327
1328 /*
1329 * GCC likes to generate cmov here, but this branch is extremely
1330 * predictable (it's just a funciton of time and the likely is
1331 * very likely) and there's a data dependence, so force GCC
1332 * to generate a branch instead. I don't barrier() because
1333 * we don't actually need a barrier, and if this function
1334 * ever gets inlined it will generate worse code.
1335 */
1336 asm volatile ("");
1337 return last;
1338}
1339
1340static inline u64 vgettsc(cycle_t *cycle_now)
1341{
1342 long v;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 *cycle_now = read_tsc();
1346
1347 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1348 return v * gtod->clock.mult;
1349}
1350
1351static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1352{
1353 unsigned long seq;
1354 u64 ns;
1355 int mode;
1356 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1357
1358 ts->tv_nsec = 0;
1359 do {
1360 seq = read_seqcount_begin(&gtod->seq);
1361 mode = gtod->clock.vclock_mode;
1362 ts->tv_sec = gtod->monotonic_time_sec;
1363 ns = gtod->monotonic_time_snsec;
1364 ns += vgettsc(cycle_now);
1365 ns >>= gtod->clock.shift;
1366 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1367 timespec_add_ns(ts, ns);
1368
1369 return mode;
1370}
1371
1372/* returns true if host is using tsc clocksource */
1373static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1374{
1375 struct timespec ts;
1376
1377 /* checked again under seqlock below */
1378 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1379 return false;
1380
1381 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1382 return false;
1383
1384 monotonic_to_bootbased(&ts);
1385 *kernel_ns = timespec_to_ns(&ts);
1386
1387 return true;
1388}
1389#endif
1390
1391/*
1392 *
b48aa97e
MT		 1393 * Assuming a stable TSC across physical CPUS, and a stable TSC
1394 * across virtual CPUs, the following condition is possible.
1395 * Each numbered line represents an event visible to both
d828199e
MT		 1396 * CPUs at the next numbered event.
1397 *
1398 * "timespecX" represents host monotonic time. "tscX" represents
1399 * RDTSC value.
1400 *
1401 * VCPU0 on CPU0 | VCPU1 on CPU1
1402 *
1403 * 1. read timespec0,tsc0
1404 * 2. | timespec1 = timespec0 + N
1405 * | tsc1 = tsc0 + M
1406 * 3. transition to guest | transition to guest
1407 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1408 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1409 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1410 *
1411 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1412 *
1413 * - ret0 < ret1
1414 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1415 * ...
1416 * - 0 < N - M => M < N
1417 *
1418 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1419 * always the case (the difference between two distinct xtime instances
1420 * might be smaller then the difference between corresponding TSC reads,
1421 * when updating guest vcpus pvclock areas).
1422 *
1423 * To avoid that problem, do not allow visibility of distinct
1424 * system_timestamp/tsc_timestamp values simultaneously: use a master
1425 * copy of host monotonic time values. Update that master copy
1426 * in lockstep.
1427 *
b48aa97e 1428 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1429 *
1430 */
1431
1432static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1433{
1434#ifdef CONFIG_X86_64
1435 struct kvm_arch *ka = &kvm->arch;
1436 int vclock_mode;
b48aa97e
MT		 1437 bool host_tsc_clocksource, vcpus_matched;
1438
1439 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1440 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1441
1442 /*
1443 * If the host uses TSC clock, then passthrough TSC as stable
1444 * to the guest.
1445 */
b48aa97e 1446 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1447 &ka->master_kernel_ns,
1448 &ka->master_cycle_now);
1449
b48aa97e
MT		 1450 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1451
d828199e
MT		 1452 if (ka->use_master_clock)
1453 atomic_set(&kvm_guest_has_master_clock, 1);
1454
1455 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1456 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1457 vcpus_matched);
d828199e
MT		 1458#endif
1459}
1460
2e762ff7
MT		 1461static void kvm_gen_update_masterclock(struct kvm *kvm)
1462{
1463#ifdef CONFIG_X86_64
1464 int i;
1465 struct kvm_vcpu *vcpu;
1466 struct kvm_arch *ka = &kvm->arch;
1467
1468 spin_lock(&ka->pvclock_gtod_sync_lock);
1469 kvm_make_mclock_inprogress_request(kvm);
1470 /* no guest entries from this point */
1471 pvclock_update_vm_gtod_copy(kvm);
1472
1473 kvm_for_each_vcpu(i, vcpu, kvm)
1474 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1475
1476 /* guest entries allowed */
1477 kvm_for_each_vcpu(i, vcpu, kvm)
1478 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1479
1480 spin_unlock(&ka->pvclock_gtod_sync_lock);
1481#endif
1482}
1483
34c238a1 1484static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1485{
d828199e 1486 unsigned long flags, this_tsc_khz;
18068523 1487 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1488 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1489 s64 kernel_ns;
d828199e 1490 u64 tsc_timestamp, host_tsc;
0b79459b 1491 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1492 u8 pvclock_flags;
d828199e
MT		 1493 bool use_master_clock;
1494
1495 kernel_ns = 0;
1496 host_tsc = 0;
18068523 1497
d828199e
MT		 1498 /*
1499 * If the host uses TSC clock, then passthrough TSC as stable
1500 * to the guest.
1501 */
1502 spin_lock(&ka->pvclock_gtod_sync_lock);
1503 use_master_clock = ka->use_master_clock;
1504 if (use_master_clock) {
1505 host_tsc = ka->master_cycle_now;
1506 kernel_ns = ka->master_kernel_ns;
1507 }
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1509
1510 /* Keep irq disabled to prevent changes to the clock */
1511 local_irq_save(flags);
1512 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1513 if (unlikely(this_tsc_khz == 0)) {
1514 local_irq_restore(flags);
1515 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1516 return 1;
1517 }
d828199e
MT		 1518 if (!use_master_clock) {
1519 host_tsc = native_read_tsc();
1520 kernel_ns = get_kernel_ns();
1521 }
1522
1523 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1524
c285545f
ZA		 1525 /*
1526 * We may have to catch up the TSC to match elapsed wall clock
1527 * time for two reasons, even if kvmclock is used.
1528 * 1) CPU could have been running below the maximum TSC rate
1529 * 2) Broken TSC compensation resets the base at each VCPU
1530 * entry to avoid unknown leaps of TSC even when running
1531 * again on the same CPU. This may cause apparent elapsed
1532 * time to disappear, and the guest to stand still or run
1533 * very slowly.
1534 */
1535 if (vcpu->tsc_catchup) {
1536 u64 tsc = compute_guest_tsc(v, kernel_ns);
1537 if (tsc > tsc_timestamp) {
f1e2b260 1538 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1539 tsc_timestamp = tsc;
1540 }
50d0a0f9
GH		 1541 }
1542
18068523
GOC		 1543 local_irq_restore(flags);
1544
0b79459b 1545 if (!vcpu->pv_time_enabled)
c285545f 1546 return 0;
18068523 1547
e48672fa 1548 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1549 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1550 &vcpu->hv_clock.tsc_shift,
1551 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1552 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1553 }
1554
1555 /* With all the info we got, fill in the values */
1d5f066e 1556 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1557 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1558 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1559 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1560
18068523
GOC		 1561 /*
1562 * The interface expects us to write an even number signaling that the
1563 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1564 * state, we just increase by 2 at the end.
18068523 1565 */
50d0a0f9 1566 vcpu->hv_clock.version += 2;
18068523 1567
0b79459b
AH		 1568 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1569 &guest_hv_clock, sizeof(guest_hv_clock))))
1570 return 0;
78c0337a
MT		 1571
1572 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1573 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1574
1575 if (vcpu->pvclock_set_guest_stopped_request) {
1576 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1577 vcpu->pvclock_set_guest_stopped_request = false;
1578 }
1579
d828199e
MT		 1580 /* If the host uses TSC clocksource, then it is stable */
1581 if (use_master_clock)
1582 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1583
78c0337a
MT		 1584 vcpu->hv_clock.flags = pvclock_flags;
1585
0b79459b
AH		 1586 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1587 &vcpu->hv_clock,
1588 sizeof(vcpu->hv_clock));
8cfdc000 1589 return 0;
c8076604
GH		 1590}
1591
0061d53d
MT		 1592/*
1593 * kvmclock updates which are isolated to a given vcpu, such as
1594 * vcpu->cpu migration, should not allow system_timestamp from
1595 * the rest of the vcpus to remain static. Otherwise ntp frequency
1596 * correction applies to one vcpu's system_timestamp but not
1597 * the others.
1598 *
1599 * So in those cases, request a kvmclock update for all vcpus.
1600 * The worst case for a remote vcpu to update its kvmclock
1601 * is then bounded by maximum nohz sleep latency.
1602 */
1603
1604static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1605{
1606 int i;
1607 struct kvm *kvm = v->kvm;
1608 struct kvm_vcpu *vcpu;
1609
1610 kvm_for_each_vcpu(i, vcpu, kvm) {
1611 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1612 kvm_vcpu_kick(vcpu);
1613 }
1614}
1615
9ba075a6
AK		 1616static bool msr_mtrr_valid(unsigned msr)
1617{
1618 switch (msr) {
1619 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1620 case MSR_MTRRfix64K_00000:
1621 case MSR_MTRRfix16K_80000:
1622 case MSR_MTRRfix16K_A0000:
1623 case MSR_MTRRfix4K_C0000:
1624 case MSR_MTRRfix4K_C8000:
1625 case MSR_MTRRfix4K_D0000:
1626 case MSR_MTRRfix4K_D8000:
1627 case MSR_MTRRfix4K_E0000:
1628 case MSR_MTRRfix4K_E8000:
1629 case MSR_MTRRfix4K_F0000:
1630 case MSR_MTRRfix4K_F8000:
1631 case MSR_MTRRdefType:
1632 case MSR_IA32_CR_PAT:
1633 return true;
1634 case 0x2f8:
1635 return true;
1636 }
1637 return false;
1638}
1639
d6289b93
MT		 1640static bool valid_pat_type(unsigned t)
1641{
1642 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1643}
1644
1645static bool valid_mtrr_type(unsigned t)
1646{
1647 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1648}
1649
1650static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1651{
1652 int i;
1653
1654 if (!msr_mtrr_valid(msr))
1655 return false;
1656
1657 if (msr == MSR_IA32_CR_PAT) {
1658 for (i = 0; i < 8; i++)
1659 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1660 return false;
1661 return true;
1662 } else if (msr == MSR_MTRRdefType) {
1663 if (data & ~0xcff)
1664 return false;
1665 return valid_mtrr_type(data & 0xff);
1666 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1667 for (i = 0; i < 8 ; i++)
1668 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1669 return false;
1670 return true;
1671 }
1672
1673 /* variable MTRRs */
1674 return valid_mtrr_type(data & 0xff);
1675}
1676
9ba075a6
AK		 1677static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1678{
0bed3b56
SY		 1679 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1680
d6289b93 1681 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1682 return 1;
1683
0bed3b56
SY		 1684 if (msr == MSR_MTRRdefType) {
1685 vcpu->arch.mtrr_state.def_type = data;
1686 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1687 } else if (msr == MSR_MTRRfix64K_00000)
1688 p[0] = data;
1689 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1690 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1691 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1692 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1693 else if (msr == MSR_IA32_CR_PAT)
1694 vcpu->arch.pat = data;
1695 else { /* Variable MTRRs */
1696 int idx, is_mtrr_mask;
1697 u64 *pt;
1698
1699 idx = (msr - 0x200) / 2;
1700 is_mtrr_mask = msr - 0x200 - 2 * idx;
1701 if (!is_mtrr_mask)
1702 pt =
1703 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1704 else
1705 pt =
1706 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1707 *pt = data;
1708 }
1709
1710 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1711 return 0;
1712}
15c4a640 1713
890ca9ae 1714static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1715{
890ca9ae
HY		 1716 u64 mcg_cap = vcpu->arch.mcg_cap;
1717 unsigned bank_num = mcg_cap & 0xff;
1718
15c4a640 1719 switch (msr) {
15c4a640 1720 case MSR_IA32_MCG_STATUS:
890ca9ae 1721 vcpu->arch.mcg_status = data;
15c4a640 1722 break;
c7ac679c 1723 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1724 if (!(mcg_cap & MCG_CTL_P))
1725 return 1;
1726 if (data != 0 && data != ~(u64)0)
1727 return -1;
1728 vcpu->arch.mcg_ctl = data;
1729 break;
1730 default:
1731 if (msr >= MSR_IA32_MC0_CTL &&
1732 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1733 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1734 /* only 0 or all 1s can be written to IA32_MCi_CTL
1735 * some Linux kernels though clear bit 10 in bank 4 to
1736 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1737 * this to avoid an uncatched #GP in the guest
1738 */
890ca9ae 1739 if ((offset & 0x3) == 0 &&
114be429 1740 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1741 return -1;
1742 vcpu->arch.mce_banks[offset] = data;
1743 break;
1744 }
1745 return 1;
1746 }
1747 return 0;
1748}
1749
ffde22ac
ES		 1750static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1751{
1752 struct kvm *kvm = vcpu->kvm;
1753 int lm = is_long_mode(vcpu);
1754 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1755 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1756 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1757 : kvm->arch.xen_hvm_config.blob_size_32;
1758 u32 page_num = data & ~PAGE_MASK;
1759 u64 page_addr = data & PAGE_MASK;
1760 u8 *page;
1761 int r;
1762
1763 r = -E2BIG;
1764 if (page_num >= blob_size)
1765 goto out;
1766 r = -ENOMEM;
ff5c2c03
SL		 1767 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1768 if (IS_ERR(page)) {
1769 r = PTR_ERR(page);
ffde22ac 1770 goto out;
ff5c2c03 1771 }
ffde22ac
ES		 1772 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1773 goto out_free;
1774 r = 0;
1775out_free:
1776 kfree(page);
1777out:
1778 return r;
1779}
1780
55cd8e5a
GN		 1781static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1782{
1783 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1784}
1785
1786static bool kvm_hv_msr_partition_wide(u32 msr)
1787{
1788 bool r = false;
1789 switch (msr) {
1790 case HV_X64_MSR_GUEST_OS_ID:
1791 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1792 case HV_X64_MSR_REFERENCE_TSC:
1793 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1794 r = true;
1795 break;
1796 }
1797
1798 return r;
1799}
1800
1801static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1802{
1803 struct kvm *kvm = vcpu->kvm;
1804
1805 switch (msr) {
1806 case HV_X64_MSR_GUEST_OS_ID:
1807 kvm->arch.hv_guest_os_id = data;
1808 /* setting guest os id to zero disables hypercall page */
1809 if (!kvm->arch.hv_guest_os_id)
1810 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1811 break;
1812 case HV_X64_MSR_HYPERCALL: {
1813 u64 gfn;
1814 unsigned long addr;
1815 u8 instructions[4];
1816
1817 /* if guest os id is not set hypercall should remain disabled */
1818 if (!kvm->arch.hv_guest_os_id)
1819 break;
1820 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1821 kvm->arch.hv_hypercall = data;
1822 break;
1823 }
1824 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1825 addr = gfn_to_hva(kvm, gfn);
1826 if (kvm_is_error_hva(addr))
1827 return 1;
1828 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1829 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1830 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1831 return 1;
1832 kvm->arch.hv_hypercall = data;
1833 break;
1834 }
e984097b
VR		 1835 case HV_X64_MSR_REFERENCE_TSC: {
1836 u64 gfn;
1837 HV_REFERENCE_TSC_PAGE tsc_ref;
1838 memset(&tsc_ref, 0, sizeof(tsc_ref));
1839 kvm->arch.hv_tsc_page = data;
1840 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1841 break;
1842 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1843 if (kvm_write_guest(kvm, data,
1844 &tsc_ref, sizeof(tsc_ref)))
1845 return 1;
1846 mark_page_dirty(kvm, gfn);
1847 break;
1848 }
55cd8e5a 1849 default:
a737f256
CD		 1850 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1851 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1852 return 1;
1853 }
1854 return 0;
1855}
1856
1857static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858{
10388a07
GN		 1859 switch (msr) {
1860 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1861 unsigned long addr;
55cd8e5a 1862
10388a07
GN		 1863 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1864 vcpu->arch.hv_vapic = data;
1865 break;
1866 }
1867 addr = gfn_to_hva(vcpu->kvm, data >>
1868 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1869 if (kvm_is_error_hva(addr))
1870 return 1;
8b0cedff 1871 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1872 return 1;
1873 vcpu->arch.hv_vapic = data;
1874 break;
1875 }
1876 case HV_X64_MSR_EOI:
1877 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1878 case HV_X64_MSR_ICR:
1879 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1880 case HV_X64_MSR_TPR:
1881 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1882 default:
a737f256
CD		 1883 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1884 "data 0x%llx\n", msr, data);
10388a07
GN		 1885 return 1;
1886 }
1887
1888 return 0;
55cd8e5a
GN		 1889}
1890
344d9588
GN		 1891static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1892{
1893 gpa_t gpa = data & ~0x3f;
1894
4a969980 1895 /* Bits 2:5 are reserved, Should be zero */
6adba527 1896 if (data & 0x3c)
344d9588
GN		 1897 return 1;
1898
1899 vcpu->arch.apf.msr_val = data;
1900
1901 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1902 kvm_clear_async_pf_completion_queue(vcpu);
1903 kvm_async_pf_hash_reset(vcpu);
1904 return 0;
1905 }
1906
8f964525
AH		 1907 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1908 sizeof(u32)))
344d9588
GN		 1909 return 1;
1910
6adba527 1911 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1912 kvm_async_pf_wakeup_all(vcpu);
1913 return 0;
1914}
1915
12f9a48f
GC		 1916static void kvmclock_reset(struct kvm_vcpu *vcpu)
1917{
0b79459b 1918 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1919}
1920
c9aaa895
GC		 1921static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1922{
1923 u64 delta;
1924
1925 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1926 return;
1927
1928 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1929 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1930 vcpu->arch.st.accum_steal = delta;
1931}
1932
1933static void record_steal_time(struct kvm_vcpu *vcpu)
1934{
1935 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1936 return;
1937
1938 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1939 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1940 return;
1941
1942 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1943 vcpu->arch.st.steal.version += 2;
1944 vcpu->arch.st.accum_steal = 0;
1945
1946 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1947 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1948}
1949
8fe8ab46 1950int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1951{
5753785f 1952 bool pr = false;
8fe8ab46
WA		 1953 u32 msr = msr_info->index;
1954 u64 data = msr_info->data;
5753785f 1955
15c4a640 1956 switch (msr) {
2e32b719
BP		 1957 case MSR_AMD64_NB_CFG:
1958 case MSR_IA32_UCODE_REV:
1959 case MSR_IA32_UCODE_WRITE:
1960 case MSR_VM_HSAVE_PA:
1961 case MSR_AMD64_PATCH_LOADER:
1962 case MSR_AMD64_BU_CFG2:
1963 break;
1964
15c4a640 1965 case MSR_EFER:
b69e8cae 1966 return set_efer(vcpu, data);
8f1589d9
AP		 1967 case MSR_K7_HWCR:
1968 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1969 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1970 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1971 if (data != 0) {
a737f256
CD		 1972 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1973 data);
8f1589d9
AP		 1974 return 1;
1975 }
15c4a640 1976 break;
f7c6d140
AP		 1977 case MSR_FAM10H_MMIO_CONF_BASE:
1978 if (data != 0) {
a737f256
CD		 1979 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1980 "0x%llx\n", data);
f7c6d140
AP		 1981 return 1;
1982 }
15c4a640 1983 break;
b5e2fec0
AG		 1984 case MSR_IA32_DEBUGCTLMSR:
1985 if (!data) {
1986 /* We support the non-activated case already */
1987 break;
1988 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1989 /* Values other than LBR and BTF are vendor-specific,
1990 thus reserved and should throw a #GP */
1991 return 1;
1992 }
a737f256
CD		 1993 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1994 __func__, data);
b5e2fec0 1995 break;
9ba075a6
AK		 1996 case 0x200 ... 0x2ff:
1997 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1998 case MSR_IA32_APICBASE:
1999 kvm_set_apic_base(vcpu, data);
2000 break;
0105d1a5
GN		 2001 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2002 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2003 case MSR_IA32_TSCDEADLINE:
2004 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2005 break;
ba904635
WA		 2006 case MSR_IA32_TSC_ADJUST:
2007 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2008 if (!msr_info->host_initiated) {
2009 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2010 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2011 }
2012 vcpu->arch.ia32_tsc_adjust_msr = data;
2013 }
2014 break;
15c4a640 2015 case MSR_IA32_MISC_ENABLE:
ad312c7c 2016 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2017 break;
11c6bffa 2018 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2019 case MSR_KVM_WALL_CLOCK:
2020 vcpu->kvm->arch.wall_clock = data;
2021 kvm_write_wall_clock(vcpu->kvm, data);
2022 break;
11c6bffa 2023 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2024 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2025 u64 gpa_offset;
12f9a48f 2026 kvmclock_reset(vcpu);
18068523
GOC		 2027
2028 vcpu->arch.time = data;
0061d53d 2029 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2030
2031 /* we verify if the enable bit is set... */
2032 if (!(data & 1))
2033 break;
2034
0b79459b 2035 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2036
0b79459b 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2038 &vcpu->arch.pv_time, data & ~1ULL,
2039 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2040 vcpu->arch.pv_time_enabled = false;
2041 else
2042 vcpu->arch.pv_time_enabled = true;
32cad84f 2043
18068523
GOC		 2044 break;
2045 }
344d9588
GN		 2046 case MSR_KVM_ASYNC_PF_EN:
2047 if (kvm_pv_enable_async_pf(vcpu, data))
2048 return 1;
2049 break;
c9aaa895
GC		 2050 case MSR_KVM_STEAL_TIME:
2051
2052 if (unlikely(!sched_info_on()))
2053 return 1;
2054
2055 if (data & KVM_STEAL_RESERVED_MASK)
2056 return 1;
2057
2058 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2059 data & KVM_STEAL_VALID_BITS,
2060 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2061 return 1;
2062
2063 vcpu->arch.st.msr_val = data;
2064
2065 if (!(data & KVM_MSR_ENABLED))
2066 break;
2067
2068 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2069
2070 preempt_disable();
2071 accumulate_steal_time(vcpu);
2072 preempt_enable();
2073
2074 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2075
2076 break;
ae7a2a3f
MT		 2077 case MSR_KVM_PV_EOI_EN:
2078 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2079 return 1;
2080 break;
c9aaa895 2081
890ca9ae
HY		 2082 case MSR_IA32_MCG_CTL:
2083 case MSR_IA32_MCG_STATUS:
2084 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2085 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2086
2087 /* Performance counters are not protected by a CPUID bit,
2088 * so we should check all of them in the generic path for the sake of
2089 * cross vendor migration.
2090 * Writing a zero into the event select MSRs disables them,
2091 * which we perfectly emulate ;-). Any other value should be at least
2092 * reported, some guests depend on them.
2093 */
71db6023
AP		 2094 case MSR_K7_EVNTSEL0:
2095 case MSR_K7_EVNTSEL1:
2096 case MSR_K7_EVNTSEL2:
2097 case MSR_K7_EVNTSEL3:
2098 if (data != 0)
a737f256
CD		 2099 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2100 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2101 break;
2102 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2103 * so we ignore writes to make it happy.
2104 */
71db6023
AP		 2105 case MSR_K7_PERFCTR0:
2106 case MSR_K7_PERFCTR1:
2107 case MSR_K7_PERFCTR2:
2108 case MSR_K7_PERFCTR3:
a737f256
CD		 2109 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2110 "0x%x data 0x%llx\n", msr, data);
71db6023 2111 break;
5753785f
GN		 2112 case MSR_P6_PERFCTR0:
2113 case MSR_P6_PERFCTR1:
2114 pr = true;
2115 case MSR_P6_EVNTSEL0:
2116 case MSR_P6_EVNTSEL1:
2117 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2118 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2119
2120 if (pr || data != 0)
a737f256
CD		 2121 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2122 "0x%x data 0x%llx\n", msr, data);
5753785f 2123 break;
84e0cefa
JS		 2124 case MSR_K7_CLK_CTL:
2125 /*
2126 * Ignore all writes to this no longer documented MSR.
2127 * Writes are only relevant for old K7 processors,
2128 * all pre-dating SVM, but a recommended workaround from
4a969980 2129 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2130 * affected processor models on the command line, hence
2131 * the need to ignore the workaround.
2132 */
2133 break;
55cd8e5a
GN		 2134 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2135 if (kvm_hv_msr_partition_wide(msr)) {
2136 int r;
2137 mutex_lock(&vcpu->kvm->lock);
2138 r = set_msr_hyperv_pw(vcpu, msr, data);
2139 mutex_unlock(&vcpu->kvm->lock);
2140 return r;
2141 } else
2142 return set_msr_hyperv(vcpu, msr, data);
2143 break;
91c9c3ed 2144 case MSR_IA32_BBL_CR_CTL3:
2145 /* Drop writes to this legacy MSR -- see rdmsr
2146 * counterpart for further detail.
2147 */
a737f256 2148 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2149 break;
2b036c6b
BO		 2150 case MSR_AMD64_OSVW_ID_LENGTH:
2151 if (!guest_cpuid_has_osvw(vcpu))
2152 return 1;
2153 vcpu->arch.osvw.length = data;
2154 break;
2155 case MSR_AMD64_OSVW_STATUS:
2156 if (!guest_cpuid_has_osvw(vcpu))
2157 return 1;
2158 vcpu->arch.osvw.status = data;
2159 break;
15c4a640 2160 default:
ffde22ac
ES		 2161 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2162 return xen_hvm_config(vcpu, data);
f5132b01 2163 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2164 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2165 if (!ignore_msrs) {
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2167 msr, data);
ed85c068
AP		 2168 return 1;
2169 } else {
a737f256
CD		 2170 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2171 msr, data);
ed85c068
AP		 2172 break;
2173 }
15c4a640
CO		 2174 }
2175 return 0;
2176}
2177EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2178
2179
2180/*
2181 * Reads an msr value (of 'msr_index') into 'pdata'.
2182 * Returns 0 on success, non-0 otherwise.
2183 * Assumes vcpu_load() was already called.
2184 */
2185int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2186{
2187 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2188}
2189
9ba075a6
AK		 2190static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2191{
0bed3b56
SY		 2192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2193
9ba075a6
AK		 2194 if (!msr_mtrr_valid(msr))
2195 return 1;
2196
0bed3b56
SY		 2197 if (msr == MSR_MTRRdefType)
2198 *pdata = vcpu->arch.mtrr_state.def_type +
2199 (vcpu->arch.mtrr_state.enabled << 10);
2200 else if (msr == MSR_MTRRfix64K_00000)
2201 *pdata = p[0];
2202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2203 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2205 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2206 else if (msr == MSR_IA32_CR_PAT)
2207 *pdata = vcpu->arch.pat;
2208 else { /* Variable MTRRs */
2209 int idx, is_mtrr_mask;
2210 u64 *pt;
2211
2212 idx = (msr - 0x200) / 2;
2213 is_mtrr_mask = msr - 0x200 - 2 * idx;
2214 if (!is_mtrr_mask)
2215 pt =
2216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2217 else
2218 pt =
2219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2220 *pdata = *pt;
2221 }
2222
9ba075a6
AK		 2223 return 0;
2224}
2225
890ca9ae 2226static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2227{
2228 u64 data;
890ca9ae
HY		 2229 u64 mcg_cap = vcpu->arch.mcg_cap;
2230 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2231
2232 switch (msr) {
15c4a640
CO		 2233 case MSR_IA32_P5_MC_ADDR:
2234 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2235 data = 0;
2236 break;
15c4a640 2237 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2238 data = vcpu->arch.mcg_cap;
2239 break;
c7ac679c 2240 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2241 if (!(mcg_cap & MCG_CTL_P))
2242 return 1;
2243 data = vcpu->arch.mcg_ctl;
2244 break;
2245 case MSR_IA32_MCG_STATUS:
2246 data = vcpu->arch.mcg_status;
2247 break;
2248 default:
2249 if (msr >= MSR_IA32_MC0_CTL &&
2250 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2251 u32 offset = msr - MSR_IA32_MC0_CTL;
2252 data = vcpu->arch.mce_banks[offset];
2253 break;
2254 }
2255 return 1;
2256 }
2257 *pdata = data;
2258 return 0;
2259}
2260
55cd8e5a
GN		 2261static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2262{
2263 u64 data = 0;
2264 struct kvm *kvm = vcpu->kvm;
2265
2266 switch (msr) {
2267 case HV_X64_MSR_GUEST_OS_ID:
2268 data = kvm->arch.hv_guest_os_id;
2269 break;
2270 case HV_X64_MSR_HYPERCALL:
2271 data = kvm->arch.hv_hypercall;
2272 break;
e984097b
VR		 2273 case HV_X64_MSR_TIME_REF_COUNT: {
2274 data =
2275 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2276 break;
2277 }
2278 case HV_X64_MSR_REFERENCE_TSC:
2279 data = kvm->arch.hv_tsc_page;
2280 break;
55cd8e5a 2281 default:
a737f256 2282 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2283 return 1;
2284 }
2285
2286 *pdata = data;
2287 return 0;
2288}
2289
2290static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2291{
2292 u64 data = 0;
2293
2294 switch (msr) {
2295 case HV_X64_MSR_VP_INDEX: {
2296 int r;
2297 struct kvm_vcpu *v;
2298 kvm_for_each_vcpu(r, v, vcpu->kvm)
2299 if (v == vcpu)
2300 data = r;
2301 break;
2302 }
10388a07
GN		 2303 case HV_X64_MSR_EOI:
2304 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2305 case HV_X64_MSR_ICR:
2306 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2307 case HV_X64_MSR_TPR:
2308 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2309 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2310 data = vcpu->arch.hv_vapic;
2311 break;
55cd8e5a 2312 default:
a737f256 2313 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2314 return 1;
2315 }
2316 *pdata = data;
2317 return 0;
2318}
2319
890ca9ae
HY		 2320int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321{
2322 u64 data;
2323
2324 switch (msr) {
890ca9ae 2325 case MSR_IA32_PLATFORM_ID:
15c4a640 2326 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2327 case MSR_IA32_DEBUGCTLMSR:
2328 case MSR_IA32_LASTBRANCHFROMIP:
2329 case MSR_IA32_LASTBRANCHTOIP:
2330 case MSR_IA32_LASTINTFROMIP:
2331 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2332 case MSR_K8_SYSCFG:
2333 case MSR_K7_HWCR:
61a6bd67 2334 case MSR_VM_HSAVE_PA:
9e699624 2335 case MSR_K7_EVNTSEL0:
1f3ee616 2336 case MSR_K7_PERFCTR0:
1fdbd48c 2337 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2338 case MSR_AMD64_NB_CFG:
f7c6d140 2339 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2340 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2341 data = 0;
2342 break;
5753785f
GN		 2343 case MSR_P6_PERFCTR0:
2344 case MSR_P6_PERFCTR1:
2345 case MSR_P6_EVNTSEL0:
2346 case MSR_P6_EVNTSEL1:
2347 if (kvm_pmu_msr(vcpu, msr))
2348 return kvm_pmu_get_msr(vcpu, msr, pdata);
2349 data = 0;
2350 break;
742bc670
MT		 2351 case MSR_IA32_UCODE_REV:
2352 data = 0x100000000ULL;
2353 break;
9ba075a6
AK		 2354 case MSR_MTRRcap:
2355 data = 0x500 | KVM_NR_VAR_MTRR;
2356 break;
2357 case 0x200 ... 0x2ff:
2358 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2359 case 0xcd: /* fsb frequency */
2360 data = 3;
2361 break;
7b914098
JS		 2362 /*
2363 * MSR_EBC_FREQUENCY_ID
2364 * Conservative value valid for even the basic CPU models.
2365 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2366 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2367 * and 266MHz for model 3, or 4. Set Core Clock
2368 * Frequency to System Bus Frequency Ratio to 1 (bits
2369 * 31:24) even though these are only valid for CPU
2370 * models > 2, however guests may end up dividing or
2371 * multiplying by zero otherwise.
2372 */
2373 case MSR_EBC_FREQUENCY_ID:
2374 data = 1 << 24;
2375 break;
15c4a640
CO		 2376 case MSR_IA32_APICBASE:
2377 data = kvm_get_apic_base(vcpu);
2378 break;
0105d1a5
GN		 2379 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2380 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2381 break;
a3e06bbe
LJ		 2382 case MSR_IA32_TSCDEADLINE:
2383 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2384 break;
ba904635
WA		 2385 case MSR_IA32_TSC_ADJUST:
2386 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2387 break;
15c4a640 2388 case MSR_IA32_MISC_ENABLE:
ad312c7c 2389 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2390 break;
847f0ad8
AG		 2391 case MSR_IA32_PERF_STATUS:
2392 /* TSC increment by tick */
2393 data = 1000ULL;
2394 /* CPU multiplier */
2395 data |= (((uint64_t)4ULL) << 40);
2396 break;
15c4a640 2397 case MSR_EFER:
f6801dff 2398 data = vcpu->arch.efer;
15c4a640 2399 break;
18068523 2400 case MSR_KVM_WALL_CLOCK:
11c6bffa 2401 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2402 data = vcpu->kvm->arch.wall_clock;
2403 break;
2404 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2405 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2406 data = vcpu->arch.time;
2407 break;
344d9588
GN		 2408 case MSR_KVM_ASYNC_PF_EN:
2409 data = vcpu->arch.apf.msr_val;
2410 break;
c9aaa895
GC		 2411 case MSR_KVM_STEAL_TIME:
2412 data = vcpu->arch.st.msr_val;
2413 break;
1d92128f
MT		 2414 case MSR_KVM_PV_EOI_EN:
2415 data = vcpu->arch.pv_eoi.msr_val;
2416 break;
890ca9ae
HY		 2417 case MSR_IA32_P5_MC_ADDR:
2418 case MSR_IA32_P5_MC_TYPE:
2419 case MSR_IA32_MCG_CAP:
2420 case MSR_IA32_MCG_CTL:
2421 case MSR_IA32_MCG_STATUS:
2422 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2423 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2424 case MSR_K7_CLK_CTL:
2425 /*
2426 * Provide expected ramp-up count for K7. All other
2427 * are set to zero, indicating minimum divisors for
2428 * every field.
2429 *
2430 * This prevents guest kernels on AMD host with CPU
2431 * type 6, model 8 and higher from exploding due to
2432 * the rdmsr failing.
2433 */
2434 data = 0x20000000;
2435 break;
55cd8e5a
GN		 2436 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2437 if (kvm_hv_msr_partition_wide(msr)) {
2438 int r;
2439 mutex_lock(&vcpu->kvm->lock);
2440 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2441 mutex_unlock(&vcpu->kvm->lock);
2442 return r;
2443 } else
2444 return get_msr_hyperv(vcpu, msr, pdata);
2445 break;
91c9c3ed 2446 case MSR_IA32_BBL_CR_CTL3:
2447 /* This legacy MSR exists but isn't fully documented in current
2448 * silicon. It is however accessed by winxp in very narrow
2449 * scenarios where it sets bit #19, itself documented as
2450 * a "reserved" bit. Best effort attempt to source coherent
2451 * read data here should the balance of the register be
2452 * interpreted by the guest:
2453 *
2454 * L2 cache control register 3: 64GB range, 256KB size,
2455 * enabled, latency 0x1, configured
2456 */
2457 data = 0xbe702111;
2458 break;
2b036c6b
BO		 2459 case MSR_AMD64_OSVW_ID_LENGTH:
2460 if (!guest_cpuid_has_osvw(vcpu))
2461 return 1;
2462 data = vcpu->arch.osvw.length;
2463 break;
2464 case MSR_AMD64_OSVW_STATUS:
2465 if (!guest_cpuid_has_osvw(vcpu))
2466 return 1;
2467 data = vcpu->arch.osvw.status;
2468 break;
15c4a640 2469 default:
f5132b01
GN		 2470 if (kvm_pmu_msr(vcpu, msr))
2471 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2472 if (!ignore_msrs) {
a737f256 2473 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2474 return 1;
2475 } else {
a737f256 2476 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2477 data = 0;
2478 }
2479 break;
15c4a640
CO		 2480 }
2481 *pdata = data;
2482 return 0;
2483}
2484EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2485
313a3dc7
CO		 2486/*
2487 * Read or write a bunch of msrs. All parameters are kernel addresses.
2488 *
2489 * @return number of msrs set successfully.
2490 */
2491static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2492 struct kvm_msr_entry *entries,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data))
2495{
f656ce01 2496 int i, idx;
313a3dc7 2497
f656ce01 2498 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2499 for (i = 0; i < msrs->nmsrs; ++i)
2500 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2501 break;
f656ce01 2502 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2503
313a3dc7
CO		 2504 return i;
2505}
2506
2507/*
2508 * Read or write a bunch of msrs. Parameters are user addresses.
2509 *
2510 * @return number of msrs set successfully.
2511 */
2512static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2513 int (*do_msr)(struct kvm_vcpu *vcpu,
2514 unsigned index, u64 *data),
2515 int writeback)
2516{
2517 struct kvm_msrs msrs;
2518 struct kvm_msr_entry *entries;
2519 int r, n;
2520 unsigned size;
2521
2522 r = -EFAULT;
2523 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2524 goto out;
2525
2526 r = -E2BIG;
2527 if (msrs.nmsrs >= MAX_IO_MSRS)
2528 goto out;
2529
313a3dc7 2530 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2531 entries = memdup_user(user_msrs->entries, size);
2532 if (IS_ERR(entries)) {
2533 r = PTR_ERR(entries);
313a3dc7 2534 goto out;
ff5c2c03 2535 }
313a3dc7
CO		 2536
2537 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2538 if (r < 0)
2539 goto out_free;
2540
2541 r = -EFAULT;
2542 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2543 goto out_free;
2544
2545 r = n;
2546
2547out_free:
7a73c028 2548 kfree(entries);
313a3dc7
CO		 2549out:
2550 return r;
2551}
2552
018d00d2
ZX		 2553int kvm_dev_ioctl_check_extension(long ext)
2554{
2555 int r;
2556
2557 switch (ext) {
2558 case KVM_CAP_IRQCHIP:
2559 case KVM_CAP_HLT:
2560 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2561 case KVM_CAP_SET_TSS_ADDR:
07716717 2562 case KVM_CAP_EXT_CPUID:
9c15bb1d 2563 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2564 case KVM_CAP_CLOCKSOURCE:
7837699f 2565 case KVM_CAP_PIT:
a28e4f5a 2566 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2567 case KVM_CAP_MP_STATE:
ed848624 2568 case KVM_CAP_SYNC_MMU:
a355c85c 2569 case KVM_CAP_USER_NMI:
52d939a0 2570 case KVM_CAP_REINJECT_CONTROL:
4925663a 2571 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2572 case KVM_CAP_IRQFD:
d34e6b17 2573 case KVM_CAP_IOEVENTFD:
c5ff41ce 2574 case KVM_CAP_PIT2:
e9f42757 2575 case KVM_CAP_PIT_STATE2:
b927a3ce 2576 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2577 case KVM_CAP_XEN_HVM:
afbcf7ab 2578 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2579 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2580 case KVM_CAP_HYPERV:
10388a07 2581 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2582 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2583 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2584 case KVM_CAP_DEBUGREGS:
d2be1651 2585 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2586 case KVM_CAP_XSAVE:
344d9588 2587 case KVM_CAP_ASYNC_PF:
92a1f12d 2588 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2589 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2590 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2591#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2592 case KVM_CAP_ASSIGN_DEV_IRQ:
2593 case KVM_CAP_PCI_2_3:
e984097b 2594 case KVM_CAP_HYPERV_TIME:
2a5bab10 2595#endif
018d00d2
ZX		 2596 r = 1;
2597 break;
542472b5
LV		 2598 case KVM_CAP_COALESCED_MMIO:
2599 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2600 break;
774ead3a
AK		 2601 case KVM_CAP_VAPIC:
2602 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2603 break;
f725230a 2604 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2605 r = KVM_SOFT_MAX_VCPUS;
2606 break;
2607 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2608 r = KVM_MAX_VCPUS;
2609 break;
a988b910 2610 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2611 r = KVM_USER_MEM_SLOTS;
a988b910 2612 break;
a68a6a72
MT		 2613 case KVM_CAP_PV_MMU: /* obsolete */
2614 r = 0;
2f333bcb 2615 break;
4cee4b72 2616#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2617 case KVM_CAP_IOMMU:
a1b60c1c 2618 r = iommu_present(&pci_bus_type);
62c476c7 2619 break;
4cee4b72 2620#endif
890ca9ae
HY		 2621 case KVM_CAP_MCE:
2622 r = KVM_MAX_MCE_BANKS;
2623 break;
2d5b5a66
SY		 2624 case KVM_CAP_XCRS:
2625 r = cpu_has_xsave;
2626 break;
92a1f12d
JR		 2627 case KVM_CAP_TSC_CONTROL:
2628 r = kvm_has_tsc_control;
2629 break;
4d25a066
JK		 2630 case KVM_CAP_TSC_DEADLINE_TIMER:
2631 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2632 break;
018d00d2
ZX		 2633 default:
2634 r = 0;
2635 break;
2636 }
2637 return r;
2638
2639}
2640
043405e1
CO		 2641long kvm_arch_dev_ioctl(struct file *filp,
2642 unsigned int ioctl, unsigned long arg)
2643{
2644 void __user *argp = (void __user *)arg;
2645 long r;
2646
2647 switch (ioctl) {
2648 case KVM_GET_MSR_INDEX_LIST: {
2649 struct kvm_msr_list __user *user_msr_list = argp;
2650 struct kvm_msr_list msr_list;
2651 unsigned n;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2655 goto out;
2656 n = msr_list.nmsrs;
2657 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2658 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2659 goto out;
2660 r = -E2BIG;
e125e7b6 2661 if (n < msr_list.nmsrs)
043405e1
CO		 2662 goto out;
2663 r = -EFAULT;
2664 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2665 num_msrs_to_save * sizeof(u32)))
2666 goto out;
e125e7b6 2667 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2668 &emulated_msrs,
2669 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2670 goto out;
2671 r = 0;
2672 break;
2673 }
9c15bb1d
BP		 2674 case KVM_GET_SUPPORTED_CPUID:
2675 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2676 struct kvm_cpuid2 __user *cpuid_arg = argp;
2677 struct kvm_cpuid2 cpuid;
2678
2679 r = -EFAULT;
2680 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2681 goto out;
9c15bb1d
BP		 2682
2683 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2684 ioctl);
674eea0f
AK		 2685 if (r)
2686 goto out;
2687
2688 r = -EFAULT;
2689 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
890ca9ae
HY		 2694 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2695 u64 mce_cap;
2696
2697 mce_cap = KVM_MCE_CAP_SUPPORTED;
2698 r = -EFAULT;
2699 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2700 goto out;
2701 r = 0;
2702 break;
2703 }
043405e1
CO		 2704 default:
2705 r = -EINVAL;
2706 }
2707out:
2708 return r;
2709}
2710
f5f48ee1
SY		 2711static void wbinvd_ipi(void *garbage)
2712{
2713 wbinvd();
2714}
2715
2716static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717{
e0f0bbc5 2718 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2719}
2720
313a3dc7
CO		 2721void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2722{
f5f48ee1
SY		 2723 /* Address WBINVD may be executed by guest */
2724 if (need_emulate_wbinvd(vcpu)) {
2725 if (kvm_x86_ops->has_wbinvd_exit())
2726 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2727 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2728 smp_call_function_single(vcpu->cpu,
2729 wbinvd_ipi, NULL, 1);
2730 }
2731
313a3dc7 2732 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2733
0dd6a6ed
ZA		 2734 /* Apply any externally detected TSC adjustments (due to suspend) */
2735 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2736 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2737 vcpu->arch.tsc_offset_adjustment = 0;
2738 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2739 }
8f6055cb 2740
48434c20 2741 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2742 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2743 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2744 if (tsc_delta < 0)
2745 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2746 if (check_tsc_unstable()) {
b183aa58
ZA		 2747 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2748 vcpu->arch.last_guest_tsc);
2749 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2750 vcpu->arch.tsc_catchup = 1;
c285545f 2751 }
d98d07ca
MT		 2752 /*
2753 * On a host with synchronized TSC, there is no need to update
2754 * kvmclock on vcpu->cpu migration
2755 */
2756 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2757 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2758 if (vcpu->cpu != cpu)
2759 kvm_migrate_timers(vcpu);
e48672fa 2760 vcpu->cpu = cpu;
6b7d7e76 2761 }
c9aaa895
GC		 2762
2763 accumulate_steal_time(vcpu);
2764 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2765}
2766
2767void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2768{
02daab21 2769 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2770 kvm_put_guest_fpu(vcpu);
6f526ec5 2771 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2772}
2773
313a3dc7
CO		 2774static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2775 struct kvm_lapic_state *s)
2776{
5a71785d 2777 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2778 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2779
2780 return 0;
2781}
2782
2783static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2784 struct kvm_lapic_state *s)
2785{
64eb0620 2786 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2787 update_cr8_intercept(vcpu);
313a3dc7
CO		 2788
2789 return 0;
2790}
2791
f77bc6a4
ZX		 2792static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2793 struct kvm_interrupt *irq)
2794{
02cdb50f 2795 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2796 return -EINVAL;
2797 if (irqchip_in_kernel(vcpu->kvm))
2798 return -ENXIO;
f77bc6a4 2799
66fd3f7f 2800 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2802
f77bc6a4
ZX		 2803 return 0;
2804}
2805
c4abb7c9
JK		 2806static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2807{
c4abb7c9 2808 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2809
2810 return 0;
2811}
2812
b209749f
AK		 2813static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2814 struct kvm_tpr_access_ctl *tac)
2815{
2816 if (tac->flags)
2817 return -EINVAL;
2818 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2819 return 0;
2820}
2821
890ca9ae
HY		 2822static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2823 u64 mcg_cap)
2824{
2825 int r;
2826 unsigned bank_num = mcg_cap & 0xff, bank;
2827
2828 r = -EINVAL;
a9e38c3e 2829 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2830 goto out;
2831 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2832 goto out;
2833 r = 0;
2834 vcpu->arch.mcg_cap = mcg_cap;
2835 /* Init IA32_MCG_CTL to all 1s */
2836 if (mcg_cap & MCG_CTL_P)
2837 vcpu->arch.mcg_ctl = ~(u64)0;
2838 /* Init IA32_MCi_CTL to all 1s */
2839 for (bank = 0; bank < bank_num; bank++)
2840 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2841out:
2842 return r;
2843}
2844
2845static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2846 struct kvm_x86_mce *mce)
2847{
2848 u64 mcg_cap = vcpu->arch.mcg_cap;
2849 unsigned bank_num = mcg_cap & 0xff;
2850 u64 *banks = vcpu->arch.mce_banks;
2851
2852 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2853 return -EINVAL;
2854 /*
2855 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2856 * reporting is disabled
2857 */
2858 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2859 vcpu->arch.mcg_ctl != ~(u64)0)
2860 return 0;
2861 banks += 4 * mce->bank;
2862 /*
2863 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2864 * reporting is disabled for the bank
2865 */
2866 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2867 return 0;
2868 if (mce->status & MCI_STATUS_UC) {
2869 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2870 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2871 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2872 return 0;
2873 }
2874 if (banks[1] & MCI_STATUS_VAL)
2875 mce->status |= MCI_STATUS_OVER;
2876 banks[2] = mce->addr;
2877 banks[3] = mce->misc;
2878 vcpu->arch.mcg_status = mce->mcg_status;
2879 banks[1] = mce->status;
2880 kvm_queue_exception(vcpu, MC_VECTOR);
2881 } else if (!(banks[1] & MCI_STATUS_VAL)
2882 || !(banks[1] & MCI_STATUS_UC)) {
2883 if (banks[1] & MCI_STATUS_VAL)
2884 mce->status |= MCI_STATUS_OVER;
2885 banks[2] = mce->addr;
2886 banks[3] = mce->misc;
2887 banks[1] = mce->status;
2888 } else
2889 banks[1] |= MCI_STATUS_OVER;
2890 return 0;
2891}
2892
3cfc3092
JK		 2893static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2894 struct kvm_vcpu_events *events)
2895{
7460fb4a 2896 process_nmi(vcpu);
03b82a30
JK		 2897 events->exception.injected =
2898 vcpu->arch.exception.pending &&
2899 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2900 events->exception.nr = vcpu->arch.exception.nr;
2901 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2902 events->exception.pad = 0;
3cfc3092
JK		 2903 events->exception.error_code = vcpu->arch.exception.error_code;
2904
03b82a30
JK		 2905 events->interrupt.injected =
2906 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2907 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2908 events->interrupt.soft = 0;
48005f64
JK		 2909 events->interrupt.shadow =
2910 kvm_x86_ops->get_interrupt_shadow(vcpu,
2911 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2912
2913 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2914 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2915 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2916 events->nmi.pad = 0;
3cfc3092 2917
66450a21 2918 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2919
dab4b911 2920 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2921 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2922 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2923}
2924
2925static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927{
dab4b911 2928 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2929 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2930 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2931 return -EINVAL;
2932
7460fb4a 2933 process_nmi(vcpu);
3cfc3092
JK		 2934 vcpu->arch.exception.pending = events->exception.injected;
2935 vcpu->arch.exception.nr = events->exception.nr;
2936 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2937 vcpu->arch.exception.error_code = events->exception.error_code;
2938
2939 vcpu->arch.interrupt.pending = events->interrupt.injected;
2940 vcpu->arch.interrupt.nr = events->interrupt.nr;
2941 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2942 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2943 kvm_x86_ops->set_interrupt_shadow(vcpu,
2944 events->interrupt.shadow);
3cfc3092
JK		 2945
2946 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2947 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2948 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2949 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2950
66450a21
JK		 2951 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2952 kvm_vcpu_has_lapic(vcpu))
2953 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2954
3842d135
AK		 2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
2956
3cfc3092
JK		 2957 return 0;
2958}
2959
a1efbe77
JK		 2960static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2961 struct kvm_debugregs *dbgregs)
2962{
a1efbe77
JK		 2963 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2964 dbgregs->dr6 = vcpu->arch.dr6;
2965 dbgregs->dr7 = vcpu->arch.dr7;
2966 dbgregs->flags = 0;
97e69aa6 2967 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2968}
2969
2970static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2971 struct kvm_debugregs *dbgregs)
2972{
2973 if (dbgregs->flags)
2974 return -EINVAL;
2975
a1efbe77
JK		 2976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2977 vcpu->arch.dr6 = dbgregs->dr6;
2978 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2979 kvm_update_dr7(vcpu);
a1efbe77 2980
a1efbe77
JK		 2981 return 0;
2982}
2983
2d5b5a66
SY		 2984static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2985 struct kvm_xsave *guest_xsave)
2986{
4344ee98 2987 if (cpu_has_xsave) {
2d5b5a66
SY		 2988 memcpy(guest_xsave->region,
2989 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 2990 vcpu->arch.guest_xstate_size);
2991 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
2992 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
2993 } else {
2d5b5a66
SY		 2994 memcpy(guest_xsave->region,
2995 &vcpu->arch.guest_fpu.state->fxsave,
2996 sizeof(struct i387_fxsave_struct));
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2998 XSTATE_FPSSE;
2999 }
3000}
3001
3002static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3003 struct kvm_xsave *guest_xsave)
3004{
3005 u64 xstate_bv =
3006 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3007
d7876f1b
PB		 3008 if (cpu_has_xsave) {
3009 /*
3010 * Here we allow setting states that are not present in
3011 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3012 * with old userspace.
3013 */
3014 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3015 return -EINVAL;
3016 if (xstate_bv & ~host_xcr0)
3017 return -EINVAL;
2d5b5a66 3018 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3019 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3020 } else {
2d5b5a66
SY		 3021 if (xstate_bv & ~XSTATE_FPSSE)
3022 return -EINVAL;
3023 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3024 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3025 }
3026 return 0;
3027}
3028
3029static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031{
3032 if (!cpu_has_xsave) {
3033 guest_xcrs->nr_xcrs = 0;
3034 return;
3035 }
3036
3037 guest_xcrs->nr_xcrs = 1;
3038 guest_xcrs->flags = 0;
3039 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3040 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3041}
3042
3043static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3044 struct kvm_xcrs *guest_xcrs)
3045{
3046 int i, r = 0;
3047
3048 if (!cpu_has_xsave)
3049 return -EINVAL;
3050
3051 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3052 return -EINVAL;
3053
3054 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3055 /* Only support XCR0 currently */
c67a04cb 3056 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3057 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3058 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3059 break;
3060 }
3061 if (r)
3062 r = -EINVAL;
3063 return r;
3064}
3065
1c0b28c2
EM		 3066/*
3067 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3068 * stopped by the hypervisor. This function will be called from the host only.
3069 * EINVAL is returned when the host attempts to set the flag for a guest that
3070 * does not support pv clocks.
3071 */
3072static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3073{
0b79459b 3074 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3075 return -EINVAL;
51d59c6b 3076 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3078 return 0;
3079}
3080
313a3dc7
CO		 3081long kvm_arch_vcpu_ioctl(struct file *filp,
3082 unsigned int ioctl, unsigned long arg)
3083{
3084 struct kvm_vcpu *vcpu = filp->private_data;
3085 void __user *argp = (void __user *)arg;
3086 int r;
d1ac91d8
AK		 3087 union {
3088 struct kvm_lapic_state *lapic;
3089 struct kvm_xsave *xsave;
3090 struct kvm_xcrs *xcrs;
3091 void *buffer;
3092 } u;
3093
3094 u.buffer = NULL;
313a3dc7
CO		 3095 switch (ioctl) {
3096 case KVM_GET_LAPIC: {
2204ae3c
MT		 3097 r = -EINVAL;
3098 if (!vcpu->arch.apic)
3099 goto out;
d1ac91d8 3100 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3101
b772ff36 3102 r = -ENOMEM;
d1ac91d8 3103 if (!u.lapic)
b772ff36 3104 goto out;
d1ac91d8 3105 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3106 if (r)
3107 goto out;
3108 r = -EFAULT;
d1ac91d8 3109 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3110 goto out;
3111 r = 0;
3112 break;
3113 }
3114 case KVM_SET_LAPIC: {
2204ae3c
MT		 3115 r = -EINVAL;
3116 if (!vcpu->arch.apic)
3117 goto out;
ff5c2c03 3118 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3119 if (IS_ERR(u.lapic))
3120 return PTR_ERR(u.lapic);
ff5c2c03 3121
d1ac91d8 3122 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3123 break;
3124 }
f77bc6a4
ZX		 3125 case KVM_INTERRUPT: {
3126 struct kvm_interrupt irq;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&irq, argp, sizeof irq))
3130 goto out;
3131 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3132 break;
3133 }
c4abb7c9
JK		 3134 case KVM_NMI: {
3135 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3136 break;
3137 }
313a3dc7
CO		 3138 case KVM_SET_CPUID: {
3139 struct kvm_cpuid __user *cpuid_arg = argp;
3140 struct kvm_cpuid cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3146 break;
3147 }
07716717
DK		 3148 case KVM_SET_CPUID2: {
3149 struct kvm_cpuid2 __user *cpuid_arg = argp;
3150 struct kvm_cpuid2 cpuid;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 goto out;
3155 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3156 cpuid_arg->entries);
07716717
DK		 3157 break;
3158 }
3159 case KVM_GET_CPUID2: {
3160 struct kvm_cpuid2 __user *cpuid_arg = argp;
3161 struct kvm_cpuid2 cpuid;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3165 goto out;
3166 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3167 cpuid_arg->entries);
07716717
DK		 3168 if (r)
3169 goto out;
3170 r = -EFAULT;
3171 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3172 goto out;
3173 r = 0;
3174 break;
3175 }
313a3dc7
CO		 3176 case KVM_GET_MSRS:
3177 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3178 break;
3179 case KVM_SET_MSRS:
3180 r = msr_io(vcpu, argp, do_set_msr, 0);
3181 break;
b209749f
AK		 3182 case KVM_TPR_ACCESS_REPORTING: {
3183 struct kvm_tpr_access_ctl tac;
3184
3185 r = -EFAULT;
3186 if (copy_from_user(&tac, argp, sizeof tac))
3187 goto out;
3188 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3189 if (r)
3190 goto out;
3191 r = -EFAULT;
3192 if (copy_to_user(argp, &tac, sizeof tac))
3193 goto out;
3194 r = 0;
3195 break;
3196 };
b93463aa
AK		 3197 case KVM_SET_VAPIC_ADDR: {
3198 struct kvm_vapic_addr va;
3199
3200 r = -EINVAL;
3201 if (!irqchip_in_kernel(vcpu->kvm))
3202 goto out;
3203 r = -EFAULT;
3204 if (copy_from_user(&va, argp, sizeof va))
3205 goto out;
3206 r = 0;
3207 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3208 break;
3209 }
890ca9ae
HY		 3210 case KVM_X86_SETUP_MCE: {
3211 u64 mcg_cap;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3215 goto out;
3216 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3217 break;
3218 }
3219 case KVM_X86_SET_MCE: {
3220 struct kvm_x86_mce mce;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&mce, argp, sizeof mce))
3224 goto out;
3225 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3226 break;
3227 }
3cfc3092
JK		 3228 case KVM_GET_VCPU_EVENTS: {
3229 struct kvm_vcpu_events events;
3230
3231 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3232
3233 r = -EFAULT;
3234 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3235 break;
3236 r = 0;
3237 break;
3238 }
3239 case KVM_SET_VCPU_EVENTS: {
3240 struct kvm_vcpu_events events;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3247 break;
3248 }
a1efbe77
JK		 3249 case KVM_GET_DEBUGREGS: {
3250 struct kvm_debugregs dbgregs;
3251
3252 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3253
3254 r = -EFAULT;
3255 if (copy_to_user(argp, &dbgregs,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258 r = 0;
3259 break;
3260 }
3261 case KVM_SET_DEBUGREGS: {
3262 struct kvm_debugregs dbgregs;
3263
3264 r = -EFAULT;
3265 if (copy_from_user(&dbgregs, argp,
3266 sizeof(struct kvm_debugregs)))
3267 break;
3268
3269 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3270 break;
3271 }
2d5b5a66 3272 case KVM_GET_XSAVE: {
d1ac91d8 3273 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3274 r = -ENOMEM;
d1ac91d8 3275 if (!u.xsave)
2d5b5a66
SY		 3276 break;
3277
d1ac91d8 3278 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3279
3280 r = -EFAULT;
d1ac91d8 3281 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XSAVE: {
ff5c2c03 3287 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3288 if (IS_ERR(u.xsave))
3289 return PTR_ERR(u.xsave);
2d5b5a66 3290
d1ac91d8 3291 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3292 break;
3293 }
3294 case KVM_GET_XCRS: {
d1ac91d8 3295 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3296 r = -ENOMEM;
d1ac91d8 3297 if (!u.xcrs)
2d5b5a66
SY		 3298 break;
3299
d1ac91d8 3300 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3301
3302 r = -EFAULT;
d1ac91d8 3303 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3304 sizeof(struct kvm_xcrs)))
3305 break;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_SET_XCRS: {
ff5c2c03 3310 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3311 if (IS_ERR(u.xcrs))
3312 return PTR_ERR(u.xcrs);
2d5b5a66 3313
d1ac91d8 3314 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3315 break;
3316 }
92a1f12d
JR		 3317 case KVM_SET_TSC_KHZ: {
3318 u32 user_tsc_khz;
3319
3320 r = -EINVAL;
92a1f12d
JR		 3321 user_tsc_khz = (u32)arg;
3322
3323 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3324 goto out;
3325
cc578287
ZA		 3326 if (user_tsc_khz == 0)
3327 user_tsc_khz = tsc_khz;
3328
3329 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3330
3331 r = 0;
3332 goto out;
3333 }
3334 case KVM_GET_TSC_KHZ: {
cc578287 3335 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3336 goto out;
3337 }
1c0b28c2
EM		 3338 case KVM_KVMCLOCK_CTRL: {
3339 r = kvm_set_guest_paused(vcpu);
3340 goto out;
3341 }
313a3dc7
CO		 3342 default:
3343 r = -EINVAL;
3344 }
3345out:
d1ac91d8 3346 kfree(u.buffer);
313a3dc7
CO		 3347 return r;
3348}
3349
5b1c1493
CO		 3350int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3351{
3352 return VM_FAULT_SIGBUS;
3353}
3354
1fe779f8
CO		 3355static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3356{
3357 int ret;
3358
3359 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3360 return -EINVAL;
1fe779f8
CO		 3361 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3362 return ret;
3363}
3364
b927a3ce
SY		 3365static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3366 u64 ident_addr)
3367{
3368 kvm->arch.ept_identity_map_addr = ident_addr;
3369 return 0;
3370}
3371
1fe779f8
CO		 3372static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3373 u32 kvm_nr_mmu_pages)
3374{
3375 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3376 return -EINVAL;
3377
79fac95e 3378 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3379
3380 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3381 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3382
79fac95e 3383 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3384 return 0;
3385}
3386
3387static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3388{
39de71ec 3389 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3390}
3391
1fe779f8
CO		 3392static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3393{
3394 int r;
3395
3396 r = 0;
3397 switch (chip->chip_id) {
3398 case KVM_IRQCHIP_PIC_MASTER:
3399 memcpy(&chip->chip.pic,
3400 &pic_irqchip(kvm)->pics[0],
3401 sizeof(struct kvm_pic_state));
3402 break;
3403 case KVM_IRQCHIP_PIC_SLAVE:
3404 memcpy(&chip->chip.pic,
3405 &pic_irqchip(kvm)->pics[1],
3406 sizeof(struct kvm_pic_state));
3407 break;
3408 case KVM_IRQCHIP_IOAPIC:
eba0226b 3409 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3410 break;
3411 default:
3412 r = -EINVAL;
3413 break;
3414 }
3415 return r;
3416}
3417
3418static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3419{
3420 int r;
3421
3422 r = 0;
3423 switch (chip->chip_id) {
3424 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3425 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3426 memcpy(&pic_irqchip(kvm)->pics[0],
3427 &chip->chip.pic,
3428 sizeof(struct kvm_pic_state));
f4f51050 3429 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3430 break;
3431 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3432 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3433 memcpy(&pic_irqchip(kvm)->pics[1],
3434 &chip->chip.pic,
3435 sizeof(struct kvm_pic_state));
f4f51050 3436 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3437 break;
3438 case KVM_IRQCHIP_IOAPIC:
eba0226b 3439 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3440 break;
3441 default:
3442 r = -EINVAL;
3443 break;
3444 }
3445 kvm_pic_update_irq(pic_irqchip(kvm));
3446 return r;
3447}
3448
e0f63cb9
SY		 3449static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450{
3451 int r = 0;
3452
894a9c55 3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3454 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3456 return r;
3457}
3458
3459static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3460{
3461 int r = 0;
3462
894a9c55 3463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3464 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3465 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3466 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3467 return r;
3468}
3469
3470static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3471{
3472 int r = 0;
3473
3474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3475 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3476 sizeof(ps->channels));
3477 ps->flags = kvm->arch.vpit->pit_state.flags;
3478 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3479 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3480 return r;
3481}
3482
3483static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3484{
3485 int r = 0, start = 0;
3486 u32 prev_legacy, cur_legacy;
3487 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3488 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3489 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3490 if (!prev_legacy && cur_legacy)
3491 start = 1;
3492 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3493 sizeof(kvm->arch.vpit->pit_state.channels));
3494 kvm->arch.vpit->pit_state.flags = ps->flags;
3495 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3497 return r;
3498}
3499
52d939a0
MT		 3500static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3501 struct kvm_reinject_control *control)
3502{
3503 if (!kvm->arch.vpit)
3504 return -ENXIO;
894a9c55 3505 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3506 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3507 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3508 return 0;
3509}
3510
95d4c16c 3511/**
60c34612
TY		 3512 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3513 * @kvm: kvm instance
3514 * @log: slot id and address to which we copy the log
95d4c16c 3515 *
60c34612
TY		 3516 * We need to keep it in mind that VCPU threads can write to the bitmap
3517 * concurrently. So, to avoid losing data, we keep the following order for
3518 * each bit:
95d4c16c 3519 *
60c34612
TY		 3520 * 1. Take a snapshot of the bit and clear it if needed.
3521 * 2. Write protect the corresponding page.
3522 * 3. Flush TLB's if needed.
3523 * 4. Copy the snapshot to the userspace.
95d4c16c 3524 *
60c34612
TY		 3525 * Between 2 and 3, the guest may write to the page using the remaining TLB
3526 * entry. This is not a problem because the page will be reported dirty at
3527 * step 4 using the snapshot taken before and step 3 ensures that successive
3528 * writes will be logged for the next call.
5bb064dc 3529 */
60c34612 3530int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3531{
7850ac54 3532 int r;
5bb064dc 3533 struct kvm_memory_slot *memslot;
60c34612
TY		 3534 unsigned long n, i;
3535 unsigned long *dirty_bitmap;
3536 unsigned long *dirty_bitmap_buffer;
3537 bool is_dirty = false;
5bb064dc 3538
79fac95e 3539 mutex_lock(&kvm->slots_lock);
5bb064dc 3540
b050b015 3541 r = -EINVAL;
bbacc0c1 3542 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3543 goto out;
3544
28a37544 3545 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3546
3547 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3548 r = -ENOENT;
60c34612 3549 if (!dirty_bitmap)
b050b015
MT		 3550 goto out;
3551
87bf6e7d 3552 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3553
60c34612
TY		 3554 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3555 memset(dirty_bitmap_buffer, 0, n);
b050b015 3556
60c34612 3557 spin_lock(&kvm->mmu_lock);
b050b015 3558
60c34612
TY		 3559 for (i = 0; i < n / sizeof(long); i++) {
3560 unsigned long mask;
3561 gfn_t offset;
cdfca7b3 3562
60c34612
TY		 3563 if (!dirty_bitmap[i])
3564 continue;
b050b015 3565
60c34612 3566 is_dirty = true;
914ebccd 3567
60c34612
TY		 3568 mask = xchg(&dirty_bitmap[i], 0);
3569 dirty_bitmap_buffer[i] = mask;
edde99ce 3570
60c34612
TY		 3571 offset = i * BITS_PER_LONG;
3572 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3573 }
60c34612
TY		 3574 if (is_dirty)
3575 kvm_flush_remote_tlbs(kvm);
3576
3577 spin_unlock(&kvm->mmu_lock);
3578
3579 r = -EFAULT;
3580 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3581 goto out;
b050b015 3582
5bb064dc
ZX		 3583 r = 0;
3584out:
79fac95e 3585 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3586 return r;
3587}
3588
aa2fbe6d
YZ		 3589int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3590 bool line_status)
23d43cf9
CD		 3591{
3592 if (!irqchip_in_kernel(kvm))
3593 return -ENXIO;
3594
3595 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3596 irq_event->irq, irq_event->level,
3597 line_status);
23d43cf9
CD		 3598 return 0;
3599}
3600
1fe779f8
CO		 3601long kvm_arch_vm_ioctl(struct file *filp,
3602 unsigned int ioctl, unsigned long arg)
3603{
3604 struct kvm *kvm = filp->private_data;
3605 void __user *argp = (void __user *)arg;
367e1319 3606 int r = -ENOTTY;
f0d66275
DH		 3607 /*
3608 * This union makes it completely explicit to gcc-3.x
3609 * that these two variables' stack usage should be
3610 * combined, not added together.
3611 */
3612 union {
3613 struct kvm_pit_state ps;
e9f42757 3614 struct kvm_pit_state2 ps2;
c5ff41ce 3615 struct kvm_pit_config pit_config;
f0d66275 3616 } u;
1fe779f8
CO		 3617
3618 switch (ioctl) {
3619 case KVM_SET_TSS_ADDR:
3620 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3621 break;
b927a3ce
SY		 3622 case KVM_SET_IDENTITY_MAP_ADDR: {
3623 u64 ident_addr;
3624
3625 r = -EFAULT;
3626 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3627 goto out;
3628 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3629 break;
3630 }
1fe779f8
CO		 3631 case KVM_SET_NR_MMU_PAGES:
3632 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3633 break;
3634 case KVM_GET_NR_MMU_PAGES:
3635 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3636 break;
3ddea128
MT		 3637 case KVM_CREATE_IRQCHIP: {
3638 struct kvm_pic *vpic;
3639
3640 mutex_lock(&kvm->lock);
3641 r = -EEXIST;
3642 if (kvm->arch.vpic)
3643 goto create_irqchip_unlock;
3e515705
AK		 3644 r = -EINVAL;
3645 if (atomic_read(&kvm->online_vcpus))
3646 goto create_irqchip_unlock;
1fe779f8 3647 r = -ENOMEM;
3ddea128
MT		 3648 vpic = kvm_create_pic(kvm);
3649 if (vpic) {
1fe779f8
CO		 3650 r = kvm_ioapic_init(kvm);
3651 if (r) {
175504cd 3652 mutex_lock(&kvm->slots_lock);
72bb2fcd 3653 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3654 &vpic->dev_master);
3655 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3656 &vpic->dev_slave);
3657 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3658 &vpic->dev_eclr);
175504cd 3659 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3660 kfree(vpic);
3661 goto create_irqchip_unlock;
1fe779f8
CO		 3662 }
3663 } else
3ddea128
MT		 3664 goto create_irqchip_unlock;
3665 smp_wmb();
3666 kvm->arch.vpic = vpic;
3667 smp_wmb();
399ec807
AK		 3668 r = kvm_setup_default_irq_routing(kvm);
3669 if (r) {
175504cd 3670 mutex_lock(&kvm->slots_lock);
3ddea128 3671 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3672 kvm_ioapic_destroy(kvm);
3673 kvm_destroy_pic(kvm);
3ddea128 3674 mutex_unlock(&kvm->irq_lock);
175504cd 3675 mutex_unlock(&kvm->slots_lock);
399ec807 3676 }
3ddea128
MT		 3677 create_irqchip_unlock:
3678 mutex_unlock(&kvm->lock);
1fe779f8 3679 break;
3ddea128 3680 }
7837699f 3681 case KVM_CREATE_PIT:
c5ff41ce
JK		 3682 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3683 goto create_pit;
3684 case KVM_CREATE_PIT2:
3685 r = -EFAULT;
3686 if (copy_from_user(&u.pit_config, argp,
3687 sizeof(struct kvm_pit_config)))
3688 goto out;
3689 create_pit:
79fac95e 3690 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3691 r = -EEXIST;
3692 if (kvm->arch.vpit)
3693 goto create_pit_unlock;
7837699f 3694 r = -ENOMEM;
c5ff41ce 3695 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3696 if (kvm->arch.vpit)
3697 r = 0;
269e05e4 3698 create_pit_unlock:
79fac95e 3699 mutex_unlock(&kvm->slots_lock);
7837699f 3700 break;
1fe779f8
CO		 3701 case KVM_GET_IRQCHIP: {
3702 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3703 struct kvm_irqchip *chip;
1fe779f8 3704
ff5c2c03
SL		 3705 chip = memdup_user(argp, sizeof(*chip));
3706 if (IS_ERR(chip)) {
3707 r = PTR_ERR(chip);
1fe779f8 3708 goto out;
ff5c2c03
SL		 3709 }
3710
1fe779f8
CO		 3711 r = -ENXIO;
3712 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3713 goto get_irqchip_out;
3714 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3715 if (r)
f0d66275 3716 goto get_irqchip_out;
1fe779f8 3717 r = -EFAULT;
f0d66275
DH		 3718 if (copy_to_user(argp, chip, sizeof *chip))
3719 goto get_irqchip_out;
1fe779f8 3720 r = 0;
f0d66275
DH		 3721 get_irqchip_out:
3722 kfree(chip);
1fe779f8
CO		 3723 break;
3724 }
3725 case KVM_SET_IRQCHIP: {
3726 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3727 struct kvm_irqchip *chip;
1fe779f8 3728
ff5c2c03
SL		 3729 chip = memdup_user(argp, sizeof(*chip));
3730 if (IS_ERR(chip)) {
3731 r = PTR_ERR(chip);
1fe779f8 3732 goto out;
ff5c2c03
SL		 3733 }
3734
1fe779f8
CO		 3735 r = -ENXIO;
3736 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3737 goto set_irqchip_out;
3738 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3739 if (r)
f0d66275 3740 goto set_irqchip_out;
1fe779f8 3741 r = 0;
f0d66275
DH		 3742 set_irqchip_out:
3743 kfree(chip);
1fe779f8
CO		 3744 break;
3745 }
e0f63cb9 3746 case KVM_GET_PIT: {
e0f63cb9 3747 r = -EFAULT;
f0d66275 3748 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3749 goto out;
3750 r = -ENXIO;
3751 if (!kvm->arch.vpit)
3752 goto out;
f0d66275 3753 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3754 if (r)
3755 goto out;
3756 r = -EFAULT;
f0d66275 3757 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3758 goto out;
3759 r = 0;
3760 break;
3761 }
3762 case KVM_SET_PIT: {
e0f63cb9 3763 r = -EFAULT;
f0d66275 3764 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3765 goto out;
3766 r = -ENXIO;
3767 if (!kvm->arch.vpit)
3768 goto out;
f0d66275 3769 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3770 break;
3771 }
e9f42757
BK		 3772 case KVM_GET_PIT2: {
3773 r = -ENXIO;
3774 if (!kvm->arch.vpit)
3775 goto out;
3776 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3777 if (r)
3778 goto out;
3779 r = -EFAULT;
3780 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3781 goto out;
3782 r = 0;
3783 break;
3784 }
3785 case KVM_SET_PIT2: {
3786 r = -EFAULT;
3787 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3788 goto out;
3789 r = -ENXIO;
3790 if (!kvm->arch.vpit)
3791 goto out;
3792 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3793 break;
3794 }
52d939a0
MT		 3795 case KVM_REINJECT_CONTROL: {
3796 struct kvm_reinject_control control;
3797 r = -EFAULT;
3798 if (copy_from_user(&control, argp, sizeof(control)))
3799 goto out;
3800 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3801 break;
3802 }
ffde22ac
ES		 3803 case KVM_XEN_HVM_CONFIG: {
3804 r = -EFAULT;
3805 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3806 sizeof(struct kvm_xen_hvm_config)))
3807 goto out;
3808 r = -EINVAL;
3809 if (kvm->arch.xen_hvm_config.flags)
3810 goto out;
3811 r = 0;
3812 break;
3813 }
afbcf7ab 3814 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3815 struct kvm_clock_data user_ns;
3816 u64 now_ns;
3817 s64 delta;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3821 goto out;
3822
3823 r = -EINVAL;
3824 if (user_ns.flags)
3825 goto out;
3826
3827 r = 0;
395c6b0a 3828 local_irq_disable();
759379dd 3829 now_ns = get_kernel_ns();
afbcf7ab 3830 delta = user_ns.clock - now_ns;
395c6b0a 3831 local_irq_enable();
afbcf7ab 3832 kvm->arch.kvmclock_offset = delta;
2e762ff7 3833 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3834 break;
3835 }
3836 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3837 struct kvm_clock_data user_ns;
3838 u64 now_ns;
3839
395c6b0a 3840 local_irq_disable();
759379dd 3841 now_ns = get_kernel_ns();
afbcf7ab 3842 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3843 local_irq_enable();
afbcf7ab 3844 user_ns.flags = 0;
97e69aa6 3845 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3846
3847 r = -EFAULT;
3848 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3849 goto out;
3850 r = 0;
3851 break;
3852 }
3853
1fe779f8
CO		 3854 default:
3855 ;
3856 }
3857out:
3858 return r;
3859}
3860
a16b043c 3861static void kvm_init_msr_list(void)
043405e1
CO		 3862{
3863 u32 dummy[2];
3864 unsigned i, j;
3865
e3267cbb
GC		 3866 /* skip the first msrs in the list. KVM-specific */
3867 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3868 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3869 continue;
3870 if (j < i)
3871 msrs_to_save[j] = msrs_to_save[i];
3872 j++;
3873 }
3874 num_msrs_to_save = j;
3875}
3876
bda9020e
MT		 3877static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3878 const void *v)
bbd9b64e 3879{
70252a10
AK		 3880 int handled = 0;
3881 int n;
3882
3883 do {
3884 n = min(len, 8);
3885 if (!(vcpu->arch.apic &&
3886 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3887 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3888 break;
3889 handled += n;
3890 addr += n;
3891 len -= n;
3892 v += n;
3893 } while (len);
bbd9b64e 3894
70252a10 3895 return handled;
bbd9b64e
CO		 3896}
3897
bda9020e 3898static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3899{
70252a10
AK		 3900 int handled = 0;
3901 int n;
3902
3903 do {
3904 n = min(len, 8);
3905 if (!(vcpu->arch.apic &&
3906 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3907 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3908 break;
3909 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3910 handled += n;
3911 addr += n;
3912 len -= n;
3913 v += n;
3914 } while (len);
bbd9b64e 3915
70252a10 3916 return handled;
bbd9b64e
CO		 3917}
3918
2dafc6c2
GN		 3919static void kvm_set_segment(struct kvm_vcpu *vcpu,
3920 struct kvm_segment *var, int seg)
3921{
3922 kvm_x86_ops->set_segment(vcpu, var, seg);
3923}
3924
3925void kvm_get_segment(struct kvm_vcpu *vcpu,
3926 struct kvm_segment *var, int seg)
3927{
3928 kvm_x86_ops->get_segment(vcpu, var, seg);
3929}
3930
e459e322 3931gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3932{
3933 gpa_t t_gpa;
ab9ae313 3934 struct x86_exception exception;
02f59dc9
JR		 3935
3936 BUG_ON(!mmu_is_nested(vcpu));
3937
3938 /* NPT walks are always user-walks */
3939 access |= PFERR_USER_MASK;
ab9ae313 3940 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3941
3942 return t_gpa;
3943}
3944
ab9ae313
AK		 3945gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3946 struct x86_exception *exception)
1871c602
GN		 3947{
3948 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3949 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3950}
3951
ab9ae313
AK		 3952 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3953 struct x86_exception *exception)
1871c602
GN		 3954{
3955 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3956 access |= PFERR_FETCH_MASK;
ab9ae313 3957 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3958}
3959
ab9ae313
AK		 3960gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3961 struct x86_exception *exception)
1871c602
GN		 3962{
3963 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3964 access |= PFERR_WRITE_MASK;
ab9ae313 3965 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3966}
3967
3968/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3969gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3970 struct x86_exception *exception)
1871c602 3971{
ab9ae313 3972 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3973}
3974
3975static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3976 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3977 struct x86_exception *exception)
bbd9b64e
CO		 3978{
3979 void *data = val;
10589a46 3980 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3981
3982 while (bytes) {
14dfe855 3983 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3984 exception);
bbd9b64e 3985 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3986 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3987 int ret;
3988
bcc55cba 3989 if (gpa == UNMAPPED_GVA)
ab9ae313 3990 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3991 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3992 if (ret < 0) {
c3cd7ffa 3993 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3994 goto out;
3995 }
bbd9b64e 3996
77c2002e
IE		 3997 bytes -= toread;
3998 data += toread;
3999 addr += toread;
bbd9b64e 4000 }
10589a46 4001out:
10589a46 4002 return r;
bbd9b64e 4003}
77c2002e 4004
1871c602 4005/* used for instruction fetching */
0f65dd70
AK		 4006static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4007 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4008 struct x86_exception *exception)
1871c602 4009{
0f65dd70 4010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4011 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4012
1871c602 4013 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4014 access | PFERR_FETCH_MASK,
4015 exception);
1871c602
GN		 4016}
4017
064aea77 4018int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4019 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4020 struct x86_exception *exception)
1871c602 4021{
0f65dd70 4022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4023 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4024
1871c602 4025 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4026 exception);
1871c602 4027}
064aea77 4028EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4029
0f65dd70
AK		 4030static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4031 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4032 struct x86_exception *exception)
1871c602 4033{
0f65dd70 4034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4035 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4036}
4037
6a4d7550 4038int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4039 gva_t addr, void *val,
2dafc6c2 4040 unsigned int bytes,
bcc55cba 4041 struct x86_exception *exception)
77c2002e 4042{
0f65dd70 4043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4044 void *data = val;
4045 int r = X86EMUL_CONTINUE;
4046
4047 while (bytes) {
14dfe855
JR		 4048 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4049 PFERR_WRITE_MASK,
ab9ae313 4050 exception);
77c2002e
IE		 4051 unsigned offset = addr & (PAGE_SIZE-1);
4052 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4053 int ret;
4054
bcc55cba 4055 if (gpa == UNMAPPED_GVA)
ab9ae313 4056 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4057 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4058 if (ret < 0) {
c3cd7ffa 4059 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4060 goto out;
4061 }
4062
4063 bytes -= towrite;
4064 data += towrite;
4065 addr += towrite;
4066 }
4067out:
4068 return r;
4069}
6a4d7550 4070EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4071
af7cc7d1
XG		 4072static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4073 gpa_t *gpa, struct x86_exception *exception,
4074 bool write)
4075{
97d64b78
AK		 4076 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4077 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4078
97d64b78
AK		 4079 if (vcpu_match_mmio_gva(vcpu, gva)
4080 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4081 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4082 (gva & (PAGE_SIZE - 1));
4f022648 4083 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4084 return 1;
4085 }
4086
af7cc7d1
XG		 4087 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4088
4089 if (*gpa == UNMAPPED_GVA)
4090 return -1;
4091
4092 /* For APIC access vmexit */
4093 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4094 return 1;
4095
4f022648
XG		 4096 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4097 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4098 return 1;
4f022648 4099 }
bebb106a 4100
af7cc7d1
XG		 4101 return 0;
4102}
4103
3200f405 4104int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4105 const void *val, int bytes)
bbd9b64e
CO		 4106{
4107 int ret;
4108
4109 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4110 if (ret < 0)
bbd9b64e 4111 return 0;
f57f2ef5 4112 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4113 return 1;
4114}
4115
77d197b2
XG		 4116struct read_write_emulator_ops {
4117 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4118 int bytes);
4119 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes);
4121 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4122 int bytes, void *val);
4123 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4124 void *val, int bytes);
4125 bool write;
4126};
4127
4128static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4129{
4130 if (vcpu->mmio_read_completed) {
77d197b2 4131 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4132 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4133 vcpu->mmio_read_completed = 0;
4134 return 1;
4135 }
4136
4137 return 0;
4138}
4139
4140static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4141 void *val, int bytes)
4142{
4143 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4144}
4145
4146static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4147 void *val, int bytes)
4148{
4149 return emulator_write_phys(vcpu, gpa, val, bytes);
4150}
4151
4152static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4153{
4154 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4155 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4156}
4157
4158static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4159 void *val, int bytes)
4160{
4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4162 return X86EMUL_IO_NEEDED;
4163}
4164
4165static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4166 void *val, int bytes)
4167{
f78146b0
AK		 4168 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4169
87da7e66 4170 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4171 return X86EMUL_CONTINUE;
4172}
4173
0fbe9b0b 4174static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4175 .read_write_prepare = read_prepare,
4176 .read_write_emulate = read_emulate,
4177 .read_write_mmio = vcpu_mmio_read,
4178 .read_write_exit_mmio = read_exit_mmio,
4179};
4180
0fbe9b0b 4181static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4182 .read_write_emulate = write_emulate,
4183 .read_write_mmio = write_mmio,
4184 .read_write_exit_mmio = write_exit_mmio,
4185 .write = true,
4186};
4187
22388a3c
XG		 4188static int emulator_read_write_onepage(unsigned long addr, void *val,
4189 unsigned int bytes,
4190 struct x86_exception *exception,
4191 struct kvm_vcpu *vcpu,
0fbe9b0b 4192 const struct read_write_emulator_ops *ops)
bbd9b64e 4193{
af7cc7d1
XG		 4194 gpa_t gpa;
4195 int handled, ret;
22388a3c 4196 bool write = ops->write;
f78146b0 4197 struct kvm_mmio_fragment *frag;
10589a46 4198
22388a3c 4199 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4200
af7cc7d1 4201 if (ret < 0)
bbd9b64e 4202 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4203
4204 /* For APIC access vmexit */
af7cc7d1 4205 if (ret)
bbd9b64e
CO		 4206 goto mmio;
4207
22388a3c 4208 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4209 return X86EMUL_CONTINUE;
4210
4211mmio:
4212 /*
4213 * Is this MMIO handled locally?
4214 */
22388a3c 4215 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4216 if (handled == bytes)
bbd9b64e 4217 return X86EMUL_CONTINUE;
bbd9b64e 4218
70252a10
AK		 4219 gpa += handled;
4220 bytes -= handled;
4221 val += handled;
4222
87da7e66
XG		 4223 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4224 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4225 frag->gpa = gpa;
4226 frag->data = val;
4227 frag->len = bytes;
f78146b0 4228 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4229}
4230
22388a3c
XG		 4231int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4232 void *val, unsigned int bytes,
4233 struct x86_exception *exception,
0fbe9b0b 4234 const struct read_write_emulator_ops *ops)
bbd9b64e 4235{
0f65dd70 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4237 gpa_t gpa;
4238 int rc;
4239
4240 if (ops->read_write_prepare &&
4241 ops->read_write_prepare(vcpu, val, bytes))
4242 return X86EMUL_CONTINUE;
4243
4244 vcpu->mmio_nr_fragments = 0;
0f65dd70 4245
bbd9b64e
CO		 4246 /* Crossing a page boundary? */
4247 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4248 int now;
bbd9b64e
CO		 4249
4250 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4251 rc = emulator_read_write_onepage(addr, val, now, exception,
4252 vcpu, ops);
4253
bbd9b64e
CO		 4254 if (rc != X86EMUL_CONTINUE)
4255 return rc;
4256 addr += now;
4257 val += now;
4258 bytes -= now;
4259 }
22388a3c 4260
f78146b0
AK		 4261 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4262 vcpu, ops);
4263 if (rc != X86EMUL_CONTINUE)
4264 return rc;
4265
4266 if (!vcpu->mmio_nr_fragments)
4267 return rc;
4268
4269 gpa = vcpu->mmio_fragments[0].gpa;
4270
4271 vcpu->mmio_needed = 1;
4272 vcpu->mmio_cur_fragment = 0;
4273
87da7e66 4274 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4275 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4276 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4277 vcpu->run->mmio.phys_addr = gpa;
4278
4279 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4280}
4281
4282static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr,
4284 void *val,
4285 unsigned int bytes,
4286 struct x86_exception *exception)
4287{
4288 return emulator_read_write(ctxt, addr, val, bytes,
4289 exception, &read_emultor);
4290}
4291
4292int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4293 unsigned long addr,
4294 const void *val,
4295 unsigned int bytes,
4296 struct x86_exception *exception)
4297{
4298 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4299 exception, &write_emultor);
bbd9b64e 4300}
bbd9b64e 4301
daea3e73
AK		 4302#define CMPXCHG_TYPE(t, ptr, old, new) \
4303 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4304
4305#ifdef CONFIG_X86_64
4306# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4307#else
4308# define CMPXCHG64(ptr, old, new) \
9749a6c0 4309 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4310#endif
4311
0f65dd70
AK		 4312static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
bbd9b64e
CO		 4314 const void *old,
4315 const void *new,
4316 unsigned int bytes,
0f65dd70 4317 struct x86_exception *exception)
bbd9b64e 4318{
0f65dd70 4319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4320 gpa_t gpa;
4321 struct page *page;
4322 char *kaddr;
4323 bool exchanged;
2bacc55c 4324
daea3e73
AK		 4325 /* guests cmpxchg8b have to be emulated atomically */
4326 if (bytes > 8 || (bytes & (bytes - 1)))
4327 goto emul_write;
10589a46 4328
daea3e73 4329 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4330
daea3e73
AK		 4331 if (gpa == UNMAPPED_GVA ||
4332 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4333 goto emul_write;
2bacc55c 4334
daea3e73
AK		 4335 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4336 goto emul_write;
72dc67a6 4337
daea3e73 4338 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4339 if (is_error_page(page))
c19b8bd6 4340 goto emul_write;
72dc67a6 4341
8fd75e12 4342 kaddr = kmap_atomic(page);
daea3e73
AK		 4343 kaddr += offset_in_page(gpa);
4344 switch (bytes) {
4345 case 1:
4346 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4347 break;
4348 case 2:
4349 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4350 break;
4351 case 4:
4352 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4353 break;
4354 case 8:
4355 exchanged = CMPXCHG64(kaddr, old, new);
4356 break;
4357 default:
4358 BUG();
2bacc55c 4359 }
8fd75e12 4360 kunmap_atomic(kaddr);
daea3e73
AK		 4361 kvm_release_page_dirty(page);
4362
4363 if (!exchanged)
4364 return X86EMUL_CMPXCHG_FAILED;
4365
f57f2ef5 4366 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4367
4368 return X86EMUL_CONTINUE;
4a5f48f6 4369
3200f405 4370emul_write:
daea3e73 4371 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4372
0f65dd70 4373 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4374}
4375
cf8f70bf
GN		 4376static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4377{
4378 /* TODO: String I/O for in kernel device */
4379 int r;
4380
4381 if (vcpu->arch.pio.in)
4382 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4383 vcpu->arch.pio.size, pd);
4384 else
4385 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4386 vcpu->arch.pio.port, vcpu->arch.pio.size,
4387 pd);
4388 return r;
4389}
4390
6f6fbe98
XG		 4391static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4392 unsigned short port, void *val,
4393 unsigned int count, bool in)
cf8f70bf 4394{
6f6fbe98 4395 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4396
4397 vcpu->arch.pio.port = port;
6f6fbe98 4398 vcpu->arch.pio.in = in;
7972995b 4399 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4400 vcpu->arch.pio.size = size;
4401
4402 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4403 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4404 return 1;
4405 }
4406
4407 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4408 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4409 vcpu->run->io.size = size;
4410 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4411 vcpu->run->io.count = count;
4412 vcpu->run->io.port = port;
4413
4414 return 0;
4415}
4416
6f6fbe98
XG		 4417static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4418 int size, unsigned short port, void *val,
4419 unsigned int count)
cf8f70bf 4420{
ca1d4a9e 4421 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4422 int ret;
ca1d4a9e 4423
6f6fbe98
XG		 4424 if (vcpu->arch.pio.count)
4425 goto data_avail;
cf8f70bf 4426
6f6fbe98
XG		 4427 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4428 if (ret) {
4429data_avail:
4430 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4431 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4432 return 1;
4433 }
4434
cf8f70bf
GN		 4435 return 0;
4436}
4437
6f6fbe98
XG		 4438static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4439 int size, unsigned short port,
4440 const void *val, unsigned int count)
4441{
4442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4443
4444 memcpy(vcpu->arch.pio_data, val, size * count);
4445 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4446}
4447
bbd9b64e
CO		 4448static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4449{
4450 return kvm_x86_ops->get_segment_base(vcpu, seg);
4451}
4452
3cb16fe7 4453static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4454{
3cb16fe7 4455 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4456}
4457
f5f48ee1
SY		 4458int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4459{
4460 if (!need_emulate_wbinvd(vcpu))
4461 return X86EMUL_CONTINUE;
4462
4463 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4464 int cpu = get_cpu();
4465
4466 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4467 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4468 wbinvd_ipi, NULL, 1);
2eec7343 4469 put_cpu();
f5f48ee1 4470 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4471 } else
4472 wbinvd();
f5f48ee1
SY		 4473 return X86EMUL_CONTINUE;
4474}
4475EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4476
bcaf5cc5
AK		 4477static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4478{
4479 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4480}
4481
717746e3 4482int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4483{
717746e3 4484 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4485}
4486
717746e3 4487int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4488{
338dbc97 4489
717746e3 4490 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4491}
4492
52a46617 4493static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4494{
52a46617 4495 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4496}
4497
717746e3 4498static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4499{
717746e3 4500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4501 unsigned long value;
4502
4503 switch (cr) {
4504 case 0:
4505 value = kvm_read_cr0(vcpu);
4506 break;
4507 case 2:
4508 value = vcpu->arch.cr2;
4509 break;
4510 case 3:
9f8fe504 4511 value = kvm_read_cr3(vcpu);
52a46617
GN		 4512 break;
4513 case 4:
4514 value = kvm_read_cr4(vcpu);
4515 break;
4516 case 8:
4517 value = kvm_get_cr8(vcpu);
4518 break;
4519 default:
a737f256 4520 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4521 return 0;
4522 }
4523
4524 return value;
4525}
4526
717746e3 4527static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4528{
717746e3 4529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4530 int res = 0;
4531
52a46617
GN		 4532 switch (cr) {
4533 case 0:
49a9b07e 4534 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4535 break;
4536 case 2:
4537 vcpu->arch.cr2 = val;
4538 break;
4539 case 3:
2390218b 4540 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4541 break;
4542 case 4:
a83b29c6 4543 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4544 break;
4545 case 8:
eea1cff9 4546 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4547 break;
4548 default:
a737f256 4549 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4550 res = -1;
52a46617 4551 }
0f12244f
GN		 4552
4553 return res;
52a46617
GN		 4554}
4555
4cee4798
KW		 4556static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4557{
4558 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4559}
4560
717746e3 4561static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4562{
717746e3 4563 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4564}
4565
4bff1e86 4566static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4567{
4bff1e86 4568 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4569}
4570
4bff1e86 4571static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4572{
4bff1e86 4573 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4574}
4575
1ac9d0cf
AK		 4576static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4577{
4578 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4579}
4580
4581static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4582{
4583 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4584}
4585
4bff1e86
AK		 4586static unsigned long emulator_get_cached_segment_base(
4587 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4588{
4bff1e86 4589 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4590}
4591
1aa36616
AK		 4592static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4593 struct desc_struct *desc, u32 *base3,
4594 int seg)
2dafc6c2
GN		 4595{
4596 struct kvm_segment var;
4597
4bff1e86 4598 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4599 *selector = var.selector;
2dafc6c2 4600
378a8b09
GN		 4601 if (var.unusable) {
4602 memset(desc, 0, sizeof(*desc));
2dafc6c2 4603 return false;
378a8b09 4604 }
2dafc6c2
GN		 4605
4606 if (var.g)
4607 var.limit >>= 12;
4608 set_desc_limit(desc, var.limit);
4609 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4610#ifdef CONFIG_X86_64
4611 if (base3)
4612 *base3 = var.base >> 32;
4613#endif
2dafc6c2
GN		 4614 desc->type = var.type;
4615 desc->s = var.s;
4616 desc->dpl = var.dpl;
4617 desc->p = var.present;
4618 desc->avl = var.avl;
4619 desc->l = var.l;
4620 desc->d = var.db;
4621 desc->g = var.g;
4622
4623 return true;
4624}
4625
1aa36616
AK		 4626static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4627 struct desc_struct *desc, u32 base3,
4628 int seg)
2dafc6c2 4629{
4bff1e86 4630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4631 struct kvm_segment var;
4632
1aa36616 4633 var.selector = selector;
2dafc6c2 4634 var.base = get_desc_base(desc);
5601d05b
GN		 4635#ifdef CONFIG_X86_64
4636 var.base |= ((u64)base3) << 32;
4637#endif
2dafc6c2
GN		 4638 var.limit = get_desc_limit(desc);
4639 if (desc->g)
4640 var.limit = (var.limit << 12) | 0xfff;
4641 var.type = desc->type;
4642 var.present = desc->p;
4643 var.dpl = desc->dpl;
4644 var.db = desc->d;
4645 var.s = desc->s;
4646 var.l = desc->l;
4647 var.g = desc->g;
4648 var.avl = desc->avl;
4649 var.present = desc->p;
4650 var.unusable = !var.present;
4651 var.padding = 0;
4652
4653 kvm_set_segment(vcpu, &var, seg);
4654 return;
4655}
4656
717746e3
AK		 4657static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4658 u32 msr_index, u64 *pdata)
4659{
4660 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4661}
4662
4663static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4664 u32 msr_index, u64 data)
4665{
8fe8ab46
WA		 4666 struct msr_data msr;
4667
4668 msr.data = data;
4669 msr.index = msr_index;
4670 msr.host_initiated = false;
4671 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4672}
4673
222d21aa
AK		 4674static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4675 u32 pmc, u64 *pdata)
4676{
4677 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4678}
4679
6c3287f7
AK		 4680static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4681{
4682 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4683}
4684
5037f6f3
AK		 4685static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4686{
4687 preempt_disable();
5197b808 4688 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4689 /*
4690 * CR0.TS may reference the host fpu state, not the guest fpu state,
4691 * so it may be clear at this point.
4692 */
4693 clts();
4694}
4695
4696static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4697{
4698 preempt_enable();
4699}
4700
2953538e 4701static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4702 struct x86_instruction_info *info,
c4f035c6
AK		 4703 enum x86_intercept_stage stage)
4704{
2953538e 4705 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4706}
4707
0017f93a 4708static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4709 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4710{
0017f93a 4711 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4712}
4713
dd856efa
AK		 4714static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4715{
4716 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4717}
4718
4719static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4720{
4721 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4722}
4723
0225fb50 4724static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4725 .read_gpr = emulator_read_gpr,
4726 .write_gpr = emulator_write_gpr,
1871c602 4727 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4728 .write_std = kvm_write_guest_virt_system,
1871c602 4729 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4730 .read_emulated = emulator_read_emulated,
4731 .write_emulated = emulator_write_emulated,
4732 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4733 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4734 .pio_in_emulated = emulator_pio_in_emulated,
4735 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4736 .get_segment = emulator_get_segment,
4737 .set_segment = emulator_set_segment,
5951c442 4738 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4739 .get_gdt = emulator_get_gdt,
160ce1f1 4740 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4741 .set_gdt = emulator_set_gdt,
4742 .set_idt = emulator_set_idt,
52a46617
GN		 4743 .get_cr = emulator_get_cr,
4744 .set_cr = emulator_set_cr,
4cee4798 4745 .set_rflags = emulator_set_rflags,
9c537244 4746 .cpl = emulator_get_cpl,
35aa5375
GN		 4747 .get_dr = emulator_get_dr,
4748 .set_dr = emulator_set_dr,
717746e3
AK		 4749 .set_msr = emulator_set_msr,
4750 .get_msr = emulator_get_msr,
222d21aa 4751 .read_pmc = emulator_read_pmc,
6c3287f7 4752 .halt = emulator_halt,
bcaf5cc5 4753 .wbinvd = emulator_wbinvd,
d6aa1000 4754 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4755 .get_fpu = emulator_get_fpu,
4756 .put_fpu = emulator_put_fpu,
c4f035c6 4757 .intercept = emulator_intercept,
bdb42f5a 4758 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4759};
4760
95cb2295
GN		 4761static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4762{
4763 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4764 /*
4765 * an sti; sti; sequence only disable interrupts for the first
4766 * instruction. So, if the last instruction, be it emulated or
4767 * not, left the system with the INT_STI flag enabled, it
4768 * means that the last instruction is an sti. We should not
4769 * leave the flag on in this case. The same goes for mov ss
4770 */
4771 if (!(int_shadow & mask))
4772 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4773}
4774
54b8486f
GN		 4775static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4776{
4777 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4778 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4779 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4780 else if (ctxt->exception.error_code_valid)
4781 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4782 ctxt->exception.error_code);
54b8486f 4783 else
da9cb575 4784 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4785}
4786
dd856efa 4787static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4788{
1ce19dc1
BP		 4789 memset(&ctxt->opcode_len, 0,
4790 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4791
9dac77fa
AK		 4792 ctxt->fetch.start = 0;
4793 ctxt->fetch.end = 0;
4794 ctxt->io_read.pos = 0;
4795 ctxt->io_read.end = 0;
4796 ctxt->mem_read.pos = 0;
4797 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4798}
4799
8ec4722d
MG		 4800static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4801{
adf52235 4802 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4803 int cs_db, cs_l;
4804
8ec4722d
MG		 4805 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4806
adf52235
TY		 4807 ctxt->eflags = kvm_get_rflags(vcpu);
4808 ctxt->eip = kvm_rip_read(vcpu);
4809 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4810 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4811 cs_l ? X86EMUL_MODE_PROT64 :
4812 cs_db ? X86EMUL_MODE_PROT32 :
4813 X86EMUL_MODE_PROT16;
4814 ctxt->guest_mode = is_guest_mode(vcpu);
4815
dd856efa 4816 init_decode_cache(ctxt);
7ae441ea 4817 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4818}
4819
71f9833b 4820int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4821{
9d74191a 4822 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4823 int ret;
4824
4825 init_emulate_ctxt(vcpu);
4826
9dac77fa
AK		 4827 ctxt->op_bytes = 2;
4828 ctxt->ad_bytes = 2;
4829 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4830 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4831
4832 if (ret != X86EMUL_CONTINUE)
4833 return EMULATE_FAIL;
4834
9dac77fa 4835 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4836 kvm_rip_write(vcpu, ctxt->eip);
4837 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4838
4839 if (irq == NMI_VECTOR)
7460fb4a 4840 vcpu->arch.nmi_pending = 0;
63995653
MG		 4841 else
4842 vcpu->arch.interrupt.pending = false;
4843
4844 return EMULATE_DONE;
4845}
4846EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4847
6d77dbfc
GN		 4848static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4849{
fc3a9157
JR		 4850 int r = EMULATE_DONE;
4851
6d77dbfc
GN		 4852 ++vcpu->stat.insn_emulation_fail;
4853 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4854 if (!is_guest_mode(vcpu)) {
4855 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4856 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4857 vcpu->run->internal.ndata = 0;
4858 r = EMULATE_FAIL;
4859 }
6d77dbfc 4860 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4861
4862 return r;
6d77dbfc
GN		 4863}
4864
93c05d3e 4865static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4866 bool write_fault_to_shadow_pgtable,
4867 int emulation_type)
a6f177ef 4868{
95b3cf69 4869 gpa_t gpa = cr2;
8e3d9d06 4870 pfn_t pfn;
a6f177ef 4871
991eebf9
GN		 4872 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4873 return false;
4874
95b3cf69
XG		 4875 if (!vcpu->arch.mmu.direct_map) {
4876 /*
4877 * Write permission should be allowed since only
4878 * write access need to be emulated.
4879 */
4880 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4881
95b3cf69
XG		 4882 /*
4883 * If the mapping is invalid in guest, let cpu retry
4884 * it to generate fault.
4885 */
4886 if (gpa == UNMAPPED_GVA)
4887 return true;
4888 }
a6f177ef 4889
8e3d9d06
XG		 4890 /*
4891 * Do not retry the unhandleable instruction if it faults on the
4892 * readonly host memory, otherwise it will goto a infinite loop:
4893 * retry instruction -> write #PF -> emulation fail -> retry
4894 * instruction -> ...
4895 */
4896 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4897
4898 /*
4899 * If the instruction failed on the error pfn, it can not be fixed,
4900 * report the error to userspace.
4901 */
4902 if (is_error_noslot_pfn(pfn))
4903 return false;
4904
4905 kvm_release_pfn_clean(pfn);
4906
4907 /* The instructions are well-emulated on direct mmu. */
4908 if (vcpu->arch.mmu.direct_map) {
4909 unsigned int indirect_shadow_pages;
4910
4911 spin_lock(&vcpu->kvm->mmu_lock);
4912 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4913 spin_unlock(&vcpu->kvm->mmu_lock);
4914
4915 if (indirect_shadow_pages)
4916 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4917
a6f177ef 4918 return true;
8e3d9d06 4919 }
a6f177ef 4920
95b3cf69
XG		 4921 /*
4922 * if emulation was due to access to shadowed page table
4923 * and it failed try to unshadow page and re-enter the
4924 * guest to let CPU execute the instruction.
4925 */
4926 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4927
4928 /*
4929 * If the access faults on its page table, it can not
4930 * be fixed by unprotecting shadow page and it should
4931 * be reported to userspace.
4932 */
4933 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4934}
4935
1cb3f3ae
XG		 4936static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4937 unsigned long cr2, int emulation_type)
4938{
4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4940 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4941
4942 last_retry_eip = vcpu->arch.last_retry_eip;
4943 last_retry_addr = vcpu->arch.last_retry_addr;
4944
4945 /*
4946 * If the emulation is caused by #PF and it is non-page_table
4947 * writing instruction, it means the VM-EXIT is caused by shadow
4948 * page protected, we can zap the shadow page and retry this
4949 * instruction directly.
4950 *
4951 * Note: if the guest uses a non-page-table modifying instruction
4952 * on the PDE that points to the instruction, then we will unmap
4953 * the instruction and go to an infinite loop. So, we cache the
4954 * last retried eip and the last fault address, if we meet the eip
4955 * and the address again, we can break out of the potential infinite
4956 * loop.
4957 */
4958 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4959
4960 if (!(emulation_type & EMULTYPE_RETRY))
4961 return false;
4962
4963 if (x86_page_table_writing_insn(ctxt))
4964 return false;
4965
4966 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4967 return false;
4968
4969 vcpu->arch.last_retry_eip = ctxt->eip;
4970 vcpu->arch.last_retry_addr = cr2;
4971
4972 if (!vcpu->arch.mmu.direct_map)
4973 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4974
22368028 4975 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4976
4977 return true;
4978}
4979
716d51ab
GN		 4980static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4981static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4982
4a1e10d5
PB		 4983static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4984 unsigned long *db)
4985{
4986 u32 dr6 = 0;
4987 int i;
4988 u32 enable, rwlen;
4989
4990 enable = dr7;
4991 rwlen = dr7 >> 16;
4992 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4993 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4994 dr6 |= (1 << i);
4995 return dr6;
4996}
4997
663f4c61
PB		 4998static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4999{
5000 struct kvm_run *kvm_run = vcpu->run;
5001
5002 /*
5003 * Use the "raw" value to see if TF was passed to the processor.
5004 * Note that the new value of the flags has not been saved yet.
5005 *
5006 * This is correct even for TF set by the guest, because "the
5007 * processor will not generate this exception after the instruction
5008 * that sets the TF flag".
5009 */
5010 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5011
5012 if (unlikely(rflags & X86_EFLAGS_TF)) {
5013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5014 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5015 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5016 kvm_run->debug.arch.exception = DB_VECTOR;
5017 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5018 *r = EMULATE_USER_EXIT;
5019 } else {
5020 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5021 /*
5022 * "Certain debug exceptions may clear bit 0-3. The
5023 * remaining contents of the DR6 register are never
5024 * cleared by the processor".
5025 */
5026 vcpu->arch.dr6 &= ~15;
5027 vcpu->arch.dr6 |= DR6_BS;
5028 kvm_queue_exception(vcpu, DB_VECTOR);
5029 }
5030 }
5031}
5032
4a1e10d5
PB		 5033static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5034{
5035 struct kvm_run *kvm_run = vcpu->run;
5036 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5037 u32 dr6 = 0;
5038
5039 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5040 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5041 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5042 vcpu->arch.guest_debug_dr7,
5043 vcpu->arch.eff_db);
5044
5045 if (dr6 != 0) {
5046 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5047 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5048 get_segment_base(vcpu, VCPU_SREG_CS);
5049
5050 kvm_run->debug.arch.exception = DB_VECTOR;
5051 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5052 *r = EMULATE_USER_EXIT;
5053 return true;
5054 }
5055 }
5056
5057 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5058 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5059 vcpu->arch.dr7,
5060 vcpu->arch.db);
5061
5062 if (dr6 != 0) {
5063 vcpu->arch.dr6 &= ~15;
5064 vcpu->arch.dr6 |= dr6;
5065 kvm_queue_exception(vcpu, DB_VECTOR);
5066 *r = EMULATE_DONE;
5067 return true;
5068 }
5069 }
5070
5071 return false;
5072}
5073
51d8b661
AP		 5074int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5075 unsigned long cr2,
dc25e89e
AP		 5076 int emulation_type,
5077 void *insn,
5078 int insn_len)
bbd9b64e 5079{
95cb2295 5080 int r;
9d74191a 5081 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5082 bool writeback = true;
93c05d3e 5083 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5084
93c05d3e
XG		 5085 /*
5086 * Clear write_fault_to_shadow_pgtable here to ensure it is
5087 * never reused.
5088 */
5089 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5090 kvm_clear_exception_queue(vcpu);
8d7d8102 5091
571008da 5092 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5093 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5094
5095 /*
5096 * We will reenter on the same instruction since
5097 * we do not set complete_userspace_io. This does not
5098 * handle watchpoints yet, those would be handled in
5099 * the emulate_ops.
5100 */
5101 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5102 return r;
5103
9d74191a
TY		 5104 ctxt->interruptibility = 0;
5105 ctxt->have_exception = false;
5106 ctxt->perm_ok = false;
bbd9b64e 5107
b51e974f 5108 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5109
9d74191a 5110 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5111
e46479f8 5112 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5113 ++vcpu->stat.insn_emulation;
1d2887e2 5114 if (r != EMULATION_OK) {
4005996e
AK		 5115 if (emulation_type & EMULTYPE_TRAP_UD)
5116 return EMULATE_FAIL;
991eebf9
GN		 5117 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5118 emulation_type))
bbd9b64e 5119 return EMULATE_DONE;
6d77dbfc
GN		 5120 if (emulation_type & EMULTYPE_SKIP)
5121 return EMULATE_FAIL;
5122 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5123 }
5124 }
5125
ba8afb6b 5126 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5127 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5128 return EMULATE_DONE;
5129 }
5130
1cb3f3ae
XG		 5131 if (retry_instruction(ctxt, cr2, emulation_type))
5132 return EMULATE_DONE;
5133
7ae441ea 5134 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5135 changes registers values during IO operation */
7ae441ea
GN		 5136 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5137 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5138 emulator_invalidate_register_cache(ctxt);
7ae441ea 5139 }
4d2179e1 5140
5cd21917 5141restart:
9d74191a 5142 r = x86_emulate_insn(ctxt);
bbd9b64e 5143
775fde86
JR		 5144 if (r == EMULATION_INTERCEPTED)
5145 return EMULATE_DONE;
5146
d2ddd1c4 5147 if (r == EMULATION_FAILED) {
991eebf9
GN		 5148 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5149 emulation_type))
c3cd7ffa
GN		 5150 return EMULATE_DONE;
5151
6d77dbfc 5152 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5153 }
5154
9d74191a 5155 if (ctxt->have_exception) {
54b8486f 5156 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5157 r = EMULATE_DONE;
5158 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5159 if (!vcpu->arch.pio.in) {
5160 /* FIXME: return into emulator if single-stepping. */
3457e419 5161 vcpu->arch.pio.count = 0;
0912c977 5162 } else {
7ae441ea 5163 writeback = false;
716d51ab
GN		 5164 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5165 }
ac0a48c3 5166 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5167 } else if (vcpu->mmio_needed) {
5168 if (!vcpu->mmio_is_write)
5169 writeback = false;
ac0a48c3 5170 r = EMULATE_USER_EXIT;
716d51ab 5171 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5172 } else if (r == EMULATION_RESTART)
5cd21917 5173 goto restart;
d2ddd1c4
GN		 5174 else
5175 r = EMULATE_DONE;
f850e2e6 5176
7ae441ea 5177 if (writeback) {
9d74191a 5178 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5179 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5180 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5181 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5182 if (r == EMULATE_DONE)
5183 kvm_vcpu_check_singlestep(vcpu, &r);
5184 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5185 } else
5186 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5187
5188 return r;
de7d789a 5189}
51d8b661 5190EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5191
cf8f70bf 5192int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5193{
cf8f70bf 5194 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5195 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5196 size, port, &val, 1);
cf8f70bf 5197 /* do not return to emulator after return from userspace */
7972995b 5198 vcpu->arch.pio.count = 0;
de7d789a
CO		 5199 return ret;
5200}
cf8f70bf 5201EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5202
8cfdc000
ZA		 5203static void tsc_bad(void *info)
5204{
0a3aee0d 5205 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5206}
5207
5208static void tsc_khz_changed(void *data)
c8076604 5209{
8cfdc000
ZA		 5210 struct cpufreq_freqs *freq = data;
5211 unsigned long khz = 0;
5212
5213 if (data)
5214 khz = freq->new;
5215 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5216 khz = cpufreq_quick_get(raw_smp_processor_id());
5217 if (!khz)
5218 khz = tsc_khz;
0a3aee0d 5219 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5220}
5221
c8076604
GH		 5222static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5223 void *data)
5224{
5225 struct cpufreq_freqs *freq = data;
5226 struct kvm *kvm;
5227 struct kvm_vcpu *vcpu;
5228 int i, send_ipi = 0;
5229
8cfdc000
ZA		 5230 /*
5231 * We allow guests to temporarily run on slowing clocks,
5232 * provided we notify them after, or to run on accelerating
5233 * clocks, provided we notify them before. Thus time never
5234 * goes backwards.
5235 *
5236 * However, we have a problem. We can't atomically update
5237 * the frequency of a given CPU from this function; it is
5238 * merely a notifier, which can be called from any CPU.
5239 * Changing the TSC frequency at arbitrary points in time
5240 * requires a recomputation of local variables related to
5241 * the TSC for each VCPU. We must flag these local variables
5242 * to be updated and be sure the update takes place with the
5243 * new frequency before any guests proceed.
5244 *
5245 * Unfortunately, the combination of hotplug CPU and frequency
5246 * change creates an intractable locking scenario; the order
5247 * of when these callouts happen is undefined with respect to
5248 * CPU hotplug, and they can race with each other. As such,
5249 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5250 * undefined; you can actually have a CPU frequency change take
5251 * place in between the computation of X and the setting of the
5252 * variable. To protect against this problem, all updates of
5253 * the per_cpu tsc_khz variable are done in an interrupt
5254 * protected IPI, and all callers wishing to update the value
5255 * must wait for a synchronous IPI to complete (which is trivial
5256 * if the caller is on the CPU already). This establishes the
5257 * necessary total order on variable updates.
5258 *
5259 * Note that because a guest time update may take place
5260 * anytime after the setting of the VCPU's request bit, the
5261 * correct TSC value must be set before the request. However,
5262 * to ensure the update actually makes it to any guest which
5263 * starts running in hardware virtualization between the set
5264 * and the acquisition of the spinlock, we must also ping the
5265 * CPU after setting the request bit.
5266 *
5267 */
5268
c8076604
GH		 5269 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5270 return 0;
5271 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5272 return 0;
8cfdc000
ZA		 5273
5274 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5275
2f303b74 5276 spin_lock(&kvm_lock);
c8076604 5277 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5278 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5279 if (vcpu->cpu != freq->cpu)
5280 continue;
c285545f 5281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5282 if (vcpu->cpu != smp_processor_id())
8cfdc000 5283 send_ipi = 1;
c8076604
GH		 5284 }
5285 }
2f303b74 5286 spin_unlock(&kvm_lock);
c8076604
GH		 5287
5288 if (freq->old < freq->new && send_ipi) {
5289 /*
5290 * We upscale the frequency. Must make the guest
5291 * doesn't see old kvmclock values while running with
5292 * the new frequency, otherwise we risk the guest sees
5293 * time go backwards.
5294 *
5295 * In case we update the frequency for another cpu
5296 * (which might be in guest context) send an interrupt
5297 * to kick the cpu out of guest context. Next time
5298 * guest context is entered kvmclock will be updated,
5299 * so the guest will not see stale values.
5300 */
8cfdc000 5301 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5302 }
5303 return 0;
5304}
5305
5306static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5307 .notifier_call = kvmclock_cpufreq_notifier
5308};
5309
5310static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5311 unsigned long action, void *hcpu)
5312{
5313 unsigned int cpu = (unsigned long)hcpu;
5314
5315 switch (action) {
5316 case CPU_ONLINE:
5317 case CPU_DOWN_FAILED:
5318 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5319 break;
5320 case CPU_DOWN_PREPARE:
5321 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5322 break;
5323 }
5324 return NOTIFY_OK;
5325}
5326
5327static struct notifier_block kvmclock_cpu_notifier_block = {
5328 .notifier_call = kvmclock_cpu_notifier,
5329 .priority = -INT_MAX
c8076604
GH		 5330};
5331
b820cc0c
ZA		 5332static void kvm_timer_init(void)
5333{
5334 int cpu;
5335
c285545f 5336 max_tsc_khz = tsc_khz;
8cfdc000 5337 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5338 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5339#ifdef CONFIG_CPU_FREQ
5340 struct cpufreq_policy policy;
5341 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5342 cpu = get_cpu();
5343 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5344 if (policy.cpuinfo.max_freq)
5345 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5346 put_cpu();
c285545f 5347#endif
b820cc0c
ZA		 5348 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5349 CPUFREQ_TRANSITION_NOTIFIER);
5350 }
c285545f 5351 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5352 for_each_online_cpu(cpu)
5353 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5354}
5355
ff9d07a0
ZY		 5356static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5357
f5132b01 5358int kvm_is_in_guest(void)
ff9d07a0 5359{
086c9855 5360 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5361}
5362
5363static int kvm_is_user_mode(void)
5364{
5365 int user_mode = 3;
dcf46b94 5366
086c9855
AS		 5367 if (__this_cpu_read(current_vcpu))
5368 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5369
ff9d07a0
ZY		 5370 return user_mode != 0;
5371}
5372
5373static unsigned long kvm_get_guest_ip(void)
5374{
5375 unsigned long ip = 0;
dcf46b94 5376
086c9855
AS		 5377 if (__this_cpu_read(current_vcpu))
5378 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5379
ff9d07a0
ZY		 5380 return ip;
5381}
5382
5383static struct perf_guest_info_callbacks kvm_guest_cbs = {
5384 .is_in_guest = kvm_is_in_guest,
5385 .is_user_mode = kvm_is_user_mode,
5386 .get_guest_ip = kvm_get_guest_ip,
5387};
5388
5389void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5390{
086c9855 5391 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5392}
5393EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5394
5395void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5396{
086c9855 5397 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5398}
5399EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5400
ce88decf
XG		 5401static void kvm_set_mmio_spte_mask(void)
5402{
5403 u64 mask;
5404 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5405
5406 /*
5407 * Set the reserved bits and the present bit of an paging-structure
5408 * entry to generate page fault with PFER.RSV = 1.
5409 */
885032b9
XG		 5410 /* Mask the reserved physical address bits. */
5411 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5412
5413 /* Bit 62 is always reserved for 32bit host. */
5414 mask |= 0x3ull << 62;
5415
5416 /* Set the present bit. */
ce88decf
XG		 5417 mask |= 1ull;
5418
5419#ifdef CONFIG_X86_64
5420 /*
5421 * If reserved bit is not supported, clear the present bit to disable
5422 * mmio page fault.
5423 */
5424 if (maxphyaddr == 52)
5425 mask &= ~1ull;
5426#endif
5427
5428 kvm_mmu_set_mmio_spte_mask(mask);
5429}
5430
16e8d74d
MT		 5431#ifdef CONFIG_X86_64
5432static void pvclock_gtod_update_fn(struct work_struct *work)
5433{
d828199e
MT		 5434 struct kvm *kvm;
5435
5436 struct kvm_vcpu *vcpu;
5437 int i;
5438
2f303b74 5439 spin_lock(&kvm_lock);
d828199e
MT		 5440 list_for_each_entry(kvm, &vm_list, vm_list)
5441 kvm_for_each_vcpu(i, vcpu, kvm)
5442 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5443 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5444 spin_unlock(&kvm_lock);
16e8d74d
MT		 5445}
5446
5447static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5448
5449/*
5450 * Notification about pvclock gtod data update.
5451 */
5452static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5453 void *priv)
5454{
5455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5456 struct timekeeper *tk = priv;
5457
5458 update_pvclock_gtod(tk);
5459
5460 /* disable master clock if host does not trust, or does not
5461 * use, TSC clocksource
5462 */
5463 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5464 atomic_read(&kvm_guest_has_master_clock) != 0)
5465 queue_work(system_long_wq, &pvclock_gtod_work);
5466
5467 return 0;
5468}
5469
5470static struct notifier_block pvclock_gtod_notifier = {
5471 .notifier_call = pvclock_gtod_notify,
5472};
5473#endif
5474
f8c16bba 5475int kvm_arch_init(void *opaque)
043405e1 5476{
b820cc0c 5477 int r;
6b61edf7 5478 struct kvm_x86_ops *ops = opaque;
f8c16bba 5479
f8c16bba
ZX		 5480 if (kvm_x86_ops) {
5481 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5482 r = -EEXIST;
5483 goto out;
f8c16bba
ZX		 5484 }
5485
5486 if (!ops->cpu_has_kvm_support()) {
5487 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5488 r = -EOPNOTSUPP;
5489 goto out;
f8c16bba
ZX		 5490 }
5491 if (ops->disabled_by_bios()) {
5492 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5493 r = -EOPNOTSUPP;
5494 goto out;
f8c16bba
ZX		 5495 }
5496
013f6a5d
MT		 5497 r = -ENOMEM;
5498 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5499 if (!shared_msrs) {
5500 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5501 goto out;
5502 }
5503
97db56ce
AK		 5504 r = kvm_mmu_module_init();
5505 if (r)
013f6a5d 5506 goto out_free_percpu;
97db56ce 5507
ce88decf 5508 kvm_set_mmio_spte_mask();
97db56ce
AK		 5509 kvm_init_msr_list();
5510
f8c16bba 5511 kvm_x86_ops = ops;
7b52345e 5512 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5513 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5514
b820cc0c 5515 kvm_timer_init();
c8076604 5516
ff9d07a0
ZY		 5517 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5518
2acf923e
DC		 5519 if (cpu_has_xsave)
5520 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5521
c5cc421b 5522 kvm_lapic_init();
16e8d74d
MT		 5523#ifdef CONFIG_X86_64
5524 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5525#endif
5526
f8c16bba 5527 return 0;
56c6d28a 5528
013f6a5d
MT		 5529out_free_percpu:
5530 free_percpu(shared_msrs);
56c6d28a 5531out:
56c6d28a 5532 return r;
043405e1 5533}
8776e519 5534
f8c16bba
ZX		 5535void kvm_arch_exit(void)
5536{
ff9d07a0
ZY		 5537 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5538
888d256e
JK		 5539 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5540 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5541 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5542 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5543#ifdef CONFIG_X86_64
5544 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5545#endif
f8c16bba 5546 kvm_x86_ops = NULL;
56c6d28a 5547 kvm_mmu_module_exit();
013f6a5d 5548 free_percpu(shared_msrs);
56c6d28a 5549}
f8c16bba 5550
8776e519
HB		 5551int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5552{
5553 ++vcpu->stat.halt_exits;
5554 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5555 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5556 return 1;
5557 } else {
5558 vcpu->run->exit_reason = KVM_EXIT_HLT;
5559 return 0;
5560 }
5561}
5562EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5563
55cd8e5a
GN		 5564int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5565{
5566 u64 param, ingpa, outgpa, ret;
5567 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5568 bool fast, longmode;
5569 int cs_db, cs_l;
5570
5571 /*
5572 * hypercall generates UD from non zero cpl and real mode
5573 * per HYPER-V spec
5574 */
3eeb3288 5575 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5576 kvm_queue_exception(vcpu, UD_VECTOR);
5577 return 0;
5578 }
5579
5580 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5581 longmode = is_long_mode(vcpu) && cs_l == 1;
5582
5583 if (!longmode) {
ccd46936
GN		 5584 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5585 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5586 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5587 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5588 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5589 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5590 }
5591#ifdef CONFIG_X86_64
5592 else {
5593 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5594 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5595 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5596 }
5597#endif
5598
5599 code = param & 0xffff;
5600 fast = (param >> 16) & 0x1;
5601 rep_cnt = (param >> 32) & 0xfff;
5602 rep_idx = (param >> 48) & 0xfff;
5603
5604 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5605
c25bc163
GN		 5606 switch (code) {
5607 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5608 kvm_vcpu_on_spin(vcpu);
5609 break;
5610 default:
5611 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5612 break;
5613 }
55cd8e5a
GN		 5614
5615 ret = res | (((u64)rep_done & 0xfff) << 32);
5616 if (longmode) {
5617 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5618 } else {
5619 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5620 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5621 }
5622
5623 return 1;
5624}
5625
6aef266c
SV		 5626/*
5627 * kvm_pv_kick_cpu_op: Kick a vcpu.
5628 *
5629 * @apicid - apicid of vcpu to be kicked.
5630 */
5631static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5632{
24d2166b 5633 struct kvm_lapic_irq lapic_irq;
6aef266c 5634
24d2166b
R		 5635 lapic_irq.shorthand = 0;
5636 lapic_irq.dest_mode = 0;
5637 lapic_irq.dest_id = apicid;
6aef266c 5638
24d2166b
R		 5639 lapic_irq.delivery_mode = APIC_DM_REMRD;
5640 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5641}
5642
8776e519
HB		 5643int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5644{
5645 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5646 int r = 1;
8776e519 5647
55cd8e5a
GN		 5648 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5649 return kvm_hv_hypercall(vcpu);
5650
5fdbf976
MT		 5651 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5652 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5653 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5654 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5655 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5656
229456fc 5657 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5658
8776e519
HB		 5659 if (!is_long_mode(vcpu)) {
5660 nr &= 0xFFFFFFFF;
5661 a0 &= 0xFFFFFFFF;
5662 a1 &= 0xFFFFFFFF;
5663 a2 &= 0xFFFFFFFF;
5664 a3 &= 0xFFFFFFFF;
5665 }
5666
07708c4a
JK		 5667 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5668 ret = -KVM_EPERM;
5669 goto out;
5670 }
5671
8776e519 5672 switch (nr) {
b93463aa
AK		 5673 case KVM_HC_VAPIC_POLL_IRQ:
5674 ret = 0;
5675 break;
6aef266c
SV		 5676 case KVM_HC_KICK_CPU:
5677 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5678 ret = 0;
5679 break;
8776e519
HB		 5680 default:
5681 ret = -KVM_ENOSYS;
5682 break;
5683 }
07708c4a 5684out:
5fdbf976 5685 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5686 ++vcpu->stat.hypercalls;
2f333bcb 5687 return r;
8776e519
HB		 5688}
5689EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5690
b6785def 5691static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5692{
d6aa1000 5693 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5694 char instruction[3];
5fdbf976 5695 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5696
8776e519 5697 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5698
9d74191a 5699 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5700}
5701
b6c7a5dc
HB		 5702/*
5703 * Check if userspace requested an interrupt window, and that the
5704 * interrupt window is open.
5705 *
5706 * No need to exit to userspace if we already have an interrupt queued.
5707 */
851ba692 5708static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5709{
8061823a 5710 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5711 vcpu->run->request_interrupt_window &&
5df56646 5712 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5713}
5714
851ba692 5715static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5716{
851ba692
AK		 5717 struct kvm_run *kvm_run = vcpu->run;
5718
91586a3b 5719 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5720 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5721 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5722 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5723 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5724 else
b6c7a5dc 5725 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5726 kvm_arch_interrupt_allowed(vcpu) &&
5727 !kvm_cpu_has_interrupt(vcpu) &&
5728 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5729}
5730
4484141a 5731static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5732{
5733 struct kvm_lapic *apic = vcpu->arch.apic;
5734 struct page *page;
5735
5736 if (!apic || !apic->vapic_addr)
4484141a 5737 return 0;
b93463aa
AK		 5738
5739 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5740 if (is_error_page(page))
5741 return -EFAULT;
72dc67a6
IE		 5742
5743 vcpu->arch.apic->vapic_page = page;
4484141a 5744 return 0;
b93463aa
AK		 5745}
5746
5747static void vapic_exit(struct kvm_vcpu *vcpu)
5748{
5749 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5750 int idx;
b93463aa
AK		 5751
5752 if (!apic || !apic->vapic_addr)
5753 return;
5754
f656ce01 5755 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5756 kvm_release_page_dirty(apic->vapic_page);
5757 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5758 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5759}
5760
95ba8273
GN		 5761static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5762{
5763 int max_irr, tpr;
5764
5765 if (!kvm_x86_ops->update_cr8_intercept)
5766 return;
5767
88c808fd
AK		 5768 if (!vcpu->arch.apic)
5769 return;
5770
8db3baa2
GN		 5771 if (!vcpu->arch.apic->vapic_addr)
5772 max_irr = kvm_lapic_find_highest_irr(vcpu);
5773 else
5774 max_irr = -1;
95ba8273
GN		 5775
5776 if (max_irr != -1)
5777 max_irr >>= 4;
5778
5779 tpr = kvm_lapic_get_cr8(vcpu);
5780
5781 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5782}
5783
851ba692 5784static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5785{
5786 /* try to reinject previous events if any */
b59bb7bd 5787 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5788 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5789 vcpu->arch.exception.has_error_code,
5790 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5791 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5792 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5793 vcpu->arch.exception.error_code,
5794 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5795 return;
5796 }
5797
95ba8273
GN		 5798 if (vcpu->arch.nmi_injected) {
5799 kvm_x86_ops->set_nmi(vcpu);
5800 return;
5801 }
5802
5803 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5804 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5805 return;
5806 }
5807
5808 /* try to inject new event if pending */
5809 if (vcpu->arch.nmi_pending) {
5810 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5811 --vcpu->arch.nmi_pending;
95ba8273
GN		 5812 vcpu->arch.nmi_injected = true;
5813 kvm_x86_ops->set_nmi(vcpu);
5814 }
c7c9c56c 5815 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5816 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5817 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5818 false);
5819 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5820 }
5821 }
5822}
5823
7460fb4a
AK		 5824static void process_nmi(struct kvm_vcpu *vcpu)
5825{
5826 unsigned limit = 2;
5827
5828 /*
5829 * x86 is limited to one NMI running, and one NMI pending after it.
5830 * If an NMI is already in progress, limit further NMIs to just one.
5831 * Otherwise, allow two (and we'll inject the first one immediately).
5832 */
5833 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5834 limit = 1;
5835
5836 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5837 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5838 kvm_make_request(KVM_REQ_EVENT, vcpu);
5839}
5840
3d81bc7e 5841static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5842{
5843 u64 eoi_exit_bitmap[4];
cf9e65b7 5844 u32 tmr[8];
c7c9c56c 5845
3d81bc7e
YZ		 5846 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5847 return;
c7c9c56c
YZ		 5848
5849 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5850 memset(tmr, 0, 32);
c7c9c56c 5851
cf9e65b7 5852 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5853 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5854 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5855}
5856
9357d939
TY		 5857/*
5858 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5859 * exiting to the userspace. Otherwise, the value will be returned to the
5860 * userspace.
5861 */
851ba692 5862static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5863{
5864 int r;
6a8b1d13 5865 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5866 vcpu->run->request_interrupt_window;
730dca42 5867 bool req_immediate_exit = false;
b6c7a5dc 5868
3e007509 5869 if (vcpu->requests) {
a8eeb04a 5870 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5871 kvm_mmu_unload(vcpu);
a8eeb04a 5872 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5873 __kvm_migrate_timers(vcpu);
d828199e
MT		 5874 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5875 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5876 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5877 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5878 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5879 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5880 if (unlikely(r))
5881 goto out;
5882 }
a8eeb04a 5883 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5884 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5885 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5886 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5887 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5888 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5889 r = 0;
5890 goto out;
5891 }
a8eeb04a 5892 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5893 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5894 r = 0;
5895 goto out;
5896 }
a8eeb04a 5897 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5898 vcpu->fpu_active = 0;
5899 kvm_x86_ops->fpu_deactivate(vcpu);
5900 }
af585b92
GN		 5901 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5902 /* Page is swapped out. Do synthetic halt */
5903 vcpu->arch.apf.halted = true;
5904 r = 1;
5905 goto out;
5906 }
c9aaa895
GC		 5907 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5908 record_steal_time(vcpu);
7460fb4a
AK		 5909 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5910 process_nmi(vcpu);
f5132b01
GN		 5911 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5912 kvm_handle_pmu_event(vcpu);
5913 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5914 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5915 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5916 vcpu_scan_ioapic(vcpu);
2f52d58c 5917 }
b93463aa 5918
b463a6f7 5919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5920 kvm_apic_accept_events(vcpu);
5921 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5922 r = 1;
5923 goto out;
5924 }
5925
b463a6f7
AK		 5926 inject_pending_event(vcpu);
5927
5928 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5929 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5930 req_immediate_exit =
5931 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5932 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5933 req_immediate_exit =
5934 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5935
5936 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5937 /*
5938 * Update architecture specific hints for APIC
5939 * virtual interrupt delivery.
5940 */
5941 if (kvm_x86_ops->hwapic_irr_update)
5942 kvm_x86_ops->hwapic_irr_update(vcpu,
5943 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5944 update_cr8_intercept(vcpu);
5945 kvm_lapic_sync_to_vapic(vcpu);
5946 }
5947 }
5948
d8368af8
AK		 5949 r = kvm_mmu_reload(vcpu);
5950 if (unlikely(r)) {
d905c069 5951 goto cancel_injection;
d8368af8
AK		 5952 }
5953
b6c7a5dc
HB		 5954 preempt_disable();
5955
5956 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5957 if (vcpu->fpu_active)
5958 kvm_load_guest_fpu(vcpu);
2acf923e 5959 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5960
6b7e2d09
XG		 5961 vcpu->mode = IN_GUEST_MODE;
5962
01b71917
MT		 5963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5964
6b7e2d09
XG		 5965 /* We should set ->mode before check ->requests,
5966 * see the comment in make_all_cpus_request.
5967 */
01b71917 5968 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5969
d94e1dc9 5970 local_irq_disable();
32f88400 5971
6b7e2d09 5972 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5973 || need_resched() || signal_pending(current)) {
6b7e2d09 5974 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5975 smp_wmb();
6c142801
AK		 5976 local_irq_enable();
5977 preempt_enable();
01b71917 5978 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5979 r = 1;
d905c069 5980 goto cancel_injection;
6c142801
AK		 5981 }
5982
d6185f20
NHE		 5983 if (req_immediate_exit)
5984 smp_send_reschedule(vcpu->cpu);
5985
b6c7a5dc
HB		 5986 kvm_guest_enter();
5987
42dbaa5a 5988 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5989 set_debugreg(0, 7);
5990 set_debugreg(vcpu->arch.eff_db[0], 0);
5991 set_debugreg(vcpu->arch.eff_db[1], 1);
5992 set_debugreg(vcpu->arch.eff_db[2], 2);
5993 set_debugreg(vcpu->arch.eff_db[3], 3);
5994 }
b6c7a5dc 5995
229456fc 5996 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5997 kvm_x86_ops->run(vcpu);
b6c7a5dc 5998
24f1e32c
FW		 5999 /*
6000 * If the guest has used debug registers, at least dr7
6001 * will be disabled while returning to the host.
6002 * If we don't have active breakpoints in the host, we don't
6003 * care about the messed up debug address registers. But if
6004 * we have some of them active, restore the old state.
6005 */
59d8eb53 6006 if (hw_breakpoint_active())
24f1e32c 6007 hw_breakpoint_restore();
42dbaa5a 6008
886b470c
MT		 6009 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6010 native_read_tsc());
1d5f066e 6011
6b7e2d09 6012 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6013 smp_wmb();
a547c6db
YZ		 6014
6015 /* Interrupt is enabled by handle_external_intr() */
6016 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6017
6018 ++vcpu->stat.exits;
6019
6020 /*
6021 * We must have an instruction between local_irq_enable() and
6022 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6023 * the interrupt shadow. The stat.exits increment will do nicely.
6024 * But we need to prevent reordering, hence this barrier():
6025 */
6026 barrier();
6027
6028 kvm_guest_exit();
6029
6030 preempt_enable();
6031
f656ce01 6032 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6033
b6c7a5dc
HB		 6034 /*
6035 * Profile KVM exit RIPs:
6036 */
6037 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6038 unsigned long rip = kvm_rip_read(vcpu);
6039 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6040 }
6041
cc578287
ZA		 6042 if (unlikely(vcpu->arch.tsc_always_catchup))
6043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6044
5cfb1d5a
MT		 6045 if (vcpu->arch.apic_attention)
6046 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6047
851ba692 6048 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6049 return r;
6050
6051cancel_injection:
6052 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6053 if (unlikely(vcpu->arch.apic_attention))
6054 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6055out:
6056 return r;
6057}
b6c7a5dc 6058
09cec754 6059
851ba692 6060static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6061{
6062 int r;
f656ce01 6063 struct kvm *kvm = vcpu->kvm;
d7690175 6064
f656ce01 6065 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6066 r = vapic_enter(vcpu);
6067 if (r) {
6068 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6069 return r;
6070 }
d7690175
MT		 6071
6072 r = 1;
6073 while (r > 0) {
af585b92
GN		 6074 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6075 !vcpu->arch.apf.halted)
851ba692 6076 r = vcpu_enter_guest(vcpu);
d7690175 6077 else {
f656ce01 6078 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6079 kvm_vcpu_block(vcpu);
f656ce01 6080 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6081 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6082 kvm_apic_accept_events(vcpu);
09cec754
GN		 6083 switch(vcpu->arch.mp_state) {
6084 case KVM_MP_STATE_HALTED:
6aef266c 6085 vcpu->arch.pv.pv_unhalted = false;
d7690175 6086 vcpu->arch.mp_state =
09cec754
GN		 6087 KVM_MP_STATE_RUNNABLE;
6088 case KVM_MP_STATE_RUNNABLE:
af585b92 6089 vcpu->arch.apf.halted = false;
09cec754 6090 break;
66450a21
JK		 6091 case KVM_MP_STATE_INIT_RECEIVED:
6092 break;
09cec754
GN		 6093 default:
6094 r = -EINTR;
6095 break;
6096 }
6097 }
d7690175
MT		 6098 }
6099
09cec754
GN		 6100 if (r <= 0)
6101 break;
6102
6103 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6104 if (kvm_cpu_has_pending_timer(vcpu))
6105 kvm_inject_pending_timer_irqs(vcpu);
6106
851ba692 6107 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6108 r = -EINTR;
851ba692 6109 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6110 ++vcpu->stat.request_irq_exits;
6111 }
af585b92
GN		 6112
6113 kvm_check_async_pf_completion(vcpu);
6114
09cec754
GN		 6115 if (signal_pending(current)) {
6116 r = -EINTR;
851ba692 6117 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6118 ++vcpu->stat.signal_exits;
6119 }
6120 if (need_resched()) {
f656ce01 6121 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6122 cond_resched();
f656ce01 6123 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6124 }
b6c7a5dc
HB		 6125 }
6126
f656ce01 6127 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6128
b93463aa
AK		 6129 vapic_exit(vcpu);
6130
b6c7a5dc
HB		 6131 return r;
6132}
6133
716d51ab
GN		 6134static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6135{
6136 int r;
6137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6138 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6139 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6140 if (r != EMULATE_DONE)
6141 return 0;
6142 return 1;
6143}
6144
6145static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6146{
6147 BUG_ON(!vcpu->arch.pio.count);
6148
6149 return complete_emulated_io(vcpu);
6150}
6151
f78146b0
AK		 6152/*
6153 * Implements the following, as a state machine:
6154 *
6155 * read:
6156 * for each fragment
87da7e66
XG		 6157 * for each mmio piece in the fragment
6158 * write gpa, len
6159 * exit
6160 * copy data
f78146b0
AK		 6161 * execute insn
6162 *
6163 * write:
6164 * for each fragment
87da7e66
XG		 6165 * for each mmio piece in the fragment
6166 * write gpa, len
6167 * copy data
6168 * exit
f78146b0 6169 */
716d51ab 6170static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6171{
6172 struct kvm_run *run = vcpu->run;
f78146b0 6173 struct kvm_mmio_fragment *frag;
87da7e66 6174 unsigned len;
5287f194 6175
716d51ab 6176 BUG_ON(!vcpu->mmio_needed);
5287f194 6177
716d51ab 6178 /* Complete previous fragment */
87da7e66
XG		 6179 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6180 len = min(8u, frag->len);
716d51ab 6181 if (!vcpu->mmio_is_write)
87da7e66
XG		 6182 memcpy(frag->data, run->mmio.data, len);
6183
6184 if (frag->len <= 8) {
6185 /* Switch to the next fragment. */
6186 frag++;
6187 vcpu->mmio_cur_fragment++;
6188 } else {
6189 /* Go forward to the next mmio piece. */
6190 frag->data += len;
6191 frag->gpa += len;
6192 frag->len -= len;
6193 }
6194
716d51ab
GN		 6195 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6196 vcpu->mmio_needed = 0;
0912c977
PB		 6197
6198 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6199 if (vcpu->mmio_is_write)
716d51ab
GN		 6200 return 1;
6201 vcpu->mmio_read_completed = 1;
6202 return complete_emulated_io(vcpu);
6203 }
87da7e66 6204
716d51ab
GN		 6205 run->exit_reason = KVM_EXIT_MMIO;
6206 run->mmio.phys_addr = frag->gpa;
6207 if (vcpu->mmio_is_write)
87da7e66
XG		 6208 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6209 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6210 run->mmio.is_write = vcpu->mmio_is_write;
6211 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6212 return 0;
5287f194
AK		 6213}
6214
716d51ab 6215
b6c7a5dc
HB		 6216int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6217{
6218 int r;
6219 sigset_t sigsaved;
6220
e5c30142
AK		 6221 if (!tsk_used_math(current) && init_fpu(current))
6222 return -ENOMEM;
6223
ac9f6dc0
AK		 6224 if (vcpu->sigset_active)
6225 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6226
a4535290 6227 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6228 kvm_vcpu_block(vcpu);
66450a21 6229 kvm_apic_accept_events(vcpu);
d7690175 6230 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6231 r = -EAGAIN;
6232 goto out;
b6c7a5dc
HB		 6233 }
6234
b6c7a5dc 6235 /* re-sync apic's tpr */
eea1cff9
AP		 6236 if (!irqchip_in_kernel(vcpu->kvm)) {
6237 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6238 r = -EINVAL;
6239 goto out;
6240 }
6241 }
b6c7a5dc 6242
716d51ab
GN		 6243 if (unlikely(vcpu->arch.complete_userspace_io)) {
6244 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6245 vcpu->arch.complete_userspace_io = NULL;
6246 r = cui(vcpu);
6247 if (r <= 0)
6248 goto out;
6249 } else
6250 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6251
851ba692 6252 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6253
6254out:
f1d86e46 6255 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6256 if (vcpu->sigset_active)
6257 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6258
b6c7a5dc
HB		 6259 return r;
6260}
6261
6262int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6263{
7ae441ea
GN		 6264 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6265 /*
6266 * We are here if userspace calls get_regs() in the middle of
6267 * instruction emulation. Registers state needs to be copied
4a969980 6268 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6269 * that usually, but some bad designed PV devices (vmware
6270 * backdoor interface) need this to work
6271 */
dd856efa 6272 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6273 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6274 }
5fdbf976
MT		 6275 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6276 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6277 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6278 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6279 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6280 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6281 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6282 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6283#ifdef CONFIG_X86_64
5fdbf976
MT		 6284 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6285 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6286 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6287 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6288 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6289 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6290 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6291 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6292#endif
6293
5fdbf976 6294 regs->rip = kvm_rip_read(vcpu);
91586a3b 6295 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6296
b6c7a5dc
HB		 6297 return 0;
6298}
6299
6300int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6301{
7ae441ea
GN		 6302 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6303 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6304
5fdbf976
MT		 6305 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6306 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6307 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6308 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6309 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6310 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6311 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6312 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6313#ifdef CONFIG_X86_64
5fdbf976
MT		 6314 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6315 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6316 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6317 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6318 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6319 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6320 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6321 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6322#endif
6323
5fdbf976 6324 kvm_rip_write(vcpu, regs->rip);
91586a3b 6325 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6326
b4f14abd
JK		 6327 vcpu->arch.exception.pending = false;
6328
3842d135
AK		 6329 kvm_make_request(KVM_REQ_EVENT, vcpu);
6330
b6c7a5dc
HB		 6331 return 0;
6332}
6333
b6c7a5dc
HB		 6334void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6335{
6336 struct kvm_segment cs;
6337
3e6e0aab 6338 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6339 *db = cs.db;
6340 *l = cs.l;
6341}
6342EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6343
6344int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6345 struct kvm_sregs *sregs)
6346{
89a27f4d 6347 struct desc_ptr dt;
b6c7a5dc 6348
3e6e0aab
GT		 6349 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6350 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6351 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6352 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6353 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6354 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6355
3e6e0aab
GT		 6356 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6357 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6358
6359 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6360 sregs->idt.limit = dt.size;
6361 sregs->idt.base = dt.address;
b6c7a5dc 6362 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6363 sregs->gdt.limit = dt.size;
6364 sregs->gdt.base = dt.address;
b6c7a5dc 6365
4d4ec087 6366 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6367 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6368 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6369 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6370 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6371 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6372 sregs->apic_base = kvm_get_apic_base(vcpu);
6373
923c61bb 6374 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6375
36752c9b 6376 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6377 set_bit(vcpu->arch.interrupt.nr,
6378 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6379
b6c7a5dc
HB		 6380 return 0;
6381}
6382
62d9f0db
MT		 6383int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6384 struct kvm_mp_state *mp_state)
6385{
66450a21 6386 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6387 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6388 vcpu->arch.pv.pv_unhalted)
6389 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6390 else
6391 mp_state->mp_state = vcpu->arch.mp_state;
6392
62d9f0db
MT		 6393 return 0;
6394}
6395
6396int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6397 struct kvm_mp_state *mp_state)
6398{
66450a21
JK		 6399 if (!kvm_vcpu_has_lapic(vcpu) &&
6400 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6401 return -EINVAL;
6402
6403 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6404 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6405 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6406 } else
6407 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6409 return 0;
6410}
6411
7f3d35fd
KW		 6412int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6413 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6414{
9d74191a 6415 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6416 int ret;
e01c2426 6417
8ec4722d 6418 init_emulate_ctxt(vcpu);
c697518a 6419
7f3d35fd 6420 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6421 has_error_code, error_code);
c697518a 6422
c697518a 6423 if (ret)
19d04437 6424 return EMULATE_FAIL;
37817f29 6425
9d74191a
TY		 6426 kvm_rip_write(vcpu, ctxt->eip);
6427 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6428 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6429 return EMULATE_DONE;
37817f29
IE		 6430}
6431EXPORT_SYMBOL_GPL(kvm_task_switch);
6432
b6c7a5dc
HB		 6433int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6434 struct kvm_sregs *sregs)
6435{
6436 int mmu_reset_needed = 0;
63f42e02 6437 int pending_vec, max_bits, idx;
89a27f4d 6438 struct desc_ptr dt;
b6c7a5dc 6439
6d1068b3
PM		 6440 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6441 return -EINVAL;
6442
89a27f4d
GN		 6443 dt.size = sregs->idt.limit;
6444 dt.address = sregs->idt.base;
b6c7a5dc 6445 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6446 dt.size = sregs->gdt.limit;
6447 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6448 kvm_x86_ops->set_gdt(vcpu, &dt);
6449
ad312c7c 6450 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6451 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6452 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6453 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6454
2d3ad1f4 6455 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6456
f6801dff 6457 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6458 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6459 kvm_set_apic_base(vcpu, sregs->apic_base);
6460
4d4ec087 6461 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6462 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6463 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6464
fc78f519 6465 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6466 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6467 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6468 kvm_update_cpuid(vcpu);
63f42e02
XG		 6469
6470 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6471 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6472 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6473 mmu_reset_needed = 1;
6474 }
63f42e02 6475 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6476
6477 if (mmu_reset_needed)
6478 kvm_mmu_reset_context(vcpu);
6479
a50abc3b 6480 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6481 pending_vec = find_first_bit(
6482 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6483 if (pending_vec < max_bits) {
66fd3f7f 6484 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6485 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6486 }
6487
3e6e0aab
GT		 6488 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6489 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6490 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6491 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6492 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6493 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6494
3e6e0aab
GT		 6495 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6496 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6497
5f0269f5
ME		 6498 update_cr8_intercept(vcpu);
6499
9c3e4aab 6500 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6501 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6502 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6503 !is_protmode(vcpu))
9c3e4aab
MT		 6504 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6505
3842d135
AK		 6506 kvm_make_request(KVM_REQ_EVENT, vcpu);
6507
b6c7a5dc
HB		 6508 return 0;
6509}
6510
d0bfb940
JK		 6511int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6512 struct kvm_guest_debug *dbg)
b6c7a5dc 6513{
355be0b9 6514 unsigned long rflags;
ae675ef0 6515 int i, r;
b6c7a5dc 6516
4f926bf2
JK		 6517 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6518 r = -EBUSY;
6519 if (vcpu->arch.exception.pending)
2122ff5e 6520 goto out;
4f926bf2
JK		 6521 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6522 kvm_queue_exception(vcpu, DB_VECTOR);
6523 else
6524 kvm_queue_exception(vcpu, BP_VECTOR);
6525 }
6526
91586a3b
JK		 6527 /*
6528 * Read rflags as long as potentially injected trace flags are still
6529 * filtered out.
6530 */
6531 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6532
6533 vcpu->guest_debug = dbg->control;
6534 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6535 vcpu->guest_debug = 0;
6536
6537 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6538 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6539 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6540 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6541 } else {
6542 for (i = 0; i < KVM_NR_DB_REGS; i++)
6543 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6544 }
c8639010 6545 kvm_update_dr7(vcpu);
ae675ef0 6546
f92653ee
JK		 6547 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6548 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6549 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6550
91586a3b
JK		 6551 /*
6552 * Trigger an rflags update that will inject or remove the trace
6553 * flags.
6554 */
6555 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6556
c8639010 6557 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6558
4f926bf2 6559 r = 0;
d0bfb940 6560
2122ff5e 6561out:
b6c7a5dc
HB		 6562
6563 return r;
6564}
6565
8b006791
ZX		 6566/*
6567 * Translate a guest virtual address to a guest physical address.
6568 */
6569int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6570 struct kvm_translation *tr)
6571{
6572 unsigned long vaddr = tr->linear_address;
6573 gpa_t gpa;
f656ce01 6574 int idx;
8b006791 6575
f656ce01 6576 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6577 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6578 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6579 tr->physical_address = gpa;
6580 tr->valid = gpa != UNMAPPED_GVA;
6581 tr->writeable = 1;
6582 tr->usermode = 0;
8b006791
ZX		 6583
6584 return 0;
6585}
6586
d0752060
HB		 6587int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6588{
98918833
SY		 6589 struct i387_fxsave_struct *fxsave =
6590 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6591
d0752060
HB		 6592 memcpy(fpu->fpr, fxsave->st_space, 128);
6593 fpu->fcw = fxsave->cwd;
6594 fpu->fsw = fxsave->swd;
6595 fpu->ftwx = fxsave->twd;
6596 fpu->last_opcode = fxsave->fop;
6597 fpu->last_ip = fxsave->rip;
6598 fpu->last_dp = fxsave->rdp;
6599 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6600
d0752060
HB		 6601 return 0;
6602}
6603
6604int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6605{
98918833
SY		 6606 struct i387_fxsave_struct *fxsave =
6607 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6608
d0752060
HB		 6609 memcpy(fxsave->st_space, fpu->fpr, 128);
6610 fxsave->cwd = fpu->fcw;
6611 fxsave->swd = fpu->fsw;
6612 fxsave->twd = fpu->ftwx;
6613 fxsave->fop = fpu->last_opcode;
6614 fxsave->rip = fpu->last_ip;
6615 fxsave->rdp = fpu->last_dp;
6616 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6617
d0752060
HB		 6618 return 0;
6619}
6620
10ab25cd 6621int fx_init(struct kvm_vcpu *vcpu)
d0752060 6622{
10ab25cd
JK		 6623 int err;
6624
6625 err = fpu_alloc(&vcpu->arch.guest_fpu);
6626 if (err)
6627 return err;
6628
98918833 6629 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6630
2acf923e
DC		 6631 /*
6632 * Ensure guest xcr0 is valid for loading
6633 */
6634 vcpu->arch.xcr0 = XSTATE_FP;
6635
ad312c7c 6636 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6637
6638 return 0;
d0752060
HB		 6639}
6640EXPORT_SYMBOL_GPL(fx_init);
6641
98918833
SY		 6642static void fx_free(struct kvm_vcpu *vcpu)
6643{
6644 fpu_free(&vcpu->arch.guest_fpu);
6645}
6646
d0752060
HB		 6647void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6648{
2608d7a1 6649 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6650 return;
6651
2acf923e
DC		 6652 /*
6653 * Restore all possible states in the guest,
6654 * and assume host would use all available bits.
6655 * Guest xcr0 would be loaded later.
6656 */
6657 kvm_put_guest_xcr0(vcpu);
d0752060 6658 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6659 __kernel_fpu_begin();
98918833 6660 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6661 trace_kvm_fpu(1);
d0752060 6662}
d0752060
HB		 6663
6664void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6665{
2acf923e
DC		 6666 kvm_put_guest_xcr0(vcpu);
6667
d0752060
HB		 6668 if (!vcpu->guest_fpu_loaded)
6669 return;
6670
6671 vcpu->guest_fpu_loaded = 0;
98918833 6672 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6673 __kernel_fpu_end();
f096ed85 6674 ++vcpu->stat.fpu_reload;
a8eeb04a 6675 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6676 trace_kvm_fpu(0);
d0752060 6677}
e9b11c17
ZX		 6678
6679void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6680{
12f9a48f 6681 kvmclock_reset(vcpu);
7f1ea208 6682
f5f48ee1 6683 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6684 fx_free(vcpu);
e9b11c17
ZX		 6685 kvm_x86_ops->vcpu_free(vcpu);
6686}
6687
6688struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6689 unsigned int id)
6690{
6755bae8
ZA		 6691 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6692 printk_once(KERN_WARNING
6693 "kvm: SMP vm created on host with unstable TSC; "
6694 "guest TSC will not be reliable\n");
26e5215f
AK		 6695 return kvm_x86_ops->vcpu_create(kvm, id);
6696}
e9b11c17 6697
26e5215f
AK		 6698int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6699{
6700 int r;
e9b11c17 6701
0bed3b56 6702 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6703 r = vcpu_load(vcpu);
6704 if (r)
6705 return r;
57f252f2 6706 kvm_vcpu_reset(vcpu);
8a3c1a33 6707 kvm_mmu_setup(vcpu);
e9b11c17 6708 vcpu_put(vcpu);
e9b11c17 6709
26e5215f 6710 return r;
e9b11c17
ZX		 6711}
6712
42897d86
MT		 6713int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6714{
6715 int r;
8fe8ab46 6716 struct msr_data msr;
42897d86
MT		 6717
6718 r = vcpu_load(vcpu);
6719 if (r)
6720 return r;
8fe8ab46
WA		 6721 msr.data = 0x0;
6722 msr.index = MSR_IA32_TSC;
6723 msr.host_initiated = true;
6724 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6725 vcpu_put(vcpu);
6726
6727 return r;
6728}
6729
d40ccc62 6730void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6731{
9fc77441 6732 int r;
344d9588
GN		 6733 vcpu->arch.apf.msr_val = 0;
6734
9fc77441
MT		 6735 r = vcpu_load(vcpu);
6736 BUG_ON(r);
e9b11c17
ZX		 6737 kvm_mmu_unload(vcpu);
6738 vcpu_put(vcpu);
6739
98918833 6740 fx_free(vcpu);
e9b11c17
ZX		 6741 kvm_x86_ops->vcpu_free(vcpu);
6742}
6743
66450a21 6744void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6745{
7460fb4a
AK		 6746 atomic_set(&vcpu->arch.nmi_queued, 0);
6747 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6748 vcpu->arch.nmi_injected = false;
6749
42dbaa5a
JK		 6750 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6751 vcpu->arch.dr6 = DR6_FIXED_1;
6752 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6753 kvm_update_dr7(vcpu);
42dbaa5a 6754
3842d135 6755 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6756 vcpu->arch.apf.msr_val = 0;
c9aaa895 6757 vcpu->arch.st.msr_val = 0;
3842d135 6758
12f9a48f
GC		 6759 kvmclock_reset(vcpu);
6760
af585b92
GN		 6761 kvm_clear_async_pf_completion_queue(vcpu);
6762 kvm_async_pf_hash_reset(vcpu);
6763 vcpu->arch.apf.halted = false;
3842d135 6764
f5132b01
GN		 6765 kvm_pmu_reset(vcpu);
6766
66f7b72e
JS		 6767 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6768 vcpu->arch.regs_avail = ~0;
6769 vcpu->arch.regs_dirty = ~0;
6770
57f252f2 6771 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6772}
6773
66450a21
JK		 6774void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6775{
6776 struct kvm_segment cs;
6777
6778 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6779 cs.selector = vector << 8;
6780 cs.base = vector << 12;
6781 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6782 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6783}
6784
10474ae8 6785int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6786{
ca84d1a2
ZA		 6787 struct kvm *kvm;
6788 struct kvm_vcpu *vcpu;
6789 int i;
0dd6a6ed
ZA		 6790 int ret;
6791 u64 local_tsc;
6792 u64 max_tsc = 0;
6793 bool stable, backwards_tsc = false;
18863bdd
AK		 6794
6795 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6796 ret = kvm_x86_ops->hardware_enable(garbage);
6797 if (ret != 0)
6798 return ret;
6799
6800 local_tsc = native_read_tsc();
6801 stable = !check_tsc_unstable();
6802 list_for_each_entry(kvm, &vm_list, vm_list) {
6803 kvm_for_each_vcpu(i, vcpu, kvm) {
6804 if (!stable && vcpu->cpu == smp_processor_id())
6805 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6806 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6807 backwards_tsc = true;
6808 if (vcpu->arch.last_host_tsc > max_tsc)
6809 max_tsc = vcpu->arch.last_host_tsc;
6810 }
6811 }
6812 }
6813
6814 /*
6815 * Sometimes, even reliable TSCs go backwards. This happens on
6816 * platforms that reset TSC during suspend or hibernate actions, but
6817 * maintain synchronization. We must compensate. Fortunately, we can
6818 * detect that condition here, which happens early in CPU bringup,
6819 * before any KVM threads can be running. Unfortunately, we can't
6820 * bring the TSCs fully up to date with real time, as we aren't yet far
6821 * enough into CPU bringup that we know how much real time has actually
6822 * elapsed; our helper function, get_kernel_ns() will be using boot
6823 * variables that haven't been updated yet.
6824 *
6825 * So we simply find the maximum observed TSC above, then record the
6826 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6827 * the adjustment will be applied. Note that we accumulate
6828 * adjustments, in case multiple suspend cycles happen before some VCPU
6829 * gets a chance to run again. In the event that no KVM threads get a
6830 * chance to run, we will miss the entire elapsed period, as we'll have
6831 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6832 * loose cycle time. This isn't too big a deal, since the loss will be
6833 * uniform across all VCPUs (not to mention the scenario is extremely
6834 * unlikely). It is possible that a second hibernate recovery happens
6835 * much faster than a first, causing the observed TSC here to be
6836 * smaller; this would require additional padding adjustment, which is
6837 * why we set last_host_tsc to the local tsc observed here.
6838 *
6839 * N.B. - this code below runs only on platforms with reliable TSC,
6840 * as that is the only way backwards_tsc is set above. Also note
6841 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6842 * have the same delta_cyc adjustment applied if backwards_tsc
6843 * is detected. Note further, this adjustment is only done once,
6844 * as we reset last_host_tsc on all VCPUs to stop this from being
6845 * called multiple times (one for each physical CPU bringup).
6846 *
4a969980 6847 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6848 * will be compensated by the logic in vcpu_load, which sets the TSC to
6849 * catchup mode. This will catchup all VCPUs to real time, but cannot
6850 * guarantee that they stay in perfect synchronization.
6851 */
6852 if (backwards_tsc) {
6853 u64 delta_cyc = max_tsc - local_tsc;
6854 list_for_each_entry(kvm, &vm_list, vm_list) {
6855 kvm_for_each_vcpu(i, vcpu, kvm) {
6856 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6857 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6858 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6859 &vcpu->requests);
0dd6a6ed
ZA		 6860 }
6861
6862 /*
6863 * We have to disable TSC offset matching.. if you were
6864 * booting a VM while issuing an S4 host suspend....
6865 * you may have some problem. Solving this issue is
6866 * left as an exercise to the reader.
6867 */
6868 kvm->arch.last_tsc_nsec = 0;
6869 kvm->arch.last_tsc_write = 0;
6870 }
6871
6872 }
6873 return 0;
e9b11c17
ZX		 6874}
6875
6876void kvm_arch_hardware_disable(void *garbage)
6877{
6878 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6879 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6880}
6881
6882int kvm_arch_hardware_setup(void)
6883{
6884 return kvm_x86_ops->hardware_setup();
6885}
6886
6887void kvm_arch_hardware_unsetup(void)
6888{
6889 kvm_x86_ops->hardware_unsetup();
6890}
6891
6892void kvm_arch_check_processor_compat(void *rtn)
6893{
6894 kvm_x86_ops->check_processor_compatibility(rtn);
6895}
6896
3e515705
AK		 6897bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6898{
6899 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6900}
6901
54e9818f
GN		 6902struct static_key kvm_no_apic_vcpu __read_mostly;
6903
e9b11c17
ZX		 6904int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6905{
6906 struct page *page;
6907 struct kvm *kvm;
6908 int r;
6909
6910 BUG_ON(vcpu->kvm == NULL);
6911 kvm = vcpu->kvm;
6912
6aef266c 6913 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6914 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6915 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6916 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6917 else
a4535290 6918 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6919
6920 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6921 if (!page) {
6922 r = -ENOMEM;
6923 goto fail;
6924 }
ad312c7c 6925 vcpu->arch.pio_data = page_address(page);
e9b11c17 6926
cc578287 6927 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6928
e9b11c17
ZX		 6929 r = kvm_mmu_create(vcpu);
6930 if (r < 0)
6931 goto fail_free_pio_data;
6932
6933 if (irqchip_in_kernel(kvm)) {
6934 r = kvm_create_lapic(vcpu);
6935 if (r < 0)
6936 goto fail_mmu_destroy;
54e9818f
GN		 6937 } else
6938 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6939
890ca9ae
HY		 6940 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6941 GFP_KERNEL);
6942 if (!vcpu->arch.mce_banks) {
6943 r = -ENOMEM;
443c39bc 6944 goto fail_free_lapic;
890ca9ae
HY		 6945 }
6946 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6947
f1797359
WY		 6948 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6949 r = -ENOMEM;
f5f48ee1 6950 goto fail_free_mce_banks;
f1797359 6951 }
f5f48ee1 6952
66f7b72e
JS		 6953 r = fx_init(vcpu);
6954 if (r)
6955 goto fail_free_wbinvd_dirty_mask;
6956
ba904635 6957 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6958 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6959
6960 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6961 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6962
af585b92 6963 kvm_async_pf_hash_reset(vcpu);
f5132b01 6964 kvm_pmu_init(vcpu);
af585b92 6965
e9b11c17 6966 return 0;
66f7b72e
JS		 6967fail_free_wbinvd_dirty_mask:
6968 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6969fail_free_mce_banks:
6970 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6971fail_free_lapic:
6972 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6973fail_mmu_destroy:
6974 kvm_mmu_destroy(vcpu);
6975fail_free_pio_data:
ad312c7c 6976 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6977fail:
6978 return r;
6979}
6980
6981void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6982{
f656ce01
MT		 6983 int idx;
6984
f5132b01 6985 kvm_pmu_destroy(vcpu);
36cb93fd 6986 kfree(vcpu->arch.mce_banks);
e9b11c17 6987 kvm_free_lapic(vcpu);
f656ce01 6988 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6989 kvm_mmu_destroy(vcpu);
f656ce01 6990 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6991 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6992 if (!irqchip_in_kernel(vcpu->kvm))
6993 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6994}
d19a9cd2 6995
e08b9637 6996int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6997{
e08b9637
CO		 6998 if (type)
6999 return -EINVAL;
7000
f05e70ac 7001 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7002 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7003 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7004 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7005
5550af4d
SY		 7006 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7007 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7008 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7009 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7010 &kvm->arch.irq_sources_bitmap);
5550af4d 7011
038f8c11 7012 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7013 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7014 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7015
7016 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7017
d89f5eff 7018 return 0;
d19a9cd2
ZX		 7019}
7020
7021static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7022{
9fc77441
MT		 7023 int r;
7024 r = vcpu_load(vcpu);
7025 BUG_ON(r);
d19a9cd2
ZX		 7026 kvm_mmu_unload(vcpu);
7027 vcpu_put(vcpu);
7028}
7029
7030static void kvm_free_vcpus(struct kvm *kvm)
7031{
7032 unsigned int i;
988a2cae 7033 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7034
7035 /*
7036 * Unpin any mmu pages first.
7037 */
af585b92
GN		 7038 kvm_for_each_vcpu(i, vcpu, kvm) {
7039 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7040 kvm_unload_vcpu_mmu(vcpu);
af585b92 7041 }
988a2cae
GN		 7042 kvm_for_each_vcpu(i, vcpu, kvm)
7043 kvm_arch_vcpu_free(vcpu);
7044
7045 mutex_lock(&kvm->lock);
7046 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7047 kvm->vcpus[i] = NULL;
d19a9cd2 7048
988a2cae
GN		 7049 atomic_set(&kvm->online_vcpus, 0);
7050 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7051}
7052
ad8ba2cd
SY		 7053void kvm_arch_sync_events(struct kvm *kvm)
7054{
ba4cef31 7055 kvm_free_all_assigned_devices(kvm);
aea924f6 7056 kvm_free_pit(kvm);
ad8ba2cd
SY		 7057}
7058
d19a9cd2
ZX		 7059void kvm_arch_destroy_vm(struct kvm *kvm)
7060{
27469d29
AH		 7061 if (current->mm == kvm->mm) {
7062 /*
7063 * Free memory regions allocated on behalf of userspace,
7064 * unless the the memory map has changed due to process exit
7065 * or fd copying.
7066 */
7067 struct kvm_userspace_memory_region mem;
7068 memset(&mem, 0, sizeof(mem));
7069 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071
7072 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7073 kvm_set_memory_region(kvm, &mem);
7074
7075 mem.slot = TSS_PRIVATE_MEMSLOT;
7076 kvm_set_memory_region(kvm, &mem);
7077 }
6eb55818 7078 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7079 kfree(kvm->arch.vpic);
7080 kfree(kvm->arch.vioapic);
d19a9cd2 7081 kvm_free_vcpus(kvm);
3d45830c
AK		 7082 if (kvm->arch.apic_access_page)
7083 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7084 if (kvm->arch.ept_identity_pagetable)
7085 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7086 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7087}
0de10343 7088
5587027c 7089void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7090 struct kvm_memory_slot *dont)
7091{
7092 int i;
7093
d89cc617
TY		 7094 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7095 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7096 kvm_kvfree(free->arch.rmap[i]);
7097 free->arch.rmap[i] = NULL;
77d11309 7098 }
d89cc617
TY		 7099 if (i == 0)
7100 continue;
7101
7102 if (!dont || free->arch.lpage_info[i - 1] !=
7103 dont->arch.lpage_info[i - 1]) {
7104 kvm_kvfree(free->arch.lpage_info[i - 1]);
7105 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7106 }
7107 }
7108}
7109
5587027c
AK		 7110int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7111 unsigned long npages)
db3fe4eb
TY		 7112{
7113 int i;
7114
d89cc617 7115 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7116 unsigned long ugfn;
7117 int lpages;
d89cc617 7118 int level = i + 1;
db3fe4eb
TY		 7119
7120 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7121 slot->base_gfn, level) + 1;
7122
d89cc617
TY		 7123 slot->arch.rmap[i] =
7124 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7125 if (!slot->arch.rmap[i])
77d11309 7126 goto out_free;
d89cc617
TY		 7127 if (i == 0)
7128 continue;
77d11309 7129
d89cc617
TY		 7130 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7131 sizeof(*slot->arch.lpage_info[i - 1]));
7132 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7133 goto out_free;
7134
7135 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7136 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7137 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7138 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7139 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7140 /*
7141 * If the gfn and userspace address are not aligned wrt each
7142 * other, or if explicitly asked to, disable large page
7143 * support for this slot
7144 */
7145 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7146 !kvm_largepages_enabled()) {
7147 unsigned long j;
7148
7149 for (j = 0; j < lpages; ++j)
d89cc617 7150 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7151 }
7152 }
7153
7154 return 0;
7155
7156out_free:
d89cc617
TY		 7157 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7158 kvm_kvfree(slot->arch.rmap[i]);
7159 slot->arch.rmap[i] = NULL;
7160 if (i == 0)
7161 continue;
7162
7163 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7164 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7165 }
7166 return -ENOMEM;
7167}
7168
e59dbe09
TY		 7169void kvm_arch_memslots_updated(struct kvm *kvm)
7170{
e6dff7d1
TY		 7171 /*
7172 * memslots->generation has been incremented.
7173 * mmio generation may have reached its maximum value.
7174 */
7175 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7176}
7177
f7784b8e
MT		 7178int kvm_arch_prepare_memory_region(struct kvm *kvm,
7179 struct kvm_memory_slot *memslot,
f7784b8e 7180 struct kvm_userspace_memory_region *mem,
7b6195a9 7181 enum kvm_mr_change change)
0de10343 7182{
7a905b14
TY		 7183 /*
7184 * Only private memory slots need to be mapped here since
7185 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7186 */
7b6195a9 7187 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7188 unsigned long userspace_addr;
604b38ac 7189
7a905b14
TY		 7190 /*
7191 * MAP_SHARED to prevent internal slot pages from being moved
7192 * by fork()/COW.
7193 */
7b6195a9 7194 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7195 PROT_READ | PROT_WRITE,
7196 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7197
7a905b14
TY		 7198 if (IS_ERR((void *)userspace_addr))
7199 return PTR_ERR((void *)userspace_addr);
604b38ac 7200
7a905b14 7201 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7202 }
7203
f7784b8e
MT		 7204 return 0;
7205}
7206
7207void kvm_arch_commit_memory_region(struct kvm *kvm,
7208 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7209 const struct kvm_memory_slot *old,
7210 enum kvm_mr_change change)
f7784b8e
MT		 7211{
7212
8482644a 7213 int nr_mmu_pages = 0;
f7784b8e 7214
8482644a 7215 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7216 int ret;
7217
8482644a
TY		 7218 ret = vm_munmap(old->userspace_addr,
7219 old->npages * PAGE_SIZE);
f7784b8e
MT		 7220 if (ret < 0)
7221 printk(KERN_WARNING
7222 "kvm_vm_ioctl_set_memory_region: "
7223 "failed to munmap memory\n");
7224 }
7225
48c0e4e9
XG		 7226 if (!kvm->arch.n_requested_mmu_pages)
7227 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7228
48c0e4e9 7229 if (nr_mmu_pages)
0de10343 7230 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7231 /*
7232 * Write protect all pages for dirty logging.
7233 * Existing largepage mappings are destroyed here and new ones will
7234 * not be created until the end of the logging.
7235 */
8482644a 7236 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7237 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7238}
1d737c8a 7239
2df72e9b 7240void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7241{
6ca18b69 7242 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7243}
7244
2df72e9b
MT		 7245void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7246 struct kvm_memory_slot *slot)
7247{
6ca18b69 7248 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7249}
7250
1d737c8a
ZX		 7251int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7252{
af585b92
GN		 7253 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7254 !vcpu->arch.apf.halted)
7255 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7256 || kvm_apic_has_events(vcpu)
6aef266c 7257 || vcpu->arch.pv.pv_unhalted
7460fb4a 7258 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7259 (kvm_arch_interrupt_allowed(vcpu) &&
7260 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7261}
5736199a 7262
b6d33834 7263int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7264{
b6d33834 7265 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7266}
78646121
GN		 7267
7268int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7269{
7270 return kvm_x86_ops->interrupt_allowed(vcpu);
7271}
229456fc 7272
f92653ee
JK		 7273bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7274{
7275 unsigned long current_rip = kvm_rip_read(vcpu) +
7276 get_segment_base(vcpu, VCPU_SREG_CS);
7277
7278 return current_rip == linear_rip;
7279}
7280EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7281
94fe45da
JK		 7282unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7283{
7284 unsigned long rflags;
7285
7286 rflags = kvm_x86_ops->get_rflags(vcpu);
7287 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7288 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7289 return rflags;
7290}
7291EXPORT_SYMBOL_GPL(kvm_get_rflags);
7292
7293void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7294{
7295 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7296 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7297 rflags |= X86_EFLAGS_TF;
94fe45da 7298 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7299 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7300}
7301EXPORT_SYMBOL_GPL(kvm_set_rflags);
7302
56028d08
GN		 7303void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7304{
7305 int r;
7306
fb67e14f 7307 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7308 work->wakeup_all)
56028d08
GN		 7309 return;
7310
7311 r = kvm_mmu_reload(vcpu);
7312 if (unlikely(r))
7313 return;
7314
fb67e14f
XG		 7315 if (!vcpu->arch.mmu.direct_map &&
7316 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7317 return;
7318
56028d08
GN		 7319 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7320}
7321
af585b92
GN		 7322static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7323{
7324 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7325}
7326
7327static inline u32 kvm_async_pf_next_probe(u32 key)
7328{
7329 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7330}
7331
7332static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7333{
7334 u32 key = kvm_async_pf_hash_fn(gfn);
7335
7336 while (vcpu->arch.apf.gfns[key] != ~0)
7337 key = kvm_async_pf_next_probe(key);
7338
7339 vcpu->arch.apf.gfns[key] = gfn;
7340}
7341
7342static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7343{
7344 int i;
7345 u32 key = kvm_async_pf_hash_fn(gfn);
7346
7347 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7348 (vcpu->arch.apf.gfns[key] != gfn &&
7349 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7350 key = kvm_async_pf_next_probe(key);
7351
7352 return key;
7353}
7354
7355bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7356{
7357 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7358}
7359
7360static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7361{
7362 u32 i, j, k;
7363
7364 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7365 while (true) {
7366 vcpu->arch.apf.gfns[i] = ~0;
7367 do {
7368 j = kvm_async_pf_next_probe(j);
7369 if (vcpu->arch.apf.gfns[j] == ~0)
7370 return;
7371 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7372 /*
7373 * k lies cyclically in ]i,j]
7374 * | i.k.j |
7375 * |....j i.k.| or |.k..j i...|
7376 */
7377 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7378 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7379 i = j;
7380 }
7381}
7382
7c90705b
GN		 7383static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7384{
7385
7386 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7387 sizeof(val));
7388}
7389
af585b92
GN		 7390void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7391 struct kvm_async_pf *work)
7392{
6389ee94
AK		 7393 struct x86_exception fault;
7394
7c90705b 7395 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7396 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7397
7398 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7399 (vcpu->arch.apf.send_user_only &&
7400 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7401 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7402 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7403 fault.vector = PF_VECTOR;
7404 fault.error_code_valid = true;
7405 fault.error_code = 0;
7406 fault.nested_page_fault = false;
7407 fault.address = work->arch.token;
7408 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7409 }
af585b92
GN		 7410}
7411
7412void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7413 struct kvm_async_pf *work)
7414{
6389ee94
AK		 7415 struct x86_exception fault;
7416
7c90705b 7417 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7418 if (work->wakeup_all)
7c90705b
GN		 7419 work->arch.token = ~0; /* broadcast wakeup */
7420 else
7421 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7422
7423 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7424 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7425 fault.vector = PF_VECTOR;
7426 fault.error_code_valid = true;
7427 fault.error_code = 0;
7428 fault.nested_page_fault = false;
7429 fault.address = work->arch.token;
7430 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7431 }
e6d53e3b 7432 vcpu->arch.apf.halted = false;
a4fa1635 7433 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7434}
7435
7436bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7437{
7438 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7439 return true;
7440 else
7441 return !kvm_event_needs_reinjection(vcpu) &&
7442 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7443}
7444
e0f0bbc5
AW		 7445void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7446{
7447 atomic_inc(&kvm->arch.noncoherent_dma_count);
7448}
7449EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7450
7451void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7452{
7453 atomic_dec(&kvm->arch.noncoherent_dma_count);
7454}
7455EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7456
7457bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7458{
7459 return atomic_read(&kvm->arch.noncoherent_dma_count);
7460}
7461EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7462
229456fc
MT		 7463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7475EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git