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ppc4xx: Add functionality to GPIO support
[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c
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887e2ec9 1/*
5a5958b7 2 * (C) Copyright 2006-2007
887e2ec9
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
511d0c72 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR		 26#include <libfdt.h>
27#include <fdt_support.h>
28#include <ppc440.h>
887e2ec9 29#include <asm/processor.h>
5a5958b7 30#include <asm/io.h>
887e2ec9
SR		 31
32DECLARE_GLOBAL_DATA_PTR;
33
34extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
35
1b3c360c
SR		 36ulong flash_get_size (ulong base, int banknum);
37
887e2ec9
SR		 38int board_early_init_f(void)
39{
a78bc443
SR		 40 u32 sdr0_cust0;
41 u32 sdr0_pfc1, sdr0_pfc2;
42 u32 reg;
887e2ec9
SR		 43
44 mtdcr(ebccfga, xbcfg);
45 mtdcr(ebccfgd, 0xb8400000);
46
47 /*--------------------------------------------------------------------
48 * Setup the GPIO pins
49 *-------------------------------------------------------------------*/
50 /* test-only: take GPIO init from pcs440ep ???? in config file */
d3471173
LJ		 51 out_be32((u32 *) GPIO0_OR, 0x00000000);
52 out_be32((u32 *) GPIO0_TCR, 0x0000000f);
53 out_be32((u32 *) GPIO0_OSRL, 0x50015400);
54 out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
55 out_be32((u32 *) GPIO0_TSRL, 0x50015400);
56 out_be32((u32 *) GPIO0_TSRH, 0x55005000);
57 out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
58 out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
59 out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
60 out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
61 out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
62 out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
63
64 out_be32((u32 *) GPIO1_OR, 0x00000000);
65 out_be32((u32 *) GPIO1_TCR, 0xc2000000);
66 out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
67 out_be32((u32 *) GPIO1_OSRH, 0x00000000);
68 out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
69 out_be32((u32 *) GPIO1_TSRH, 0x00000000);
70 out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
71 out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
72 out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
73 out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
74 out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
75 out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
887e2ec9
SR		 76
77 /*--------------------------------------------------------------------
78 * Setup the interrupt controller polarities, triggers, etc.
79 *-------------------------------------------------------------------*/
80 mtdcr(uic0sr, 0xffffffff); /* clear all */
81 mtdcr(uic0er, 0x00000000); /* disable all */
82 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
83 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
84 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
85 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
86 mtdcr(uic0sr, 0xffffffff); /* clear all */
87
88 mtdcr(uic1sr, 0xffffffff); /* clear all */
89 mtdcr(uic1er, 0x00000000); /* disable all */
90 mtdcr(uic1cr, 0x00000000); /* all non-critical */
91 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
92 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
93 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
94 mtdcr(uic1sr, 0xffffffff); /* clear all */
95
96 mtdcr(uic2sr, 0xffffffff); /* clear all */
97 mtdcr(uic2er, 0x00000000); /* disable all */
98 mtdcr(uic2cr, 0x00000000); /* all non-critical */
99 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
100 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
101 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
102 mtdcr(uic2sr, 0xffffffff); /* clear all */
103
104 /* 50MHz tmrclk */
d3471173 105 out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR		 106
107 /* clear write protects */
d3471173 108 out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR		 109
110 /* enable Ethernet */
d3471173 111 out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR		 112
113 /* enable USB device */
d3471173 114 out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
887e2ec9
SR		 115
116 /* select Ethernet pins */
117 mfsdr(SDR0_PFC1, sdr0_pfc1);
118 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
119 mfsdr(SDR0_PFC2, sdr0_pfc2);
120 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
121 mtsdr(SDR0_PFC2, sdr0_pfc2);
122 mtsdr(SDR0_PFC1, sdr0_pfc1);
123
124 /* PCI arbiter enabled */
125 mfsdr(sdr_pci0, reg);
126 mtsdr(sdr_pci0, 0x80000000 | reg);
127
128 /* setup NAND FLASH */
129 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 130 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR		 131 SDR0_CUST0_NDFC_ENABLE |
132 SDR0_CUST0_NDFC_BW_8_BIT |
133 SDR0_CUST0_NDFC_ARE_MASK |
134 (0x80000000 >> (28 + CFG_NAND_CS));
511d0c72 135 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR		 136
137 return 0;
138}
139
140/*---------------------------------------------------------------------------+
141 | misc_init_r.
142 +---------------------------------------------------------------------------*/
143int misc_init_r(void)
144{
145 uint pbcr;
146 int size_val = 0;
a78bc443 147 u32 reg;
854bc8da 148#ifdef CONFIG_440EPX
887e2ec9
SR		 149 unsigned long usb2d0cr = 0;
150 unsigned long usb2phy0cr, usb2h0cr = 0;
151 unsigned long sdr0_pfc1;
152 char *act = getenv("usbact");
854bc8da 153#endif
887e2ec9
SR		 154
155 /*
156 * FLASH stuff...
157 */
158
159 /* Re-do sizing to get full correct info */
1b3c360c
SR		 160
161 /* adjust flash start and offset */
162 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
163 gd->bd->bi_flashoffset = 0;
164
887e2ec9
SR		 165#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
166 mtdcr(ebccfga, pb3cr);
167#else
168 mtdcr(ebccfga, pb0cr);
169#endif
170 pbcr = mfdcr(ebccfgd);
171 switch (gd->bd->bi_flashsize) {
172 case 1 << 20:
173 size_val = 0;
174 break;
175 case 2 << 20:
176 size_val = 1;
177 break;
178 case 4 << 20:
179 size_val = 2;
180 break;
181 case 8 << 20:
182 size_val = 3;
183 break;
184 case 16 << 20:
185 size_val = 4;
186 break;
187 case 32 << 20:
188 size_val = 5;
189 break;
190 case 64 << 20:
191 size_val = 6;
192 break;
193 case 128 << 20:
194 size_val = 7;
195 break;
196 }
197 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
198#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
199 mtdcr(ebccfga, pb3cr);
200#else
201 mtdcr(ebccfga, pb0cr);
202#endif
203 mtdcr(ebccfgd, pbcr);
204
1b3c360c
SR		 205 /*
206 * Re-check to get correct base address
207 */
208 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9
SR		 209
210#ifdef CFG_ENV_IS_IN_FLASH
211 /* Monitor protection ON by default */
212 (void)flash_protect(FLAG_PROTECT_SET,
213 -CFG_MONITOR_LEN,
214 0xffffffff,
215 &flash_info[0]);
216
217 /* Env protection ON by default */
218 (void)flash_protect(FLAG_PROTECT_SET,
219 CFG_ENV_ADDR_REDUND,
220 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
221 &flash_info[0]);
222#endif
223
224 /*
225 * USB suff...
226 */
854bc8da 227#ifdef CONFIG_440EPX
887e2ec9
SR		 228 if (act == NULL || strcmp(act, "hostdev") == 0) {
229 /* SDR Setting */
511d0c72 230 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 231 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 232 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
233 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 234
235 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
236 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72
WD		 237 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
238 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 239 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 240 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 241 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 242 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 243 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 244 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 245
246 /* An 8-bit/60MHz interface is the only possible alternative
247 when connecting the Device to the PHY */
511d0c72
WD		 248 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
249 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 250
511d0c72
WD		 251 /* To enable the USB 2.0 Device function through the UTMI interface */
252 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
253 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
887e2ec9 254
511d0c72
WD		 255 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
256 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
887e2ec9 257
511d0c72 258 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 259 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 260 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
261 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 262
263 /*clear resets*/
264 udelay (1000);
265 mtsdr(SDR0_SRST1, 0x00000000);
266 udelay (1000);
267 mtsdr(SDR0_SRST0, 0x00000000);
268
269 printf("USB: Host(int phy) Device(ext phy)\n");
270
271 } else if (strcmp(act, "dev") == 0) {
272 /*-------------------PATCH-------------------------------*/
273 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
274
275 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
276 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
277 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 278 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 279 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 280 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 281 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 282 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 283 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
284
285 udelay (1000);
286 mtsdr(SDR0_SRST1, 0x672c6000);
287
288 udelay (1000);
289 mtsdr(SDR0_SRST0, 0x00000080);
290
291 udelay (1000);
292 mtsdr(SDR0_SRST1, 0x60206000);
293
294 *(unsigned int *)(0xe0000350) = 0x00000001;
295
296 udelay (1000);
297 mtsdr(SDR0_SRST1, 0x60306000);
298 /*-------------------PATCH-------------------------------*/
299
300 /* SDR Setting */
511d0c72 301 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 302 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 303 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 304 mfsdr(SDR0_PFC1, sdr0_pfc1);
305
306 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
307 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72 308 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
887e2ec9
SR		 309 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
310 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 311 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
887e2ec9 312 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 313 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
887e2ec9 314 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 315 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
887e2ec9
SR		 316
317 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
511d0c72 318 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
887e2ec9
SR		 319
320 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
511d0c72 321 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
887e2ec9
SR		 322
323 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
511d0c72 324 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
887e2ec9 325
511d0c72
WD		 326 mtsdr(SDR0_USB2H0CR, usb2h0cr);
327 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 328 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 329 mtsdr(SDR0_PFC1, sdr0_pfc1);
330
331 /*clear resets*/
332 udelay (1000);
333 mtsdr(SDR0_SRST1, 0x00000000);
334 udelay (1000);
335 mtsdr(SDR0_SRST0, 0x00000000);
336
337 printf("USB: Device(int phy)\n");
338 }
854bc8da 339#endif /* CONFIG_440EPX */
887e2ec9 340
8ce16f55
JO		 341 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
342 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
343 mtsdr(SDR0_SRST1, reg);
344
a78bc443
SR		 345 /*
346 * Clear PLB4A0_ACR[WRP]
347 * This fix will make the MAL burst disabling patch for the Linux
348 * EMAC driver obsolete.
349 */
350 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
351 mtdcr(plb4_acr, reg);
352
887e2ec9
SR		 353 return 0;
354}
355
356int checkboard(void)
357{
358 char *s = getenv("serial#");
e0b9ea8c
SR		 359 u8 rev;
360 u8 val;
887e2ec9 361
854bc8da 362#ifdef CONFIG_440EPX
887e2ec9 363 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR		 364#else
365 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
366#endif
e0b9ea8c 367
5a5958b7
SR		 368 rev = in_8((void *)(CFG_BCSR_BASE + 0));
369 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
e0b9ea8c
SR		 370 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
371
887e2ec9
SR		 372 if (s != NULL) {
373 puts(", serial# ");
374 puts(s);
375 }
376 putc('\n');
377
378 return (0);
379}
380
381#if defined(CFG_DRAM_TEST)
382int testdram(void)
383{
384 unsigned long *mem = (unsigned long *)0;
385 const unsigned long kend = (1024 / sizeof(unsigned long));
386 unsigned long k, n;
387
388 mtmsr(0);
389
390 for (k = 0; k < CFG_MBYTES_SDRAM;
391 ++k, mem += (1024 / sizeof(unsigned long))) {
392 if ((k & 1023) == 0) {
393 printf("%3d MB\r", k / 1024);
394 }
395
396 memset(mem, 0xaaaaaaaa, 1024);
397 for (n = 0; n < kend; ++n) {
398 if (mem[n] != 0xaaaaaaaa) {
399 printf("SDRAM test fails at: %08x\n",
400 (uint) & mem[n]);
401 return 1;
402 }
403 }
404
405 memset(mem, 0x55555555, 1024);
406 for (n = 0; n < kend; ++n) {
407 if (mem[n] != 0x55555555) {
408 printf("SDRAM test fails at: %08x\n",
409 (uint) & mem[n]);
410 return 1;
411 }
412 }
413 }
414 printf("SDRAM test passes\n");
415 return 0;
416}
417#endif
418
419/*************************************************************************
420 * pci_pre_init
421 *
422 * This routine is called just prior to registering the hose and gives
423 * the board the opportunity to check things. Returning a value of zero
424 * indicates that things are bad & PCI initialization should be aborted.
425 *
426 * Different boards may wish to customize the pci controller structure
427 * (add regions, override default access routines, etc) or perform
428 * certain pre-initialization actions.
429 *
430 ************************************************************************/
466fff1a 431#if defined(CONFIG_PCI)
887e2ec9
SR		 432int pci_pre_init(struct pci_controller *hose)
433{
434 unsigned long addr;
887e2ec9
SR		 435
436 /*-------------------------------------------------------------------------+
437 | Set priority for all PLB3 devices to 0.
438 | Set PLB3 arbiter to fair mode.
439 +-------------------------------------------------------------------------*/
440 mfsdr(sdr_amp1, addr);
441 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
442 addr = mfdcr(plb3_acr);
443 mtdcr(plb3_acr, addr | 0x80000000);
444
445 /*-------------------------------------------------------------------------+
446 | Set priority for all PLB4 devices to 0.
447 +-------------------------------------------------------------------------*/
448 mfsdr(sdr_amp0, addr);
449 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
450 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
451 mtdcr(plb4_acr, addr);
452
453 /*-------------------------------------------------------------------------+
454 | Set Nebula PLB4 arbiter to fair mode.
455 +-------------------------------------------------------------------------*/
456 /* Segment0 */
457 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
458 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
459 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
460 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
461 mtdcr(plb0_acr, addr);
462
463 /* Segment1 */
464 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
465 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
466 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
467 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
468 mtdcr(plb1_acr, addr);
469
470 return 1;
471}
466fff1a 472#endif /* defined(CONFIG_PCI) */
887e2ec9
SR		 473
474/*************************************************************************
475 * pci_target_init
476 *
477 * The bootstrap configuration provides default settings for the pci
478 * inbound map (PIM). But the bootstrap config choices are limited and
479 * may not be sufficient for a given board.
480 *
481 ************************************************************************/
482#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
483void pci_target_init(struct pci_controller *hose)
484{
485 /*--------------------------------------------------------------------------+
486 * Set up Direct MMIO registers
487 *--------------------------------------------------------------------------*/
488 /*--------------------------------------------------------------------------+
489 | PowerPC440EPX PCI Master configuration.
490 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
491 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
492 | Use byte reversed out routines to handle endianess.
493 | Make this region non-prefetchable.
494 +--------------------------------------------------------------------------*/
495 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
496 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
497 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
498 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
499 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
500
501 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
502 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
503 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
504 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
505 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
506
507 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
508 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
509 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
510 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
511
512 /*--------------------------------------------------------------------------+
513 * Set up Configuration registers
514 *--------------------------------------------------------------------------*/
515
516 /* Program the board's subsystem id/vendor id */
517 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
518 CFG_PCI_SUBSYS_VENDORID);
519 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
520
521 /* Configure command register as bus master */
522 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
523
524 /* 240nS PCI clock */
525 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
526
527 /* No error reporting */
528 pci_write_config_word(0, PCI_ERREN, 0);
529
530 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
531
532}
533#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
534
535/*************************************************************************
536 * pci_master_init
537 *
538 ************************************************************************/
539#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
540void pci_master_init(struct pci_controller *hose)
541{
542 unsigned short temp_short;
543
544 /*--------------------------------------------------------------------------+
545 | Write the PowerPC440 EP PCI Configuration regs.
546 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
547 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
548 +--------------------------------------------------------------------------*/
549 pci_read_config_word(0, PCI_COMMAND, &temp_short);
550 pci_write_config_word(0, PCI_COMMAND,
551 temp_short | PCI_COMMAND_MASTER |
552 PCI_COMMAND_MEMORY);
553}
554#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
555
556/*************************************************************************
557 * is_pci_host
558 *
559 * This routine is called to determine if a pci scan should be
560 * performed. With various hardware environments (especially cPCI and
561 * PPMC) it's insufficient to depend on the state of the arbiter enable
562 * bit in the strap register, or generic host/adapter assumptions.
563 *
564 * Rather than hard-code a bad assumption in the general 440 code, the
565 * 440 pci code requires the board to decide at runtime.
566 *
567 * Return 0 for adapter mode, non-zero for host (monarch) mode.
568 *
569 *
570 ************************************************************************/
571#if defined(CONFIG_PCI)
572int is_pci_host(struct pci_controller *hose)
573{
574 /* Cactus is always configured as host. */
575 return (1);
576}
577#endif /* defined(CONFIG_PCI) */
a11e0696
IL		 578#if defined(CONFIG_POST)
579/*
580 * Returns 1 if keys pressed to start the power-on long-running tests
581 * Called from board_init_f().
582 */
583int post_hotkeys_pressed(void)
584{
585 return 0; /* No hotkeys supported */
586}
587#endif /* CONFIG_POST */
13628884
SR		 588
589#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
590void ft_board_setup(void *blob, bd_t *bd)
591{
592 u32 val[4];
593 int rc;
594
595 ft_cpu_setup(blob, bd);
596
597 /* Fixup NOR mapping */
598 val[0] = 0; /* chip select number */
599 val[1] = 0; /* always 0 */
600 val[2] = gd->bd->bi_flashstart;
601 val[3] = gd->bd->bi_flashsize;
602 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
603 val, sizeof(val), 1);
604 if (rc)
605 printf("Unable to update property NOR mapping, err=%s\n",
606 fdt_strerror(rc));
607}
608#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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