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Commit | Line | Data |
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887e2ec9 | 1 | /* |
5a5958b7 | 2 | * (C) Copyright 2006-2007 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
511d0c72 | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 SR |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
13628884 SR |
26 | #include <libfdt.h> |
27 | #include <fdt_support.h> | |
28 | #include <ppc440.h> | |
b05e8bf5 | 29 | #include <asm/gpio.h> |
887e2ec9 | 30 | #include <asm/processor.h> |
5a5958b7 | 31 | #include <asm/io.h> |
887e2ec9 SR |
32 | |
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
36 | ||
1b3c360c SR |
37 | ulong flash_get_size (ulong base, int banknum); |
38 | ||
887e2ec9 SR |
39 | int board_early_init_f(void) |
40 | { | |
a78bc443 SR |
41 | u32 sdr0_cust0; |
42 | u32 sdr0_pfc1, sdr0_pfc2; | |
43 | u32 reg; | |
887e2ec9 SR |
44 | |
45 | mtdcr(ebccfga, xbcfg); | |
46 | mtdcr(ebccfgd, 0xb8400000); | |
47 | ||
887e2ec9 SR |
48 | /*-------------------------------------------------------------------- |
49 | * Setup the interrupt controller polarities, triggers, etc. | |
50 | *-------------------------------------------------------------------*/ | |
51 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
52 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
53 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
54 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ | |
55 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
56 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
57 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
58 | ||
59 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
60 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
61 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
62 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
63 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
64 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
65 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
66 | ||
67 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
68 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
69 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
70 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
71 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
72 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
73 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
74 | ||
75 | /* 50MHz tmrclk */ | |
d3471173 | 76 | out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00); |
887e2ec9 SR |
77 | |
78 | /* clear write protects */ | |
d3471173 | 79 | out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00); |
887e2ec9 SR |
80 | |
81 | /* enable Ethernet */ | |
d3471173 | 82 | out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00); |
887e2ec9 SR |
83 | |
84 | /* enable USB device */ | |
d3471173 | 85 | out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20); |
887e2ec9 SR |
86 | |
87 | /* select Ethernet pins */ | |
88 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
89 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; | |
90 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
91 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; | |
92 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
93 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
94 | ||
95 | /* PCI arbiter enabled */ | |
96 | mfsdr(sdr_pci0, reg); | |
97 | mtsdr(sdr_pci0, 0x80000000 | reg); | |
98 | ||
99 | /* setup NAND FLASH */ | |
100 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 101 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
102 | SDR0_CUST0_NDFC_ENABLE | |
103 | SDR0_CUST0_NDFC_BW_8_BIT | | |
104 | SDR0_CUST0_NDFC_ARE_MASK | | |
105 | (0x80000000 >> (28 + CFG_NAND_CS)); | |
511d0c72 | 106 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
107 | |
108 | return 0; | |
109 | } | |
110 | ||
111 | /*---------------------------------------------------------------------------+ | |
112 | | misc_init_r. | |
113 | +---------------------------------------------------------------------------*/ | |
114 | int misc_init_r(void) | |
115 | { | |
116 | uint pbcr; | |
117 | int size_val = 0; | |
a78bc443 | 118 | u32 reg; |
854bc8da | 119 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
120 | unsigned long usb2d0cr = 0; |
121 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
122 | unsigned long sdr0_pfc1; | |
123 | char *act = getenv("usbact"); | |
854bc8da | 124 | #endif |
887e2ec9 SR |
125 | |
126 | /* | |
127 | * FLASH stuff... | |
128 | */ | |
129 | ||
130 | /* Re-do sizing to get full correct info */ | |
1b3c360c SR |
131 | |
132 | /* adjust flash start and offset */ | |
133 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
134 | gd->bd->bi_flashoffset = 0; | |
135 | ||
887e2ec9 SR |
136 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
137 | mtdcr(ebccfga, pb3cr); | |
138 | #else | |
139 | mtdcr(ebccfga, pb0cr); | |
140 | #endif | |
141 | pbcr = mfdcr(ebccfgd); | |
142 | switch (gd->bd->bi_flashsize) { | |
143 | case 1 << 20: | |
144 | size_val = 0; | |
145 | break; | |
146 | case 2 << 20: | |
147 | size_val = 1; | |
148 | break; | |
149 | case 4 << 20: | |
150 | size_val = 2; | |
151 | break; | |
152 | case 8 << 20: | |
153 | size_val = 3; | |
154 | break; | |
155 | case 16 << 20: | |
156 | size_val = 4; | |
157 | break; | |
158 | case 32 << 20: | |
159 | size_val = 5; | |
160 | break; | |
161 | case 64 << 20: | |
162 | size_val = 6; | |
163 | break; | |
164 | case 128 << 20: | |
165 | size_val = 7; | |
166 | break; | |
167 | } | |
168 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
169 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
170 | mtdcr(ebccfga, pb3cr); | |
171 | #else | |
172 | mtdcr(ebccfga, pb0cr); | |
173 | #endif | |
174 | mtdcr(ebccfgd, pbcr); | |
175 | ||
1b3c360c SR |
176 | /* |
177 | * Re-check to get correct base address | |
178 | */ | |
179 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 SR |
180 | |
181 | #ifdef CFG_ENV_IS_IN_FLASH | |
182 | /* Monitor protection ON by default */ | |
183 | (void)flash_protect(FLAG_PROTECT_SET, | |
184 | -CFG_MONITOR_LEN, | |
185 | 0xffffffff, | |
186 | &flash_info[0]); | |
187 | ||
188 | /* Env protection ON by default */ | |
189 | (void)flash_protect(FLAG_PROTECT_SET, | |
190 | CFG_ENV_ADDR_REDUND, | |
191 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
192 | &flash_info[0]); | |
193 | #endif | |
194 | ||
195 | /* | |
196 | * USB suff... | |
197 | */ | |
854bc8da | 198 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
199 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
200 | /* SDR Setting */ | |
511d0c72 | 201 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 202 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
203 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
204 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
205 | |
206 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
207 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
511d0c72 WD |
208 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
209 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
887e2ec9 | 210 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
511d0c72 | 211 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
887e2ec9 | 212 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 213 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
887e2ec9 | 214 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 215 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
887e2ec9 SR |
216 | |
217 | /* An 8-bit/60MHz interface is the only possible alternative | |
218 | when connecting the Device to the PHY */ | |
511d0c72 WD |
219 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
220 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
887e2ec9 | 221 | |
511d0c72 WD |
222 | /* To enable the USB 2.0 Device function through the UTMI interface */ |
223 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
224 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ | |
887e2ec9 | 225 | |
511d0c72 WD |
226 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
227 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ | |
887e2ec9 | 228 | |
511d0c72 | 229 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 230 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
231 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
232 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
233 | |
234 | /*clear resets*/ | |
235 | udelay (1000); | |
236 | mtsdr(SDR0_SRST1, 0x00000000); | |
237 | udelay (1000); | |
238 | mtsdr(SDR0_SRST0, 0x00000000); | |
239 | ||
240 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
241 | ||
242 | } else if (strcmp(act, "dev") == 0) { | |
243 | /*-------------------PATCH-------------------------------*/ | |
244 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
245 | ||
246 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
247 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
248 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
511d0c72 | 249 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
887e2ec9 | 250 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 251 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
887e2ec9 | 252 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 253 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
887e2ec9 SR |
254 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
255 | ||
256 | udelay (1000); | |
257 | mtsdr(SDR0_SRST1, 0x672c6000); | |
258 | ||
259 | udelay (1000); | |
260 | mtsdr(SDR0_SRST0, 0x00000080); | |
261 | ||
262 | udelay (1000); | |
263 | mtsdr(SDR0_SRST1, 0x60206000); | |
264 | ||
265 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
266 | ||
267 | udelay (1000); | |
268 | mtsdr(SDR0_SRST1, 0x60306000); | |
269 | /*-------------------PATCH-------------------------------*/ | |
270 | ||
271 | /* SDR Setting */ | |
511d0c72 | 272 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 | 273 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
f780b833 | 274 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
275 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
276 | ||
277 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
278 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
511d0c72 | 279 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
887e2ec9 SR |
280 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ |
281 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
511d0c72 | 282 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ |
887e2ec9 | 283 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 284 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ |
887e2ec9 | 285 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 286 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ |
887e2ec9 SR |
287 | |
288 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
511d0c72 | 289 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ |
887e2ec9 SR |
290 | |
291 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
511d0c72 | 292 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ |
887e2ec9 SR |
293 | |
294 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
511d0c72 | 295 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ |
887e2ec9 | 296 | |
511d0c72 WD |
297 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
298 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
f780b833 | 299 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
300 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
301 | ||
302 | /*clear resets*/ | |
303 | udelay (1000); | |
304 | mtsdr(SDR0_SRST1, 0x00000000); | |
305 | udelay (1000); | |
306 | mtsdr(SDR0_SRST0, 0x00000000); | |
307 | ||
308 | printf("USB: Device(int phy)\n"); | |
309 | } | |
854bc8da | 310 | #endif /* CONFIG_440EPX */ |
887e2ec9 | 311 | |
8ce16f55 JO |
312 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
313 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); | |
314 | mtsdr(SDR0_SRST1, reg); | |
315 | ||
a78bc443 SR |
316 | /* |
317 | * Clear PLB4A0_ACR[WRP] | |
318 | * This fix will make the MAL burst disabling patch for the Linux | |
319 | * EMAC driver obsolete. | |
320 | */ | |
321 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; | |
322 | mtdcr(plb4_acr, reg); | |
323 | ||
887e2ec9 SR |
324 | return 0; |
325 | } | |
326 | ||
327 | int checkboard(void) | |
328 | { | |
329 | char *s = getenv("serial#"); | |
e0b9ea8c SR |
330 | u8 rev; |
331 | u8 val; | |
887e2ec9 | 332 | |
854bc8da | 333 | #ifdef CONFIG_440EPX |
887e2ec9 | 334 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
335 | #else |
336 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
337 | #endif | |
e0b9ea8c | 338 | |
5a5958b7 SR |
339 | rev = in_8((void *)(CFG_BCSR_BASE + 0)); |
340 | val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; | |
e0b9ea8c SR |
341 | printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); |
342 | ||
887e2ec9 SR |
343 | if (s != NULL) { |
344 | puts(", serial# "); | |
345 | puts(s); | |
346 | } | |
347 | putc('\n'); | |
348 | ||
349 | return (0); | |
350 | } | |
351 | ||
352 | #if defined(CFG_DRAM_TEST) | |
353 | int testdram(void) | |
354 | { | |
355 | unsigned long *mem = (unsigned long *)0; | |
356 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
357 | unsigned long k, n; | |
358 | ||
359 | mtmsr(0); | |
360 | ||
361 | for (k = 0; k < CFG_MBYTES_SDRAM; | |
362 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
363 | if ((k & 1023) == 0) { | |
364 | printf("%3d MB\r", k / 1024); | |
365 | } | |
366 | ||
367 | memset(mem, 0xaaaaaaaa, 1024); | |
368 | for (n = 0; n < kend; ++n) { | |
369 | if (mem[n] != 0xaaaaaaaa) { | |
370 | printf("SDRAM test fails at: %08x\n", | |
371 | (uint) & mem[n]); | |
372 | return 1; | |
373 | } | |
374 | } | |
375 | ||
376 | memset(mem, 0x55555555, 1024); | |
377 | for (n = 0; n < kend; ++n) { | |
378 | if (mem[n] != 0x55555555) { | |
379 | printf("SDRAM test fails at: %08x\n", | |
380 | (uint) & mem[n]); | |
381 | return 1; | |
382 | } | |
383 | } | |
384 | } | |
385 | printf("SDRAM test passes\n"); | |
386 | return 0; | |
387 | } | |
388 | #endif | |
389 | ||
390 | /************************************************************************* | |
391 | * pci_pre_init | |
392 | * | |
393 | * This routine is called just prior to registering the hose and gives | |
394 | * the board the opportunity to check things. Returning a value of zero | |
395 | * indicates that things are bad & PCI initialization should be aborted. | |
396 | * | |
397 | * Different boards may wish to customize the pci controller structure | |
398 | * (add regions, override default access routines, etc) or perform | |
399 | * certain pre-initialization actions. | |
400 | * | |
401 | ************************************************************************/ | |
466fff1a | 402 | #if defined(CONFIG_PCI) |
887e2ec9 SR |
403 | int pci_pre_init(struct pci_controller *hose) |
404 | { | |
405 | unsigned long addr; | |
887e2ec9 SR |
406 | |
407 | /*-------------------------------------------------------------------------+ | |
408 | | Set priority for all PLB3 devices to 0. | |
409 | | Set PLB3 arbiter to fair mode. | |
410 | +-------------------------------------------------------------------------*/ | |
411 | mfsdr(sdr_amp1, addr); | |
412 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
413 | addr = mfdcr(plb3_acr); | |
414 | mtdcr(plb3_acr, addr | 0x80000000); | |
415 | ||
416 | /*-------------------------------------------------------------------------+ | |
417 | | Set priority for all PLB4 devices to 0. | |
418 | +-------------------------------------------------------------------------*/ | |
419 | mfsdr(sdr_amp0, addr); | |
420 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
421 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
422 | mtdcr(plb4_acr, addr); | |
423 | ||
424 | /*-------------------------------------------------------------------------+ | |
425 | | Set Nebula PLB4 arbiter to fair mode. | |
426 | +-------------------------------------------------------------------------*/ | |
427 | /* Segment0 */ | |
428 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
429 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
430 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
431 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
432 | mtdcr(plb0_acr, addr); | |
433 | ||
434 | /* Segment1 */ | |
435 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
436 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
437 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
438 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
439 | mtdcr(plb1_acr, addr); | |
440 | ||
441 | return 1; | |
442 | } | |
466fff1a | 443 | #endif /* defined(CONFIG_PCI) */ |
887e2ec9 SR |
444 | |
445 | /************************************************************************* | |
446 | * pci_target_init | |
447 | * | |
448 | * The bootstrap configuration provides default settings for the pci | |
449 | * inbound map (PIM). But the bootstrap config choices are limited and | |
450 | * may not be sufficient for a given board. | |
451 | * | |
452 | ************************************************************************/ | |
453 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
454 | void pci_target_init(struct pci_controller *hose) | |
455 | { | |
456 | /*--------------------------------------------------------------------------+ | |
457 | * Set up Direct MMIO registers | |
458 | *--------------------------------------------------------------------------*/ | |
459 | /*--------------------------------------------------------------------------+ | |
460 | | PowerPC440EPX PCI Master configuration. | |
461 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
462 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
463 | | Use byte reversed out routines to handle endianess. | |
464 | | Make this region non-prefetchable. | |
465 | +--------------------------------------------------------------------------*/ | |
466 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
467 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
468 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
469 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
470 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
471 | ||
472 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
473 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
474 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
475 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
476 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
477 | ||
478 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
479 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
480 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
481 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
482 | ||
483 | /*--------------------------------------------------------------------------+ | |
484 | * Set up Configuration registers | |
485 | *--------------------------------------------------------------------------*/ | |
486 | ||
487 | /* Program the board's subsystem id/vendor id */ | |
488 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
489 | CFG_PCI_SUBSYS_VENDORID); | |
490 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
491 | ||
492 | /* Configure command register as bus master */ | |
493 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
494 | ||
495 | /* 240nS PCI clock */ | |
496 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
497 | ||
498 | /* No error reporting */ | |
499 | pci_write_config_word(0, PCI_ERREN, 0); | |
500 | ||
501 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
502 | ||
503 | } | |
504 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
505 | ||
506 | /************************************************************************* | |
507 | * pci_master_init | |
508 | * | |
509 | ************************************************************************/ | |
510 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
511 | void pci_master_init(struct pci_controller *hose) | |
512 | { | |
513 | unsigned short temp_short; | |
514 | ||
515 | /*--------------------------------------------------------------------------+ | |
516 | | Write the PowerPC440 EP PCI Configuration regs. | |
517 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
518 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
519 | +--------------------------------------------------------------------------*/ | |
520 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
521 | pci_write_config_word(0, PCI_COMMAND, | |
522 | temp_short | PCI_COMMAND_MASTER | | |
523 | PCI_COMMAND_MEMORY); | |
524 | } | |
525 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
526 | ||
527 | /************************************************************************* | |
528 | * is_pci_host | |
529 | * | |
530 | * This routine is called to determine if a pci scan should be | |
531 | * performed. With various hardware environments (especially cPCI and | |
532 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
533 | * bit in the strap register, or generic host/adapter assumptions. | |
534 | * | |
535 | * Rather than hard-code a bad assumption in the general 440 code, the | |
536 | * 440 pci code requires the board to decide at runtime. | |
537 | * | |
538 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
539 | * | |
540 | * | |
541 | ************************************************************************/ | |
542 | #if defined(CONFIG_PCI) | |
543 | int is_pci_host(struct pci_controller *hose) | |
544 | { | |
545 | /* Cactus is always configured as host. */ | |
546 | return (1); | |
547 | } | |
548 | #endif /* defined(CONFIG_PCI) */ | |
a11e0696 IL |
549 | #if defined(CONFIG_POST) |
550 | /* | |
551 | * Returns 1 if keys pressed to start the power-on long-running tests | |
552 | * Called from board_init_f(). | |
553 | */ | |
554 | int post_hotkeys_pressed(void) | |
555 | { | |
556 | return 0; /* No hotkeys supported */ | |
557 | } | |
558 | #endif /* CONFIG_POST */ | |
13628884 SR |
559 | |
560 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
561 | void ft_board_setup(void *blob, bd_t *bd) | |
562 | { | |
563 | u32 val[4]; | |
564 | int rc; | |
565 | ||
566 | ft_cpu_setup(blob, bd); | |
567 | ||
568 | /* Fixup NOR mapping */ | |
569 | val[0] = 0; /* chip select number */ | |
570 | val[1] = 0; /* always 0 */ | |
571 | val[2] = gd->bd->bi_flashstart; | |
572 | val[3] = gd->bd->bi_flashsize; | |
573 | rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", | |
574 | val, sizeof(val), 1); | |
575 | if (rc) | |
576 | printf("Unable to update property NOR mapping, err=%s\n", | |
577 | fdt_strerror(rc)); | |
578 | } | |
579 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |