]>
Commit | Line | Data |
---|---|---|
ba56f625 | 1 | /*-----------------------------------------------------------------------------+ |
31773496 JB |
2 | * This source code is dual-licensed. You may use it under the terms of the |
3 | * GNU General Public License version 2, or under the license below. | |
ba56f625 | 4 | * |
265817c7 WD |
5 | * This source code has been made available to you by IBM on an AS-IS |
6 | * basis. Anyone receiving this source is licensed under IBM | |
7 | * copyrights to use it in any way he or she deems fit, including | |
8 | * copying it, modifying it, compiling it, and redistributing it either | |
9 | * with or without modifications. No license under IBM patents or | |
10 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 11 | * |
265817c7 WD |
12 | * Any user of this software should understand that IBM cannot provide |
13 | * technical support for this software and will not be responsible for | |
14 | * any consequences resulting from the use of this software. | |
ba56f625 | 15 | * |
265817c7 WD |
16 | * Any person who transfers this source code or any derivative work |
17 | * must include the IBM copyright notice, this paragraph, and the | |
18 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 19 | * |
265817c7 WD |
20 | * COPYRIGHT I B M CORPORATION 1995 |
21 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
22 | *-----------------------------------------------------------------------------*/ |
23 | /*-----------------------------------------------------------------------------+ | |
24 | * | |
265817c7 | 25 | * File Name: enetemac.c |
ba56f625 | 26 | * |
265817c7 | 27 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 28 | * |
265817c7 | 29 | * Author: Mark Wisner |
ba56f625 WD |
30 | * |
31 | * Change Activity- | |
32 | * | |
265817c7 WD |
33 | * Date Description of Change BY |
34 | * --------- --------------------- --- | |
35 | * 05-May-99 Created MKW | |
36 | * 27-Jun-99 Clean up JWB | |
37 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
38 | * 29-Jul-99 Added Full duplex support MKW | |
39 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
40 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
41 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
42 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
43 | * to avoid chaining maximum sized packets. Push starting | |
44 | * RX descriptor address up to the next cache line boundary. | |
45 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
46 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
ddc922ff | 47 | * EMAC0_RXM register. JWB |
265817c7 WD |
48 | * 12-Mar-01 anne-sophie.harnois@nextream.fr |
49 | * - Variables are compatible with those already defined in | |
50 | * include/net.h | |
51 | * - Receive buffer descriptor ring is used to send buffers | |
52 | * to the user | |
53 | * - Info print about send/received/handled packet number if | |
54 | * INFO_405_ENET is set | |
55 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
56 | * - MAL reset in "eth_halt" included | |
57 | * - Enet speed and duplex output now in one line | |
58 | * 08-May-01 stefan.roese@esd-electronics.com | |
59 | * - MAL error handling added (eth_init called again) | |
60 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
ddc922ff | 61 | * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex |
265817c7 WD |
62 | * 04-Jan-02 stefan.roese@esd-electronics.com |
63 | * - Wait for PHY auto negotiation to complete added | |
64 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - Bug fixed in waiting for auto negotiation to complete | |
66 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
67 | * - rx and tx buffer descriptors now allocated (no fixed address | |
68 | * used anymore) | |
69 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
70 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
71 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 72 | *-----------------------------------------------------------------------------* |
265817c7 WD |
73 | * 17-Nov-03 travis.sawyer@sandburst.com |
74 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
75 | * in the 440GX. This port should work with the 440GP | |
76 | * (2 EMACs) also | |
77 | * 15-Aug-05 sr@denx.de | |
78 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
79 | now handling all 4xx cpu's. | |
ba56f625 WD |
80 | *-----------------------------------------------------------------------------*/ |
81 | ||
82 | #include <config.h> | |
ba56f625 WD |
83 | #include <common.h> |
84 | #include <net.h> | |
85 | #include <asm/processor.h> | |
2d83476a | 86 | #include <asm/io.h> |
ff768cb1 SR |
87 | #include <asm/cache.h> |
88 | #include <asm/mmu.h> | |
ba56f625 | 89 | #include <commproc.h> |
b36df561 SR |
90 | #include <asm/ppc4xx.h> |
91 | #include <asm/ppc4xx-emac.h> | |
92 | #include <asm/ppc4xx-mal.h> | |
ba56f625 WD |
93 | #include <miiphy.h> |
94 | #include <malloc.h> | |
f0813ab1 | 95 | #include <linux/compiler.h> |
ba56f625 | 96 | |
3a1ed1e1 | 97 | #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) |
d6c61aab SR |
98 | #error "CONFIG_MII has to be defined!" |
99 | #endif | |
ba56f625 | 100 | |
265817c7 | 101 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
1338e6a8 | 102 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ |
ba56f625 | 103 | |
ba56f625 WD |
104 | /* Ethernet Transmit and Receive Buffers */ |
105 | /* AS.HARNOIS | |
106 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
107 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
108 | */ | |
265817c7 | 109 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
110 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
111 | ||
ba56f625 WD |
112 | /*-----------------------------------------------------------------------------+ |
113 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
114 | * Interrupt Controller). | |
115 | *-----------------------------------------------------------------------------*/ | |
d1631fe1 SR |
116 | #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) |
117 | ||
118 | #if defined(CONFIG_HAS_ETH3) | |
119 | #if !defined(CONFIG_440GX) | |
120 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
121 | UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
122 | #else | |
123 | /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ | |
124 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
125 | #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) | |
126 | #endif /* !defined(CONFIG_440GX) */ | |
127 | #elif defined(CONFIG_HAS_ETH2) | |
128 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ | |
129 | UIC_MASK(ETH_IRQ_NUM(2))) | |
130 | #elif defined(CONFIG_HAS_ETH1) | |
131 | #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) | |
132 | #else | |
133 | #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) | |
134 | #endif | |
135 | ||
136 | /* | |
137 | * Define a default version for UIC_ETHxB for non 440GX so that we can | |
138 | * use common code for all 4xx variants | |
139 | */ | |
140 | #if !defined(UIC_ETHxB) | |
141 | #define UIC_ETHxB 0 | |
142 | #endif | |
143 | ||
144 | #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) | |
145 | #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) | |
146 | #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) | |
147 | #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) | |
148 | #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) | |
149 | ||
150 | #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
151 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
152 | ||
153 | /* | |
154 | * We have 3 different interrupt types: | |
155 | * - MAL interrupts indicating successful transfer | |
156 | * - MAL error interrupts indicating MAL related errors | |
157 | * - EMAC interrupts indicating EMAC related errors | |
158 | * | |
159 | * All those interrupts can be on different UIC's, but since | |
160 | * now at least all interrupts from one type are on the same | |
161 | * UIC. Only exception is 440GX where the EMAC interrupts are | |
162 | * spread over two UIC's! | |
163 | */ | |
5de85140 SR |
164 | #if defined(CONFIG_440GX) |
165 | #define UIC_BASE_MAL UIC1_DCR_BASE | |
166 | #define UIC_BASE_MAL_ERR UIC2_DCR_BASE | |
167 | #define UIC_BASE_EMAC UIC2_DCR_BASE | |
168 | #define UIC_BASE_EMAC_B UIC3_DCR_BASE | |
169 | #else | |
d1631fe1 SR |
170 | #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) |
171 | #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) | |
172 | #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) | |
d1631fe1 SR |
173 | #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) |
174 | #endif | |
ba56f625 | 175 | |
d6c61aab | 176 | #undef INFO_4XX_ENET |
ba56f625 | 177 | |
265817c7 WD |
178 | #define BI_PHYMODE_NONE 0 |
179 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 180 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
181 | #define BI_PHYMODE_GMII 3 |
182 | #define BI_PHYMODE_RTBI 4 | |
183 | #define BI_PHYMODE_TBI 5 | |
dbbd1257 | 184 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 185 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 186 | defined(CONFIG_405EX) |
887e2ec9 SR |
187 | #define BI_PHYMODE_SMII 6 |
188 | #define BI_PHYMODE_MII 7 | |
8ac41e3e SR |
189 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
190 | #define BI_PHYMODE_RMII 8 | |
191 | #endif | |
887e2ec9 | 192 | #endif |
78d78236 | 193 | #define BI_PHYMODE_SGMII 9 |
3c74e32a | 194 | |
1941cce7 | 195 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 196 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 197 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 198 | defined(CONFIG_405EX) |
887e2ec9 SR |
199 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) |
200 | #endif | |
d6c61aab | 201 | |
8ac41e3e SR |
202 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
203 | #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) | |
204 | #endif | |
205 | ||
206 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
207 | #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ | |
208 | #else | |
209 | #define MAL_RX_CHAN_MUL 1 | |
210 | #endif | |
211 | ||
78d78236 VG |
212 | /*--------------------------------------------------------------------+ |
213 | * Fixed PHY (PHY-less) support for Ethernet Ports. | |
214 | *--------------------------------------------------------------------*/ | |
215 | ||
216 | /* | |
217 | * Some boards do not have a PHY for each ethernet port. These ports | |
218 | * are known as Fixed PHY (or PHY-less) ports. For such ports, set | |
219 | * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and | |
6d0f6bcf | 220 | * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and |
78d78236 VG |
221 | * duplex should be for these ports in the board configuration |
222 | * file. | |
223 | * | |
224 | * For Example: | |
225 | * #define CONFIG_FIXED_PHY 0xFFFFFFFF | |
226 | * | |
227 | * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY | |
228 | * #define CONFIG_PHY1_ADDR 1 | |
229 | * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY | |
230 | * #define CONFIG_PHY3_ADDR 3 | |
231 | * | |
6d0f6bcf | 232 | * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ |
78d78236 VG |
233 | * {devnum, speed, duplex}, |
234 | * | |
6d0f6bcf JCPV |
235 | * #define CONFIG_SYS_FIXED_PHY_PORTS \ |
236 | * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ | |
237 | * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) | |
78d78236 VG |
238 | */ |
239 | ||
240 | #ifndef CONFIG_FIXED_PHY | |
241 | #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ | |
242 | #endif | |
243 | ||
6d0f6bcf JCPV |
244 | #ifndef CONFIG_SYS_FIXED_PHY_PORTS |
245 | #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ | |
78d78236 VG |
246 | #endif |
247 | ||
248 | struct fixed_phy_port { | |
249 | unsigned int devnum; /* ethernet port */ | |
250 | unsigned int speed; /* specified speed 10,100 or 1000 */ | |
251 | unsigned int duplex; /* specified duplex FULL or HALF */ | |
252 | }; | |
253 | ||
254 | static const struct fixed_phy_port fixed_phy_port[] = { | |
6d0f6bcf | 255 | CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ |
78d78236 VG |
256 | }; |
257 | ||
ba56f625 WD |
258 | /*-----------------------------------------------------------------------------+ |
259 | * Global variables. TX and RX descriptors and buffers. | |
260 | *-----------------------------------------------------------------------------*/ | |
d6c61aab | 261 | |
1e25f957 SR |
262 | /* |
263 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
264 | * supported by the cpu) | |
353f2688 SR |
265 | * |
266 | * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the | |
267 | * EMAC count is possible. As it is needed for the Kilauea/Haleakala | |
268 | * 405EX/405EXr eval board, using the same binary. | |
1e25f957 | 269 | */ |
353f2688 SR |
270 | #if defined(CONFIG_BOARD_EMAC_COUNT) |
271 | #define LAST_EMAC_NUM board_emac_count() | |
272 | #else /* CONFIG_BOARD_EMAC_COUNT */ | |
1e25f957 SR |
273 | #if defined(CONFIG_HAS_ETH3) |
274 | #define LAST_EMAC_NUM 4 | |
275 | #elif defined(CONFIG_HAS_ETH2) | |
276 | #define LAST_EMAC_NUM 3 | |
277 | #elif defined(CONFIG_HAS_ETH1) | |
278 | #define LAST_EMAC_NUM 2 | |
279 | #else | |
280 | #define LAST_EMAC_NUM 1 | |
281 | #endif | |
353f2688 | 282 | #endif /* CONFIG_BOARD_EMAC_COUNT */ |
d6c61aab | 283 | |
5fb692ca SR |
284 | /* normal boards start with EMAC0 */ |
285 | #if !defined(CONFIG_EMAC_NR_START) | |
286 | #define CONFIG_EMAC_NR_START 0 | |
287 | #endif | |
288 | ||
ff768cb1 SR |
289 | #define MAL_RX_DESC_SIZE 2048 |
290 | #define MAL_TX_DESC_SIZE 2048 | |
291 | #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) | |
292 | ||
ba56f625 WD |
293 | /*-----------------------------------------------------------------------------+ |
294 | * Prototypes and externals. | |
295 | *-----------------------------------------------------------------------------*/ | |
296 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
297 | ||
298 | int enetInt (struct eth_device *dev); | |
299 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
300 | unsigned long uic, unsigned long maldef, | |
301 | unsigned long mal_errr); | |
302 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
303 | ||
63ff004c | 304 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
5700bb63 | 305 | extern int emac4xx_miiphy_read (const char *devname, unsigned char addr, |
63ff004c | 306 | unsigned char reg, unsigned short *value); |
5700bb63 | 307 | extern int emac4xx_miiphy_write (const char *devname, unsigned char addr, |
63ff004c | 308 | unsigned char reg, unsigned short value); |
d6c61aab | 309 | |
353f2688 SR |
310 | int board_emac_count(void); |
311 | ||
8ac41e3e SR |
312 | static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) |
313 | { | |
314 | #if defined(CONFIG_440SPE) || \ | |
315 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
316 | defined(CONFIG_405EX) | |
317 | u32 val; | |
318 | ||
d1c3b275 | 319 | mfsdr(SDR0_MFR, val); |
8ac41e3e | 320 | val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
d1c3b275 | 321 | mtsdr(SDR0_MFR, val); |
8ac41e3e SR |
322 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
323 | u32 val; | |
324 | ||
325 | mfsdr(SDR0_ETH_CFG, val); | |
326 | val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
327 | mtsdr(SDR0_ETH_CFG, val); | |
328 | #endif | |
329 | } | |
330 | ||
331 | static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) | |
332 | { | |
333 | #if defined(CONFIG_440SPE) || \ | |
334 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
335 | defined(CONFIG_405EX) | |
336 | u32 val; | |
337 | ||
d1c3b275 | 338 | mfsdr(SDR0_MFR, val); |
8ac41e3e | 339 | val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
d1c3b275 | 340 | mtsdr(SDR0_MFR, val); |
8ac41e3e SR |
341 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
342 | u32 val; | |
343 | ||
344 | mfsdr(SDR0_ETH_CFG, val); | |
345 | val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
346 | mtsdr(SDR0_ETH_CFG, val); | |
347 | #endif | |
348 | } | |
349 | ||
ba56f625 | 350 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 351 | | ppc_4xx_eth_halt |
ba56f625 | 352 | | Disable MAL channel, and EMACn |
ba56f625 | 353 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 354 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 355 | { |
d6c61aab | 356 | EMAC_4XX_HW_PST hw_p = dev->priv; |
9ad31989 | 357 | u32 val = 10000; |
ba56f625 | 358 | |
ddc922ff | 359 | out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
ba56f625 WD |
360 | |
361 | /* 1st reset MAL channel */ | |
362 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab | 363 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
d1c3b275 | 364 | mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); |
d6c61aab | 365 | #else |
d1c3b275 | 366 | mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 367 | #endif |
d1c3b275 | 368 | mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); |
ba56f625 WD |
369 | |
370 | /* wait for reset */ | |
d1c3b275 | 371 | while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 | 372 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
9ad31989 SR |
373 | val--; |
374 | if (val == 0) | |
ba56f625 | 375 | break; |
ba56f625 WD |
376 | } |
377 | ||
6c5879f3 | 378 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 379 | emac_loopback_enable(hw_p); |
6c5879f3 | 380 | |
8ac41e3e | 381 | /* EMAC RESET */ |
ddc922ff | 382 | out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); |
ba56f625 | 383 | |
6c5879f3 | 384 | /* remove clocks for EMAC internal loopback */ |
8ac41e3e | 385 | emac_loopback_disable(hw_p); |
6c5879f3 | 386 | |
a93316c5 | 387 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 388 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 389 | #endif |
c157d8e2 | 390 | |
4c9e8557 SR |
391 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
392 | /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ | |
9ad31989 SR |
393 | mfsdr(SDR0_ETH_CFG, val); |
394 | val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
395 | mtsdr(SDR0_ETH_CFG, val); | |
4c9e8557 SR |
396 | #endif |
397 | ||
ba56f625 WD |
398 | return; |
399 | } | |
400 | ||
846b0dd2 | 401 | #if defined (CONFIG_440GX) |
d6c61aab | 402 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
403 | { |
404 | unsigned long pfc1; | |
405 | unsigned long zmiifer; | |
406 | unsigned long rmiifer; | |
407 | ||
d1c3b275 | 408 | mfsdr(SDR0_PFC1, pfc1); |
855a496f WD |
409 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); |
410 | ||
411 | zmiifer = 0; | |
412 | rmiifer = 0; | |
413 | ||
414 | switch (pfc1) { | |
415 | case 1: | |
416 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
417 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
418 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
419 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
420 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
421 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
422 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
423 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
424 | break; | |
425 | case 2: | |
f6e495f5 SR |
426 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); |
427 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
428 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
429 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
855a496f WD |
430 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
431 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
432 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
433 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
434 | break; | |
435 | case 3: | |
436 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
437 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
438 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
439 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
440 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
441 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
442 | break; | |
443 | case 4: | |
444 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
445 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
446 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
447 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
448 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
449 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
450 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
451 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
452 | break; | |
453 | case 5: | |
454 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
455 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
456 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
457 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
458 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
459 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
460 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
461 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
462 | break; | |
463 | case 6: | |
464 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
465 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
466 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
467 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
468 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
469 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
470 | break; |
471 | case 0: | |
472 | default: | |
473 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
474 | rmiifer = 0x0; | |
475 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
476 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
477 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
478 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
479 | break; | |
480 | } | |
481 | ||
482 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
483 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
484 | ||
ddc922ff | 485 | out_be32((void *)ZMII0_FER, zmiifer); |
ff768cb1 | 486 | out_be32((void *)RGMII_FER, rmiifer); |
855a496f WD |
487 | |
488 | return ((int)pfc1); | |
855a496f | 489 | } |
6c5879f3 | 490 | #endif /* CONFIG_440_GX */ |
855a496f | 491 | |
887e2ec9 SR |
492 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
493 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
494 | { | |
495 | unsigned long zmiifer=0x0; | |
37ed6cdd | 496 | unsigned long pfc1; |
887e2ec9 | 497 | |
d1c3b275 | 498 | mfsdr(SDR0_PFC1, pfc1); |
37ed6cdd MF |
499 | pfc1 &= SDR0_PFC1_SELECT_MASK; |
500 | ||
2f15278c | 501 | switch (pfc1) { |
37ed6cdd | 502 | case SDR0_PFC1_SELECT_CONFIG_2: |
887e2ec9 | 503 | /* 1 x GMII port */ |
ddc922ff | 504 | out_be32((void *)ZMII0_FER, 0x00); |
2d83476a | 505 | out_be32((void *)RGMII_FER, 0x00000037); |
887e2ec9 SR |
506 | bis->bi_phymode[0] = BI_PHYMODE_GMII; |
507 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
508 | break; | |
37ed6cdd | 509 | case SDR0_PFC1_SELECT_CONFIG_4: |
887e2ec9 | 510 | /* 2 x RGMII ports */ |
ddc922ff | 511 | out_be32((void *)ZMII0_FER, 0x00); |
2d83476a | 512 | out_be32((void *)RGMII_FER, 0x00000055); |
887e2ec9 SR |
513 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
514 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
515 | break; | |
37ed6cdd | 516 | case SDR0_PFC1_SELECT_CONFIG_6: |
887e2ec9 | 517 | /* 2 x SMII ports */ |
ddc922ff | 518 | out_be32((void *)ZMII0_FER, |
2d83476a SR |
519 | ((ZMII_FER_SMII) << ZMII_FER_V(0)) | |
520 | ((ZMII_FER_SMII) << ZMII_FER_V(1))); | |
521 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
522 | bis->bi_phymode[0] = BI_PHYMODE_SMII; |
523 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
524 | break; | |
525 | case SDR0_PFC1_SELECT_CONFIG_1_2: | |
526 | /* only 1 x MII supported */ | |
ddc922ff | 527 | out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
2d83476a | 528 | out_be32((void *)RGMII_FER, 0x00000000); |
37ed6cdd MF |
529 | bis->bi_phymode[0] = BI_PHYMODE_MII; |
530 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
887e2ec9 SR |
531 | break; |
532 | default: | |
533 | break; | |
534 | } | |
535 | ||
536 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
ddc922ff | 537 | zmiifer = in_be32((void *)ZMII0_FER); |
887e2ec9 | 538 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
ddc922ff | 539 | out_be32((void *)ZMII0_FER, zmiifer); |
887e2ec9 SR |
540 | |
541 | return ((int)0x0); | |
542 | } | |
543 | #endif /* CONFIG_440EPX */ | |
544 | ||
dbbd1257 SR |
545 | #if defined(CONFIG_405EX) |
546 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
547 | { | |
1740c1bf | 548 | u32 rgmiifer = 0; |
dbbd1257 SR |
549 | |
550 | /* | |
1740c1bf GE |
551 | * The 405EX(r)'s RGMII bridge can operate in one of several |
552 | * modes, only one of which (2 x RGMII) allows the | |
553 | * simultaneous use of both EMACs on the 405EX. | |
dbbd1257 | 554 | */ |
1740c1bf GE |
555 | |
556 | switch (CONFIG_EMAC_PHY_MODE) { | |
557 | ||
558 | case EMAC_PHY_MODE_NONE: | |
559 | /* No ports */ | |
560 | rgmiifer |= RGMII_FER_DIS << 0; | |
561 | rgmiifer |= RGMII_FER_DIS << 4; | |
562 | out_be32((void *)RGMII_FER, rgmiifer); | |
563 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
564 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
565 | break; | |
566 | case EMAC_PHY_MODE_NONE_RGMII: | |
567 | /* 1 x RGMII port on channel 0 */ | |
568 | rgmiifer |= RGMII_FER_RGMII << 0; | |
569 | rgmiifer |= RGMII_FER_DIS << 4; | |
570 | out_be32((void *)RGMII_FER, rgmiifer); | |
571 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
572 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
573 | break; | |
574 | case EMAC_PHY_MODE_RGMII_NONE: | |
575 | /* 1 x RGMII port on channel 1 */ | |
576 | rgmiifer |= RGMII_FER_DIS << 0; | |
577 | rgmiifer |= RGMII_FER_RGMII << 4; | |
578 | out_be32((void *)RGMII_FER, rgmiifer); | |
579 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
580 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
581 | break; | |
582 | case EMAC_PHY_MODE_RGMII_RGMII: | |
dbbd1257 | 583 | /* 2 x RGMII ports */ |
1740c1bf GE |
584 | rgmiifer |= RGMII_FER_RGMII << 0; |
585 | rgmiifer |= RGMII_FER_RGMII << 4; | |
586 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
587 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
588 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
589 | break; | |
1740c1bf GE |
590 | case EMAC_PHY_MODE_NONE_GMII: |
591 | /* 1 x GMII port on channel 0 */ | |
592 | rgmiifer |= RGMII_FER_GMII << 0; | |
593 | rgmiifer |= RGMII_FER_DIS << 4; | |
594 | out_be32((void *)RGMII_FER, rgmiifer); | |
595 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
596 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
597 | break; | |
598 | case EMAC_PHY_MODE_NONE_MII: | |
599 | /* 1 x MII port on channel 0 */ | |
600 | rgmiifer |= RGMII_FER_MII << 0; | |
601 | rgmiifer |= RGMII_FER_DIS << 4; | |
602 | out_be32((void *)RGMII_FER, rgmiifer); | |
603 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
604 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
605 | break; | |
606 | case EMAC_PHY_MODE_GMII_NONE: | |
607 | /* 1 x GMII port on channel 1 */ | |
608 | rgmiifer |= RGMII_FER_DIS << 0; | |
609 | rgmiifer |= RGMII_FER_GMII << 4; | |
610 | out_be32((void *)RGMII_FER, rgmiifer); | |
611 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
612 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
613 | break; | |
614 | case EMAC_PHY_MODE_MII_NONE: | |
615 | /* 1 x MII port on channel 1 */ | |
616 | rgmiifer |= RGMII_FER_DIS << 0; | |
617 | rgmiifer |= RGMII_FER_MII << 4; | |
618 | out_be32((void *)RGMII_FER, rgmiifer); | |
619 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
620 | bis->bi_phymode[1] = BI_PHYMODE_MII; | |
dbbd1257 SR |
621 | break; |
622 | default: | |
623 | break; | |
624 | } | |
625 | ||
626 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
1740c1bf GE |
627 | rgmiifer = in_be32((void *)RGMII_FER); |
628 | rgmiifer |= (1 << (19-devnum)); | |
629 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
630 | |
631 | return ((int)0x0); | |
632 | } | |
633 | #endif /* CONFIG_405EX */ | |
634 | ||
8ac41e3e SR |
635 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
636 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
637 | { | |
638 | u32 eth_cfg; | |
639 | u32 zmiifer; /* ZMII0_FER reg. */ | |
640 | u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ | |
641 | u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ | |
4c9e8557 | 642 | int mode; |
8ac41e3e SR |
643 | |
644 | zmiifer = 0; | |
645 | rmiifer = 0; | |
646 | rmiifer1 = 0; | |
647 | ||
4c9e8557 SR |
648 | #if defined(CONFIG_460EX) |
649 | mode = 9; | |
78d78236 VG |
650 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
651 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
652 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) | |
653 | mode = 11; /* config SGMII */ | |
4c9e8557 SR |
654 | #else |
655 | mode = 10; | |
78d78236 VG |
656 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
657 | if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && | |
658 | ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && | |
659 | ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) | |
660 | mode = 12; /* config SGMII */ | |
4c9e8557 SR |
661 | #endif |
662 | ||
8ac41e3e SR |
663 | /* TODO: |
664 | * NOTE: 460GT has 2 RGMII bridge cores: | |
665 | * emac0 ------ RGMII0_BASE | |
666 | * | | |
667 | * emac1 -----+ | |
668 | * | |
669 | * emac2 ------ RGMII1_BASE | |
670 | * | | |
671 | * emac3 -----+ | |
672 | * | |
673 | * 460EX has 1 RGMII bridge core: | |
674 | * and RGMII1_BASE is disabled | |
675 | * emac0 ------ RGMII0_BASE | |
676 | * | | |
677 | * emac1 -----+ | |
678 | */ | |
679 | ||
680 | /* | |
681 | * Right now only 2*RGMII is supported. Please extend when needed. | |
682 | * sr - 2008-02-19 | |
78d78236 VG |
683 | * Add SGMII support. |
684 | * vg - 2008-07-28 | |
8ac41e3e | 685 | */ |
4c9e8557 | 686 | switch (mode) { |
8ac41e3e SR |
687 | case 1: |
688 | /* 1 MII - 460EX */ | |
689 | /* GMC0 EMAC4_0, ZMII Bridge */ | |
690 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
691 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
692 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
693 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
694 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
695 | break; | |
696 | case 2: | |
697 | /* 2 MII - 460GT */ | |
698 | /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ | |
699 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
700 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); | |
701 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
702 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
703 | bis->bi_phymode[2] = BI_PHYMODE_MII; | |
704 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
705 | break; | |
706 | case 3: | |
707 | /* 2 RMII - 460EX */ | |
708 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
709 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
710 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
711 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
712 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
713 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
714 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
715 | break; | |
716 | case 4: | |
717 | /* 4 RMII - 460GT */ | |
718 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ | |
719 | /* ZMII Bridge */ | |
720 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
721 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
722 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
723 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
724 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
725 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
726 | bis->bi_phymode[2] = BI_PHYMODE_RMII; | |
727 | bis->bi_phymode[3] = BI_PHYMODE_RMII; | |
728 | break; | |
729 | case 5: | |
730 | /* 2 SMII - 460EX */ | |
731 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
732 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
733 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
734 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
735 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
736 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
737 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
738 | break; | |
739 | case 6: | |
740 | /* 4 SMII - 460GT */ | |
741 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ | |
742 | /* ZMII Bridge */ | |
743 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
744 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
745 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
746 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
747 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
748 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
749 | bis->bi_phymode[2] = BI_PHYMODE_SMII; | |
750 | bis->bi_phymode[3] = BI_PHYMODE_SMII; | |
751 | break; | |
752 | case 7: | |
753 | /* This is the default mode that we want for board bringup - Maple */ | |
754 | /* 1 GMII - 460EX */ | |
755 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
756 | rmiifer |= RGMII_FER_MDIO(0); | |
757 | ||
758 | if (devnum == 0) { | |
759 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
760 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
761 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
762 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
763 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
764 | } else { | |
765 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ | |
766 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
767 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
768 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
769 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
770 | } | |
771 | break; | |
772 | case 8: | |
773 | /* 2 GMII - 460GT */ | |
774 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
775 | /* GMC1 EMAC4_2, RGMII Bridge 1 */ | |
776 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
777 | rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ | |
778 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
779 | rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ | |
780 | ||
781 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
782 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
783 | bis->bi_phymode[2] = BI_PHYMODE_GMII; | |
784 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
785 | break; | |
786 | case 9: | |
787 | /* 2 RGMII - 460EX */ | |
788 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
789 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
790 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
791 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
792 | ||
793 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
794 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
795 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
796 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
797 | break; | |
798 | case 10: | |
799 | /* 4 RGMII - 460GT */ | |
800 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
801 | /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ | |
802 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
803 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
804 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
805 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
806 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
807 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
808 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
809 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
810 | break; | |
78d78236 VG |
811 | case 11: |
812 | /* 2 SGMII - 460EX */ | |
813 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
814 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
815 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
816 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
817 | break; | |
818 | case 12: | |
819 | /* 3 SGMII - 460GT */ | |
820 | bis->bi_phymode[0] = BI_PHYMODE_SGMII; | |
821 | bis->bi_phymode[1] = BI_PHYMODE_SGMII; | |
822 | bis->bi_phymode[2] = BI_PHYMODE_SGMII; | |
823 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
824 | break; | |
8ac41e3e SR |
825 | default: |
826 | break; | |
827 | } | |
828 | ||
829 | /* Set EMAC for MDIO */ | |
830 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
831 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; | |
832 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
833 | ||
834 | out_be32((void *)RGMII_FER, rmiifer); | |
835 | #if defined(CONFIG_460GT) | |
836 | out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); | |
837 | #endif | |
838 | ||
839 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ | |
840 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
841 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
842 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | #endif /* CONFIG_460EX || CONFIG_460GT */ | |
847 | ||
ff768cb1 SR |
848 | static inline void *malloc_aligned(u32 size, u32 align) |
849 | { | |
850 | return (void *)(((u32)malloc(size + align) + align - 1) & | |
851 | ~(align - 1)); | |
852 | } | |
853 | ||
d6c61aab | 854 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 855 | { |
ff768cb1 | 856 | int i; |
d6c61aab | 857 | unsigned long reg = 0; |
ba56f625 WD |
858 | unsigned long msr; |
859 | unsigned long speed; | |
860 | unsigned long duplex; | |
861 | unsigned long failsafe; | |
862 | unsigned mode_reg; | |
863 | unsigned short devnum; | |
864 | unsigned short reg_short; | |
887e2ec9 SR |
865 | #if defined(CONFIG_440GX) || \ |
866 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 867 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 868 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 869 | defined(CONFIG_405EX) |
0c24dec5 | 870 | u32 opbfreq; |
d6c61aab | 871 | sys_info_t sysinfo; |
0544c636 | 872 | #if defined(CONFIG_440GX) || \ |
dbbd1257 | 873 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 874 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 875 | defined(CONFIG_405EX) |
f0813ab1 | 876 | __maybe_unused int ethgroup = -1; |
6e7fb6ea | 877 | #endif |
6c5879f3 | 878 | #endif |
ff768cb1 SR |
879 | u32 bd_cached; |
880 | u32 bd_uncached = 0; | |
4fae35a5 AG |
881 | #ifdef CONFIG_4xx_DCACHE |
882 | static u32 last_used_ea = 0; | |
883 | #endif | |
e54ec0f0 SR |
884 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
885 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ | |
886 | defined(CONFIG_405EX) | |
887 | int rgmii_channel; | |
888 | #endif | |
6c5879f3 | 889 | |
d6c61aab | 890 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
891 | |
892 | /* before doing anything, figure out if we have a MAC address */ | |
893 | /* if not, bail */ | |
4f92ac36 SR |
894 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
895 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 896 | return -1; |
4f92ac36 | 897 | } |
ba56f625 | 898 | |
887e2ec9 SR |
899 | #if defined(CONFIG_440GX) || \ |
900 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 901 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 902 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 903 | defined(CONFIG_405EX) |
ba56f625 WD |
904 | /* Need to get the OPB frequency so we can access the PHY */ |
905 | get_sys_info (&sysinfo); | |
d6c61aab | 906 | #endif |
ba56f625 | 907 | |
ba56f625 WD |
908 | msr = mfmsr (); |
909 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
910 | ||
911 | devnum = hw_p->devnum; | |
912 | ||
d6c61aab | 913 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
914 | /* AS.HARNOIS |
915 | * We should have : | |
265817c7 | 916 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
917 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
918 | * is possible that new packets (without relationship with | |
919 | * current transfer) have got the time to arrived before | |
920 | * netloop calls eth_halt | |
921 | */ | |
922 | printf ("About preceeding transfer (eth%d):\n" | |
923 | "- Sent packet number %d\n" | |
924 | "- Received packet number %d\n" | |
925 | "- Handled packet number %d\n", | |
926 | hw_p->devnum, | |
927 | hw_p->stats.pkts_tx, | |
928 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
929 | ||
930 | hw_p->stats.pkts_tx = 0; | |
931 | hw_p->stats.pkts_rx = 0; | |
932 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 933 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
934 | #endif |
935 | ||
265817c7 WD |
936 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
937 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
938 | |
939 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
940 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
941 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
942 | ||
943 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
944 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
945 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
946 | ||
6c5879f3 | 947 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
948 | /* set RMII mode */ |
949 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
950 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
951 | /* NOTE: only one emac at a time */ | |
952 | reg = 0; | |
ddc922ff | 953 | out_be32((void *)ZMII0_FER, 0); |
ba56f625 | 954 | udelay (100); |
ba56f625 | 955 | |
8ac41e3e | 956 | #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
ddc922ff | 957 | out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
8ac41e3e SR |
958 | #elif defined(CONFIG_440GX) || \ |
959 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
960 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d6c61aab | 961 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
0e6d798c | 962 | #endif |
c57c7980 | 963 | |
ddc922ff | 964 | out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); |
6e7fb6ea | 965 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
dbbd1257 SR |
966 | #if defined(CONFIG_405EX) |
967 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); | |
968 | #endif | |
d6c61aab | 969 | |
8ac41e3e | 970 | sync(); |
0e6d798c | 971 | |
6c5879f3 | 972 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 973 | emac_loopback_enable(hw_p); |
0e6d798c | 974 | |
8ac41e3e | 975 | /* EMAC RESET */ |
ddc922ff | 976 | out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); |
ba56f625 | 977 | |
8ac41e3e SR |
978 | /* remove clocks for EMAC internal loopback */ |
979 | emac_loopback_disable(hw_p); | |
980 | ||
ba56f625 | 981 | failsafe = 1000; |
ddc922ff | 982 | while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { |
ba56f625 WD |
983 | udelay (1000); |
984 | failsafe--; | |
985 | } | |
887e2ec9 SR |
986 | if (failsafe <= 0) |
987 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 988 | |
887e2ec9 SR |
989 | #if defined(CONFIG_440GX) || \ |
990 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 991 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 992 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 993 | defined(CONFIG_405EX) |
ba56f625 WD |
994 | /* Whack the M1 register */ |
995 | mode_reg = 0x0; | |
996 | mode_reg &= ~0x00000038; | |
0c24dec5 FR |
997 | opbfreq = sysinfo.freqOPB / 1000000; |
998 | if (opbfreq <= 50); | |
999 | else if (opbfreq <= 66) | |
ddc922ff | 1000 | mode_reg |= EMAC_MR1_OBCI_66; |
0c24dec5 | 1001 | else if (opbfreq <= 83) |
ddc922ff | 1002 | mode_reg |= EMAC_MR1_OBCI_83; |
0c24dec5 | 1003 | else if (opbfreq <= 100) |
ddc922ff | 1004 | mode_reg |= EMAC_MR1_OBCI_100; |
ba56f625 | 1005 | else |
ddc922ff | 1006 | mode_reg |= EMAC_MR1_OBCI_GT100; |
ba56f625 | 1007 | |
ddc922ff | 1008 | out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); |
6e7fb6ea | 1009 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 | 1010 | |
78d78236 VG |
1011 | #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ |
1012 | defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) | |
1013 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1014 | /* | |
1015 | * In SGMII mode, GPCS access is needed for | |
1016 | * communication with the internal SGMII SerDes. | |
1017 | */ | |
1018 | switch (devnum) { | |
1019 | #if defined(CONFIG_GPCS_PHY_ADDR) | |
1020 | case 0: | |
1021 | reg = CONFIG_GPCS_PHY_ADDR; | |
1022 | break; | |
1023 | #endif | |
1024 | #if defined(CONFIG_GPCS_PHY1_ADDR) | |
1025 | case 1: | |
1026 | reg = CONFIG_GPCS_PHY1_ADDR; | |
1027 | break; | |
1028 | #endif | |
1029 | #if defined(CONFIG_GPCS_PHY2_ADDR) | |
1030 | case 2: | |
1031 | reg = CONFIG_GPCS_PHY2_ADDR; | |
1032 | break; | |
1033 | #endif | |
1034 | #if defined(CONFIG_GPCS_PHY3_ADDR) | |
1035 | case 3: | |
1036 | reg = CONFIG_GPCS_PHY3_ADDR; | |
1037 | break; | |
1038 | #endif | |
1039 | } | |
1040 | ||
ddc922ff NG |
1041 | mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); |
1042 | mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); | |
1043 | out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); | |
78d78236 VG |
1044 | |
1045 | /* Configure GPCS interface to recommended setting for SGMII */ | |
1046 | miiphy_reset(dev->name, reg); | |
1047 | miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ | |
1048 | miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ | |
1049 | miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ | |
1050 | } | |
1051 | #endif /* defined(CONFIG_GPCS_PHY_ADDR) */ | |
1052 | ||
ba56f625 WD |
1053 | /* wait for PHY to complete auto negotiation */ |
1054 | reg_short = 0; | |
ba56f625 WD |
1055 | switch (devnum) { |
1056 | case 0: | |
1057 | reg = CONFIG_PHY_ADDR; | |
1058 | break; | |
d6c61aab | 1059 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
1060 | case 1: |
1061 | reg = CONFIG_PHY1_ADDR; | |
1062 | break; | |
d6c61aab | 1063 | #endif |
4c9e8557 | 1064 | #if defined (CONFIG_PHY2_ADDR) |
ba56f625 WD |
1065 | case 2: |
1066 | reg = CONFIG_PHY2_ADDR; | |
1067 | break; | |
4c9e8557 SR |
1068 | #endif |
1069 | #if defined (CONFIG_PHY3_ADDR) | |
ba56f625 WD |
1070 | case 3: |
1071 | reg = CONFIG_PHY3_ADDR; | |
1072 | break; | |
1073 | #endif | |
1074 | default: | |
1075 | reg = CONFIG_PHY_ADDR; | |
1076 | break; | |
1077 | } | |
1078 | ||
3c74e32a WD |
1079 | bis->bi_phynum[devnum] = reg; |
1080 | ||
78d78236 VG |
1081 | if (reg == CONFIG_FIXED_PHY) |
1082 | goto get_speed; | |
1083 | ||
d6c61aab | 1084 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
1085 | /* |
1086 | * Reset the phy, only if its the first time through | |
1087 | * otherwise, just check the speeds & feeds | |
1088 | */ | |
1089 | if (hw_p->first_init == 0) { | |
ec0c2ec7 | 1090 | #if defined(CONFIG_M88E1111_PHY) |
887e2ec9 SR |
1091 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); |
1092 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
1093 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
1094 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
ca08054e SR |
1095 | #if defined(CONFIG_M88E1111_DISABLE_FIBER) |
1096 | miiphy_read(dev->name, reg, 0x1b, ®_short); | |
1097 | reg_short |= 0x8000; | |
1098 | miiphy_write(dev->name, reg, 0x1b, reg_short); | |
1099 | #endif | |
887e2ec9 | 1100 | #endif |
78d78236 VG |
1101 | #if defined(CONFIG_M88E1112_PHY) |
1102 | if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { | |
1103 | /* | |
1104 | * Marvell 88E1112 PHY needs to have the SGMII MAC | |
1105 | * interace (page 2) properly configured to | |
1106 | * communicate with the 460EX/GT GPCS interface. | |
1107 | */ | |
1108 | ||
1109 | /* Set access to Page 2 */ | |
1110 | miiphy_write(dev->name, reg, 0x16, 0x0002); | |
1111 | ||
1112 | miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ | |
1113 | miiphy_read(dev->name, reg, 0x1a, ®_short); | |
1114 | reg_short |= 0x8000; /* bypass Auto-Negotiation */ | |
1115 | miiphy_write(dev->name, reg, 0x1a, reg_short); | |
1116 | miiphy_reset(dev->name, reg); /* reset MAC interface */ | |
1117 | ||
1118 | /* Reset access to Page 0 */ | |
1119 | miiphy_write(dev->name, reg, 0x16, 0x0000); | |
1120 | } | |
1121 | #endif /* defined(CONFIG_M88E1112_PHY) */ | |
63ff004c | 1122 | miiphy_reset (dev->name, reg); |
ba56f625 | 1123 | |
887e2ec9 SR |
1124 | #if defined(CONFIG_440GX) || \ |
1125 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
8ac41e3e | 1126 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1127 | defined(CONFIG_405EX) |
887e2ec9 | 1128 | |
0e6d798c | 1129 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 1130 | /* |
17f50f22 SR |
1131 | * Cicada 8201 PHY needs to have an extended register whacked |
1132 | * for RGMII mode. | |
fc1cfcdb | 1133 | */ |
887e2ec9 | 1134 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 1135 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 1136 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 1137 | #else |
63ff004c | 1138 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 1139 | #endif |
17f50f22 SR |
1140 | /* |
1141 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
1142 | * Interoperability problem with Intel 82547EI phys | |
1143 | * This work around (provided by Vitesse) changes | |
1144 | * the default timer convergence from 8ms to 12ms | |
1145 | */ | |
63ff004c MB |
1146 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
1147 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
1148 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
1149 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
1150 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
1151 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
1152 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
1153 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
1154 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
1155 | /* end Vitesse/Cicada errata */ |
1156 | } | |
6ca8646c | 1157 | #endif /* defined(CONFIG_CIS8201_PHY) */ |
5fb692ca SR |
1158 | |
1159 | #if defined(CONFIG_ET1011C_PHY) | |
1160 | /* | |
1161 | * Agere ET1011c PHY needs to have an extended register whacked | |
1162 | * for RGMII mode. | |
1163 | */ | |
1164 | if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { | |
1165 | miiphy_read (dev->name, reg, 0x16, ®_short); | |
1166 | reg_short &= ~(0x7); | |
1167 | reg_short |= 0x6; /* RGMII DLL Delay*/ | |
1168 | miiphy_write (dev->name, reg, 0x16, reg_short); | |
1169 | ||
1170 | miiphy_read (dev->name, reg, 0x17, ®_short); | |
1171 | reg_short &= ~(0x40); | |
1172 | miiphy_write (dev->name, reg, 0x17, reg_short); | |
1173 | ||
1174 | miiphy_write(dev->name, reg, 0x1c, 0x74f0); | |
1175 | } | |
6ca8646c | 1176 | #endif /* defined(CONFIG_ET1011C_PHY) */ |
5fb692ca | 1177 | |
6ca8646c | 1178 | #endif /* defined(CONFIG_440GX) ... */ |
a06752e3 | 1179 | /* Start/Restart autonegotiation */ |
63ff004c | 1180 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
1181 | udelay (1000); |
1182 | } | |
d6c61aab | 1183 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 1184 | |
8ef583a0 | 1185 | miiphy_read (dev->name, reg, MII_BMSR, ®_short); |
ba56f625 WD |
1186 | |
1187 | /* | |
0e6d798c | 1188 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 | 1189 | */ |
8ef583a0 MF |
1190 | if ((reg_short & BMSR_ANEGCAPABLE) |
1191 | && !(reg_short & BMSR_ANEGCOMPLETE)) { | |
ba56f625 WD |
1192 | puts ("Waiting for PHY auto negotiation to complete"); |
1193 | i = 0; | |
8ef583a0 | 1194 | while (!(reg_short & BMSR_ANEGCOMPLETE)) { |
ba56f625 WD |
1195 | /* |
1196 | * Timeout reached ? | |
1197 | */ | |
1198 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
1199 | puts (" TIMEOUT !\n"); | |
1200 | break; | |
1201 | } | |
1202 | ||
1203 | if ((i++ % 1000) == 0) { | |
1204 | putc ('.'); | |
1205 | } | |
1206 | udelay (1000); /* 1 ms */ | |
8ef583a0 | 1207 | miiphy_read (dev->name, reg, MII_BMSR, ®_short); |
ba56f625 WD |
1208 | } |
1209 | puts (" done\n"); | |
1210 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
1211 | } | |
d6c61aab | 1212 | |
78d78236 VG |
1213 | get_speed: |
1214 | if (reg == CONFIG_FIXED_PHY) { | |
1215 | for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { | |
1216 | if (devnum == fixed_phy_port[i].devnum) { | |
1217 | speed = fixed_phy_port[i].speed; | |
1218 | duplex = fixed_phy_port[i].duplex; | |
1219 | break; | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | if (i == ARRAY_SIZE(fixed_phy_port)) { | |
1224 | printf("ERROR: PHY (%s) not configured correctly!\n", | |
1225 | dev->name); | |
1226 | return -1; | |
1227 | } | |
1228 | } else { | |
1229 | speed = miiphy_speed(dev->name, reg); | |
1230 | duplex = miiphy_duplex(dev->name, reg); | |
1231 | } | |
ba56f625 WD |
1232 | |
1233 | if (hw_p->print_speed) { | |
1234 | hw_p->print_speed = 0; | |
5fb692ca SR |
1235 | printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", |
1236 | (int) speed, (duplex == HALF) ? "HALF" : "FULL", | |
1237 | hw_p->devnum); | |
ba56f625 WD |
1238 | } |
1239 | ||
8ac41e3e SR |
1240 | #if defined(CONFIG_440) && \ |
1241 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ | |
1242 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
1243 | !defined(CONFIG_460EX) && !defined(CONFIG_460GT) | |
846b0dd2 | 1244 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
d1c3b275 | 1245 | mfsdr(SDR0_MFR, reg); |
c157d8e2 SR |
1246 | if (speed == 100) { |
1247 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
1248 | } else { | |
1249 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
1250 | } | |
d1c3b275 | 1251 | mtsdr(SDR0_MFR, reg); |
c157d8e2 | 1252 | #endif |
c57c7980 | 1253 | |
ba56f625 | 1254 | /* Set ZMII/RGMII speed according to the phy link speed */ |
ddc922ff | 1255 | reg = in_be32((void *)ZMII0_SSR); |
855a496f | 1256 | if ( (speed == 100) || (speed == 1000) ) |
ddc922ff | 1257 | out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); |
ba56f625 | 1258 | else |
ddc922ff | 1259 | out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); |
ba56f625 WD |
1260 | |
1261 | if ((devnum == 2) || (devnum == 3)) { | |
1262 | if (speed == 1000) | |
1263 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
1264 | else if (speed == 100) | |
1265 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 1266 | else if (speed == 10) |
ba56f625 | 1267 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
1268 | else { |
1269 | printf("Error in RGMII Speed\n"); | |
1270 | return -1; | |
1271 | } | |
ff768cb1 | 1272 | out_be32((void *)RGMII_SSR, reg); |
ba56f625 | 1273 | } |
6e7fb6ea | 1274 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 1275 | |
dbbd1257 | 1276 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 1277 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1278 | defined(CONFIG_405EX) |
e54ec0f0 SR |
1279 | if (devnum >= 2) |
1280 | rgmii_channel = devnum - 2; | |
1281 | else | |
1282 | rgmii_channel = devnum; | |
1283 | ||
887e2ec9 | 1284 | if (speed == 1000) |
e54ec0f0 | 1285 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1286 | else if (speed == 100) |
e54ec0f0 | 1287 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1288 | else if (speed == 10) |
e54ec0f0 | 1289 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 SR |
1290 | else { |
1291 | printf("Error in RGMII Speed\n"); | |
1292 | return -1; | |
1293 | } | |
2d83476a | 1294 | out_be32((void *)RGMII_SSR, reg); |
8ac41e3e SR |
1295 | #if defined(CONFIG_460GT) |
1296 | if ((devnum == 2) || (devnum == 3)) | |
1297 | out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); | |
1298 | #endif | |
887e2ec9 SR |
1299 | #endif |
1300 | ||
ba56f625 | 1301 | /* set the Mal configuration reg */ |
887e2ec9 SR |
1302 | #if defined(CONFIG_440GX) || \ |
1303 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1304 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1305 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1306 | defined(CONFIG_405EX) |
d1c3b275 | 1307 | mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
17f50f22 SR |
1308 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); |
1309 | #else | |
d1c3b275 | 1310 | mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); |
ba56f625 | 1311 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 | 1312 | if (get_pvr() == PVR_440GP_RB) { |
d1c3b275 | 1313 | mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); |
17f50f22 SR |
1314 | } |
1315 | #endif | |
ba56f625 | 1316 | |
ba56f625 WD |
1317 | /* |
1318 | * Malloc MAL buffer desciptors, make sure they are | |
1319 | * aligned on cache line boundary size | |
1320 | * (401/403/IOP480 = 16, 405 = 32) | |
1321 | * and doesn't cross cache block boundaries. | |
1322 | */ | |
ff768cb1 SR |
1323 | if (hw_p->first_init == 0) { |
1324 | debug("*** Allocating descriptor memory ***\n"); | |
ba56f625 | 1325 | |
ff768cb1 SR |
1326 | bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); |
1327 | if (!bd_cached) { | |
b002144e | 1328 | printf("%s: Error allocating MAL descriptor buffers!\n", __func__); |
ff768cb1 SR |
1329 | return -1; |
1330 | } | |
b79316f2 | 1331 | |
ff768cb1 | 1332 | #ifdef CONFIG_4xx_DCACHE |
ba79fde5 | 1333 | flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); |
4fae35a5 | 1334 | if (!last_used_ea) |
6d0f6bcf JCPV |
1335 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1336 | bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; | |
5e3dca57 | 1337 | #else |
4fae35a5 | 1338 | bd_uncached = bis->bi_memsize; |
5e3dca57 | 1339 | #endif |
4fae35a5 AG |
1340 | else |
1341 | bd_uncached = last_used_ea + MAL_ALLOC_SIZE; | |
1342 | ||
1343 | last_used_ea = bd_uncached; | |
ff768cb1 SR |
1344 | program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, |
1345 | TLB_WORD2_I_ENABLE); | |
1346 | #else | |
1347 | bd_uncached = bd_cached; | |
1348 | #endif | |
1349 | hw_p->tx_phys = bd_cached; | |
1350 | hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; | |
1351 | hw_p->tx = (mal_desc_t *)(bd_uncached); | |
1352 | hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); | |
c97e74af | 1353 | debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx); |
ba56f625 WD |
1354 | } |
1355 | ||
1356 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
1357 | hw_p->tx[i].ctrl = 0; | |
1358 | hw_p->tx[i].data_len = 0; | |
ff768cb1 SR |
1359 | if (hw_p->first_init == 0) |
1360 | hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, | |
1361 | L1_CACHE_BYTES); | |
ba56f625 WD |
1362 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
1363 | if ((NUM_TX_BUFF - 1) == i) | |
1364 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
1365 | hw_p->tx_run[i] = -1; | |
c97e74af | 1366 | debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr); |
ba56f625 WD |
1367 | } |
1368 | ||
1369 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
1370 | hw_p->rx[i].ctrl = 0; | |
1371 | hw_p->rx[i].data_len = 0; | |
ff768cb1 | 1372 | hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; |
ba56f625 WD |
1373 | if ((NUM_RX_BUFF - 1) == i) |
1374 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
1375 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
1376 | hw_p->rx_ready[i] = -1; | |
c97e74af | 1377 | debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr); |
ba56f625 WD |
1378 | } |
1379 | ||
1380 | reg = 0x00000000; | |
1381 | ||
1382 | reg |= dev->enetaddr[0]; /* set high address */ | |
1383 | reg = reg << 8; | |
1384 | reg |= dev->enetaddr[1]; | |
1385 | ||
ddc922ff | 1386 | out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); |
ba56f625 WD |
1387 | |
1388 | reg = 0x00000000; | |
1389 | reg |= dev->enetaddr[2]; /* set low address */ | |
1390 | reg = reg << 8; | |
1391 | reg |= dev->enetaddr[3]; | |
1392 | reg = reg << 8; | |
1393 | reg |= dev->enetaddr[4]; | |
1394 | reg = reg << 8; | |
1395 | reg |= dev->enetaddr[5]; | |
1396 | ||
ddc922ff | 1397 | out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); |
ba56f625 WD |
1398 | |
1399 | switch (devnum) { | |
1400 | case 1: | |
1401 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1402 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
d1c3b275 | 1403 | mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); |
c157d8e2 | 1404 | #else |
d1c3b275 | 1405 | mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); |
c157d8e2 | 1406 | #endif |
d6c61aab | 1407 | #if defined(CONFIG_440) |
d1c3b275 SR |
1408 | mtdcr (MAL0_TXBADDR, 0x0); |
1409 | mtdcr (MAL0_RXBADDR, 0x0); | |
d6c61aab | 1410 | #endif |
8ac41e3e SR |
1411 | |
1412 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d1c3b275 | 1413 | mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); |
8ac41e3e | 1414 | /* set RX buffer size */ |
d1c3b275 | 1415 | mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); |
8ac41e3e | 1416 | #else |
d1c3b275 | 1417 | mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); |
ba56f625 | 1418 | /* set RX buffer size */ |
d1c3b275 | 1419 | mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); |
8ac41e3e | 1420 | #endif |
ba56f625 | 1421 | break; |
846b0dd2 | 1422 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1423 | case 2: |
1424 | /* setup MAL tx & rx channel pointers */ | |
d1c3b275 SR |
1425 | mtdcr (MAL0_TXBADDR, 0x0); |
1426 | mtdcr (MAL0_RXBADDR, 0x0); | |
1427 | mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); | |
1428 | mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); | |
ba56f625 | 1429 | /* set RX buffer size */ |
d1c3b275 | 1430 | mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); |
ba56f625 WD |
1431 | break; |
1432 | case 3: | |
1433 | /* setup MAL tx & rx channel pointers */ | |
d1c3b275 SR |
1434 | mtdcr (MAL0_TXBADDR, 0x0); |
1435 | mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); | |
1436 | mtdcr (MAL0_RXBADDR, 0x0); | |
1437 | mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); | |
ba56f625 | 1438 | /* set RX buffer size */ |
d1c3b275 | 1439 | mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); |
ba56f625 | 1440 | break; |
c57c7980 | 1441 | #endif /* CONFIG_440GX */ |
4c9e8557 SR |
1442 | #if defined (CONFIG_460GT) |
1443 | case 2: | |
1444 | /* setup MAL tx & rx channel pointers */ | |
d1c3b275 SR |
1445 | mtdcr (MAL0_TXBADDR, 0x0); |
1446 | mtdcr (MAL0_RXBADDR, 0x0); | |
1447 | mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); | |
1448 | mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); | |
4c9e8557 | 1449 | /* set RX buffer size */ |
d1c3b275 | 1450 | mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); |
4c9e8557 SR |
1451 | break; |
1452 | case 3: | |
1453 | /* setup MAL tx & rx channel pointers */ | |
d1c3b275 SR |
1454 | mtdcr (MAL0_TXBADDR, 0x0); |
1455 | mtdcr (MAL0_RXBADDR, 0x0); | |
1456 | mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); | |
1457 | mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); | |
4c9e8557 | 1458 | /* set RX buffer size */ |
d1c3b275 | 1459 | mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); |
4c9e8557 SR |
1460 | break; |
1461 | #endif /* CONFIG_460GT */ | |
ba56f625 WD |
1462 | case 0: |
1463 | default: | |
1464 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1465 | #if defined(CONFIG_440) |
d1c3b275 SR |
1466 | mtdcr (MAL0_TXBADDR, 0x0); |
1467 | mtdcr (MAL0_RXBADDR, 0x0); | |
d6c61aab | 1468 | #endif |
d1c3b275 SR |
1469 | mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); |
1470 | mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); | |
ba56f625 | 1471 | /* set RX buffer size */ |
d1c3b275 | 1472 | mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); |
ba56f625 WD |
1473 | break; |
1474 | } | |
1475 | ||
1476 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 1477 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
d1c3b275 | 1478 | mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
c157d8e2 | 1479 | #else |
d1c3b275 | 1480 | mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 1481 | #endif |
d1c3b275 | 1482 | mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); |
ba56f625 WD |
1483 | |
1484 | /* set transmit enable & receive enable */ | |
ddc922ff | 1485 | out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); |
ba56f625 | 1486 | |
ddc922ff | 1487 | mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); |
76957cb3 SR |
1488 | |
1489 | /* set rx-/tx-fifo size */ | |
1490 | mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; | |
ba56f625 WD |
1491 | |
1492 | /* set speed */ | |
6e7fb6ea | 1493 | if (speed == _1000BASET) { |
5e7abce9 | 1494 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
6e7fb6ea | 1495 | unsigned long pfc1; |
887e2ec9 | 1496 | |
d1c3b275 | 1497 | mfsdr (SDR0_PFC1, pfc1); |
6e7fb6ea | 1498 | pfc1 |= SDR0_PFC1_EM_1000; |
d1c3b275 | 1499 | mtsdr (SDR0_PFC1, pfc1); |
6e7fb6ea | 1500 | #endif |
ddc922ff | 1501 | mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; |
6e7fb6ea | 1502 | } else if (speed == _100BASET) |
ddc922ff | 1503 | mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; |
ba56f625 WD |
1504 | else |
1505 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
1506 | if (duplex == FULL) | |
ddc922ff | 1507 | mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; |
ba56f625 | 1508 | |
ddc922ff | 1509 | out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); |
ba56f625 WD |
1510 | |
1511 | /* Enable broadcast and indvidual address */ | |
1512 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
ddc922ff | 1513 | out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
ba56f625 WD |
1514 | |
1515 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
1516 | ||
1517 | /* set transmit request threshold register */ | |
ddc922ff | 1518 | out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
ba56f625 | 1519 | |
265817c7 | 1520 | /* set receive low/high water mark register */ |
d6c61aab | 1521 | #if defined(CONFIG_440) |
6c5879f3 | 1522 | /* 440s has a 64 byte burst length */ |
ddc922ff | 1523 | out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
1524 | #else |
1525 | /* 405s have a 16 byte burst length */ | |
ddc922ff | 1526 | out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
d6c61aab | 1527 | #endif /* defined(CONFIG_440) */ |
ddc922ff | 1528 | out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); |
ba56f625 WD |
1529 | |
1530 | /* Set fifo limit entry in tx mode 0 */ | |
ddc922ff | 1531 | out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); |
ba56f625 | 1532 | /* Frame gap set */ |
ddc922ff | 1533 | out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
ba56f625 WD |
1534 | |
1535 | /* Set EMAC IER */ | |
d6c61aab | 1536 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
1537 | if (speed == _100BASET) |
1538 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
1539 | ||
ddc922ff NG |
1540 | out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
1541 | out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); | |
ba56f625 WD |
1542 | |
1543 | if (hw_p->first_init == 0) { | |
1544 | /* | |
1545 | * Connect interrupt service routines | |
1546 | */ | |
dbbd1257 SR |
1547 | irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), |
1548 | (interrupt_handler_t *) enetInt, dev); | |
ba56f625 | 1549 | } |
ba56f625 WD |
1550 | |
1551 | mtmsr (msr); /* enable interrupts again */ | |
1552 | ||
1553 | hw_p->bis = bis; | |
1554 | hw_p->first_init = 1; | |
1555 | ||
802b769b | 1556 | return 0; |
ba56f625 WD |
1557 | } |
1558 | ||
1559 | ||
3f9eb617 | 1560 | static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len) |
ba56f625 WD |
1561 | { |
1562 | struct enet_frame *ef_ptr; | |
1563 | ulong time_start, time_now; | |
1564 | unsigned long temp_txm0; | |
d6c61aab | 1565 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1566 | |
1567 | ef_ptr = (struct enet_frame *) ptr; | |
1568 | ||
1569 | /*-----------------------------------------------------------------------+ | |
1570 | * Copy in our address into the frame. | |
1571 | *-----------------------------------------------------------------------*/ | |
1572 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
1573 | ||
1574 | /*-----------------------------------------------------------------------+ | |
1575 | * If frame is too long or too short, modify length. | |
1576 | *-----------------------------------------------------------------------*/ | |
1577 | /* TBS: where does the fragment go???? */ | |
1578 | if (len > ENET_MAX_MTU) | |
1579 | len = ENET_MAX_MTU; | |
1580 | ||
1581 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
1582 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
ba79fde5 | 1583 | flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); |
ba56f625 WD |
1584 | |
1585 | /*-----------------------------------------------------------------------+ | |
1586 | * set TX Buffer busy, and send it | |
1587 | *-----------------------------------------------------------------------*/ | |
1588 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
1589 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
1590 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
1591 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1592 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1593 | ||
1594 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1595 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1596 | ||
8ac41e3e | 1597 | sync(); |
ba56f625 | 1598 | |
ddc922ff NG |
1599 | out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, |
1600 | in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); | |
d6c61aab | 1601 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1602 | hw_p->stats.pkts_tx++; |
1603 | #endif | |
1604 | ||
1605 | /*-----------------------------------------------------------------------+ | |
1606 | * poll unitl the packet is sent and then make sure it is OK | |
1607 | *-----------------------------------------------------------------------*/ | |
1608 | time_start = get_timer (0); | |
1609 | while (1) { | |
ddc922ff | 1610 | temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); |
ba56f625 | 1611 | /* loop until either TINT turns on or 3 seconds elapse */ |
ddc922ff | 1612 | if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { |
ba56f625 WD |
1613 | /* transmit is done, so now check for errors |
1614 | * If there is an error, an interrupt should | |
1615 | * happen when we return | |
1616 | */ | |
1617 | time_now = get_timer (0); | |
1618 | if ((time_now - time_start) > 3000) { | |
1619 | return (-1); | |
1620 | } | |
1621 | } else { | |
1622 | return (len); | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | ||
ba56f625 WD |
1627 | int enetInt (struct eth_device *dev) |
1628 | { | |
1629 | int serviced; | |
1630 | int rc = -1; /* default to not us */ | |
d1631fe1 SR |
1631 | u32 mal_isr; |
1632 | u32 emac_isr = 0; | |
1633 | u32 mal_eob; | |
1634 | u32 uic_mal; | |
1635 | u32 uic_mal_err; | |
1636 | u32 uic_emac; | |
1637 | u32 uic_emac_b; | |
d6c61aab | 1638 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1639 | |
1640 | /* | |
1641 | * Because the mal is generic, we need to get the current | |
1642 | * eth device | |
1643 | */ | |
d6c61aab | 1644 | dev = eth_get_dev(); |
ba56f625 WD |
1645 | |
1646 | hw_p = dev->priv; | |
1647 | ||
ba56f625 WD |
1648 | /* enter loop that stays in interrupt code until nothing to service */ |
1649 | do { | |
1650 | serviced = 0; | |
1651 | ||
d1631fe1 SR |
1652 | uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); |
1653 | uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); | |
1654 | uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); | |
1655 | uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); | |
887e2ec9 | 1656 | |
d1631fe1 SR |
1657 | if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) |
1658 | && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) | |
1659 | && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { | |
ba56f625 WD |
1660 | /* not for us */ |
1661 | return (rc); | |
1662 | } | |
d1631fe1 | 1663 | |
ba56f625 | 1664 | /* get and clear controller status interrupts */ |
d1631fe1 SR |
1665 | /* look at MAL and EMAC error interrupts */ |
1666 | if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { | |
1667 | /* we have a MAL error interrupt */ | |
d1c3b275 | 1668 | mal_isr = mfdcr(MAL0_ESR); |
d1631fe1 SR |
1669 | mal_err(dev, mal_isr, uic_mal_err, |
1670 | MAL_UIC_DEF, MAL_UIC_ERR); | |
ba56f625 | 1671 | |
d1631fe1 SR |
1672 | /* clear MAL error interrupt status bits */ |
1673 | mtdcr(UIC_BASE_MAL_ERR + UIC_SR, | |
1674 | UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); | |
ba56f625 | 1675 | |
d1631fe1 | 1676 | return -1; |
ba56f625 WD |
1677 | } |
1678 | ||
d1631fe1 SR |
1679 | /* look for EMAC errors */ |
1680 | if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { | |
ddc922ff | 1681 | emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); |
d1631fe1 | 1682 | emac_err(dev, emac_isr); |
6e7fb6ea | 1683 | |
d1631fe1 SR |
1684 | /* clear EMAC error interrupt status bits */ |
1685 | mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); | |
1686 | mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); | |
6e7fb6ea | 1687 | |
d1631fe1 | 1688 | return -1; |
ba56f625 | 1689 | } |
d6c61aab | 1690 | |
d1631fe1 SR |
1691 | /* handle MAX TX EOB interrupt from a tx */ |
1692 | if (uic_mal & UIC_MAL_TXEOB) { | |
1693 | /* clear MAL interrupt status bits */ | |
d1c3b275 SR |
1694 | mal_eob = mfdcr(MAL0_TXEOBISR); |
1695 | mtdcr(MAL0_TXEOBISR, mal_eob); | |
d1631fe1 SR |
1696 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); |
1697 | ||
1698 | /* indicate that we serviced an interrupt */ | |
1699 | serviced = 1; | |
1700 | rc = 0; | |
d6c61aab SR |
1701 | } |
1702 | ||
16263087 | 1703 | /* handle MAL RX EOB interrupt from a receive */ |
d1631fe1 SR |
1704 | /* check for EOB on valid channels */ |
1705 | if (uic_mal & UIC_MAL_RXEOB) { | |
d1c3b275 | 1706 | mal_eob = mfdcr(MAL0_RXEOBISR); |
d1631fe1 SR |
1707 | if (mal_eob & |
1708 | (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { | |
1709 | /* push packet to upper layer */ | |
1710 | enet_rcv(dev, emac_isr); | |
d6c61aab | 1711 | |
d1631fe1 SR |
1712 | /* clear MAL interrupt status bits */ |
1713 | mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); | |
d6c61aab | 1714 | |
d6c61aab SR |
1715 | /* indicate that we serviced an interrupt */ |
1716 | serviced = 1; | |
1717 | rc = 0; | |
1718 | } | |
1719 | } | |
c0b46d8e JC |
1720 | #if defined(CONFIG_405EZ) |
1721 | /* | |
1722 | * On 405EZ the RX-/TX-interrupts are coalesced into | |
1723 | * one IRQ bit in the UIC. We need to acknowledge the | |
1724 | * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. | |
1725 | */ | |
1726 | mtsdr(SDR0_ICINTSTAT, | |
1727 | SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); | |
1728 | #endif /* defined(CONFIG_405EZ) */ | |
d1631fe1 | 1729 | } while (serviced); |
d6c61aab SR |
1730 | |
1731 | return (rc); | |
1732 | } | |
1733 | ||
ba56f625 WD |
1734 | /*-----------------------------------------------------------------------------+ |
1735 | * MAL Error Routine | |
1736 | *-----------------------------------------------------------------------------*/ | |
1737 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1738 | unsigned long uic, unsigned long maldef, | |
1739 | unsigned long mal_errr) | |
1740 | { | |
d6c61aab | 1741 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1742 | |
d1c3b275 | 1743 | mtdcr (MAL0_ESR, isr); /* clear interrupt */ |
ba56f625 WD |
1744 | |
1745 | /* clear DE interrupt */ | |
d1c3b275 SR |
1746 | mtdcr (MAL0_TXDEIR, 0xC0000000); |
1747 | mtdcr (MAL0_RXDEIR, 0x80000000); | |
ba56f625 | 1748 | |
d6c61aab | 1749 | #ifdef INFO_4XX_ENET |
265817c7 | 1750 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1751 | #endif |
1752 | ||
1753 | eth_init (hw_p->bis); /* start again... */ | |
1754 | } | |
1755 | ||
1756 | /*-----------------------------------------------------------------------------+ | |
1757 | * EMAC Error Routine | |
1758 | *-----------------------------------------------------------------------------*/ | |
1759 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1760 | { | |
d6c61aab | 1761 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1762 | |
1763 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
ddc922ff | 1764 | out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); |
ba56f625 WD |
1765 | } |
1766 | ||
1767 | /*-----------------------------------------------------------------------------+ | |
1768 | * enet_rcv() handles the ethernet receive data | |
1769 | *-----------------------------------------------------------------------------*/ | |
1770 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1771 | { | |
ba56f625 WD |
1772 | unsigned long data_len; |
1773 | unsigned long rx_eob_isr; | |
d6c61aab | 1774 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1775 | |
1776 | int handled = 0; | |
1777 | int i; | |
1778 | int loop_count = 0; | |
1779 | ||
d1c3b275 | 1780 | rx_eob_isr = mfdcr (MAL0_RXEOBISR); |
8ac41e3e | 1781 | if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { |
ba56f625 | 1782 | /* clear EOB */ |
d1c3b275 | 1783 | mtdcr (MAL0_RXEOBISR, rx_eob_isr); |
ba56f625 WD |
1784 | |
1785 | /* EMAC RX done */ | |
1786 | while (1) { /* do all */ | |
1787 | i = hw_p->rx_slot; | |
1788 | ||
1789 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1790 | || (loop_count >= NUM_RX_BUFF)) | |
1791 | break; | |
a2e1c709 | 1792 | |
ba56f625 | 1793 | loop_count++; |
ba56f625 | 1794 | handled++; |
8ac41e3e | 1795 | data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ |
ba56f625 WD |
1796 | if (data_len) { |
1797 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1798 | data_len = 0; | |
1799 | else { | |
1800 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1801 | data_len = 0; | |
1802 | hw_p->stats.rx_err_log[hw_p-> | |
1803 | rx_err_index] | |
1804 | = hw_p->rx[i].ctrl; | |
1805 | hw_p->rx_err_index++; | |
1806 | if (hw_p->rx_err_index == | |
1807 | MAX_ERR_LOG) | |
1808 | hw_p->rx_err_index = | |
1809 | 0; | |
fc1cfcdb | 1810 | } /* emac_erros */ |
ba56f625 | 1811 | } /* data_len < max mtu */ |
fc1cfcdb | 1812 | } /* if data_len */ |
ba56f625 WD |
1813 | if (!data_len) { /* no data */ |
1814 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1815 | ||
1816 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1817 | } | |
1818 | ||
1819 | /* !data_len */ | |
1820 | /* AS.HARNOIS */ | |
1821 | /* Check if user has already eaten buffer */ | |
1822 | /* if not => ERROR */ | |
1823 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1824 | if (hw_p->is_receiving) | |
1825 | printf ("ERROR : Receive buffers are full!\n"); | |
1826 | break; | |
1827 | } else { | |
1828 | hw_p->stats.rx_frames++; | |
1829 | hw_p->stats.rx += data_len; | |
d6c61aab | 1830 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1831 | hw_p->stats.pkts_rx++; |
1832 | #endif | |
1833 | /* AS.HARNOIS | |
1834 | * use ring buffer | |
1835 | */ | |
1836 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1837 | hw_p->rx_i_index++; | |
1838 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1839 | hw_p->rx_i_index = 0; | |
1840 | ||
a2e1c709 SR |
1841 | hw_p->rx_slot++; |
1842 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1843 | hw_p->rx_slot = 0; | |
1844 | ||
ba56f625 WD |
1845 | /* AS.HARNOIS |
1846 | * free receive buffer only when | |
1847 | * buffer has been handled (eth_rx) | |
1848 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1849 | */ | |
1850 | } /* if data_len */ | |
1851 | } /* while */ | |
1852 | } /* if EMACK_RXCHL */ | |
1853 | } | |
1854 | ||
1855 | ||
d6c61aab | 1856 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1857 | { |
1858 | int length; | |
1859 | int user_index; | |
1860 | unsigned long msr; | |
d6c61aab | 1861 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1862 | |
265817c7 | 1863 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1864 | |
1865 | for (;;) { | |
1866 | /* AS.HARNOIS | |
1867 | * use ring buffer and | |
1868 | * get index from rx buffer desciptor queue | |
1869 | */ | |
1870 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1871 | if (user_index == -1) { | |
1872 | length = -1; | |
1873 | break; /* nothing received - leave for() loop */ | |
1874 | } | |
1875 | ||
1876 | msr = mfmsr (); | |
1877 | mtmsr (msr & ~(MSR_EE)); | |
1878 | ||
8ac41e3e | 1879 | length = hw_p->rx[user_index].data_len & 0x0fff; |
ba56f625 WD |
1880 | |
1881 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1882 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1883 | /* NetReceive(NetRxPackets[i], length); */ | |
ff768cb1 SR |
1884 | invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, |
1885 | (u32)hw_p->rx[user_index].data_ptr + | |
ba79fde5 | 1886 | length - 4); |
ba56f625 WD |
1887 | NetReceive (NetRxPackets[user_index], length - 4); |
1888 | /* Free Recv Buffer */ | |
1889 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1890 | /* Free rx buffer descriptor queue */ | |
1891 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1892 | hw_p->rx_u_index++; | |
1893 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1894 | hw_p->rx_u_index = 0; | |
1895 | ||
d6c61aab | 1896 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1897 | hw_p->stats.pkts_handled++; |
1898 | #endif | |
1899 | ||
1900 | mtmsr (msr); /* Enable IRQ's */ | |
1901 | } | |
1902 | ||
265817c7 | 1903 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1904 | |
1905 | return length; | |
1906 | } | |
1907 | ||
d6c61aab | 1908 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1909 | { |
1910 | static int virgin = 0; | |
ba56f625 WD |
1911 | struct eth_device *dev; |
1912 | int eth_num = 0; | |
d6c61aab | 1913 | EMAC_4XX_HW_PST hw = NULL; |
5fb692ca SR |
1914 | u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; |
1915 | u32 hw_addr[4]; | |
d1631fe1 | 1916 | u32 mal_ier; |
ba56f625 | 1917 | |
846b0dd2 | 1918 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1919 | unsigned long pfc1; |
1920 | ||
d1c3b275 | 1921 | mfsdr (SDR0_PFC1, pfc1); |
ba56f625 WD |
1922 | pfc1 &= ~(0x01e00000); |
1923 | pfc1 |= 0x01200000; | |
d1c3b275 | 1924 | mtsdr (SDR0_PFC1, pfc1); |
c157d8e2 | 1925 | #endif |
6c5879f3 | 1926 | |
5fb692ca SR |
1927 | /* first clear all mac-addresses */ |
1928 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) | |
1929 | memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); | |
a06752e3 | 1930 | |
1e25f957 | 1931 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
d3f87148 | 1932 | int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START; |
ba56f625 | 1933 | switch (eth_num) { |
e2ffd59b | 1934 | default: /* fall through */ |
ba56f625 | 1935 | case 0: |
d3f87148 | 1936 | eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]); |
5fb692ca | 1937 | hw_addr[eth_num] = 0x0; |
ba56f625 | 1938 | break; |
e2ffd59b | 1939 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1940 | case 1: |
d3f87148 | 1941 | eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]); |
5fb692ca | 1942 | hw_addr[eth_num] = 0x100; |
ba56f625 | 1943 | break; |
e2ffd59b WD |
1944 | #endif |
1945 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1946 | case 2: |
d3f87148 | 1947 | eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]); |
4c9e8557 SR |
1948 | #if defined(CONFIG_460GT) |
1949 | hw_addr[eth_num] = 0x300; | |
1950 | #else | |
5fb692ca | 1951 | hw_addr[eth_num] = 0x400; |
4c9e8557 | 1952 | #endif |
ba56f625 | 1953 | break; |
e2ffd59b WD |
1954 | #endif |
1955 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1956 | case 3: |
d3f87148 | 1957 | eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]); |
4c9e8557 SR |
1958 | #if defined(CONFIG_460GT) |
1959 | hw_addr[eth_num] = 0x400; | |
1960 | #else | |
5fb692ca | 1961 | hw_addr[eth_num] = 0x600; |
4c9e8557 | 1962 | #endif |
ba56f625 | 1963 | break; |
e2ffd59b | 1964 | #endif |
ba56f625 | 1965 | } |
5fb692ca SR |
1966 | } |
1967 | ||
1968 | /* set phy num and mode */ | |
1969 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
1970 | bis->bi_phymode[0] = 0; | |
1971 | ||
1972 | #if defined(CONFIG_PHY1_ADDR) | |
1973 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; | |
1974 | bis->bi_phymode[1] = 0; | |
1975 | #endif | |
1976 | #if defined(CONFIG_440GX) | |
1977 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; | |
1978 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
1979 | bis->bi_phymode[2] = 2; | |
1980 | bis->bi_phymode[3] = 2; | |
dbbd1257 | 1981 | #endif |
5fb692ca | 1982 | |
dbbd1257 SR |
1983 | #if defined(CONFIG_440GX) || \ |
1984 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
1985 | defined(CONFIG_405EX) | |
5fb692ca SR |
1986 | ppc_4xx_eth_setup_bridge(0, bis); |
1987 | #endif | |
1988 | ||
1989 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { | |
1990 | /* | |
1991 | * See if we can actually bring up the interface, | |
1992 | * otherwise, skip it | |
1993 | */ | |
1994 | if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { | |
1995 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
1996 | continue; | |
1997 | } | |
ba56f625 WD |
1998 | |
1999 | /* Allocate device structure */ | |
2000 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
2001 | if (dev == NULL) { | |
d6c61aab | 2002 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2003 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
2004 | return (-1); |
2005 | } | |
b2532eff | 2006 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
2007 | |
2008 | /* Allocate our private use data */ | |
d6c61aab | 2009 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 2010 | if (hw == NULL) { |
d6c61aab | 2011 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2012 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
2013 | eth_num); |
2014 | free (dev); | |
2015 | return (-1); | |
2016 | } | |
b2532eff | 2017 | memset(hw, 0, sizeof(*hw)); |
ba56f625 | 2018 | |
5fb692ca SR |
2019 | hw->hw_addr = hw_addr[eth_num]; |
2020 | memcpy (dev->enetaddr, ethaddr[eth_num], 6); | |
ba56f625 | 2021 | hw->devnum = eth_num; |
c157d8e2 | 2022 | hw->print_speed = 1; |
ba56f625 | 2023 | |
5fb692ca | 2024 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); |
ba56f625 | 2025 | dev->priv = (void *) hw; |
d6c61aab SR |
2026 | dev->init = ppc_4xx_eth_init; |
2027 | dev->halt = ppc_4xx_eth_halt; | |
2028 | dev->send = ppc_4xx_eth_send; | |
2029 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 | 2030 | |
3ce04d9b SR |
2031 | eth_register(dev); |
2032 | ||
2033 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) | |
2034 | miiphy_register(dev->name, | |
2035 | emac4xx_miiphy_read, emac4xx_miiphy_write); | |
2036 | #endif | |
2037 | ||
ba56f625 WD |
2038 | if (0 == virgin) { |
2039 | /* set the MAL IER ??? names may change with new spec ??? */ | |
dbbd1257 SR |
2040 | #if defined(CONFIG_440SPE) || \ |
2041 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
8ac41e3e | 2042 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 2043 | defined(CONFIG_405EX) |
6c5879f3 MB |
2044 | mal_ier = |
2045 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
2046 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
2047 | #else | |
ba56f625 WD |
2048 | mal_ier = |
2049 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
2050 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 2051 | #endif |
d1c3b275 SR |
2052 | mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ |
2053 | mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ | |
2054 | mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ | |
2055 | mtdcr (MAL0_IER, mal_ier); | |
ba56f625 WD |
2056 | |
2057 | /* install MAL interrupt handler */ | |
d1631fe1 | 2058 | irq_install_handler (VECNUM_MAL_SERR, |
ba56f625 WD |
2059 | (interrupt_handler_t *) enetInt, |
2060 | dev); | |
d1631fe1 | 2061 | irq_install_handler (VECNUM_MAL_TXEOB, |
ba56f625 WD |
2062 | (interrupt_handler_t *) enetInt, |
2063 | dev); | |
d1631fe1 | 2064 | irq_install_handler (VECNUM_MAL_RXEOB, |
ba56f625 WD |
2065 | (interrupt_handler_t *) enetInt, |
2066 | dev); | |
d1631fe1 | 2067 | irq_install_handler (VECNUM_MAL_TXDE, |
ba56f625 WD |
2068 | (interrupt_handler_t *) enetInt, |
2069 | dev); | |
d1631fe1 | 2070 | irq_install_handler (VECNUM_MAL_RXDE, |
ba56f625 WD |
2071 | (interrupt_handler_t *) enetInt, |
2072 | dev); | |
2073 | virgin = 1; | |
2074 | } | |
ba56f625 | 2075 | } /* end for each supported device */ |
802b769b SR |
2076 | |
2077 | return 0; | |
ba56f625 | 2078 | } |