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d0722149 DE |
1 | /* GNU/Linux/x86-64 specific low level interface, for the remote server |
2 | for GDB. | |
61baf725 | 3 | Copyright (C) 2002-2017 Free Software Foundation, Inc. |
d0722149 DE |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
d41f6d8e | 20 | #include "server.h" |
d0722149 | 21 | #include <signal.h> |
6a271cae | 22 | #include <limits.h> |
f4647387 | 23 | #include <inttypes.h> |
d0722149 DE |
24 | #include "linux-low.h" |
25 | #include "i387-fp.h" | |
df7e5265 GB |
26 | #include "x86-low.h" |
27 | #include "x86-xstate.h" | |
5826e159 | 28 | #include "nat/gdb_ptrace.h" |
d0722149 | 29 | |
93813b37 WT |
30 | #ifdef __x86_64__ |
31 | #include "nat/amd64-linux-siginfo.h" | |
32 | #endif | |
33 | ||
d0722149 | 34 | #include "gdb_proc_service.h" |
b5737fa9 PA |
35 | /* Don't include elf/common.h if linux/elf.h got included by |
36 | gdb_proc_service.h. */ | |
37 | #ifndef ELFMAG0 | |
38 | #include "elf/common.h" | |
39 | #endif | |
40 | ||
58b4daa5 | 41 | #include "agent.h" |
3aee8918 | 42 | #include "tdesc.h" |
c144c7a0 | 43 | #include "tracepoint.h" |
f699aaba | 44 | #include "ax.h" |
7b669087 | 45 | #include "nat/linux-nat.h" |
4b134ca1 | 46 | #include "nat/x86-linux.h" |
8e5d4070 | 47 | #include "nat/x86-linux-dregs.h" |
ae91f625 | 48 | #include "linux-x86-tdesc.h" |
a196ebeb | 49 | |
3aee8918 PA |
50 | #ifdef __x86_64__ |
51 | static struct target_desc *tdesc_amd64_linux_no_xml; | |
52 | #endif | |
53 | static struct target_desc *tdesc_i386_linux_no_xml; | |
54 | ||
1570b33e | 55 | |
fa593d66 | 56 | static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 }; |
405f8e94 | 57 | static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 }; |
fa593d66 | 58 | |
1570b33e L |
59 | /* Backward compatibility for gdb without XML support. */ |
60 | ||
61 | static const char *xmltarget_i386_linux_no_xml = "@<target>\ | |
62 | <architecture>i386</architecture>\ | |
63 | <osabi>GNU/Linux</osabi>\ | |
64 | </target>"; | |
f6d1620c L |
65 | |
66 | #ifdef __x86_64__ | |
1570b33e L |
67 | static const char *xmltarget_amd64_linux_no_xml = "@<target>\ |
68 | <architecture>i386:x86-64</architecture>\ | |
69 | <osabi>GNU/Linux</osabi>\ | |
70 | </target>"; | |
f6d1620c | 71 | #endif |
d0722149 DE |
72 | |
73 | #include <sys/reg.h> | |
74 | #include <sys/procfs.h> | |
5826e159 | 75 | #include "nat/gdb_ptrace.h" |
1570b33e L |
76 | #include <sys/uio.h> |
77 | ||
d0722149 DE |
78 | #ifndef PTRACE_GET_THREAD_AREA |
79 | #define PTRACE_GET_THREAD_AREA 25 | |
80 | #endif | |
81 | ||
82 | /* This definition comes from prctl.h, but some kernels may not have it. */ | |
83 | #ifndef PTRACE_ARCH_PRCTL | |
84 | #define PTRACE_ARCH_PRCTL 30 | |
85 | #endif | |
86 | ||
87 | /* The following definitions come from prctl.h, but may be absent | |
88 | for certain configurations. */ | |
89 | #ifndef ARCH_GET_FS | |
90 | #define ARCH_SET_GS 0x1001 | |
91 | #define ARCH_SET_FS 0x1002 | |
92 | #define ARCH_GET_FS 0x1003 | |
93 | #define ARCH_GET_GS 0x1004 | |
94 | #endif | |
95 | ||
aa5ca48f DE |
96 | /* Per-process arch-specific data we want to keep. */ |
97 | ||
98 | struct arch_process_info | |
99 | { | |
df7e5265 | 100 | struct x86_debug_reg_state debug_reg_state; |
aa5ca48f DE |
101 | }; |
102 | ||
d0722149 DE |
103 | #ifdef __x86_64__ |
104 | ||
105 | /* Mapping between the general-purpose registers in `struct user' | |
106 | format and GDB's register array layout. | |
107 | Note that the transfer layout uses 64-bit regs. */ | |
108 | static /*const*/ int i386_regmap[] = | |
109 | { | |
110 | RAX * 8, RCX * 8, RDX * 8, RBX * 8, | |
111 | RSP * 8, RBP * 8, RSI * 8, RDI * 8, | |
112 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, | |
113 | DS * 8, ES * 8, FS * 8, GS * 8 | |
114 | }; | |
115 | ||
116 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) | |
117 | ||
118 | /* So code below doesn't have to care, i386 or amd64. */ | |
119 | #define ORIG_EAX ORIG_RAX | |
bc9540e8 | 120 | #define REGSIZE 8 |
d0722149 DE |
121 | |
122 | static const int x86_64_regmap[] = | |
123 | { | |
124 | RAX * 8, RBX * 8, RCX * 8, RDX * 8, | |
125 | RSI * 8, RDI * 8, RBP * 8, RSP * 8, | |
126 | R8 * 8, R9 * 8, R10 * 8, R11 * 8, | |
127 | R12 * 8, R13 * 8, R14 * 8, R15 * 8, | |
128 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, | |
129 | DS * 8, ES * 8, FS * 8, GS * 8, | |
130 | -1, -1, -1, -1, -1, -1, -1, -1, | |
131 | -1, -1, -1, -1, -1, -1, -1, -1, | |
132 | -1, -1, -1, -1, -1, -1, -1, -1, | |
a196ebeb WT |
133 | -1, |
134 | -1, -1, -1, -1, -1, -1, -1, -1, | |
135 | ORIG_RAX * 8, | |
2735833d WT |
136 | #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
137 | 21 * 8, 22 * 8, | |
138 | #else | |
139 | -1, -1, | |
140 | #endif | |
a196ebeb | 141 | -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ |
01f9f808 MS |
142 | -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ |
143 | -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */ | |
144 | -1, -1, -1, -1, -1, -1, -1, -1, | |
145 | -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */ | |
146 | -1, -1, -1, -1, -1, -1, -1, -1, | |
147 | -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ | |
148 | -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */ | |
149 | -1, -1, -1, -1, -1, -1, -1, -1, | |
150 | -1, -1, -1, -1, -1, -1, -1, -1, | |
51547df6 MS |
151 | -1, -1, -1, -1, -1, -1, -1, -1, |
152 | -1 /* pkru */ | |
d0722149 DE |
153 | }; |
154 | ||
155 | #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0])) | |
9e0aa64f | 156 | #define X86_64_USER_REGS (GS + 1) |
d0722149 DE |
157 | |
158 | #else /* ! __x86_64__ */ | |
159 | ||
160 | /* Mapping between the general-purpose registers in `struct user' | |
161 | format and GDB's register array layout. */ | |
162 | static /*const*/ int i386_regmap[] = | |
163 | { | |
164 | EAX * 4, ECX * 4, EDX * 4, EBX * 4, | |
165 | UESP * 4, EBP * 4, ESI * 4, EDI * 4, | |
166 | EIP * 4, EFL * 4, CS * 4, SS * 4, | |
167 | DS * 4, ES * 4, FS * 4, GS * 4 | |
168 | }; | |
169 | ||
170 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) | |
171 | ||
bc9540e8 PA |
172 | #define REGSIZE 4 |
173 | ||
d0722149 | 174 | #endif |
3aee8918 PA |
175 | |
176 | #ifdef __x86_64__ | |
177 | ||
178 | /* Returns true if the current inferior belongs to a x86-64 process, | |
179 | per the tdesc. */ | |
180 | ||
181 | static int | |
182 | is_64bit_tdesc (void) | |
183 | { | |
0bfdf32f | 184 | struct regcache *regcache = get_thread_regcache (current_thread, 0); |
3aee8918 PA |
185 | |
186 | return register_size (regcache->tdesc, 0) == 8; | |
187 | } | |
188 | ||
189 | #endif | |
190 | ||
d0722149 DE |
191 | \f |
192 | /* Called by libthread_db. */ | |
193 | ||
194 | ps_err_e | |
754653a7 | 195 | ps_get_thread_area (struct ps_prochandle *ph, |
d0722149 DE |
196 | lwpid_t lwpid, int idx, void **base) |
197 | { | |
198 | #ifdef __x86_64__ | |
3aee8918 | 199 | int use_64bit = is_64bit_tdesc (); |
d0722149 DE |
200 | |
201 | if (use_64bit) | |
202 | { | |
203 | switch (idx) | |
204 | { | |
205 | case FS: | |
206 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0) | |
207 | return PS_OK; | |
208 | break; | |
209 | case GS: | |
210 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0) | |
211 | return PS_OK; | |
212 | break; | |
213 | default: | |
214 | return PS_BADADDR; | |
215 | } | |
216 | return PS_ERR; | |
217 | } | |
218 | #endif | |
219 | ||
220 | { | |
221 | unsigned int desc[4]; | |
222 | ||
223 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, | |
224 | (void *) (intptr_t) idx, (unsigned long) &desc) < 0) | |
225 | return PS_ERR; | |
226 | ||
d1ec4ce7 DE |
227 | /* Ensure we properly extend the value to 64-bits for x86_64. */ |
228 | *base = (void *) (uintptr_t) desc[1]; | |
d0722149 DE |
229 | return PS_OK; |
230 | } | |
231 | } | |
fa593d66 PA |
232 | |
233 | /* Get the thread area address. This is used to recognize which | |
234 | thread is which when tracing with the in-process agent library. We | |
235 | don't read anything from the address, and treat it as opaque; it's | |
236 | the address itself that we assume is unique per-thread. */ | |
237 | ||
238 | static int | |
239 | x86_get_thread_area (int lwpid, CORE_ADDR *addr) | |
240 | { | |
241 | #ifdef __x86_64__ | |
3aee8918 | 242 | int use_64bit = is_64bit_tdesc (); |
fa593d66 PA |
243 | |
244 | if (use_64bit) | |
245 | { | |
246 | void *base; | |
247 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) | |
248 | { | |
249 | *addr = (CORE_ADDR) (uintptr_t) base; | |
250 | return 0; | |
251 | } | |
252 | ||
253 | return -1; | |
254 | } | |
255 | #endif | |
256 | ||
257 | { | |
258 | struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid)); | |
d86d4aaf DE |
259 | struct thread_info *thr = get_lwp_thread (lwp); |
260 | struct regcache *regcache = get_thread_regcache (thr, 1); | |
fa593d66 PA |
261 | unsigned int desc[4]; |
262 | ULONGEST gs = 0; | |
263 | const int reg_thread_area = 3; /* bits to scale down register value. */ | |
264 | int idx; | |
265 | ||
266 | collect_register_by_name (regcache, "gs", &gs); | |
267 | ||
268 | idx = gs >> reg_thread_area; | |
269 | ||
270 | if (ptrace (PTRACE_GET_THREAD_AREA, | |
d86d4aaf | 271 | lwpid_of (thr), |
493e2a69 | 272 | (void *) (long) idx, (unsigned long) &desc) < 0) |
fa593d66 PA |
273 | return -1; |
274 | ||
275 | *addr = desc[1]; | |
276 | return 0; | |
277 | } | |
278 | } | |
279 | ||
280 | ||
d0722149 DE |
281 | \f |
282 | static int | |
3aee8918 | 283 | x86_cannot_store_register (int regno) |
d0722149 | 284 | { |
3aee8918 PA |
285 | #ifdef __x86_64__ |
286 | if (is_64bit_tdesc ()) | |
287 | return 0; | |
288 | #endif | |
289 | ||
d0722149 DE |
290 | return regno >= I386_NUM_REGS; |
291 | } | |
292 | ||
293 | static int | |
3aee8918 | 294 | x86_cannot_fetch_register (int regno) |
d0722149 | 295 | { |
3aee8918 PA |
296 | #ifdef __x86_64__ |
297 | if (is_64bit_tdesc ()) | |
298 | return 0; | |
299 | #endif | |
300 | ||
d0722149 DE |
301 | return regno >= I386_NUM_REGS; |
302 | } | |
303 | ||
304 | static void | |
442ea881 | 305 | x86_fill_gregset (struct regcache *regcache, void *buf) |
d0722149 DE |
306 | { |
307 | int i; | |
308 | ||
309 | #ifdef __x86_64__ | |
3aee8918 | 310 | if (register_size (regcache->tdesc, 0) == 8) |
d0722149 DE |
311 | { |
312 | for (i = 0; i < X86_64_NUM_REGS; i++) | |
313 | if (x86_64_regmap[i] != -1) | |
442ea881 | 314 | collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
2735833d WT |
315 | |
316 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE | |
317 | { | |
318 | unsigned long base; | |
319 | int lwpid = lwpid_of (current_thread); | |
320 | ||
321 | collect_register_by_name (regcache, "fs_base", &base); | |
322 | ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_SET_FS); | |
323 | ||
324 | collect_register_by_name (regcache, "gs_base", &base); | |
325 | ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_SET_GS); | |
326 | } | |
327 | #endif | |
328 | ||
d0722149 DE |
329 | return; |
330 | } | |
9e0aa64f JK |
331 | |
332 | /* 32-bit inferior registers need to be zero-extended. | |
333 | Callers would read uninitialized memory otherwise. */ | |
334 | memset (buf, 0x00, X86_64_USER_REGS * 8); | |
d0722149 DE |
335 | #endif |
336 | ||
337 | for (i = 0; i < I386_NUM_REGS; i++) | |
442ea881 | 338 | collect_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
d0722149 | 339 | |
442ea881 | 340 | collect_register_by_name (regcache, "orig_eax", |
bc9540e8 | 341 | ((char *) buf) + ORIG_EAX * REGSIZE); |
d0722149 DE |
342 | } |
343 | ||
344 | static void | |
442ea881 | 345 | x86_store_gregset (struct regcache *regcache, const void *buf) |
d0722149 DE |
346 | { |
347 | int i; | |
348 | ||
349 | #ifdef __x86_64__ | |
3aee8918 | 350 | if (register_size (regcache->tdesc, 0) == 8) |
d0722149 DE |
351 | { |
352 | for (i = 0; i < X86_64_NUM_REGS; i++) | |
353 | if (x86_64_regmap[i] != -1) | |
442ea881 | 354 | supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
2735833d WT |
355 | |
356 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE | |
357 | { | |
358 | unsigned long base; | |
359 | int lwpid = lwpid_of (current_thread); | |
360 | ||
361 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) | |
362 | supply_register_by_name (regcache, "fs_base", &base); | |
363 | ||
364 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_GS) == 0) | |
365 | supply_register_by_name (regcache, "gs_base", &base); | |
366 | } | |
367 | #endif | |
d0722149 DE |
368 | return; |
369 | } | |
370 | #endif | |
371 | ||
372 | for (i = 0; i < I386_NUM_REGS; i++) | |
442ea881 | 373 | supply_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
d0722149 | 374 | |
442ea881 | 375 | supply_register_by_name (regcache, "orig_eax", |
bc9540e8 | 376 | ((char *) buf) + ORIG_EAX * REGSIZE); |
d0722149 DE |
377 | } |
378 | ||
379 | static void | |
442ea881 | 380 | x86_fill_fpregset (struct regcache *regcache, void *buf) |
d0722149 DE |
381 | { |
382 | #ifdef __x86_64__ | |
442ea881 | 383 | i387_cache_to_fxsave (regcache, buf); |
d0722149 | 384 | #else |
442ea881 | 385 | i387_cache_to_fsave (regcache, buf); |
d0722149 DE |
386 | #endif |
387 | } | |
388 | ||
389 | static void | |
442ea881 | 390 | x86_store_fpregset (struct regcache *regcache, const void *buf) |
d0722149 DE |
391 | { |
392 | #ifdef __x86_64__ | |
442ea881 | 393 | i387_fxsave_to_cache (regcache, buf); |
d0722149 | 394 | #else |
442ea881 | 395 | i387_fsave_to_cache (regcache, buf); |
d0722149 DE |
396 | #endif |
397 | } | |
398 | ||
399 | #ifndef __x86_64__ | |
400 | ||
401 | static void | |
442ea881 | 402 | x86_fill_fpxregset (struct regcache *regcache, void *buf) |
d0722149 | 403 | { |
442ea881 | 404 | i387_cache_to_fxsave (regcache, buf); |
d0722149 DE |
405 | } |
406 | ||
407 | static void | |
442ea881 | 408 | x86_store_fpxregset (struct regcache *regcache, const void *buf) |
d0722149 | 409 | { |
442ea881 | 410 | i387_fxsave_to_cache (regcache, buf); |
d0722149 DE |
411 | } |
412 | ||
413 | #endif | |
414 | ||
1570b33e L |
415 | static void |
416 | x86_fill_xstateregset (struct regcache *regcache, void *buf) | |
417 | { | |
418 | i387_cache_to_xsave (regcache, buf); | |
419 | } | |
420 | ||
421 | static void | |
422 | x86_store_xstateregset (struct regcache *regcache, const void *buf) | |
423 | { | |
424 | i387_xsave_to_cache (regcache, buf); | |
425 | } | |
426 | ||
d0722149 DE |
427 | /* ??? The non-biarch i386 case stores all the i387 regs twice. |
428 | Once in i387_.*fsave.* and once in i387_.*fxsave.*. | |
429 | This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS | |
430 | doesn't work. IWBN to avoid the duplication in the case where it | |
431 | does work. Maybe the arch_setup routine could check whether it works | |
3aee8918 | 432 | and update the supported regsets accordingly. */ |
d0722149 | 433 | |
3aee8918 | 434 | static struct regset_info x86_regsets[] = |
d0722149 DE |
435 | { |
436 | #ifdef HAVE_PTRACE_GETREGS | |
1570b33e | 437 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), |
d0722149 DE |
438 | GENERAL_REGS, |
439 | x86_fill_gregset, x86_store_gregset }, | |
1570b33e L |
440 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0, |
441 | EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset }, | |
d0722149 DE |
442 | # ifndef __x86_64__ |
443 | # ifdef HAVE_PTRACE_GETFPXREGS | |
1570b33e | 444 | { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t), |
d0722149 DE |
445 | EXTENDED_REGS, |
446 | x86_fill_fpxregset, x86_store_fpxregset }, | |
447 | # endif | |
448 | # endif | |
1570b33e | 449 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t), |
d0722149 DE |
450 | FP_REGS, |
451 | x86_fill_fpregset, x86_store_fpregset }, | |
452 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 453 | NULL_REGSET |
d0722149 DE |
454 | }; |
455 | ||
456 | static CORE_ADDR | |
442ea881 | 457 | x86_get_pc (struct regcache *regcache) |
d0722149 | 458 | { |
3aee8918 | 459 | int use_64bit = register_size (regcache->tdesc, 0) == 8; |
d0722149 DE |
460 | |
461 | if (use_64bit) | |
462 | { | |
6598661d PA |
463 | uint64_t pc; |
464 | ||
442ea881 | 465 | collect_register_by_name (regcache, "rip", &pc); |
d0722149 DE |
466 | return (CORE_ADDR) pc; |
467 | } | |
468 | else | |
469 | { | |
6598661d PA |
470 | uint32_t pc; |
471 | ||
442ea881 | 472 | collect_register_by_name (regcache, "eip", &pc); |
d0722149 DE |
473 | return (CORE_ADDR) pc; |
474 | } | |
475 | } | |
476 | ||
477 | static void | |
442ea881 | 478 | x86_set_pc (struct regcache *regcache, CORE_ADDR pc) |
d0722149 | 479 | { |
3aee8918 | 480 | int use_64bit = register_size (regcache->tdesc, 0) == 8; |
d0722149 DE |
481 | |
482 | if (use_64bit) | |
483 | { | |
6598661d PA |
484 | uint64_t newpc = pc; |
485 | ||
442ea881 | 486 | supply_register_by_name (regcache, "rip", &newpc); |
d0722149 DE |
487 | } |
488 | else | |
489 | { | |
6598661d PA |
490 | uint32_t newpc = pc; |
491 | ||
442ea881 | 492 | supply_register_by_name (regcache, "eip", &newpc); |
d0722149 DE |
493 | } |
494 | } | |
495 | \f | |
dd373349 | 496 | static const gdb_byte x86_breakpoint[] = { 0xCC }; |
d0722149 DE |
497 | #define x86_breakpoint_len 1 |
498 | ||
499 | static int | |
500 | x86_breakpoint_at (CORE_ADDR pc) | |
501 | { | |
502 | unsigned char c; | |
503 | ||
fc7238bb | 504 | (*the_target->read_memory) (pc, &c, 1); |
d0722149 DE |
505 | if (c == 0xCC) |
506 | return 1; | |
507 | ||
508 | return 0; | |
509 | } | |
510 | \f | |
42995dbd | 511 | /* Low-level function vector. */ |
df7e5265 | 512 | struct x86_dr_low_type x86_dr_low = |
42995dbd | 513 | { |
d33472ad GB |
514 | x86_linux_dr_set_control, |
515 | x86_linux_dr_set_addr, | |
516 | x86_linux_dr_get_addr, | |
517 | x86_linux_dr_get_status, | |
518 | x86_linux_dr_get_control, | |
42995dbd GB |
519 | sizeof (void *), |
520 | }; | |
aa5ca48f | 521 | \f |
90d74c30 | 522 | /* Breakpoint/Watchpoint support. */ |
aa5ca48f DE |
523 | |
524 | static int | |
802e8e6d PA |
525 | x86_supports_z_point_type (char z_type) |
526 | { | |
527 | switch (z_type) | |
528 | { | |
529 | case Z_PACKET_SW_BP: | |
530 | case Z_PACKET_HW_BP: | |
531 | case Z_PACKET_WRITE_WP: | |
532 | case Z_PACKET_ACCESS_WP: | |
533 | return 1; | |
534 | default: | |
535 | return 0; | |
536 | } | |
537 | } | |
538 | ||
539 | static int | |
540 | x86_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
541 | int size, struct raw_breakpoint *bp) | |
aa5ca48f DE |
542 | { |
543 | struct process_info *proc = current_process (); | |
802e8e6d | 544 | |
aa5ca48f DE |
545 | switch (type) |
546 | { | |
802e8e6d PA |
547 | case raw_bkpt_type_hw: |
548 | case raw_bkpt_type_write_wp: | |
549 | case raw_bkpt_type_access_wp: | |
a4165e94 | 550 | { |
802e8e6d PA |
551 | enum target_hw_bp_type hw_type |
552 | = raw_bkpt_type_to_target_hw_bp_type (type); | |
df7e5265 | 553 | struct x86_debug_reg_state *state |
fe978cb0 | 554 | = &proc->priv->arch_private->debug_reg_state; |
a4165e94 | 555 | |
df7e5265 | 556 | return x86_dr_insert_watchpoint (state, hw_type, addr, size); |
a4165e94 | 557 | } |
961bd387 | 558 | |
aa5ca48f DE |
559 | default: |
560 | /* Unsupported. */ | |
561 | return 1; | |
562 | } | |
563 | } | |
564 | ||
565 | static int | |
802e8e6d PA |
566 | x86_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
567 | int size, struct raw_breakpoint *bp) | |
aa5ca48f DE |
568 | { |
569 | struct process_info *proc = current_process (); | |
802e8e6d | 570 | |
aa5ca48f DE |
571 | switch (type) |
572 | { | |
802e8e6d PA |
573 | case raw_bkpt_type_hw: |
574 | case raw_bkpt_type_write_wp: | |
575 | case raw_bkpt_type_access_wp: | |
a4165e94 | 576 | { |
802e8e6d PA |
577 | enum target_hw_bp_type hw_type |
578 | = raw_bkpt_type_to_target_hw_bp_type (type); | |
df7e5265 | 579 | struct x86_debug_reg_state *state |
fe978cb0 | 580 | = &proc->priv->arch_private->debug_reg_state; |
a4165e94 | 581 | |
df7e5265 | 582 | return x86_dr_remove_watchpoint (state, hw_type, addr, size); |
a4165e94 | 583 | } |
aa5ca48f DE |
584 | default: |
585 | /* Unsupported. */ | |
586 | return 1; | |
587 | } | |
588 | } | |
589 | ||
590 | static int | |
591 | x86_stopped_by_watchpoint (void) | |
592 | { | |
593 | struct process_info *proc = current_process (); | |
fe978cb0 | 594 | return x86_dr_stopped_by_watchpoint (&proc->priv->arch_private->debug_reg_state); |
aa5ca48f DE |
595 | } |
596 | ||
597 | static CORE_ADDR | |
598 | x86_stopped_data_address (void) | |
599 | { | |
600 | struct process_info *proc = current_process (); | |
601 | CORE_ADDR addr; | |
fe978cb0 | 602 | if (x86_dr_stopped_data_address (&proc->priv->arch_private->debug_reg_state, |
df7e5265 | 603 | &addr)) |
aa5ca48f DE |
604 | return addr; |
605 | return 0; | |
606 | } | |
607 | \f | |
608 | /* Called when a new process is created. */ | |
609 | ||
610 | static struct arch_process_info * | |
611 | x86_linux_new_process (void) | |
612 | { | |
ed859da7 | 613 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
aa5ca48f | 614 | |
df7e5265 | 615 | x86_low_init_dregs (&info->debug_reg_state); |
aa5ca48f DE |
616 | |
617 | return info; | |
618 | } | |
619 | ||
3a8a0396 DB |
620 | /* Target routine for linux_new_fork. */ |
621 | ||
622 | static void | |
623 | x86_linux_new_fork (struct process_info *parent, struct process_info *child) | |
624 | { | |
625 | /* These are allocated by linux_add_process. */ | |
626 | gdb_assert (parent->priv != NULL | |
627 | && parent->priv->arch_private != NULL); | |
628 | gdb_assert (child->priv != NULL | |
629 | && child->priv->arch_private != NULL); | |
630 | ||
631 | /* Linux kernel before 2.6.33 commit | |
632 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
633 | will inherit hardware debug registers from parent | |
634 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
635 | zeroed debug registers. | |
636 | ||
637 | GDB core assumes the child inherits the watchpoints/hw | |
638 | breakpoints of the parent, and will remove them all from the | |
639 | forked off process. Copy the debug registers mirrors into the | |
640 | new process so that all breakpoints and watchpoints can be | |
641 | removed together. The debug registers mirror will become zeroed | |
642 | in the end before detaching the forked off process, thus making | |
643 | this compatible with older Linux kernels too. */ | |
644 | ||
645 | *child->priv->arch_private = *parent->priv->arch_private; | |
646 | } | |
647 | ||
70a0bb6b GB |
648 | /* See nat/x86-dregs.h. */ |
649 | ||
650 | struct x86_debug_reg_state * | |
651 | x86_debug_reg_state (pid_t pid) | |
652 | { | |
653 | struct process_info *proc = find_process_pid (pid); | |
654 | ||
655 | return &proc->priv->arch_private->debug_reg_state; | |
656 | } | |
aa5ca48f | 657 | \f |
d0722149 DE |
658 | /* When GDBSERVER is built as a 64-bit application on linux, the |
659 | PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since | |
660 | debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same | |
661 | as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit | |
662 | conversion in-place ourselves. */ | |
663 | ||
9cf12d57 | 664 | /* Convert a ptrace/host siginfo object, into/from the siginfo in the |
d0722149 DE |
665 | layout of the inferiors' architecture. Returns true if any |
666 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
9cf12d57 | 667 | from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to |
d0722149 DE |
668 | INF. */ |
669 | ||
670 | static int | |
9cf12d57 | 671 | x86_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) |
d0722149 DE |
672 | { |
673 | #ifdef __x86_64__ | |
760256f9 | 674 | unsigned int machine; |
0bfdf32f | 675 | int tid = lwpid_of (current_thread); |
760256f9 PA |
676 | int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); |
677 | ||
d0722149 | 678 | /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ |
3aee8918 | 679 | if (!is_64bit_tdesc ()) |
9cf12d57 | 680 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
c23bbc1c | 681 | FIXUP_32); |
c92b5177 | 682 | /* No fixup for native x32 GDB. */ |
760256f9 | 683 | else if (!is_elf64 && sizeof (void *) == 8) |
9cf12d57 | 684 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
c23bbc1c | 685 | FIXUP_X32); |
d0722149 DE |
686 | #endif |
687 | ||
688 | return 0; | |
689 | } | |
690 | \f | |
1570b33e L |
691 | static int use_xml; |
692 | ||
3aee8918 PA |
693 | /* Format of XSAVE extended state is: |
694 | struct | |
695 | { | |
696 | fxsave_bytes[0..463] | |
697 | sw_usable_bytes[464..511] | |
698 | xstate_hdr_bytes[512..575] | |
699 | avx_bytes[576..831] | |
700 | future_state etc | |
701 | }; | |
702 | ||
703 | Same memory layout will be used for the coredump NT_X86_XSTATE | |
704 | representing the XSAVE extended state registers. | |
705 | ||
706 | The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled | |
707 | extended state mask, which is the same as the extended control register | |
708 | 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask | |
709 | together with the mask saved in the xstate_hdr_bytes to determine what | |
710 | states the processor/OS supports and what state, used or initialized, | |
711 | the process/thread is in. */ | |
712 | #define I386_LINUX_XSAVE_XCR0_OFFSET 464 | |
713 | ||
714 | /* Does the current host support the GETFPXREGS request? The header | |
715 | file may or may not define it, and even if it is defined, the | |
716 | kernel will return EIO if it's running on a pre-SSE processor. */ | |
717 | int have_ptrace_getfpxregs = | |
718 | #ifdef HAVE_PTRACE_GETFPXREGS | |
719 | -1 | |
720 | #else | |
721 | 0 | |
722 | #endif | |
723 | ; | |
1570b33e | 724 | |
3aee8918 PA |
725 | /* Get Linux/x86 target description from running target. */ |
726 | ||
727 | static const struct target_desc * | |
728 | x86_linux_read_description (void) | |
1570b33e | 729 | { |
3aee8918 PA |
730 | unsigned int machine; |
731 | int is_elf64; | |
a196ebeb | 732 | int xcr0_features; |
3aee8918 PA |
733 | int tid; |
734 | static uint64_t xcr0; | |
3a13a53b | 735 | struct regset_info *regset; |
1570b33e | 736 | |
0bfdf32f | 737 | tid = lwpid_of (current_thread); |
1570b33e | 738 | |
3aee8918 | 739 | is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); |
45ba0d02 | 740 | |
3aee8918 | 741 | if (sizeof (void *) == 4) |
3a13a53b | 742 | { |
3aee8918 PA |
743 | if (is_elf64 > 0) |
744 | error (_("Can't debug 64-bit process with 32-bit GDBserver")); | |
745 | #ifndef __x86_64__ | |
746 | else if (machine == EM_X86_64) | |
747 | error (_("Can't debug x86-64 process with 32-bit GDBserver")); | |
748 | #endif | |
749 | } | |
3a13a53b | 750 | |
3aee8918 PA |
751 | #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS |
752 | if (machine == EM_386 && have_ptrace_getfpxregs == -1) | |
753 | { | |
754 | elf_fpxregset_t fpxregs; | |
3a13a53b | 755 | |
3aee8918 | 756 | if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0) |
3a13a53b | 757 | { |
3aee8918 PA |
758 | have_ptrace_getfpxregs = 0; |
759 | have_ptrace_getregset = 0; | |
760 | return tdesc_i386_mmx_linux; | |
3a13a53b | 761 | } |
3aee8918 PA |
762 | else |
763 | have_ptrace_getfpxregs = 1; | |
3a13a53b | 764 | } |
1570b33e L |
765 | #endif |
766 | ||
767 | if (!use_xml) | |
768 | { | |
df7e5265 | 769 | x86_xcr0 = X86_XSTATE_SSE_MASK; |
3aee8918 | 770 | |
1570b33e L |
771 | /* Don't use XML. */ |
772 | #ifdef __x86_64__ | |
3aee8918 PA |
773 | if (machine == EM_X86_64) |
774 | return tdesc_amd64_linux_no_xml; | |
1570b33e | 775 | else |
1570b33e | 776 | #endif |
3aee8918 | 777 | return tdesc_i386_linux_no_xml; |
1570b33e L |
778 | } |
779 | ||
1570b33e L |
780 | if (have_ptrace_getregset == -1) |
781 | { | |
df7e5265 | 782 | uint64_t xstateregs[(X86_XSTATE_SSE_SIZE / sizeof (uint64_t))]; |
1570b33e | 783 | struct iovec iov; |
1570b33e L |
784 | |
785 | iov.iov_base = xstateregs; | |
786 | iov.iov_len = sizeof (xstateregs); | |
787 | ||
788 | /* Check if PTRACE_GETREGSET works. */ | |
3aee8918 PA |
789 | if (ptrace (PTRACE_GETREGSET, tid, |
790 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
791 | have_ptrace_getregset = 0; | |
792 | else | |
1570b33e | 793 | { |
3aee8918 PA |
794 | have_ptrace_getregset = 1; |
795 | ||
796 | /* Get XCR0 from XSAVE extended state. */ | |
797 | xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET | |
798 | / sizeof (uint64_t))]; | |
799 | ||
800 | /* Use PTRACE_GETREGSET if it is available. */ | |
801 | for (regset = x86_regsets; | |
802 | regset->fill_function != NULL; regset++) | |
803 | if (regset->get_request == PTRACE_GETREGSET) | |
df7e5265 | 804 | regset->size = X86_XSTATE_SIZE (xcr0); |
3aee8918 PA |
805 | else if (regset->type != GENERAL_REGS) |
806 | regset->size = 0; | |
1570b33e | 807 | } |
1570b33e L |
808 | } |
809 | ||
3aee8918 | 810 | /* Check the native XCR0 only if PTRACE_GETREGSET is available. */ |
a196ebeb | 811 | xcr0_features = (have_ptrace_getregset |
2e1e43e1 | 812 | && (xcr0 & X86_XSTATE_ALL_MASK)); |
3aee8918 | 813 | |
a196ebeb | 814 | if (xcr0_features) |
3aee8918 | 815 | x86_xcr0 = xcr0; |
1570b33e | 816 | |
3aee8918 PA |
817 | if (machine == EM_X86_64) |
818 | { | |
1570b33e | 819 | #ifdef __x86_64__ |
a196ebeb | 820 | if (is_elf64) |
3aee8918 | 821 | { |
a196ebeb WT |
822 | if (xcr0_features) |
823 | { | |
df7e5265 | 824 | switch (xcr0 & X86_XSTATE_ALL_MASK) |
a196ebeb | 825 | { |
51547df6 MS |
826 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
827 | return tdesc_amd64_avx_mpx_avx512_pku_linux; | |
01f9f808 | 828 | |
a1fa17ee MS |
829 | case X86_XSTATE_AVX_AVX512_MASK: |
830 | return tdesc_amd64_avx_avx512_linux; | |
831 | ||
2b863f51 WT |
832 | case X86_XSTATE_AVX_MPX_MASK: |
833 | return tdesc_amd64_avx_mpx_linux; | |
834 | ||
df7e5265 | 835 | case X86_XSTATE_MPX_MASK: |
a196ebeb WT |
836 | return tdesc_amd64_mpx_linux; |
837 | ||
df7e5265 | 838 | case X86_XSTATE_AVX_MASK: |
a196ebeb WT |
839 | return tdesc_amd64_avx_linux; |
840 | ||
841 | default: | |
842 | return tdesc_amd64_linux; | |
843 | } | |
844 | } | |
4d47af5c | 845 | else |
a196ebeb | 846 | return tdesc_amd64_linux; |
3aee8918 PA |
847 | } |
848 | else | |
849 | { | |
a196ebeb WT |
850 | if (xcr0_features) |
851 | { | |
df7e5265 | 852 | switch (xcr0 & X86_XSTATE_ALL_MASK) |
a196ebeb | 853 | { |
51547df6 MS |
854 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
855 | /* No x32 MPX and PKU, fall back to avx_avx512. */ | |
856 | return tdesc_x32_avx_avx512_linux; | |
857 | ||
22049425 | 858 | case X86_XSTATE_AVX_AVX512_MASK: |
a1fa17ee | 859 | return tdesc_x32_avx_avx512_linux; |
01f9f808 | 860 | |
df7e5265 GB |
861 | case X86_XSTATE_MPX_MASK: /* No MPX on x32. */ |
862 | case X86_XSTATE_AVX_MASK: | |
a196ebeb WT |
863 | return tdesc_x32_avx_linux; |
864 | ||
865 | default: | |
866 | return tdesc_x32_linux; | |
867 | } | |
868 | } | |
3aee8918 | 869 | else |
a196ebeb | 870 | return tdesc_x32_linux; |
1570b33e | 871 | } |
3aee8918 | 872 | #endif |
1570b33e | 873 | } |
3aee8918 PA |
874 | else |
875 | { | |
a196ebeb WT |
876 | if (xcr0_features) |
877 | { | |
df7e5265 | 878 | switch (xcr0 & X86_XSTATE_ALL_MASK) |
a196ebeb | 879 | { |
51547df6 MS |
880 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
881 | return tdesc_i386_avx_mpx_avx512_pku_linux; | |
01f9f808 | 882 | |
a1fa17ee MS |
883 | case (X86_XSTATE_AVX_AVX512_MASK): |
884 | return tdesc_i386_avx_avx512_linux; | |
885 | ||
df7e5265 | 886 | case (X86_XSTATE_MPX_MASK): |
a196ebeb WT |
887 | return tdesc_i386_mpx_linux; |
888 | ||
2b863f51 WT |
889 | case (X86_XSTATE_AVX_MPX_MASK): |
890 | return tdesc_i386_avx_mpx_linux; | |
891 | ||
df7e5265 | 892 | case (X86_XSTATE_AVX_MASK): |
a196ebeb WT |
893 | return tdesc_i386_avx_linux; |
894 | ||
895 | default: | |
896 | return tdesc_i386_linux; | |
897 | } | |
898 | } | |
3aee8918 PA |
899 | else |
900 | return tdesc_i386_linux; | |
901 | } | |
902 | ||
903 | gdb_assert_not_reached ("failed to return tdesc"); | |
904 | } | |
905 | ||
906 | /* Callback for find_inferior. Stops iteration when a thread with a | |
907 | given PID is found. */ | |
908 | ||
909 | static int | |
910 | same_process_callback (struct inferior_list_entry *entry, void *data) | |
911 | { | |
912 | int pid = *(int *) data; | |
913 | ||
914 | return (ptid_get_pid (entry->id) == pid); | |
915 | } | |
916 | ||
917 | /* Callback for for_each_inferior. Calls the arch_setup routine for | |
918 | each process. */ | |
919 | ||
920 | static void | |
921 | x86_arch_setup_process_callback (struct inferior_list_entry *entry) | |
922 | { | |
923 | int pid = ptid_get_pid (entry->id); | |
924 | ||
925 | /* Look up any thread of this processes. */ | |
0bfdf32f | 926 | current_thread |
3aee8918 PA |
927 | = (struct thread_info *) find_inferior (&all_threads, |
928 | same_process_callback, &pid); | |
929 | ||
930 | the_low_target.arch_setup (); | |
931 | } | |
932 | ||
933 | /* Update all the target description of all processes; a new GDB | |
934 | connected, and it may or not support xml target descriptions. */ | |
935 | ||
936 | static void | |
937 | x86_linux_update_xmltarget (void) | |
938 | { | |
0bfdf32f | 939 | struct thread_info *saved_thread = current_thread; |
3aee8918 PA |
940 | |
941 | /* Before changing the register cache's internal layout, flush the | |
942 | contents of the current valid caches back to the threads, and | |
943 | release the current regcache objects. */ | |
944 | regcache_release (); | |
945 | ||
946 | for_each_inferior (&all_processes, x86_arch_setup_process_callback); | |
947 | ||
0bfdf32f | 948 | current_thread = saved_thread; |
1570b33e L |
949 | } |
950 | ||
951 | /* Process qSupported query, "xmlRegisters=". Update the buffer size for | |
952 | PTRACE_GETREGSET. */ | |
953 | ||
954 | static void | |
06e03fff | 955 | x86_linux_process_qsupported (char **features, int count) |
1570b33e | 956 | { |
06e03fff PA |
957 | int i; |
958 | ||
1570b33e L |
959 | /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters=" |
960 | with "i386" in qSupported query, it supports x86 XML target | |
961 | descriptions. */ | |
962 | use_xml = 0; | |
06e03fff | 963 | for (i = 0; i < count; i++) |
1570b33e | 964 | { |
06e03fff | 965 | const char *feature = features[i]; |
1570b33e | 966 | |
06e03fff | 967 | if (startswith (feature, "xmlRegisters=")) |
1570b33e | 968 | { |
06e03fff PA |
969 | char *copy = xstrdup (feature + 13); |
970 | char *p; | |
971 | ||
972 | for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ",")) | |
1570b33e | 973 | { |
06e03fff PA |
974 | if (strcmp (p, "i386") == 0) |
975 | { | |
976 | use_xml = 1; | |
977 | break; | |
978 | } | |
1570b33e | 979 | } |
1570b33e | 980 | |
06e03fff PA |
981 | free (copy); |
982 | } | |
1570b33e | 983 | } |
1570b33e L |
984 | x86_linux_update_xmltarget (); |
985 | } | |
986 | ||
3aee8918 | 987 | /* Common for x86/x86-64. */ |
d0722149 | 988 | |
3aee8918 PA |
989 | static struct regsets_info x86_regsets_info = |
990 | { | |
991 | x86_regsets, /* regsets */ | |
992 | 0, /* num_regsets */ | |
993 | NULL, /* disabled_regsets */ | |
994 | }; | |
214d508e L |
995 | |
996 | #ifdef __x86_64__ | |
3aee8918 PA |
997 | static struct regs_info amd64_linux_regs_info = |
998 | { | |
999 | NULL, /* regset_bitmap */ | |
1000 | NULL, /* usrregs_info */ | |
1001 | &x86_regsets_info | |
1002 | }; | |
d0722149 | 1003 | #endif |
3aee8918 PA |
1004 | static struct usrregs_info i386_linux_usrregs_info = |
1005 | { | |
1006 | I386_NUM_REGS, | |
1007 | i386_regmap, | |
1008 | }; | |
d0722149 | 1009 | |
3aee8918 PA |
1010 | static struct regs_info i386_linux_regs_info = |
1011 | { | |
1012 | NULL, /* regset_bitmap */ | |
1013 | &i386_linux_usrregs_info, | |
1014 | &x86_regsets_info | |
1015 | }; | |
d0722149 | 1016 | |
3aee8918 PA |
1017 | const struct regs_info * |
1018 | x86_linux_regs_info (void) | |
1019 | { | |
1020 | #ifdef __x86_64__ | |
1021 | if (is_64bit_tdesc ()) | |
1022 | return &amd64_linux_regs_info; | |
1023 | else | |
1024 | #endif | |
1025 | return &i386_linux_regs_info; | |
1026 | } | |
d0722149 | 1027 | |
3aee8918 PA |
1028 | /* Initialize the target description for the architecture of the |
1029 | inferior. */ | |
1570b33e | 1030 | |
3aee8918 PA |
1031 | static void |
1032 | x86_arch_setup (void) | |
1033 | { | |
1034 | current_process ()->tdesc = x86_linux_read_description (); | |
d0722149 DE |
1035 | } |
1036 | ||
82075af2 JS |
1037 | /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return |
1038 | code. This should only be called if LWP got a SYSCALL_SIGTRAP. */ | |
1039 | ||
1040 | static void | |
4cc32bec | 1041 | x86_get_syscall_trapinfo (struct regcache *regcache, int *sysno) |
82075af2 JS |
1042 | { |
1043 | int use_64bit = register_size (regcache->tdesc, 0) == 8; | |
1044 | ||
1045 | if (use_64bit) | |
1046 | { | |
1047 | long l_sysno; | |
82075af2 JS |
1048 | |
1049 | collect_register_by_name (regcache, "orig_rax", &l_sysno); | |
82075af2 | 1050 | *sysno = (int) l_sysno; |
82075af2 JS |
1051 | } |
1052 | else | |
4cc32bec | 1053 | collect_register_by_name (regcache, "orig_eax", sysno); |
82075af2 JS |
1054 | } |
1055 | ||
219f2f23 PA |
1056 | static int |
1057 | x86_supports_tracepoints (void) | |
1058 | { | |
1059 | return 1; | |
1060 | } | |
1061 | ||
fa593d66 PA |
1062 | static void |
1063 | append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf) | |
1064 | { | |
1065 | write_inferior_memory (*to, buf, len); | |
1066 | *to += len; | |
1067 | } | |
1068 | ||
1069 | static int | |
a121b7c1 | 1070 | push_opcode (unsigned char *buf, const char *op) |
fa593d66 PA |
1071 | { |
1072 | unsigned char *buf_org = buf; | |
1073 | ||
1074 | while (1) | |
1075 | { | |
1076 | char *endptr; | |
1077 | unsigned long ul = strtoul (op, &endptr, 16); | |
1078 | ||
1079 | if (endptr == op) | |
1080 | break; | |
1081 | ||
1082 | *buf++ = ul; | |
1083 | op = endptr; | |
1084 | } | |
1085 | ||
1086 | return buf - buf_org; | |
1087 | } | |
1088 | ||
1089 | #ifdef __x86_64__ | |
1090 | ||
1091 | /* Build a jump pad that saves registers and calls a collection | |
1092 | function. Writes a jump instruction to the jump pad to | |
1093 | JJUMPAD_INSN. The caller is responsible to write it in at the | |
1094 | tracepoint address. */ | |
1095 | ||
1096 | static int | |
1097 | amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1098 | CORE_ADDR collector, | |
1099 | CORE_ADDR lockaddr, | |
1100 | ULONGEST orig_size, | |
1101 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1102 | CORE_ADDR *trampoline, |
1103 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1104 | unsigned char *jjump_pad_insn, |
1105 | ULONGEST *jjump_pad_insn_size, | |
1106 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1107 | CORE_ADDR *adjusted_insn_addr_end, |
1108 | char *err) | |
fa593d66 PA |
1109 | { |
1110 | unsigned char buf[40]; | |
1111 | int i, offset; | |
f4647387 YQ |
1112 | int64_t loffset; |
1113 | ||
fa593d66 PA |
1114 | CORE_ADDR buildaddr = *jump_entry; |
1115 | ||
1116 | /* Build the jump pad. */ | |
1117 | ||
1118 | /* First, do tracepoint data collection. Save registers. */ | |
1119 | i = 0; | |
1120 | /* Need to ensure stack pointer saved first. */ | |
1121 | buf[i++] = 0x54; /* push %rsp */ | |
1122 | buf[i++] = 0x55; /* push %rbp */ | |
1123 | buf[i++] = 0x57; /* push %rdi */ | |
1124 | buf[i++] = 0x56; /* push %rsi */ | |
1125 | buf[i++] = 0x52; /* push %rdx */ | |
1126 | buf[i++] = 0x51; /* push %rcx */ | |
1127 | buf[i++] = 0x53; /* push %rbx */ | |
1128 | buf[i++] = 0x50; /* push %rax */ | |
1129 | buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */ | |
1130 | buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */ | |
1131 | buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */ | |
1132 | buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */ | |
1133 | buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */ | |
1134 | buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */ | |
1135 | buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */ | |
1136 | buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */ | |
1137 | buf[i++] = 0x9c; /* pushfq */ | |
c8ef42ee | 1138 | buf[i++] = 0x48; /* movabs <addr>,%rdi */ |
fa593d66 | 1139 | buf[i++] = 0xbf; |
c8ef42ee PA |
1140 | memcpy (buf + i, &tpaddr, 8); |
1141 | i += 8; | |
fa593d66 PA |
1142 | buf[i++] = 0x57; /* push %rdi */ |
1143 | append_insns (&buildaddr, i, buf); | |
1144 | ||
1145 | /* Stack space for the collecting_t object. */ | |
1146 | i = 0; | |
1147 | i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */ | |
1148 | i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */ | |
1149 | memcpy (buf + i, &tpoint, 8); | |
1150 | i += 8; | |
1151 | i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */ | |
1152 | i += push_opcode (&buf[i], | |
1153 | "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */ | |
1154 | i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */ | |
1155 | append_insns (&buildaddr, i, buf); | |
1156 | ||
1157 | /* spin-lock. */ | |
1158 | i = 0; | |
1159 | i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */ | |
1160 | memcpy (&buf[i], (void *) &lockaddr, 8); | |
1161 | i += 8; | |
1162 | i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */ | |
1163 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1164 | i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */ | |
1165 | i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */ | |
1166 | i += push_opcode (&buf[i], "75 f4"); /* jne <again> */ | |
1167 | append_insns (&buildaddr, i, buf); | |
1168 | ||
1169 | /* Set up the gdb_collect call. */ | |
1170 | /* At this point, (stack pointer + 0x18) is the base of our saved | |
1171 | register block. */ | |
1172 | ||
1173 | i = 0; | |
1174 | i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */ | |
1175 | i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */ | |
1176 | ||
1177 | /* tpoint address may be 64-bit wide. */ | |
1178 | i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */ | |
1179 | memcpy (buf + i, &tpoint, 8); | |
1180 | i += 8; | |
1181 | append_insns (&buildaddr, i, buf); | |
1182 | ||
1183 | /* The collector function being in the shared library, may be | |
1184 | >31-bits away off the jump pad. */ | |
1185 | i = 0; | |
1186 | i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */ | |
1187 | memcpy (buf + i, &collector, 8); | |
1188 | i += 8; | |
1189 | i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */ | |
1190 | append_insns (&buildaddr, i, buf); | |
1191 | ||
1192 | /* Clear the spin-lock. */ | |
1193 | i = 0; | |
1194 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1195 | i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */ | |
1196 | memcpy (buf + i, &lockaddr, 8); | |
1197 | i += 8; | |
1198 | append_insns (&buildaddr, i, buf); | |
1199 | ||
1200 | /* Remove stack that had been used for the collect_t object. */ | |
1201 | i = 0; | |
1202 | i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */ | |
1203 | append_insns (&buildaddr, i, buf); | |
1204 | ||
1205 | /* Restore register state. */ | |
1206 | i = 0; | |
1207 | buf[i++] = 0x48; /* add $0x8,%rsp */ | |
1208 | buf[i++] = 0x83; | |
1209 | buf[i++] = 0xc4; | |
1210 | buf[i++] = 0x08; | |
1211 | buf[i++] = 0x9d; /* popfq */ | |
1212 | buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */ | |
1213 | buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */ | |
1214 | buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */ | |
1215 | buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */ | |
1216 | buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */ | |
1217 | buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */ | |
1218 | buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */ | |
1219 | buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */ | |
1220 | buf[i++] = 0x58; /* pop %rax */ | |
1221 | buf[i++] = 0x5b; /* pop %rbx */ | |
1222 | buf[i++] = 0x59; /* pop %rcx */ | |
1223 | buf[i++] = 0x5a; /* pop %rdx */ | |
1224 | buf[i++] = 0x5e; /* pop %rsi */ | |
1225 | buf[i++] = 0x5f; /* pop %rdi */ | |
1226 | buf[i++] = 0x5d; /* pop %rbp */ | |
1227 | buf[i++] = 0x5c; /* pop %rsp */ | |
1228 | append_insns (&buildaddr, i, buf); | |
1229 | ||
1230 | /* Now, adjust the original instruction to execute in the jump | |
1231 | pad. */ | |
1232 | *adjusted_insn_addr = buildaddr; | |
1233 | relocate_instruction (&buildaddr, tpaddr); | |
1234 | *adjusted_insn_addr_end = buildaddr; | |
1235 | ||
1236 | /* Finally, write a jump back to the program. */ | |
f4647387 YQ |
1237 | |
1238 | loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); | |
1239 | if (loffset > INT_MAX || loffset < INT_MIN) | |
1240 | { | |
1241 | sprintf (err, | |
1242 | "E.Jump back from jump pad too far from tracepoint " | |
1243 | "(offset 0x%" PRIx64 " > int32).", loffset); | |
1244 | return 1; | |
1245 | } | |
1246 | ||
1247 | offset = (int) loffset; | |
fa593d66 PA |
1248 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
1249 | memcpy (buf + 1, &offset, 4); | |
1250 | append_insns (&buildaddr, sizeof (jump_insn), buf); | |
1251 | ||
1252 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1253 | is always done last (by our caller actually), so that we can | |
1254 | install fast tracepoints with threads running. This relies on | |
1255 | the agent's atomic write support. */ | |
f4647387 YQ |
1256 | loffset = *jump_entry - (tpaddr + sizeof (jump_insn)); |
1257 | if (loffset > INT_MAX || loffset < INT_MIN) | |
1258 | { | |
1259 | sprintf (err, | |
1260 | "E.Jump pad too far from tracepoint " | |
1261 | "(offset 0x%" PRIx64 " > int32).", loffset); | |
1262 | return 1; | |
1263 | } | |
1264 | ||
1265 | offset = (int) loffset; | |
1266 | ||
fa593d66 PA |
1267 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
1268 | memcpy (buf + 1, &offset, 4); | |
1269 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); | |
1270 | *jjump_pad_insn_size = sizeof (jump_insn); | |
1271 | ||
1272 | /* Return the end address of our pad. */ | |
1273 | *jump_entry = buildaddr; | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | #endif /* __x86_64__ */ | |
1279 | ||
1280 | /* Build a jump pad that saves registers and calls a collection | |
1281 | function. Writes a jump instruction to the jump pad to | |
1282 | JJUMPAD_INSN. The caller is responsible to write it in at the | |
1283 | tracepoint address. */ | |
1284 | ||
1285 | static int | |
1286 | i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1287 | CORE_ADDR collector, | |
1288 | CORE_ADDR lockaddr, | |
1289 | ULONGEST orig_size, | |
1290 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1291 | CORE_ADDR *trampoline, |
1292 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1293 | unsigned char *jjump_pad_insn, |
1294 | ULONGEST *jjump_pad_insn_size, | |
1295 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1296 | CORE_ADDR *adjusted_insn_addr_end, |
1297 | char *err) | |
fa593d66 PA |
1298 | { |
1299 | unsigned char buf[0x100]; | |
1300 | int i, offset; | |
1301 | CORE_ADDR buildaddr = *jump_entry; | |
1302 | ||
1303 | /* Build the jump pad. */ | |
1304 | ||
1305 | /* First, do tracepoint data collection. Save registers. */ | |
1306 | i = 0; | |
1307 | buf[i++] = 0x60; /* pushad */ | |
1308 | buf[i++] = 0x68; /* push tpaddr aka $pc */ | |
1309 | *((int *)(buf + i)) = (int) tpaddr; | |
1310 | i += 4; | |
1311 | buf[i++] = 0x9c; /* pushf */ | |
1312 | buf[i++] = 0x1e; /* push %ds */ | |
1313 | buf[i++] = 0x06; /* push %es */ | |
1314 | buf[i++] = 0x0f; /* push %fs */ | |
1315 | buf[i++] = 0xa0; | |
1316 | buf[i++] = 0x0f; /* push %gs */ | |
1317 | buf[i++] = 0xa8; | |
1318 | buf[i++] = 0x16; /* push %ss */ | |
1319 | buf[i++] = 0x0e; /* push %cs */ | |
1320 | append_insns (&buildaddr, i, buf); | |
1321 | ||
1322 | /* Stack space for the collecting_t object. */ | |
1323 | i = 0; | |
1324 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ | |
1325 | ||
1326 | /* Build the object. */ | |
1327 | i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */ | |
1328 | memcpy (buf + i, &tpoint, 4); | |
1329 | i += 4; | |
1330 | i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */ | |
1331 | ||
1332 | i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */ | |
1333 | i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */ | |
1334 | append_insns (&buildaddr, i, buf); | |
1335 | ||
1336 | /* spin-lock. Note this is using cmpxchg, which leaves i386 behind. | |
1337 | If we cared for it, this could be using xchg alternatively. */ | |
1338 | ||
1339 | i = 0; | |
1340 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1341 | i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg | |
1342 | %esp,<lockaddr> */ | |
1343 | memcpy (&buf[i], (void *) &lockaddr, 4); | |
1344 | i += 4; | |
1345 | i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */ | |
1346 | i += push_opcode (&buf[i], "75 f2"); /* jne <again> */ | |
1347 | append_insns (&buildaddr, i, buf); | |
1348 | ||
1349 | ||
1350 | /* Set up arguments to the gdb_collect call. */ | |
1351 | i = 0; | |
1352 | i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */ | |
1353 | i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */ | |
1354 | i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */ | |
1355 | append_insns (&buildaddr, i, buf); | |
1356 | ||
1357 | i = 0; | |
1358 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ | |
1359 | append_insns (&buildaddr, i, buf); | |
1360 | ||
1361 | i = 0; | |
1362 | i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */ | |
1363 | memcpy (&buf[i], (void *) &tpoint, 4); | |
1364 | i += 4; | |
1365 | append_insns (&buildaddr, i, buf); | |
1366 | ||
1367 | buf[0] = 0xe8; /* call <reladdr> */ | |
1368 | offset = collector - (buildaddr + sizeof (jump_insn)); | |
1369 | memcpy (buf + 1, &offset, 4); | |
1370 | append_insns (&buildaddr, 5, buf); | |
1371 | /* Clean up after the call. */ | |
1372 | buf[0] = 0x83; /* add $0x8,%esp */ | |
1373 | buf[1] = 0xc4; | |
1374 | buf[2] = 0x08; | |
1375 | append_insns (&buildaddr, 3, buf); | |
1376 | ||
1377 | ||
1378 | /* Clear the spin-lock. This would need the LOCK prefix on older | |
1379 | broken archs. */ | |
1380 | i = 0; | |
1381 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1382 | i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */ | |
1383 | memcpy (buf + i, &lockaddr, 4); | |
1384 | i += 4; | |
1385 | append_insns (&buildaddr, i, buf); | |
1386 | ||
1387 | ||
1388 | /* Remove stack that had been used for the collect_t object. */ | |
1389 | i = 0; | |
1390 | i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */ | |
1391 | append_insns (&buildaddr, i, buf); | |
1392 | ||
1393 | i = 0; | |
1394 | buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */ | |
1395 | buf[i++] = 0xc4; | |
1396 | buf[i++] = 0x04; | |
1397 | buf[i++] = 0x17; /* pop %ss */ | |
1398 | buf[i++] = 0x0f; /* pop %gs */ | |
1399 | buf[i++] = 0xa9; | |
1400 | buf[i++] = 0x0f; /* pop %fs */ | |
1401 | buf[i++] = 0xa1; | |
1402 | buf[i++] = 0x07; /* pop %es */ | |
405f8e94 | 1403 | buf[i++] = 0x1f; /* pop %ds */ |
fa593d66 PA |
1404 | buf[i++] = 0x9d; /* popf */ |
1405 | buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */ | |
1406 | buf[i++] = 0xc4; | |
1407 | buf[i++] = 0x04; | |
1408 | buf[i++] = 0x61; /* popad */ | |
1409 | append_insns (&buildaddr, i, buf); | |
1410 | ||
1411 | /* Now, adjust the original instruction to execute in the jump | |
1412 | pad. */ | |
1413 | *adjusted_insn_addr = buildaddr; | |
1414 | relocate_instruction (&buildaddr, tpaddr); | |
1415 | *adjusted_insn_addr_end = buildaddr; | |
1416 | ||
1417 | /* Write the jump back to the program. */ | |
1418 | offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); | |
1419 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1420 | memcpy (buf + 1, &offset, 4); | |
1421 | append_insns (&buildaddr, sizeof (jump_insn), buf); | |
1422 | ||
1423 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1424 | is always done last (by our caller actually), so that we can | |
1425 | install fast tracepoints with threads running. This relies on | |
1426 | the agent's atomic write support. */ | |
405f8e94 SS |
1427 | if (orig_size == 4) |
1428 | { | |
1429 | /* Create a trampoline. */ | |
1430 | *trampoline_size = sizeof (jump_insn); | |
1431 | if (!claim_trampoline_space (*trampoline_size, trampoline)) | |
1432 | { | |
1433 | /* No trampoline space available. */ | |
1434 | strcpy (err, | |
1435 | "E.Cannot allocate trampoline space needed for fast " | |
1436 | "tracepoints on 4-byte instructions."); | |
1437 | return 1; | |
1438 | } | |
1439 | ||
1440 | offset = *jump_entry - (*trampoline + sizeof (jump_insn)); | |
1441 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1442 | memcpy (buf + 1, &offset, 4); | |
1443 | write_inferior_memory (*trampoline, buf, sizeof (jump_insn)); | |
1444 | ||
1445 | /* Use a 16-bit relative jump instruction to jump to the trampoline. */ | |
1446 | offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff; | |
1447 | memcpy (buf, small_jump_insn, sizeof (small_jump_insn)); | |
1448 | memcpy (buf + 2, &offset, 2); | |
1449 | memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn)); | |
1450 | *jjump_pad_insn_size = sizeof (small_jump_insn); | |
1451 | } | |
1452 | else | |
1453 | { | |
1454 | /* Else use a 32-bit relative jump instruction. */ | |
1455 | offset = *jump_entry - (tpaddr + sizeof (jump_insn)); | |
1456 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1457 | memcpy (buf + 1, &offset, 4); | |
1458 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); | |
1459 | *jjump_pad_insn_size = sizeof (jump_insn); | |
1460 | } | |
fa593d66 PA |
1461 | |
1462 | /* Return the end address of our pad. */ | |
1463 | *jump_entry = buildaddr; | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static int | |
1469 | x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1470 | CORE_ADDR collector, | |
1471 | CORE_ADDR lockaddr, | |
1472 | ULONGEST orig_size, | |
1473 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1474 | CORE_ADDR *trampoline, |
1475 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1476 | unsigned char *jjump_pad_insn, |
1477 | ULONGEST *jjump_pad_insn_size, | |
1478 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1479 | CORE_ADDR *adjusted_insn_addr_end, |
1480 | char *err) | |
fa593d66 PA |
1481 | { |
1482 | #ifdef __x86_64__ | |
3aee8918 | 1483 | if (is_64bit_tdesc ()) |
fa593d66 PA |
1484 | return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr, |
1485 | collector, lockaddr, | |
1486 | orig_size, jump_entry, | |
405f8e94 | 1487 | trampoline, trampoline_size, |
fa593d66 PA |
1488 | jjump_pad_insn, |
1489 | jjump_pad_insn_size, | |
1490 | adjusted_insn_addr, | |
405f8e94 SS |
1491 | adjusted_insn_addr_end, |
1492 | err); | |
fa593d66 PA |
1493 | #endif |
1494 | ||
1495 | return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr, | |
1496 | collector, lockaddr, | |
1497 | orig_size, jump_entry, | |
405f8e94 | 1498 | trampoline, trampoline_size, |
fa593d66 PA |
1499 | jjump_pad_insn, |
1500 | jjump_pad_insn_size, | |
1501 | adjusted_insn_addr, | |
405f8e94 SS |
1502 | adjusted_insn_addr_end, |
1503 | err); | |
1504 | } | |
1505 | ||
1506 | /* Return the minimum instruction length for fast tracepoints on x86/x86-64 | |
1507 | architectures. */ | |
1508 | ||
1509 | static int | |
1510 | x86_get_min_fast_tracepoint_insn_len (void) | |
1511 | { | |
1512 | static int warned_about_fast_tracepoints = 0; | |
1513 | ||
1514 | #ifdef __x86_64__ | |
1515 | /* On x86-64, 5-byte jump instructions with a 4-byte offset are always | |
1516 | used for fast tracepoints. */ | |
3aee8918 | 1517 | if (is_64bit_tdesc ()) |
405f8e94 SS |
1518 | return 5; |
1519 | #endif | |
1520 | ||
58b4daa5 | 1521 | if (agent_loaded_p ()) |
405f8e94 SS |
1522 | { |
1523 | char errbuf[IPA_BUFSIZ]; | |
1524 | ||
1525 | errbuf[0] = '\0'; | |
1526 | ||
1527 | /* On x86, if trampolines are available, then 4-byte jump instructions | |
1528 | with a 2-byte offset may be used, otherwise 5-byte jump instructions | |
1529 | with a 4-byte offset are used instead. */ | |
1530 | if (have_fast_tracepoint_trampoline_buffer (errbuf)) | |
1531 | return 4; | |
1532 | else | |
1533 | { | |
1534 | /* GDB has no channel to explain to user why a shorter fast | |
1535 | tracepoint is not possible, but at least make GDBserver | |
1536 | mention that something has gone awry. */ | |
1537 | if (!warned_about_fast_tracepoints) | |
1538 | { | |
1539 | warning ("4-byte fast tracepoints not available; %s\n", errbuf); | |
1540 | warned_about_fast_tracepoints = 1; | |
1541 | } | |
1542 | return 5; | |
1543 | } | |
1544 | } | |
1545 | else | |
1546 | { | |
1547 | /* Indicate that the minimum length is currently unknown since the IPA | |
1548 | has not loaded yet. */ | |
1549 | return 0; | |
1550 | } | |
fa593d66 PA |
1551 | } |
1552 | ||
6a271cae PA |
1553 | static void |
1554 | add_insns (unsigned char *start, int len) | |
1555 | { | |
1556 | CORE_ADDR buildaddr = current_insn_ptr; | |
1557 | ||
1558 | if (debug_threads) | |
87ce2a04 DE |
1559 | debug_printf ("Adding %d bytes of insn at %s\n", |
1560 | len, paddress (buildaddr)); | |
6a271cae PA |
1561 | |
1562 | append_insns (&buildaddr, len, start); | |
1563 | current_insn_ptr = buildaddr; | |
1564 | } | |
1565 | ||
6a271cae PA |
1566 | /* Our general strategy for emitting code is to avoid specifying raw |
1567 | bytes whenever possible, and instead copy a block of inline asm | |
1568 | that is embedded in the function. This is a little messy, because | |
1569 | we need to keep the compiler from discarding what looks like dead | |
1570 | code, plus suppress various warnings. */ | |
1571 | ||
9e4344e5 PA |
1572 | #define EMIT_ASM(NAME, INSNS) \ |
1573 | do \ | |
1574 | { \ | |
1575 | extern unsigned char start_ ## NAME, end_ ## NAME; \ | |
1576 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ | |
493e2a69 | 1577 | __asm__ ("jmp end_" #NAME "\n" \ |
9e4344e5 PA |
1578 | "\t" "start_" #NAME ":" \ |
1579 | "\t" INSNS "\n" \ | |
1580 | "\t" "end_" #NAME ":"); \ | |
1581 | } while (0) | |
6a271cae PA |
1582 | |
1583 | #ifdef __x86_64__ | |
1584 | ||
1585 | #define EMIT_ASM32(NAME,INSNS) \ | |
9e4344e5 PA |
1586 | do \ |
1587 | { \ | |
1588 | extern unsigned char start_ ## NAME, end_ ## NAME; \ | |
1589 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ | |
1590 | __asm__ (".code32\n" \ | |
1591 | "\t" "jmp end_" #NAME "\n" \ | |
1592 | "\t" "start_" #NAME ":\n" \ | |
1593 | "\t" INSNS "\n" \ | |
1594 | "\t" "end_" #NAME ":\n" \ | |
1595 | ".code64\n"); \ | |
1596 | } while (0) | |
6a271cae PA |
1597 | |
1598 | #else | |
1599 | ||
1600 | #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS) | |
1601 | ||
1602 | #endif | |
1603 | ||
1604 | #ifdef __x86_64__ | |
1605 | ||
1606 | static void | |
1607 | amd64_emit_prologue (void) | |
1608 | { | |
1609 | EMIT_ASM (amd64_prologue, | |
1610 | "pushq %rbp\n\t" | |
1611 | "movq %rsp,%rbp\n\t" | |
1612 | "sub $0x20,%rsp\n\t" | |
1613 | "movq %rdi,-8(%rbp)\n\t" | |
1614 | "movq %rsi,-16(%rbp)"); | |
1615 | } | |
1616 | ||
1617 | ||
1618 | static void | |
1619 | amd64_emit_epilogue (void) | |
1620 | { | |
1621 | EMIT_ASM (amd64_epilogue, | |
1622 | "movq -16(%rbp),%rdi\n\t" | |
1623 | "movq %rax,(%rdi)\n\t" | |
1624 | "xor %rax,%rax\n\t" | |
1625 | "leave\n\t" | |
1626 | "ret"); | |
1627 | } | |
1628 | ||
1629 | static void | |
1630 | amd64_emit_add (void) | |
1631 | { | |
1632 | EMIT_ASM (amd64_add, | |
1633 | "add (%rsp),%rax\n\t" | |
1634 | "lea 0x8(%rsp),%rsp"); | |
1635 | } | |
1636 | ||
1637 | static void | |
1638 | amd64_emit_sub (void) | |
1639 | { | |
1640 | EMIT_ASM (amd64_sub, | |
1641 | "sub %rax,(%rsp)\n\t" | |
1642 | "pop %rax"); | |
1643 | } | |
1644 | ||
1645 | static void | |
1646 | amd64_emit_mul (void) | |
1647 | { | |
1648 | emit_error = 1; | |
1649 | } | |
1650 | ||
1651 | static void | |
1652 | amd64_emit_lsh (void) | |
1653 | { | |
1654 | emit_error = 1; | |
1655 | } | |
1656 | ||
1657 | static void | |
1658 | amd64_emit_rsh_signed (void) | |
1659 | { | |
1660 | emit_error = 1; | |
1661 | } | |
1662 | ||
1663 | static void | |
1664 | amd64_emit_rsh_unsigned (void) | |
1665 | { | |
1666 | emit_error = 1; | |
1667 | } | |
1668 | ||
1669 | static void | |
1670 | amd64_emit_ext (int arg) | |
1671 | { | |
1672 | switch (arg) | |
1673 | { | |
1674 | case 8: | |
1675 | EMIT_ASM (amd64_ext_8, | |
1676 | "cbtw\n\t" | |
1677 | "cwtl\n\t" | |
1678 | "cltq"); | |
1679 | break; | |
1680 | case 16: | |
1681 | EMIT_ASM (amd64_ext_16, | |
1682 | "cwtl\n\t" | |
1683 | "cltq"); | |
1684 | break; | |
1685 | case 32: | |
1686 | EMIT_ASM (amd64_ext_32, | |
1687 | "cltq"); | |
1688 | break; | |
1689 | default: | |
1690 | emit_error = 1; | |
1691 | } | |
1692 | } | |
1693 | ||
1694 | static void | |
1695 | amd64_emit_log_not (void) | |
1696 | { | |
1697 | EMIT_ASM (amd64_log_not, | |
1698 | "test %rax,%rax\n\t" | |
1699 | "sete %cl\n\t" | |
1700 | "movzbq %cl,%rax"); | |
1701 | } | |
1702 | ||
1703 | static void | |
1704 | amd64_emit_bit_and (void) | |
1705 | { | |
1706 | EMIT_ASM (amd64_and, | |
1707 | "and (%rsp),%rax\n\t" | |
1708 | "lea 0x8(%rsp),%rsp"); | |
1709 | } | |
1710 | ||
1711 | static void | |
1712 | amd64_emit_bit_or (void) | |
1713 | { | |
1714 | EMIT_ASM (amd64_or, | |
1715 | "or (%rsp),%rax\n\t" | |
1716 | "lea 0x8(%rsp),%rsp"); | |
1717 | } | |
1718 | ||
1719 | static void | |
1720 | amd64_emit_bit_xor (void) | |
1721 | { | |
1722 | EMIT_ASM (amd64_xor, | |
1723 | "xor (%rsp),%rax\n\t" | |
1724 | "lea 0x8(%rsp),%rsp"); | |
1725 | } | |
1726 | ||
1727 | static void | |
1728 | amd64_emit_bit_not (void) | |
1729 | { | |
1730 | EMIT_ASM (amd64_bit_not, | |
1731 | "xorq $0xffffffffffffffff,%rax"); | |
1732 | } | |
1733 | ||
1734 | static void | |
1735 | amd64_emit_equal (void) | |
1736 | { | |
1737 | EMIT_ASM (amd64_equal, | |
1738 | "cmp %rax,(%rsp)\n\t" | |
1739 | "je .Lamd64_equal_true\n\t" | |
1740 | "xor %rax,%rax\n\t" | |
1741 | "jmp .Lamd64_equal_end\n\t" | |
1742 | ".Lamd64_equal_true:\n\t" | |
1743 | "mov $0x1,%rax\n\t" | |
1744 | ".Lamd64_equal_end:\n\t" | |
1745 | "lea 0x8(%rsp),%rsp"); | |
1746 | } | |
1747 | ||
1748 | static void | |
1749 | amd64_emit_less_signed (void) | |
1750 | { | |
1751 | EMIT_ASM (amd64_less_signed, | |
1752 | "cmp %rax,(%rsp)\n\t" | |
1753 | "jl .Lamd64_less_signed_true\n\t" | |
1754 | "xor %rax,%rax\n\t" | |
1755 | "jmp .Lamd64_less_signed_end\n\t" | |
1756 | ".Lamd64_less_signed_true:\n\t" | |
1757 | "mov $1,%rax\n\t" | |
1758 | ".Lamd64_less_signed_end:\n\t" | |
1759 | "lea 0x8(%rsp),%rsp"); | |
1760 | } | |
1761 | ||
1762 | static void | |
1763 | amd64_emit_less_unsigned (void) | |
1764 | { | |
1765 | EMIT_ASM (amd64_less_unsigned, | |
1766 | "cmp %rax,(%rsp)\n\t" | |
1767 | "jb .Lamd64_less_unsigned_true\n\t" | |
1768 | "xor %rax,%rax\n\t" | |
1769 | "jmp .Lamd64_less_unsigned_end\n\t" | |
1770 | ".Lamd64_less_unsigned_true:\n\t" | |
1771 | "mov $1,%rax\n\t" | |
1772 | ".Lamd64_less_unsigned_end:\n\t" | |
1773 | "lea 0x8(%rsp),%rsp"); | |
1774 | } | |
1775 | ||
1776 | static void | |
1777 | amd64_emit_ref (int size) | |
1778 | { | |
1779 | switch (size) | |
1780 | { | |
1781 | case 1: | |
1782 | EMIT_ASM (amd64_ref1, | |
1783 | "movb (%rax),%al"); | |
1784 | break; | |
1785 | case 2: | |
1786 | EMIT_ASM (amd64_ref2, | |
1787 | "movw (%rax),%ax"); | |
1788 | break; | |
1789 | case 4: | |
1790 | EMIT_ASM (amd64_ref4, | |
1791 | "movl (%rax),%eax"); | |
1792 | break; | |
1793 | case 8: | |
1794 | EMIT_ASM (amd64_ref8, | |
1795 | "movq (%rax),%rax"); | |
1796 | break; | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | static void | |
1801 | amd64_emit_if_goto (int *offset_p, int *size_p) | |
1802 | { | |
1803 | EMIT_ASM (amd64_if_goto, | |
1804 | "mov %rax,%rcx\n\t" | |
1805 | "pop %rax\n\t" | |
1806 | "cmp $0,%rcx\n\t" | |
1807 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); | |
1808 | if (offset_p) | |
1809 | *offset_p = 10; | |
1810 | if (size_p) | |
1811 | *size_p = 4; | |
1812 | } | |
1813 | ||
1814 | static void | |
1815 | amd64_emit_goto (int *offset_p, int *size_p) | |
1816 | { | |
1817 | EMIT_ASM (amd64_goto, | |
1818 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); | |
1819 | if (offset_p) | |
1820 | *offset_p = 1; | |
1821 | if (size_p) | |
1822 | *size_p = 4; | |
1823 | } | |
1824 | ||
1825 | static void | |
1826 | amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) | |
1827 | { | |
1828 | int diff = (to - (from + size)); | |
1829 | unsigned char buf[sizeof (int)]; | |
1830 | ||
1831 | if (size != 4) | |
1832 | { | |
1833 | emit_error = 1; | |
1834 | return; | |
1835 | } | |
1836 | ||
1837 | memcpy (buf, &diff, sizeof (int)); | |
1838 | write_inferior_memory (from, buf, sizeof (int)); | |
1839 | } | |
1840 | ||
1841 | static void | |
4e29fb54 | 1842 | amd64_emit_const (LONGEST num) |
6a271cae PA |
1843 | { |
1844 | unsigned char buf[16]; | |
1845 | int i; | |
1846 | CORE_ADDR buildaddr = current_insn_ptr; | |
1847 | ||
1848 | i = 0; | |
1849 | buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */ | |
b00ad6ff | 1850 | memcpy (&buf[i], &num, sizeof (num)); |
6a271cae PA |
1851 | i += 8; |
1852 | append_insns (&buildaddr, i, buf); | |
1853 | current_insn_ptr = buildaddr; | |
1854 | } | |
1855 | ||
1856 | static void | |
1857 | amd64_emit_call (CORE_ADDR fn) | |
1858 | { | |
1859 | unsigned char buf[16]; | |
1860 | int i; | |
1861 | CORE_ADDR buildaddr; | |
4e29fb54 | 1862 | LONGEST offset64; |
6a271cae PA |
1863 | |
1864 | /* The destination function being in the shared library, may be | |
1865 | >31-bits away off the compiled code pad. */ | |
1866 | ||
1867 | buildaddr = current_insn_ptr; | |
1868 | ||
1869 | offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */); | |
1870 | ||
1871 | i = 0; | |
1872 | ||
1873 | if (offset64 > INT_MAX || offset64 < INT_MIN) | |
1874 | { | |
1875 | /* Offset is too large for a call. Use callq, but that requires | |
1876 | a register, so avoid it if possible. Use r10, since it is | |
1877 | call-clobbered, we don't have to push/pop it. */ | |
1878 | buf[i++] = 0x48; /* mov $fn,%r10 */ | |
1879 | buf[i++] = 0xba; | |
1880 | memcpy (buf + i, &fn, 8); | |
1881 | i += 8; | |
1882 | buf[i++] = 0xff; /* callq *%r10 */ | |
1883 | buf[i++] = 0xd2; | |
1884 | } | |
1885 | else | |
1886 | { | |
1887 | int offset32 = offset64; /* we know we can't overflow here. */ | |
ed036b40 PA |
1888 | |
1889 | buf[i++] = 0xe8; /* call <reladdr> */ | |
6a271cae PA |
1890 | memcpy (buf + i, &offset32, 4); |
1891 | i += 4; | |
1892 | } | |
1893 | ||
1894 | append_insns (&buildaddr, i, buf); | |
1895 | current_insn_ptr = buildaddr; | |
1896 | } | |
1897 | ||
1898 | static void | |
1899 | amd64_emit_reg (int reg) | |
1900 | { | |
1901 | unsigned char buf[16]; | |
1902 | int i; | |
1903 | CORE_ADDR buildaddr; | |
1904 | ||
1905 | /* Assume raw_regs is still in %rdi. */ | |
1906 | buildaddr = current_insn_ptr; | |
1907 | i = 0; | |
1908 | buf[i++] = 0xbe; /* mov $<n>,%esi */ | |
b00ad6ff | 1909 | memcpy (&buf[i], ®, sizeof (reg)); |
6a271cae PA |
1910 | i += 4; |
1911 | append_insns (&buildaddr, i, buf); | |
1912 | current_insn_ptr = buildaddr; | |
1913 | amd64_emit_call (get_raw_reg_func_addr ()); | |
1914 | } | |
1915 | ||
1916 | static void | |
1917 | amd64_emit_pop (void) | |
1918 | { | |
1919 | EMIT_ASM (amd64_pop, | |
1920 | "pop %rax"); | |
1921 | } | |
1922 | ||
1923 | static void | |
1924 | amd64_emit_stack_flush (void) | |
1925 | { | |
1926 | EMIT_ASM (amd64_stack_flush, | |
1927 | "push %rax"); | |
1928 | } | |
1929 | ||
1930 | static void | |
1931 | amd64_emit_zero_ext (int arg) | |
1932 | { | |
1933 | switch (arg) | |
1934 | { | |
1935 | case 8: | |
1936 | EMIT_ASM (amd64_zero_ext_8, | |
1937 | "and $0xff,%rax"); | |
1938 | break; | |
1939 | case 16: | |
1940 | EMIT_ASM (amd64_zero_ext_16, | |
1941 | "and $0xffff,%rax"); | |
1942 | break; | |
1943 | case 32: | |
1944 | EMIT_ASM (amd64_zero_ext_32, | |
1945 | "mov $0xffffffff,%rcx\n\t" | |
1946 | "and %rcx,%rax"); | |
1947 | break; | |
1948 | default: | |
1949 | emit_error = 1; | |
1950 | } | |
1951 | } | |
1952 | ||
1953 | static void | |
1954 | amd64_emit_swap (void) | |
1955 | { | |
1956 | EMIT_ASM (amd64_swap, | |
1957 | "mov %rax,%rcx\n\t" | |
1958 | "pop %rax\n\t" | |
1959 | "push %rcx"); | |
1960 | } | |
1961 | ||
1962 | static void | |
1963 | amd64_emit_stack_adjust (int n) | |
1964 | { | |
1965 | unsigned char buf[16]; | |
1966 | int i; | |
1967 | CORE_ADDR buildaddr = current_insn_ptr; | |
1968 | ||
1969 | i = 0; | |
1970 | buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */ | |
1971 | buf[i++] = 0x8d; | |
1972 | buf[i++] = 0x64; | |
1973 | buf[i++] = 0x24; | |
1974 | /* This only handles adjustments up to 16, but we don't expect any more. */ | |
1975 | buf[i++] = n * 8; | |
1976 | append_insns (&buildaddr, i, buf); | |
1977 | current_insn_ptr = buildaddr; | |
1978 | } | |
1979 | ||
1980 | /* FN's prototype is `LONGEST(*fn)(int)'. */ | |
1981 | ||
1982 | static void | |
1983 | amd64_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
1984 | { | |
1985 | unsigned char buf[16]; | |
1986 | int i; | |
1987 | CORE_ADDR buildaddr; | |
1988 | ||
1989 | buildaddr = current_insn_ptr; | |
1990 | i = 0; | |
1991 | buf[i++] = 0xbf; /* movl $<n>,%edi */ | |
b00ad6ff | 1992 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
1993 | i += 4; |
1994 | append_insns (&buildaddr, i, buf); | |
1995 | current_insn_ptr = buildaddr; | |
1996 | amd64_emit_call (fn); | |
1997 | } | |
1998 | ||
4e29fb54 | 1999 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
6a271cae PA |
2000 | |
2001 | static void | |
2002 | amd64_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
2003 | { | |
2004 | unsigned char buf[16]; | |
2005 | int i; | |
2006 | CORE_ADDR buildaddr; | |
2007 | ||
2008 | buildaddr = current_insn_ptr; | |
2009 | i = 0; | |
2010 | buf[i++] = 0xbf; /* movl $<n>,%edi */ | |
b00ad6ff | 2011 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2012 | i += 4; |
2013 | append_insns (&buildaddr, i, buf); | |
2014 | current_insn_ptr = buildaddr; | |
2015 | EMIT_ASM (amd64_void_call_2_a, | |
2016 | /* Save away a copy of the stack top. */ | |
2017 | "push %rax\n\t" | |
2018 | /* Also pass top as the second argument. */ | |
2019 | "mov %rax,%rsi"); | |
2020 | amd64_emit_call (fn); | |
2021 | EMIT_ASM (amd64_void_call_2_b, | |
2022 | /* Restore the stack top, %rax may have been trashed. */ | |
2023 | "pop %rax"); | |
2024 | } | |
2025 | ||
6b9801d4 SS |
2026 | void |
2027 | amd64_emit_eq_goto (int *offset_p, int *size_p) | |
2028 | { | |
2029 | EMIT_ASM (amd64_eq, | |
2030 | "cmp %rax,(%rsp)\n\t" | |
2031 | "jne .Lamd64_eq_fallthru\n\t" | |
2032 | "lea 0x8(%rsp),%rsp\n\t" | |
2033 | "pop %rax\n\t" | |
2034 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2035 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2036 | ".Lamd64_eq_fallthru:\n\t" | |
2037 | "lea 0x8(%rsp),%rsp\n\t" | |
2038 | "pop %rax"); | |
2039 | ||
2040 | if (offset_p) | |
2041 | *offset_p = 13; | |
2042 | if (size_p) | |
2043 | *size_p = 4; | |
2044 | } | |
2045 | ||
2046 | void | |
2047 | amd64_emit_ne_goto (int *offset_p, int *size_p) | |
2048 | { | |
2049 | EMIT_ASM (amd64_ne, | |
2050 | "cmp %rax,(%rsp)\n\t" | |
2051 | "je .Lamd64_ne_fallthru\n\t" | |
2052 | "lea 0x8(%rsp),%rsp\n\t" | |
2053 | "pop %rax\n\t" | |
2054 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2055 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2056 | ".Lamd64_ne_fallthru:\n\t" | |
2057 | "lea 0x8(%rsp),%rsp\n\t" | |
2058 | "pop %rax"); | |
2059 | ||
2060 | if (offset_p) | |
2061 | *offset_p = 13; | |
2062 | if (size_p) | |
2063 | *size_p = 4; | |
2064 | } | |
2065 | ||
2066 | void | |
2067 | amd64_emit_lt_goto (int *offset_p, int *size_p) | |
2068 | { | |
2069 | EMIT_ASM (amd64_lt, | |
2070 | "cmp %rax,(%rsp)\n\t" | |
2071 | "jnl .Lamd64_lt_fallthru\n\t" | |
2072 | "lea 0x8(%rsp),%rsp\n\t" | |
2073 | "pop %rax\n\t" | |
2074 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2075 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2076 | ".Lamd64_lt_fallthru:\n\t" | |
2077 | "lea 0x8(%rsp),%rsp\n\t" | |
2078 | "pop %rax"); | |
2079 | ||
2080 | if (offset_p) | |
2081 | *offset_p = 13; | |
2082 | if (size_p) | |
2083 | *size_p = 4; | |
2084 | } | |
2085 | ||
2086 | void | |
2087 | amd64_emit_le_goto (int *offset_p, int *size_p) | |
2088 | { | |
2089 | EMIT_ASM (amd64_le, | |
2090 | "cmp %rax,(%rsp)\n\t" | |
2091 | "jnle .Lamd64_le_fallthru\n\t" | |
2092 | "lea 0x8(%rsp),%rsp\n\t" | |
2093 | "pop %rax\n\t" | |
2094 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2095 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2096 | ".Lamd64_le_fallthru:\n\t" | |
2097 | "lea 0x8(%rsp),%rsp\n\t" | |
2098 | "pop %rax"); | |
2099 | ||
2100 | if (offset_p) | |
2101 | *offset_p = 13; | |
2102 | if (size_p) | |
2103 | *size_p = 4; | |
2104 | } | |
2105 | ||
2106 | void | |
2107 | amd64_emit_gt_goto (int *offset_p, int *size_p) | |
2108 | { | |
2109 | EMIT_ASM (amd64_gt, | |
2110 | "cmp %rax,(%rsp)\n\t" | |
2111 | "jng .Lamd64_gt_fallthru\n\t" | |
2112 | "lea 0x8(%rsp),%rsp\n\t" | |
2113 | "pop %rax\n\t" | |
2114 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2115 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2116 | ".Lamd64_gt_fallthru:\n\t" | |
2117 | "lea 0x8(%rsp),%rsp\n\t" | |
2118 | "pop %rax"); | |
2119 | ||
2120 | if (offset_p) | |
2121 | *offset_p = 13; | |
2122 | if (size_p) | |
2123 | *size_p = 4; | |
2124 | } | |
2125 | ||
2126 | void | |
2127 | amd64_emit_ge_goto (int *offset_p, int *size_p) | |
2128 | { | |
2129 | EMIT_ASM (amd64_ge, | |
2130 | "cmp %rax,(%rsp)\n\t" | |
2131 | "jnge .Lamd64_ge_fallthru\n\t" | |
2132 | ".Lamd64_ge_jump:\n\t" | |
2133 | "lea 0x8(%rsp),%rsp\n\t" | |
2134 | "pop %rax\n\t" | |
2135 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2136 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2137 | ".Lamd64_ge_fallthru:\n\t" | |
2138 | "lea 0x8(%rsp),%rsp\n\t" | |
2139 | "pop %rax"); | |
2140 | ||
2141 | if (offset_p) | |
2142 | *offset_p = 13; | |
2143 | if (size_p) | |
2144 | *size_p = 4; | |
2145 | } | |
2146 | ||
6a271cae PA |
2147 | struct emit_ops amd64_emit_ops = |
2148 | { | |
2149 | amd64_emit_prologue, | |
2150 | amd64_emit_epilogue, | |
2151 | amd64_emit_add, | |
2152 | amd64_emit_sub, | |
2153 | amd64_emit_mul, | |
2154 | amd64_emit_lsh, | |
2155 | amd64_emit_rsh_signed, | |
2156 | amd64_emit_rsh_unsigned, | |
2157 | amd64_emit_ext, | |
2158 | amd64_emit_log_not, | |
2159 | amd64_emit_bit_and, | |
2160 | amd64_emit_bit_or, | |
2161 | amd64_emit_bit_xor, | |
2162 | amd64_emit_bit_not, | |
2163 | amd64_emit_equal, | |
2164 | amd64_emit_less_signed, | |
2165 | amd64_emit_less_unsigned, | |
2166 | amd64_emit_ref, | |
2167 | amd64_emit_if_goto, | |
2168 | amd64_emit_goto, | |
2169 | amd64_write_goto_address, | |
2170 | amd64_emit_const, | |
2171 | amd64_emit_call, | |
2172 | amd64_emit_reg, | |
2173 | amd64_emit_pop, | |
2174 | amd64_emit_stack_flush, | |
2175 | amd64_emit_zero_ext, | |
2176 | amd64_emit_swap, | |
2177 | amd64_emit_stack_adjust, | |
2178 | amd64_emit_int_call_1, | |
6b9801d4 SS |
2179 | amd64_emit_void_call_2, |
2180 | amd64_emit_eq_goto, | |
2181 | amd64_emit_ne_goto, | |
2182 | amd64_emit_lt_goto, | |
2183 | amd64_emit_le_goto, | |
2184 | amd64_emit_gt_goto, | |
2185 | amd64_emit_ge_goto | |
6a271cae PA |
2186 | }; |
2187 | ||
2188 | #endif /* __x86_64__ */ | |
2189 | ||
2190 | static void | |
2191 | i386_emit_prologue (void) | |
2192 | { | |
2193 | EMIT_ASM32 (i386_prologue, | |
2194 | "push %ebp\n\t" | |
bf15cbda SS |
2195 | "mov %esp,%ebp\n\t" |
2196 | "push %ebx"); | |
6a271cae PA |
2197 | /* At this point, the raw regs base address is at 8(%ebp), and the |
2198 | value pointer is at 12(%ebp). */ | |
2199 | } | |
2200 | ||
2201 | static void | |
2202 | i386_emit_epilogue (void) | |
2203 | { | |
2204 | EMIT_ASM32 (i386_epilogue, | |
2205 | "mov 12(%ebp),%ecx\n\t" | |
2206 | "mov %eax,(%ecx)\n\t" | |
2207 | "mov %ebx,0x4(%ecx)\n\t" | |
2208 | "xor %eax,%eax\n\t" | |
bf15cbda | 2209 | "pop %ebx\n\t" |
6a271cae PA |
2210 | "pop %ebp\n\t" |
2211 | "ret"); | |
2212 | } | |
2213 | ||
2214 | static void | |
2215 | i386_emit_add (void) | |
2216 | { | |
2217 | EMIT_ASM32 (i386_add, | |
2218 | "add (%esp),%eax\n\t" | |
2219 | "adc 0x4(%esp),%ebx\n\t" | |
2220 | "lea 0x8(%esp),%esp"); | |
2221 | } | |
2222 | ||
2223 | static void | |
2224 | i386_emit_sub (void) | |
2225 | { | |
2226 | EMIT_ASM32 (i386_sub, | |
2227 | "subl %eax,(%esp)\n\t" | |
2228 | "sbbl %ebx,4(%esp)\n\t" | |
2229 | "pop %eax\n\t" | |
2230 | "pop %ebx\n\t"); | |
2231 | } | |
2232 | ||
2233 | static void | |
2234 | i386_emit_mul (void) | |
2235 | { | |
2236 | emit_error = 1; | |
2237 | } | |
2238 | ||
2239 | static void | |
2240 | i386_emit_lsh (void) | |
2241 | { | |
2242 | emit_error = 1; | |
2243 | } | |
2244 | ||
2245 | static void | |
2246 | i386_emit_rsh_signed (void) | |
2247 | { | |
2248 | emit_error = 1; | |
2249 | } | |
2250 | ||
2251 | static void | |
2252 | i386_emit_rsh_unsigned (void) | |
2253 | { | |
2254 | emit_error = 1; | |
2255 | } | |
2256 | ||
2257 | static void | |
2258 | i386_emit_ext (int arg) | |
2259 | { | |
2260 | switch (arg) | |
2261 | { | |
2262 | case 8: | |
2263 | EMIT_ASM32 (i386_ext_8, | |
2264 | "cbtw\n\t" | |
2265 | "cwtl\n\t" | |
2266 | "movl %eax,%ebx\n\t" | |
2267 | "sarl $31,%ebx"); | |
2268 | break; | |
2269 | case 16: | |
2270 | EMIT_ASM32 (i386_ext_16, | |
2271 | "cwtl\n\t" | |
2272 | "movl %eax,%ebx\n\t" | |
2273 | "sarl $31,%ebx"); | |
2274 | break; | |
2275 | case 32: | |
2276 | EMIT_ASM32 (i386_ext_32, | |
2277 | "movl %eax,%ebx\n\t" | |
2278 | "sarl $31,%ebx"); | |
2279 | break; | |
2280 | default: | |
2281 | emit_error = 1; | |
2282 | } | |
2283 | } | |
2284 | ||
2285 | static void | |
2286 | i386_emit_log_not (void) | |
2287 | { | |
2288 | EMIT_ASM32 (i386_log_not, | |
2289 | "or %ebx,%eax\n\t" | |
2290 | "test %eax,%eax\n\t" | |
2291 | "sete %cl\n\t" | |
2292 | "xor %ebx,%ebx\n\t" | |
2293 | "movzbl %cl,%eax"); | |
2294 | } | |
2295 | ||
2296 | static void | |
2297 | i386_emit_bit_and (void) | |
2298 | { | |
2299 | EMIT_ASM32 (i386_and, | |
2300 | "and (%esp),%eax\n\t" | |
2301 | "and 0x4(%esp),%ebx\n\t" | |
2302 | "lea 0x8(%esp),%esp"); | |
2303 | } | |
2304 | ||
2305 | static void | |
2306 | i386_emit_bit_or (void) | |
2307 | { | |
2308 | EMIT_ASM32 (i386_or, | |
2309 | "or (%esp),%eax\n\t" | |
2310 | "or 0x4(%esp),%ebx\n\t" | |
2311 | "lea 0x8(%esp),%esp"); | |
2312 | } | |
2313 | ||
2314 | static void | |
2315 | i386_emit_bit_xor (void) | |
2316 | { | |
2317 | EMIT_ASM32 (i386_xor, | |
2318 | "xor (%esp),%eax\n\t" | |
2319 | "xor 0x4(%esp),%ebx\n\t" | |
2320 | "lea 0x8(%esp),%esp"); | |
2321 | } | |
2322 | ||
2323 | static void | |
2324 | i386_emit_bit_not (void) | |
2325 | { | |
2326 | EMIT_ASM32 (i386_bit_not, | |
2327 | "xor $0xffffffff,%eax\n\t" | |
2328 | "xor $0xffffffff,%ebx\n\t"); | |
2329 | } | |
2330 | ||
2331 | static void | |
2332 | i386_emit_equal (void) | |
2333 | { | |
2334 | EMIT_ASM32 (i386_equal, | |
2335 | "cmpl %ebx,4(%esp)\n\t" | |
2336 | "jne .Li386_equal_false\n\t" | |
2337 | "cmpl %eax,(%esp)\n\t" | |
2338 | "je .Li386_equal_true\n\t" | |
2339 | ".Li386_equal_false:\n\t" | |
2340 | "xor %eax,%eax\n\t" | |
2341 | "jmp .Li386_equal_end\n\t" | |
2342 | ".Li386_equal_true:\n\t" | |
2343 | "mov $1,%eax\n\t" | |
2344 | ".Li386_equal_end:\n\t" | |
2345 | "xor %ebx,%ebx\n\t" | |
2346 | "lea 0x8(%esp),%esp"); | |
2347 | } | |
2348 | ||
2349 | static void | |
2350 | i386_emit_less_signed (void) | |
2351 | { | |
2352 | EMIT_ASM32 (i386_less_signed, | |
2353 | "cmpl %ebx,4(%esp)\n\t" | |
2354 | "jl .Li386_less_signed_true\n\t" | |
2355 | "jne .Li386_less_signed_false\n\t" | |
2356 | "cmpl %eax,(%esp)\n\t" | |
2357 | "jl .Li386_less_signed_true\n\t" | |
2358 | ".Li386_less_signed_false:\n\t" | |
2359 | "xor %eax,%eax\n\t" | |
2360 | "jmp .Li386_less_signed_end\n\t" | |
2361 | ".Li386_less_signed_true:\n\t" | |
2362 | "mov $1,%eax\n\t" | |
2363 | ".Li386_less_signed_end:\n\t" | |
2364 | "xor %ebx,%ebx\n\t" | |
2365 | "lea 0x8(%esp),%esp"); | |
2366 | } | |
2367 | ||
2368 | static void | |
2369 | i386_emit_less_unsigned (void) | |
2370 | { | |
2371 | EMIT_ASM32 (i386_less_unsigned, | |
2372 | "cmpl %ebx,4(%esp)\n\t" | |
2373 | "jb .Li386_less_unsigned_true\n\t" | |
2374 | "jne .Li386_less_unsigned_false\n\t" | |
2375 | "cmpl %eax,(%esp)\n\t" | |
2376 | "jb .Li386_less_unsigned_true\n\t" | |
2377 | ".Li386_less_unsigned_false:\n\t" | |
2378 | "xor %eax,%eax\n\t" | |
2379 | "jmp .Li386_less_unsigned_end\n\t" | |
2380 | ".Li386_less_unsigned_true:\n\t" | |
2381 | "mov $1,%eax\n\t" | |
2382 | ".Li386_less_unsigned_end:\n\t" | |
2383 | "xor %ebx,%ebx\n\t" | |
2384 | "lea 0x8(%esp),%esp"); | |
2385 | } | |
2386 | ||
2387 | static void | |
2388 | i386_emit_ref (int size) | |
2389 | { | |
2390 | switch (size) | |
2391 | { | |
2392 | case 1: | |
2393 | EMIT_ASM32 (i386_ref1, | |
2394 | "movb (%eax),%al"); | |
2395 | break; | |
2396 | case 2: | |
2397 | EMIT_ASM32 (i386_ref2, | |
2398 | "movw (%eax),%ax"); | |
2399 | break; | |
2400 | case 4: | |
2401 | EMIT_ASM32 (i386_ref4, | |
2402 | "movl (%eax),%eax"); | |
2403 | break; | |
2404 | case 8: | |
2405 | EMIT_ASM32 (i386_ref8, | |
2406 | "movl 4(%eax),%ebx\n\t" | |
2407 | "movl (%eax),%eax"); | |
2408 | break; | |
2409 | } | |
2410 | } | |
2411 | ||
2412 | static void | |
2413 | i386_emit_if_goto (int *offset_p, int *size_p) | |
2414 | { | |
2415 | EMIT_ASM32 (i386_if_goto, | |
2416 | "mov %eax,%ecx\n\t" | |
2417 | "or %ebx,%ecx\n\t" | |
2418 | "pop %eax\n\t" | |
2419 | "pop %ebx\n\t" | |
2420 | "cmpl $0,%ecx\n\t" | |
2421 | /* Don't trust the assembler to choose the right jump */ | |
2422 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); | |
2423 | ||
2424 | if (offset_p) | |
2425 | *offset_p = 11; /* be sure that this matches the sequence above */ | |
2426 | if (size_p) | |
2427 | *size_p = 4; | |
2428 | } | |
2429 | ||
2430 | static void | |
2431 | i386_emit_goto (int *offset_p, int *size_p) | |
2432 | { | |
2433 | EMIT_ASM32 (i386_goto, | |
2434 | /* Don't trust the assembler to choose the right jump */ | |
2435 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); | |
2436 | if (offset_p) | |
2437 | *offset_p = 1; | |
2438 | if (size_p) | |
2439 | *size_p = 4; | |
2440 | } | |
2441 | ||
2442 | static void | |
2443 | i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) | |
2444 | { | |
2445 | int diff = (to - (from + size)); | |
2446 | unsigned char buf[sizeof (int)]; | |
2447 | ||
2448 | /* We're only doing 4-byte sizes at the moment. */ | |
2449 | if (size != 4) | |
2450 | { | |
2451 | emit_error = 1; | |
2452 | return; | |
2453 | } | |
2454 | ||
2455 | memcpy (buf, &diff, sizeof (int)); | |
2456 | write_inferior_memory (from, buf, sizeof (int)); | |
2457 | } | |
2458 | ||
2459 | static void | |
4e29fb54 | 2460 | i386_emit_const (LONGEST num) |
6a271cae PA |
2461 | { |
2462 | unsigned char buf[16]; | |
b00ad6ff | 2463 | int i, hi, lo; |
6a271cae PA |
2464 | CORE_ADDR buildaddr = current_insn_ptr; |
2465 | ||
2466 | i = 0; | |
2467 | buf[i++] = 0xb8; /* mov $<n>,%eax */ | |
b00ad6ff NF |
2468 | lo = num & 0xffffffff; |
2469 | memcpy (&buf[i], &lo, sizeof (lo)); | |
6a271cae PA |
2470 | i += 4; |
2471 | hi = ((num >> 32) & 0xffffffff); | |
2472 | if (hi) | |
2473 | { | |
2474 | buf[i++] = 0xbb; /* mov $<n>,%ebx */ | |
b00ad6ff | 2475 | memcpy (&buf[i], &hi, sizeof (hi)); |
6a271cae PA |
2476 | i += 4; |
2477 | } | |
2478 | else | |
2479 | { | |
2480 | buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */ | |
2481 | } | |
2482 | append_insns (&buildaddr, i, buf); | |
2483 | current_insn_ptr = buildaddr; | |
2484 | } | |
2485 | ||
2486 | static void | |
2487 | i386_emit_call (CORE_ADDR fn) | |
2488 | { | |
2489 | unsigned char buf[16]; | |
2490 | int i, offset; | |
2491 | CORE_ADDR buildaddr; | |
2492 | ||
2493 | buildaddr = current_insn_ptr; | |
2494 | i = 0; | |
2495 | buf[i++] = 0xe8; /* call <reladdr> */ | |
2496 | offset = ((int) fn) - (buildaddr + 5); | |
2497 | memcpy (buf + 1, &offset, 4); | |
2498 | append_insns (&buildaddr, 5, buf); | |
2499 | current_insn_ptr = buildaddr; | |
2500 | } | |
2501 | ||
2502 | static void | |
2503 | i386_emit_reg (int reg) | |
2504 | { | |
2505 | unsigned char buf[16]; | |
2506 | int i; | |
2507 | CORE_ADDR buildaddr; | |
2508 | ||
2509 | EMIT_ASM32 (i386_reg_a, | |
2510 | "sub $0x8,%esp"); | |
2511 | buildaddr = current_insn_ptr; | |
2512 | i = 0; | |
2513 | buf[i++] = 0xb8; /* mov $<n>,%eax */ | |
b00ad6ff | 2514 | memcpy (&buf[i], ®, sizeof (reg)); |
6a271cae PA |
2515 | i += 4; |
2516 | append_insns (&buildaddr, i, buf); | |
2517 | current_insn_ptr = buildaddr; | |
2518 | EMIT_ASM32 (i386_reg_b, | |
2519 | "mov %eax,4(%esp)\n\t" | |
2520 | "mov 8(%ebp),%eax\n\t" | |
2521 | "mov %eax,(%esp)"); | |
2522 | i386_emit_call (get_raw_reg_func_addr ()); | |
2523 | EMIT_ASM32 (i386_reg_c, | |
2524 | "xor %ebx,%ebx\n\t" | |
2525 | "lea 0x8(%esp),%esp"); | |
2526 | } | |
2527 | ||
2528 | static void | |
2529 | i386_emit_pop (void) | |
2530 | { | |
2531 | EMIT_ASM32 (i386_pop, | |
2532 | "pop %eax\n\t" | |
2533 | "pop %ebx"); | |
2534 | } | |
2535 | ||
2536 | static void | |
2537 | i386_emit_stack_flush (void) | |
2538 | { | |
2539 | EMIT_ASM32 (i386_stack_flush, | |
2540 | "push %ebx\n\t" | |
2541 | "push %eax"); | |
2542 | } | |
2543 | ||
2544 | static void | |
2545 | i386_emit_zero_ext (int arg) | |
2546 | { | |
2547 | switch (arg) | |
2548 | { | |
2549 | case 8: | |
2550 | EMIT_ASM32 (i386_zero_ext_8, | |
2551 | "and $0xff,%eax\n\t" | |
2552 | "xor %ebx,%ebx"); | |
2553 | break; | |
2554 | case 16: | |
2555 | EMIT_ASM32 (i386_zero_ext_16, | |
2556 | "and $0xffff,%eax\n\t" | |
2557 | "xor %ebx,%ebx"); | |
2558 | break; | |
2559 | case 32: | |
2560 | EMIT_ASM32 (i386_zero_ext_32, | |
2561 | "xor %ebx,%ebx"); | |
2562 | break; | |
2563 | default: | |
2564 | emit_error = 1; | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | static void | |
2569 | i386_emit_swap (void) | |
2570 | { | |
2571 | EMIT_ASM32 (i386_swap, | |
2572 | "mov %eax,%ecx\n\t" | |
2573 | "mov %ebx,%edx\n\t" | |
2574 | "pop %eax\n\t" | |
2575 | "pop %ebx\n\t" | |
2576 | "push %edx\n\t" | |
2577 | "push %ecx"); | |
2578 | } | |
2579 | ||
2580 | static void | |
2581 | i386_emit_stack_adjust (int n) | |
2582 | { | |
2583 | unsigned char buf[16]; | |
2584 | int i; | |
2585 | CORE_ADDR buildaddr = current_insn_ptr; | |
2586 | ||
2587 | i = 0; | |
2588 | buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */ | |
2589 | buf[i++] = 0x64; | |
2590 | buf[i++] = 0x24; | |
2591 | buf[i++] = n * 8; | |
2592 | append_insns (&buildaddr, i, buf); | |
2593 | current_insn_ptr = buildaddr; | |
2594 | } | |
2595 | ||
2596 | /* FN's prototype is `LONGEST(*fn)(int)'. */ | |
2597 | ||
2598 | static void | |
2599 | i386_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
2600 | { | |
2601 | unsigned char buf[16]; | |
2602 | int i; | |
2603 | CORE_ADDR buildaddr; | |
2604 | ||
2605 | EMIT_ASM32 (i386_int_call_1_a, | |
2606 | /* Reserve a bit of stack space. */ | |
2607 | "sub $0x8,%esp"); | |
2608 | /* Put the one argument on the stack. */ | |
2609 | buildaddr = current_insn_ptr; | |
2610 | i = 0; | |
2611 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ | |
2612 | buf[i++] = 0x04; | |
2613 | buf[i++] = 0x24; | |
b00ad6ff | 2614 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2615 | i += 4; |
2616 | append_insns (&buildaddr, i, buf); | |
2617 | current_insn_ptr = buildaddr; | |
2618 | i386_emit_call (fn); | |
2619 | EMIT_ASM32 (i386_int_call_1_c, | |
2620 | "mov %edx,%ebx\n\t" | |
2621 | "lea 0x8(%esp),%esp"); | |
2622 | } | |
2623 | ||
4e29fb54 | 2624 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
6a271cae PA |
2625 | |
2626 | static void | |
2627 | i386_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
2628 | { | |
2629 | unsigned char buf[16]; | |
2630 | int i; | |
2631 | CORE_ADDR buildaddr; | |
2632 | ||
2633 | EMIT_ASM32 (i386_void_call_2_a, | |
2634 | /* Preserve %eax only; we don't have to worry about %ebx. */ | |
2635 | "push %eax\n\t" | |
2636 | /* Reserve a bit of stack space for arguments. */ | |
2637 | "sub $0x10,%esp\n\t" | |
2638 | /* Copy "top" to the second argument position. (Note that | |
2639 | we can't assume function won't scribble on its | |
2640 | arguments, so don't try to restore from this.) */ | |
2641 | "mov %eax,4(%esp)\n\t" | |
2642 | "mov %ebx,8(%esp)"); | |
2643 | /* Put the first argument on the stack. */ | |
2644 | buildaddr = current_insn_ptr; | |
2645 | i = 0; | |
2646 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ | |
2647 | buf[i++] = 0x04; | |
2648 | buf[i++] = 0x24; | |
b00ad6ff | 2649 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2650 | i += 4; |
2651 | append_insns (&buildaddr, i, buf); | |
2652 | current_insn_ptr = buildaddr; | |
2653 | i386_emit_call (fn); | |
2654 | EMIT_ASM32 (i386_void_call_2_b, | |
2655 | "lea 0x10(%esp),%esp\n\t" | |
2656 | /* Restore original stack top. */ | |
2657 | "pop %eax"); | |
2658 | } | |
2659 | ||
6b9801d4 SS |
2660 | |
2661 | void | |
2662 | i386_emit_eq_goto (int *offset_p, int *size_p) | |
2663 | { | |
2664 | EMIT_ASM32 (eq, | |
2665 | /* Check low half first, more likely to be decider */ | |
2666 | "cmpl %eax,(%esp)\n\t" | |
2667 | "jne .Leq_fallthru\n\t" | |
2668 | "cmpl %ebx,4(%esp)\n\t" | |
2669 | "jne .Leq_fallthru\n\t" | |
2670 | "lea 0x8(%esp),%esp\n\t" | |
2671 | "pop %eax\n\t" | |
2672 | "pop %ebx\n\t" | |
2673 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2674 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2675 | ".Leq_fallthru:\n\t" | |
2676 | "lea 0x8(%esp),%esp\n\t" | |
2677 | "pop %eax\n\t" | |
2678 | "pop %ebx"); | |
2679 | ||
2680 | if (offset_p) | |
2681 | *offset_p = 18; | |
2682 | if (size_p) | |
2683 | *size_p = 4; | |
2684 | } | |
2685 | ||
2686 | void | |
2687 | i386_emit_ne_goto (int *offset_p, int *size_p) | |
2688 | { | |
2689 | EMIT_ASM32 (ne, | |
2690 | /* Check low half first, more likely to be decider */ | |
2691 | "cmpl %eax,(%esp)\n\t" | |
2692 | "jne .Lne_jump\n\t" | |
2693 | "cmpl %ebx,4(%esp)\n\t" | |
2694 | "je .Lne_fallthru\n\t" | |
2695 | ".Lne_jump:\n\t" | |
2696 | "lea 0x8(%esp),%esp\n\t" | |
2697 | "pop %eax\n\t" | |
2698 | "pop %ebx\n\t" | |
2699 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2700 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2701 | ".Lne_fallthru:\n\t" | |
2702 | "lea 0x8(%esp),%esp\n\t" | |
2703 | "pop %eax\n\t" | |
2704 | "pop %ebx"); | |
2705 | ||
2706 | if (offset_p) | |
2707 | *offset_p = 18; | |
2708 | if (size_p) | |
2709 | *size_p = 4; | |
2710 | } | |
2711 | ||
2712 | void | |
2713 | i386_emit_lt_goto (int *offset_p, int *size_p) | |
2714 | { | |
2715 | EMIT_ASM32 (lt, | |
2716 | "cmpl %ebx,4(%esp)\n\t" | |
2717 | "jl .Llt_jump\n\t" | |
2718 | "jne .Llt_fallthru\n\t" | |
2719 | "cmpl %eax,(%esp)\n\t" | |
2720 | "jnl .Llt_fallthru\n\t" | |
2721 | ".Llt_jump:\n\t" | |
2722 | "lea 0x8(%esp),%esp\n\t" | |
2723 | "pop %eax\n\t" | |
2724 | "pop %ebx\n\t" | |
2725 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2726 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2727 | ".Llt_fallthru:\n\t" | |
2728 | "lea 0x8(%esp),%esp\n\t" | |
2729 | "pop %eax\n\t" | |
2730 | "pop %ebx"); | |
2731 | ||
2732 | if (offset_p) | |
2733 | *offset_p = 20; | |
2734 | if (size_p) | |
2735 | *size_p = 4; | |
2736 | } | |
2737 | ||
2738 | void | |
2739 | i386_emit_le_goto (int *offset_p, int *size_p) | |
2740 | { | |
2741 | EMIT_ASM32 (le, | |
2742 | "cmpl %ebx,4(%esp)\n\t" | |
2743 | "jle .Lle_jump\n\t" | |
2744 | "jne .Lle_fallthru\n\t" | |
2745 | "cmpl %eax,(%esp)\n\t" | |
2746 | "jnle .Lle_fallthru\n\t" | |
2747 | ".Lle_jump:\n\t" | |
2748 | "lea 0x8(%esp),%esp\n\t" | |
2749 | "pop %eax\n\t" | |
2750 | "pop %ebx\n\t" | |
2751 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2752 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2753 | ".Lle_fallthru:\n\t" | |
2754 | "lea 0x8(%esp),%esp\n\t" | |
2755 | "pop %eax\n\t" | |
2756 | "pop %ebx"); | |
2757 | ||
2758 | if (offset_p) | |
2759 | *offset_p = 20; | |
2760 | if (size_p) | |
2761 | *size_p = 4; | |
2762 | } | |
2763 | ||
2764 | void | |
2765 | i386_emit_gt_goto (int *offset_p, int *size_p) | |
2766 | { | |
2767 | EMIT_ASM32 (gt, | |
2768 | "cmpl %ebx,4(%esp)\n\t" | |
2769 | "jg .Lgt_jump\n\t" | |
2770 | "jne .Lgt_fallthru\n\t" | |
2771 | "cmpl %eax,(%esp)\n\t" | |
2772 | "jng .Lgt_fallthru\n\t" | |
2773 | ".Lgt_jump:\n\t" | |
2774 | "lea 0x8(%esp),%esp\n\t" | |
2775 | "pop %eax\n\t" | |
2776 | "pop %ebx\n\t" | |
2777 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2778 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2779 | ".Lgt_fallthru:\n\t" | |
2780 | "lea 0x8(%esp),%esp\n\t" | |
2781 | "pop %eax\n\t" | |
2782 | "pop %ebx"); | |
2783 | ||
2784 | if (offset_p) | |
2785 | *offset_p = 20; | |
2786 | if (size_p) | |
2787 | *size_p = 4; | |
2788 | } | |
2789 | ||
2790 | void | |
2791 | i386_emit_ge_goto (int *offset_p, int *size_p) | |
2792 | { | |
2793 | EMIT_ASM32 (ge, | |
2794 | "cmpl %ebx,4(%esp)\n\t" | |
2795 | "jge .Lge_jump\n\t" | |
2796 | "jne .Lge_fallthru\n\t" | |
2797 | "cmpl %eax,(%esp)\n\t" | |
2798 | "jnge .Lge_fallthru\n\t" | |
2799 | ".Lge_jump:\n\t" | |
2800 | "lea 0x8(%esp),%esp\n\t" | |
2801 | "pop %eax\n\t" | |
2802 | "pop %ebx\n\t" | |
2803 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2804 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2805 | ".Lge_fallthru:\n\t" | |
2806 | "lea 0x8(%esp),%esp\n\t" | |
2807 | "pop %eax\n\t" | |
2808 | "pop %ebx"); | |
2809 | ||
2810 | if (offset_p) | |
2811 | *offset_p = 20; | |
2812 | if (size_p) | |
2813 | *size_p = 4; | |
2814 | } | |
2815 | ||
6a271cae PA |
2816 | struct emit_ops i386_emit_ops = |
2817 | { | |
2818 | i386_emit_prologue, | |
2819 | i386_emit_epilogue, | |
2820 | i386_emit_add, | |
2821 | i386_emit_sub, | |
2822 | i386_emit_mul, | |
2823 | i386_emit_lsh, | |
2824 | i386_emit_rsh_signed, | |
2825 | i386_emit_rsh_unsigned, | |
2826 | i386_emit_ext, | |
2827 | i386_emit_log_not, | |
2828 | i386_emit_bit_and, | |
2829 | i386_emit_bit_or, | |
2830 | i386_emit_bit_xor, | |
2831 | i386_emit_bit_not, | |
2832 | i386_emit_equal, | |
2833 | i386_emit_less_signed, | |
2834 | i386_emit_less_unsigned, | |
2835 | i386_emit_ref, | |
2836 | i386_emit_if_goto, | |
2837 | i386_emit_goto, | |
2838 | i386_write_goto_address, | |
2839 | i386_emit_const, | |
2840 | i386_emit_call, | |
2841 | i386_emit_reg, | |
2842 | i386_emit_pop, | |
2843 | i386_emit_stack_flush, | |
2844 | i386_emit_zero_ext, | |
2845 | i386_emit_swap, | |
2846 | i386_emit_stack_adjust, | |
2847 | i386_emit_int_call_1, | |
6b9801d4 SS |
2848 | i386_emit_void_call_2, |
2849 | i386_emit_eq_goto, | |
2850 | i386_emit_ne_goto, | |
2851 | i386_emit_lt_goto, | |
2852 | i386_emit_le_goto, | |
2853 | i386_emit_gt_goto, | |
2854 | i386_emit_ge_goto | |
6a271cae PA |
2855 | }; |
2856 | ||
2857 | ||
2858 | static struct emit_ops * | |
2859 | x86_emit_ops (void) | |
2860 | { | |
2861 | #ifdef __x86_64__ | |
3aee8918 | 2862 | if (is_64bit_tdesc ()) |
6a271cae PA |
2863 | return &amd64_emit_ops; |
2864 | else | |
2865 | #endif | |
2866 | return &i386_emit_ops; | |
2867 | } | |
2868 | ||
dd373349 AT |
2869 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
2870 | ||
2871 | static const gdb_byte * | |
2872 | x86_sw_breakpoint_from_kind (int kind, int *size) | |
2873 | { | |
2874 | *size = x86_breakpoint_len; | |
2875 | return x86_breakpoint; | |
2876 | } | |
2877 | ||
c2d6af84 PA |
2878 | static int |
2879 | x86_supports_range_stepping (void) | |
2880 | { | |
2881 | return 1; | |
2882 | } | |
2883 | ||
7d00775e AT |
2884 | /* Implementation of linux_target_ops method "supports_hardware_single_step". |
2885 | */ | |
2886 | ||
2887 | static int | |
2888 | x86_supports_hardware_single_step (void) | |
2889 | { | |
2890 | return 1; | |
2891 | } | |
2892 | ||
ae91f625 MK |
2893 | static int |
2894 | x86_get_ipa_tdesc_idx (void) | |
2895 | { | |
2896 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
2897 | const struct target_desc *tdesc = regcache->tdesc; | |
2898 | ||
2899 | #ifdef __x86_64__ | |
2900 | if (tdesc == tdesc_amd64_linux || tdesc == tdesc_amd64_linux_no_xml | |
2901 | || tdesc == tdesc_x32_linux) | |
2902 | return X86_TDESC_SSE; | |
2903 | if (tdesc == tdesc_amd64_avx_linux || tdesc == tdesc_x32_avx_linux) | |
2904 | return X86_TDESC_AVX; | |
2905 | if (tdesc == tdesc_amd64_mpx_linux) | |
2906 | return X86_TDESC_MPX; | |
2b863f51 WT |
2907 | if (tdesc == tdesc_amd64_avx_mpx_linux) |
2908 | return X86_TDESC_AVX_MPX; | |
51547df6 MS |
2909 | if (tdesc == tdesc_amd64_avx_mpx_avx512_pku_linux || tdesc == tdesc_x32_avx_avx512_linux) |
2910 | return X86_TDESC_AVX_MPX_AVX512_PKU; | |
a1fa17ee MS |
2911 | if (tdesc == tdesc_amd64_avx_avx512_linux) |
2912 | return X86_TDESC_AVX_AVX512; | |
ae91f625 MK |
2913 | #endif |
2914 | ||
2915 | if (tdesc == tdesc_i386_mmx_linux) | |
2916 | return X86_TDESC_MMX; | |
2917 | if (tdesc == tdesc_i386_linux || tdesc == tdesc_i386_linux_no_xml) | |
2918 | return X86_TDESC_SSE; | |
2919 | if (tdesc == tdesc_i386_avx_linux) | |
2920 | return X86_TDESC_AVX; | |
2921 | if (tdesc == tdesc_i386_mpx_linux) | |
2922 | return X86_TDESC_MPX; | |
2b863f51 WT |
2923 | if (tdesc == tdesc_i386_avx_mpx_linux) |
2924 | return X86_TDESC_AVX_MPX; | |
51547df6 MS |
2925 | if (tdesc == tdesc_i386_avx_mpx_avx512_pku_linux) |
2926 | return X86_TDESC_AVX_MPX_AVX512_PKU; | |
a1fa17ee MS |
2927 | if (tdesc == tdesc_i386_avx_avx512_linux) |
2928 | return X86_TDESC_AVX_AVX512; | |
ae91f625 MK |
2929 | |
2930 | return 0; | |
2931 | } | |
2932 | ||
d0722149 DE |
2933 | /* This is initialized assuming an amd64 target. |
2934 | x86_arch_setup will correct it for i386 or amd64 targets. */ | |
2935 | ||
2936 | struct linux_target_ops the_low_target = | |
2937 | { | |
2938 | x86_arch_setup, | |
3aee8918 PA |
2939 | x86_linux_regs_info, |
2940 | x86_cannot_fetch_register, | |
2941 | x86_cannot_store_register, | |
c14dfd32 | 2942 | NULL, /* fetch_register */ |
d0722149 DE |
2943 | x86_get_pc, |
2944 | x86_set_pc, | |
dd373349 AT |
2945 | NULL, /* breakpoint_kind_from_pc */ |
2946 | x86_sw_breakpoint_from_kind, | |
d0722149 DE |
2947 | NULL, |
2948 | 1, | |
2949 | x86_breakpoint_at, | |
802e8e6d | 2950 | x86_supports_z_point_type, |
aa5ca48f DE |
2951 | x86_insert_point, |
2952 | x86_remove_point, | |
2953 | x86_stopped_by_watchpoint, | |
2954 | x86_stopped_data_address, | |
d0722149 DE |
2955 | /* collect_ptrace_register/supply_ptrace_register are not needed in the |
2956 | native i386 case (no registers smaller than an xfer unit), and are not | |
2957 | used in the biarch case (HAVE_LINUX_USRREGS is not defined). */ | |
2958 | NULL, | |
2959 | NULL, | |
2960 | /* need to fix up i386 siginfo if host is amd64 */ | |
2961 | x86_siginfo_fixup, | |
aa5ca48f DE |
2962 | x86_linux_new_process, |
2963 | x86_linux_new_thread, | |
3a8a0396 | 2964 | x86_linux_new_fork, |
1570b33e | 2965 | x86_linux_prepare_to_resume, |
219f2f23 | 2966 | x86_linux_process_qsupported, |
fa593d66 PA |
2967 | x86_supports_tracepoints, |
2968 | x86_get_thread_area, | |
6a271cae | 2969 | x86_install_fast_tracepoint_jump_pad, |
405f8e94 SS |
2970 | x86_emit_ops, |
2971 | x86_get_min_fast_tracepoint_insn_len, | |
c2d6af84 | 2972 | x86_supports_range_stepping, |
7d00775e AT |
2973 | NULL, /* breakpoint_kind_from_current_state */ |
2974 | x86_supports_hardware_single_step, | |
82075af2 | 2975 | x86_get_syscall_trapinfo, |
ae91f625 | 2976 | x86_get_ipa_tdesc_idx, |
d0722149 | 2977 | }; |
3aee8918 PA |
2978 | |
2979 | void | |
2980 | initialize_low_arch (void) | |
2981 | { | |
2982 | /* Initialize the Linux target descriptions. */ | |
2983 | #ifdef __x86_64__ | |
2984 | init_registers_amd64_linux (); | |
2985 | init_registers_amd64_avx_linux (); | |
a196ebeb | 2986 | init_registers_amd64_mpx_linux (); |
2b863f51 | 2987 | init_registers_amd64_avx_mpx_linux (); |
a1fa17ee | 2988 | init_registers_amd64_avx_avx512_linux (); |
51547df6 | 2989 | init_registers_amd64_avx_mpx_avx512_pku_linux (); |
a196ebeb | 2990 | |
3aee8918 | 2991 | init_registers_x32_linux (); |
7e5aaa09 | 2992 | init_registers_x32_avx_linux (); |
a1fa17ee | 2993 | init_registers_x32_avx_avx512_linux (); |
3aee8918 | 2994 | |
8d749320 | 2995 | tdesc_amd64_linux_no_xml = XNEW (struct target_desc); |
3aee8918 PA |
2996 | copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux); |
2997 | tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml; | |
2998 | #endif | |
2999 | init_registers_i386_linux (); | |
3000 | init_registers_i386_mmx_linux (); | |
3001 | init_registers_i386_avx_linux (); | |
a196ebeb | 3002 | init_registers_i386_mpx_linux (); |
2b863f51 | 3003 | init_registers_i386_avx_mpx_linux (); |
a1fa17ee | 3004 | init_registers_i386_avx_avx512_linux (); |
51547df6 | 3005 | init_registers_i386_avx_mpx_avx512_pku_linux (); |
3aee8918 | 3006 | |
8d749320 | 3007 | tdesc_i386_linux_no_xml = XNEW (struct target_desc); |
3aee8918 PA |
3008 | copy_target_description (tdesc_i386_linux_no_xml, tdesc_i386_linux); |
3009 | tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml; | |
3010 | ||
3011 | initialize_regsets_info (&x86_regsets_info); | |
3012 | } |