1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
75 #include "nat/gdb_ptrace.h"
78 #ifndef PTRACE_GET_THREAD_AREA
79 #define PTRACE_GET_THREAD_AREA 25
82 /* This definition comes from prctl.h, but some kernels may not have it. */
83 #ifndef PTRACE_ARCH_PRCTL
84 #define PTRACE_ARCH_PRCTL 30
87 /* The following definitions come from prctl.h, but may be absent
88 for certain configurations. */
90 #define ARCH_SET_GS 0x1001
91 #define ARCH_SET_FS 0x1002
92 #define ARCH_GET_FS 0x1003
93 #define ARCH_GET_GS 0x1004
96 /* Per-process arch-specific data we want to keep. */
98 struct arch_process_info
100 struct x86_debug_reg_state debug_reg_state
;
105 /* Mapping between the general-purpose registers in `struct user'
106 format and GDB's register array layout.
107 Note that the transfer layout uses 64-bit regs. */
108 static /*const*/ int i386_regmap
[] =
110 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
111 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
112 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
113 DS
* 8, ES
* 8, FS
* 8, GS
* 8
116 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
118 /* So code below doesn't have to care, i386 or amd64. */
119 #define ORIG_EAX ORIG_RAX
122 static const int x86_64_regmap
[] =
124 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
125 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
126 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
127 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
128 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
129 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
130 -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1,
134 -1, -1, -1, -1, -1, -1, -1, -1,
136 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
141 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
142 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
143 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
144 -1, -1, -1, -1, -1, -1, -1, -1,
145 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
146 -1, -1, -1, -1, -1, -1, -1, -1,
147 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
148 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
149 -1, -1, -1, -1, -1, -1, -1, -1,
150 -1, -1, -1, -1, -1, -1, -1, -1,
151 -1, -1, -1, -1, -1, -1, -1, -1,
155 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
156 #define X86_64_USER_REGS (GS + 1)
158 #else /* ! __x86_64__ */
160 /* Mapping between the general-purpose registers in `struct user'
161 format and GDB's register array layout. */
162 static /*const*/ int i386_regmap
[] =
164 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
165 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
166 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
167 DS
* 4, ES
* 4, FS
* 4, GS
* 4
170 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
178 /* Returns true if the current inferior belongs to a x86-64 process,
182 is_64bit_tdesc (void)
184 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
186 return register_size (regcache
->tdesc
, 0) == 8;
192 /* Called by libthread_db. */
195 ps_get_thread_area (struct ps_prochandle
*ph
,
196 lwpid_t lwpid
, int idx
, void **base
)
199 int use_64bit
= is_64bit_tdesc ();
206 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
210 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
221 unsigned int desc
[4];
223 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
224 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
227 /* Ensure we properly extend the value to 64-bits for x86_64. */
228 *base
= (void *) (uintptr_t) desc
[1];
233 /* Get the thread area address. This is used to recognize which
234 thread is which when tracing with the in-process agent library. We
235 don't read anything from the address, and treat it as opaque; it's
236 the address itself that we assume is unique per-thread. */
239 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
242 int use_64bit
= is_64bit_tdesc ();
247 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
249 *addr
= (CORE_ADDR
) (uintptr_t) base
;
258 struct lwp_info
*lwp
= find_lwp_pid (pid_to_ptid (lwpid
));
259 struct thread_info
*thr
= get_lwp_thread (lwp
);
260 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
261 unsigned int desc
[4];
263 const int reg_thread_area
= 3; /* bits to scale down register value. */
266 collect_register_by_name (regcache
, "gs", &gs
);
268 idx
= gs
>> reg_thread_area
;
270 if (ptrace (PTRACE_GET_THREAD_AREA
,
272 (void *) (long) idx
, (unsigned long) &desc
) < 0)
283 x86_cannot_store_register (int regno
)
286 if (is_64bit_tdesc ())
290 return regno
>= I386_NUM_REGS
;
294 x86_cannot_fetch_register (int regno
)
297 if (is_64bit_tdesc ())
301 return regno
>= I386_NUM_REGS
;
305 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
310 if (register_size (regcache
->tdesc
, 0) == 8)
312 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
313 if (x86_64_regmap
[i
] != -1)
314 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
316 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
319 int lwpid
= lwpid_of (current_thread
);
321 collect_register_by_name (regcache
, "fs_base", &base
);
322 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
324 collect_register_by_name (regcache
, "gs_base", &base
);
325 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
332 /* 32-bit inferior registers need to be zero-extended.
333 Callers would read uninitialized memory otherwise. */
334 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
337 for (i
= 0; i
< I386_NUM_REGS
; i
++)
338 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
340 collect_register_by_name (regcache
, "orig_eax",
341 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
345 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
350 if (register_size (regcache
->tdesc
, 0) == 8)
352 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
353 if (x86_64_regmap
[i
] != -1)
354 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
356 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
359 int lwpid
= lwpid_of (current_thread
);
361 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
362 supply_register_by_name (regcache
, "fs_base", &base
);
364 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
365 supply_register_by_name (regcache
, "gs_base", &base
);
372 for (i
= 0; i
< I386_NUM_REGS
; i
++)
373 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
375 supply_register_by_name (regcache
, "orig_eax",
376 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
380 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
383 i387_cache_to_fxsave (regcache
, buf
);
385 i387_cache_to_fsave (regcache
, buf
);
390 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
393 i387_fxsave_to_cache (regcache
, buf
);
395 i387_fsave_to_cache (regcache
, buf
);
402 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
404 i387_cache_to_fxsave (regcache
, buf
);
408 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
410 i387_fxsave_to_cache (regcache
, buf
);
416 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
418 i387_cache_to_xsave (regcache
, buf
);
422 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
424 i387_xsave_to_cache (regcache
, buf
);
427 /* ??? The non-biarch i386 case stores all the i387 regs twice.
428 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
429 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
430 doesn't work. IWBN to avoid the duplication in the case where it
431 does work. Maybe the arch_setup routine could check whether it works
432 and update the supported regsets accordingly. */
434 static struct regset_info x86_regsets
[] =
436 #ifdef HAVE_PTRACE_GETREGS
437 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
439 x86_fill_gregset
, x86_store_gregset
},
440 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
441 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
443 # ifdef HAVE_PTRACE_GETFPXREGS
444 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
446 x86_fill_fpxregset
, x86_store_fpxregset
},
449 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
451 x86_fill_fpregset
, x86_store_fpregset
},
452 #endif /* HAVE_PTRACE_GETREGS */
457 x86_get_pc (struct regcache
*regcache
)
459 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
465 collect_register_by_name (regcache
, "rip", &pc
);
466 return (CORE_ADDR
) pc
;
472 collect_register_by_name (regcache
, "eip", &pc
);
473 return (CORE_ADDR
) pc
;
478 x86_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
480 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
486 supply_register_by_name (regcache
, "rip", &newpc
);
492 supply_register_by_name (regcache
, "eip", &newpc
);
496 static const gdb_byte x86_breakpoint
[] = { 0xCC };
497 #define x86_breakpoint_len 1
500 x86_breakpoint_at (CORE_ADDR pc
)
504 (*the_target
->read_memory
) (pc
, &c
, 1);
511 /* Low-level function vector. */
512 struct x86_dr_low_type x86_dr_low
=
514 x86_linux_dr_set_control
,
515 x86_linux_dr_set_addr
,
516 x86_linux_dr_get_addr
,
517 x86_linux_dr_get_status
,
518 x86_linux_dr_get_control
,
522 /* Breakpoint/Watchpoint support. */
525 x86_supports_z_point_type (char z_type
)
531 case Z_PACKET_WRITE_WP
:
532 case Z_PACKET_ACCESS_WP
:
540 x86_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
541 int size
, struct raw_breakpoint
*bp
)
543 struct process_info
*proc
= current_process ();
547 case raw_bkpt_type_hw
:
548 case raw_bkpt_type_write_wp
:
549 case raw_bkpt_type_access_wp
:
551 enum target_hw_bp_type hw_type
552 = raw_bkpt_type_to_target_hw_bp_type (type
);
553 struct x86_debug_reg_state
*state
554 = &proc
->priv
->arch_private
->debug_reg_state
;
556 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
566 x86_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
567 int size
, struct raw_breakpoint
*bp
)
569 struct process_info
*proc
= current_process ();
573 case raw_bkpt_type_hw
:
574 case raw_bkpt_type_write_wp
:
575 case raw_bkpt_type_access_wp
:
577 enum target_hw_bp_type hw_type
578 = raw_bkpt_type_to_target_hw_bp_type (type
);
579 struct x86_debug_reg_state
*state
580 = &proc
->priv
->arch_private
->debug_reg_state
;
582 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
591 x86_stopped_by_watchpoint (void)
593 struct process_info
*proc
= current_process ();
594 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
598 x86_stopped_data_address (void)
600 struct process_info
*proc
= current_process ();
602 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
608 /* Called when a new process is created. */
610 static struct arch_process_info
*
611 x86_linux_new_process (void)
613 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
615 x86_low_init_dregs (&info
->debug_reg_state
);
620 /* Target routine for linux_new_fork. */
623 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
625 /* These are allocated by linux_add_process. */
626 gdb_assert (parent
->priv
!= NULL
627 && parent
->priv
->arch_private
!= NULL
);
628 gdb_assert (child
->priv
!= NULL
629 && child
->priv
->arch_private
!= NULL
);
631 /* Linux kernel before 2.6.33 commit
632 72f674d203cd230426437cdcf7dd6f681dad8b0d
633 will inherit hardware debug registers from parent
634 on fork/vfork/clone. Newer Linux kernels create such tasks with
635 zeroed debug registers.
637 GDB core assumes the child inherits the watchpoints/hw
638 breakpoints of the parent, and will remove them all from the
639 forked off process. Copy the debug registers mirrors into the
640 new process so that all breakpoints and watchpoints can be
641 removed together. The debug registers mirror will become zeroed
642 in the end before detaching the forked off process, thus making
643 this compatible with older Linux kernels too. */
645 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
648 /* See nat/x86-dregs.h. */
650 struct x86_debug_reg_state
*
651 x86_debug_reg_state (pid_t pid
)
653 struct process_info
*proc
= find_process_pid (pid
);
655 return &proc
->priv
->arch_private
->debug_reg_state
;
658 /* When GDBSERVER is built as a 64-bit application on linux, the
659 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
660 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
661 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
662 conversion in-place ourselves. */
664 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
665 layout of the inferiors' architecture. Returns true if any
666 conversion was done; false otherwise. If DIRECTION is 1, then copy
667 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
671 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
674 unsigned int machine
;
675 int tid
= lwpid_of (current_thread
);
676 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
678 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
679 if (!is_64bit_tdesc ())
680 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
682 /* No fixup for native x32 GDB. */
683 else if (!is_elf64
&& sizeof (void *) == 8)
684 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
693 /* Format of XSAVE extended state is:
697 sw_usable_bytes[464..511]
698 xstate_hdr_bytes[512..575]
703 Same memory layout will be used for the coredump NT_X86_XSTATE
704 representing the XSAVE extended state registers.
706 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
707 extended state mask, which is the same as the extended control register
708 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
709 together with the mask saved in the xstate_hdr_bytes to determine what
710 states the processor/OS supports and what state, used or initialized,
711 the process/thread is in. */
712 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
714 /* Does the current host support the GETFPXREGS request? The header
715 file may or may not define it, and even if it is defined, the
716 kernel will return EIO if it's running on a pre-SSE processor. */
717 int have_ptrace_getfpxregs
=
718 #ifdef HAVE_PTRACE_GETFPXREGS
725 /* Get Linux/x86 target description from running target. */
727 static const struct target_desc
*
728 x86_linux_read_description (void)
730 unsigned int machine
;
734 static uint64_t xcr0
;
735 struct regset_info
*regset
;
737 tid
= lwpid_of (current_thread
);
739 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
741 if (sizeof (void *) == 4)
744 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
746 else if (machine
== EM_X86_64
)
747 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
751 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
752 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
754 elf_fpxregset_t fpxregs
;
756 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
758 have_ptrace_getfpxregs
= 0;
759 have_ptrace_getregset
= 0;
760 return tdesc_i386_mmx_linux
;
763 have_ptrace_getfpxregs
= 1;
769 x86_xcr0
= X86_XSTATE_SSE_MASK
;
773 if (machine
== EM_X86_64
)
774 return tdesc_amd64_linux_no_xml
;
777 return tdesc_i386_linux_no_xml
;
780 if (have_ptrace_getregset
== -1)
782 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
785 iov
.iov_base
= xstateregs
;
786 iov
.iov_len
= sizeof (xstateregs
);
788 /* Check if PTRACE_GETREGSET works. */
789 if (ptrace (PTRACE_GETREGSET
, tid
,
790 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
791 have_ptrace_getregset
= 0;
794 have_ptrace_getregset
= 1;
796 /* Get XCR0 from XSAVE extended state. */
797 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
798 / sizeof (uint64_t))];
800 /* Use PTRACE_GETREGSET if it is available. */
801 for (regset
= x86_regsets
;
802 regset
->fill_function
!= NULL
; regset
++)
803 if (regset
->get_request
== PTRACE_GETREGSET
)
804 regset
->size
= X86_XSTATE_SIZE (xcr0
);
805 else if (regset
->type
!= GENERAL_REGS
)
810 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
811 xcr0_features
= (have_ptrace_getregset
812 && (xcr0
& X86_XSTATE_ALL_MASK
));
817 if (machine
== EM_X86_64
)
824 switch (xcr0
& X86_XSTATE_ALL_MASK
)
826 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
:
827 return tdesc_amd64_avx_mpx_avx512_pku_linux
;
829 case X86_XSTATE_AVX_AVX512_MASK
:
830 return tdesc_amd64_avx_avx512_linux
;
832 case X86_XSTATE_AVX_MPX_MASK
:
833 return tdesc_amd64_avx_mpx_linux
;
835 case X86_XSTATE_MPX_MASK
:
836 return tdesc_amd64_mpx_linux
;
838 case X86_XSTATE_AVX_MASK
:
839 return tdesc_amd64_avx_linux
;
842 return tdesc_amd64_linux
;
846 return tdesc_amd64_linux
;
852 switch (xcr0
& X86_XSTATE_ALL_MASK
)
854 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
:
855 /* No x32 MPX and PKU, fall back to avx_avx512. */
856 return tdesc_x32_avx_avx512_linux
;
858 case X86_XSTATE_AVX_AVX512_MASK
:
859 return tdesc_x32_avx_avx512_linux
;
861 case X86_XSTATE_MPX_MASK
: /* No MPX on x32. */
862 case X86_XSTATE_AVX_MASK
:
863 return tdesc_x32_avx_linux
;
866 return tdesc_x32_linux
;
870 return tdesc_x32_linux
;
878 switch (xcr0
& X86_XSTATE_ALL_MASK
)
880 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
:
881 return tdesc_i386_avx_mpx_avx512_pku_linux
;
883 case (X86_XSTATE_AVX_AVX512_MASK
):
884 return tdesc_i386_avx_avx512_linux
;
886 case (X86_XSTATE_MPX_MASK
):
887 return tdesc_i386_mpx_linux
;
889 case (X86_XSTATE_AVX_MPX_MASK
):
890 return tdesc_i386_avx_mpx_linux
;
892 case (X86_XSTATE_AVX_MASK
):
893 return tdesc_i386_avx_linux
;
896 return tdesc_i386_linux
;
900 return tdesc_i386_linux
;
903 gdb_assert_not_reached ("failed to return tdesc");
906 /* Callback for find_inferior. Stops iteration when a thread with a
907 given PID is found. */
910 same_process_callback (struct inferior_list_entry
*entry
, void *data
)
912 int pid
= *(int *) data
;
914 return (ptid_get_pid (entry
->id
) == pid
);
917 /* Callback for for_each_inferior. Calls the arch_setup routine for
921 x86_arch_setup_process_callback (struct inferior_list_entry
*entry
)
923 int pid
= ptid_get_pid (entry
->id
);
925 /* Look up any thread of this processes. */
927 = (struct thread_info
*) find_inferior (&all_threads
,
928 same_process_callback
, &pid
);
930 the_low_target
.arch_setup ();
933 /* Update all the target description of all processes; a new GDB
934 connected, and it may or not support xml target descriptions. */
937 x86_linux_update_xmltarget (void)
939 struct thread_info
*saved_thread
= current_thread
;
941 /* Before changing the register cache's internal layout, flush the
942 contents of the current valid caches back to the threads, and
943 release the current regcache objects. */
946 for_each_inferior (&all_processes
, x86_arch_setup_process_callback
);
948 current_thread
= saved_thread
;
951 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
955 x86_linux_process_qsupported (char **features
, int count
)
959 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
960 with "i386" in qSupported query, it supports x86 XML target
963 for (i
= 0; i
< count
; i
++)
965 const char *feature
= features
[i
];
967 if (startswith (feature
, "xmlRegisters="))
969 char *copy
= xstrdup (feature
+ 13);
972 for (p
= strtok (copy
, ","); p
!= NULL
; p
= strtok (NULL
, ","))
974 if (strcmp (p
, "i386") == 0)
984 x86_linux_update_xmltarget ();
987 /* Common for x86/x86-64. */
989 static struct regsets_info x86_regsets_info
=
991 x86_regsets
, /* regsets */
993 NULL
, /* disabled_regsets */
997 static struct regs_info amd64_linux_regs_info
=
999 NULL
, /* regset_bitmap */
1000 NULL
, /* usrregs_info */
1004 static struct usrregs_info i386_linux_usrregs_info
=
1010 static struct regs_info i386_linux_regs_info
=
1012 NULL
, /* regset_bitmap */
1013 &i386_linux_usrregs_info
,
1017 const struct regs_info
*
1018 x86_linux_regs_info (void)
1021 if (is_64bit_tdesc ())
1022 return &amd64_linux_regs_info
;
1025 return &i386_linux_regs_info
;
1028 /* Initialize the target description for the architecture of the
1032 x86_arch_setup (void)
1034 current_process ()->tdesc
= x86_linux_read_description ();
1037 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1038 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1041 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1043 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1049 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1050 *sysno
= (int) l_sysno
;
1053 collect_register_by_name (regcache
, "orig_eax", sysno
);
1057 x86_supports_tracepoints (void)
1063 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1065 write_inferior_memory (*to
, buf
, len
);
1070 push_opcode (unsigned char *buf
, const char *op
)
1072 unsigned char *buf_org
= buf
;
1077 unsigned long ul
= strtoul (op
, &endptr
, 16);
1086 return buf
- buf_org
;
1091 /* Build a jump pad that saves registers and calls a collection
1092 function. Writes a jump instruction to the jump pad to
1093 JJUMPAD_INSN. The caller is responsible to write it in at the
1094 tracepoint address. */
1097 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1098 CORE_ADDR collector
,
1101 CORE_ADDR
*jump_entry
,
1102 CORE_ADDR
*trampoline
,
1103 ULONGEST
*trampoline_size
,
1104 unsigned char *jjump_pad_insn
,
1105 ULONGEST
*jjump_pad_insn_size
,
1106 CORE_ADDR
*adjusted_insn_addr
,
1107 CORE_ADDR
*adjusted_insn_addr_end
,
1110 unsigned char buf
[40];
1114 CORE_ADDR buildaddr
= *jump_entry
;
1116 /* Build the jump pad. */
1118 /* First, do tracepoint data collection. Save registers. */
1120 /* Need to ensure stack pointer saved first. */
1121 buf
[i
++] = 0x54; /* push %rsp */
1122 buf
[i
++] = 0x55; /* push %rbp */
1123 buf
[i
++] = 0x57; /* push %rdi */
1124 buf
[i
++] = 0x56; /* push %rsi */
1125 buf
[i
++] = 0x52; /* push %rdx */
1126 buf
[i
++] = 0x51; /* push %rcx */
1127 buf
[i
++] = 0x53; /* push %rbx */
1128 buf
[i
++] = 0x50; /* push %rax */
1129 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1130 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1131 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1132 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1133 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1134 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1135 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1136 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1137 buf
[i
++] = 0x9c; /* pushfq */
1138 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1140 memcpy (buf
+ i
, &tpaddr
, 8);
1142 buf
[i
++] = 0x57; /* push %rdi */
1143 append_insns (&buildaddr
, i
, buf
);
1145 /* Stack space for the collecting_t object. */
1147 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1148 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1149 memcpy (buf
+ i
, &tpoint
, 8);
1151 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1152 i
+= push_opcode (&buf
[i
],
1153 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1154 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1155 append_insns (&buildaddr
, i
, buf
);
1159 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1160 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1162 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1163 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1164 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1165 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1166 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1167 append_insns (&buildaddr
, i
, buf
);
1169 /* Set up the gdb_collect call. */
1170 /* At this point, (stack pointer + 0x18) is the base of our saved
1174 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1175 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1177 /* tpoint address may be 64-bit wide. */
1178 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1179 memcpy (buf
+ i
, &tpoint
, 8);
1181 append_insns (&buildaddr
, i
, buf
);
1183 /* The collector function being in the shared library, may be
1184 >31-bits away off the jump pad. */
1186 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1187 memcpy (buf
+ i
, &collector
, 8);
1189 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1190 append_insns (&buildaddr
, i
, buf
);
1192 /* Clear the spin-lock. */
1194 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1195 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1196 memcpy (buf
+ i
, &lockaddr
, 8);
1198 append_insns (&buildaddr
, i
, buf
);
1200 /* Remove stack that had been used for the collect_t object. */
1202 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1203 append_insns (&buildaddr
, i
, buf
);
1205 /* Restore register state. */
1207 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1211 buf
[i
++] = 0x9d; /* popfq */
1212 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1213 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1214 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1215 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1216 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1217 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1218 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1219 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1220 buf
[i
++] = 0x58; /* pop %rax */
1221 buf
[i
++] = 0x5b; /* pop %rbx */
1222 buf
[i
++] = 0x59; /* pop %rcx */
1223 buf
[i
++] = 0x5a; /* pop %rdx */
1224 buf
[i
++] = 0x5e; /* pop %rsi */
1225 buf
[i
++] = 0x5f; /* pop %rdi */
1226 buf
[i
++] = 0x5d; /* pop %rbp */
1227 buf
[i
++] = 0x5c; /* pop %rsp */
1228 append_insns (&buildaddr
, i
, buf
);
1230 /* Now, adjust the original instruction to execute in the jump
1232 *adjusted_insn_addr
= buildaddr
;
1233 relocate_instruction (&buildaddr
, tpaddr
);
1234 *adjusted_insn_addr_end
= buildaddr
;
1236 /* Finally, write a jump back to the program. */
1238 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1239 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1242 "E.Jump back from jump pad too far from tracepoint "
1243 "(offset 0x%" PRIx64
" > int32).", loffset
);
1247 offset
= (int) loffset
;
1248 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1249 memcpy (buf
+ 1, &offset
, 4);
1250 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1252 /* The jump pad is now built. Wire in a jump to our jump pad. This
1253 is always done last (by our caller actually), so that we can
1254 install fast tracepoints with threads running. This relies on
1255 the agent's atomic write support. */
1256 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1257 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1260 "E.Jump pad too far from tracepoint "
1261 "(offset 0x%" PRIx64
" > int32).", loffset
);
1265 offset
= (int) loffset
;
1267 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1268 memcpy (buf
+ 1, &offset
, 4);
1269 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1270 *jjump_pad_insn_size
= sizeof (jump_insn
);
1272 /* Return the end address of our pad. */
1273 *jump_entry
= buildaddr
;
1278 #endif /* __x86_64__ */
1280 /* Build a jump pad that saves registers and calls a collection
1281 function. Writes a jump instruction to the jump pad to
1282 JJUMPAD_INSN. The caller is responsible to write it in at the
1283 tracepoint address. */
1286 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1287 CORE_ADDR collector
,
1290 CORE_ADDR
*jump_entry
,
1291 CORE_ADDR
*trampoline
,
1292 ULONGEST
*trampoline_size
,
1293 unsigned char *jjump_pad_insn
,
1294 ULONGEST
*jjump_pad_insn_size
,
1295 CORE_ADDR
*adjusted_insn_addr
,
1296 CORE_ADDR
*adjusted_insn_addr_end
,
1299 unsigned char buf
[0x100];
1301 CORE_ADDR buildaddr
= *jump_entry
;
1303 /* Build the jump pad. */
1305 /* First, do tracepoint data collection. Save registers. */
1307 buf
[i
++] = 0x60; /* pushad */
1308 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1309 *((int *)(buf
+ i
)) = (int) tpaddr
;
1311 buf
[i
++] = 0x9c; /* pushf */
1312 buf
[i
++] = 0x1e; /* push %ds */
1313 buf
[i
++] = 0x06; /* push %es */
1314 buf
[i
++] = 0x0f; /* push %fs */
1316 buf
[i
++] = 0x0f; /* push %gs */
1318 buf
[i
++] = 0x16; /* push %ss */
1319 buf
[i
++] = 0x0e; /* push %cs */
1320 append_insns (&buildaddr
, i
, buf
);
1322 /* Stack space for the collecting_t object. */
1324 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1326 /* Build the object. */
1327 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1328 memcpy (buf
+ i
, &tpoint
, 4);
1330 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1332 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1333 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1334 append_insns (&buildaddr
, i
, buf
);
1336 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1337 If we cared for it, this could be using xchg alternatively. */
1340 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1341 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1343 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1345 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1346 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1347 append_insns (&buildaddr
, i
, buf
);
1350 /* Set up arguments to the gdb_collect call. */
1352 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1353 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1354 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1355 append_insns (&buildaddr
, i
, buf
);
1358 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1359 append_insns (&buildaddr
, i
, buf
);
1362 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1363 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1365 append_insns (&buildaddr
, i
, buf
);
1367 buf
[0] = 0xe8; /* call <reladdr> */
1368 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1369 memcpy (buf
+ 1, &offset
, 4);
1370 append_insns (&buildaddr
, 5, buf
);
1371 /* Clean up after the call. */
1372 buf
[0] = 0x83; /* add $0x8,%esp */
1375 append_insns (&buildaddr
, 3, buf
);
1378 /* Clear the spin-lock. This would need the LOCK prefix on older
1381 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1382 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1383 memcpy (buf
+ i
, &lockaddr
, 4);
1385 append_insns (&buildaddr
, i
, buf
);
1388 /* Remove stack that had been used for the collect_t object. */
1390 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1391 append_insns (&buildaddr
, i
, buf
);
1394 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1397 buf
[i
++] = 0x17; /* pop %ss */
1398 buf
[i
++] = 0x0f; /* pop %gs */
1400 buf
[i
++] = 0x0f; /* pop %fs */
1402 buf
[i
++] = 0x07; /* pop %es */
1403 buf
[i
++] = 0x1f; /* pop %ds */
1404 buf
[i
++] = 0x9d; /* popf */
1405 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1408 buf
[i
++] = 0x61; /* popad */
1409 append_insns (&buildaddr
, i
, buf
);
1411 /* Now, adjust the original instruction to execute in the jump
1413 *adjusted_insn_addr
= buildaddr
;
1414 relocate_instruction (&buildaddr
, tpaddr
);
1415 *adjusted_insn_addr_end
= buildaddr
;
1417 /* Write the jump back to the program. */
1418 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1419 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1420 memcpy (buf
+ 1, &offset
, 4);
1421 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1423 /* The jump pad is now built. Wire in a jump to our jump pad. This
1424 is always done last (by our caller actually), so that we can
1425 install fast tracepoints with threads running. This relies on
1426 the agent's atomic write support. */
1429 /* Create a trampoline. */
1430 *trampoline_size
= sizeof (jump_insn
);
1431 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1433 /* No trampoline space available. */
1435 "E.Cannot allocate trampoline space needed for fast "
1436 "tracepoints on 4-byte instructions.");
1440 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1441 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1442 memcpy (buf
+ 1, &offset
, 4);
1443 write_inferior_memory (*trampoline
, buf
, sizeof (jump_insn
));
1445 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1446 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1447 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1448 memcpy (buf
+ 2, &offset
, 2);
1449 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1450 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1454 /* Else use a 32-bit relative jump instruction. */
1455 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1456 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1457 memcpy (buf
+ 1, &offset
, 4);
1458 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1459 *jjump_pad_insn_size
= sizeof (jump_insn
);
1462 /* Return the end address of our pad. */
1463 *jump_entry
= buildaddr
;
1469 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1470 CORE_ADDR collector
,
1473 CORE_ADDR
*jump_entry
,
1474 CORE_ADDR
*trampoline
,
1475 ULONGEST
*trampoline_size
,
1476 unsigned char *jjump_pad_insn
,
1477 ULONGEST
*jjump_pad_insn_size
,
1478 CORE_ADDR
*adjusted_insn_addr
,
1479 CORE_ADDR
*adjusted_insn_addr_end
,
1483 if (is_64bit_tdesc ())
1484 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1485 collector
, lockaddr
,
1486 orig_size
, jump_entry
,
1487 trampoline
, trampoline_size
,
1489 jjump_pad_insn_size
,
1491 adjusted_insn_addr_end
,
1495 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1496 collector
, lockaddr
,
1497 orig_size
, jump_entry
,
1498 trampoline
, trampoline_size
,
1500 jjump_pad_insn_size
,
1502 adjusted_insn_addr_end
,
1506 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1510 x86_get_min_fast_tracepoint_insn_len (void)
1512 static int warned_about_fast_tracepoints
= 0;
1515 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1516 used for fast tracepoints. */
1517 if (is_64bit_tdesc ())
1521 if (agent_loaded_p ())
1523 char errbuf
[IPA_BUFSIZ
];
1527 /* On x86, if trampolines are available, then 4-byte jump instructions
1528 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1529 with a 4-byte offset are used instead. */
1530 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1534 /* GDB has no channel to explain to user why a shorter fast
1535 tracepoint is not possible, but at least make GDBserver
1536 mention that something has gone awry. */
1537 if (!warned_about_fast_tracepoints
)
1539 warning ("4-byte fast tracepoints not available; %s\n", errbuf
);
1540 warned_about_fast_tracepoints
= 1;
1547 /* Indicate that the minimum length is currently unknown since the IPA
1548 has not loaded yet. */
1554 add_insns (unsigned char *start
, int len
)
1556 CORE_ADDR buildaddr
= current_insn_ptr
;
1559 debug_printf ("Adding %d bytes of insn at %s\n",
1560 len
, paddress (buildaddr
));
1562 append_insns (&buildaddr
, len
, start
);
1563 current_insn_ptr
= buildaddr
;
1566 /* Our general strategy for emitting code is to avoid specifying raw
1567 bytes whenever possible, and instead copy a block of inline asm
1568 that is embedded in the function. This is a little messy, because
1569 we need to keep the compiler from discarding what looks like dead
1570 code, plus suppress various warnings. */
1572 #define EMIT_ASM(NAME, INSNS) \
1575 extern unsigned char start_ ## NAME, end_ ## NAME; \
1576 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1577 __asm__ ("jmp end_" #NAME "\n" \
1578 "\t" "start_" #NAME ":" \
1580 "\t" "end_" #NAME ":"); \
1585 #define EMIT_ASM32(NAME,INSNS) \
1588 extern unsigned char start_ ## NAME, end_ ## NAME; \
1589 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1590 __asm__ (".code32\n" \
1591 "\t" "jmp end_" #NAME "\n" \
1592 "\t" "start_" #NAME ":\n" \
1594 "\t" "end_" #NAME ":\n" \
1600 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1607 amd64_emit_prologue (void)
1609 EMIT_ASM (amd64_prologue
,
1611 "movq %rsp,%rbp\n\t"
1612 "sub $0x20,%rsp\n\t"
1613 "movq %rdi,-8(%rbp)\n\t"
1614 "movq %rsi,-16(%rbp)");
1619 amd64_emit_epilogue (void)
1621 EMIT_ASM (amd64_epilogue
,
1622 "movq -16(%rbp),%rdi\n\t"
1623 "movq %rax,(%rdi)\n\t"
1630 amd64_emit_add (void)
1632 EMIT_ASM (amd64_add
,
1633 "add (%rsp),%rax\n\t"
1634 "lea 0x8(%rsp),%rsp");
1638 amd64_emit_sub (void)
1640 EMIT_ASM (amd64_sub
,
1641 "sub %rax,(%rsp)\n\t"
1646 amd64_emit_mul (void)
1652 amd64_emit_lsh (void)
1658 amd64_emit_rsh_signed (void)
1664 amd64_emit_rsh_unsigned (void)
1670 amd64_emit_ext (int arg
)
1675 EMIT_ASM (amd64_ext_8
,
1681 EMIT_ASM (amd64_ext_16
,
1686 EMIT_ASM (amd64_ext_32
,
1695 amd64_emit_log_not (void)
1697 EMIT_ASM (amd64_log_not
,
1698 "test %rax,%rax\n\t"
1704 amd64_emit_bit_and (void)
1706 EMIT_ASM (amd64_and
,
1707 "and (%rsp),%rax\n\t"
1708 "lea 0x8(%rsp),%rsp");
1712 amd64_emit_bit_or (void)
1715 "or (%rsp),%rax\n\t"
1716 "lea 0x8(%rsp),%rsp");
1720 amd64_emit_bit_xor (void)
1722 EMIT_ASM (amd64_xor
,
1723 "xor (%rsp),%rax\n\t"
1724 "lea 0x8(%rsp),%rsp");
1728 amd64_emit_bit_not (void)
1730 EMIT_ASM (amd64_bit_not
,
1731 "xorq $0xffffffffffffffff,%rax");
1735 amd64_emit_equal (void)
1737 EMIT_ASM (amd64_equal
,
1738 "cmp %rax,(%rsp)\n\t"
1739 "je .Lamd64_equal_true\n\t"
1741 "jmp .Lamd64_equal_end\n\t"
1742 ".Lamd64_equal_true:\n\t"
1744 ".Lamd64_equal_end:\n\t"
1745 "lea 0x8(%rsp),%rsp");
1749 amd64_emit_less_signed (void)
1751 EMIT_ASM (amd64_less_signed
,
1752 "cmp %rax,(%rsp)\n\t"
1753 "jl .Lamd64_less_signed_true\n\t"
1755 "jmp .Lamd64_less_signed_end\n\t"
1756 ".Lamd64_less_signed_true:\n\t"
1758 ".Lamd64_less_signed_end:\n\t"
1759 "lea 0x8(%rsp),%rsp");
1763 amd64_emit_less_unsigned (void)
1765 EMIT_ASM (amd64_less_unsigned
,
1766 "cmp %rax,(%rsp)\n\t"
1767 "jb .Lamd64_less_unsigned_true\n\t"
1769 "jmp .Lamd64_less_unsigned_end\n\t"
1770 ".Lamd64_less_unsigned_true:\n\t"
1772 ".Lamd64_less_unsigned_end:\n\t"
1773 "lea 0x8(%rsp),%rsp");
1777 amd64_emit_ref (int size
)
1782 EMIT_ASM (amd64_ref1
,
1786 EMIT_ASM (amd64_ref2
,
1790 EMIT_ASM (amd64_ref4
,
1791 "movl (%rax),%eax");
1794 EMIT_ASM (amd64_ref8
,
1795 "movq (%rax),%rax");
1801 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1803 EMIT_ASM (amd64_if_goto
,
1807 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1815 amd64_emit_goto (int *offset_p
, int *size_p
)
1817 EMIT_ASM (amd64_goto
,
1818 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1826 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1828 int diff
= (to
- (from
+ size
));
1829 unsigned char buf
[sizeof (int)];
1837 memcpy (buf
, &diff
, sizeof (int));
1838 write_inferior_memory (from
, buf
, sizeof (int));
1842 amd64_emit_const (LONGEST num
)
1844 unsigned char buf
[16];
1846 CORE_ADDR buildaddr
= current_insn_ptr
;
1849 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1850 memcpy (&buf
[i
], &num
, sizeof (num
));
1852 append_insns (&buildaddr
, i
, buf
);
1853 current_insn_ptr
= buildaddr
;
1857 amd64_emit_call (CORE_ADDR fn
)
1859 unsigned char buf
[16];
1861 CORE_ADDR buildaddr
;
1864 /* The destination function being in the shared library, may be
1865 >31-bits away off the compiled code pad. */
1867 buildaddr
= current_insn_ptr
;
1869 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1873 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1875 /* Offset is too large for a call. Use callq, but that requires
1876 a register, so avoid it if possible. Use r10, since it is
1877 call-clobbered, we don't have to push/pop it. */
1878 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1880 memcpy (buf
+ i
, &fn
, 8);
1882 buf
[i
++] = 0xff; /* callq *%r10 */
1887 int offset32
= offset64
; /* we know we can't overflow here. */
1889 buf
[i
++] = 0xe8; /* call <reladdr> */
1890 memcpy (buf
+ i
, &offset32
, 4);
1894 append_insns (&buildaddr
, i
, buf
);
1895 current_insn_ptr
= buildaddr
;
1899 amd64_emit_reg (int reg
)
1901 unsigned char buf
[16];
1903 CORE_ADDR buildaddr
;
1905 /* Assume raw_regs is still in %rdi. */
1906 buildaddr
= current_insn_ptr
;
1908 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1909 memcpy (&buf
[i
], ®
, sizeof (reg
));
1911 append_insns (&buildaddr
, i
, buf
);
1912 current_insn_ptr
= buildaddr
;
1913 amd64_emit_call (get_raw_reg_func_addr ());
1917 amd64_emit_pop (void)
1919 EMIT_ASM (amd64_pop
,
1924 amd64_emit_stack_flush (void)
1926 EMIT_ASM (amd64_stack_flush
,
1931 amd64_emit_zero_ext (int arg
)
1936 EMIT_ASM (amd64_zero_ext_8
,
1940 EMIT_ASM (amd64_zero_ext_16
,
1941 "and $0xffff,%rax");
1944 EMIT_ASM (amd64_zero_ext_32
,
1945 "mov $0xffffffff,%rcx\n\t"
1954 amd64_emit_swap (void)
1956 EMIT_ASM (amd64_swap
,
1963 amd64_emit_stack_adjust (int n
)
1965 unsigned char buf
[16];
1967 CORE_ADDR buildaddr
= current_insn_ptr
;
1970 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1974 /* This only handles adjustments up to 16, but we don't expect any more. */
1976 append_insns (&buildaddr
, i
, buf
);
1977 current_insn_ptr
= buildaddr
;
1980 /* FN's prototype is `LONGEST(*fn)(int)'. */
1983 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1985 unsigned char buf
[16];
1987 CORE_ADDR buildaddr
;
1989 buildaddr
= current_insn_ptr
;
1991 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1992 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1994 append_insns (&buildaddr
, i
, buf
);
1995 current_insn_ptr
= buildaddr
;
1996 amd64_emit_call (fn
);
1999 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2002 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2004 unsigned char buf
[16];
2006 CORE_ADDR buildaddr
;
2008 buildaddr
= current_insn_ptr
;
2010 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2011 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2013 append_insns (&buildaddr
, i
, buf
);
2014 current_insn_ptr
= buildaddr
;
2015 EMIT_ASM (amd64_void_call_2_a
,
2016 /* Save away a copy of the stack top. */
2018 /* Also pass top as the second argument. */
2020 amd64_emit_call (fn
);
2021 EMIT_ASM (amd64_void_call_2_b
,
2022 /* Restore the stack top, %rax may have been trashed. */
2027 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2030 "cmp %rax,(%rsp)\n\t"
2031 "jne .Lamd64_eq_fallthru\n\t"
2032 "lea 0x8(%rsp),%rsp\n\t"
2034 /* jmp, but don't trust the assembler to choose the right jump */
2035 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2036 ".Lamd64_eq_fallthru:\n\t"
2037 "lea 0x8(%rsp),%rsp\n\t"
2047 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2050 "cmp %rax,(%rsp)\n\t"
2051 "je .Lamd64_ne_fallthru\n\t"
2052 "lea 0x8(%rsp),%rsp\n\t"
2054 /* jmp, but don't trust the assembler to choose the right jump */
2055 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2056 ".Lamd64_ne_fallthru:\n\t"
2057 "lea 0x8(%rsp),%rsp\n\t"
2067 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2070 "cmp %rax,(%rsp)\n\t"
2071 "jnl .Lamd64_lt_fallthru\n\t"
2072 "lea 0x8(%rsp),%rsp\n\t"
2074 /* jmp, but don't trust the assembler to choose the right jump */
2075 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2076 ".Lamd64_lt_fallthru:\n\t"
2077 "lea 0x8(%rsp),%rsp\n\t"
2087 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2090 "cmp %rax,(%rsp)\n\t"
2091 "jnle .Lamd64_le_fallthru\n\t"
2092 "lea 0x8(%rsp),%rsp\n\t"
2094 /* jmp, but don't trust the assembler to choose the right jump */
2095 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2096 ".Lamd64_le_fallthru:\n\t"
2097 "lea 0x8(%rsp),%rsp\n\t"
2107 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2110 "cmp %rax,(%rsp)\n\t"
2111 "jng .Lamd64_gt_fallthru\n\t"
2112 "lea 0x8(%rsp),%rsp\n\t"
2114 /* jmp, but don't trust the assembler to choose the right jump */
2115 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2116 ".Lamd64_gt_fallthru:\n\t"
2117 "lea 0x8(%rsp),%rsp\n\t"
2127 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2130 "cmp %rax,(%rsp)\n\t"
2131 "jnge .Lamd64_ge_fallthru\n\t"
2132 ".Lamd64_ge_jump:\n\t"
2133 "lea 0x8(%rsp),%rsp\n\t"
2135 /* jmp, but don't trust the assembler to choose the right jump */
2136 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2137 ".Lamd64_ge_fallthru:\n\t"
2138 "lea 0x8(%rsp),%rsp\n\t"
2147 struct emit_ops amd64_emit_ops
=
2149 amd64_emit_prologue
,
2150 amd64_emit_epilogue
,
2155 amd64_emit_rsh_signed
,
2156 amd64_emit_rsh_unsigned
,
2164 amd64_emit_less_signed
,
2165 amd64_emit_less_unsigned
,
2169 amd64_write_goto_address
,
2174 amd64_emit_stack_flush
,
2175 amd64_emit_zero_ext
,
2177 amd64_emit_stack_adjust
,
2178 amd64_emit_int_call_1
,
2179 amd64_emit_void_call_2
,
2188 #endif /* __x86_64__ */
2191 i386_emit_prologue (void)
2193 EMIT_ASM32 (i386_prologue
,
2197 /* At this point, the raw regs base address is at 8(%ebp), and the
2198 value pointer is at 12(%ebp). */
2202 i386_emit_epilogue (void)
2204 EMIT_ASM32 (i386_epilogue
,
2205 "mov 12(%ebp),%ecx\n\t"
2206 "mov %eax,(%ecx)\n\t"
2207 "mov %ebx,0x4(%ecx)\n\t"
2215 i386_emit_add (void)
2217 EMIT_ASM32 (i386_add
,
2218 "add (%esp),%eax\n\t"
2219 "adc 0x4(%esp),%ebx\n\t"
2220 "lea 0x8(%esp),%esp");
2224 i386_emit_sub (void)
2226 EMIT_ASM32 (i386_sub
,
2227 "subl %eax,(%esp)\n\t"
2228 "sbbl %ebx,4(%esp)\n\t"
2234 i386_emit_mul (void)
2240 i386_emit_lsh (void)
2246 i386_emit_rsh_signed (void)
2252 i386_emit_rsh_unsigned (void)
2258 i386_emit_ext (int arg
)
2263 EMIT_ASM32 (i386_ext_8
,
2266 "movl %eax,%ebx\n\t"
2270 EMIT_ASM32 (i386_ext_16
,
2272 "movl %eax,%ebx\n\t"
2276 EMIT_ASM32 (i386_ext_32
,
2277 "movl %eax,%ebx\n\t"
2286 i386_emit_log_not (void)
2288 EMIT_ASM32 (i386_log_not
,
2290 "test %eax,%eax\n\t"
2297 i386_emit_bit_and (void)
2299 EMIT_ASM32 (i386_and
,
2300 "and (%esp),%eax\n\t"
2301 "and 0x4(%esp),%ebx\n\t"
2302 "lea 0x8(%esp),%esp");
2306 i386_emit_bit_or (void)
2308 EMIT_ASM32 (i386_or
,
2309 "or (%esp),%eax\n\t"
2310 "or 0x4(%esp),%ebx\n\t"
2311 "lea 0x8(%esp),%esp");
2315 i386_emit_bit_xor (void)
2317 EMIT_ASM32 (i386_xor
,
2318 "xor (%esp),%eax\n\t"
2319 "xor 0x4(%esp),%ebx\n\t"
2320 "lea 0x8(%esp),%esp");
2324 i386_emit_bit_not (void)
2326 EMIT_ASM32 (i386_bit_not
,
2327 "xor $0xffffffff,%eax\n\t"
2328 "xor $0xffffffff,%ebx\n\t");
2332 i386_emit_equal (void)
2334 EMIT_ASM32 (i386_equal
,
2335 "cmpl %ebx,4(%esp)\n\t"
2336 "jne .Li386_equal_false\n\t"
2337 "cmpl %eax,(%esp)\n\t"
2338 "je .Li386_equal_true\n\t"
2339 ".Li386_equal_false:\n\t"
2341 "jmp .Li386_equal_end\n\t"
2342 ".Li386_equal_true:\n\t"
2344 ".Li386_equal_end:\n\t"
2346 "lea 0x8(%esp),%esp");
2350 i386_emit_less_signed (void)
2352 EMIT_ASM32 (i386_less_signed
,
2353 "cmpl %ebx,4(%esp)\n\t"
2354 "jl .Li386_less_signed_true\n\t"
2355 "jne .Li386_less_signed_false\n\t"
2356 "cmpl %eax,(%esp)\n\t"
2357 "jl .Li386_less_signed_true\n\t"
2358 ".Li386_less_signed_false:\n\t"
2360 "jmp .Li386_less_signed_end\n\t"
2361 ".Li386_less_signed_true:\n\t"
2363 ".Li386_less_signed_end:\n\t"
2365 "lea 0x8(%esp),%esp");
2369 i386_emit_less_unsigned (void)
2371 EMIT_ASM32 (i386_less_unsigned
,
2372 "cmpl %ebx,4(%esp)\n\t"
2373 "jb .Li386_less_unsigned_true\n\t"
2374 "jne .Li386_less_unsigned_false\n\t"
2375 "cmpl %eax,(%esp)\n\t"
2376 "jb .Li386_less_unsigned_true\n\t"
2377 ".Li386_less_unsigned_false:\n\t"
2379 "jmp .Li386_less_unsigned_end\n\t"
2380 ".Li386_less_unsigned_true:\n\t"
2382 ".Li386_less_unsigned_end:\n\t"
2384 "lea 0x8(%esp),%esp");
2388 i386_emit_ref (int size
)
2393 EMIT_ASM32 (i386_ref1
,
2397 EMIT_ASM32 (i386_ref2
,
2401 EMIT_ASM32 (i386_ref4
,
2402 "movl (%eax),%eax");
2405 EMIT_ASM32 (i386_ref8
,
2406 "movl 4(%eax),%ebx\n\t"
2407 "movl (%eax),%eax");
2413 i386_emit_if_goto (int *offset_p
, int *size_p
)
2415 EMIT_ASM32 (i386_if_goto
,
2421 /* Don't trust the assembler to choose the right jump */
2422 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2425 *offset_p
= 11; /* be sure that this matches the sequence above */
2431 i386_emit_goto (int *offset_p
, int *size_p
)
2433 EMIT_ASM32 (i386_goto
,
2434 /* Don't trust the assembler to choose the right jump */
2435 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2443 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2445 int diff
= (to
- (from
+ size
));
2446 unsigned char buf
[sizeof (int)];
2448 /* We're only doing 4-byte sizes at the moment. */
2455 memcpy (buf
, &diff
, sizeof (int));
2456 write_inferior_memory (from
, buf
, sizeof (int));
2460 i386_emit_const (LONGEST num
)
2462 unsigned char buf
[16];
2464 CORE_ADDR buildaddr
= current_insn_ptr
;
2467 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2468 lo
= num
& 0xffffffff;
2469 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2471 hi
= ((num
>> 32) & 0xffffffff);
2474 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2475 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2480 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2482 append_insns (&buildaddr
, i
, buf
);
2483 current_insn_ptr
= buildaddr
;
2487 i386_emit_call (CORE_ADDR fn
)
2489 unsigned char buf
[16];
2491 CORE_ADDR buildaddr
;
2493 buildaddr
= current_insn_ptr
;
2495 buf
[i
++] = 0xe8; /* call <reladdr> */
2496 offset
= ((int) fn
) - (buildaddr
+ 5);
2497 memcpy (buf
+ 1, &offset
, 4);
2498 append_insns (&buildaddr
, 5, buf
);
2499 current_insn_ptr
= buildaddr
;
2503 i386_emit_reg (int reg
)
2505 unsigned char buf
[16];
2507 CORE_ADDR buildaddr
;
2509 EMIT_ASM32 (i386_reg_a
,
2511 buildaddr
= current_insn_ptr
;
2513 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2514 memcpy (&buf
[i
], ®
, sizeof (reg
));
2516 append_insns (&buildaddr
, i
, buf
);
2517 current_insn_ptr
= buildaddr
;
2518 EMIT_ASM32 (i386_reg_b
,
2519 "mov %eax,4(%esp)\n\t"
2520 "mov 8(%ebp),%eax\n\t"
2522 i386_emit_call (get_raw_reg_func_addr ());
2523 EMIT_ASM32 (i386_reg_c
,
2525 "lea 0x8(%esp),%esp");
2529 i386_emit_pop (void)
2531 EMIT_ASM32 (i386_pop
,
2537 i386_emit_stack_flush (void)
2539 EMIT_ASM32 (i386_stack_flush
,
2545 i386_emit_zero_ext (int arg
)
2550 EMIT_ASM32 (i386_zero_ext_8
,
2551 "and $0xff,%eax\n\t"
2555 EMIT_ASM32 (i386_zero_ext_16
,
2556 "and $0xffff,%eax\n\t"
2560 EMIT_ASM32 (i386_zero_ext_32
,
2569 i386_emit_swap (void)
2571 EMIT_ASM32 (i386_swap
,
2581 i386_emit_stack_adjust (int n
)
2583 unsigned char buf
[16];
2585 CORE_ADDR buildaddr
= current_insn_ptr
;
2588 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2592 append_insns (&buildaddr
, i
, buf
);
2593 current_insn_ptr
= buildaddr
;
2596 /* FN's prototype is `LONGEST(*fn)(int)'. */
2599 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2601 unsigned char buf
[16];
2603 CORE_ADDR buildaddr
;
2605 EMIT_ASM32 (i386_int_call_1_a
,
2606 /* Reserve a bit of stack space. */
2608 /* Put the one argument on the stack. */
2609 buildaddr
= current_insn_ptr
;
2611 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2614 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2616 append_insns (&buildaddr
, i
, buf
);
2617 current_insn_ptr
= buildaddr
;
2618 i386_emit_call (fn
);
2619 EMIT_ASM32 (i386_int_call_1_c
,
2621 "lea 0x8(%esp),%esp");
2624 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2627 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2629 unsigned char buf
[16];
2631 CORE_ADDR buildaddr
;
2633 EMIT_ASM32 (i386_void_call_2_a
,
2634 /* Preserve %eax only; we don't have to worry about %ebx. */
2636 /* Reserve a bit of stack space for arguments. */
2637 "sub $0x10,%esp\n\t"
2638 /* Copy "top" to the second argument position. (Note that
2639 we can't assume function won't scribble on its
2640 arguments, so don't try to restore from this.) */
2641 "mov %eax,4(%esp)\n\t"
2642 "mov %ebx,8(%esp)");
2643 /* Put the first argument on the stack. */
2644 buildaddr
= current_insn_ptr
;
2646 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2649 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2651 append_insns (&buildaddr
, i
, buf
);
2652 current_insn_ptr
= buildaddr
;
2653 i386_emit_call (fn
);
2654 EMIT_ASM32 (i386_void_call_2_b
,
2655 "lea 0x10(%esp),%esp\n\t"
2656 /* Restore original stack top. */
2662 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2665 /* Check low half first, more likely to be decider */
2666 "cmpl %eax,(%esp)\n\t"
2667 "jne .Leq_fallthru\n\t"
2668 "cmpl %ebx,4(%esp)\n\t"
2669 "jne .Leq_fallthru\n\t"
2670 "lea 0x8(%esp),%esp\n\t"
2673 /* jmp, but don't trust the assembler to choose the right jump */
2674 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2675 ".Leq_fallthru:\n\t"
2676 "lea 0x8(%esp),%esp\n\t"
2687 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2690 /* Check low half first, more likely to be decider */
2691 "cmpl %eax,(%esp)\n\t"
2693 "cmpl %ebx,4(%esp)\n\t"
2694 "je .Lne_fallthru\n\t"
2696 "lea 0x8(%esp),%esp\n\t"
2699 /* jmp, but don't trust the assembler to choose the right jump */
2700 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2701 ".Lne_fallthru:\n\t"
2702 "lea 0x8(%esp),%esp\n\t"
2713 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2716 "cmpl %ebx,4(%esp)\n\t"
2718 "jne .Llt_fallthru\n\t"
2719 "cmpl %eax,(%esp)\n\t"
2720 "jnl .Llt_fallthru\n\t"
2722 "lea 0x8(%esp),%esp\n\t"
2725 /* jmp, but don't trust the assembler to choose the right jump */
2726 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2727 ".Llt_fallthru:\n\t"
2728 "lea 0x8(%esp),%esp\n\t"
2739 i386_emit_le_goto (int *offset_p
, int *size_p
)
2742 "cmpl %ebx,4(%esp)\n\t"
2744 "jne .Lle_fallthru\n\t"
2745 "cmpl %eax,(%esp)\n\t"
2746 "jnle .Lle_fallthru\n\t"
2748 "lea 0x8(%esp),%esp\n\t"
2751 /* jmp, but don't trust the assembler to choose the right jump */
2752 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2753 ".Lle_fallthru:\n\t"
2754 "lea 0x8(%esp),%esp\n\t"
2765 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2768 "cmpl %ebx,4(%esp)\n\t"
2770 "jne .Lgt_fallthru\n\t"
2771 "cmpl %eax,(%esp)\n\t"
2772 "jng .Lgt_fallthru\n\t"
2774 "lea 0x8(%esp),%esp\n\t"
2777 /* jmp, but don't trust the assembler to choose the right jump */
2778 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2779 ".Lgt_fallthru:\n\t"
2780 "lea 0x8(%esp),%esp\n\t"
2791 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2794 "cmpl %ebx,4(%esp)\n\t"
2796 "jne .Lge_fallthru\n\t"
2797 "cmpl %eax,(%esp)\n\t"
2798 "jnge .Lge_fallthru\n\t"
2800 "lea 0x8(%esp),%esp\n\t"
2803 /* jmp, but don't trust the assembler to choose the right jump */
2804 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2805 ".Lge_fallthru:\n\t"
2806 "lea 0x8(%esp),%esp\n\t"
2816 struct emit_ops i386_emit_ops
=
2824 i386_emit_rsh_signed
,
2825 i386_emit_rsh_unsigned
,
2833 i386_emit_less_signed
,
2834 i386_emit_less_unsigned
,
2838 i386_write_goto_address
,
2843 i386_emit_stack_flush
,
2846 i386_emit_stack_adjust
,
2847 i386_emit_int_call_1
,
2848 i386_emit_void_call_2
,
2858 static struct emit_ops
*
2862 if (is_64bit_tdesc ())
2863 return &amd64_emit_ops
;
2866 return &i386_emit_ops
;
2869 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2871 static const gdb_byte
*
2872 x86_sw_breakpoint_from_kind (int kind
, int *size
)
2874 *size
= x86_breakpoint_len
;
2875 return x86_breakpoint
;
2879 x86_supports_range_stepping (void)
2884 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2888 x86_supports_hardware_single_step (void)
2894 x86_get_ipa_tdesc_idx (void)
2896 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2897 const struct target_desc
*tdesc
= regcache
->tdesc
;
2900 if (tdesc
== tdesc_amd64_linux
|| tdesc
== tdesc_amd64_linux_no_xml
2901 || tdesc
== tdesc_x32_linux
)
2902 return X86_TDESC_SSE
;
2903 if (tdesc
== tdesc_amd64_avx_linux
|| tdesc
== tdesc_x32_avx_linux
)
2904 return X86_TDESC_AVX
;
2905 if (tdesc
== tdesc_amd64_mpx_linux
)
2906 return X86_TDESC_MPX
;
2907 if (tdesc
== tdesc_amd64_avx_mpx_linux
)
2908 return X86_TDESC_AVX_MPX
;
2909 if (tdesc
== tdesc_amd64_avx_mpx_avx512_pku_linux
|| tdesc
== tdesc_x32_avx_avx512_linux
)
2910 return X86_TDESC_AVX_MPX_AVX512_PKU
;
2911 if (tdesc
== tdesc_amd64_avx_avx512_linux
)
2912 return X86_TDESC_AVX_AVX512
;
2915 if (tdesc
== tdesc_i386_mmx_linux
)
2916 return X86_TDESC_MMX
;
2917 if (tdesc
== tdesc_i386_linux
|| tdesc
== tdesc_i386_linux_no_xml
)
2918 return X86_TDESC_SSE
;
2919 if (tdesc
== tdesc_i386_avx_linux
)
2920 return X86_TDESC_AVX
;
2921 if (tdesc
== tdesc_i386_mpx_linux
)
2922 return X86_TDESC_MPX
;
2923 if (tdesc
== tdesc_i386_avx_mpx_linux
)
2924 return X86_TDESC_AVX_MPX
;
2925 if (tdesc
== tdesc_i386_avx_mpx_avx512_pku_linux
)
2926 return X86_TDESC_AVX_MPX_AVX512_PKU
;
2927 if (tdesc
== tdesc_i386_avx_avx512_linux
)
2928 return X86_TDESC_AVX_AVX512
;
2933 /* This is initialized assuming an amd64 target.
2934 x86_arch_setup will correct it for i386 or amd64 targets. */
2936 struct linux_target_ops the_low_target
=
2939 x86_linux_regs_info
,
2940 x86_cannot_fetch_register
,
2941 x86_cannot_store_register
,
2942 NULL
, /* fetch_register */
2945 NULL
, /* breakpoint_kind_from_pc */
2946 x86_sw_breakpoint_from_kind
,
2950 x86_supports_z_point_type
,
2953 x86_stopped_by_watchpoint
,
2954 x86_stopped_data_address
,
2955 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2956 native i386 case (no registers smaller than an xfer unit), and are not
2957 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2960 /* need to fix up i386 siginfo if host is amd64 */
2962 x86_linux_new_process
,
2963 x86_linux_new_thread
,
2965 x86_linux_prepare_to_resume
,
2966 x86_linux_process_qsupported
,
2967 x86_supports_tracepoints
,
2968 x86_get_thread_area
,
2969 x86_install_fast_tracepoint_jump_pad
,
2971 x86_get_min_fast_tracepoint_insn_len
,
2972 x86_supports_range_stepping
,
2973 NULL
, /* breakpoint_kind_from_current_state */
2974 x86_supports_hardware_single_step
,
2975 x86_get_syscall_trapinfo
,
2976 x86_get_ipa_tdesc_idx
,
2980 initialize_low_arch (void)
2982 /* Initialize the Linux target descriptions. */
2984 init_registers_amd64_linux ();
2985 init_registers_amd64_avx_linux ();
2986 init_registers_amd64_mpx_linux ();
2987 init_registers_amd64_avx_mpx_linux ();
2988 init_registers_amd64_avx_avx512_linux ();
2989 init_registers_amd64_avx_mpx_avx512_pku_linux ();
2991 init_registers_x32_linux ();
2992 init_registers_x32_avx_linux ();
2993 init_registers_x32_avx_avx512_linux ();
2995 tdesc_amd64_linux_no_xml
= XNEW (struct target_desc
);
2996 copy_target_description (tdesc_amd64_linux_no_xml
, tdesc_amd64_linux
);
2997 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2999 init_registers_i386_linux ();
3000 init_registers_i386_mmx_linux ();
3001 init_registers_i386_avx_linux ();
3002 init_registers_i386_mpx_linux ();
3003 init_registers_i386_avx_mpx_linux ();
3004 init_registers_i386_avx_avx512_linux ();
3005 init_registers_i386_avx_mpx_avx512_pku_linux ();
3007 tdesc_i386_linux_no_xml
= XNEW (struct target_desc
);
3008 copy_target_description (tdesc_i386_linux_no_xml
, tdesc_i386_linux
);
3009 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
3011 initialize_regsets_info (&x86_regsets_info
);