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Commit | Line | Data |
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03f5c550 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
03f5c550 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
03f5c550 WD |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8541cds board configuration file | |
9 | * | |
10 | * Please refer to doc/README.mpc85xxcds for more info. | |
11 | * | |
12 | */ | |
03f5c550 WD |
13 | #ifndef __CONFIG_H |
14 | #define __CONFIG_H | |
15 | ||
16 | /* High Level Configuration Options */ | |
9c4c5ae3 | 17 | #define CONFIG_CPM2 1 /* has CPM2 */ |
03f5c550 | 18 | |
2ae18241 WD |
19 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
20 | ||
842033e6 | 21 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 22 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 23 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
03f5c550 | 24 | #define CONFIG_ENV_OVERWRITE |
d9b94f28 | 25 | |
25eedb2c | 26 | #define CONFIG_FSL_VIA |
25eedb2c | 27 | |
03f5c550 WD |
28 | #ifndef __ASSEMBLY__ |
29 | extern unsigned long get_clock_freq(void); | |
30 | #endif | |
31 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
32 | ||
33 | /* | |
34 | * These can be toggled for performance analysis, otherwise use default. | |
35 | */ | |
53677ef1 | 36 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
03f5c550 | 37 | #define CONFIG_BTB /* toggle branch predition */ |
03f5c550 | 38 | |
6d0f6bcf JCPV |
39 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
40 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
03f5c550 | 41 | |
e46fedfe TT |
42 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
43 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
03f5c550 | 44 | |
aa11d85c | 45 | /* DDR Setup */ |
aa11d85c JL |
46 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
47 | #define CONFIG_DDR_SPD | |
48 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
49 | ||
50 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
51 | ||
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
53 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
03f5c550 | 54 | |
aa11d85c JL |
55 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
56 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
57 | ||
58 | /* I2C addresses of SPD EEPROMs */ | |
59 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
03f5c550 WD |
60 | |
61 | /* | |
62 | * Make sure required options are set | |
63 | */ | |
64 | #ifndef CONFIG_SPD_EEPROM | |
65 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") | |
66 | #endif | |
67 | ||
7202d43d JL |
68 | #undef CONFIG_CLOCKS_IN_MHZ |
69 | ||
03f5c550 | 70 | /* |
7202d43d | 71 | * Local Bus Definitions |
03f5c550 | 72 | */ |
7202d43d JL |
73 | |
74 | /* | |
75 | * FLASH on the Local Bus | |
76 | * Two banks, 8M each, using the CFI driver. | |
77 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
78 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
79 | * | |
80 | * BR0, BR1: | |
81 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
82 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
83 | * Port Size = 16 bits = BRx[19:20] = 10 | |
84 | * Use GPCM = BRx[24:26] = 000 | |
85 | * Valid = BRx[31] = 1 | |
86 | * | |
87 | * 0 4 8 12 16 20 24 28 | |
88 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
89 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
90 | * | |
91 | * OR0, OR1: | |
92 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
93 | * Reserved ORx[17:18] = 11, confusion here? | |
94 | * CSNT = ORx[20] = 1 | |
95 | * ACS = half cycle delay = ORx[21:22] = 11 | |
96 | * SCY = 6 = ORx[24:27] = 0110 | |
97 | * TRLX = use relaxed timing = ORx[29] = 1 | |
98 | * EAD = use external address latch delay = OR[31] = 1 | |
99 | * | |
100 | * 0 4 8 12 16 20 24 28 | |
101 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
102 | */ | |
103 | ||
6d0f6bcf | 104 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
03f5c550 | 105 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
107 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
03f5c550 | 108 | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
110 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
03f5c550 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
113 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
114 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
115 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
116 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
117 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
03f5c550 | 118 | |
14d0a02a | 119 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
03f5c550 | 120 | |
00b1883a | 121 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_FLASH_CFI |
123 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
03f5c550 | 124 | |
03f5c550 | 125 | /* |
7202d43d | 126 | * SDRAM on the Local Bus |
03f5c550 | 127 | */ |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
129 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
03f5c550 WD |
130 | |
131 | /* | |
132 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 133 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
03f5c550 WD |
134 | * |
135 | * For BR2, need: | |
136 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
137 | * port-size = 32-bits = BR2[19:20] = 11 | |
138 | * no parity checking = BR2[21:22] = 00 | |
139 | * SDRAM for MSEL = BR2[24:26] = 011 | |
140 | * Valid = BR[31] = 1 | |
141 | * | |
142 | * 0 4 8 12 16 20 24 28 | |
143 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
144 | * | |
6d0f6bcf | 145 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
03f5c550 WD |
146 | * FIXME: the top 17 bits of BR2. |
147 | */ | |
148 | ||
6d0f6bcf | 149 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
03f5c550 WD |
150 | |
151 | /* | |
6d0f6bcf | 152 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
03f5c550 WD |
153 | * |
154 | * For OR2, need: | |
155 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
156 | * XAM, OR2[17:18] = 11 | |
157 | * 9 columns OR2[19-21] = 010 | |
158 | * 13 rows OR2[23-25] = 100 | |
159 | * EAD set for extra time OR[31] = 1 | |
160 | * | |
161 | * 0 4 8 12 16 20 24 28 | |
162 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
163 | */ | |
164 | ||
6d0f6bcf | 165 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
03f5c550 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
168 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
169 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
170 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
03f5c550 | 171 | |
03f5c550 WD |
172 | /* |
173 | * Common settings for all Local Bus SDRAM commands. | |
174 | * At run time, either BSMA1516 (for CPU 1.1) | |
175 | * or BSMA1617 (for CPU 1.0) (old) | |
176 | * is OR'ed in too. | |
177 | */ | |
b0fe93ed KG |
178 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
179 | | LSDMR_PRETOACT7 \ | |
180 | | LSDMR_ACTTORW7 \ | |
181 | | LSDMR_BL8 \ | |
182 | | LSDMR_WRC4 \ | |
183 | | LSDMR_CL3 \ | |
184 | | LSDMR_RFEN \ | |
03f5c550 WD |
185 | ) |
186 | ||
187 | /* | |
188 | * The CADMUS registers are connected to CS3 on CDS. | |
189 | * The new memory map places CADMUS at 0xf8000000. | |
190 | * | |
191 | * For BR3, need: | |
192 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
193 | * port-size = 8-bits = BR[19:20] = 01 | |
194 | * no parity checking = BR[21:22] = 00 | |
195 | * GPMC for MSEL = BR[24:26] = 000 | |
196 | * Valid = BR[31] = 1 | |
197 | * | |
198 | * 0 4 8 12 16 20 24 28 | |
199 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
200 | * | |
201 | * For OR3, need: | |
202 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
203 | * disable buffer ctrl OR[19] = 0 | |
204 | * CSNT OR[20] = 1 | |
205 | * ACS OR[21:22] = 11 | |
206 | * XACS OR[23] = 1 | |
207 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
208 | * SETA OR[28] = 0 | |
209 | * TRLX OR[29] = 1 | |
210 | * EHTR OR[30] = 1 | |
211 | * EAD extra time OR[31] = 1 | |
212 | * | |
213 | * 0 4 8 12 16 20 24 28 | |
214 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
215 | */ | |
216 | ||
25eedb2c JL |
217 | #define CONFIG_FSL_CADMUS |
218 | ||
03f5c550 | 219 | #define CADMUS_BASE_ADDR 0xf8000000 |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
221 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
03f5c550 | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
224 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 225 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
03f5c550 | 226 | |
25ddd1fb | 227 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 228 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
03f5c550 | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
231 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
03f5c550 WD |
232 | |
233 | /* Serial Port */ | |
234 | #define CONFIG_CONS_INDEX 2 | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_NS16550_SERIAL |
236 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
237 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
03f5c550 | 238 | |
6d0f6bcf | 239 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
03f5c550 WD |
240 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
241 | ||
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
243 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
03f5c550 | 244 | |
20476726 JL |
245 | /* |
246 | * I2C | |
247 | */ | |
00f792e0 HS |
248 | #define CONFIG_SYS_I2C |
249 | #define CONFIG_SYS_I2C_FSL | |
250 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
251 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
252 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
253 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
03f5c550 | 254 | |
e8d18541 TT |
255 | /* EEPROM */ |
256 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_I2C_EEPROM_CCID |
258 | #define CONFIG_SYS_ID_EEPROM | |
259 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
260 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 261 | |
03f5c550 WD |
262 | /* |
263 | * General PCI | |
362dd830 | 264 | * Memory space is mapped 1-1, but I/O space must start from 0. |
03f5c550 | 265 | */ |
5af0fdd8 | 266 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 267 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 268 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 269 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 270 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 271 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
273 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
274 | ||
5af0fdd8 | 275 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
10795f42 | 276 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
5af0fdd8 | 277 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
6d0f6bcf | 278 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 279 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 |
5f91ef6a | 280 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
282 | #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ | |
03f5c550 | 283 | |
7f3f2bd2 RV |
284 | #ifdef CONFIG_LEGACY |
285 | #define BRIDGE_ID 17 | |
286 | #define VIA_ID 2 | |
287 | #else | |
288 | #define BRIDGE_ID 28 | |
289 | #define VIA_ID 4 | |
290 | #endif | |
03f5c550 WD |
291 | |
292 | #if defined(CONFIG_PCI) | |
293 | ||
bf1dfffd | 294 | #define CONFIG_MPC85XX_PCI2 |
03f5c550 WD |
295 | |
296 | #undef CONFIG_EEPRO100 | |
297 | #undef CONFIG_TULIP | |
298 | ||
03f5c550 | 299 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 300 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
03f5c550 WD |
301 | |
302 | #endif /* CONFIG_PCI */ | |
303 | ||
03f5c550 WD |
304 | #if defined(CONFIG_TSEC_ENET) |
305 | ||
03f5c550 | 306 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
307 | #define CONFIG_TSEC1 1 |
308 | #define CONFIG_TSEC1_NAME "TSEC0" | |
309 | #define CONFIG_TSEC2 1 | |
310 | #define CONFIG_TSEC2_NAME "TSEC1" | |
03f5c550 WD |
311 | #define TSEC1_PHY_ADDR 0 |
312 | #define TSEC2_PHY_ADDR 1 | |
03f5c550 WD |
313 | #define TSEC1_PHYIDX 0 |
314 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
315 | #define TSEC1_FLAGS TSEC_GIGABIT |
316 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
317 | |
318 | /* Options are: TSEC[0-1] */ | |
319 | #define CONFIG_ETHPRIME "TSEC0" | |
03f5c550 WD |
320 | |
321 | #endif /* CONFIG_TSEC_ENET */ | |
322 | ||
03f5c550 WD |
323 | /* |
324 | * Environment | |
325 | */ | |
5a1aceb0 | 326 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 327 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
328 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
329 | #define CONFIG_ENV_SIZE 0x2000 | |
03f5c550 WD |
330 | |
331 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
03f5c550 | 333 | |
659e2f67 JL |
334 | /* |
335 | * BOOTP options | |
336 | */ | |
337 | #define CONFIG_BOOTP_BOOTFILESIZE | |
338 | #define CONFIG_BOOTP_BOOTPATH | |
339 | #define CONFIG_BOOTP_GATEWAY | |
340 | #define CONFIG_BOOTP_HOSTNAME | |
341 | ||
2835e518 JL |
342 | /* |
343 | * Command line configuration. | |
344 | */ | |
1c9aa76b | 345 | #define CONFIG_CMD_IRQ |
199e262e | 346 | #define CONFIG_CMD_REGINFO |
2835e518 | 347 | |
03f5c550 | 348 | #if defined(CONFIG_PCI) |
2835e518 | 349 | #define CONFIG_CMD_PCI |
03f5c550 | 350 | #endif |
2835e518 | 351 | |
03f5c550 WD |
352 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
353 | ||
354 | /* | |
355 | * Miscellaneous configurable options | |
356 | */ | |
6d0f6bcf | 357 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
358 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
359 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 360 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
2835e518 | 361 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 362 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
03f5c550 | 363 | #else |
6d0f6bcf | 364 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
03f5c550 | 365 | #endif |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
367 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
368 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
03f5c550 WD |
369 | |
370 | /* | |
371 | * For booting Linux, the board info and command line data | |
a832ac41 | 372 | * have to be in the first 64 MB of memory, since this is |
03f5c550 WD |
373 | * the maximum mapped by the Linux kernel during initialization. |
374 | */ | |
a832ac41 KG |
375 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
376 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
03f5c550 | 377 | |
2835e518 | 378 | #if defined(CONFIG_CMD_KGDB) |
03f5c550 | 379 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
03f5c550 WD |
380 | #endif |
381 | ||
03f5c550 WD |
382 | /* |
383 | * Environment Configuration | |
384 | */ | |
385 | ||
386 | /* The mac addresses for all ethernet interface */ | |
387 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 388 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 389 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 390 | #define CONFIG_HAS_ETH2 |
03f5c550 WD |
391 | #endif |
392 | ||
393 | #define CONFIG_IPADDR 192.168.1.253 | |
394 | ||
395 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 396 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 397 | #define CONFIG_BOOTFILE "your.uImage" |
03f5c550 WD |
398 | |
399 | #define CONFIG_SERVERIP 192.168.1.1 | |
400 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
401 | #define CONFIG_NETMASK 255.255.255.0 | |
402 | ||
403 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
404 | ||
03f5c550 WD |
405 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
406 | ||
407 | #define CONFIG_BAUDRATE 115200 | |
408 | ||
409 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
410 | "netdev=eth0\0" \ | |
411 | "consoledev=ttyS1\0" \ | |
8272dc2f AF |
412 | "ramdiskaddr=600000\0" \ |
413 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
414 | "fdtaddr=400000\0" \ | |
415 | "fdtfile=your.fdt.dtb\0" | |
03f5c550 WD |
416 | |
417 | #define CONFIG_NFSBOOTCOMMAND \ | |
418 | "setenv bootargs root=/dev/nfs rw " \ | |
419 | "nfsroot=$serverip:$rootpath " \ | |
420 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
421 | "console=$consoledev,$baudrate $othbootargs;" \ | |
422 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
423 | "tftp $fdtaddr $fdtfile;" \ |
424 | "bootm $loadaddr - $fdtaddr" | |
03f5c550 WD |
425 | |
426 | #define CONFIG_RAMBOOTCOMMAND \ | |
427 | "setenv bootargs root=/dev/ram rw " \ | |
428 | "console=$consoledev,$baudrate $othbootargs;" \ | |
429 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
430 | "tftp $loadaddr $bootfile;" \ | |
431 | "bootm $loadaddr $ramdiskaddr" | |
432 | ||
433 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
434 | ||
03f5c550 | 435 | #endif /* __CONFIG_H */ |