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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
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22#define CONFIG_SYS_GENERIC_BOARD
23#define CONFIG_DISPLAY_BOARDINFO
56523f12 24
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25/*
26 * Valid values for CONFIG_SYS_TEXT_BASE are:
27 * 0xFC000000 boot low (standard configuration with room for
28 * max 64 MByte Flash ROM)
29 * 0xFFF00000 boot high (for a backup copy of U-Boot)
30 * 0x00100000 boot from RAM (for testing only)
31 */
32#ifndef CONFIG_SYS_TEXT_BASE
33#define CONFIG_SYS_TEXT_BASE 0xFC000000
34#endif
35
5196a7a0 36/* On a Cameron or on a FO300 board or ... */
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37#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
38 && !defined(CONFIG_FO300)
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39#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
40#endif
41
6d0f6bcf 42#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 43
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44#define CONFIG_HIGH_BATS 1 /* High BATs supported */
45
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46/*
47 * Serial console configuration
48 */
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49#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 51#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 52#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 53
6d3bc9b8 54#ifdef CONFIG_FO300
6d0f6bcf 55#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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56#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
57#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 58#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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59#if 0
60#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
61 /* switch is closed */
62#endif
63
64#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
65 /* switch is open */
5196a7a0 66#endif /* CONFIG_FO300 */
6d3bc9b8 67
98e69567 68#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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69#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
70#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
71#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 72#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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73#define CONFIG_BOARD_EARLY_INIT_R
74#endif /* CONFIG_STK52XX */
56523f12 75
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76/*
77 * PCI Mapping:
78 * 0x40000000 - 0x4fffffff - PCI Memory
79 * 0x50000000 - 0x50ffffff - PCI IO Space
80 */
98e69567 81#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 82#define CONFIG_PCI 1
56523f12 83#define CONFIG_PCI_PNP 1
31a64923 84/* #define CONFIG_PCI_SCAN_SHOW 1 */
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85
86#define CONFIG_PCI_MEM_BUS 0x40000000
87#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
88#define CONFIG_PCI_MEM_SIZE 0x10000000
89
90#define CONFIG_PCI_IO_BUS 0x50000000
91#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
92#define CONFIG_PCI_IO_SIZE 0x01000000
93
cd65a3dc 94#define CONFIG_EEPRO100 1
6d0f6bcf 95#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 96#define CONFIG_NS8382X 1
83e40ba7 97#endif /* CONFIG_STK52XX */
56523f12 98
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99/*
100 * Video console
101 */
5078cce8 102#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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103#define CONFIG_VIDEO
104#define CONFIG_VIDEO_SM501
105#define CONFIG_VIDEO_SM501_32BPP
106#define CONFIG_CFB_CONSOLE
107#define CONFIG_VIDEO_LOGO
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108
109#ifndef CONFIG_FO300
8f0b7cbe 110#define CONFIG_CONSOLE_EXTRA_INFO
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111#else
112#define CONFIG_VIDEO_BMP_LOGO
113#endif
114
115#define CONFIG_VGA_AS_SINGLE_DEVICE
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116#define CONFIG_VIDEO_SW_CURSOR
117#define CONFIG_SPLASH_SCREEN
6d0f6bcf 118#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 119#endif /* #ifndef CONFIG_TQM5200S */
56523f12 120
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121
122/* Partitions */
89c02e2c 123#define CONFIG_MAC_PARTITION
56523f12 124#define CONFIG_DOS_PARTITION
8f0b7cbe 125#define CONFIG_ISO_PARTITION
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126
127/* USB */
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128#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
129 defined(CONFIG_STK52XX)
7b59b3c7 130#define CONFIG_USB_OHCI_NEW
6d0f6bcf 131#define CONFIG_SYS_OHCI_BE_CONTROLLER
56523f12 132#define CONFIG_USB_STORAGE
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133#define CONFIG_CMD_FAT
134#define CONFIG_CMD_USB
53e336e9 135
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136#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
137#define CONFIG_SYS_USB_OHCI_CPU_INIT
138#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
139#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
140#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 141
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142#endif
143
135ae006 144#ifndef CONFIG_CAM5200
56523f12 145/* POST support */
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146#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
147 CONFIG_SYS_POST_CPU | \
148 CONFIG_SYS_POST_I2C)
5078cce8 149#endif
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150
151#ifdef CONFIG_POST
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152/* preserve space for the post_word at end of on-chip SRAM */
153#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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154#endif
155
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156
157/*
a1aa0bb5 158 * BOOTP options
56523f12 159 */
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160#define CONFIG_BOOTP_BOOTFILESIZE
161#define CONFIG_BOOTP_BOOTPATH
162#define CONFIG_BOOTP_GATEWAY
163#define CONFIG_BOOTP_HOSTNAME
164
165
56523f12 166/*
2694690e 167 * Command line configuration.
56523f12 168 */
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169#define CONFIG_CMD_ASKENV
170#define CONFIG_CMD_DATE
171#define CONFIG_CMD_DHCP
172#define CONFIG_CMD_EEPROM
173#define CONFIG_CMD_I2C
174#define CONFIG_CMD_JFFS2
175#define CONFIG_CMD_MII
2694690e 176#define CONFIG_CMD_PING
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177#define CONFIG_CMD_REGINFO
178#define CONFIG_CMD_SNTP
179#define CONFIG_CMD_BSP
180
181#ifdef CONFIG_VIDEO
182 #define CONFIG_CMD_BMP
183#endif
184
185#ifdef CONFIG_PCI
2b2a587d 186#define CONFIG_CMD_PCI
f33fca22 187#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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188#endif
189
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190#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
191 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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192 #define CONFIG_CMD_IDE
193 #define CONFIG_CMD_FAT
194 #define CONFIG_CMD_EXT2
195#endif
196
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197#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
198 defined(CONFIG_STK52XX)
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199 #define CONFIG_CFG_USB
200 #define CONFIG_CFG_FAT
201#endif
202
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203#ifdef CONFIG_POST
204 #define CONFIG_CMD_DIAG
205#endif
206
56523f12 207
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208#define CONFIG_TIMESTAMP /* display image timestamps */
209
14d0a02a 210#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 211# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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212#endif
213
214/*
215 * Autobooting
216 */
217#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
218
81050926 219#define CONFIG_PREBOOT "echo;" \
4c4aca81 220 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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221 "echo"
222
223#undef CONFIG_BOOTARGS
224
6d0f6bcf 225#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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226# define ENV_UPDT \
227 "update=protect off FFF00000 +${filesize};" \
228 "erase FFF00000 +${filesize};" \
5078cce8 229 "cp.b 200000 FFF00000 ${filesize};" \
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230 "protect on FFF00000 +${filesize}\0"
231#else /* default lowboot configuration */
6d3bc9b8 232# define ENV_UPDT \
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233 "update=protect off FC000000 +${filesize};" \
234 "erase FC000000 +${filesize};" \
6d3bc9b8 235 "cp.b 200000 FC000000 ${filesize};" \
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236 "protect on FC000000 +${filesize}\0"
237#endif
5078cce8 238
e1f601b5 239#if defined(CONFIG_TQM5200)
6abaee42 240#define CUSTOM_ENV_SETTINGS \
e1f601b5 241 "hostname=tqm5200\0" \
6abaee42 242 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 243 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 244 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 245#elif defined(CONFIG_CAM5200)
1636d1c8 246#define CUSTOM_ENV_SETTINGS \
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247 "bootfile=cam5200/uImage\0" \
248 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 249 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
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250#endif
251
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252#if defined(CONFIG_TQM5200_B)
253#define ENV_FLASH_LAYOUT \
254 "fdt_addr=FC100000\0" \
255 "kernel_addr=FC140000\0" \
256 "ramdisk_addr=FC600000\0"
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257#elif defined(CONFIG_CHARON)
258#define ENV_FLASH_LAYOUT \
259 "fdt_addr=FDFC0000\0" \
260 "kernel_addr=FC0A0000\0" \
261 "ramdisk_addr=FC200000\0"
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262#else /* !CONFIG_TQM5200_B */
263#define ENV_FLASH_LAYOUT \
264 "fdt_addr=FC0A0000\0" \
265 "kernel_addr=FC0C0000\0" \
266 "ramdisk_addr=FC300000\0"
267#endif
268
81050926 269#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 270 "netdev=eth0\0" \
e1f601b5 271 "console=ttyPSC0\0" \
a5cc5555 272 ENV_FLASH_LAYOUT \
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273 "kernel_addr_r=400000\0" \
274 "fdt_addr_r=600000\0" \
89c02e2c 275 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 276 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 277 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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278 "nfsroot=${serverip}:${rootpath}\0" \
279 "addip=setenv bootargs ${bootargs} " \
280 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
281 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 282 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 283 "console=${console},${baudrate}\0" \
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284 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
285 "flash_self_old=sete console ttyS0; " \
286 "run ramargs addip addcons addmtd; " \
fe126d8b 287 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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288 "flash_self=run ramargs addip addcons;" \
289 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
290 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 291 "bootm ${kernel_addr}\0" \
e1f601b5 292 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 293 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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294 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
295 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
296 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
297 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 298 "run nfsargs addip addcons addmtd; " \
e1f601b5 299 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 300 CUSTOM_ENV_SETTINGS \
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301 "load=tftp 200000 ${u-boot}\0" \
302 ENV_UPDT \
7e6bf358 303 ""
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304
305#define CONFIG_BOOTCOMMAND "run net_nfs"
306
307/*
308 * IPB Bus clocking configuration.
309 */
6d0f6bcf 310#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 311
6d0f6bcf 312#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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313/*
314 * PCI Bus clocking configuration
315 *
316 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 317 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 318 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 319 */
6d0f6bcf 320#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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321#endif
322
323/*
324 * I2C configuration
325 */
326#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 327#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 328#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 329#else
6d0f6bcf 330#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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331#endif
332
333/*
334 * I2C clock frequency
335 *
336 * Please notice, that the resulting clock frequency could differ from the
337 * configured value. This is because the I2C clock is derived from system
338 * clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf 339 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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340 * approximation allways lies below the configured value, never above.
341 */
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342#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
343#define CONFIG_SYS_I2C_SLAVE 0x7F
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344
345/*
346 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
347 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
348 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
349 * same configuration could be used.
350 */
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351#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
352#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
353#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
354#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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355
356/*
357 * HW-Monitor configuration on Mini-FAP
358 */
359#if defined (CONFIG_MINIFAP)
6d0f6bcf 360#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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361#endif
362
363/* List of I2C addresses to be verified by POST */
56523f12 364#if defined (CONFIG_MINIFAP)
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365#undef CONFIG_SYS_POST_I2C_ADDRS
366#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
367 CONFIG_SYS_I2C_HWMON_ADDR, \
368 CONFIG_SYS_I2C_SLAVE}
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369#endif
370
371/*
372 * Flash configuration
373 */
6d0f6bcf 374#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 375
d9384de2 376#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 377#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 378 (= chip selects) */
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379#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
380#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
381#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
382
383#define CONFIG_SYS_FLASH_ADDR0 0x555
384#define CONFIG_SYS_FLASH_ADDR1 0x2AA
385#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
386#define CONFIG_SYS_MAX_FLASH_SECT 128
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387#else
388/* use CFI flash driver */
6d0f6bcf 389#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 390#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 391#define CONFIG_FLASH_CFI_MTD /* with MTD support */
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392#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
393#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 394 (= chip selects) */
6d0f6bcf 395#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 396#endif
7299712c 397
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398#define CONFIG_SYS_FLASH_EMPTY_INFO
399#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
400#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 401
135ae006 402#if defined (CONFIG_CAM5200)
6d0f6bcf 403# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 404#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 405# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 406#else
6d0f6bcf 407# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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408#endif
409
d534f5cc 410/* Dynamic MTD partition support */
68d7d651 411#define CONFIG_CMD_MTDPARTS
942556a9 412#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 413#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 414
5624d66a 415#if defined(CONFIG_STK52XX)
5078cce8 416# if defined(CONFIG_TQM5200_B)
6d0f6bcf 417# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 418# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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419 "256k(dtb)," \
420 "2304k(kernel)," \
421 "2560k(small-fs)," \
45a212c4 422 "2m(initrd)," \
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423 "8m(misc)," \
424 "16m(big-fs)"
425# else /* highboot */
259bff7c 426# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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427 "3584k(small-fs)," \
428 "2m(initrd)," \
429 "8m(misc)," \
430 "15m(big-fs)," \
431 "1m(firmware)"
6d0f6bcf 432# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 433# else /* !CONFIG_TQM5200_B */
259bff7c 434# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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435 "128k(dtb)," \
436 "2304k(kernel)," \
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437 "2m(initrd)," \
438 "4m(small-fs)," \
5078cce8 439 "8m(misc)," \
e1f601b5 440 "15m(big-fs)"
5078cce8 441# endif /* CONFIG_TQM5200_B */
135ae006 442#elif defined (CONFIG_CAM5200)
259bff7c 443# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 444 "1792k(kernel)," \
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445 "5632k(rootfs)," \
446 "24m(home)"
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447#elif defined (CONFIG_CHARON)
448# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
449 "1408k(kernel)," \
450 "2m(initrd)," \
451 "4m(small-fs)," \
452 "24320k(big-fs)," \
453 "256k(dts)"
6d3bc9b8 454#elif defined (CONFIG_FO300)
259bff7c 455# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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456 "1408k(kernel)," \
457 "2m(initrd)," \
458 "4m(small-fs)," \
459 "8m(misc)," \
460 "16m(big-fs)"
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461#else
462# error "Unknown Carrier Board"
463#endif /* CONFIG_STK52XX */
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464
465/*
466 * Environment settings
467 */
5a1aceb0 468#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 469#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 470#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 471#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 472#else
0e8d1586 473#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 474#endif /* CONFIG_TQM5200_B */
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475#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
476#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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477
478/*
479 * Memory map
480 */
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481#define CONFIG_SYS_MBAR 0xF0000000
482#define CONFIG_SYS_SDRAM_BASE 0x00000000
483#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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484
485/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 486#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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487#ifdef CONFIG_POST
488/* preserve space for the post_word at end of on-chip SRAM */
553f0982 489#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 490#else
553f0982 491#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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492#endif
493
494
25ddd1fb 495#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 496#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 497
14d0a02a 498#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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499#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
500# define CONFIG_SYS_RAMBOOT 1
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501#endif
502
135ae006 503#if defined (CONFIG_CAM5200)
6d0f6bcf 504# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 505#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 506# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 507#else
6d0f6bcf 508# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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509#endif
510
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511#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
512#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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513
514/*
515 * Ethernet configuration
516 */
517#define CONFIG_MPC5xxx_FEC 1
86321fc1 518#define CONFIG_MPC5xxx_FEC_MII100
56523f12 519/*
86321fc1 520 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 521 */
86321fc1 522/* #define CONFIG_MPC5xxx_FEC_MII10 */
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523#define CONFIG_PHY_ADDR 0x00
524
525/*
526 * GPIO configuration
527 *
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528 * use CS1: Bit 0 (mask: 0x80000000):
529 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 530 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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531 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
532 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
533 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
534 * Use for REV200 STK52XX boards and FO300 boards. Do not use
535 * with REV100 modules (because, there I2C1 is used as I2C bus).
536 * use ATA: Bits 6-7 (mask 0x03000000):
537 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
538 * Use for CAM5200 board.
539 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
540 * use PSC6: Bits 9-11 (mask 0x00700000):
541 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
542 * UART, CODEC or IrDA.
543 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
544 * enable extended POST tests.
545 * Use for MINI-FAP and TQM5200_IB boards.
546 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
547 * Extended POST test is not available.
548 * Use for STK52xx, FO300 and CAM5200 boards.
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549 * WARNING: When the extended POST is enabled, these bits will
550 * be overridden by this code as GPIOs!
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551 * use PCI_DIS: Bit 16 (mask 0x00008000):
552 * 1 -> disable PCI controller (on CAM5200 board).
553 * use USB: Bits 18-19 (mask 0x00003000):
554 * 10 -> two UARTs (on FO300 and CAM5200).
555 * use PSC3: Bits 20-23 (mask: 0x00000f00):
556 * 0000 -> All PSC3 pins are GPIOs.
557 * 1100 -> UART/SPI (on FO300 board).
558 * 0100 -> UART (on CAM5200 board).
559 * use PSC2: Bits 25:27 (mask: 0x00000030):
560 * 000 -> All PSC2 pins are GPIOs.
561 * 100 -> UART (on CAM5200 board).
562 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 563 * Use for REV100 STK52xx boards
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564 * 01x -> Use AC97 (on FO300 board).
565 * use PSC1: Bits 29-31 (mask: 0x00000007):
566 * 100 -> UART (on all boards).
56523f12 567 */
98e69567 568#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 569#if defined (CONFIG_MINIFAP)
6d0f6bcf 570# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 571#elif defined (CONFIG_STK52XX)
83e40ba7 572# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 573# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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574# else /* STK52xx REV200 and above */
575# if defined (CONFIG_TQM5200_REV100)
576# error TQM5200 REV100 not supported on STK52XX REV200 or above
577# else/* TQM5200 REV200 and above */
6d0f6bcf 578# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 579# endif
8f0b7cbe 580# endif
6d3bc9b8 581#elif defined (CONFIG_FO300)
6d0f6bcf 582# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 583#elif defined (CONFIG_CAM5200)
6d0f6bcf 584# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 585#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 586# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 587#endif
98e69567 588#endif
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589
590/*
591 * RTC configuration
592 */
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593#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
594# define CONFIG_RTC_M41T11 1
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595# define CONFIG_SYS_I2C_RTC_ADDR 0x68
596# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 597 year */
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598#else
599# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
600#endif
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601
602/*
603 * Miscellaneous configurable options
604 */
6d0f6bcf 605#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 606
2751a95a 607#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf 608#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
5078cce8 609
6d0f6bcf 610#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 611#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 612#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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613#endif
614
615#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 616#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 617#else
6d0f6bcf 618#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 619#endif
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620#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
621#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
622#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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623
624/* Enable an alternate, more extensive memory test */
6d0f6bcf 625#define CONFIG_SYS_ALT_MEMTEST
56523f12 626
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627#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
628#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 629
6d0f6bcf 630#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 631
56523f12 632/*
a1aa0bb5 633 * Enable loopw command.
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634 */
635#define CONFIG_LOOPW
636
637/*
638 * Various low-level settings
639 */
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640#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
641#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 642
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643#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
644#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
645#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
646#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 647#else
6d0f6bcf 648#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 649#endif
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650#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
651#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 652
7e6bf358 653#define CONFIG_LAST_STAGE_INIT
7e6bf358 654
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655/*
656 * SRAM - Do not map below 2 GB in address space, because this area is used
657 * for SDRAM autosizing.
658 */
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659#define CONFIG_SYS_CS2_START 0xE5000000
660#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
661#define CONFIG_SYS_CS2_CFG 0x0004D930
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662
663/*
664 * Grafic controller - Do not map below 2 GB in address space, because this
665 * area is used for SDRAM autosizing.
666 */
8f0b7cbe 667#define SM501_FB_BASE 0xE0000000
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668#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
669#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
670#define CONFIG_SYS_CS1_CFG 0x8F48FF70
671#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 672
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673#define CONFIG_SYS_CS_BURST 0x00000000
674#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 675
7299712c 676#if defined(CONFIG_CAM5200)
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677#define CONFIG_SYS_CS4_START 0xB0000000
678#define CONFIG_SYS_CS4_SIZE 0x00010000
679#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 680
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681#define CONFIG_SYS_CS5_START 0xD0000000
682#define CONFIG_SYS_CS5_SIZE 0x01208000
683#define CONFIG_SYS_CS5_CFG 0x1414BF10
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684#endif
685
6d0f6bcf 686#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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687
688/*-----------------------------------------------------------------------
689 * USB stuff
690 *-----------------------------------------------------------------------
691 */
692#define CONFIG_USB_CLOCK 0x0001BBBB
693#define CONFIG_USB_CONFIG 0x00001000
694
695/*-----------------------------------------------------------------------
696 * IDE/ATA stuff Supports IDE harddisk
697 *-----------------------------------------------------------------------
698 */
699
81050926 700#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 701
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702#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
703#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 704
81050926 705#define CONFIG_IDE_RESET /* reset for ide supported */
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706#define CONFIG_IDE_PREINIT
707
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708#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
709#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 710
6d0f6bcf 711#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 712
6d0f6bcf 713#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 714
95c44ec4 715/* Offset for data I/O */
6d0f6bcf 716#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 717
95c44ec4 718/* Offset for normal register accesses */
6d0f6bcf 719#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 720
95c44ec4 721/* Offset for alternate registers */
6d0f6bcf 722#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 723
95c44ec4 724/* Interval between registers */
6d0f6bcf 725#define CONFIG_SYS_ATA_STRIDE 4
56523f12 726
33af3e66 727/* Support ATAPI devices */
95c44ec4 728#define CONFIG_ATAPI 1
33af3e66 729
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730/*-----------------------------------------------------------------------
731 * Open firmware flat tree support
732 *-----------------------------------------------------------------------
733 */
cf2817a8 734#define CONFIG_OF_LIBFDT 1
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735#define CONFIG_OF_BOARD_SETUP 1
736
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737#define OF_CPU "PowerPC,5200@0"
738#define OF_SOC "soc5200@f0000000"
739#define OF_TBCLK (bd->bi_busfreq / 4)
740#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
741
56523f12 742#endif /* __CONFIG_H */