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56523f12 | 1 | /* |
69445d6c | 2 | * (C) Copyright 2003-2014 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
45a212c4 | 5 | * (C) Copyright 2004-2006 |
56523f12 WD |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
56523f12 WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
56523f12 WD |
14 | /* |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5078cce8 WD |
20 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
21 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
69445d6c WD |
22 | #define CONFIG_SYS_GENERIC_BOARD |
23 | #define CONFIG_DISPLAY_BOARDINFO | |
56523f12 | 24 | |
2ae18241 WD |
25 | /* |
26 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
27 | * 0xFC000000 boot low (standard configuration with room for | |
28 | * max 64 MByte Flash ROM) | |
29 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
30 | * 0x00100000 boot from RAM (for testing only) | |
31 | */ | |
32 | #ifndef CONFIG_SYS_TEXT_BASE | |
33 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
34 | #endif | |
35 | ||
5196a7a0 | 36 | /* On a Cameron or on a FO300 board or ... */ |
98e69567 HS |
37 | #if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \ |
38 | && !defined(CONFIG_FO300) | |
5078cce8 WD |
39 | #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ |
40 | #endif | |
41 | ||
6d0f6bcf | 42 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
56523f12 | 43 | |
31d82672 BB |
44 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
45 | ||
56523f12 WD |
46 | /* |
47 | * Serial console configuration | |
48 | */ | |
5078cce8 WD |
49 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
50 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 51 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
bef92e21 | 52 | #define CONFIG_BOOTCOUNT_LIMIT 1 |
56523f12 | 53 | |
6d3bc9b8 | 54 | #ifdef CONFIG_FO300 |
6d0f6bcf | 55 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ |
6d3bc9b8 MB |
56 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
57 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ | |
ddde6b7c | 58 | #define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ |
6d3bc9b8 MB |
59 | #if 0 |
60 | #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ | |
61 | /* switch is closed */ | |
62 | #endif | |
63 | ||
64 | #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ | |
65 | /* switch is open */ | |
5196a7a0 | 66 | #endif /* CONFIG_FO300 */ |
6d3bc9b8 | 67 | |
98e69567 | 68 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
7e6bf358 WD |
69 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ |
70 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
71 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 72 | #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
7e6bf358 WD |
73 | #define CONFIG_BOARD_EARLY_INIT_R |
74 | #endif /* CONFIG_STK52XX */ | |
56523f12 | 75 | |
56523f12 WD |
76 | /* |
77 | * PCI Mapping: | |
78 | * 0x40000000 - 0x4fffffff - PCI Memory | |
79 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
80 | */ | |
98e69567 | 81 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
7e6bf358 | 82 | #define CONFIG_PCI 1 |
56523f12 | 83 | #define CONFIG_PCI_PNP 1 |
31a64923 | 84 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
56523f12 WD |
85 | |
86 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
87 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
88 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
89 | ||
90 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
91 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
92 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
93 | ||
cd65a3dc | 94 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 95 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
56523f12 | 96 | #define CONFIG_NS8382X 1 |
83e40ba7 | 97 | #endif /* CONFIG_STK52XX */ |
56523f12 | 98 | |
8f0b7cbe WD |
99 | /* |
100 | * Video console | |
101 | */ | |
5078cce8 | 102 | #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ |
8f0b7cbe WD |
103 | #define CONFIG_VIDEO |
104 | #define CONFIG_VIDEO_SM501 | |
105 | #define CONFIG_VIDEO_SM501_32BPP | |
106 | #define CONFIG_CFB_CONSOLE | |
107 | #define CONFIG_VIDEO_LOGO | |
6d3bc9b8 MB |
108 | |
109 | #ifndef CONFIG_FO300 | |
8f0b7cbe | 110 | #define CONFIG_CONSOLE_EXTRA_INFO |
6d3bc9b8 MB |
111 | #else |
112 | #define CONFIG_VIDEO_BMP_LOGO | |
113 | #endif | |
114 | ||
115 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
8f0b7cbe WD |
116 | #define CONFIG_VIDEO_SW_CURSOR |
117 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 118 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
6d3bc9b8 | 119 | #endif /* #ifndef CONFIG_TQM5200S */ |
56523f12 | 120 | |
56523f12 WD |
121 | |
122 | /* Partitions */ | |
89c02e2c | 123 | #define CONFIG_MAC_PARTITION |
56523f12 | 124 | #define CONFIG_DOS_PARTITION |
8f0b7cbe | 125 | #define CONFIG_ISO_PARTITION |
56523f12 WD |
126 | |
127 | /* USB */ | |
98e69567 HS |
128 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
129 | defined(CONFIG_STK52XX) | |
7b59b3c7 | 130 | #define CONFIG_USB_OHCI_NEW |
6d0f6bcf | 131 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
56523f12 | 132 | #define CONFIG_USB_STORAGE |
afaac86f WD |
133 | #define CONFIG_CMD_FAT |
134 | #define CONFIG_CMD_USB | |
53e336e9 | 135 | |
6d0f6bcf JCPV |
136 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
137 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
138 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
139 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
140 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 141 | |
56523f12 WD |
142 | #endif |
143 | ||
135ae006 | 144 | #ifndef CONFIG_CAM5200 |
56523f12 | 145 | /* POST support */ |
6d0f6bcf JCPV |
146 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
147 | CONFIG_SYS_POST_CPU | \ | |
148 | CONFIG_SYS_POST_I2C) | |
5078cce8 | 149 | #endif |
56523f12 WD |
150 | |
151 | #ifdef CONFIG_POST | |
56523f12 WD |
152 | /* preserve space for the post_word at end of on-chip SRAM */ |
153 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
56523f12 WD |
154 | #endif |
155 | ||
56523f12 WD |
156 | |
157 | /* | |
a1aa0bb5 | 158 | * BOOTP options |
56523f12 | 159 | */ |
a1aa0bb5 JL |
160 | #define CONFIG_BOOTP_BOOTFILESIZE |
161 | #define CONFIG_BOOTP_BOOTPATH | |
162 | #define CONFIG_BOOTP_GATEWAY | |
163 | #define CONFIG_BOOTP_HOSTNAME | |
164 | ||
165 | ||
56523f12 | 166 | /* |
2694690e | 167 | * Command line configuration. |
56523f12 | 168 | */ |
2694690e JL |
169 | #include <config_cmd_default.h> |
170 | ||
171 | #define CONFIG_CMD_ASKENV | |
172 | #define CONFIG_CMD_DATE | |
173 | #define CONFIG_CMD_DHCP | |
174 | #define CONFIG_CMD_EEPROM | |
175 | #define CONFIG_CMD_I2C | |
176 | #define CONFIG_CMD_JFFS2 | |
177 | #define CONFIG_CMD_MII | |
178 | #define CONFIG_CMD_NFS | |
179 | #define CONFIG_CMD_PING | |
2694690e JL |
180 | #define CONFIG_CMD_REGINFO |
181 | #define CONFIG_CMD_SNTP | |
182 | #define CONFIG_CMD_BSP | |
183 | ||
184 | #ifdef CONFIG_VIDEO | |
185 | #define CONFIG_CMD_BMP | |
186 | #endif | |
187 | ||
188 | #ifdef CONFIG_PCI | |
2b2a587d | 189 | #define CONFIG_CMD_PCI |
f33fca22 | 190 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2694690e JL |
191 | #endif |
192 | ||
98e69567 HS |
193 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
194 | defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) | |
2694690e JL |
195 | #define CONFIG_CMD_IDE |
196 | #define CONFIG_CMD_FAT | |
197 | #define CONFIG_CMD_EXT2 | |
198 | #endif | |
199 | ||
98e69567 HS |
200 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
201 | defined(CONFIG_STK52XX) | |
2694690e JL |
202 | #define CONFIG_CFG_USB |
203 | #define CONFIG_CFG_FAT | |
204 | #endif | |
205 | ||
af075ee9 JL |
206 | #ifdef CONFIG_POST |
207 | #define CONFIG_CMD_DIAG | |
208 | #endif | |
209 | ||
56523f12 | 210 | |
151ab83a WD |
211 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
212 | ||
14d0a02a | 213 | #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) |
6d0f6bcf | 214 | # define CONFIG_SYS_LOWBOOT 1 /* Boot low */ |
56523f12 WD |
215 | #endif |
216 | ||
217 | /* | |
218 | * Autobooting | |
219 | */ | |
220 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
221 | ||
81050926 | 222 | #define CONFIG_PREBOOT "echo;" \ |
4c4aca81 | 223 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
56523f12 WD |
224 | "echo" |
225 | ||
226 | #undef CONFIG_BOOTARGS | |
227 | ||
6d0f6bcf | 228 | #if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) |
78d620eb WD |
229 | # define ENV_UPDT \ |
230 | "update=protect off FFF00000 +${filesize};" \ | |
231 | "erase FFF00000 +${filesize};" \ | |
5078cce8 | 232 | "cp.b 200000 FFF00000 ${filesize};" \ |
78d620eb WD |
233 | "protect on FFF00000 +${filesize}\0" |
234 | #else /* default lowboot configuration */ | |
6d3bc9b8 | 235 | # define ENV_UPDT \ |
78d620eb WD |
236 | "update=protect off FC000000 +${filesize};" \ |
237 | "erase FC000000 +${filesize};" \ | |
6d3bc9b8 | 238 | "cp.b 200000 FC000000 ${filesize};" \ |
78d620eb WD |
239 | "protect on FC000000 +${filesize}\0" |
240 | #endif | |
5078cce8 | 241 | |
e1f601b5 | 242 | #if defined(CONFIG_TQM5200) |
6abaee42 | 243 | #define CUSTOM_ENV_SETTINGS \ |
e1f601b5 | 244 | "hostname=tqm5200\0" \ |
6abaee42 | 245 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
8f8416fa | 246 | "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ |
6abaee42 | 247 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" |
e1f601b5 | 248 | #elif defined(CONFIG_CAM5200) |
1636d1c8 | 249 | #define CUSTOM_ENV_SETTINGS \ |
6abaee42 RT |
250 | "bootfile=cam5200/uImage\0" \ |
251 | "u-boot=cam5200/u-boot.bin\0" \ | |
74de7aef | 252 | "setup=tftp 200000 cam5200/setup.img; source 200000\0" |
6abaee42 RT |
253 | #endif |
254 | ||
a5cc5555 MK |
255 | #if defined(CONFIG_TQM5200_B) |
256 | #define ENV_FLASH_LAYOUT \ | |
257 | "fdt_addr=FC100000\0" \ | |
258 | "kernel_addr=FC140000\0" \ | |
259 | "ramdisk_addr=FC600000\0" | |
5624d66a HS |
260 | #elif defined(CONFIG_CHARON) |
261 | #define ENV_FLASH_LAYOUT \ | |
262 | "fdt_addr=FDFC0000\0" \ | |
263 | "kernel_addr=FC0A0000\0" \ | |
264 | "ramdisk_addr=FC200000\0" | |
a5cc5555 MK |
265 | #else /* !CONFIG_TQM5200_B */ |
266 | #define ENV_FLASH_LAYOUT \ | |
267 | "fdt_addr=FC0A0000\0" \ | |
268 | "kernel_addr=FC0C0000\0" \ | |
269 | "ramdisk_addr=FC300000\0" | |
270 | #endif | |
271 | ||
81050926 | 272 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56523f12 | 273 | "netdev=eth0\0" \ |
e1f601b5 | 274 | "console=ttyPSC0\0" \ |
a5cc5555 | 275 | ENV_FLASH_LAYOUT \ |
d78791ae BS |
276 | "kernel_addr_r=400000\0" \ |
277 | "fdt_addr_r=600000\0" \ | |
89c02e2c | 278 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
56523f12 | 279 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
56523f12 | 280 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
281 | "nfsroot=${serverip}:${rootpath}\0" \ |
282 | "addip=setenv bootargs ${bootargs} " \ | |
283 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
284 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5078cce8 | 285 | "addcons=setenv bootargs ${bootargs} " \ |
8f8416fa | 286 | "console=${console},${baudrate}\0" \ |
98e69567 HS |
287 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
288 | "flash_self_old=sete console ttyS0; " \ | |
289 | "run ramargs addip addcons addmtd; " \ | |
fe126d8b | 290 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
e1f601b5 BS |
291 | "flash_self=run ramargs addip addcons;" \ |
292 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
293 | "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ | |
fe126d8b | 294 | "bootm ${kernel_addr}\0" \ |
e1f601b5 | 295 | "flash_nfs=run nfsargs addip addcons;" \ |
8f8416fa | 296 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
e1f601b5 BS |
297 | "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ |
298 | "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ | |
299 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
300 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
98e69567 | 301 | "run nfsargs addip addcons addmtd; " \ |
e1f601b5 | 302 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
6abaee42 | 303 | CUSTOM_ENV_SETTINGS \ |
5078cce8 WD |
304 | "load=tftp 200000 ${u-boot}\0" \ |
305 | ENV_UPDT \ | |
7e6bf358 | 306 | "" |
56523f12 WD |
307 | |
308 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
309 | ||
310 | /* | |
311 | * IPB Bus clocking configuration. | |
312 | */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
56523f12 | 314 | |
6d0f6bcf | 315 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) |
56523f12 WD |
316 | /* |
317 | * PCI Bus clocking configuration | |
318 | * | |
319 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 320 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of |
c99512d6 | 321 | * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
56523f12 | 322 | */ |
6d0f6bcf | 323 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
56523f12 WD |
324 | #endif |
325 | ||
326 | /* | |
327 | * I2C configuration | |
328 | */ | |
329 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
8f0b7cbe | 330 | #ifdef CONFIG_TQM5200_REV100 |
6d0f6bcf | 331 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ |
56523f12 | 332 | #else |
6d0f6bcf | 333 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
56523f12 WD |
334 | #endif |
335 | ||
336 | /* | |
337 | * I2C clock frequency | |
338 | * | |
339 | * Please notice, that the resulting clock frequency could differ from the | |
340 | * configured value. This is because the I2C clock is derived from system | |
341 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 342 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
56523f12 WD |
343 | * approximation allways lies below the configured value, never above. |
344 | */ | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
346 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
56523f12 WD |
347 | |
348 | /* | |
349 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
350 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
351 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
352 | * same configuration could be used. | |
353 | */ | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
355 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
356 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
357 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
56523f12 WD |
358 | |
359 | /* | |
360 | * HW-Monitor configuration on Mini-FAP | |
361 | */ | |
362 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 363 | #define CONFIG_SYS_I2C_HWMON_ADDR 0x2C |
56523f12 WD |
364 | #endif |
365 | ||
366 | /* List of I2C addresses to be verified by POST */ | |
56523f12 | 367 | #if defined (CONFIG_MINIFAP) |
60aaaa07 PT |
368 | #undef CONFIG_SYS_POST_I2C_ADDRS |
369 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
370 | CONFIG_SYS_I2C_HWMON_ADDR, \ | |
371 | CONFIG_SYS_I2C_SLAVE} | |
56523f12 WD |
372 | #endif |
373 | ||
374 | /* | |
375 | * Flash configuration | |
376 | */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
56523f12 | 378 | |
d9384de2 | 379 | #if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) |
6d0f6bcf | 380 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks |
7299712c | 381 | (= chip selects) */ |
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ |
383 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
384 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
385 | ||
386 | #define CONFIG_SYS_FLASH_ADDR0 0x555 | |
387 | #define CONFIG_SYS_FLASH_ADDR1 0x2AA | |
388 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ | |
389 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
d9384de2 MB |
390 | #else |
391 | /* use CFI flash driver */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 393 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
085ecde1 | 394 | #define CONFIG_FLASH_CFI_MTD /* with MTD support */ |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
396 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
d9384de2 | 397 | (= chip selects) */ |
6d0f6bcf | 398 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
d9384de2 | 399 | #endif |
7299712c | 400 | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
402 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
403 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
56523f12 | 404 | |
135ae006 | 405 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 406 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
5078cce8 | 407 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 408 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) |
45a212c4 | 409 | #else |
6d0f6bcf | 410 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
5078cce8 WD |
411 | #endif |
412 | ||
d534f5cc | 413 | /* Dynamic MTD partition support */ |
68d7d651 | 414 | #define CONFIG_CMD_MTDPARTS |
942556a9 | 415 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
259bff7c | 416 | #define MTDIDS_DEFAULT "nor0=fc000000.flash" |
5078cce8 | 417 | |
5624d66a | 418 | #if defined(CONFIG_STK52XX) |
5078cce8 | 419 | # if defined(CONFIG_TQM5200_B) |
6d0f6bcf | 420 | # if defined(CONFIG_SYS_LOWBOOT) |
259bff7c | 421 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \ |
a5cc5555 MK |
422 | "256k(dtb)," \ |
423 | "2304k(kernel)," \ | |
424 | "2560k(small-fs)," \ | |
45a212c4 | 425 | "2m(initrd)," \ |
5078cce8 WD |
426 | "8m(misc)," \ |
427 | "16m(big-fs)" | |
428 | # else /* highboot */ | |
259bff7c | 429 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\ |
5078cce8 WD |
430 | "3584k(small-fs)," \ |
431 | "2m(initrd)," \ | |
432 | "8m(misc)," \ | |
433 | "15m(big-fs)," \ | |
434 | "1m(firmware)" | |
6d0f6bcf | 435 | # endif /* CONFIG_SYS_LOWBOOT */ |
5078cce8 | 436 | # else /* !CONFIG_TQM5200_B */ |
259bff7c | 437 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
e1f601b5 BS |
438 | "128k(dtb)," \ |
439 | "2304k(kernel)," \ | |
d534f5cc WD |
440 | "2m(initrd)," \ |
441 | "4m(small-fs)," \ | |
5078cce8 | 442 | "8m(misc)," \ |
e1f601b5 | 443 | "15m(big-fs)" |
5078cce8 | 444 | # endif /* CONFIG_TQM5200_B */ |
135ae006 | 445 | #elif defined (CONFIG_CAM5200) |
259bff7c | 446 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\ |
5078cce8 | 447 | "1792k(kernel)," \ |
7299712c MB |
448 | "5632k(rootfs)," \ |
449 | "24m(home)" | |
5624d66a HS |
450 | #elif defined (CONFIG_CHARON) |
451 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ | |
452 | "1408k(kernel)," \ | |
453 | "2m(initrd)," \ | |
454 | "4m(small-fs)," \ | |
455 | "24320k(big-fs)," \ | |
456 | "256k(dts)" | |
6d3bc9b8 | 457 | #elif defined (CONFIG_FO300) |
259bff7c | 458 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
6d3bc9b8 MB |
459 | "1408k(kernel)," \ |
460 | "2m(initrd)," \ | |
461 | "4m(small-fs)," \ | |
462 | "8m(misc)," \ | |
463 | "16m(big-fs)" | |
5078cce8 WD |
464 | #else |
465 | # error "Unknown Carrier Board" | |
466 | #endif /* CONFIG_STK52XX */ | |
56523f12 WD |
467 | |
468 | /* | |
469 | * Environment settings | |
470 | */ | |
5a1aceb0 | 471 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 472 | #define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ |
78d620eb | 473 | #if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) |
0e8d1586 | 474 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 475 | #else |
0e8d1586 | 476 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
5078cce8 | 477 | #endif /* CONFIG_TQM5200_B */ |
0e8d1586 JCPV |
478 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
479 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
56523f12 WD |
480 | |
481 | /* | |
482 | * Memory map | |
483 | */ | |
6d0f6bcf JCPV |
484 | #define CONFIG_SYS_MBAR 0xF0000000 |
485 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
486 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
56523f12 WD |
487 | |
488 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 489 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
56523f12 WD |
490 | #ifdef CONFIG_POST |
491 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 492 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
56523f12 | 493 | #else |
553f0982 | 494 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
56523f12 WD |
495 | #endif |
496 | ||
497 | ||
25ddd1fb | 498 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 499 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
56523f12 | 500 | |
14d0a02a | 501 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
502 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
503 | # define CONFIG_SYS_RAMBOOT 1 | |
56523f12 WD |
504 | #endif |
505 | ||
135ae006 | 506 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 507 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5078cce8 | 508 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 509 | # define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
45a212c4 | 510 | #else |
6d0f6bcf | 511 | # define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
5078cce8 WD |
512 | #endif |
513 | ||
6d0f6bcf JCPV |
514 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
515 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
56523f12 WD |
516 | |
517 | /* | |
518 | * Ethernet configuration | |
519 | */ | |
520 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 521 | #define CONFIG_MPC5xxx_FEC_MII100 |
56523f12 | 522 | /* |
86321fc1 | 523 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
56523f12 | 524 | */ |
86321fc1 | 525 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
56523f12 WD |
526 | #define CONFIG_PHY_ADDR 0x00 |
527 | ||
528 | /* | |
529 | * GPIO configuration | |
530 | * | |
7299712c MB |
531 | * use CS1: Bit 0 (mask: 0x80000000): |
532 | * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). | |
56523f12 | 533 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
7299712c MB |
534 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. |
535 | * SPI on PSC3 according to PSC3 setting. Use for CAM5200. | |
536 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
537 | * Use for REV200 STK52XX boards and FO300 boards. Do not use | |
538 | * with REV100 modules (because, there I2C1 is used as I2C bus). | |
539 | * use ATA: Bits 6-7 (mask 0x03000000): | |
540 | * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. | |
541 | * Use for CAM5200 board. | |
542 | * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. | |
543 | * use PSC6: Bits 9-11 (mask 0x00700000): | |
544 | * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as | |
545 | * UART, CODEC or IrDA. | |
546 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to | |
547 | * enable extended POST tests. | |
548 | * Use for MINI-FAP and TQM5200_IB boards. | |
549 | * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. | |
550 | * Extended POST test is not available. | |
551 | * Use for STK52xx, FO300 and CAM5200 boards. | |
95c44ec4 DZ |
552 | * WARNING: When the extended POST is enabled, these bits will |
553 | * be overridden by this code as GPIOs! | |
7299712c MB |
554 | * use PCI_DIS: Bit 16 (mask 0x00008000): |
555 | * 1 -> disable PCI controller (on CAM5200 board). | |
556 | * use USB: Bits 18-19 (mask 0x00003000): | |
557 | * 10 -> two UARTs (on FO300 and CAM5200). | |
558 | * use PSC3: Bits 20-23 (mask: 0x00000f00): | |
559 | * 0000 -> All PSC3 pins are GPIOs. | |
560 | * 1100 -> UART/SPI (on FO300 board). | |
561 | * 0100 -> UART (on CAM5200 board). | |
562 | * use PSC2: Bits 25:27 (mask: 0x00000030): | |
563 | * 000 -> All PSC2 pins are GPIOs. | |
564 | * 100 -> UART (on CAM5200 board). | |
565 | * 001 -> CAN1/2 on PSC2 pins. | |
95c44ec4 | 566 | * Use for REV100 STK52xx boards |
7299712c MB |
567 | * 01x -> Use AC97 (on FO300 board). |
568 | * use PSC1: Bits 29-31 (mask: 0x00000007): | |
569 | * 100 -> UART (on all boards). | |
56523f12 | 570 | */ |
98e69567 | 571 | #if !defined(CONFIG_SYS_GPS_PORT_CONFIG) |
56523f12 | 572 | #if defined (CONFIG_MINIFAP) |
6d0f6bcf | 573 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 |
7e6bf358 | 574 | #elif defined (CONFIG_STK52XX) |
83e40ba7 | 575 | # if defined (CONFIG_STK52XX_REV100) |
6d0f6bcf | 576 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
83e40ba7 WD |
577 | # else /* STK52xx REV200 and above */ |
578 | # if defined (CONFIG_TQM5200_REV100) | |
579 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
580 | # else/* TQM5200 REV200 and above */ | |
6d0f6bcf | 581 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 |
83e40ba7 | 582 | # endif |
8f0b7cbe | 583 | # endif |
6d3bc9b8 | 584 | #elif defined (CONFIG_FO300) |
6d0f6bcf | 585 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 |
7299712c | 586 | #elif defined (CONFIG_CAM5200) |
6d0f6bcf | 587 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 |
83e40ba7 | 588 | #else /* TMQ5200 Inbetriebnahme-Board */ |
6d0f6bcf | 589 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 |
56523f12 | 590 | #endif |
98e69567 | 591 | #endif |
56523f12 WD |
592 | |
593 | /* | |
594 | * RTC configuration | |
595 | */ | |
4f562f14 WD |
596 | #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) |
597 | # define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
598 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
599 | # define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base | |
edd0b509 | 600 | year */ |
4f562f14 WD |
601 | #else |
602 | # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
603 | #endif | |
56523f12 WD |
604 | |
605 | /* | |
606 | * Miscellaneous configurable options | |
607 | */ | |
6d0f6bcf | 608 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5078cce8 | 609 | |
2751a95a | 610 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf | 611 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
5078cce8 | 612 | |
6d0f6bcf | 613 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
2694690e | 614 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 615 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
2694690e JL |
616 | #endif |
617 | ||
618 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 619 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
56523f12 | 620 | #else |
6d0f6bcf | 621 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
56523f12 | 622 | #endif |
6d0f6bcf JCPV |
623 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
624 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
625 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
56523f12 WD |
626 | |
627 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 628 | #define CONFIG_SYS_ALT_MEMTEST |
56523f12 | 629 | |
6d0f6bcf JCPV |
630 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
631 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
56523f12 | 632 | |
6d0f6bcf | 633 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
56523f12 | 634 | |
56523f12 | 635 | /* |
a1aa0bb5 | 636 | * Enable loopw command. |
56523f12 WD |
637 | */ |
638 | #define CONFIG_LOOPW | |
639 | ||
640 | /* | |
641 | * Various low-level settings | |
642 | */ | |
6d0f6bcf JCPV |
643 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
644 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
56523f12 | 645 | |
6d0f6bcf JCPV |
646 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
647 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
648 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
649 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
56523f12 | 650 | #else |
6d0f6bcf | 651 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
56523f12 | 652 | #endif |
6d0f6bcf JCPV |
653 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
654 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
56523f12 | 655 | |
7e6bf358 | 656 | #define CONFIG_LAST_STAGE_INIT |
7e6bf358 | 657 | |
56523f12 WD |
658 | /* |
659 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
660 | * for SDRAM autosizing. | |
661 | */ | |
6d0f6bcf JCPV |
662 | #define CONFIG_SYS_CS2_START 0xE5000000 |
663 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
664 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
56523f12 WD |
665 | |
666 | /* | |
667 | * Grafic controller - Do not map below 2 GB in address space, because this | |
668 | * area is used for SDRAM autosizing. | |
669 | */ | |
8f0b7cbe | 670 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
671 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
672 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
673 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
674 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
56523f12 | 675 | |
6d0f6bcf JCPV |
676 | #define CONFIG_SYS_CS_BURST 0x00000000 |
677 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
56523f12 | 678 | |
7299712c | 679 | #if defined(CONFIG_CAM5200) |
6d0f6bcf JCPV |
680 | #define CONFIG_SYS_CS4_START 0xB0000000 |
681 | #define CONFIG_SYS_CS4_SIZE 0x00010000 | |
682 | #define CONFIG_SYS_CS4_CFG 0x01019C10 | |
7299712c | 683 | |
6d0f6bcf JCPV |
684 | #define CONFIG_SYS_CS5_START 0xD0000000 |
685 | #define CONFIG_SYS_CS5_SIZE 0x01208000 | |
686 | #define CONFIG_SYS_CS5_CFG 0x1414BF10 | |
7299712c MB |
687 | #endif |
688 | ||
6d0f6bcf | 689 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
56523f12 WD |
690 | |
691 | /*----------------------------------------------------------------------- | |
692 | * USB stuff | |
693 | *----------------------------------------------------------------------- | |
694 | */ | |
695 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
696 | #define CONFIG_USB_CONFIG 0x00001000 | |
697 | ||
698 | /*----------------------------------------------------------------------- | |
699 | * IDE/ATA stuff Supports IDE harddisk | |
700 | *----------------------------------------------------------------------- | |
701 | */ | |
702 | ||
81050926 | 703 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
56523f12 | 704 | |
81050926 WD |
705 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
706 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
56523f12 | 707 | |
81050926 | 708 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
56523f12 WD |
709 | #define CONFIG_IDE_PREINIT |
710 | ||
6d0f6bcf JCPV |
711 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
712 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
56523f12 | 713 | |
6d0f6bcf | 714 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
56523f12 | 715 | |
6d0f6bcf | 716 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
56523f12 | 717 | |
95c44ec4 | 718 | /* Offset for data I/O */ |
6d0f6bcf | 719 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
56523f12 | 720 | |
95c44ec4 | 721 | /* Offset for normal register accesses */ |
6d0f6bcf | 722 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
56523f12 | 723 | |
95c44ec4 | 724 | /* Offset for alternate registers */ |
6d0f6bcf | 725 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
56523f12 | 726 | |
95c44ec4 | 727 | /* Interval between registers */ |
6d0f6bcf | 728 | #define CONFIG_SYS_ATA_STRIDE 4 |
56523f12 | 729 | |
33af3e66 | 730 | /* Support ATAPI devices */ |
95c44ec4 | 731 | #define CONFIG_ATAPI 1 |
33af3e66 | 732 | |
8f8416fa BS |
733 | /*----------------------------------------------------------------------- |
734 | * Open firmware flat tree support | |
735 | *----------------------------------------------------------------------- | |
736 | */ | |
cf2817a8 | 737 | #define CONFIG_OF_LIBFDT 1 |
8f8416fa BS |
738 | #define CONFIG_OF_BOARD_SETUP 1 |
739 | ||
8f8416fa BS |
740 | #define OF_CPU "PowerPC,5200@0" |
741 | #define OF_SOC "soc5200@f0000000" | |
742 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
743 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
744 | ||
56523f12 | 745 | #endif /* __CONFIG_H */ |