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56523f12 | 1 | /* |
69445d6c | 2 | * (C) Copyright 2003-2014 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
45a212c4 | 5 | * (C) Copyright 2004-2006 |
56523f12 WD |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
56523f12 WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
56523f12 WD |
14 | /* |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5078cce8 WD |
20 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
21 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
56523f12 | 22 | |
2ae18241 WD |
23 | /* |
24 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
25 | * 0xFC000000 boot low (standard configuration with room for | |
26 | * max 64 MByte Flash ROM) | |
27 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
28 | * 0x00100000 boot from RAM (for testing only) | |
29 | */ | |
30 | #ifndef CONFIG_SYS_TEXT_BASE | |
31 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
32 | #endif | |
33 | ||
5196a7a0 | 34 | /* On a Cameron or on a FO300 board or ... */ |
98e69567 HS |
35 | #if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \ |
36 | && !defined(CONFIG_FO300) | |
5078cce8 WD |
37 | #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ |
38 | #endif | |
39 | ||
6d0f6bcf | 40 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
56523f12 | 41 | |
31d82672 BB |
42 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
43 | ||
56523f12 WD |
44 | /* |
45 | * Serial console configuration | |
46 | */ | |
5078cce8 | 47 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
6d0f6bcf | 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
bef92e21 | 49 | #define CONFIG_BOOTCOUNT_LIMIT 1 |
56523f12 | 50 | |
6d3bc9b8 | 51 | #ifdef CONFIG_FO300 |
6d0f6bcf | 52 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ |
ddde6b7c | 53 | #define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ |
6d3bc9b8 MB |
54 | #if 0 |
55 | #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ | |
56 | /* switch is closed */ | |
57 | #endif | |
58 | ||
59 | #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ | |
60 | /* switch is open */ | |
5196a7a0 | 61 | #endif /* CONFIG_FO300 */ |
6d3bc9b8 | 62 | |
98e69567 | 63 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
7e6bf358 WD |
64 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ |
65 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
66 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 67 | #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
7e6bf358 WD |
68 | #define CONFIG_BOARD_EARLY_INIT_R |
69 | #endif /* CONFIG_STK52XX */ | |
56523f12 | 70 | |
56523f12 WD |
71 | /* |
72 | * PCI Mapping: | |
73 | * 0x40000000 - 0x4fffffff - PCI Memory | |
74 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
75 | */ | |
98e69567 | 76 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
31a64923 | 77 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
56523f12 WD |
78 | |
79 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
80 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
81 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
82 | ||
83 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
84 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
85 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
86 | ||
cd65a3dc | 87 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 88 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
56523f12 | 89 | #define CONFIG_NS8382X 1 |
83e40ba7 | 90 | #endif /* CONFIG_STK52XX */ |
56523f12 | 91 | |
8f0b7cbe WD |
92 | /* |
93 | * Video console | |
94 | */ | |
5078cce8 | 95 | #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ |
8f0b7cbe WD |
96 | #define CONFIG_VIDEO_SM501 |
97 | #define CONFIG_VIDEO_SM501_32BPP | |
8f0b7cbe | 98 | #define CONFIG_VIDEO_LOGO |
6d3bc9b8 MB |
99 | |
100 | #ifndef CONFIG_FO300 | |
6d3bc9b8 MB |
101 | #else |
102 | #define CONFIG_VIDEO_BMP_LOGO | |
103 | #endif | |
104 | ||
8f0b7cbe | 105 | #define CONFIG_SPLASH_SCREEN |
6d3bc9b8 | 106 | #endif /* #ifndef CONFIG_TQM5200S */ |
56523f12 | 107 | |
56523f12 | 108 | /* Partitions */ |
56523f12 WD |
109 | |
110 | /* USB */ | |
98e69567 HS |
111 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
112 | defined(CONFIG_STK52XX) | |
7b59b3c7 | 113 | #define CONFIG_USB_OHCI_NEW |
6d0f6bcf | 114 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
53e336e9 | 115 | |
6d0f6bcf JCPV |
116 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
117 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
118 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
119 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
120 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 121 | |
56523f12 WD |
122 | #endif |
123 | ||
135ae006 | 124 | #ifndef CONFIG_CAM5200 |
56523f12 | 125 | /* POST support */ |
6d0f6bcf | 126 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
eb5ba3ae | 127 | CONFIG_SYS_POST_CPU) |
5078cce8 | 128 | #endif |
56523f12 WD |
129 | |
130 | #ifdef CONFIG_POST | |
56523f12 WD |
131 | /* preserve space for the post_word at end of on-chip SRAM */ |
132 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
56523f12 WD |
133 | #endif |
134 | ||
56523f12 | 135 | /* |
a1aa0bb5 | 136 | * BOOTP options |
56523f12 | 137 | */ |
a1aa0bb5 JL |
138 | #define CONFIG_BOOTP_BOOTFILESIZE |
139 | #define CONFIG_BOOTP_BOOTPATH | |
140 | #define CONFIG_BOOTP_GATEWAY | |
141 | #define CONFIG_BOOTP_HOSTNAME | |
142 | ||
56523f12 | 143 | /* |
2694690e | 144 | * Command line configuration. |
56523f12 | 145 | */ |
2694690e | 146 | #define CONFIG_CMD_REGINFO |
2694690e | 147 | |
2694690e | 148 | #ifdef CONFIG_PCI |
2b2a587d | 149 | #define CONFIG_CMD_PCI |
f33fca22 | 150 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2694690e JL |
151 | #endif |
152 | ||
98e69567 HS |
153 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
154 | defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) | |
2694690e JL |
155 | #endif |
156 | ||
98e69567 HS |
157 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
158 | defined(CONFIG_STK52XX) | |
2694690e JL |
159 | #define CONFIG_CFG_USB |
160 | #define CONFIG_CFG_FAT | |
161 | #endif | |
162 | ||
151ab83a WD |
163 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
164 | ||
14d0a02a | 165 | #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) |
6d0f6bcf | 166 | # define CONFIG_SYS_LOWBOOT 1 /* Boot low */ |
56523f12 WD |
167 | #endif |
168 | ||
169 | /* | |
170 | * Autobooting | |
171 | */ | |
56523f12 | 172 | |
81050926 | 173 | #define CONFIG_PREBOOT "echo;" \ |
4c4aca81 | 174 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
56523f12 WD |
175 | "echo" |
176 | ||
177 | #undef CONFIG_BOOTARGS | |
178 | ||
6d0f6bcf | 179 | #if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) |
78d620eb WD |
180 | # define ENV_UPDT \ |
181 | "update=protect off FFF00000 +${filesize};" \ | |
182 | "erase FFF00000 +${filesize};" \ | |
5078cce8 | 183 | "cp.b 200000 FFF00000 ${filesize};" \ |
78d620eb WD |
184 | "protect on FFF00000 +${filesize}\0" |
185 | #else /* default lowboot configuration */ | |
6d3bc9b8 | 186 | # define ENV_UPDT \ |
78d620eb WD |
187 | "update=protect off FC000000 +${filesize};" \ |
188 | "erase FC000000 +${filesize};" \ | |
6d3bc9b8 | 189 | "cp.b 200000 FC000000 ${filesize};" \ |
78d620eb WD |
190 | "protect on FC000000 +${filesize}\0" |
191 | #endif | |
5078cce8 | 192 | |
e1f601b5 | 193 | #if defined(CONFIG_TQM5200) |
6abaee42 | 194 | #define CUSTOM_ENV_SETTINGS \ |
e1f601b5 | 195 | "hostname=tqm5200\0" \ |
6abaee42 | 196 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
8f8416fa | 197 | "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ |
6abaee42 | 198 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" |
e1f601b5 | 199 | #elif defined(CONFIG_CAM5200) |
1636d1c8 | 200 | #define CUSTOM_ENV_SETTINGS \ |
6abaee42 RT |
201 | "bootfile=cam5200/uImage\0" \ |
202 | "u-boot=cam5200/u-boot.bin\0" \ | |
74de7aef | 203 | "setup=tftp 200000 cam5200/setup.img; source 200000\0" |
6abaee42 RT |
204 | #endif |
205 | ||
a5cc5555 MK |
206 | #if defined(CONFIG_TQM5200_B) |
207 | #define ENV_FLASH_LAYOUT \ | |
208 | "fdt_addr=FC100000\0" \ | |
209 | "kernel_addr=FC140000\0" \ | |
210 | "ramdisk_addr=FC600000\0" | |
5624d66a HS |
211 | #elif defined(CONFIG_CHARON) |
212 | #define ENV_FLASH_LAYOUT \ | |
213 | "fdt_addr=FDFC0000\0" \ | |
214 | "kernel_addr=FC0A0000\0" \ | |
215 | "ramdisk_addr=FC200000\0" | |
a5cc5555 MK |
216 | #else /* !CONFIG_TQM5200_B */ |
217 | #define ENV_FLASH_LAYOUT \ | |
218 | "fdt_addr=FC0A0000\0" \ | |
219 | "kernel_addr=FC0C0000\0" \ | |
220 | "ramdisk_addr=FC300000\0" | |
221 | #endif | |
222 | ||
81050926 | 223 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56523f12 | 224 | "netdev=eth0\0" \ |
e1f601b5 | 225 | "console=ttyPSC0\0" \ |
a5cc5555 | 226 | ENV_FLASH_LAYOUT \ |
d78791ae BS |
227 | "kernel_addr_r=400000\0" \ |
228 | "fdt_addr_r=600000\0" \ | |
89c02e2c | 229 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
56523f12 | 230 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
56523f12 | 231 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
232 | "nfsroot=${serverip}:${rootpath}\0" \ |
233 | "addip=setenv bootargs ${bootargs} " \ | |
234 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
235 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5078cce8 | 236 | "addcons=setenv bootargs ${bootargs} " \ |
8f8416fa | 237 | "console=${console},${baudrate}\0" \ |
98e69567 HS |
238 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
239 | "flash_self_old=sete console ttyS0; " \ | |
240 | "run ramargs addip addcons addmtd; " \ | |
fe126d8b | 241 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
e1f601b5 BS |
242 | "flash_self=run ramargs addip addcons;" \ |
243 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
244 | "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ | |
fe126d8b | 245 | "bootm ${kernel_addr}\0" \ |
e1f601b5 | 246 | "flash_nfs=run nfsargs addip addcons;" \ |
8f8416fa | 247 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
e1f601b5 BS |
248 | "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ |
249 | "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ | |
250 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
251 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
98e69567 | 252 | "run nfsargs addip addcons addmtd; " \ |
e1f601b5 | 253 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
6abaee42 | 254 | CUSTOM_ENV_SETTINGS \ |
5078cce8 WD |
255 | "load=tftp 200000 ${u-boot}\0" \ |
256 | ENV_UPDT \ | |
7e6bf358 | 257 | "" |
56523f12 WD |
258 | |
259 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
260 | ||
261 | /* | |
262 | * IPB Bus clocking configuration. | |
263 | */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
56523f12 | 265 | |
6d0f6bcf | 266 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) |
56523f12 WD |
267 | /* |
268 | * PCI Bus clocking configuration | |
269 | * | |
270 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 271 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of |
c99512d6 | 272 | * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
56523f12 | 273 | */ |
6d0f6bcf | 274 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
56523f12 WD |
275 | #endif |
276 | ||
56523f12 WD |
277 | /* |
278 | * Flash configuration | |
279 | */ | |
6d0f6bcf | 280 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
56523f12 | 281 | |
d9384de2 | 282 | #if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) |
6d0f6bcf | 283 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks |
7299712c | 284 | (= chip selects) */ |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ |
286 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
287 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
288 | ||
289 | #define CONFIG_SYS_FLASH_ADDR0 0x555 | |
290 | #define CONFIG_SYS_FLASH_ADDR1 0x2AA | |
291 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ | |
292 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
d9384de2 MB |
293 | #else |
294 | /* use CFI flash driver */ | |
6d0f6bcf | 295 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 296 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
085ecde1 | 297 | #define CONFIG_FLASH_CFI_MTD /* with MTD support */ |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
299 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
d9384de2 | 300 | (= chip selects) */ |
6d0f6bcf | 301 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
d9384de2 | 302 | #endif |
7299712c | 303 | |
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
305 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
306 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
56523f12 | 307 | |
135ae006 | 308 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 309 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
5078cce8 | 310 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 311 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) |
45a212c4 | 312 | #else |
6d0f6bcf | 313 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
5078cce8 WD |
314 | #endif |
315 | ||
d534f5cc | 316 | /* Dynamic MTD partition support */ |
68d7d651 | 317 | #define CONFIG_CMD_MTDPARTS |
942556a9 | 318 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
259bff7c | 319 | #define MTDIDS_DEFAULT "nor0=fc000000.flash" |
5078cce8 | 320 | |
5624d66a | 321 | #if defined(CONFIG_STK52XX) |
5078cce8 | 322 | # if defined(CONFIG_TQM5200_B) |
6d0f6bcf | 323 | # if defined(CONFIG_SYS_LOWBOOT) |
259bff7c | 324 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \ |
a5cc5555 MK |
325 | "256k(dtb)," \ |
326 | "2304k(kernel)," \ | |
327 | "2560k(small-fs)," \ | |
45a212c4 | 328 | "2m(initrd)," \ |
5078cce8 WD |
329 | "8m(misc)," \ |
330 | "16m(big-fs)" | |
331 | # else /* highboot */ | |
259bff7c | 332 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\ |
5078cce8 WD |
333 | "3584k(small-fs)," \ |
334 | "2m(initrd)," \ | |
335 | "8m(misc)," \ | |
336 | "15m(big-fs)," \ | |
337 | "1m(firmware)" | |
6d0f6bcf | 338 | # endif /* CONFIG_SYS_LOWBOOT */ |
5078cce8 | 339 | # else /* !CONFIG_TQM5200_B */ |
259bff7c | 340 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
e1f601b5 BS |
341 | "128k(dtb)," \ |
342 | "2304k(kernel)," \ | |
d534f5cc WD |
343 | "2m(initrd)," \ |
344 | "4m(small-fs)," \ | |
5078cce8 | 345 | "8m(misc)," \ |
e1f601b5 | 346 | "15m(big-fs)" |
5078cce8 | 347 | # endif /* CONFIG_TQM5200_B */ |
135ae006 | 348 | #elif defined (CONFIG_CAM5200) |
259bff7c | 349 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\ |
5078cce8 | 350 | "1792k(kernel)," \ |
7299712c MB |
351 | "5632k(rootfs)," \ |
352 | "24m(home)" | |
5624d66a HS |
353 | #elif defined (CONFIG_CHARON) |
354 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ | |
355 | "1408k(kernel)," \ | |
356 | "2m(initrd)," \ | |
357 | "4m(small-fs)," \ | |
358 | "24320k(big-fs)," \ | |
359 | "256k(dts)" | |
6d3bc9b8 | 360 | #elif defined (CONFIG_FO300) |
259bff7c | 361 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
6d3bc9b8 MB |
362 | "1408k(kernel)," \ |
363 | "2m(initrd)," \ | |
364 | "4m(small-fs)," \ | |
365 | "8m(misc)," \ | |
366 | "16m(big-fs)" | |
5078cce8 WD |
367 | #else |
368 | # error "Unknown Carrier Board" | |
369 | #endif /* CONFIG_STK52XX */ | |
56523f12 WD |
370 | |
371 | /* | |
372 | * Environment settings | |
373 | */ | |
5a1aceb0 | 374 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 375 | #define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ |
78d620eb | 376 | #if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) |
0e8d1586 | 377 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 378 | #else |
0e8d1586 | 379 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
5078cce8 | 380 | #endif /* CONFIG_TQM5200_B */ |
0e8d1586 JCPV |
381 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
382 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
56523f12 WD |
383 | |
384 | /* | |
385 | * Memory map | |
386 | */ | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_MBAR 0xF0000000 |
388 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
389 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
56523f12 WD |
390 | |
391 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
56523f12 WD |
393 | #ifdef CONFIG_POST |
394 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 395 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
56523f12 | 396 | #else |
553f0982 | 397 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
56523f12 WD |
398 | #endif |
399 | ||
25ddd1fb | 400 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 401 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
56523f12 | 402 | |
14d0a02a | 403 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
404 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
405 | # define CONFIG_SYS_RAMBOOT 1 | |
56523f12 WD |
406 | #endif |
407 | ||
135ae006 | 408 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 409 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5078cce8 | 410 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 411 | # define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
45a212c4 | 412 | #else |
6d0f6bcf | 413 | # define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
5078cce8 WD |
414 | #endif |
415 | ||
6d0f6bcf JCPV |
416 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
417 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
56523f12 WD |
418 | |
419 | /* | |
420 | * Ethernet configuration | |
421 | */ | |
422 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 423 | #define CONFIG_MPC5xxx_FEC_MII100 |
56523f12 | 424 | /* |
86321fc1 | 425 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
56523f12 | 426 | */ |
86321fc1 | 427 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
56523f12 WD |
428 | #define CONFIG_PHY_ADDR 0x00 |
429 | ||
430 | /* | |
431 | * GPIO configuration | |
432 | * | |
7299712c MB |
433 | * use CS1: Bit 0 (mask: 0x80000000): |
434 | * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). | |
56523f12 | 435 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
7299712c MB |
436 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. |
437 | * SPI on PSC3 according to PSC3 setting. Use for CAM5200. | |
438 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
439 | * Use for REV200 STK52XX boards and FO300 boards. Do not use | |
440 | * with REV100 modules (because, there I2C1 is used as I2C bus). | |
441 | * use ATA: Bits 6-7 (mask 0x03000000): | |
442 | * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. | |
443 | * Use for CAM5200 board. | |
444 | * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. | |
445 | * use PSC6: Bits 9-11 (mask 0x00700000): | |
446 | * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as | |
447 | * UART, CODEC or IrDA. | |
448 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to | |
449 | * enable extended POST tests. | |
450 | * Use for MINI-FAP and TQM5200_IB boards. | |
451 | * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. | |
452 | * Extended POST test is not available. | |
453 | * Use for STK52xx, FO300 and CAM5200 boards. | |
95c44ec4 DZ |
454 | * WARNING: When the extended POST is enabled, these bits will |
455 | * be overridden by this code as GPIOs! | |
7299712c MB |
456 | * use PCI_DIS: Bit 16 (mask 0x00008000): |
457 | * 1 -> disable PCI controller (on CAM5200 board). | |
458 | * use USB: Bits 18-19 (mask 0x00003000): | |
459 | * 10 -> two UARTs (on FO300 and CAM5200). | |
460 | * use PSC3: Bits 20-23 (mask: 0x00000f00): | |
461 | * 0000 -> All PSC3 pins are GPIOs. | |
462 | * 1100 -> UART/SPI (on FO300 board). | |
463 | * 0100 -> UART (on CAM5200 board). | |
464 | * use PSC2: Bits 25:27 (mask: 0x00000030): | |
465 | * 000 -> All PSC2 pins are GPIOs. | |
466 | * 100 -> UART (on CAM5200 board). | |
467 | * 001 -> CAN1/2 on PSC2 pins. | |
95c44ec4 | 468 | * Use for REV100 STK52xx boards |
7299712c MB |
469 | * 01x -> Use AC97 (on FO300 board). |
470 | * use PSC1: Bits 29-31 (mask: 0x00000007): | |
471 | * 100 -> UART (on all boards). | |
56523f12 | 472 | */ |
98e69567 | 473 | #if !defined(CONFIG_SYS_GPS_PORT_CONFIG) |
56523f12 | 474 | #if defined (CONFIG_MINIFAP) |
6d0f6bcf | 475 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 |
7e6bf358 | 476 | #elif defined (CONFIG_STK52XX) |
83e40ba7 | 477 | # if defined (CONFIG_STK52XX_REV100) |
6d0f6bcf | 478 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
83e40ba7 WD |
479 | # else /* STK52xx REV200 and above */ |
480 | # if defined (CONFIG_TQM5200_REV100) | |
481 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
482 | # else/* TQM5200 REV200 and above */ | |
6d0f6bcf | 483 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 |
83e40ba7 | 484 | # endif |
8f0b7cbe | 485 | # endif |
6d3bc9b8 | 486 | #elif defined (CONFIG_FO300) |
6d0f6bcf | 487 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 |
7299712c | 488 | #elif defined (CONFIG_CAM5200) |
6d0f6bcf | 489 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 |
83e40ba7 | 490 | #else /* TMQ5200 Inbetriebnahme-Board */ |
6d0f6bcf | 491 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 |
56523f12 | 492 | #endif |
98e69567 | 493 | #endif |
56523f12 | 494 | |
56523f12 WD |
495 | /* |
496 | * Miscellaneous configurable options | |
497 | */ | |
6d0f6bcf | 498 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5078cce8 | 499 | |
2751a95a | 500 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5078cce8 | 501 | |
6d0f6bcf | 502 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
2694690e | 503 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 504 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
2694690e JL |
505 | #endif |
506 | ||
507 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 508 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
56523f12 | 509 | #else |
6d0f6bcf | 510 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
56523f12 | 511 | #endif |
6d0f6bcf JCPV |
512 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
513 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
514 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
56523f12 WD |
515 | |
516 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 517 | #define CONFIG_SYS_ALT_MEMTEST |
56523f12 | 518 | |
6d0f6bcf JCPV |
519 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
520 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
56523f12 | 521 | |
6d0f6bcf | 522 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
56523f12 | 523 | |
56523f12 WD |
524 | /* |
525 | * Various low-level settings | |
526 | */ | |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
528 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
56523f12 | 529 | |
6d0f6bcf JCPV |
530 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
531 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
532 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
533 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
56523f12 | 534 | #else |
6d0f6bcf | 535 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
56523f12 | 536 | #endif |
6d0f6bcf JCPV |
537 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
538 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
56523f12 | 539 | |
7e6bf358 | 540 | #define CONFIG_LAST_STAGE_INIT |
7e6bf358 | 541 | |
56523f12 WD |
542 | /* |
543 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
544 | * for SDRAM autosizing. | |
545 | */ | |
6d0f6bcf JCPV |
546 | #define CONFIG_SYS_CS2_START 0xE5000000 |
547 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
548 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
56523f12 WD |
549 | |
550 | /* | |
551 | * Grafic controller - Do not map below 2 GB in address space, because this | |
552 | * area is used for SDRAM autosizing. | |
553 | */ | |
8f0b7cbe | 554 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
555 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
556 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
557 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
558 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
56523f12 | 559 | |
6d0f6bcf JCPV |
560 | #define CONFIG_SYS_CS_BURST 0x00000000 |
561 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
56523f12 | 562 | |
7299712c | 563 | #if defined(CONFIG_CAM5200) |
6d0f6bcf JCPV |
564 | #define CONFIG_SYS_CS4_START 0xB0000000 |
565 | #define CONFIG_SYS_CS4_SIZE 0x00010000 | |
566 | #define CONFIG_SYS_CS4_CFG 0x01019C10 | |
7299712c | 567 | |
6d0f6bcf JCPV |
568 | #define CONFIG_SYS_CS5_START 0xD0000000 |
569 | #define CONFIG_SYS_CS5_SIZE 0x01208000 | |
570 | #define CONFIG_SYS_CS5_CFG 0x1414BF10 | |
7299712c MB |
571 | #endif |
572 | ||
6d0f6bcf | 573 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
56523f12 WD |
574 | |
575 | /*----------------------------------------------------------------------- | |
576 | * USB stuff | |
577 | *----------------------------------------------------------------------- | |
578 | */ | |
579 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
580 | #define CONFIG_USB_CONFIG 0x00001000 | |
581 | ||
582 | /*----------------------------------------------------------------------- | |
583 | * IDE/ATA stuff Supports IDE harddisk | |
584 | *----------------------------------------------------------------------- | |
585 | */ | |
586 | ||
81050926 | 587 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
56523f12 | 588 | |
81050926 WD |
589 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
590 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
56523f12 | 591 | |
81050926 | 592 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
56523f12 WD |
593 | #define CONFIG_IDE_PREINIT |
594 | ||
6d0f6bcf JCPV |
595 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
596 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
56523f12 | 597 | |
6d0f6bcf | 598 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
56523f12 | 599 | |
6d0f6bcf | 600 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
56523f12 | 601 | |
95c44ec4 | 602 | /* Offset for data I/O */ |
6d0f6bcf | 603 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
56523f12 | 604 | |
95c44ec4 | 605 | /* Offset for normal register accesses */ |
6d0f6bcf | 606 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
56523f12 | 607 | |
95c44ec4 | 608 | /* Offset for alternate registers */ |
6d0f6bcf | 609 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
56523f12 | 610 | |
95c44ec4 | 611 | /* Interval between registers */ |
6d0f6bcf | 612 | #define CONFIG_SYS_ATA_STRIDE 4 |
56523f12 | 613 | |
33af3e66 | 614 | /* Support ATAPI devices */ |
95c44ec4 | 615 | #define CONFIG_ATAPI 1 |
33af3e66 | 616 | |
8f8416fa BS |
617 | /*----------------------------------------------------------------------- |
618 | * Open firmware flat tree support | |
619 | *----------------------------------------------------------------------- | |
620 | */ | |
8f8416fa BS |
621 | #define OF_CPU "PowerPC,5200@0" |
622 | #define OF_SOC "soc5200@f0000000" | |
623 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
624 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
625 | ||
56523f12 | 626 | #endif /* __CONFIG_H */ |