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Convert CONFIG_CMD_BMP to Kconfig
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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
56523f12
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
56523f12
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
56523f12
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
5078cce8 47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
6d0f6bcf 48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 49#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 50
6d3bc9b8 51#ifdef CONFIG_FO300
6d0f6bcf 52#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
ddde6b7c 53#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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54#if 0
55#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
56 /* switch is closed */
57#endif
58
59#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
60 /* switch is open */
5196a7a0 61#endif /* CONFIG_FO300 */
6d3bc9b8 62
98e69567 63#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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64#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
65#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
66#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 67#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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68#define CONFIG_BOARD_EARLY_INIT_R
69#endif /* CONFIG_STK52XX */
56523f12 70
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71/*
72 * PCI Mapping:
73 * 0x40000000 - 0x4fffffff - PCI Memory
74 * 0x50000000 - 0x50ffffff - PCI IO Space
75 */
98e69567 76#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
31a64923 77/* #define CONFIG_PCI_SCAN_SHOW 1 */
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78
79#define CONFIG_PCI_MEM_BUS 0x40000000
80#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81#define CONFIG_PCI_MEM_SIZE 0x10000000
82
83#define CONFIG_PCI_IO_BUS 0x50000000
84#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85#define CONFIG_PCI_IO_SIZE 0x01000000
86
cd65a3dc 87#define CONFIG_EEPRO100 1
6d0f6bcf 88#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 89#define CONFIG_NS8382X 1
83e40ba7 90#endif /* CONFIG_STK52XX */
56523f12 91
8f0b7cbe
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92/*
93 * Video console
94 */
5078cce8 95#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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96#define CONFIG_VIDEO_SM501
97#define CONFIG_VIDEO_SM501_32BPP
8f0b7cbe 98#define CONFIG_VIDEO_LOGO
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99
100#ifndef CONFIG_FO300
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101#else
102#define CONFIG_VIDEO_BMP_LOGO
103#endif
104
8f0b7cbe 105#define CONFIG_SPLASH_SCREEN
6d3bc9b8 106#endif /* #ifndef CONFIG_TQM5200S */
56523f12 107
56523f12 108/* Partitions */
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109
110/* USB */
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111#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
112 defined(CONFIG_STK52XX)
7b59b3c7 113#define CONFIG_USB_OHCI_NEW
6d0f6bcf 114#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 115
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116#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
117#define CONFIG_SYS_USB_OHCI_CPU_INIT
118#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
119#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
120#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 121
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122#endif
123
135ae006 124#ifndef CONFIG_CAM5200
56523f12 125/* POST support */
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126#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
127 CONFIG_SYS_POST_CPU | \
128 CONFIG_SYS_POST_I2C)
5078cce8 129#endif
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130
131#ifdef CONFIG_POST
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132/* preserve space for the post_word at end of on-chip SRAM */
133#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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134#endif
135
56523f12 136/*
a1aa0bb5 137 * BOOTP options
56523f12 138 */
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139#define CONFIG_BOOTP_BOOTFILESIZE
140#define CONFIG_BOOTP_BOOTPATH
141#define CONFIG_BOOTP_GATEWAY
142#define CONFIG_BOOTP_HOSTNAME
143
56523f12 144/*
2694690e 145 * Command line configuration.
56523f12 146 */
2694690e 147#define CONFIG_CMD_DATE
2694690e 148#define CONFIG_CMD_EEPROM
2694690e 149#define CONFIG_CMD_JFFS2
2694690e 150#define CONFIG_CMD_REGINFO
2694690e
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151#define CONFIG_CMD_BSP
152
2694690e 153#ifdef CONFIG_PCI
2b2a587d 154#define CONFIG_CMD_PCI
f33fca22 155#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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156#endif
157
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158#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
159 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 160 #define CONFIG_CMD_IDE
2694690e
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161#endif
162
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163#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
164 defined(CONFIG_STK52XX)
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165 #define CONFIG_CFG_USB
166 #define CONFIG_CFG_FAT
167#endif
168
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169#ifdef CONFIG_POST
170 #define CONFIG_CMD_DIAG
171#endif
172
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173#define CONFIG_TIMESTAMP /* display image timestamps */
174
14d0a02a 175#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 176# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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177#endif
178
179/*
180 * Autobooting
181 */
56523f12 182
81050926 183#define CONFIG_PREBOOT "echo;" \
4c4aca81 184 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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185 "echo"
186
187#undef CONFIG_BOOTARGS
188
6d0f6bcf 189#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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190# define ENV_UPDT \
191 "update=protect off FFF00000 +${filesize};" \
192 "erase FFF00000 +${filesize};" \
5078cce8 193 "cp.b 200000 FFF00000 ${filesize};" \
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194 "protect on FFF00000 +${filesize}\0"
195#else /* default lowboot configuration */
6d3bc9b8 196# define ENV_UPDT \
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197 "update=protect off FC000000 +${filesize};" \
198 "erase FC000000 +${filesize};" \
6d3bc9b8 199 "cp.b 200000 FC000000 ${filesize};" \
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200 "protect on FC000000 +${filesize}\0"
201#endif
5078cce8 202
e1f601b5 203#if defined(CONFIG_TQM5200)
6abaee42 204#define CUSTOM_ENV_SETTINGS \
e1f601b5 205 "hostname=tqm5200\0" \
6abaee42 206 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 207 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 208 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 209#elif defined(CONFIG_CAM5200)
1636d1c8 210#define CUSTOM_ENV_SETTINGS \
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211 "bootfile=cam5200/uImage\0" \
212 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 213 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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214#endif
215
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216#if defined(CONFIG_TQM5200_B)
217#define ENV_FLASH_LAYOUT \
218 "fdt_addr=FC100000\0" \
219 "kernel_addr=FC140000\0" \
220 "ramdisk_addr=FC600000\0"
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221#elif defined(CONFIG_CHARON)
222#define ENV_FLASH_LAYOUT \
223 "fdt_addr=FDFC0000\0" \
224 "kernel_addr=FC0A0000\0" \
225 "ramdisk_addr=FC200000\0"
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226#else /* !CONFIG_TQM5200_B */
227#define ENV_FLASH_LAYOUT \
228 "fdt_addr=FC0A0000\0" \
229 "kernel_addr=FC0C0000\0" \
230 "ramdisk_addr=FC300000\0"
231#endif
232
81050926 233#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 234 "netdev=eth0\0" \
e1f601b5 235 "console=ttyPSC0\0" \
a5cc5555 236 ENV_FLASH_LAYOUT \
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237 "kernel_addr_r=400000\0" \
238 "fdt_addr_r=600000\0" \
89c02e2c 239 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 240 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 241 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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242 "nfsroot=${serverip}:${rootpath}\0" \
243 "addip=setenv bootargs ${bootargs} " \
244 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
245 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 246 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 247 "console=${console},${baudrate}\0" \
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248 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
249 "flash_self_old=sete console ttyS0; " \
250 "run ramargs addip addcons addmtd; " \
fe126d8b 251 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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252 "flash_self=run ramargs addip addcons;" \
253 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
254 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 255 "bootm ${kernel_addr}\0" \
e1f601b5 256 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 257 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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258 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
259 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
260 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
261 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 262 "run nfsargs addip addcons addmtd; " \
e1f601b5 263 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 264 CUSTOM_ENV_SETTINGS \
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265 "load=tftp 200000 ${u-boot}\0" \
266 ENV_UPDT \
7e6bf358 267 ""
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268
269#define CONFIG_BOOTCOMMAND "run net_nfs"
270
271/*
272 * IPB Bus clocking configuration.
273 */
6d0f6bcf 274#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 275
6d0f6bcf 276#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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277/*
278 * PCI Bus clocking configuration
279 *
280 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 281 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 282 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 283 */
6d0f6bcf 284#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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285#endif
286
287/*
288 * I2C configuration
289 */
290#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 291#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 292#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 293#else
6d0f6bcf 294#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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295#endif
296
297/*
298 * I2C clock frequency
299 *
300 * Please notice, that the resulting clock frequency could differ from the
301 * configured value. This is because the I2C clock is derived from system
a187559e 302 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 303 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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304 * approximation allways lies below the configured value, never above.
305 */
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JCPV
306#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
307#define CONFIG_SYS_I2C_SLAVE 0x7F
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308
309/*
310 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
311 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
312 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
313 * same configuration could be used.
314 */
6d0f6bcf
JCPV
315#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
316#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
317#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
318#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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319
320/*
321 * HW-Monitor configuration on Mini-FAP
322 */
323#if defined (CONFIG_MINIFAP)
6d0f6bcf 324#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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325#endif
326
327/* List of I2C addresses to be verified by POST */
56523f12 328#if defined (CONFIG_MINIFAP)
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329#undef CONFIG_SYS_POST_I2C_ADDRS
330#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
331 CONFIG_SYS_I2C_HWMON_ADDR, \
332 CONFIG_SYS_I2C_SLAVE}
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333#endif
334
335/*
336 * Flash configuration
337 */
6d0f6bcf 338#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 339
d9384de2 340#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 341#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 342 (= chip selects) */
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343#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
344#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
345#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
346
347#define CONFIG_SYS_FLASH_ADDR0 0x555
348#define CONFIG_SYS_FLASH_ADDR1 0x2AA
349#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
350#define CONFIG_SYS_MAX_FLASH_SECT 128
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351#else
352/* use CFI flash driver */
6d0f6bcf 353#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 354#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 355#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
356#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
357#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 358 (= chip selects) */
6d0f6bcf 359#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 360#endif
7299712c 361
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JCPV
362#define CONFIG_SYS_FLASH_EMPTY_INFO
363#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
364#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 365
135ae006 366#if defined (CONFIG_CAM5200)
6d0f6bcf 367# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 368#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 369# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 370#else
6d0f6bcf 371# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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372#endif
373
d534f5cc 374/* Dynamic MTD partition support */
68d7d651 375#define CONFIG_CMD_MTDPARTS
942556a9 376#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 377#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 378
5624d66a 379#if defined(CONFIG_STK52XX)
5078cce8 380# if defined(CONFIG_TQM5200_B)
6d0f6bcf 381# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 382# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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383 "256k(dtb)," \
384 "2304k(kernel)," \
385 "2560k(small-fs)," \
45a212c4 386 "2m(initrd)," \
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387 "8m(misc)," \
388 "16m(big-fs)"
389# else /* highboot */
259bff7c 390# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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391 "3584k(small-fs)," \
392 "2m(initrd)," \
393 "8m(misc)," \
394 "15m(big-fs)," \
395 "1m(firmware)"
6d0f6bcf 396# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 397# else /* !CONFIG_TQM5200_B */
259bff7c 398# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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399 "128k(dtb)," \
400 "2304k(kernel)," \
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WD
401 "2m(initrd)," \
402 "4m(small-fs)," \
5078cce8 403 "8m(misc)," \
e1f601b5 404 "15m(big-fs)"
5078cce8 405# endif /* CONFIG_TQM5200_B */
135ae006 406#elif defined (CONFIG_CAM5200)
259bff7c 407# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 408 "1792k(kernel)," \
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409 "5632k(rootfs)," \
410 "24m(home)"
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411#elif defined (CONFIG_CHARON)
412# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
413 "1408k(kernel)," \
414 "2m(initrd)," \
415 "4m(small-fs)," \
416 "24320k(big-fs)," \
417 "256k(dts)"
6d3bc9b8 418#elif defined (CONFIG_FO300)
259bff7c 419# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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420 "1408k(kernel)," \
421 "2m(initrd)," \
422 "4m(small-fs)," \
423 "8m(misc)," \
424 "16m(big-fs)"
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425#else
426# error "Unknown Carrier Board"
427#endif /* CONFIG_STK52XX */
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428
429/*
430 * Environment settings
431 */
5a1aceb0 432#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 433#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 434#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 435#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 436#else
0e8d1586 437#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 438#endif /* CONFIG_TQM5200_B */
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439#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
440#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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441
442/*
443 * Memory map
444 */
6d0f6bcf
JCPV
445#define CONFIG_SYS_MBAR 0xF0000000
446#define CONFIG_SYS_SDRAM_BASE 0x00000000
447#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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448
449/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 450#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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451#ifdef CONFIG_POST
452/* preserve space for the post_word at end of on-chip SRAM */
553f0982 453#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 454#else
553f0982 455#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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456#endif
457
25ddd1fb 458#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 459#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 460
14d0a02a 461#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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462#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
463# define CONFIG_SYS_RAMBOOT 1
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464#endif
465
135ae006 466#if defined (CONFIG_CAM5200)
6d0f6bcf 467# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 468#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 469# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 470#else
6d0f6bcf 471# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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472#endif
473
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474#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
475#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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476
477/*
478 * Ethernet configuration
479 */
480#define CONFIG_MPC5xxx_FEC 1
86321fc1 481#define CONFIG_MPC5xxx_FEC_MII100
56523f12 482/*
86321fc1 483 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 484 */
86321fc1 485/* #define CONFIG_MPC5xxx_FEC_MII10 */
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486#define CONFIG_PHY_ADDR 0x00
487
488/*
489 * GPIO configuration
490 *
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491 * use CS1: Bit 0 (mask: 0x80000000):
492 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 493 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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494 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
495 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
496 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
497 * Use for REV200 STK52XX boards and FO300 boards. Do not use
498 * with REV100 modules (because, there I2C1 is used as I2C bus).
499 * use ATA: Bits 6-7 (mask 0x03000000):
500 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
501 * Use for CAM5200 board.
502 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
503 * use PSC6: Bits 9-11 (mask 0x00700000):
504 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
505 * UART, CODEC or IrDA.
506 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
507 * enable extended POST tests.
508 * Use for MINI-FAP and TQM5200_IB boards.
509 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
510 * Extended POST test is not available.
511 * Use for STK52xx, FO300 and CAM5200 boards.
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512 * WARNING: When the extended POST is enabled, these bits will
513 * be overridden by this code as GPIOs!
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514 * use PCI_DIS: Bit 16 (mask 0x00008000):
515 * 1 -> disable PCI controller (on CAM5200 board).
516 * use USB: Bits 18-19 (mask 0x00003000):
517 * 10 -> two UARTs (on FO300 and CAM5200).
518 * use PSC3: Bits 20-23 (mask: 0x00000f00):
519 * 0000 -> All PSC3 pins are GPIOs.
520 * 1100 -> UART/SPI (on FO300 board).
521 * 0100 -> UART (on CAM5200 board).
522 * use PSC2: Bits 25:27 (mask: 0x00000030):
523 * 000 -> All PSC2 pins are GPIOs.
524 * 100 -> UART (on CAM5200 board).
525 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 526 * Use for REV100 STK52xx boards
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527 * 01x -> Use AC97 (on FO300 board).
528 * use PSC1: Bits 29-31 (mask: 0x00000007):
529 * 100 -> UART (on all boards).
56523f12 530 */
98e69567 531#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 532#if defined (CONFIG_MINIFAP)
6d0f6bcf 533# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 534#elif defined (CONFIG_STK52XX)
83e40ba7 535# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 536# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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537# else /* STK52xx REV200 and above */
538# if defined (CONFIG_TQM5200_REV100)
539# error TQM5200 REV100 not supported on STK52XX REV200 or above
540# else/* TQM5200 REV200 and above */
6d0f6bcf 541# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 542# endif
8f0b7cbe 543# endif
6d3bc9b8 544#elif defined (CONFIG_FO300)
6d0f6bcf 545# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 546#elif defined (CONFIG_CAM5200)
6d0f6bcf 547# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 548#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 549# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 550#endif
98e69567 551#endif
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552
553/*
554 * RTC configuration
555 */
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556#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
557# define CONFIG_RTC_M41T11 1
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558# define CONFIG_SYS_I2C_RTC_ADDR 0x68
559# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 560 year */
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561#else
562# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
563#endif
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564
565/*
566 * Miscellaneous configurable options
567 */
6d0f6bcf 568#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 569
2751a95a 570#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 571
6d0f6bcf 572#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 573#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 574#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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575#endif
576
577#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 578#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 579#else
6d0f6bcf 580#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 581#endif
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582#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
583#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
584#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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585
586/* Enable an alternate, more extensive memory test */
6d0f6bcf 587#define CONFIG_SYS_ALT_MEMTEST
56523f12 588
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589#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
590#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 591
6d0f6bcf 592#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 593
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594/*
595 * Various low-level settings
596 */
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597#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
598#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 599
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600#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
601#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
602#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
603#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 604#else
6d0f6bcf 605#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 606#endif
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607#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
608#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 609
7e6bf358 610#define CONFIG_LAST_STAGE_INIT
7e6bf358 611
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612/*
613 * SRAM - Do not map below 2 GB in address space, because this area is used
614 * for SDRAM autosizing.
615 */
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616#define CONFIG_SYS_CS2_START 0xE5000000
617#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
618#define CONFIG_SYS_CS2_CFG 0x0004D930
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619
620/*
621 * Grafic controller - Do not map below 2 GB in address space, because this
622 * area is used for SDRAM autosizing.
623 */
8f0b7cbe 624#define SM501_FB_BASE 0xE0000000
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625#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
626#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
627#define CONFIG_SYS_CS1_CFG 0x8F48FF70
628#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 629
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630#define CONFIG_SYS_CS_BURST 0x00000000
631#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 632
7299712c 633#if defined(CONFIG_CAM5200)
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634#define CONFIG_SYS_CS4_START 0xB0000000
635#define CONFIG_SYS_CS4_SIZE 0x00010000
636#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 637
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638#define CONFIG_SYS_CS5_START 0xD0000000
639#define CONFIG_SYS_CS5_SIZE 0x01208000
640#define CONFIG_SYS_CS5_CFG 0x1414BF10
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641#endif
642
6d0f6bcf 643#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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644
645/*-----------------------------------------------------------------------
646 * USB stuff
647 *-----------------------------------------------------------------------
648 */
649#define CONFIG_USB_CLOCK 0x0001BBBB
650#define CONFIG_USB_CONFIG 0x00001000
651
652/*-----------------------------------------------------------------------
653 * IDE/ATA stuff Supports IDE harddisk
654 *-----------------------------------------------------------------------
655 */
656
81050926 657#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 658
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659#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
660#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 661
81050926 662#define CONFIG_IDE_RESET /* reset for ide supported */
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663#define CONFIG_IDE_PREINIT
664
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665#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
666#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 667
6d0f6bcf 668#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 669
6d0f6bcf 670#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 671
95c44ec4 672/* Offset for data I/O */
6d0f6bcf 673#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 674
95c44ec4 675/* Offset for normal register accesses */
6d0f6bcf 676#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 677
95c44ec4 678/* Offset for alternate registers */
6d0f6bcf 679#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 680
95c44ec4 681/* Interval between registers */
6d0f6bcf 682#define CONFIG_SYS_ATA_STRIDE 4
56523f12 683
33af3e66 684/* Support ATAPI devices */
95c44ec4 685#define CONFIG_ATAPI 1
33af3e66 686
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687/*-----------------------------------------------------------------------
688 * Open firmware flat tree support
689 *-----------------------------------------------------------------------
690 */
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691#define OF_CPU "PowerPC,5200@0"
692#define OF_SOC "soc5200@f0000000"
693#define OF_TBCLK (bd->bi_busfreq / 4)
694#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
695
56523f12 696#endif /* __CONFIG_H */