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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
56523f12
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
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47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
48#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 49#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 50#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 51
6d3bc9b8 52#ifdef CONFIG_FO300
6d0f6bcf 53#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
ddde6b7c 54#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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55#if 0
56#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
57 /* switch is closed */
58#endif
59
60#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
61 /* switch is open */
5196a7a0 62#endif /* CONFIG_FO300 */
6d3bc9b8 63
98e69567 64#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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65#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
66#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
67#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 68#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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69#define CONFIG_BOARD_EARLY_INIT_R
70#endif /* CONFIG_STK52XX */
56523f12 71
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72/*
73 * PCI Mapping:
74 * 0x40000000 - 0x4fffffff - PCI Memory
75 * 0x50000000 - 0x50ffffff - PCI IO Space
76 */
98e69567 77#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
31a64923 78/* #define CONFIG_PCI_SCAN_SHOW 1 */
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79
80#define CONFIG_PCI_MEM_BUS 0x40000000
81#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
82#define CONFIG_PCI_MEM_SIZE 0x10000000
83
84#define CONFIG_PCI_IO_BUS 0x50000000
85#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
86#define CONFIG_PCI_IO_SIZE 0x01000000
87
cd65a3dc 88#define CONFIG_EEPRO100 1
6d0f6bcf 89#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 90#define CONFIG_NS8382X 1
83e40ba7 91#endif /* CONFIG_STK52XX */
56523f12 92
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93/*
94 * Video console
95 */
5078cce8 96#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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97#define CONFIG_VIDEO_SM501
98#define CONFIG_VIDEO_SM501_32BPP
8f0b7cbe 99#define CONFIG_VIDEO_LOGO
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100
101#ifndef CONFIG_FO300
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102#else
103#define CONFIG_VIDEO_BMP_LOGO
104#endif
105
8f0b7cbe 106#define CONFIG_SPLASH_SCREEN
6d3bc9b8 107#endif /* #ifndef CONFIG_TQM5200S */
56523f12 108
56523f12 109/* Partitions */
56523f12 110#define CONFIG_DOS_PARTITION
8f0b7cbe 111#define CONFIG_ISO_PARTITION
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112
113/* USB */
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114#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
115 defined(CONFIG_STK52XX)
7b59b3c7 116#define CONFIG_USB_OHCI_NEW
6d0f6bcf 117#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 118
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119#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
120#define CONFIG_SYS_USB_OHCI_CPU_INIT
121#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
122#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
123#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 124
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125#endif
126
135ae006 127#ifndef CONFIG_CAM5200
56523f12 128/* POST support */
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129#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
130 CONFIG_SYS_POST_CPU | \
131 CONFIG_SYS_POST_I2C)
5078cce8 132#endif
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133
134#ifdef CONFIG_POST
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135/* preserve space for the post_word at end of on-chip SRAM */
136#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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137#endif
138
56523f12 139/*
a1aa0bb5 140 * BOOTP options
56523f12 141 */
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142#define CONFIG_BOOTP_BOOTFILESIZE
143#define CONFIG_BOOTP_BOOTPATH
144#define CONFIG_BOOTP_GATEWAY
145#define CONFIG_BOOTP_HOSTNAME
146
56523f12 147/*
2694690e 148 * Command line configuration.
56523f12 149 */
2694690e 150#define CONFIG_CMD_DATE
2694690e 151#define CONFIG_CMD_EEPROM
2694690e 152#define CONFIG_CMD_JFFS2
2694690e 153#define CONFIG_CMD_REGINFO
2694690e
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154#define CONFIG_CMD_BSP
155
156#ifdef CONFIG_VIDEO
157 #define CONFIG_CMD_BMP
158#endif
159
160#ifdef CONFIG_PCI
2b2a587d 161#define CONFIG_CMD_PCI
f33fca22 162#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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163#endif
164
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165#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
166 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 167 #define CONFIG_CMD_IDE
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168#endif
169
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170#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
171 defined(CONFIG_STK52XX)
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172 #define CONFIG_CFG_USB
173 #define CONFIG_CFG_FAT
174#endif
175
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176#ifdef CONFIG_POST
177 #define CONFIG_CMD_DIAG
178#endif
179
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180#define CONFIG_TIMESTAMP /* display image timestamps */
181
14d0a02a 182#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 183# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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184#endif
185
186/*
187 * Autobooting
188 */
56523f12 189
81050926 190#define CONFIG_PREBOOT "echo;" \
4c4aca81 191 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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192 "echo"
193
194#undef CONFIG_BOOTARGS
195
6d0f6bcf 196#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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197# define ENV_UPDT \
198 "update=protect off FFF00000 +${filesize};" \
199 "erase FFF00000 +${filesize};" \
5078cce8 200 "cp.b 200000 FFF00000 ${filesize};" \
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201 "protect on FFF00000 +${filesize}\0"
202#else /* default lowboot configuration */
6d3bc9b8 203# define ENV_UPDT \
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204 "update=protect off FC000000 +${filesize};" \
205 "erase FC000000 +${filesize};" \
6d3bc9b8 206 "cp.b 200000 FC000000 ${filesize};" \
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207 "protect on FC000000 +${filesize}\0"
208#endif
5078cce8 209
e1f601b5 210#if defined(CONFIG_TQM5200)
6abaee42 211#define CUSTOM_ENV_SETTINGS \
e1f601b5 212 "hostname=tqm5200\0" \
6abaee42 213 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 214 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 215 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 216#elif defined(CONFIG_CAM5200)
1636d1c8 217#define CUSTOM_ENV_SETTINGS \
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218 "bootfile=cam5200/uImage\0" \
219 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 220 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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221#endif
222
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223#if defined(CONFIG_TQM5200_B)
224#define ENV_FLASH_LAYOUT \
225 "fdt_addr=FC100000\0" \
226 "kernel_addr=FC140000\0" \
227 "ramdisk_addr=FC600000\0"
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228#elif defined(CONFIG_CHARON)
229#define ENV_FLASH_LAYOUT \
230 "fdt_addr=FDFC0000\0" \
231 "kernel_addr=FC0A0000\0" \
232 "ramdisk_addr=FC200000\0"
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233#else /* !CONFIG_TQM5200_B */
234#define ENV_FLASH_LAYOUT \
235 "fdt_addr=FC0A0000\0" \
236 "kernel_addr=FC0C0000\0" \
237 "ramdisk_addr=FC300000\0"
238#endif
239
81050926 240#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 241 "netdev=eth0\0" \
e1f601b5 242 "console=ttyPSC0\0" \
a5cc5555 243 ENV_FLASH_LAYOUT \
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244 "kernel_addr_r=400000\0" \
245 "fdt_addr_r=600000\0" \
89c02e2c 246 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 247 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 248 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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249 "nfsroot=${serverip}:${rootpath}\0" \
250 "addip=setenv bootargs ${bootargs} " \
251 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
252 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 253 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 254 "console=${console},${baudrate}\0" \
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255 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
256 "flash_self_old=sete console ttyS0; " \
257 "run ramargs addip addcons addmtd; " \
fe126d8b 258 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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259 "flash_self=run ramargs addip addcons;" \
260 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
261 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 262 "bootm ${kernel_addr}\0" \
e1f601b5 263 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 264 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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265 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
266 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
267 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
268 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 269 "run nfsargs addip addcons addmtd; " \
e1f601b5 270 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 271 CUSTOM_ENV_SETTINGS \
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272 "load=tftp 200000 ${u-boot}\0" \
273 ENV_UPDT \
7e6bf358 274 ""
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275
276#define CONFIG_BOOTCOMMAND "run net_nfs"
277
278/*
279 * IPB Bus clocking configuration.
280 */
6d0f6bcf 281#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 282
6d0f6bcf 283#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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284/*
285 * PCI Bus clocking configuration
286 *
287 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 288 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 289 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 290 */
6d0f6bcf 291#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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292#endif
293
294/*
295 * I2C configuration
296 */
297#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 298#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 299#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 300#else
6d0f6bcf 301#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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302#endif
303
304/*
305 * I2C clock frequency
306 *
307 * Please notice, that the resulting clock frequency could differ from the
308 * configured value. This is because the I2C clock is derived from system
a187559e 309 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 310 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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311 * approximation allways lies below the configured value, never above.
312 */
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JCPV
313#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
314#define CONFIG_SYS_I2C_SLAVE 0x7F
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315
316/*
317 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
318 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
319 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
320 * same configuration could be used.
321 */
6d0f6bcf
JCPV
322#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
323#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
324#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
325#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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326
327/*
328 * HW-Monitor configuration on Mini-FAP
329 */
330#if defined (CONFIG_MINIFAP)
6d0f6bcf 331#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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332#endif
333
334/* List of I2C addresses to be verified by POST */
56523f12 335#if defined (CONFIG_MINIFAP)
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336#undef CONFIG_SYS_POST_I2C_ADDRS
337#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
338 CONFIG_SYS_I2C_HWMON_ADDR, \
339 CONFIG_SYS_I2C_SLAVE}
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340#endif
341
342/*
343 * Flash configuration
344 */
6d0f6bcf 345#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 346
d9384de2 347#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 348#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 349 (= chip selects) */
6d0f6bcf
JCPV
350#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
351#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
352#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
353
354#define CONFIG_SYS_FLASH_ADDR0 0x555
355#define CONFIG_SYS_FLASH_ADDR1 0x2AA
356#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
357#define CONFIG_SYS_MAX_FLASH_SECT 128
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358#else
359/* use CFI flash driver */
6d0f6bcf 360#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 361#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 362#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
363#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
364#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 365 (= chip selects) */
6d0f6bcf 366#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 367#endif
7299712c 368
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369#define CONFIG_SYS_FLASH_EMPTY_INFO
370#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
371#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 372
135ae006 373#if defined (CONFIG_CAM5200)
6d0f6bcf 374# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 375#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 376# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 377#else
6d0f6bcf 378# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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379#endif
380
d534f5cc 381/* Dynamic MTD partition support */
68d7d651 382#define CONFIG_CMD_MTDPARTS
942556a9 383#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 384#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 385
5624d66a 386#if defined(CONFIG_STK52XX)
5078cce8 387# if defined(CONFIG_TQM5200_B)
6d0f6bcf 388# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 389# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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390 "256k(dtb)," \
391 "2304k(kernel)," \
392 "2560k(small-fs)," \
45a212c4 393 "2m(initrd)," \
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394 "8m(misc)," \
395 "16m(big-fs)"
396# else /* highboot */
259bff7c 397# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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398 "3584k(small-fs)," \
399 "2m(initrd)," \
400 "8m(misc)," \
401 "15m(big-fs)," \
402 "1m(firmware)"
6d0f6bcf 403# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 404# else /* !CONFIG_TQM5200_B */
259bff7c 405# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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406 "128k(dtb)," \
407 "2304k(kernel)," \
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408 "2m(initrd)," \
409 "4m(small-fs)," \
5078cce8 410 "8m(misc)," \
e1f601b5 411 "15m(big-fs)"
5078cce8 412# endif /* CONFIG_TQM5200_B */
135ae006 413#elif defined (CONFIG_CAM5200)
259bff7c 414# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 415 "1792k(kernel)," \
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416 "5632k(rootfs)," \
417 "24m(home)"
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418#elif defined (CONFIG_CHARON)
419# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
420 "1408k(kernel)," \
421 "2m(initrd)," \
422 "4m(small-fs)," \
423 "24320k(big-fs)," \
424 "256k(dts)"
6d3bc9b8 425#elif defined (CONFIG_FO300)
259bff7c 426# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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427 "1408k(kernel)," \
428 "2m(initrd)," \
429 "4m(small-fs)," \
430 "8m(misc)," \
431 "16m(big-fs)"
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432#else
433# error "Unknown Carrier Board"
434#endif /* CONFIG_STK52XX */
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435
436/*
437 * Environment settings
438 */
5a1aceb0 439#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 440#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 441#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 442#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 443#else
0e8d1586 444#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 445#endif /* CONFIG_TQM5200_B */
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446#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
447#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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448
449/*
450 * Memory map
451 */
6d0f6bcf
JCPV
452#define CONFIG_SYS_MBAR 0xF0000000
453#define CONFIG_SYS_SDRAM_BASE 0x00000000
454#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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455
456/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 457#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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458#ifdef CONFIG_POST
459/* preserve space for the post_word at end of on-chip SRAM */
553f0982 460#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 461#else
553f0982 462#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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463#endif
464
25ddd1fb 465#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 466#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 467
14d0a02a 468#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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469#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
470# define CONFIG_SYS_RAMBOOT 1
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471#endif
472
135ae006 473#if defined (CONFIG_CAM5200)
6d0f6bcf 474# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 475#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 476# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 477#else
6d0f6bcf 478# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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479#endif
480
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481#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
482#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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483
484/*
485 * Ethernet configuration
486 */
487#define CONFIG_MPC5xxx_FEC 1
86321fc1 488#define CONFIG_MPC5xxx_FEC_MII100
56523f12 489/*
86321fc1 490 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 491 */
86321fc1 492/* #define CONFIG_MPC5xxx_FEC_MII10 */
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493#define CONFIG_PHY_ADDR 0x00
494
495/*
496 * GPIO configuration
497 *
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498 * use CS1: Bit 0 (mask: 0x80000000):
499 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 500 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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501 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
502 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
503 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
504 * Use for REV200 STK52XX boards and FO300 boards. Do not use
505 * with REV100 modules (because, there I2C1 is used as I2C bus).
506 * use ATA: Bits 6-7 (mask 0x03000000):
507 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
508 * Use for CAM5200 board.
509 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
510 * use PSC6: Bits 9-11 (mask 0x00700000):
511 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
512 * UART, CODEC or IrDA.
513 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
514 * enable extended POST tests.
515 * Use for MINI-FAP and TQM5200_IB boards.
516 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
517 * Extended POST test is not available.
518 * Use for STK52xx, FO300 and CAM5200 boards.
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519 * WARNING: When the extended POST is enabled, these bits will
520 * be overridden by this code as GPIOs!
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521 * use PCI_DIS: Bit 16 (mask 0x00008000):
522 * 1 -> disable PCI controller (on CAM5200 board).
523 * use USB: Bits 18-19 (mask 0x00003000):
524 * 10 -> two UARTs (on FO300 and CAM5200).
525 * use PSC3: Bits 20-23 (mask: 0x00000f00):
526 * 0000 -> All PSC3 pins are GPIOs.
527 * 1100 -> UART/SPI (on FO300 board).
528 * 0100 -> UART (on CAM5200 board).
529 * use PSC2: Bits 25:27 (mask: 0x00000030):
530 * 000 -> All PSC2 pins are GPIOs.
531 * 100 -> UART (on CAM5200 board).
532 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 533 * Use for REV100 STK52xx boards
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534 * 01x -> Use AC97 (on FO300 board).
535 * use PSC1: Bits 29-31 (mask: 0x00000007):
536 * 100 -> UART (on all boards).
56523f12 537 */
98e69567 538#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 539#if defined (CONFIG_MINIFAP)
6d0f6bcf 540# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 541#elif defined (CONFIG_STK52XX)
83e40ba7 542# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 543# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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544# else /* STK52xx REV200 and above */
545# if defined (CONFIG_TQM5200_REV100)
546# error TQM5200 REV100 not supported on STK52XX REV200 or above
547# else/* TQM5200 REV200 and above */
6d0f6bcf 548# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 549# endif
8f0b7cbe 550# endif
6d3bc9b8 551#elif defined (CONFIG_FO300)
6d0f6bcf 552# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 553#elif defined (CONFIG_CAM5200)
6d0f6bcf 554# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 555#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 556# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 557#endif
98e69567 558#endif
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559
560/*
561 * RTC configuration
562 */
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563#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
564# define CONFIG_RTC_M41T11 1
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565# define CONFIG_SYS_I2C_RTC_ADDR 0x68
566# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 567 year */
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568#else
569# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
570#endif
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571
572/*
573 * Miscellaneous configurable options
574 */
6d0f6bcf 575#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 576
2751a95a 577#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 578
6d0f6bcf 579#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 580#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 581#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
2694690e
JL
582#endif
583
584#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 585#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 586#else
6d0f6bcf 587#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 588#endif
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589#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
590#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
591#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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592
593/* Enable an alternate, more extensive memory test */
6d0f6bcf 594#define CONFIG_SYS_ALT_MEMTEST
56523f12 595
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596#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
597#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 598
6d0f6bcf 599#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 600
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601/*
602 * Various low-level settings
603 */
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604#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
605#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 606
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607#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
608#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
609#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
610#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 611#else
6d0f6bcf 612#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 613#endif
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614#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
615#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 616
7e6bf358 617#define CONFIG_LAST_STAGE_INIT
7e6bf358 618
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619/*
620 * SRAM - Do not map below 2 GB in address space, because this area is used
621 * for SDRAM autosizing.
622 */
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623#define CONFIG_SYS_CS2_START 0xE5000000
624#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
625#define CONFIG_SYS_CS2_CFG 0x0004D930
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626
627/*
628 * Grafic controller - Do not map below 2 GB in address space, because this
629 * area is used for SDRAM autosizing.
630 */
8f0b7cbe 631#define SM501_FB_BASE 0xE0000000
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632#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
633#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
634#define CONFIG_SYS_CS1_CFG 0x8F48FF70
635#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 636
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637#define CONFIG_SYS_CS_BURST 0x00000000
638#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 639
7299712c 640#if defined(CONFIG_CAM5200)
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641#define CONFIG_SYS_CS4_START 0xB0000000
642#define CONFIG_SYS_CS4_SIZE 0x00010000
643#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 644
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645#define CONFIG_SYS_CS5_START 0xD0000000
646#define CONFIG_SYS_CS5_SIZE 0x01208000
647#define CONFIG_SYS_CS5_CFG 0x1414BF10
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648#endif
649
6d0f6bcf 650#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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651
652/*-----------------------------------------------------------------------
653 * USB stuff
654 *-----------------------------------------------------------------------
655 */
656#define CONFIG_USB_CLOCK 0x0001BBBB
657#define CONFIG_USB_CONFIG 0x00001000
658
659/*-----------------------------------------------------------------------
660 * IDE/ATA stuff Supports IDE harddisk
661 *-----------------------------------------------------------------------
662 */
663
81050926 664#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 665
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666#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
667#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 668
81050926 669#define CONFIG_IDE_RESET /* reset for ide supported */
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670#define CONFIG_IDE_PREINIT
671
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672#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
673#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 674
6d0f6bcf 675#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 676
6d0f6bcf 677#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 678
95c44ec4 679/* Offset for data I/O */
6d0f6bcf 680#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 681
95c44ec4 682/* Offset for normal register accesses */
6d0f6bcf 683#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 684
95c44ec4 685/* Offset for alternate registers */
6d0f6bcf 686#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 687
95c44ec4 688/* Interval between registers */
6d0f6bcf 689#define CONFIG_SYS_ATA_STRIDE 4
56523f12 690
33af3e66 691/* Support ATAPI devices */
95c44ec4 692#define CONFIG_ATAPI 1
33af3e66 693
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694/*-----------------------------------------------------------------------
695 * Open firmware flat tree support
696 *-----------------------------------------------------------------------
697 */
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698#define OF_CPU "PowerPC,5200@0"
699#define OF_SOC "soc5200@f0000000"
700#define OF_TBCLK (bd->bi_busfreq / 4)
701#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
702
56523f12 703#endif /* __CONFIG_H */