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d4ca31c4 | 1 | /* |
7c803be2 | 2 | * (C) Copyright 2000-2008 |
d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c178d3da | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d4ca31c4 WD |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
37 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
38 | ||
66ca92a5 | 39 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
41 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
66ca92a5 | 42 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ |
c178d3da WD |
43 | /* (it will be used if there is no */ |
44 | /* 'cpuclk' variable with valid value) */ | |
d4ca31c4 | 45 | |
6d0f6bcf | 46 | #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ |
75d1ea7f WD |
47 | /* (function measure_gclk() */ |
48 | /* will be called) */ | |
6d0f6bcf JCPV |
49 | #ifdef CONFIG_SYS_MEASURE_CPUCLK |
50 | #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
75d1ea7f WD |
51 | #endif |
52 | ||
c178d3da | 53 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
54 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
55 | #define CONFIG_SYS_MAXIDLE 10 | |
d4ca31c4 WD |
56 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
57 | ||
c178d3da | 58 | #define CONFIG_BOOTCOUNT_LIMIT |
d4ca31c4 WD |
59 | |
60 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
61 | ||
62 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
63 | ||
c178d3da | 64 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 65 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d4ca31c4 WD |
66 | "echo" |
67 | ||
68 | #undef CONFIG_BOOTARGS | |
69 | ||
c178d3da | 70 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
d4ca31c4 WD |
71 | "netdev=eth0\0" \ |
72 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 73 | "nfsroot=${serverip}:${rootpath}\0" \ |
d4ca31c4 | 74 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
75 | "addip=setenv bootargs ${bootargs} " \ |
76 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
77 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d4ca31c4 | 78 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 79 | "bootm ${kernel_addr}\0" \ |
d4ca31c4 | 80 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
81 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
82 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d4ca31c4 | 83 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
84 | "hostname=TQM866M\0" \ |
85 | "bootfile=TQM866M/uImage\0" \ | |
9ef57bbe MK |
86 | "fdt_addr=400C0000\0" \ |
87 | "kernel_addr=40100000\0" \ | |
eb6da805 | 88 | "ramdisk_addr=40280000\0" \ |
29f8f58f | 89 | "u-boot=TQM866M/u-image.bin\0" \ |
9ef57bbe | 90 | "load=tftp 200000 ${u-boot}\0" \ |
29f8f58f WD |
91 | "update=prot off 40000000 +${filesize};" \ |
92 | "era 40000000 +${filesize};" \ | |
9ef57bbe | 93 | "cp.b 200000 40000000 ${filesize};" \ |
29f8f58f | 94 | "sete filesize;save\0" \ |
d4ca31c4 WD |
95 | "" |
96 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
97 | ||
98 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 99 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
d4ca31c4 WD |
100 | |
101 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
102 | ||
c178d3da | 103 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
d4ca31c4 WD |
104 | |
105 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
106 | ||
107 | /* enable I2C and select the hardware/software driver */ | |
108 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
c178d3da | 109 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
d4ca31c4 | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
112 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
d4ca31c4 WD |
113 | |
114 | #ifdef CONFIG_SOFT_I2C | |
115 | /* | |
116 | * Software (bit-bang) I2C driver configuration | |
117 | */ | |
118 | #define PB_SCL 0x00000020 /* PB 26 */ | |
119 | #define PB_SDA 0x00000010 /* PB 27 */ | |
120 | ||
121 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
122 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
123 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
124 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
125 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
c178d3da | 126 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
d4ca31c4 | 127 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
c178d3da | 128 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
d4ca31c4 WD |
129 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
130 | #endif /* CONFIG_SOFT_I2C */ | |
131 | ||
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ |
133 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
134 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
135 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
d4ca31c4 | 136 | |
37d4bb70 JL |
137 | /* |
138 | * BOOTP options | |
139 | */ | |
140 | #define CONFIG_BOOTP_SUBNETMASK | |
141 | #define CONFIG_BOOTP_GATEWAY | |
142 | #define CONFIG_BOOTP_HOSTNAME | |
143 | #define CONFIG_BOOTP_BOOTPATH | |
144 | #define CONFIG_BOOTP_BOOTFILESIZE | |
145 | ||
d4ca31c4 WD |
146 | |
147 | #define CONFIG_MAC_PARTITION | |
148 | #define CONFIG_DOS_PARTITION | |
149 | ||
a6cccaea WD |
150 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
151 | ||
152 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
d4ca31c4 | 153 | |
d4ca31c4 | 154 | |
2694690e JL |
155 | /* |
156 | * Command line configuration. | |
157 | */ | |
158 | #include <config_cmd_default.h> | |
159 | ||
160 | #define CONFIG_CMD_ASKENV | |
161 | #define CONFIG_CMD_DHCP | |
162 | #define CONFIG_CMD_EEPROM | |
29f8f58f | 163 | #define CONFIG_CMD_ELF |
9a63b7f4 | 164 | #define CONFIG_CMD_EXT2 |
2694690e | 165 | #define CONFIG_CMD_IDE |
29f8f58f | 166 | #define CONFIG_CMD_JFFS2 |
2694690e | 167 | #define CONFIG_CMD_NFS |
29f8f58f WD |
168 | #define CONFIG_CMD_SNTP |
169 | ||
170 | ||
171 | #define CONFIG_NETCONSOLE | |
2694690e | 172 | |
d4ca31c4 WD |
173 | |
174 | /* | |
175 | * Miscellaneous configurable options | |
176 | */ | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
178 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d4ca31c4 | 179 | |
2751a95a | 180 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
182 | #ifdef CONFIG_SYS_HUSH_PARSER | |
183 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
d4ca31c4 WD |
184 | #endif |
185 | ||
2694690e | 186 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 187 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4ca31c4 | 188 | #else |
6d0f6bcf | 189 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d4ca31c4 | 190 | #endif |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
192 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
193 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d4ca31c4 | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
196 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d4ca31c4 | 197 | |
6d0f6bcf | 198 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
d4ca31c4 | 199 | |
6d0f6bcf | 200 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d4ca31c4 | 201 | |
6d0f6bcf | 202 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
d4ca31c4 WD |
203 | |
204 | /* | |
205 | * Low Level Configuration Settings | |
206 | * (address mappings, register initial values, etc.) | |
207 | * You should know what you are doing if you make changes here. | |
208 | */ | |
209 | /*----------------------------------------------------------------------- | |
210 | * Internal Memory Mapped Register | |
211 | */ | |
6d0f6bcf | 212 | #define CONFIG_SYS_IMMR 0xFFF00000 |
d4ca31c4 WD |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * Definitions for initial stack pointer and data area (in DPRAM) | |
216 | */ | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
218 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
219 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
220 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
221 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
d4ca31c4 WD |
222 | |
223 | /*----------------------------------------------------------------------- | |
224 | * Start addresses for the final memory configuration | |
225 | * (Set up by the startup code) | |
6d0f6bcf | 226 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d4ca31c4 | 227 | */ |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
229 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
230 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
231 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
232 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
d4ca31c4 WD |
233 | |
234 | /* | |
235 | * For booting Linux, the board info and command line data | |
236 | * have to be in the first 8 MB of memory, since this is | |
237 | * the maximum mapped by the Linux kernel during initialization. | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d4ca31c4 WD |
240 | |
241 | /*----------------------------------------------------------------------- | |
242 | * FLASH organization | |
243 | */ | |
e318d9e9 | 244 | /* use CFI flash driver */ |
6d0f6bcf | 245 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 246 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
248 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
249 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
250 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
251 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
d4ca31c4 | 252 | |
5a1aceb0 | 253 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
254 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
255 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
256 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
d4ca31c4 WD |
257 | |
258 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
259 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
260 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
d4ca31c4 | 261 | |
6d0f6bcf | 262 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 263 | |
7c803be2 WD |
264 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
265 | ||
29f8f58f WD |
266 | /*----------------------------------------------------------------------- |
267 | * Dynamic MTD partition support | |
268 | */ | |
68d7d651 | 269 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
270 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
271 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
272 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
273 | ||
274 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
275 | "128k(dtb)," \ | |
276 | "1920k(kernel)," \ | |
277 | "5632(rootfs)," \ | |
cd82919e | 278 | "4m(data)" |
29f8f58f | 279 | |
d4ca31c4 WD |
280 | /*----------------------------------------------------------------------- |
281 | * Hardware Information Block | |
282 | */ | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
284 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
285 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
d4ca31c4 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * Cache Configuration | |
289 | */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 291 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 292 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
d4ca31c4 WD |
293 | #endif |
294 | ||
295 | /*----------------------------------------------------------------------- | |
296 | * SYPCR - System Protection Control 11-9 | |
297 | * SYPCR can only be written once after reset! | |
298 | *----------------------------------------------------------------------- | |
299 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
300 | */ | |
301 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 302 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
d4ca31c4 WD |
303 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
304 | #else | |
6d0f6bcf | 305 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
d4ca31c4 WD |
306 | #endif |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * SIUMCR - SIU Module Configuration 11-6 | |
310 | *----------------------------------------------------------------------- | |
311 | * PCMCIA config., multi-function pin tri-state | |
312 | */ | |
c178d3da | 313 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf | 314 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 | 315 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 316 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 WD |
317 | #endif /* CONFIG_CAN_DRIVER */ |
318 | ||
319 | /*----------------------------------------------------------------------- | |
320 | * TBSCR - Time Base Status and Control 11-26 | |
321 | *----------------------------------------------------------------------- | |
322 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
323 | */ | |
6d0f6bcf | 324 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
d4ca31c4 | 325 | |
d4ca31c4 WD |
326 | /*----------------------------------------------------------------------- |
327 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
328 | *----------------------------------------------------------------------- | |
329 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
330 | */ | |
6d0f6bcf | 331 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
d4ca31c4 | 332 | |
d4ca31c4 WD |
333 | /*----------------------------------------------------------------------- |
334 | * SCCR - System Clock and reset Control Register 15-27 | |
335 | *----------------------------------------------------------------------- | |
336 | * Set clock output, timebase and RTC source and divider, | |
337 | * power management and some other internal clocks | |
338 | */ | |
339 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 340 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d4ca31c4 WD |
341 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
342 | SCCR_DFALCD00) | |
d4ca31c4 WD |
343 | |
344 | /*----------------------------------------------------------------------- | |
345 | * PCMCIA stuff | |
346 | *----------------------------------------------------------------------- | |
347 | * | |
348 | */ | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
350 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
351 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
352 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
353 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
354 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
355 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
356 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
d4ca31c4 WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
360 | *----------------------------------------------------------------------- | |
361 | */ | |
362 | ||
c178d3da | 363 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
d4ca31c4 | 364 | |
c178d3da WD |
365 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
366 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
d4ca31c4 WD |
367 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
368 | ||
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
370 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
d4ca31c4 | 371 | |
6d0f6bcf | 372 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
d4ca31c4 | 373 | |
6d0f6bcf | 374 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
d4ca31c4 WD |
375 | |
376 | /* Offset for data I/O */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
378 | |
379 | /* Offset for normal register accesses */ | |
6d0f6bcf | 380 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
381 | |
382 | /* Offset for alternate registers */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
d4ca31c4 WD |
384 | |
385 | /*----------------------------------------------------------------------- | |
386 | * | |
387 | *----------------------------------------------------------------------- | |
388 | * | |
389 | */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_DER 0 |
d4ca31c4 WD |
391 | |
392 | /* | |
393 | * Init Memory Controller: | |
394 | * | |
395 | * BR0/1 and OR0/1 (FLASH) | |
396 | */ | |
397 | ||
398 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
399 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
400 | ||
401 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
402 | * restrict access enough to keep SRAM working (if any) | |
403 | * but not too much to meddle with FLASH accesses | |
404 | */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
406 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
d4ca31c4 WD |
407 | |
408 | /* | |
c178d3da | 409 | * FLASH timing: Default value of OR0 after reset |
d4ca31c4 | 410 | */ |
6d0f6bcf | 411 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
c178d3da | 412 | OR_SCY_15_CLK | OR_TRLX) |
d4ca31c4 | 413 | |
6d0f6bcf JCPV |
414 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
415 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
416 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 | 417 | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
419 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
420 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 WD |
421 | |
422 | /* | |
423 | * BR2/3 and OR2/3 (SDRAM) | |
424 | * | |
425 | */ | |
426 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
427 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
c178d3da | 428 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
d4ca31c4 WD |
429 | |
430 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 431 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
d4ca31c4 | 432 | |
6d0f6bcf JCPV |
433 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
434 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 435 | |
c178d3da | 436 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf JCPV |
437 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
438 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 439 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
441 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
442 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
443 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
d4ca31c4 WD |
444 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
445 | #endif /* CONFIG_CAN_DRIVER */ | |
446 | ||
c178d3da | 447 | /* |
c178d3da WD |
448 | * 4096 Rows from SDRAM example configuration |
449 | * 1000 factor s -> ms | |
450 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
451 | * 4 Number of refresh cycles per period | |
452 | * 64 Refresh cycle in ms per number of rows | |
453 | */ | |
6d0f6bcf | 454 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
c178d3da | 455 | |
d4ca31c4 | 456 | /* |
d43e489b MK |
457 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
458 | * | |
459 | * CPUclock(MHz) * 31.2 | |
6d0f6bcf | 460 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
d43e489b MK |
461 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
462 | * | |
6d0f6bcf JCPV |
463 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
464 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
465 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
466 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
d43e489b MK |
467 | * |
468 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
469 | * be met also in the default configuration, i.e. if environment variable | |
470 | * 'cpuclk' is not set. | |
d4ca31c4 | 471 | */ |
6d0f6bcf | 472 | #define CONFIG_SYS_MAMR_PTA 97 |
d4ca31c4 WD |
473 | |
474 | /* | |
d43e489b | 475 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
d4ca31c4 | 476 | */ |
d43e489b | 477 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 478 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
d43e489b | 479 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 480 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
d4ca31c4 WD |
481 | |
482 | /* | |
483 | * MAMR settings for SDRAM | |
484 | */ | |
485 | ||
486 | /* 8 column SDRAM */ | |
6d0f6bcf | 487 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
488 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
489 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
490 | /* 9 column SDRAM */ | |
6d0f6bcf | 491 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
492 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
493 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
c178d3da | 494 | /* 10 column SDRAM */ |
6d0f6bcf | 495 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
c178d3da WD |
496 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
497 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
d4ca31c4 WD |
498 | |
499 | /* | |
500 | * Internal Definitions | |
501 | * | |
502 | * Boot Flags | |
503 | */ | |
c178d3da | 504 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
d4ca31c4 WD |
505 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
506 | ||
507 | #define CONFIG_SCC1_ENET | |
508 | #define CONFIG_FEC_ENET | |
509 | #define CONFIG_ETHPRIME "SCC ETHERNET" | |
510 | ||
511 | #endif /* __CONFIG_H */ |