]>
Commit | Line | Data |
---|---|---|
1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
1cb8e980 WD |
32 | /* |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ | |
37 | #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ | |
38 | #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ | |
39 | ||
40 | /* input clock of PLL */ | |
41 | #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ | |
42 | ||
43 | #define USE_920T_MMU 1 | |
44 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
45 | ||
53677ef1 | 46 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
1cb8e980 WD |
47 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
48 | #define CONFIG_INITRD_TAG 1 | |
49 | ||
a5562901 | 50 | |
a1aa0bb5 JL |
51 | /* |
52 | * BOOTP options | |
53 | */ | |
54 | #define CONFIG_BOOTP_BOOTFILESIZE | |
55 | #define CONFIG_BOOTP_BOOTPATH | |
56 | #define CONFIG_BOOTP_GATEWAY | |
57 | #define CONFIG_BOOTP_HOSTNAME | |
58 | ||
59 | ||
a5562901 JL |
60 | /* |
61 | * Command line configuration. | |
62 | */ | |
63 | #include <config_cmd_default.h> | |
64 | ||
65 | #define CONFIG_CMD_CACHE | |
66 | #define CONFIG_CMD_EEPROM | |
67 | #define CONFIG_CMD_I2C | |
68 | #define CONFIG_CMD_USB | |
69 | #define CONFIG_CMD_REGINFO | |
70 | #define CONFIG_CMD_FAT | |
71 | #define CONFIG_CMD_DATE | |
72 | #define CONFIG_CMD_ELF | |
73 | #define CONFIG_CMD_DHCP | |
74 | #define CONFIG_CMD_PING | |
75 | #define CONFIG_CMD_BSP | |
76 | ||
1cb8e980 | 77 | |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_HUSH_PARSER |
79 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1cb8e980 WD |
80 | /*********************************************************** |
81 | * I2C stuff: | |
82 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
83 | * address 0x50 with 16bit addressing | |
84 | ***********************************************************/ | |
85 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
87 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ | |
1cb8e980 | 88 | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
90 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
bb1f8b4f | 91 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
92 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ |
93 | #define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ | |
1cb8e980 | 94 | |
6d0f6bcf JCPV |
95 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
96 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ | |
97 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
1cb8e980 WD |
98 | |
99 | /* | |
100 | * Size of malloc() pool | |
101 | */ | |
0e8d1586 | 102 | /*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ |
6d0f6bcf | 103 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
1cb8e980 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
106 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ | |
1cb8e980 WD |
107 | |
108 | /* | |
109 | * Hardware drivers | |
110 | */ | |
111 | #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ | |
112 | #define CS8900_BASE 0x20000300 | |
53677ef1 | 113 | #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ |
1cb8e980 WD |
114 | |
115 | #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ | |
116 | ||
117 | /* | |
118 | * select serial console configuration | |
119 | */ | |
300f99f4 | 120 | #define CONFIG_S3C24X0_SERIAL |
1cb8e980 WD |
121 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
122 | ||
48b42616 WD |
123 | /************************************************************ |
124 | * USB support | |
125 | ************************************************************/ | |
a2663ea4 WD |
126 | #define CONFIG_USB_OHCI 1 |
127 | #define CONFIG_USB_KEYBOARD 1 | |
128 | #define CONFIG_USB_STORAGE 1 | |
129 | #define CONFIG_DOS_PARTITION 1 | |
48b42616 WD |
130 | |
131 | /* Enable needed helper functions */ | |
52cb4d4f | 132 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 WD |
133 | |
134 | /************************************************************ | |
135 | * RTC | |
136 | ************************************************************/ | |
137 | #define CONFIG_RTC_S3C24X0 1 | |
138 | ||
139 | ||
1cb8e980 WD |
140 | /* allow to overwrite serial and ethaddr */ |
141 | #define CONFIG_ENV_OVERWRITE | |
142 | ||
143 | #define CONFIG_BAUDRATE 9600 | |
144 | ||
a2663ea4 WD |
145 | #define CONFIG_BOOTDELAY 5 |
146 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ | |
2893ecbf | 147 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
53677ef1 | 148 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
a2663ea4 | 149 | |
1cb8e980 WD |
150 | #define CONFIG_NETMASK 255.255.255.0 |
151 | #define CONFIG_IPADDR 10.0.0.110 | |
152 | #define CONFIG_SERVERIP 10.0.0.1 | |
153 | ||
a5562901 | 154 | #if defined(CONFIG_CMD_KGDB) |
1cb8e980 WD |
155 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
156 | /* what's this ? it's not used anywhere */ | |
157 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
158 | #endif | |
159 | ||
160 | /* | |
161 | * Miscellaneous configurable options | |
162 | */ | |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
164 | #define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ | |
165 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
166 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
167 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
1cb8e980 | 169 | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
171 | #define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ | |
531716e1 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_ALT_MEMTEST |
174 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ | |
1cb8e980 | 175 | |
1cb8e980 | 176 | /* we configure PWM Timer 4 to 1us ~ 1MHz */ |
6d0f6bcf JCPV |
177 | /*#define CONFIG_SYS_HZ 1000000 */ |
178 | #define CONFIG_SYS_HZ 1562500 | |
1cb8e980 WD |
179 | |
180 | /* valid baudrates */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
1cb8e980 | 182 | |
a2663ea4 WD |
183 | /* support BZIP2 compression */ |
184 | #define CONFIG_BZIP2 1 | |
185 | ||
48b42616 WD |
186 | /************************************************************ |
187 | * Ident | |
188 | ************************************************************/ | |
189 | /*#define VERSION_TAG "released"*/ | |
190 | #define VERSION_TAG "unstable" | |
191 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG | |
192 | ||
1cb8e980 WD |
193 | /*----------------------------------------------------------------------- |
194 | * Stack sizes | |
195 | * | |
196 | * The stack sizes are set up in start.S using the settings below | |
197 | */ | |
198 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
199 | #ifdef CONFIG_USE_IRQ | |
200 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
201 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
202 | #endif | |
203 | ||
204 | /*----------------------------------------------------------------------- | |
205 | * Physical Memory Map | |
206 | */ | |
207 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
208 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
1cb8e980 WD |
209 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
210 | ||
6d0f6bcf | 211 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 WD |
212 | |
213 | /*----------------------------------------------------------------------- | |
214 | * FLASH and environment organization | |
215 | */ | |
216 | ||
217 | #define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ | |
218 | #if 0 | |
219 | #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ | |
220 | #endif | |
221 | ||
6d0f6bcf | 222 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
1cb8e980 WD |
223 | #ifdef CONFIG_AMD_LV800 |
224 | #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ |
226 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ | |
1cb8e980 WD |
227 | #endif |
228 | #ifdef CONFIG_AMD_LV400 | |
229 | #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ |
231 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ | |
1cb8e980 WD |
232 | #endif |
233 | ||
234 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
236 | #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
1cb8e980 WD |
237 | |
238 | #if 0 | |
5a1aceb0 | 239 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 240 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
1cb8e980 WD |
241 | #endif |
242 | ||
48b42616 | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
245 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
48b42616 WD |
246 | |
247 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 | |
248 | ||
249 | /*----------------------------------------------------------------------- | |
250 | * NAND flash settings | |
251 | */ | |
a5562901 | 252 | #if defined(CONFIG_CMD_NAND) |
48b42616 | 253 | |
cc4a0cee | 254 | #define CONFIG_NAND_LEGACY |
6d0f6bcf | 255 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
48b42616 WD |
256 | #define SECTORSIZE 512 |
257 | ||
258 | #define ADDR_COLUMN 1 | |
259 | #define ADDR_PAGE 2 | |
260 | #define ADDR_COLUMN_PAGE 3 | |
261 | ||
53677ef1 | 262 | #define NAND_ChipID_UNKNOWN 0x00 |
48b42616 | 263 | #define NAND_MAX_FLOORS 1 |
48b42616 WD |
264 | |
265 | #define NAND_WAIT_READY(nand) NF_WaitRB() | |
266 | ||
267 | #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) | |
268 | #define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) | |
269 | ||
270 | ||
271 | #define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) | |
272 | #define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) | |
273 | #define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) | |
274 | #define WRITE_NAND(d, adr) NF_Write(d) | |
275 | #define READ_NAND(adr) NF_Read() | |
276 | /* the following functions are NOP's because S3C24X0 handles this in hardware */ | |
277 | #define NAND_CTL_CLRALE(nandptr) | |
278 | #define NAND_CTL_SETALE(nandptr) | |
279 | #define NAND_CTL_CLRCLE(nandptr) | |
280 | #define NAND_CTL_SETCLE(nandptr) | |
281 | ||
282 | #define CONFIG_MTD_NAND_VERIFY_WRITE 1 | |
283 | #define CONFIG_MTD_NAND_ECC_JFFS2 1 | |
284 | ||
a5562901 | 285 | #endif |
1cb8e980 WD |
286 | |
287 | #endif /* __CONFIG_H */ |