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36b4e2dd | 1 | /* |
9fc376be | 2 | * (C) Copyright 2011 CompuLab, Ltd. |
36b4e2dd | 3 | * Mike Rapoport <mike@compulab.co.il> |
dccd9a0b | 4 | * Igor Grinberg <grinberg@compulab.co.il> |
36b4e2dd MR |
5 | * |
6 | * Based on omap3_beagle.h | |
7 | * (C) Copyright 2006-2008 | |
8 | * Texas Instruments. | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
b65a77a8 | 12 | * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards |
36b4e2dd | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
36b4e2dd MR |
15 | */ |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
3709844f AA |
20 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
21 | ||
36b4e2dd MR |
22 | /* |
23 | * High Level Configuration Options | |
24 | */ | |
9fc376be | 25 | #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ |
36b4e2dd | 26 | |
36b4e2dd | 27 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
987ec585 | 28 | #include <asm/arch/omap.h> |
36b4e2dd | 29 | |
36b4e2dd MR |
30 | /* Clock Defines */ |
31 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
32 | #define V_SCLK (V_OSCK >> 1) | |
33 | ||
36b4e2dd MR |
34 | #define CONFIG_MISC_INIT_R |
35 | ||
9fc376be NK |
36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
37 | #define CONFIG_SETUP_MEMORY_TAGS | |
38 | #define CONFIG_INITRD_TAG | |
39 | #define CONFIG_REVISION_TAG | |
82309250 | 40 | #define CONFIG_SERIAL_TAG |
36b4e2dd MR |
41 | |
42 | /* | |
43 | * Size of malloc() pool | |
44 | */ | |
390cdcda | 45 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
9fc376be NK |
46 | /* Sector */ |
47 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
36b4e2dd MR |
48 | |
49 | /* | |
50 | * Hardware drivers | |
51 | */ | |
52 | ||
53 | /* | |
54 | * NS16550 Configuration | |
55 | */ | |
56 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
57 | ||
36b4e2dd MR |
58 | #define CONFIG_SYS_NS16550_SERIAL |
59 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
60 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
61 | ||
62 | /* | |
63 | * select serial console configuration | |
64 | */ | |
65 | #define CONFIG_CONS_INDEX 3 | |
66 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
67 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
68 | ||
69 | /* allow to overwrite serial and ethaddr */ | |
70 | #define CONFIG_ENV_OVERWRITE | |
36b4e2dd MR |
71 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
72 | 115200} | |
9fc376be | 73 | |
36b4e2dd | 74 | /* USB */ |
9fc376be | 75 | #define CONFIG_USB_OMAP3 |
95de1e2f | 76 | #define CONFIG_USB_MUSB_UDC |
9fc376be | 77 | #define CONFIG_TWL4030_USB |
36b4e2dd MR |
78 | |
79 | /* USB device configuration */ | |
9fc376be NK |
80 | #define CONFIG_USB_DEVICE |
81 | #define CONFIG_USB_TTY | |
36b4e2dd MR |
82 | |
83 | /* commands to include */ | |
36b4e2dd | 84 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
0b800a6b | 85 | #define CONFIG_MTD_PARTITIONS |
36b4e2dd | 86 | |
6789e84e HS |
87 | #define CONFIG_SYS_I2C |
88 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
89 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
82309250 NK |
90 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
91 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
52658fda | 92 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
79874ae9 | 93 | #define CONFIG_I2C_MULTI_BUS |
36b4e2dd MR |
94 | |
95 | /* | |
96 | * TWL4030 | |
97 | */ | |
9fc376be | 98 | #define CONFIG_TWL4030_LED |
36b4e2dd MR |
99 | |
100 | /* | |
101 | * Board NAND Info. | |
102 | */ | |
36b4e2dd MR |
103 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
104 | /* to access nand */ | |
105 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
106 | /* to access nand at */ | |
107 | /* CS0 */ | |
36b4e2dd MR |
108 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
109 | /* devices */ | |
7bb6e29b | 110 | |
36b4e2dd | 111 | /* Environment information */ |
36b4e2dd MR |
112 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
113 | "loadaddr=0x82000000\0" \ | |
114 | "usbtty=cdc_acm\0" \ | |
f3ef3609 | 115 | "console=ttyO2,115200n8\0" \ |
36b4e2dd MR |
116 | "mpurate=500\0" \ |
117 | "vram=12M\0" \ | |
118 | "dvimode=1024x768MR-16@60\0" \ | |
119 | "defaultdisplay=dvi\0" \ | |
120 | "mmcdev=0\0" \ | |
121 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
0b800a6b | 122 | "mmcrootfstype=ext4 rootwait\0" \ |
36b4e2dd | 123 | "nandroot=/dev/mtdblock4 rw\0" \ |
0b800a6b | 124 | "nandrootfstype=ubifs\0" \ |
36b4e2dd MR |
125 | "mmcargs=setenv bootargs console=${console} " \ |
126 | "mpurate=${mpurate} " \ | |
127 | "vram=${vram} " \ | |
128 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
129 | "omapdss.def_disp=${defaultdisplay} " \ |
130 | "root=${mmcroot} " \ | |
131 | "rootfstype=${mmcrootfstype}\0" \ | |
132 | "nandargs=setenv bootargs console=${console} " \ | |
133 | "mpurate=${mpurate} " \ | |
134 | "vram=${vram} " \ | |
135 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
136 | "omapdss.def_disp=${defaultdisplay} " \ |
137 | "root=${nandroot} " \ | |
138 | "rootfstype=${nandrootfstype}\0" \ | |
139 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
140 | "bootscript=echo Running bootscript from mmc ...; " \ | |
141 | "source ${loadaddr}\0" \ | |
142 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
143 | "mmcboot=echo Booting from mmc ...; " \ | |
144 | "run mmcargs; " \ | |
145 | "bootm ${loadaddr}\0" \ | |
146 | "nandboot=echo Booting from nand ...; " \ | |
147 | "run nandargs; " \ | |
0b800a6b | 148 | "nand read ${loadaddr} 2a0000 400000; " \ |
36b4e2dd MR |
149 | "bootm ${loadaddr}\0" \ |
150 | ||
151 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 152 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
36b4e2dd MR |
153 | "if run loadbootscript; then " \ |
154 | "run bootscript; " \ | |
155 | "else " \ | |
156 | "if run loaduimage; then " \ | |
157 | "run mmcboot; " \ | |
158 | "else run nandboot; " \ | |
159 | "fi; " \ | |
160 | "fi; " \ | |
161 | "else run nandboot; fi" | |
162 | ||
36b4e2dd MR |
163 | /* |
164 | * Miscellaneous configurable options | |
165 | */ | |
41d7e702 IG |
166 | #define CONFIG_AUTO_COMPLETE |
167 | #define CONFIG_CMDLINE_EDITING | |
168 | #define CONFIG_TIMESTAMP | |
9fc376be | 169 | #define CONFIG_SYS_AUTOLOAD "no" |
36b4e2dd | 170 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
36b4e2dd MR |
171 | |
172 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
173 | /* works on */ | |
174 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
175 | 0x01F00000) /* 31MB */ | |
176 | ||
177 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
178 | /* load address */ | |
179 | ||
180 | /* | |
181 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
182 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
183 | * This rate is divided by a local divisor. | |
184 | */ | |
185 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
186 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
36b4e2dd | 187 | |
36b4e2dd MR |
188 | /*----------------------------------------------------------------------- |
189 | * Physical Memory Map | |
190 | */ | |
191 | #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ | |
192 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
36b4e2dd | 193 | |
36b4e2dd MR |
194 | /*----------------------------------------------------------------------- |
195 | * FLASH and environment organization | |
196 | */ | |
197 | ||
198 | /* **** PISMO SUPPORT *** */ | |
36b4e2dd MR |
199 | /* Monitor at start of flash */ |
200 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
3530a35d | 201 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
36b4e2dd | 202 | |
7672d9d5 AF |
203 | #define CONFIG_ENV_OFFSET 0x260000 |
204 | #define CONFIG_ENV_ADDR 0x260000 | |
36b4e2dd | 205 | |
36b4e2dd MR |
206 | /* additions for new relocation code, must be added to all boards */ |
207 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
208 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
209 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
210 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
211 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
212 | GENERATED_GBL_DATA_SIZE) | |
213 | ||
2b8754b2 | 214 | /* Status LED */ |
ebc18afd | 215 | #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ |
2b8754b2 | 216 | |
60e6bdcc NK |
217 | #define CONFIG_SPLASHIMAGE_GUARD |
218 | ||
7878ca51 | 219 | /* Display Configuration */ |
7878ca51 NK |
220 | #define CONFIG_VIDEO_OMAP3 |
221 | #define LCD_BPP LCD_COLOR16 | |
222 | ||
f35034fe | 223 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 224 | #define CONFIG_SPLASH_SOURCE |
f35034fe | 225 | #define CONFIG_BMP_16BPP |
63c4f17b NK |
226 | #define CONFIG_SCF0403_LCD |
227 | ||
3e51b7c8 | 228 | /* Defines for SPL */ |
3e51b7c8 | 229 | #define CONFIG_SPL_FRAMEWORK |
3e51b7c8 | 230 | |
e2ccdf89 | 231 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 232 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
3e51b7c8 | 233 | |
3e51b7c8 SR |
234 | #define CONFIG_SPL_NAND_BASE |
235 | #define CONFIG_SPL_NAND_DRIVERS | |
236 | #define CONFIG_SPL_NAND_ECC | |
3e51b7c8 SR |
237 | |
238 | /* NAND boot config */ | |
239 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
240 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
241 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
242 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
243 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
244 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
245 | /* | |
246 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
247 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
248 | */ | |
249 | #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ | |
250 | 10, 11, 12 } | |
251 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
252 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
253 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
254 | ||
255 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
256 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
257 | ||
258 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
259 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
260 | CONFIG_SPL_TEXT_BASE) | |
3e51b7c8 SR |
261 | |
262 | /* | |
263 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
264 | * older x-loader implementations. And move the BSS area so that it | |
265 | * doesn't overlap with TEXT_BASE. | |
266 | */ | |
267 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
268 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
269 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
270 | ||
271 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
272 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
273 | ||
bcb447e1 | 274 | /* EEPROM */ |
bcb447e1 NK |
275 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
276 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
277 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
278 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
279 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
280 | ||
36b4e2dd | 281 | #endif /* __CONFIG_H */ |